--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.1\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Ensure stdint is only used by the compiler, and not the assembler. */\r
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)\r
+ #include <stdint.h>\r
+ extern uint32_t SystemD2Clock;\r
+ void vGenerateM4ToM7Interrupt( void * xUpdatedMessageBuffer );\r
+#endif\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemD2Clock )\r
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
+#define configMAX_PRIORITIES ( 7 )\r
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 0\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 0\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 10\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xQueueGetMutexHolder 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_eTaskGetState 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#ifndef __IASMARM__\r
+ void vAssertCalled( const char *pcFile, const uint32_t ulLine );\r
+#endif /* __IASMARM__ */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { vAssertCalled( __FILE__, __LINE__ ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+ standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* Override the default implementation of sbRECEIVE_COMPLETED so the macro\r
+creates an interrupt in the M7 core. See the comments at the top of main.c. */\r
+#define sbRECEIVE_COMPLETED( pxStreamBuffer ) vGenerateM4ToM7Interrupt( pxStreamBuffer )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file FreeRTOS/FreeRTOS_HwSemaphoreCoreSync/CM4/Inc/stm32h7xx_hal_conf.h\r
+ * @author MCD Application Team\r
+ * @brief HAL configuration file for Cortex-M4.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H7xx_HAL_CONF_H\r
+#define __STM32H7xx_HAL_CONF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* ########################## Module Selection ############################## */\r
+/**\r
+ * @brief This is the list of modules to be used in the HAL driver\r
+ */\r
+#define HAL_MODULE_ENABLED\r
+#define HAL_ADC_MODULE_ENABLED \r
+/* #define HAL_CEC_MODULE_ENABLED */\r
+/* #define HAL_COMP_MODULE_ENABLED */\r
+#define HAL_CORTEX_MODULE_ENABLED\r
+/* #define HAL_CRC_MODULE_ENABLED */\r
+/* #define HAL_CRYP_MODULE_ENABLED */\r
+/* #define HAL_DAC_MODULE_ENABLED */\r
+/* #define HAL_DCMI_MODULE_ENABLED */\r
+/* #define HAL_DFSDM_MODULE_ENABLED */\r
+#define HAL_DMA_MODULE_ENABLED\r
+/* #define HAL_DMA2D_MODULE_ENABLED */\r
+/* #define HAL_ETH_MODULE_ENABLED */\r
+/* #define HAL_EXTI_MODULE_ENABLED */\r
+/* #define HAL_FDCAN_MODULE_ENABLED */\r
+#define HAL_FLASH_MODULE_ENABLED \r
+#define HAL_GPIO_MODULE_ENABLED\r
+/* #define HAL_HASH_MODULE_ENABLED */\r
+/* #define HAL_HCD_MODULE_ENABLED */\r
+/* #define HAL_HRTIM_MODULE_ENABLED */\r
+#define HAL_HSEM_MODULE_ENABLED\r
+#define HAL_I2C_MODULE_ENABLED\r
+/* #define HAL_I2S_MODULE_ENABLED */\r
+/* #define HAL_IRDA_MODULE_ENABLED */\r
+/* #define HAL_IWDG_MODULE_ENABLED */\r
+/* #define HAL_JPEG_MODULE_ENABLED */\r
+/* #define HAL_LPTIM_MODULE_ENABLED */\r
+/* #define HAL_LTDC_MODULE_ENABLED */\r
+/* #define HAL_MDIOS_MODULE_ENABLED */\r
+/* #define HAL_MDMA_MODULE_ENABLED */\r
+/* #define HAL_MMC_MODULE_ENABLED */\r
+/* #define HAL_NAND_MODULE_ENABLED */\r
+/* #define HAL_NOR_MODULE_ENABLED */\r
+/* #define HAL_OPAMP_MODULE_ENABLED */\r
+/* #define HAL_PCD_MODULE_ENABLED */\r
+#define HAL_PWR_MODULE_ENABLED\r
+/* #define HAL_QSPI_MODULE_ENABLED */\r
+/* #define HAL_RAMECC_MODULE_ENABLED */\r
+#define HAL_RCC_MODULE_ENABLED\r
+/* #define HAL_RNG_MODULE_ENABLED */\r
+/* #define HAL_RTC_MODULE_ENABLED */\r
+/* #define HAL_SAI_MODULE_ENABLED */\r
+/* #define HAL_SD_MODULE_ENABLED */\r
+/* #define HAL_SDRAM_MODULE_ENABLED */\r
+/* #define HAL_SMARTCARD_MODULE_ENABLED */\r
+/* #define HAL_SMBUS_MODULE_ENABLED */\r
+/* #define HAL_SPDIFRX_MODULE_ENABLED */\r
+/* #define HAL_SPI_MODULE_ENABLED */\r
+/* #define HAL_SRAM_MODULE_ENABLED */\r
+/* #define HAL_SWPMI_MODULE_ENABLED */\r
+/* #define HAL_TIM_MODULE_ENABLED */\r
+#define HAL_UART_MODULE_ENABLED\r
+/* #define HAL_USART_MODULE_ENABLED */\r
+/* #define HAL_WWDG_MODULE_ENABLED */\r
+\r
+/* ########################## Oscillator Values adaptation ####################*/\r
+/**\r
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSE is used as system clock source, directly or through the PLL).\r
+ */\r
+#if !defined (HSE_VALUE)\r
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+ * @brief Internal oscillator (CSI) default value.\r
+ * This value is the default CSI value after Reset.\r
+ */\r
+#if !defined (CSI_VALUE)\r
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* CSI_VALUE */\r
+\r
+/**\r
+ * @brief Internal High Speed oscillator (HSI) value.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSI is used as system clock source, directly or through the PLL).\r
+ */\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @brief External Low Speed oscillator (LSE) value.\r
+ * This value is used by the UART, RTC HAL module to compute the system frequency\r
+ */\r
+#if !defined (LSE_VALUE)\r
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/\r
+#endif /* LSE_VALUE */\r
+\r
+\r
+#if !defined (LSE_STARTUP_TIMEOUT)\r
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */\r
+#endif /* LSE_STARTUP_TIMEOUT */\r
+\r
+#if !defined (LSI_VALUE)\r
+ #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/\r
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature.*/\r
+\r
+/**\r
+ * @brief External clock source for I2S peripheral\r
+ * This value is used by the I2S HAL module to compute the I2S clock source\r
+ * frequency, this source is inserted directly through I2S_CKIN pad.\r
+ */\r
+#if !defined (EXTERNAL_CLOCK_VALUE)\r
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/\r
+#endif /* EXTERNAL_CLOCK_VALUE */\r
+\r
+/* Tip: To avoid modifying this file each time you need to use different HSE,\r
+ === you can define the HSE value in your toolchain compiler preprocessor. */\r
+\r
+/* ########################### System Configuration ######################### */\r
+/**\r
+ * @brief This is the HAL system configuration section\r
+ */\r
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */\r
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */\r
+#define USE_RTOS 0\r
+#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */\r
+\r
+/* ########################### Ethernet Configuration ######################### */\r
+#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */\r
+#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */\r
+\r
+#define ETH_MAC_ADDR0 ((uint8_t)0x02)\r
+#define ETH_MAC_ADDR1 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR2 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR3 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR4 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR5 ((uint8_t)0x00)\r
+\r
+/* ########################## Assert Selection ############################## */\r
+/**\r
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the\r
+ * HAL drivers code\r
+ */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/**\r
+ * @brief Include module's header file\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_rcc.h"\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_gpio.h"\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dma.h"\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_MDMA_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_mdma.h"\r
+#endif /* HAL_MDMA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hash.h"\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dcmi.h"\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dma2d.h"\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DFSDM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dfsdm.h"\r
+#endif /* HAL_DFSDM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_eth.h"\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_EXTI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_exti.h"\r
+#endif /* HAL_EXTI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_cortex.h"\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_adc.h"\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FDCAN_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_fdcan.h"\r
+#endif /* HAL_FDCAN_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CEC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_cec.h"\r
+#endif /* HAL_CEC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_COMP_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_comp.h"\r
+#endif /* HAL_COMP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_crc.h"\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_cryp.h"\r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dac.h"\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_flash.h"\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HRTIM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hrtim.h"\r
+#endif /* HAL_HRTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HSEM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hsem.h"\r
+#endif /* HAL_HSEM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sram.h"\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_nor.h"\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_nand.h"\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_i2c.h"\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_i2s.h"\r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_iwdg.h"\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_JPEG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_jpeg.h"\r
+#endif /* HAL_JPEG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_MDIOS_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_mdios.h"\r
+#endif /* HAL_MDIOS_MODULE_ENABLED */\r
+\r
+\r
+#ifdef HAL_MMC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_mmc.h"\r
+#endif /* HAL_MMC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+#include "stm32h7xx_hal_lptim.h"\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+#include "stm32h7xx_hal_ltdc.h"\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_OPAMP_MODULE_ENABLED\r
+#include "stm32h7xx_hal_opamp.h"\r
+#endif /* HAL_OPAMP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_pwr.h"\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_qspi.h"\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RAMECC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_ramecc.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_rng.h"\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_rtc.h"\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sai.h"\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sd.h"\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SDRAM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sdram.h"\r
+#endif /* HAL_SDRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_spi.h"\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPDIFRX_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_spdifrx.h"\r
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SWPMI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_swpmi.h"\r
+#endif /* HAL_SWPMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_tim.h"\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_uart.h"\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_usart.h"\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_irda.h"\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_smartcard.h"\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMBUS_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_smbus.h"\r
+#endif /* HAL_SMBUS_MODULE_ENABLED */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_wwdg.h"\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_pcd.h"\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hcd.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed.\r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t *file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0U)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H7xx_HAL_CONF_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM4/Inc/stm32h7xx_it.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the headers of the interrupt handlers for Cortex-M4.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H7xx_IT_H\r
+#define __STM32H7xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+void EXTI0_IRQHandler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H7xx_IT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * See https://www.freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html for usage\r
+ * instructions (TBD, not available at the time of writing).\r
+ *\r
+ * Behavior\r
+ * --------\r
+ *\r
+ * This example stress tests a simple Asymmetric Multi Processing (AMP) core to\r
+ * core communication mechanism implemented using FreeRTOS message buffers:\r
+ * https://www.freertos.org/RTOS-stream-message-buffers.html Message buffers\r
+ * are used to pass an ASCII representation of an incrementing number (so "0",\r
+ * followed by "1", followed by "2", etc.) from a single 'sending' task that\r
+ * runs on the Arm Cortex-M7 core (the M7 core) to two "receiving" tasks\r
+ * running on the Arm Cortex-M4 core (the M4 core). There are two data message\r
+ * buffers, one for each receiving task. To distinguish between the receiving\r
+ * tasks one is assigned the task number 0, and the other task number 1.\r
+ *\r
+ * The M7 task sits in a loop sending the ascii strings to each M4 task. If a\r
+ * receiving task receives the next expected value in the sequence it prints its\r
+ * task number to the UART. If a receiving task receives anything else, or its\r
+ * attempt to receive data times out, then it hits an assert() that prints an\r
+ * error message to the UART before stopping all further processing on the M4\r
+ * core. If the example is running correctly you will see lots of "0"s (from\r
+ * the receiving task assigned task number 0) and "1"s (from the receiving task\r
+ * assigned task number 1) streaming from the UART. The time taken to output\r
+ * characters from the UART is the only thing throttling the speed of the core\r
+ * to core communication as it causes the message buffers to become full - which\r
+ * would probably happen anyway as the M7 core is executing at twice the\r
+ * frequency of the M4 core.\r
+ *\r
+ *\r
+ * Implementation of sbSEND_COMPLETED()\r
+ * ------------------------------------\r
+ *\r
+ * sbSEND_COMPLETED is a macro called by FreeRTOS after data has been sent to a\r
+ * message buffer in case there was a task blocked on the message buffer waiting\r
+ * for data to become available - in which case the waiting task would be\r
+ * unblocked: https://www.freertos.org/RTOS-message-buffer-example.html\r
+ * However, the default sbSEND_COMPLETED implementation assumes the sending task\r
+ * (or interrupt) and the receiving task are under the control of the same\r
+ * instance of the FreeRTOS kernel and run on the same MCU core. In this AMP\r
+ * example the sending task and the receiving tasks are under the control of two\r
+ * different instances of the FreeRTOS kernel, and run on different MCU cores,\r
+ * so the default sbSEND_COMPLETED implementation won't work (each FreeRTOS\r
+ * kernel instance only knowns about the tasks under its control). AMP\r
+ * scenarios therefore require the sbSEND_COMPLETED macro (and potentially the\r
+ * sbRECEIVE_COMPLETED macro, see below) to be overridden, which is done by\r
+ * simply providing your own implementation in the project's FreeRTOSConfig.h\r
+ * file. Note this example has a FreeRTOSConfig.h file used by the application\r
+ * that runs on the M7 core and a separate FreeRTOSConfig.h file used by the\r
+ * application that runs on the M4 core. The implementation of sbSEND_COMPLETED\r
+ * used by the M7 core simply triggers an interrupt in the M4 core. The\r
+ * interrupt's handler (the ISR that was triggered by the M7 core but executes\r
+ * on the M4 core) must then do the job that would otherwise be done by the\r
+ * default implementation of sbSEND_COMPLETE - namely unblock a task if the task\r
+ * was waiting to receive data from the message buffer that now contains data.\r
+ * There are two data message buffers though, so first ISR must determine which\r
+ * of the two contains data.\r
+ *\r
+ * This demo only has two data message buffers, so it would be reasonable to\r
+ * have the ISR simply query both to see which contained data, but that solution\r
+ * would not scale if there are many message buffers, or if the number of\r
+ * message buffers was unknown. Therefore, to demonstrate a more scalable\r
+ * solution, this example introduced a third message buffer - a 'control'\r
+ * message buffer as opposed to a 'data' message buffer. After the task on the\r
+ * M7 core writes to a data message buffer it writes the handle of the message\r
+ * buffer that contains data to the control message buffer. The ISR running on\r
+ * the M4 core then reads from the control message buffer to know which data\r
+ * message buffer contains data.\r
+ *\r
+ * The above described scenario contains many implementation decisions.\r
+ * Alternative methods of enabling the M4 core to know data message buffer\r
+ * contains data include:\r
+ *\r
+ * 1) Using a different interrupt for each data message buffer.\r
+ * 2) Passing all data from the M7 core to the M4 core through a single message\r
+ * buffer, along with additional data that tells the ISR running on the M4\r
+ * core which task to forward the data to.\r
+ *\r
+ *\r
+ * Implementation of sbRECEIVE_COMPLETED()\r
+ * ---------------------------------------\r
+ *\r
+ * sbRECEIVE_COMPLETED is the complement of sbSEND_COMPLETED. It is a macro\r
+ * called by FreeRTOS after data has been read from a message buffer in case\r
+ * there was a task blocked on the message buffer waiting for space to become\r
+ * available - in which case the waiting task would be unblocked so it can\r
+ * complete its write to the buffer.\r
+ *\r
+ * In this example the M7 task writes to the message buffers faster than the M4\r
+ * tasks read from them (in part because the M7 is running faster, and in part\r
+ * because the M4 cores write to the UART), so the buffers become full, and the\r
+ * M7 task enters the Blocked state to wait for space to become available. As\r
+ * with the sbSEND_COMPLETED macro, the default implementation of the\r
+ * sbRECEIVE_COMPLETED macro only works if the sender and receiver are under the\r
+ * control of the same instance of FreeRTOS and execute on the same core.\r
+ * Therefore, just as the application that executes on the M7 core overrides\r
+ * the default implementation of sbSEND_SOMPLETED(), the application that runs\r
+ * on the M4 core overrides the default implementation of sbRECEIVE_COMPLETED()\r
+ * to likewise generate an interrupt in the M7 core - so sbRECEIVE_COMPLETED()\r
+ * executes on the M4 core and generates an interrupt on the M7 core. To keep\r
+ * things simple the ISR that runs on the M7 core does not use a control\r
+ * message buffer to know which data message buffer contains space, and instead\r
+ * simply sends a notification to both data message buffers. Note however that\r
+ * this overly simplistic implementation is only acceptable because it is\r
+ * known that there is only one sending task, and that task cannot be blocked on\r
+ * both message buffers at the same time. Also, sending the notification to the\r
+ * data message buffer updates the receiving task's direct to task notification\r
+ * state: https://www.freertos.org/RTOS-task-notifications.html which is only ok\r
+ * because it is known the task is not using its notification state for any\r
+ * other purpose.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include "stdio.h"\r
+#include "string.h"\r
+\r
+/* STM32 includes. */\r
+#include "stm32h7xx_hal.h"\r
+#include "stm32h745i_discovery.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "message_buffer.h"\r
+\r
+/* Demo includes. */\r
+#include "MessageBufferLocations.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Seen as an infinite block by the ST HAL. */\r
+#define mainHAL_MAX_TIMEOUT 0xFFFFFFFFUL\r
+\r
+/* When the cores boot they very crudely wait for each other in a non chip\r
+specific way by waiting for the other core to start incrementing a shared\r
+variable within an array. mainINDEX_TO_TEST sets the index within the array to\r
+the variable this core tests to see if it is incrementing, and\r
+mainINDEX_TO_INCREMENT sets the index within the array to the variable this core\r
+increments to indicate to the other core that it is at the sync point. Note\r
+this is not a foolproof method and it is better to use a hardware specific\r
+solution, such as having one core boot the other core when it was ready, or\r
+using some kind of shared semaphore or interrupt. */\r
+#define mainINDEX_TO_TEST 1\r
+#define mainINDEX_TO_INCREMENT 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Implements the tasks that receive messages from the M7 core.\r
+ */\r
+static void prvM4CoreTasks( void *pvParameters );\r
+\r
+/*\r
+ * The interrupt triggered by the M7 core when there is data available in the\r
+ * message buffer used for core to core communication.\r
+ */\r
+void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin );\r
+\r
+/*\r
+ * Just waits to see a variable being incremented by the M7 core to know when\r
+ * the M7 has created the message buffers used for core to core communication.\r
+ */\r
+static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement );\r
+\r
+/*\r
+ * Configures the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Handle to the UART used to output strings. */\r
+static UART_HandleTypeDef xUARTHandle = { 0 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+static const uint8_t pucBootMessage[] = "\r\nM4 started and waiting for the M7 to run.\r\n";\r
+static const uint8_t pucCreatingTasksMessage[] = "M4 core proceeding to create demo tasks.\r\n";\r
+uint32_t x;\r
+\r
+ /*** See the comments at the top of this page ***/\r
+\r
+\r
+ /* Prep the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The M4 core task prints its status out at various places so you know what\r
+ it is doing when debugging the M7 core. This messages is just to indicate\r
+ it has booted and is about to wait for the M7 core. If the M7 is already\r
+ running then reset the hardware so both cores start at once. */\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucBootMessage, sizeof( pucBootMessage ), mainHAL_MAX_TIMEOUT );\r
+ prvWaitForOtherCoreToStart( mainINDEX_TO_TEST, mainINDEX_TO_INCREMENT );\r
+\r
+ /* By this point the M7 should have initialized the message buffers used to\r
+ send data from the M7 to the M4 core. The message buffers are statically\r
+ allocated at a known location so both cores know where they are. See\r
+ MessageBufferLocations.h. */\r
+ configASSERT( ( xControlMessageBuffer != NULL ) && ( xDataMessageBuffers[ 0 ] != NULL ) && ( xDataMessageBuffers[ 1 ] != NULL ) );\r
+\r
+ /* Everything seems as expected - print a message to say the M4 is about to\r
+ create the tasks that receive data from the M7 core. */\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucCreatingTasksMessage, sizeof( pucCreatingTasksMessage ), mainHAL_MAX_TIMEOUT );\r
+\r
+ for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )\r
+ {\r
+ /* Pass the loop counter into the created task using the task's\r
+ parameter. The task then uses the value as an index into the\r
+ xDataMessageBuffers arrays. */\r
+ xTaskCreate( prvM4CoreTasks, /* Function that implements the task. */\r
+ "AMPM4Core", /* Task name, for debugging only. */\r
+ configMINIMAL_STACK_SIZE, /* Size of stack to allocate for this task - in words. */\r
+ ( void * ) x, /* Task parameter. */\r
+ tskIDLE_PRIORITY + 1, /* Task priority. */\r
+ NULL ); /* Task handle. Not used in this case. */\r
+ }\r
+\r
+ /* Start scheduler */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will not get here if the scheduler starts successfully. If you do end up\r
+ here then there wasn't enough heap memory available to start either the idle\r
+ task or the timer/daemon task. https://www.freertos.org/a00111.html */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvM4CoreTasks( void *pvParameters )\r
+{\r
+static const uint8_t pucTaskStartedMessage[] = "M4 task started.\r\n";\r
+BaseType_t xTaskNumber;\r
+size_t xReceivedBytes;\r
+uint32_t ulNextValue = 0;\r
+char cExpectedString[ 15 ];\r
+char cReceivedString[ 15 ];\r
+char cMessage;\r
+const TickType_t xShortBlockTime = pdMS_TO_TICKS( 5 );\r
+\r
+ /* This task is created more than once so the task's parameter is used to\r
+ pass in a task number, which is then used as an index into the message\r
+ buffer array. */\r
+ xTaskNumber = ( BaseType_t ) pvParameters;\r
+ configASSERT( xTaskNumber < mbaNUMBER_OF_CORE_2_TASKS );\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Message transmitted to indicate the task has started. */\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucTaskStartedMessage, sizeof( pucTaskStartedMessage ), mainHAL_MAX_TIMEOUT );\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ /* The tasks print out a letter to indicate that the expected message was\r
+ received from the other core. */\r
+ if( xTaskNumber == 0 )\r
+ {\r
+ cMessage = '0';\r
+ }\r
+ else\r
+ {\r
+ cMessage = '1';\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* The M7 core creates and sends to this core an ascii string of an\r
+ incrementing number. Create the string that is expected to be received\r
+ this time round the loop. */\r
+ sprintf( cExpectedString, "%lu", ( unsigned long ) ulNextValue );\r
+\r
+ /* Wait to receive the next message from core 1. */\r
+ memset( cReceivedString, 0x00, sizeof( cReceivedString ) );\r
+ xReceivedBytes = xMessageBufferReceive( /* Handle of message buffer. */\r
+ xDataMessageBuffers[ xTaskNumber ],\r
+ /* Buffer into which received data is placed. */\r
+ cReceivedString,\r
+ /* Size of the receive buffer. */\r
+ sizeof( cReceivedString ),\r
+ /* Time to wait for data to arrive. */\r
+ xShortBlockTime );\r
+\r
+ /* Check the number of bytes received was as expected. */\r
+ configASSERT( xReceivedBytes == strlen( cExpectedString ) );\r
+\r
+ /* If the received string matches that expected then output the task\r
+ number to give visible indication that the task is still running. */\r
+ if( strcmp( cReceivedString, cExpectedString ) == 0 )\r
+ {\r
+ /* Also print out the task number to give a visual indication that\r
+ the M4 core is receiving the expected data. */\r
+ vTaskSuspendAll();\r
+ {\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) &cMessage, sizeof( cMessage ), mainHAL_MAX_TIMEOUT );\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+ /* Expect the next string in sequence the next time around. */\r
+ ulNextValue++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vGenerateM4ToM7Interrupt( void * xUpdatedMessageBuffer )\r
+{\r
+MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;\r
+const char cMessage[] = "\r\nvGenerateM4ToM7Interrupt\r\n";\r
+\r
+ /* Called by the implementation of sbRECEIVE_COMPLETED() in FreeRTOSConfig.h.\r
+ See the comments at the top of this file. Write the handle of the data\r
+ message buffer to which data was written to the control message buffer. */\r
+#if 0\r
+ if( xUpdatedBuffer != xControlMessageBuffer )\r
+ {\r
+ while( xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ) != sizeof( xUpdatedBuffer ) )\r
+ {\r
+ /* Nothing to do here. Note it is very bad to loop in an interrupt\r
+ service routine. If a loop is really required then defer the\r
+ routine to a task. */\r
+ }\r
+\r
+ /* Generate interrupt in the M4 core. */\r
+ HAL_EXTI_D1_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, DISABLE );\r
+ HAL_EXTI_D2_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, ENABLE );\r
+ HAL_EXTI_GenerateSWInterrupt( EXTI_LINE0 );\r
+ }\r
+#endif\r
+\r
+ /* Generate interrupt in the M7 core. */\r
+ HAL_EXTI_D2_EventInputConfig( EXTI_LINE1, EXTI_MODE_IT, DISABLE );\r
+ HAL_EXTI_D1_EventInputConfig( EXTI_LINE1, EXTI_MODE_IT, ENABLE );\r
+ HAL_EXTI_GenerateSWInterrupt( EXTI_LINE1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )\r
+{\r
+MessageBufferHandle_t xUpdatedMessageBuffer;\r
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Avoid compiler warnings about unused parameters. */\r
+ ( void ) GPIO_Pin;\r
+\r
+ /* Clear interrupt. */\r
+ HAL_EXTI_D2_ClearFlag( EXTI_LINE0 );\r
+\r
+ configASSERT( ( xControlMessageBuffer != NULL ) && ( xDataMessageBuffers[ 0 ] != NULL ) && ( xDataMessageBuffers[ 1 ] != NULL ) );\r
+\r
+ /* In this example there are mbaNUMBER_OF_CORE_2_TASKS receiving tasks that\r
+ run on the M4 core. It would be possible for the M7 core to use a single\r
+ message buffer to send to both tasks, but that would require additional data\r
+ to be sent to the message buffer - namely an identifier to indicate which\r
+ receiving task a message was intended for along with some arbitration in the\r
+ ISR. As an alternative, this example uses one message buffer per receiving\r
+ task and a control message buffer. The M7 core sends data to a receiving\r
+ task using that task's dedicated message buffer, then sends the handle of\r
+ the message buffer that it just sent data to to the control task. This\r
+ interrupt service routine receives the handle from the control task then\r
+ uses the handle to signal the message buffer that contains the data.\r
+\r
+ Receive the handle of the message buffer that contains data from the\r
+ control message buffer. */\r
+ while( xMessageBufferReceiveFromISR( xControlMessageBuffer,\r
+ &xUpdatedMessageBuffer,\r
+ sizeof( xUpdatedMessageBuffer ),\r
+ &xHigherPriorityTaskWoken ) == sizeof( xUpdatedMessageBuffer ) )\r
+ {\r
+ /* Call the API function that sends a notification to any task that is\r
+ blocked on the xUpdatedMessageBuffer message buffer waiting for data to\r
+ arrive. */\r
+ xMessageBufferSendCompletedFromISR( xUpdatedMessageBuffer, &xHigherPriorityTaskWoken );\r
+ }\r
+\r
+ /* Normal FreeRTOS "yield from interrupt" semantics, where\r
+ xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to\r
+ pdTRUE if the interrupt unblocks a task that has a priority above that of\r
+ the currently executing task. */\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement )\r
+{\r
+volatile uint32_t ulInitialCount = ulStartSyncCounters[ ulIndexToTest ];\r
+\r
+ /* When the cores boot they very crudely wait for each other in a non chip\r
+ specific way by waiting for the other core to start incrementing a shared\r
+ variable within an array. mainINDEX_TO_TEST sets the index within the array\r
+ to the variable this core tests to see if it is incrementing, and\r
+ mainINDEX_TO_INCREMENT sets the index within the array to the variable this\r
+ core increments to indicate to the other core that it is at the sync point.\r
+ Note this is not a foolproof method and it is better to use a hardware\r
+ specific solution, such as having one core boot the other core when it was\r
+ ready, or using some kind of shared semaphore or interrupt. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* Indicate to the M7 core that this core is at the synchronisation\r
+ point. */\r
+ ulStartSyncCounters[ ulIndexToIncrement ]++;\r
+\r
+ /* Has the counter incremented by the other core changed? */\r
+ if( ulStartSyncCounters[ ulIndexToTest ] != ulInitialCount )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* One more increment before exiting to avoid race. */\r
+ ulStartSyncCounters[ ulIndexToIncrement ]++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( const char *pcFile, const uint32_t ulLine )\r
+{\r
+char pcLine[ 10 ];\r
+const uint8_t pucM4AssertFile[] = "M4 Assert hit in file ";\r
+const uint8_t pucM4AssertLine[] = "on line number ";\r
+\r
+ /* Assert disables interrupts so no other code can run, prints out the\r
+ location of the offending assert(), then loops doing nothing waiting for\r
+ the user to inspect or reset. */\r
+ taskDISABLE_INTERRUPTS();\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucM4AssertFile, sizeof( pucM4AssertFile ), mainHAL_MAX_TIMEOUT );\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pcFile, strlen( pcFile ), mainHAL_MAX_TIMEOUT );\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucM4AssertLine, sizeof( pucM4AssertLine ), mainHAL_MAX_TIMEOUT );\r
+ sprintf( pcLine, "%u\r\n", ulLine );\r
+ HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pcLine, strlen( pcLine ), mainHAL_MAX_TIMEOUT );\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Prevent the HAL's initialisation of SysTick actually starting the systick\r
+ interrupt as the kernel has not started yet. */\r
+ taskDISABLE_INTERRUPTS();\r
+ HAL_Init();\r
+ BSP_LED_Init( LED2 );\r
+\r
+ /* This core uses the UART, so initialise it. */\r
+ xUARTHandle.Instance = USART3;\r
+ xUARTHandle.Init.BaudRate = 115200;\r
+ xUARTHandle.Init.WordLength = UART_WORDLENGTH_8B;\r
+ xUARTHandle.Init.StopBits = UART_STOPBITS_1;\r
+ xUARTHandle.Init.Parity = UART_PARITY_NONE;\r
+ xUARTHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;\r
+ xUARTHandle.Init.Mode = UART_MODE_TX_RX;\r
+ xUARTHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;\r
+ xUARTHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;\r
+ xUARTHandle.Init.OverSampling = UART_OVERSAMPLING_16;\r
+ HAL_UART_Init( &xUARTHandle );\r
+ HAL_UARTEx_SetRxFifoThreshold( &xUARTHandle, UART_RXFIFO_THRESHOLD_1_4 );\r
+ HAL_UARTEx_EnableFifoMode( &xUARTHandle );\r
+\r
+ /* AIEC Common configuration: make CPU1 and CPU2 SWI line1 sensitive to\r
+ rising edge. */\r
+ HAL_EXTI_EdgeConfig( EXTI_LINE1, EXTI_RISING_EDGE );\r
+\r
+ /* Interrupt used for M7 to M4 notifications. */\r
+ HAL_NVIC_SetPriority( EXTI0_IRQn, 0xFU, 0U );\r
+ HAL_NVIC_EnableIRQ( EXTI0_IRQn );\r
+}\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file UART/UART_WakeUpFromStopUsingFIFO/CM7/Src/stm32h7xx_hal_msp.c\r
+ * @author MCD Application Team\r
+ * @brief HAL MSP module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2018 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+#include "stm32h745i_discovery.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* User can use this section to tailor USARTx/UARTx instance used and associated\r
+ resources */\r
+#define USARTx USART3\r
+#define USARTx_CLK_ENABLE() __HAL_RCC_USART3_CLK_ENABLE()\r
+#define USARTx_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()\r
+#define USARTx_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()\r
+\r
+#define RCC_PERIPHCLK_USARTx RCC_PERIPHCLK_USART3\r
+#define RCC_USARTxCLKSOURCE_HSI RCC_USART3CLKSOURCE_HSI\r
+\r
+#define USARTx_FORCE_RESET() __HAL_RCC_USART3_FORCE_RESET()\r
+#define USARTx_RELEASE_RESET() __HAL_RCC_USART3_RELEASE_RESET()\r
+\r
+#define USARTx_IRQn USART3_IRQn\r
+#define USARTx_IRQHandler USART3_IRQHandler\r
+\r
+#define USARTx_TX_PIN GPIO_PIN_10\r
+#define USARTx_TX_GPIO_PORT GPIOB\r
+#define USARTx_TX_AF GPIO_AF7_USART3\r
+#define USARTx_RX_PIN GPIO_PIN_11\r
+#define USARTx_RX_GPIO_PORT GPIOB\r
+#define USARTx_RX_AF GPIO_AF7_USART3\r
+\r
+\r
+/** @addtogroup STM32H7xx_HAL_Examples\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_MSP\r
+ * @brief HAL MSP module.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_MSP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART MSP Initialization\r
+ * This function configures the hardware resources used in this example:\r
+ * - Peripheral's clock enable\r
+ * - Peripheral's GPIO Configuration\r
+ * @param huart: UART handle pointer\r
+ * @retval None\r
+ */\r
+void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+\r
+ RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;\r
+\r
+ /*##-1- Enable peripherals and GPIO Clocks #################################*/\r
+ /* Enable GPIO TX/RX clock */\r
+ USARTx_TX_GPIO_CLK_ENABLE();\r
+ USARTx_RX_GPIO_CLK_ENABLE();\r
+\r
+ /* Select HSI as source of USARTx clocks */\r
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USARTx;\r
+ RCC_PeriphClkInit.Usart234578ClockSelection = RCC_USARTxCLKSOURCE_HSI;\r
+ HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);\r
+\r
+ /* Enable USARTx clock */\r
+ USARTx_CLK_ENABLE();\r
+\r
+ /*##-2- Configure peripheral GPIO ##########################################*/\r
+ /* UART TX GPIO pin configuration */\r
+ GPIO_InitStruct.Pin = USARTx_TX_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ GPIO_InitStruct.Alternate = USARTx_TX_AF;\r
+\r
+ HAL_GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+ /* UART RX GPIO pin configuration */\r
+ GPIO_InitStruct.Pin = USARTx_RX_PIN;\r
+ GPIO_InitStruct.Alternate = USARTx_RX_AF;\r
+\r
+ HAL_GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+ /* NVIC for USART */\r
+ HAL_NVIC_SetPriority(USARTx_IRQn, 0, 1);\r
+ HAL_NVIC_EnableIRQ(USARTx_IRQn);\r
+}\r
+\r
+/**\r
+ * @brief UART MSP De-Initialization\r
+ * This function frees the hardware resources used in this example:\r
+ * - Disable the Peripheral's clock\r
+ * - Revert GPIO and NVIC configuration to their default state\r
+ * @param huart: UART handle pointer\r
+ * @retval None\r
+ */\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /*##-1- Reset peripherals ##################################################*/\r
+ USARTx_FORCE_RESET();\r
+ USARTx_RELEASE_RESET();\r
+\r
+ /*##-2- Disable peripherals and GPIO Clocks ################################*/\r
+ /* Configure UART Tx as alternate function */\r
+ HAL_GPIO_DeInit(USARTx_TX_GPIO_PORT, USARTx_TX_PIN);\r
+ /* Configure UART Rx as alternate function */\r
+ HAL_GPIO_DeInit(USARTx_RX_GPIO_PORT, USARTx_RX_PIN);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM4/Src/stm32h7xx_it.c\r
+ * @author MCD Application Team\r
+ * @brief Main Interrupt Service Routines for Cortex-M4.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_it.h"\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Examples\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO_IOToggle\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/* Cortex-M4 Processor Exceptions Handlers */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles NMI exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Memory Manage exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MemManage_Handler(void)\r
+{\r
+ /* Go to infinite loop when Memory Manage exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Bus Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Bus Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Usage Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Usage Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief This function handles Debug Monitor exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/******************************************************************************/\r
+/* STM32H7xx Peripherals Interrupt Handlers */\r
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
+/* available peripheral interrupt handler's name please refer to the startup */\r
+/* file (startup_stm32h7xx.s). */\r
+/******************************************************************************/\r
+/**\r
+ * @brief This function handles EXTI0 interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI0_IRQHandler( void )\r
+{\r
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);\r
+}\r
+\r
+/**\r
+ * @brief This function handles PPP interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+/*void PPP_IRQHandler(void)\r
+{\r
+}*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.1\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Ensure stdint is only used by the compiler, and not the assembler. */\r
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)\r
+ #include <stdint.h>\r
+ extern uint32_t SystemCoreClock;\r
+ void vGenerateM7ToM4Interrupt( void * xUpdatedMessageBuffer );\r
+#endif\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
+#define configMAX_PRIORITIES ( 7 )\r
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 0\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 0\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 10\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xQueueGetMutexHolder 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_eTaskGetState 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+ standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* Override the default implementation of sbSEND_COMPLETED so the macro creates\r
+an interrupt in the M4 core. See the comments at the top of main.c. */\r
+#define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateM7ToM4Interrupt( pxStreamBuffer )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file FreeRTOS/FreeRTOS_HwSemaphoreCoreSync/CM7/Inc/stm32h7xx_hal_conf.h\r
+ * @author MCD Application Team\r
+ * @brief HAL configuration file for Cortex-M7.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H7xx_HAL_CONF_H\r
+#define __STM32H7xx_HAL_CONF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* ########################## Module Selection ############################## */\r
+/**\r
+ * @brief This is the list of modules to be used in the HAL driver \r
+ */\r
+#define HAL_MODULE_ENABLED \r
+/* #define HAL_ADC_MODULE_ENABLED */\r
+/* #define HAL_CEC_MODULE_ENABLED */\r
+/* #define HAL_COMP_MODULE_ENABLED */\r
+#define HAL_CORTEX_MODULE_ENABLED\r
+/* #define HAL_CRC_MODULE_ENABLED */ \r
+/* #define HAL_CRYP_MODULE_ENABLED */\r
+/* #define HAL_DAC_MODULE_ENABLED */\r
+/* #define HAL_DCMI_MODULE_ENABLED */\r
+/* #define HAL_DFSDM_MODULE_ENABLED */\r
+#define HAL_DMA_MODULE_ENABLED\r
+/* #define HAL_DMA2D_MODULE_ENABLED */\r
+/* #define HAL_ETH_MODULE_ENABLED */\r
+/* #define HAL_EXTI_MODULE_ENABLED */\r
+/* #define HAL_FDCAN_MODULE_ENABLED */\r
+#define HAL_FLASH_MODULE_ENABLED \r
+#define HAL_GPIO_MODULE_ENABLED\r
+/* #define HAL_HASH_MODULE_ENABLED */\r
+/* #define HAL_HCD_MODULE_ENABLED */\r
+/* #define HAL_HRTIM_MODULE_ENABLED */\r
+#define HAL_HSEM_MODULE_ENABLED\r
+#define HAL_I2C_MODULE_ENABLED\r
+/* #define HAL_I2S_MODULE_ENABLED */\r
+/* #define HAL_IRDA_MODULE_ENABLED */\r
+/* #define HAL_IWDG_MODULE_ENABLED */\r
+/* #define HAL_JPEG_MODULE_ENABLED */\r
+/* #define HAL_LPTIM_MODULE_ENABLED */\r
+/* #define HAL_LTDC_MODULE_ENABLED */\r
+/* #define HAL_MDIOS_MODULE_ENABLED */\r
+/* #define HAL_MDMA_MODULE_ENABLED */\r
+/* #define HAL_MMC_MODULE_ENABLED */ \r
+/* #define HAL_NAND_MODULE_ENABLED */\r
+/* #define HAL_NOR_MODULE_ENABLED */\r
+/* #define HAL_OPAMP_MODULE_ENABLED */ \r
+/* #define HAL_PCD_MODULE_ENABLED */\r
+#define HAL_PWR_MODULE_ENABLED\r
+/* #define HAL_QSPI_MODULE_ENABLED */\r
+/* #define HAL_RAMECC_MODULE_ENABLED */ \r
+#define HAL_RCC_MODULE_ENABLED\r
+/* #define HAL_RNG_MODULE_ENABLED */ \r
+/* #define HAL_RTC_MODULE_ENABLED */\r
+/* #define HAL_SAI_MODULE_ENABLED */\r
+/* #define HAL_SD_MODULE_ENABLED */ \r
+/* #define HAL_SDRAM_MODULE_ENABLED */\r
+/* #define HAL_SMARTCARD_MODULE_ENABLED */\r
+/* #define HAL_SMBUS_MODULE_ENABLED */\r
+/* #define HAL_SPDIFRX_MODULE_ENABLED */ \r
+/* #define HAL_SPI_MODULE_ENABLED */\r
+/* #define HAL_SRAM_MODULE_ENABLED */\r
+/* #define HAL_SWPMI_MODULE_ENABLED */\r
+#define HAL_TIM_MODULE_ENABLED \r
+#define HAL_UART_MODULE_ENABLED \r
+/* #define HAL_USART_MODULE_ENABLED */ \r
+/* #define HAL_WWDG_MODULE_ENABLED */\r
+\r
+/* ########################## Oscillator Values adaptation ####################*/\r
+/**\r
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSE is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSE_VALUE) \r
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+ * @brief Internal oscillator (CSI) default value.\r
+ * This value is the default CSI value after Reset.\r
+ */\r
+#if !defined (CSI_VALUE)\r
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* CSI_VALUE */\r
+ \r
+/**\r
+ * @brief Internal High Speed oscillator (HSI) value.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSI is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @brief External Low Speed oscillator (LSE) value.\r
+ * This value is used by the UART, RTC HAL module to compute the system frequency\r
+ */\r
+#if !defined (LSE_VALUE)\r
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/\r
+#endif /* LSE_VALUE */\r
+\r
+ \r
+#if !defined (LSE_STARTUP_TIMEOUT)\r
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */\r
+#endif /* LSE_STARTUP_TIMEOUT */\r
+\r
+#if !defined (LSI_VALUE) \r
+ #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/\r
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature.*/\r
+\r
+/**\r
+ * @brief External clock source for I2S peripheral\r
+ * This value is used by the I2S HAL module to compute the I2S clock source \r
+ * frequency, this source is inserted directly through I2S_CKIN pad. \r
+ */\r
+#if !defined (EXTERNAL_CLOCK_VALUE)\r
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/\r
+#endif /* EXTERNAL_CLOCK_VALUE */\r
+\r
+/* Tip: To avoid modifying this file each time you need to use different HSE,\r
+ === you can define the HSE value in your toolchain compiler preprocessor. */\r
+\r
+/* ########################### System Configuration ######################### */\r
+/**\r
+ * @brief This is the HAL system configuration section\r
+ */ \r
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */\r
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */\r
+#define USE_RTOS 0\r
+#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */\r
+\r
+/* ########################### Ethernet Configuration ######################### */\r
+#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */\r
+#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */\r
+\r
+#define ETH_MAC_ADDR0 ((uint8_t)0x02)\r
+#define ETH_MAC_ADDR1 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR2 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR3 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR4 ((uint8_t)0x00)\r
+#define ETH_MAC_ADDR5 ((uint8_t)0x00)\r
+\r
+/* ########################## Assert Selection ############################## */\r
+/**\r
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
+ * HAL drivers code\r
+ */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/**\r
+ * @brief Include module's header file \r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_rcc.h"\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_gpio.h"\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dma.h"\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_MDMA_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_mdma.h"\r
+#endif /* HAL_MDMA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hash.h"\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dcmi.h"\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dma2d.h"\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DFSDM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dfsdm.h"\r
+#endif /* HAL_DFSDM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_eth.h"\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_EXTI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_exti.h"\r
+#endif /* HAL_EXTI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_cortex.h"\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_adc.h"\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FDCAN_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_fdcan.h"\r
+#endif /* HAL_FDCAN_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CEC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_cec.h"\r
+#endif /* HAL_CEC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_COMP_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_comp.h"\r
+#endif /* HAL_COMP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_crc.h"\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_cryp.h" \r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_dac.h"\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_flash.h"\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HRTIM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hrtim.h"\r
+#endif /* HAL_HRTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HSEM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hsem.h"\r
+#endif /* HAL_HSEM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sram.h"\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_nor.h"\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_nand.h"\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_i2c.h"\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_i2s.h"\r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_iwdg.h"\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_JPEG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_jpeg.h"\r
+#endif /* HAL_JPEG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_MDIOS_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_mdios.h"\r
+#endif /* HAL_MDIOS_MODULE_ENABLED */\r
+\r
+\r
+#ifdef HAL_MMC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_mmc.h"\r
+#endif /* HAL_MMC_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+#include "stm32h7xx_hal_lptim.h"\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+#include "stm32h7xx_hal_ltdc.h"\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_OPAMP_MODULE_ENABLED\r
+#include "stm32h7xx_hal_opamp.h"\r
+#endif /* HAL_OPAMP_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_pwr.h"\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_qspi.h"\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RAMECC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_ramecc.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_rng.h"\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_rtc.h"\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sai.h"\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sd.h"\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SDRAM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_sdram.h"\r
+#endif /* HAL_SDRAM_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_spi.h"\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPDIFRX_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_spdifrx.h"\r
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SWPMI_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_swpmi.h"\r
+#endif /* HAL_SWPMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_tim.h"\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_uart.h"\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_usart.h"\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_irda.h"\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_smartcard.h"\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMBUS_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_smbus.h"\r
+#endif /* HAL_SMBUS_MODULE_ENABLED */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_wwdg.h"\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_pcd.h"\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+ #include "stm32h7xx_hal_hcd.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed. \r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t *file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0U)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H7xx_HAL_CONF_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM7/Inc/stm32h7xx_it.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the headers of the interrupt handlers for Cortex-M7.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H7xx_IT_H\r
+#define __STM32H7xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+void EXTI1_IRQHandler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H7xx_IT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * See https://www.freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html for usage\r
+ * instructions (TBD, not available at the time of writing).\r
+ *\r
+ * Behavior\r
+ * --------\r
+ *\r
+ * This example stress tests a simple Asymmetric Multi Processing (AMP) core to\r
+ * core communication mechanism implemented using FreeRTOS message buffers:\r
+ * https://www.freertos.org/RTOS-stream-message-buffers.html Message buffers\r
+ * are used to pass an ASCII representation of an incrementing number (so "0",\r
+ * followed by "1", followed by "2", etc.) from a single 'sending' task that\r
+ * runs on the Arm Cortex-M7 core (the M7 core) to two "receiving" tasks\r
+ * running on the Arm Cortex-M4 core (the M4 core). There are two data message\r
+ * buffers, one for each receiving task. To distinguish between the receiving\r
+ * tasks one is assigned the task number 0, and the other task number 1.\r
+ *\r
+ * The M7 task sits in a loop sending the ascii strings to each M4 task. If a\r
+ * receiving task receives the next expected value in the sequence it prints its\r
+ * task number to the UART. If a receiving task receives anything else, or its\r
+ * attempt to receive data times out, then it hits an assert() that prints an\r
+ * error message to the UART before stopping all further processing on the M4\r
+ * core. If the example is running correctly you will see lots of "0"s (from\r
+ * the receiving task assigned task number 0) and "1"s (from the receiving task\r
+ * assigned task number 1) streaming from the UART. The time taken to output\r
+ * characters from the UART is the only thing throttling the speed of the core\r
+ * to core communication as it causes the message buffers to become full - which\r
+ * would probably happen anyway as the M7 core is executing at twice the\r
+ * frequency of the M4 core.\r
+ *\r
+ *\r
+ * Implementation of sbSEND_COMPLETED()\r
+ * ------------------------------------\r
+ *\r
+ * sbSEND_COMPLETED is a macro called by FreeRTOS after data has been sent to a\r
+ * message buffer in case there was a task blocked on the message buffer waiting\r
+ * for data to become available - in which case the waiting task would be\r
+ * unblocked: https://www.freertos.org/RTOS-message-buffer-example.html\r
+ * However, the default sbSEND_COMPLETED implementation assumes the sending task\r
+ * (or interrupt) and the receiving task are under the control of the same\r
+ * instance of the FreeRTOS kernel and run on the same MCU core. In this AMP\r
+ * example the sending task and the receiving tasks are under the control of two\r
+ * different instances of the FreeRTOS kernel, and run on different MCU cores,\r
+ * so the default sbSEND_COMPLETED implementation won't work (each FreeRTOS\r
+ * kernel instance only knowns about the tasks under its control). AMP\r
+ * scenarios therefore require the sbSEND_COMPLETED macro (and potentially the\r
+ * sbRECEIVE_COMPLETED macro, see below) to be overridden, which is done by\r
+ * simply providing your own implementation in the project's FreeRTOSConfig.h\r
+ * file. Note this example has a FreeRTOSConfig.h file used by the application\r
+ * that runs on the M7 core and a separate FreeRTOSConfig.h file used by the\r
+ * application that runs on the M4 core. The implementation of sbSEND_COMPLETED\r
+ * used by the M7 core simply triggers an interrupt in the M4 core. The\r
+ * interrupt's handler (the ISR that was triggered by the M7 core but executes\r
+ * on the M4 core) must then do the job that would otherwise be done by the\r
+ * default implementation of sbSEND_COMPLETE - namely unblock a task if the task\r
+ * was waiting to receive data from the message buffer that now contains data.\r
+ * There are two data message buffers though, so first ISR must determine which\r
+ * of the two contains data.\r
+ *\r
+ * This demo only has two data message buffers, so it would be reasonable to\r
+ * have the ISR simply query both to see which contained data, but that solution\r
+ * would not scale if there are many message buffers, or if the number of\r
+ * message buffers was unknown. Therefore, to demonstrate a more scalable\r
+ * solution, this example introduced a third message buffer - a 'control'\r
+ * message buffer as opposed to a 'data' message buffer. After the task on the\r
+ * M7 core writes to a data message buffer it writes the handle of the message\r
+ * buffer that contains data to the control message buffer. The ISR running on\r
+ * the M4 core then reads from the control message buffer to know which data\r
+ * message buffer contains data.\r
+ *\r
+ * The above described scenario contains many implementation decisions.\r
+ * Alternative methods of enabling the M4 core to know data message buffer\r
+ * contains data include:\r
+ *\r
+ * 1) Using a different interrupt for each data message buffer.\r
+ * 2) Passing all data from the M7 core to the M4 core through a single message\r
+ * buffer, along with additional data that tells the ISR running on the M4\r
+ * core which task to forward the data to.\r
+ *\r
+ *\r
+ * Implementation of sbRECEIVE_COMPLETED()\r
+ * ---------------------------------------\r
+ *\r
+ * sbRECEIVE_COMPLETED is the complement of sbSEND_COMPLETED. It is a macro\r
+ * called by FreeRTOS after data has been read from a message buffer in case\r
+ * there was a task blocked on the message buffer waiting for space to become\r
+ * available - in which case the waiting task would be unblocked so it can\r
+ * complete its write to the buffer.\r
+ *\r
+ * In this example the M7 task writes to the message buffers faster than the M4\r
+ * tasks read from them (in part because the M7 is running faster, and in part\r
+ * because the M4 cores write to the UART), so the buffers become full, and the\r
+ * M7 task enters the Blocked state to wait for space to become available. As\r
+ * with the sbSEND_COMPLETED macro, the default implementation of the\r
+ * sbRECEIVE_COMPLETED macro only works if the sender and receiver are under the\r
+ * control of the same instance of FreeRTOS and execute on the same core.\r
+ * Therefore, just as the application that executes on the M7 core overrides\r
+ * the default implementation of sbSEND_SOMPLETED(), the application that runs\r
+ * on the M4 core overrides the default implementation of sbRECEIVE_COMPLETED()\r
+ * to likewise generate an interrupt in the M7 core - so sbRECEIVE_COMPLETED()\r
+ * executes on the M4 core and generates an interrupt on the M7 core. To keep\r
+ * things simple the ISR that runs on the M7 core does not use a control\r
+ * message buffer to know which data message buffer contains space, and instead\r
+ * simply sends a notification to both data message buffers. Note however that\r
+ * this overly simplistic implementation is only acceptable because it is\r
+ * known that there is only one sending task, and that task cannot be blocked on\r
+ * both message buffers at the same time. Also, sending the notification to the\r
+ * data message buffer updates the receiving task's direct to task notification\r
+ * state: https://www.freertos.org/RTOS-task-notifications.html which is only ok\r
+ * because it is known the task is not using its notification state for any\r
+ * other purpose.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include "stdio.h"\r
+#include "string.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "message_buffer.h"\r
+#include "MessageBufferLocations.h"\r
+\r
+/* ST includes. */\r
+#include "stm32h7xx_hal.h"\r
+#include "stm32h745i_discovery.h"\r
+\r
+/* When the cores boot they very crudely wait for each other in a non chip\r
+specific way by waiting for the other core to start incrementing a shared\r
+variable within an array. mainINDEX_TO_TEST sets the index within the array to\r
+the variable this core tests to see if it is incrementing, and\r
+mainINDEX_TO_INCREMENT sets the index within the array to the variable this core\r
+increments to indicate to the other core that it is at the sync point. Note\r
+this is not a foolproof method and it is better to use a hardware specific\r
+solution, such as having one core boot the other core when it was ready, or\r
+using some kind of shared semaphore or interrupt. */\r
+#define mainINDEX_TO_TEST 0\r
+#define mainINDEX_TO_INCREMENT 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Implements the task that sends messages to the M7 core.\r
+ */\r
+static void prvM7CoreTasks( void *pvParameters );\r
+\r
+/*\r
+ * configSUPPORT_STATIC_ALLOCATION is set to 1, requiring this callback to\r
+ * provide statically allocated data for use by the idle task, which is a task\r
+ * created by the scheduler when it starts.\r
+ */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );\r
+\r
+/*\r
+ * Just waits to see a variable being incremented by the M4 core to know when\r
+ * the M4 has created the message buffers used for core to core communication.\r
+ */\r
+static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement );\r
+\r
+/*\r
+ * Setup the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static TaskHandle_t xM7AMPTask = NULL;\r
+\r
+int main( void )\r
+{\r
+BaseType_t x;\r
+\r
+ /*** See the comments at the top of this page ***/\r
+\r
+ prvSetupHardware();\r
+\r
+ /* Create the control and data message buffers, as described at the top of\r
+ this file. The message buffers are statically allocated at a known location\r
+ as both cores need to know where they are. See MessageBufferLocations.h. */\r
+ xControlMessageBuffer = xMessageBufferCreateStatic( /* The buffer size in bytes. */\r
+ mbaCONTROL_MESSAGE_BUFFER_SIZE,\r
+ /* Statically allocated buffer storage area. */\r
+ ucControlBufferStorage,\r
+ /* Message buffer handle. */\r
+ &xControlMessageBufferStruct );\r
+ for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )\r
+ {\r
+ xDataMessageBuffers[ x ] = xMessageBufferCreateStatic( mbaTASK_MESSAGE_BUFFER_SIZE,\r
+ &( ucDataBufferStorage[ x ][ 0 ] ),\r
+ &( xDataMessageBufferStructs[ x ] ) );\r
+ }\r
+\r
+ /* The message buffers have been initialised so it is safe for both cores to\r
+ synchronise their startup. */\r
+ prvWaitForOtherCoreToStart( mainINDEX_TO_TEST, mainINDEX_TO_INCREMENT );\r
+\r
+ /* Start the task that executes on the M7 core. */\r
+ xTaskCreate( prvM7CoreTasks, /* Function that implements the task. */\r
+ "AMPM7Core", /* Task name, for debugging only. */\r
+ configMINIMAL_STACK_SIZE, /* Size of stack (in words) to allocate for this task. */\r
+ NULL, /* Task parameter, not used in this case. */\r
+ tskIDLE_PRIORITY, /* Task priority. */\r
+ &xM7AMPTask ); /* Task handle, used to unblock task from interrupt. */\r
+\r
+ /* Start scheduler */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will not get here if the scheduler starts successfully. If you do end up\r
+ here then there wasn't enough heap memory available to start either the idle\r
+ task or the timer/daemon task. https://www.freertos.org/a00111.html */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvM7CoreTasks( void *pvParameters )\r
+{\r
+BaseType_t x;\r
+uint32_t ulNextValue = 0;\r
+const TickType_t xDelay = pdMS_TO_TICKS( 25 );\r
+char cString[ 15 ];\r
+size_t xStringLength;\r
+\r
+ /* Remove warning about unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Create the next string to send. The value is incremented on each\r
+ loop iteration, and the length of the string changes as the number of\r
+ digits in the value increases. */\r
+ sprintf( cString, "%lu", ( unsigned long ) ulNextValue );\r
+ xStringLength = strlen( cString );\r
+\r
+ /* This task runs on the M7 core, use the message buffers to send the\r
+ strings to the tasks running on the M4 core. This will result in\r
+ sbSEND_COMPLETED() being executed, which in turn will write the handle\r
+ of the message buffer written to into xControlMessageBuffer then\r
+ generate an interrupt in M4 core. */\r
+ for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )\r
+ {\r
+ while( xMessageBufferSend( xDataMessageBuffers[ x ],\r
+ ( void * ) cString,\r
+ xStringLength,\r
+ portMAX_DELAY ) != xStringLength );\r
+\r
+ /* Delay before repeating */\r
+// vTaskDelay( xDelay );\r
+ }\r
+\r
+ ulNextValue++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vGenerateM7ToM4Interrupt( void * xUpdatedMessageBuffer )\r
+{\r
+MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;\r
+\r
+ /* Called by the implementation of sbSEND_COMPLETED() in FreeRTOSConfig.h.\r
+ See the comments at the top of this file. Write the handle of the data\r
+ message buffer to which data was written to the control message buffer. */\r
+ if( xUpdatedBuffer != xControlMessageBuffer )\r
+ {\r
+ while( xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ) != sizeof( xUpdatedBuffer ) )\r
+ {\r
+ /* Nothing to do here. Note it is very bad to loop in an interrupt\r
+ service routine. If a loop is really required then defer the\r
+ routine to a task. */\r
+ }\r
+\r
+ /* Generate interrupt in the M4 core. */\r
+ HAL_EXTI_D1_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, DISABLE );\r
+ HAL_EXTI_D2_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, ENABLE );\r
+ HAL_EXTI_GenerateSWInterrupt( EXTI_LINE0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Idle task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xIdleTaskTCB;\r
+static uint32_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
+\r
+ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide\r
+ an implementation of vApplicationGetIdleTaskMemory() to provide the memory\r
+ that is used by the Idle task.\r
+ https://www.freertos.org/a00110.html#configSUPPORT_STATIC_ALLOCATION */\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
+ state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement )\r
+{\r
+volatile uint32_t ulInitialCount = ulStartSyncCounters[ ulIndexToTest ], x;\r
+const uint32_t ulCrudeLoopDelay = 0xfffffUL;\r
+\r
+ /* When the cores boot they very crudely wait for each other in a non chip\r
+ specific way by waiting for the other core to start incrementing a shared\r
+ variable within an array. mainINDEX_TO_TEST sets the index within the array\r
+ to the variable this core tests to see if it is incrementing, and\r
+ mainINDEX_TO_INCREMENT sets the index within the array to the variable this\r
+ core increments to indicate to the other core that it is at the sync point.\r
+ Note this is not a foolproof method and it is better to use a hardware\r
+ specific solution, such as having one core boot the other core when it was\r
+ ready, or using some kind of shared semaphore or interrupt. */\r
+\r
+ /* Wait for the other core to reach the synchronisation point. */\r
+ while( ulStartSyncCounters[ ulIndexToTest ] == ulInitialCount );\r
+ ulInitialCount = ulStartSyncCounters[ ulIndexToTest ];\r
+\r
+ for( ;; )\r
+ {\r
+ ulStartSyncCounters[ ulIndexToIncrement ]++;\r
+ if( ulStartSyncCounters[ ulIndexToTest ] != ulInitialCount )\r
+ {\r
+ ulStartSyncCounters[ ulIndexToIncrement ]++;\r
+ break;\r
+ }\r
+\r
+ /* Unlike the M4 core, this core does not have direct access to the UART,\r
+ so simply toggle an LED to show its status. */\r
+ for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );\r
+ BSP_LED_Off( LED2 );\r
+ for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );\r
+ BSP_LED_On( LED2 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )\r
+{\r
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
+uint32_t x;\r
+\r
+ configASSERT( xM7AMPTask );\r
+\r
+ HAL_EXTI_D1_ClearFlag( EXTI_LINE1 );\r
+\r
+ /* Task can't be blocked on both so just send the notification to both. */\r
+ for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )\r
+ {\r
+ xMessageBufferReceiveCompletedFromISR( xDataMessageBuffers[ x ], &xHigherPriorityTaskWoken );\r
+ }\r
+\r
+ /* Normal FreeRTOS "yield from interrupt" semantics, where\r
+ xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to\r
+ pdTRUE if the interrupt unblocks a task that has a priority above that of\r
+ the currently executing task. */\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+MPU_Region_InitTypeDef MPU_InitStruct;\r
+RCC_ClkInitTypeDef RCC_ClkInitStruct;\r
+RCC_OscInitTypeDef RCC_OscInitStruct;\r
+\r
+ /* Configure the MPU attributes as Not Cachable for Internal D3SRAM. The\r
+ Base Address is 0x38000000 (D3_SRAM_BASE), and the size is 64K. */\r
+ HAL_MPU_Disable();\r
+ MPU_InitStruct.Enable = MPU_REGION_ENABLE;\r
+ MPU_InitStruct.BaseAddress = D3_SRAM_BASE;\r
+ MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;\r
+ MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;\r
+ MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;\r
+ MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;\r
+ MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;\r
+ MPU_InitStruct.Number = MPU_REGION_NUMBER0;\r
+ MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;\r
+ MPU_InitStruct.SubRegionDisable = 0x00;\r
+ MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;\r
+ HAL_MPU_ConfigRegion(&MPU_InitStruct);\r
+ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);\r
+\r
+ /* Enable I-Cache */\r
+ SCB_EnableICache();\r
+\r
+ /* Enable D-Cache */\r
+ SCB_EnableDCache();\r
+\r
+ HAL_Init();\r
+ BSP_LED_Init(LED1);\r
+\r
+\r
+ /*\r
+ System Clock Configuration:\r
+ System Clock source = PLL (HSE)\r
+ SYSCLK(Hz) = 400000000 (Cortex-M7 CPU Clock)\r
+ HCLK(Hz) = 200000000 (Cortex-M4 CPU, Bus matrix Clocks)\r
+ AHB Prescaler = 2\r
+ D1 APB3 Prescaler = 2 (APB3 Clock 100MHz)\r
+ D2 APB1 Prescaler = 2 (APB1 Clock 100MHz)\r
+ D2 APB2 Prescaler = 2 (APB2 Clock 100MHz)\r
+ D3 APB4 Prescaler = 2 (APB4 Clock 100MHz)\r
+ HSE Frequency(Hz) = 25000000\r
+ PLL_M = 5\r
+ PLL_N = 160\r
+ PLL_P = 2\r
+ PLL_Q = 4\r
+ PLL_R = 2\r
+ VDD(V) = 3.3\r
+ Flash Latency(WS) = 4\r
+ */\r
+\r
+ HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);\r
+\r
+ /* The voltage scaling allows optimizing the power consumption when the\r
+ device is clocked below the maximum system frequency, to update the voltage\r
+ scaling value regarding system frequency refer to product datasheet. */\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+ while( !__HAL_PWR_GET_FLAG( PWR_FLAG_VOSRDY ) )\r
+ {\r
+ __asm volatile ( "NOP" );\r
+ }\r
+\r
+ /* Enable HSE Oscillator and activate PLL with HSE as source */\r
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;\r
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;\r
+ RCC_OscInitStruct.CSIState = RCC_CSI_OFF;\r
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r
+\r
+ RCC_OscInitStruct.PLL.PLLM = 5;\r
+ RCC_OscInitStruct.PLL.PLLN = 160;\r
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;\r
+ RCC_OscInitStruct.PLL.PLLP = 2;\r
+ RCC_OscInitStruct.PLL.PLLR = 2;\r
+ RCC_OscInitStruct.PLL.PLLQ = 4;\r
+\r
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;\r
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;\r
+ configASSERT( HAL_RCC_OscConfig( &RCC_OscInitStruct ) == HAL_OK );\r
+\r
+ /* Select PLL as system clock source and configure bus clocks dividers */\r
+ RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \\r
+ RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 );\r
+\r
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;\r
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;\r
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;\r
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;\r
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;\r
+ RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;\r
+ configASSERT( HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_4 ) == HAL_OK );\r
+\r
+ /* AIEC Common configuration: make CPU1 and CPU2 SWI line0 sensitive to\r
+ rising edge. */\r
+ HAL_EXTI_EdgeConfig( EXTI_LINE0, EXTI_RISING_EDGE );\r
+\r
+ /* Interrupt used for M4 to M7 notifications. */\r
+ HAL_NVIC_SetPriority( EXTI1_IRQn, 0xFU, 0U );\r
+ HAL_NVIC_EnableIRQ( EXTI1_IRQn );\r
+}\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM7/Src/stm32h7xx_hal_timebase_tim.c\r
+ * @author MCD Application Team\r
+ * @brief HAL time base based on the hardware TIM.\r
+ * \r
+ * This file overrides the native HAL time base functions (defined as weak)\r
+ * the TIM time base:\r
+ * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms\r
+ * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+TIM_HandleTypeDef TimHandle;\r
+/* Private function prototypes -----------------------------------------------*/\r
+void TIM6_DAC_IRQHandler(void);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief This function configures the TIM6 as a time base source. \r
+ * The time source is configured to have 1ms time base with a dedicated \r
+ * Tick interrupt priority. \r
+ * @note This function is called automatically at the beginning of program after\r
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). \r
+ * @param TickPriority: Tick interrupt priority.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)\r
+{\r
+ RCC_ClkInitTypeDef clkconfig;\r
+ uint32_t uwTimclock, uwAPB1Prescaler = 0U;\r
+ uint32_t uwPrescalerValue = 0U;\r
+ uint32_t pFLatency;\r
+ \r
+ /*Configure the TIM6 IRQ priority */\r
+ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);\r
+ \r
+ /* Enable the TIM6 global Interrupt */\r
+ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);\r
+ \r
+ /* Enable TIM6 clock */\r
+ __HAL_RCC_TIM6_CLK_ENABLE();\r
+ \r
+ /* Get clock configuration */\r
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);\r
+ \r
+ /* Get APB1 prescaler */\r
+ uwAPB1Prescaler = clkconfig.APB1CLKDivider;\r
+ \r
+ /* Compute TIM6 clock */\r
+ if (uwAPB1Prescaler == RCC_HCLK_DIV1) \r
+ {\r
+ uwTimclock = HAL_RCC_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ uwTimclock = 2*HAL_RCC_GetPCLK1Freq();\r
+ }\r
+ \r
+ /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */\r
+ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);\r
+ \r
+ /* Initialize TIM6 */\r
+ TimHandle.Instance = TIM6;\r
+ \r
+ /* Initialize TIMx peripheral as follow:\r
+ + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.\r
+ + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.\r
+ + ClockDivision = 0\r
+ + Counter direction = Up\r
+ */\r
+ TimHandle.Init.Period = (1000000U / 1000U) - 1U;\r
+ TimHandle.Init.Prescaler = uwPrescalerValue;\r
+ TimHandle.Init.ClockDivision = 0;\r
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;\r
+ if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)\r
+ {\r
+ /* Start the TIM time Base generation in interrupt mode */\r
+ return HAL_TIM_Base_Start_IT(&TimHandle);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Suspend Tick increment.\r
+ * @note Disable the tick increment by disabling TIM6 update interrupt.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_SuspendTick(void)\r
+{\r
+ /* Disable TIM6 update Interrupt */\r
+ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);\r
+}\r
+\r
+/**\r
+ * @brief Resume Tick increment.\r
+ * @note Enable the tick increment by Enabling TIM6 update interrupt.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_ResumeTick(void)\r
+{\r
+ /* Enable TIM6 Update interrupt */\r
+ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);\r
+}\r
+\r
+/**\r
+ * @brief Period elapsed callback in non blocking mode\r
+ * @note This function is called when TIM6 interrupt took place, inside\r
+ * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment\r
+ * a global variable "uwTick" used as application time base.\r
+ * @param htim : TIM handle\r
+ * @retval None\r
+ */\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ HAL_IncTick();\r
+}\r
+\r
+/**\r
+ * @brief This function handles TIM interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM6_DAC_IRQHandler(void)\r
+{\r
+ HAL_TIM_IRQHandler(&TimHandle);\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM7/Src/stm32h7xx_it.c\r
+ * @author MCD Application Team\r
+ * @brief Main Interrupt Service Routines.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_it.h"\r
+#include "stm32h7xx_hal.h"\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/* Cortex-M7 Processor Exceptions Handlers */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles NMI exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Memory Manage exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MemManage_Handler(void)\r
+{\r
+ /* Go to infinite loop when Memory Manage exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Bus Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Bus Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Usage Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Usage Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Debug Monitor exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/******************************************************************************/\r
+/* STM32H7xx Peripherals Interrupt Handlers */\r
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
+/* available peripheral interrupt handler's name please refer to the startup */\r
+/* file (startup_stm32h7xx.s). */\r
+/******************************************************************************/\r
+/**\r
+ * @brief This function handles EXTI0 interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI1_IRQHandler( void )\r
+{\r
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);\r
+}\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef MESSAGE_BUFFER_AMP_H\r
+#define MESSAGE_BUFFER_AMP_H\r
+\r
+/* Enough four 4 8 byte strings, plus the additional 4 bytes per message\r
+overhead of message buffers. */\r
+#define mbaTASK_MESSAGE_BUFFER_SIZE ( 60 )\r
+\r
+#define mbaCONTROL_MESSAGE_BUFFER_SIZE ( 24 )\r
+\r
+/* The number of instances of prvM4CoreTasks that are created. */\r
+#define mbaNUMBER_OF_CORE_2_TASKS 2\r
+\r
+/* A block time of 0 simply means, don't block. */\r
+#define mbaDONT_BLOCK 0\r
+\r
+/* Place the message buffers at a fixed location so it is the same for both\r
+cores. */\r
+#pragma location = 0x38000000\r
+MessageBufferHandle_t xControlMessageBuffer;\r
+\r
+#pragma location = 0x38000004\r
+MessageBufferHandle_t xDataMessageBuffers[ mbaNUMBER_OF_CORE_2_TASKS ];\r
+\r
+#pragma location = 0x3800000c\r
+static volatile uint32_t ulStartSyncCounters[ mbaNUMBER_OF_CORE_2_TASKS ];\r
+\r
+\r
+/* The variable used to hold the stream buffer structure.*/\r
+#pragma location = 0x38000050\r
+StaticStreamBuffer_t xControlMessageBufferStruct;\r
+#pragma location = 0x380000A0\r
+StaticStreamBuffer_t xDataMessageBufferStructs[mbaNUMBER_OF_CORE_2_TASKS];\r
+/* Used to dimension the array used to hold the streams.*/\r
+/* Defines the memory that will actually hold the streams within the stream buffer.*/\r
+#pragma location = 0x38000100\r
+static uint8_t ucControlBufferStorage[ mbaCONTROL_MESSAGE_BUFFER_SIZE ];\r
+#pragma location = 0x38000200\r
+static uint8_t ucDataBufferStorage[mbaNUMBER_OF_CORE_2_TASKS][ mbaTASK_MESSAGE_BUFFER_SIZE ];\r
+\r
+\r
+#endif /* MESSAGE_BUFFER_AMP_H */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<project>\r
+ <fileVersion>3</fileVersion>\r
+ <configuration>\r
+ <name>STM32H745I_Discovery_CM7</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>30</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32H7x5_CM7.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>8.22.1.15696</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>IJET_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>8.32.1.18618</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32H7xxx_CM7.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggerExtraOption</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAllMTBOptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreNrOfCores</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreMaster</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticorePort</name>\r
+ <state>53461</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreWorkspace</name>\r
+ <state>C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\Project.eww</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveProject</name>\r
+ <state>Project</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveConfiguration</name>\r
+ <state>STM32H745I_Discovery_CM4</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadExtraImage</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MassEraseBeforeFlashing</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreNrOfCoresSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CADI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCadiMemory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Fast Model</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCADILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCADILogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CMSISDAP_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>4</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSFERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCMSISDAPUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCMSISDAPUsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IJET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetResetList</name>\r
+ <version>1</version>\r
+ <state>9</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerFromProbe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProtocolRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPin</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetCpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPrescalerList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSFERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSelectedCPUBehaviour</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPreferETB</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSettingsList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSizeList</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashBoardPathSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIjetUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCIjetUsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>16</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSFERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>NULINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>3</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>400</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchSFERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkJtagSpeedList</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkDAPNumber</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkDebugAccessPortRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUseServerSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkProbeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>TIFET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetResetList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetVccTypeDefault</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetVoltage</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetVCCDefault</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetSettlingtime</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetRadioJtagSpeedType</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetConnection</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetUsbComPort</name>\r
+ <state>Automatic</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetAllowAccessToBSL</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetRadioEraseFlash</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100BreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100DoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSFERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SwoClockEdit</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100HWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100ResetList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100JtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceRadio</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100ProbeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SWOPortRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SWOPort</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXDSTargetVccEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXDSTargetVoltage</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDSDigitalStatesConfigFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
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+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
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+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
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+ <loadFlag>0</loadFlag>\r
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+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
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+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
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+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>STM32H745I_Discovery_CM4</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
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+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSFERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>NULINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>3</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchSFERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkJtagSpeedList</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkDAPNumber</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkDebugAccessPortRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUseServerSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkProbeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>TIFET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetResetList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetVccTypeDefault</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetVoltage</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetVCCDefault</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetSettlingtime</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetRadioJtagSpeedType</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetConnection</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetUsbComPort</name>\r
+ <state>Automatic</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetAllowAccessToBSL</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetRadioEraseFlash</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100BreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100DoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSFERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SwoClockEdit</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100HWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100ResetList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100JtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceRadio</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100ProbeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SWOPortRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SWOPort</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXDSTargetVccEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXDSTargetVoltage</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDSDigitalStatesConfigFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<project>\r
+ <fileVersion>3</fileVersion>\r
+ <configuration>\r
+ <name>STM32H745I_Discovery_CM7</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>31</version>\r
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+</project>\r
--- /dev/null
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+ <check name="MISRAC++2008-18-7-1" enabled="true" />\r
+ </group>\r
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+ </group>\r
+ <group enabled="true" name="MISRAC++2008-27-0">\r
+ <check name="MISRAC++2008-27-0-1" enabled="true" />\r
+ </group>\r
+ </package>\r
+ </checks_tree>\r
+ </cstat_settings>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RuntimeChecking</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>GenRtcDebugHeap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcEnableBoundsChecking</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcCheckPtrsNonInstrMem</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcTrackPointerBounds</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcCheckAccesses</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcGenerateEntries</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcNrTrackedPointers</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcIntOverflow</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcIncUnsigned</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcIntConversion</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcInclExplicit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcIntShiftOverflow</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcInclUnsignedShiftOverflow</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcUnhandledCase</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcDivByZero</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenRtcCheckPtrsNonInstrFunc</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Application</name>\r
+ <group>\r
+ <name>EWARM</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\startup_stm32h745xx.s</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>User</name>\r
+ <group>\r
+ <name>CM4</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM4\include\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM4\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM4\stm32h7xx_hal_msp.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM4\stm32h7xx_it.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>CM7</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM7\include\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM7\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM7\stm32h7xx_hal_timebase_tim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\CM7\stm32h7xx_it.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS_Source</name>\r
+ <group>\r
+ <name>include</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\event_groups.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\message_buffer.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\queue.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\semphr.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\stream_buffer.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\task.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\include\timers.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>portable</name>\r
+ <group>\r
+ <name>IAR</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portasm.s</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>MemMang</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\event_groups.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\stream_buffer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>ST_code</name>\r
+ <group>\r
+ <name>BSP</name>\r
+ <group>\r
+ <name>STM32H745I_Discovery</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\BSP\STM32H745I-Discovery\stm32h745i_discovery.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>CMSIS</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\system_stm32h7xx.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>STM32H7xx_HAL_Driver</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_code\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+</project>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\Project.ewp</path>\r
+ </project>\r
+ <batchBuild />\r
+</workspace>\r
--- /dev/null
+<!DOCTYPE html>\r
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">\r
+<head>\r
+ <meta charset="utf-8" />\r
+ <meta name="generator" content="pandoc" />\r
+ <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />\r
+ <title>Release Notes for STM32H745I-DISCO BSP Driver</title>\r
+ <style type="text/css">\r
+ code{white-space: pre-wrap;}\r
+ span.smallcaps{font-variant: small-caps;}\r
+ span.underline{text-decoration: underline;}\r
+ div.column{display: inline-block; vertical-align: top; width: 50%;}\r
+ </style>\r
+ <link rel="stylesheet" href="../../../_htmresc/mini-st.css" />\r
+ <!--[if lt IE 9]>\r
+ <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>\r
+ <![endif]-->\r
+</head>\r
+<body>\r
+<div class="row">\r
+<div class="col-sm-12 col-lg-4">\r
+<div class="card fluid">\r
+<div class="sectione dark">\r
+<center>\r
+<h1 id="release-notes-for-stm32h745i-disco-bsp-driver"><strong>Release Notes for STM32H745I-DISCO BSP Driver</strong></h1>\r
+<p>Copyright © 2019 STMicroelectronics<br />\r
+</p>\r
+<a href="https://www.st.com" class="logo"><img src="../../../_htmresc/st_logo.png" alt="ST logo" /></a>\r
+</center>\r
+</div>\r
+</div>\r
+<h1 id="license"><strong>License</strong></h1>\r
+This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:\r
+<center>\r
+<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>\r
+</center>\r
+</div>\r
+<div class="col-sm-12 col-lg-8">\r
+<h1 id="update-history"><strong>Update History</strong></h1>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 05-April-2019</strong></label>\r
+<div>\r
+<h2 id="main-changes">Main Changes</h2>\r
+<ul>\r
+<li>First official release</li>\r
+</ul>\r
+</div>\r
+</div>\r
+</div>\r
+</div>\r
+<footer class="sticky">\r
+For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>\r
+</footer>\r
+</body>\r
+</html>\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery.c\r
+ * @author MCD Application Team\r
+ * @brief This file provides a set of firmware functions to manage LEDs,\r
+ * push-buttons, external SDRAM, external QSPI Flash,\r
+ * available on STM32H745I-Discovery board (MB1381) from \r
+ * STMicroelectronics.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL STM32H745I_DISCOVERY_LOW_LEVEL\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_Defines Private Defines\r
+ * @{\r
+ */\r
+/**\r
+ * @brief STM32H745I Discovery BSP Driver version number V1.0.0\r
+ */\r
+#define __STM32H745I_DISCOVERY_BSP_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32H745I_DISCOVERY_BSP_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
+#define __STM32H745I_DISCOVERY_BSP_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32H745I_DISCOVERY_BSP_VERSION_RC (0x00) /*!< [7:0] release candidate */\r
+#define __STM32H745I_DISCOVERY_BSP_VERSION ((__STM32H745I_DISCOVERY_BSP_VERSION_MAIN << 24)\\r
+ |(__STM32H745I_DISCOVERY_BSP_VERSION_SUB1 << 16)\\r
+ |(__STM32H745I_DISCOVERY_BSP_VERSION_SUB2 << 8 )\\r
+ |(__STM32H745I_DISCOVERY_BSP_VERSION_RC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_Variables Private Variables\r
+ * @{\r
+ */\r
+\r
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT,\r
+ LED2_GPIO_PORT};\r
+\r
+const uint32_t GPIO_PIN[LEDn] = {LED1_PIN,\r
+ LED2_PIN};\r
+\r
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT };\r
+\r
+const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN };\r
+\r
+const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn };\r
+\r
+static I2C_HandleTypeDef hdiscovery_I2c = {0};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes Private FunctionPrototypes\r
+ * @{\r
+ */\r
+static void I2Cx_MspInit(void);\r
+static void I2Cx_Init(void);\r
+static void I2Cx_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);\r
+static uint8_t I2Cx_Read(uint8_t Addr, uint8_t Reg);\r
+static HAL_StatusTypeDef I2Cx_ReadMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);\r
+static HAL_StatusTypeDef I2Cx_WriteMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);\r
+static void I2Cx_Error(uint8_t Addr);\r
+\r
+/* AUDIO IO functions */\r
+void AUDIO_IO_Init(void);\r
+void AUDIO_IO_DeInit(void);\r
+void AUDIO_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value);\r
+uint16_t AUDIO_IO_Read(uint8_t Addr, uint16_t Reg);\r
+void AUDIO_IO_Delay(uint32_t Delay);\r
+\r
+/* TouchScreen (TS) IO functions */\r
+void TS_IO_Init(void);\r
+void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);\r
+uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg);\r
+uint16_t TS_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length);\r
+void TS_IO_WriteMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length);\r
+void TS_IO_Delay(uint32_t Delay);\r
+\r
+/* LCD Display IO functions */\r
+void OTM8009A_IO_Delay(uint32_t Delay);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_BSP_Exported_Functions Exported Functions\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief This method returns the STM32H745I Discovery BSP Driver revision\r
+ * @retval version: 0xXYZR (8bits for each decimal, R for RC)\r
+ */\r
+uint32_t BSP_GetVersion(void)\r
+{\r
+ return __STM32H745I_DISCOVERY_BSP_VERSION;\r
+}\r
+\r
+/**\r
+ * @brief Configures LED GPIO.\r
+ * @param Led: LED to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4\r
+ * @retval None\r
+ */\r
+void BSP_LED_Init(Led_TypeDef Led)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+ \r
+ /* Enable the GPIO_LED clock */\r
+ LEDx_GPIO_CLK_ENABLE();\r
+ \r
+ /* Configure the GPIO_LED pin */\r
+ GPIO_InitStruct.Pin = GPIO_PIN[Led];\r
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+ GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ \r
+ HAL_GPIO_Init(GPIO_PORT[Led], &GPIO_InitStruct);\r
+ \r
+ /* By default, turn off LED */\r
+ HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInit LEDs.\r
+ * @param Led: LED to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4\r
+ * @note Led DeInit does not disable the GPIO clock\r
+ * @retval None\r
+ */\r
+void BSP_LED_DeInit(Led_TypeDef Led)\r
+{\r
+ /* Turn off LED */\r
+ HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET);\r
+ /* Configure the GPIO_LED pin */\r
+ HAL_GPIO_DeInit(GPIO_PORT[Led], GPIO_PIN[Led]);\r
+}\r
+\r
+/**\r
+ * @brief Turns selected LED On.\r
+ * @param Led: LED to be set on\r
+ * This parameter can be one of the following values:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4\r
+ * @retval None\r
+ */\r
+void BSP_LED_On(Led_TypeDef Led)\r
+{\r
+ HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET);\r
+}\r
+\r
+/**\r
+ * @brief Turns selected LED Off.\r
+ * @param Led: LED to be set off\r
+ * This parameter can be one of the following values:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4\r
+ * @retval None\r
+ */\r
+void BSP_LED_Off(Led_TypeDef Led)\r
+{\r
+ HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);\r
+}\r
+\r
+/**\r
+ * @brief Toggles the selected LED.\r
+ * @param Led: LED to be toggled\r
+ * This parameter can be one of the following values:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4\r
+ * @retval None\r
+ */\r
+void BSP_LED_Toggle(Led_TypeDef Led)\r
+{\r
+ HAL_GPIO_TogglePin(GPIO_PORT[Led], GPIO_PIN[Led]);\r
+}\r
+\r
+/**\r
+ * @brief Configures button GPIO and EXTI Line.\r
+ * @param Button: Button to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg BUTTON_WAKEUP: Wakeup Push Button\r
+ * @arg BUTTON_USER: User Push Button\r
+ * @param Button_Mode: Button mode\r
+ * This parameter can be one of the following values:\r
+ * @arg BUTTON_MODE_GPIO: Button will be used as simple IO\r
+ * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line\r
+ * with interrupt generation capability\r
+ * @retval None\r
+ */\r
+void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+ \r
+ /* Enable the BUTTON clock */\r
+ BUTTON_GPIO_CLK_ENABLE();\r
+ \r
+ if(Button_Mode == BUTTON_MODE_GPIO)\r
+ {\r
+ /* Configure Button pin as input */\r
+ GPIO_InitStruct.Pin = BUTTON_PIN[Button];\r
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);\r
+ }\r
+ \r
+ if(Button_Mode == BUTTON_MODE_EXTI)\r
+ {\r
+ /* Configure Button pin as input with External interrupt */\r
+ GPIO_InitStruct.Pin = BUTTON_PIN[Button];\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ \r
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;\r
+ \r
+ HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);\r
+ \r
+ /* Enable and set Button EXTI Interrupt to the lowest priority */\r
+ HAL_NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F, 0x00);\r
+ HAL_NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Push Button DeInit.\r
+ * @param Button: Button to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg BUTTON_WAKEUP: Wakeup Push Button\r
+ * @arg BUTTON_USER: User Push Button\r
+ * @note PB DeInit does not disable the GPIO clock\r
+ * @retval None\r
+ */\r
+void BSP_PB_DeInit(Button_TypeDef Button)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ gpio_init_structure.Pin = BUTTON_PIN[Button];\r
+ HAL_NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));\r
+ HAL_GPIO_DeInit(BUTTON_PORT[Button], gpio_init_structure.Pin);\r
+}\r
+\r
+/**\r
+ * @brief Returns the selected button state.\r
+ * @param Button: Button to be checked\r
+ * This parameter can be one of the following values:\r
+ * @arg BUTTON_WAKEUP: Wakeup Push Button\r
+ * @arg BUTTON_USER: User Push Button\r
+ * @retval The Button GPIO pin value\r
+ */\r
+uint32_t BSP_PB_GetState(Button_TypeDef Button)\r
+{\r
+ return HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_Functions Private Functions\r
+ * @{\r
+ */\r
+/*******************************************************************************\r
+ BUS OPERATIONS\r
+*******************************************************************************/\r
+\r
+/******************************* I2C Routines *********************************/\r
+/**\r
+ * @brief Initializes I2C MSP.\r
+ * @retval None\r
+ */\r
+static void I2Cx_MspInit(void)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+ RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;\r
+ \r
+ /* Configure the I2C clock source */\r
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C123;\r
+ RCC_PeriphClkInit.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;\r
+ HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);\r
+ \r
+ /* set STOPWUCK in RCC_CFGR */\r
+ __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_HSI);\r
+ \r
+ /*** Configure the GPIOs ***/ \r
+ /* Enable GPIO clock */\r
+ DISCOVERY_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();\r
+ \r
+ /* Configure I2C Tx as alternate function */\r
+ gpio_init_structure.Pin = DISCOVERY_I2Cx_SCL_PIN;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_OD;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ gpio_init_structure.Alternate = DISCOVERY_I2Cx_SCL_SDA_AF;\r
+ HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);\r
+ \r
+ /* Configure I2C Rx as alternate function */\r
+ gpio_init_structure.Pin = DISCOVERY_I2Cx_SDA_PIN;\r
+ HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);\r
+ \r
+ /*** Configure the I2C peripheral ***/ \r
+ /* Enable I2C clock */\r
+ DISCOVERY_I2Cx_CLK_ENABLE();\r
+ \r
+ /* Force the I2C peripheral clock reset */ \r
+ DISCOVERY_I2Cx_FORCE_RESET(); \r
+ \r
+ /* Release the I2C peripheral clock reset */ \r
+ DISCOVERY_I2Cx_RELEASE_RESET(); \r
+ \r
+ /* Enable and set I2Cx Interrupt to a lower priority */\r
+ HAL_NVIC_SetPriority(DISCOVERY_I2Cx_EV_IRQn, 0x0F, 0);\r
+ HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_EV_IRQn);\r
+ \r
+ /* Enable and set I2Cx Interrupt to a lower priority */\r
+ HAL_NVIC_SetPriority(DISCOVERY_I2Cx_ER_IRQn, 0x0F, 0);\r
+ HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_ER_IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Initializes I2C HAL.\r
+ * @retval None\r
+ */\r
+static void I2Cx_Init(void)\r
+{\r
+ if(HAL_I2C_GetState(&hdiscovery_I2c) == HAL_I2C_STATE_RESET)\r
+ {\r
+ hdiscovery_I2c.Instance = DISCOVERY_I2Cx;\r
+ hdiscovery_I2c.Init.Timing = DISCOVERY_I2Cx_TIMING;\r
+ hdiscovery_I2c.Init.OwnAddress1 = 0x72;\r
+ hdiscovery_I2c.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;\r
+ hdiscovery_I2c.Init.DualAddressMode = I2C_DUALADDRESS_ENABLE;\r
+ hdiscovery_I2c.Init.OwnAddress2 = 0;\r
+ hdiscovery_I2c.Init.OwnAddress2Masks = I2C_OA2_NOMASK;\r
+ hdiscovery_I2c.Init.GeneralCallMode = I2C_GENERALCALL_ENABLE;\r
+ hdiscovery_I2c.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;\r
+ \r
+ /* Init the I2C */\r
+ I2Cx_MspInit();\r
+ HAL_I2C_Init(&hdiscovery_I2c); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes a single data.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Register address \r
+ * @param Value: Data to be written\r
+ * @retval None\r
+ */\r
+static void I2Cx_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ status = HAL_I2C_Mem_Write(&hdiscovery_I2c, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, &Value, 1, 100); \r
+\r
+ /* Check the communication status */\r
+ if(status != HAL_OK)\r
+ {\r
+ /* Execute user timeout callback */\r
+ I2Cx_Error(Addr);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Reads a single data.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Register address \r
+ * @retval Read data\r
+ */\r
+static uint8_t I2Cx_Read(uint8_t Addr, uint8_t Reg)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint8_t Value = 0;\r
+ \r
+ status = HAL_I2C_Mem_Read(&hdiscovery_I2c, Addr, Reg, I2C_MEMADD_SIZE_8BIT, &Value, 1, 1000);\r
+ \r
+ /* Check the communication status */\r
+ if(status != HAL_OK)\r
+ {\r
+ /* Execute user timeout callback */\r
+ I2Cx_Error(Addr);\r
+ }\r
+ return Value; \r
+}\r
+\r
+/**\r
+ * @brief Reads multiple data.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Reg address\r
+ * @param MemAddress: memory address\r
+ * @param Buffer: Pointer to data buffer\r
+ * @param Length: Length of the data\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2Cx_ReadMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ status = HAL_I2C_Mem_Read(&hdiscovery_I2c, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);\r
+\r
+ /* Check the communication status */\r
+ if(status != HAL_OK)\r
+ {\r
+ /* I2C error occurred */\r
+ I2Cx_Error(Addr);\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Writes a value in a register of the device through BUS in using DMA mode.\r
+ * @param Addr: Device address on BUS Bus. \r
+ * @param Reg: The target register address to write\r
+ * @param MemAddress: memory address\r
+ * @param Buffer: The target register value to be written \r
+ * @param Length: buffer size to be written\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2Cx_WriteMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ status = HAL_I2C_Mem_Write(&hdiscovery_I2c, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);\r
+ \r
+ /* Check the communication status */\r
+ if(status != HAL_OK)\r
+ {\r
+ /* Re-Initiaize the I2C Bus */\r
+ I2Cx_Error(Addr);\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Manages error callback by re-initializing I2C.\r
+ * @param Addr: I2C Address\r
+ * @retval None\r
+ */\r
+static void I2Cx_Error(uint8_t Addr)\r
+{\r
+ /* De-initialize the I2C comunication bus */\r
+ HAL_I2C_DeInit(&hdiscovery_I2c);\r
+ \r
+ /* Re-Initialize the I2C communication bus */\r
+ I2Cx_Init();\r
+}\r
+\r
+/*******************************************************************************\r
+ LINK OPERATIONS\r
+*******************************************************************************/\r
+\r
+/********************************* LINK AUDIO *********************************/\r
+\r
+/**\r
+ * @brief Initializes Audio low level.\r
+ * @retval None\r
+ */\r
+void AUDIO_IO_Init(void) \r
+{\r
+ I2Cx_Init();\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes Audio low level.\r
+ * @retval None\r
+ */\r
+void AUDIO_IO_DeInit(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief Writes a single data.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Reg address \r
+ * @param Value: Data to be written\r
+ * @retval None\r
+ */\r
+void AUDIO_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value)\r
+{\r
+ uint16_t tmp = Value;\r
+ \r
+ Value = ((uint16_t)(tmp >> 8) & 0x00FF);\r
+ \r
+ Value |= ((uint16_t)(tmp << 8)& 0xFF00);\r
+ \r
+ I2Cx_WriteMultiple(Addr, Reg, I2C_MEMADD_SIZE_16BIT,(uint8_t*)&Value, 2);\r
+}\r
+\r
+/**\r
+ * @brief Reads a single data.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Reg address \r
+ * @retval Data to be read\r
+ */\r
+uint16_t AUDIO_IO_Read(uint8_t Addr, uint16_t Reg)\r
+{\r
+ uint16_t read_value = 0, tmp = 0;\r
+ \r
+ I2Cx_ReadMultiple(Addr, Reg, I2C_MEMADD_SIZE_16BIT, (uint8_t*)&read_value, 2); \r
+ \r
+ tmp = ((uint16_t)(read_value >> 8) & 0x00FF);\r
+ \r
+ tmp |= ((uint16_t)(read_value << 8)& 0xFF00);\r
+ \r
+ read_value = tmp;\r
+ \r
+ return read_value;\r
+}\r
+\r
+/**\r
+ * @brief AUDIO Codec delay\r
+ * @param Delay: Delay in ms\r
+ * @retval None\r
+ */\r
+void AUDIO_IO_Delay(uint32_t Delay)\r
+{\r
+ HAL_Delay(Delay);\r
+}\r
+\r
+/******************************** LINK TS (TouchScreen) *****************************/\r
+\r
+/**\r
+ * @brief Initialize I2C communication\r
+ * channel from MCU to TouchScreen (TS).\r
+ */\r
+void TS_IO_Init(void)\r
+{\r
+ I2Cx_Init();\r
+}\r
+\r
+/**\r
+ * @brief Writes single data with I2C communication\r
+ * channel from MCU to TouchScreen.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Register address\r
+ * @param Value: Data to be written\r
+ */\r
+void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)\r
+{\r
+ I2Cx_Write(Addr, Reg, Value);\r
+}\r
+\r
+/**\r
+ * @brief Reads single data with I2C communication\r
+ * channel from TouchScreen.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Register address\r
+ * @retval Read data\r
+ */\r
+uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)\r
+{\r
+ return I2Cx_Read(Addr, Reg);\r
+}\r
+\r
+/**\r
+ * @brief Reads multiple data with I2C communication\r
+ * channel from TouchScreen.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Register address\r
+ * @param Buffer: Pointer to data buffer\r
+ * @param Length: Length of the data\r
+ * @retval Number of read data\r
+ */\r
+uint16_t TS_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)\r
+{\r
+ return I2Cx_ReadMultiple(Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);\r
+}\r
+\r
+/**\r
+ * @brief Writes multiple data with I2C communication\r
+ * channel from MCU to TouchScreen.\r
+ * @param Addr: I2C address\r
+ * @param Reg: Register address\r
+ * @param Buffer: Pointer to data buffer\r
+ * @param Length: Length of the data\r
+ * @retval None\r
+ */\r
+void TS_IO_WriteMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)\r
+{\r
+ I2Cx_WriteMultiple(Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);\r
+}\r
+\r
+/**\r
+ * @brief Delay function used in TouchScreen low level driver.\r
+ * @param Delay: Delay in ms\r
+ * @retval None\r
+ */\r
+void TS_IO_Delay(uint32_t Delay)\r
+{\r
+ HAL_Delay(Delay);\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains definitions for STM32H745I-Discovery LEDs,\r
+ * push-buttons hardware resources.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H745I_DISCOVERY_H\r
+#define __STM32H745I_DISCOVERY_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL STM32H745I_DISCOVERY_LOW_LEVEL\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Exported_Types Exported Types\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ LED1 = 0,\r
+ LED_GREEN = LED1,\r
+ LED2 = 1,\r
+ LED_RED = LED2,\r
+} Led_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ BUTTON_WAKEUP = 0,\r
+} Button_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ BUTTON_MODE_GPIO = 0,\r
+ BUTTON_MODE_EXTI = 1\r
+} ButtonMode_TypeDef;\r
+\r
+typedef enum \r
+{\r
+ PB_SET = 0, \r
+ PB_RESET = !PB_SET\r
+} ButtonValue_TypeDef;\r
+\r
+typedef enum\r
+{\r
+ DISCO_OK = 0,\r
+ DISCO_ERROR = 1\r
+} DISCO_Status_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Exported_Constants Exported Constants\r
+ * @{\r
+ */\r
+/** \r
+ * @brief Define for STM32H745I_DISCOVERY board\r
+ */ \r
+#if !defined (USE_STM32H745I_DISCO)\r
+ #define USE_STM32H745I_DISCO\r
+#endif\r
+\r
+#define BUTTON_USER BUTTON_WAKEUP\r
+\r
+#define LEDn ((uint32_t)2)\r
+\r
+#define LED1_GPIO_PORT GPIOJ\r
+#define LED1_PIN GPIO_PIN_2\r
+#define LED2_GPIO_PORT GPIOI\r
+#define LED2_PIN GPIO_PIN_13\r
+#define LEDx_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE();__HAL_RCC_GPIOJ_CLK_ENABLE()\r
+#define LEDx_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE();__HAL_RCC_GPIOJ_CLK_DISABLE()\r
+\r
+/**\r
+ * @brief Definition for LCD Timer used to control the Brightnes\r
+ */\r
+#define LCD_TIMx TIM8\r
+#define LCD_TIMx_CLK_ENABLE() __HAL_RCC_TIM8_CLK_ENABLE()\r
+#define LCD_TIMx_CLK_DISABLE() __HAL_RCC_TIM8_CLK_DISABLE()\r
+#define LCD_TIMx_CHANNEL TIM_CHANNEL_3\r
+#define LCD_TIMx_CHANNEL_AF GPIO_AF3_TIM8\r
+#define LCD_TIMX_PERIOD_VALUE ((uint32_t)50000) /* Period Value */\r
+#define LCD_TIMX_PRESCALER_VALUE ((uint32_t)4) /* Prescaler Value */\r
+\r
+\r
+/* Only one User/Wakeup button */\r
+#define BUTTONn ((uint8_t)1)\r
+\r
+/**\r
+ * @brief Wakeup push-button\r
+ */\r
+#define WAKEUP_BUTTON_PIN GPIO_PIN_13\r
+#define WAKEUP_BUTTON_GPIO_PORT GPIOC\r
+#define WAKEUP_BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()\r
+#define WAKEUP_BUTTON_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()\r
+#define WAKEUP_BUTTON_EXTI_IRQn EXTI15_10_IRQn\r
+\r
+/* Define the USER button as an alias of the Wakeup button */\r
+#define USER_BUTTON_PIN WAKEUP_BUTTON_PIN\r
+#define USER_BUTTON_GPIO_PORT WAKEUP_BUTTON_GPIO_PORT\r
+#define USER_BUTTON_GPIO_CLK_ENABLE() WAKEUP_BUTTON_GPIO_CLK_ENABLE()\r
+#define USER_BUTTON_GPIO_CLK_DISABLE() WAKEUP_BUTTON_GPIO_CLK_DISABLE()\r
+#define USER_BUTTON_EXTI_IRQn WAKEUP_BUTTON_EXTI_IRQn\r
+\r
+#define BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()\r
+\r
+/**\r
+ * @brief TS_INT signal from TouchScreen when it is configured in interrupt mode\r
+ */\r
+#define TS_INT_PIN ((uint32_t)GPIO_PIN_2)\r
+#define TS_INT_GPIO_PORT ((GPIO_TypeDef*)GPIOG)\r
+#define TS_INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()\r
+#define TS_INT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE()\r
+#define TS_INT_EXTI_IRQn EXTI2_IRQn\r
+\r
+/**\r
+ * @brief TouchScreen FT5336 Slave I2C address\r
+ */\r
+#define TS_I2C_ADDRESS ((uint16_t)0x70)\r
+\r
+/**\r
+ * @brief Audio I2C Slave address\r
+ */\r
+#define AUDIO_I2C_ADDRESS ((uint16_t)0x34)\r
+\r
+/**\r
+ * @brief User can use this section to tailor I2C4/I2C4 instance used and associated\r
+ * resources (audio codec).\r
+ * Definition for I2C4 clock resources\r
+ */\r
+#define DISCOVERY_I2Cx I2C4\r
+#define DISCOVERY_I2Cx_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()\r
+#define DISCOVERY_I2Cx_SCL_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()\r
+\r
+#define DISCOVERY_I2Cx_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()\r
+#define DISCOVERY_I2Cx_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()\r
+\r
+/** @brief Definition for I2C4 Pins\r
+ */\r
+#define DISCOVERY_I2Cx_SCL_PIN GPIO_PIN_12 /*!< PD12 */\r
+#define DISCOVERY_I2Cx_SDA_PIN GPIO_PIN_13 /*!< PD13 */\r
+#define DISCOVERY_I2Cx_SCL_SDA_AF GPIO_AF4_I2C4\r
+#define DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT GPIOD\r
+/** @brief Definition of I2C4 interrupt requests\r
+ */\r
+#define DISCOVERY_I2Cx_EV_IRQn I2C4_EV_IRQn\r
+#define DISCOVERY_I2Cx_ER_IRQn I2C4_ER_IRQn\r
+\r
+/* I2C TIMING Register define when I2C clock source is SYSCLK */\r
+/* I2C TIMING is calculated from APB1 source clock = 200 MHz */\r
+/* 0x40912732 takes in account the big rising and aims a clock of 100khz */\r
+#ifndef DISCOVERY_I2Cx_TIMING \r
+#define DISCOVERY_I2Cx_TIMING ((uint32_t)0x40912732)\r
+#endif /* DISCOVERY_I2Cx_TIMING */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Exported_Functions Exported Functions\r
+ * @{\r
+ */\r
+uint32_t BSP_GetVersion(void);\r
+void BSP_LED_Init(Led_TypeDef Led);\r
+void BSP_LED_DeInit(Led_TypeDef Led);\r
+void BSP_LED_On(Led_TypeDef Led);\r
+void BSP_LED_Off(Led_TypeDef Led);\r
+void BSP_LED_Toggle(Led_TypeDef Led);\r
+void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);\r
+void BSP_PB_DeInit(Button_TypeDef Button);\r
+uint32_t BSP_PB_GetState(Button_TypeDef Button);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H745I_DISCOVERY_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_audio.c\r
+ * @author MCD Application Team\r
+ * @brief This file provides the Audio driver for the STM32H745I-DISCOVERY\r
+ * board.\r
+ @verbatim\r
+ How To use this driver:\r
+ -----------------------\r
+ + This driver supports STM32H7xx devices on STM32H745I-DISCOVERY (MB1248) Discovery boards.\r
+ + Call the function BSP_AUDIO_OUT_Init(\r
+ OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER,\r
+ OUTPUT_DEVICE_HEADPHONE or OUTPUT_DEVICE_BOTH)\r
+ Volume : Initial volume to be set (0 is min (mute), 100 is max (100%)\r
+ AudioFreq : Audio frequency in Hz (8000, 16000, 22500, 32000...)\r
+ this parameter is relative to the audio file/stream type.\r
+ )\r
+ This function configures all the hardware required for the audio application (codec, I2C, SAI,\r
+ GPIOs, DMA and interrupt if needed). This function returns AUDIO_OK if configuration is OK.\r
+ If the returned value is different from AUDIO_OK or the function is stuck then the communication with\r
+ the codec has failed (try to un-plug the power or reset device in this case).\r
+ - OUTPUT_DEVICE_SPEAKER : only speaker will be set as output for the audio stream.\r
+ - OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream.\r
+ - OUTPUT_DEVICE_BOTH : both Speaker and Headphone are used as outputs for the audio stream\r
+ at the same time.\r
+ Note. On STM32H745I-DISCOVERY SAI_DMA is configured in CIRCULAR mode. Due to this the application\r
+ does NOT need to call BSP_AUDIO_OUT_ChangeBuffer() to assure streaming.\r
+ + Call the function BSP_AUDIO_OUT_Play(\r
+ pBuffer: pointer to the audio data file address\r
+ Size : size of the buffer to be sent in Bytes\r
+ )\r
+ to start playing (for the first time) from the audio file/stream.\r
+ + Call the function BSP_AUDIO_OUT_Pause() to pause playing\r
+ + Call the function BSP_AUDIO_OUT_Resume() to resume playing.\r
+ Note. After calling BSP_AUDIO_OUT_Pause() function for pause, only BSP_AUDIO_OUT_Resume() should be called\r
+ for resume (it is not allowed to call BSP_AUDIO_OUT_Play() in this case).\r
+ Note. This function should be called only when the audio file is played or paused (not stopped).\r
+ + For each mode, you may need to implement the relative callback functions into your code.\r
+ The Callback functions are named BSP_AUDIO_OUT_XXX_CallBack() and only their prototypes are declared in\r
+ the stm32h745i_discovery_audio.h file. (refer to the example for more details on the callbacks implementations)\r
+ + To Stop playing, to modify the volume level, the frequency, the audio frame slot,\r
+ the device output mode the mute or the stop, use the functions: BSP_AUDIO_OUT_SetVolume(),\r
+ AUDIO_OUT_SetFrequency(), BSP_AUDIO_OUT_SetAudioFrameSlot(), BSP_AUDIO_OUT_SetOutputMode(),\r
+ BSP_AUDIO_OUT_SetMute() and BSP_AUDIO_OUT_Stop().\r
+\r
+ + Call the function BSP_AUDIO_IN_Init(\r
+ AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000...)\r
+ this parameter is relative to the audio file/stream type.\r
+ BitRes: Bit resolution fixed to 16bit\r
+ ChnlNbr: Number of channel to be configured for the DFSDM peripheral\r
+ )\r
+ This function configures all the hardware required for the audio in application (channels,\r
+ Clock source for SAI PDM periphiral, GPIOs, DMA and interrupt if needed).\r
+ This function returns AUDIO_OK if configuration is OK.If the returned value is different from AUDIO_OK then\r
+ the configuration should be wrong.\r
+ + Call the function BSP_AUDIO_IN_AllocScratch(\r
+ pScratch: pointer to scratch tables\r
+ size: size of scratch buffer)\r
+ This function must be called before BSP_AUDIO_IN_RECORD() to allocate buffer scratch for each DFSDM channel\r
+ and its size.\r
+ Note: These buffers scratch are used as intermidiate buffers to collect data within final record buffer.\r
+ size is the total size of the four buffers scratch; If size is 512 then the size of each is 128.\r
+ This function must be called after BSP_AUDIO_IN_Init()\r
+ + Call the function BSP_AUDIO_IN_RECORD(\r
+ pBuf: pointer to the recorded audio data file address\r
+ Size: size of the buffer to be written in Bytes\r
+ )\r
+ to start recording from microphones.\r
+\r
+ + Call the function BSP_AUDIO_IN_Pause() to pause recording\r
+ + Call the function BSP_AUDIO_IN_Resume() to recording playing.\r
+ Note. After calling BSP_AUDIO_IN_Pause() function for pause, only BSP_AUDIO_IN_Resume() should be called\r
+ for resume (it is not allowed to call BSP_AUDIO_IN_RECORD() in this case).\r
+ + Call the function BSP_AUDIO_IN_Stop() to stop recording\r
+ + For each mode, you may need to implement the relative callback functions into your code.\r
+ The Callback functions are named BSP_AUDIO_IN_XXX_CallBack() and only their prototypes are declared in\r
+ the stm32h745i_discovery_audio.h file. (refer to the example for more details on the callbacks implementations)\r
+ + Call the function BSP_AUDIO_IN_SelectInterface(uint32_t Interface) to select one of the two interfaces\r
+ available on the STM32H745I-Discovery board: SAI or PDM. This function is to be called before BSP_AUDIO_IN_InitEx().\r
+ + Call the function BSP_AUDIO_IN_GetInterface() to get the current used interface.\r
+ + Call the function BSP_AUDIO_IN_PDMToPCM_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut)\r
+ to init PDM filters if the libPDMFilter is used for audio data filtering.\r
+ + Call the function BSP_AUDIO_IN_PDMToPCM(uint16_t* PDMBuf, uint16_t* PCMBuf) to filter PDM data to PCM format\r
+ if the libPDMFilter library is used for audio data filtering.\r
+\r
+ Driver architecture:\r
+ --------------------\r
+ + This driver provides the High Audio Layer: consists of the function API exported in the stm32h745i_discovery_audio.h file\r
+ (BSP_AUDIO_OUT_Init(), BSP_AUDIO_OUT_Play() ...)\r
+ + This driver provide also the Media Access Layer (MAL): which consists of functions allowing to access the media containing/\r
+ providing the audio file/stream. These functions are also included as local functions into\r
+ the stm32h745i_discovery_audio.c file (DFSDMx_Init(), DFSDMx_DeInit(), SAIx_Init() and SAIx_DeInit())\r
+\r
+ Known Limitations:\r
+ ------------------\r
+ 1- If the TDM Format used to play in parallel 2 audio Stream (the first Stream is configured in codec SLOT0 and second\r
+ Stream in SLOT1) the Pause/Resume, volume and mute feature will control the both streams.\r
+ 2- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size,\r
+ File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file.\r
+ 3- Supports only Stereo audio streaming.\r
+ 4- Supports only 16-bits audio data size.\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery_audio.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO STM32H745I_DISCOVERY_AUDIO\r
+ * @brief This file includes the low layer driver for wm8994 Audio Codec\r
+ * available on STM32H745I-DISCOVERY discovery board(MB1248).\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_Private_Variables Private Variables\r
+ * @{\r
+ */\r
+/* PLAY */\r
+AUDIO_DrvTypeDef *audio_drv;\r
+SAI_HandleTypeDef haudio_out_sai;\r
+SAI_HandleTypeDef haudio_in_sai;\r
+\r
+/* RECORD */\r
+AUDIOIN_ContextTypeDef hAudioIn;\r
+\r
+/* Audio in Volume value */\r
+__IO uint16_t AudioInVolume = DEFAULT_AUDIO_IN_VOLUME;\r
+\r
+/* PDM filters params */\r
+PDM_Filter_Handler_t PDM_FilterHandler[2];\r
+PDM_Filter_Config_t PDM_FilterConfig[2];\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_Private_Function_Prototypes OUT Private Function Prototypes\r
+ * @{\r
+ */\r
+static void SAIx_Out_Init(uint32_t SaiOutMode, uint32_t SlotActive, uint32_t AudioFreq);\r
+static void SAIx_Out_DeInit(SAI_HandleTypeDef *hsai);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_IN_Private_Function_Prototypes IN Private Function Prototypes\r
+ * @{\r
+ */\r
+static void SAIx_In_MspInit(SAI_HandleTypeDef *hsai, void *Params);\r
+static void SAIx_In_MspDeInit(SAI_HandleTypeDef *hsai, void *Params);\r
+static void SAIx_In_Init(uint32_t SaiInMode, uint32_t SlotActive, uint32_t AudioFreq);\r
+static void SAIx_In_DeInit(SAI_HandleTypeDef *hsai);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_OUT_Exported_Functions OUT Exported Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the audio Out peripheral.\r
+ * @param OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,\r
+ * or OUTPUT_DEVICE_BOTH.\r
+ * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))\r
+ * @param AudioFreq: Audio frequency used to play the audio stream.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)\r
+{\r
+ uint8_t ret = AUDIO_ERROR;\r
+ uint32_t deviceid = 0x00;\r
+ uint32_t slot_active;\r
+\r
+ /* Initialize SAI2 sub_block A as MASTER TX */\r
+ haudio_out_sai.Instance = AUDIO_OUT_SAIx;\r
+\r
+ /* Disable SAI */\r
+ SAIx_Out_DeInit(&haudio_out_sai);\r
+\r
+ /* PLL clock is set depending by the AudioFreq (44.1khz vs 48khz groups) */\r
+ BSP_AUDIO_OUT_ClockConfig(&haudio_out_sai, AudioFreq, NULL);\r
+\r
+ /* SAI data transfer preparation:\r
+ Prepare the Media to be used for the audio transfer from memory to SAI peripheral */\r
+\r
+ if(HAL_SAI_GetState(&haudio_out_sai) == HAL_SAI_STATE_RESET)\r
+ {\r
+ /* Init the SAI MSP: this __weak function can be redefined by the application*/\r
+ BSP_AUDIO_OUT_MspInit(&haudio_out_sai, NULL);\r
+ }\r
+\r
+ /* Init SAI as master RX output */\r
+ slot_active = CODEC_AUDIOFRAME_SLOT_0123;\r
+ SAIx_Out_Init(SAI_MODEMASTER_TX, slot_active, AudioFreq);\r
+\r
+ /* wm8994 codec initialization */\r
+ deviceid = wm8994_drv.ReadID(AUDIO_I2C_ADDRESS);\r
+\r
+ if((deviceid) == WM8994_ID)\r
+ {\r
+ /* Reset the Codec Registers */\r
+ wm8994_drv.Reset(AUDIO_I2C_ADDRESS);\r
+ /* Initialize the audio driver structure */\r
+ audio_drv = &wm8994_drv;\r
+ ret = AUDIO_OK;\r
+ }\r
+ else\r
+ {\r
+ ret = AUDIO_ERROR;\r
+ }\r
+\r
+ if(ret == AUDIO_OK)\r
+ {\r
+ /* Initialize the codec internal registers */\r
+ audio_drv->Init(AUDIO_I2C_ADDRESS, OutputDevice, Volume, AudioFreq);\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Starts playing audio stream from a data buffer for a determined size.\r
+ * @param pBuffer: Pointer to the buffer\r
+ * @param Size: Number of audio data BYTES.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_Play(uint16_t* pBuffer, uint32_t Size)\r
+{\r
+ /* Call the audio Codec Play function */\r
+ if(audio_drv->Play(AUDIO_I2C_ADDRESS, pBuffer, Size) != 0)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Update the Media layer and enable it for play */\r
+ HAL_SAI_Transmit_DMA(&haudio_out_sai, (uint8_t*) pBuffer, DMA_MAX(Size / AUDIODATA_SIZE));\r
+\r
+ return AUDIO_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sends n-Bytes on the SAI interface.\r
+ * @param pData: pointer on data address\r
+ * @param Size: number of data to be written\r
+ * @retval None\r
+ */\r
+void BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size)\r
+{\r
+ HAL_SAI_Transmit_DMA(&haudio_out_sai, (uint8_t*) pData, Size);\r
+}\r
+\r
+/**\r
+ * @brief This function Pauses the audio file stream. In case\r
+ * of using DMA, the DMA Pause feature is used.\r
+ * @warning When calling BSP_AUDIO_OUT_Pause() function for pause, only\r
+ * BSP_AUDIO_OUT_Resume() function should be called for resume (use of BSP_AUDIO_OUT_Play()\r
+ * function for resume could lead to unexpected behaviour).\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_Pause(void)\r
+{\r
+ /* Call the Audio Codec Pause/Resume function */\r
+ if(audio_drv->Pause(AUDIO_I2C_ADDRESS) != 0)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Call the Media layer pause function */\r
+ HAL_SAI_DMAPause(&haudio_out_sai);\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Resumes the audio file stream.\r
+ * @warning When calling BSP_AUDIO_OUT_Pause() function for pause, only\r
+ * BSP_AUDIO_OUT_Resume() function should be called for resume (use of BSP_AUDIO_OUT_Play()\r
+ * function for resume could lead to unexpected behaviour).\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_Resume(void)\r
+{\r
+ /* Call the Audio Codec Pause/Resume function */\r
+ if(audio_drv->Resume(AUDIO_I2C_ADDRESS) != 0)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Call the Media layer pause/resume function */\r
+ HAL_SAI_DMAResume(&haudio_out_sai);\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Stops audio playing and Power down the Audio Codec.\r
+ * @param Option: could be one of the following parameters\r
+ * - CODEC_PDWN_SW: for software power off (by writing registers).\r
+ * Then no need to reconfigure the Codec after power on.\r
+ * - CODEC_PDWN_HW: completely shut down the codec (physically).\r
+ * Then need to reconfigure the Codec after power on.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option)\r
+{\r
+ /* Call the Media layer stop function */\r
+ HAL_SAI_DMAStop(&haudio_out_sai);\r
+\r
+ /* Call Audio Codec Stop function */\r
+ if(audio_drv->Stop(AUDIO_I2C_ADDRESS, Option) != 0)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ if(Option == CODEC_PDWN_HW)\r
+ {\r
+ /* Wait at least 100us */\r
+ HAL_Delay(1);\r
+ }\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Controls the current audio volume level.\r
+ * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for\r
+ * Mute and 100 for Max volume level).\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume)\r
+{\r
+ /* Call the codec volume control function with converted volume value */\r
+ if(audio_drv->SetVolume(AUDIO_I2C_ADDRESS, Volume) != 0)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MUTE mode by software\r
+ * @param Cmd: Could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to\r
+ * unmute the codec and restore previous volume level.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd)\r
+{\r
+ /* Call the Codec Mute function */\r
+ if(audio_drv->SetMute(AUDIO_I2C_ADDRESS, Cmd) != 0)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Switch dynamically (while audio file is played) the output target\r
+ * (speaker or headphone).\r
+ * @param Output: The audio output target: OUTPUT_DEVICE_SPEAKER,\r
+ * OUTPUT_DEVICE_HEADPHONE or OUTPUT_DEVICE_BOTH\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output)\r
+{\r
+ /* Call the Codec output device function */\r
+ if(audio_drv->SetOutputMode(AUDIO_I2C_ADDRESS, Output) != 0)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Updates the audio frequency.\r
+ * @param AudioFreq: Audio frequency used to play the audio stream.\r
+ * @note This API should be called after the BSP_AUDIO_OUT_Init() to adjust the\r
+ * audio frequency.\r
+ * @retval None\r
+ */\r
+void BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq)\r
+{\r
+ /* PLL clock is set depending by the AudioFreq (44.1khz vs 48khz groups) */\r
+ BSP_AUDIO_OUT_ClockConfig(&haudio_out_sai, AudioFreq, NULL);\r
+\r
+ /* Disable SAI peripheral to allow access to SAI internal registers */\r
+ __HAL_SAI_DISABLE(&haudio_out_sai);\r
+\r
+ /* Update the SAI audio frequency configuration */\r
+ haudio_out_sai.Init.AudioFrequency = AudioFreq;\r
+ HAL_SAI_Init(&haudio_out_sai);\r
+\r
+ /* Enable SAI peripheral to generate MCLK */\r
+ __HAL_SAI_ENABLE(&haudio_out_sai);\r
+}\r
+\r
+/**\r
+ * @brief Updates the Audio frame slot configuration.\r
+ * @param AudioFrameSlot: specifies the audio Frame slot\r
+ * @note This API should be called after the BSP_AUDIO_OUT_Init() to adjust the\r
+ * audio frame slot.\r
+ * @retval None\r
+ */\r
+void BSP_AUDIO_OUT_SetAudioFrameSlot(uint32_t AudioFrameSlot)\r
+{\r
+ /* Disable SAI peripheral to allow access to SAI internal registers */\r
+ __HAL_SAI_DISABLE(&haudio_out_sai);\r
+\r
+ /* Update the SAI audio frame slot configuration */\r
+ haudio_out_sai.SlotInit.SlotActive = AudioFrameSlot;\r
+ HAL_SAI_Init(&haudio_out_sai);\r
+\r
+ /* Enable SAI peripheral to generate MCLK */\r
+ __HAL_SAI_ENABLE(&haudio_out_sai);\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the audio out peripheral.\r
+ * @retval None\r
+ */\r
+void BSP_AUDIO_OUT_DeInit(void)\r
+{\r
+ SAIx_Out_DeInit(&haudio_out_sai);\r
+ /* DeInit the SAI MSP : this __weak function can be rewritten by the application */\r
+ BSP_AUDIO_OUT_MspDeInit(&haudio_out_sai, NULL);\r
+}\r
+\r
+/**\r
+ * @brief Manages the DMA full Transfer complete event.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_OUT_TransferComplete_CallBack(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief Manages the DMA Half Transfer complete event.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_OUT_HalfTransfer_CallBack(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief Manages the DMA FIFO error event.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_OUT_Error_CallBack(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief Initializes BSP_AUDIO_OUT MSP.\r
+ * @param hsai: SAI handle\r
+ * @param Params: pointer on additional configuration parameters, can be NULL.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_OUT_MspInit(SAI_HandleTypeDef *hsai, void *Params)\r
+{\r
+ static DMA_HandleTypeDef hdma_sai_tx;\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ /* Enable SAI clock */\r
+ AUDIO_OUT_SAIx_CLK_ENABLE();\r
+\r
+ /* CODEC_SAI pins configuration: FS, SCK and SD pins */\r
+ /* Enable FS, SCK and SD clocks */\r
+ AUDIO_OUT_SAIx_SD_FS_CLK_ENABLE();\r
+ /* Enable FS, SCK and SD pins */\r
+ gpio_init_structure.Pin = AUDIO_OUT_SAIx_FS_PIN | AUDIO_OUT_SAIx_SCK_PIN | AUDIO_OUT_SAIx_SD_PIN;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ gpio_init_structure.Alternate = AUDIO_OUT_SAIx_AF;\r
+ HAL_GPIO_Init(AUDIO_OUT_SAIx_SD_FS_SCK_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* Enable MCLK clock */\r
+ AUDIO_OUT_SAIx_MCLK_ENABLE();\r
+ /* Enable MCLK pin */\r
+ gpio_init_structure.Pin = AUDIO_OUT_SAIx_MCLK_PIN;\r
+ HAL_GPIO_Init(AUDIO_OUT_SAIx_MCLK_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* Enable the DMA clock */\r
+ AUDIO_OUT_SAIx_DMAx_CLK_ENABLE();\r
+\r
+ if(hsai->Instance == AUDIO_OUT_SAIx)\r
+ {\r
+ /* Configure the hdma_saiTx handle parameters */\r
+ hdma_sai_tx.Init.Request = AUDIO_OUT_SAIx_DMAx_REQUEST;\r
+ hdma_sai_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;\r
+ hdma_sai_tx.Init.PeriphInc = DMA_PINC_DISABLE;\r
+ hdma_sai_tx.Init.MemInc = DMA_MINC_ENABLE;\r
+ hdma_sai_tx.Init.PeriphDataAlignment = AUDIO_OUT_SAIx_DMAx_PERIPH_DATA_SIZE;\r
+ hdma_sai_tx.Init.MemDataAlignment = AUDIO_OUT_SAIx_DMAx_MEM_DATA_SIZE;\r
+ hdma_sai_tx.Init.Mode = DMA_CIRCULAR;\r
+ hdma_sai_tx.Init.Priority = DMA_PRIORITY_HIGH;\r
+ hdma_sai_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;\r
+ hdma_sai_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;\r
+ hdma_sai_tx.Init.MemBurst = DMA_MBURST_SINGLE;\r
+ hdma_sai_tx.Init.PeriphBurst = DMA_PBURST_SINGLE;\r
+\r
+ hdma_sai_tx.Instance = AUDIO_OUT_SAIx_DMAx_STREAM;\r
+\r
+ /* Associate the DMA handle */\r
+ __HAL_LINKDMA(hsai, hdmatx, hdma_sai_tx);\r
+\r
+ /* Deinitialize the Stream for new transfer */\r
+ HAL_DMA_DeInit(&hdma_sai_tx);\r
+\r
+ /* Configure the DMA Stream */\r
+ HAL_DMA_Init(&hdma_sai_tx);\r
+ }\r
+\r
+ /* SAI DMA IRQ Channel configuration */\r
+ HAL_NVIC_SetPriority(AUDIO_OUT_SAIx_DMAx_IRQ, AUDIO_OUT_IRQ_PREPRIO, 0);\r
+ HAL_NVIC_EnableIRQ(AUDIO_OUT_SAIx_DMAx_IRQ);\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes SAI MSP.\r
+ * @param hsai: SAI handle\r
+ * @param Params: pointer on additional configuration parameters, can be NULL.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_OUT_MspDeInit(SAI_HandleTypeDef *hsai, void *Params)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ /* SAI DMA IRQ Channel deactivation */\r
+ HAL_NVIC_DisableIRQ(AUDIO_OUT_SAIx_DMAx_IRQ);\r
+\r
+ if(hsai->Instance == AUDIO_OUT_SAIx)\r
+ {\r
+ /* Deinitialize the DMA stream */\r
+ HAL_DMA_DeInit(hsai->hdmatx);\r
+ }\r
+\r
+ /* Disable SAI peripheral */\r
+ __HAL_SAI_DISABLE(hsai);\r
+\r
+ /* Deactivates CODEC_SAI pins FS, SCK, MCK and SD by putting them in input mode */\r
+ gpio_init_structure.Pin = AUDIO_OUT_SAIx_FS_PIN | AUDIO_OUT_SAIx_SCK_PIN | AUDIO_OUT_SAIx_SD_PIN;\r
+ HAL_GPIO_DeInit(AUDIO_OUT_SAIx_SD_FS_SCK_GPIO_PORT, gpio_init_structure.Pin);\r
+\r
+ gpio_init_structure.Pin = AUDIO_OUT_SAIx_MCLK_PIN;\r
+ HAL_GPIO_DeInit(AUDIO_OUT_SAIx_MCLK_GPIO_PORT, gpio_init_structure.Pin);\r
+\r
+ /* Disable SAI clock */\r
+ AUDIO_OUT_SAIx_CLK_DISABLE();\r
+\r
+ /* GPIO pins clock and DMA clock can be shut down in the applic\r
+ by surcharging this __weak function */\r
+}\r
+\r
+/**\r
+ * @brief Clock Config.\r
+ * @param hsai: might be required to set audio peripheral predivider if any.\r
+ * @param AudioFreq: Audio frequency used to play the audio stream.\r
+ * @param Params: pointer on additional configuration parameters, can be NULL.\r
+ * @note This API is called by BSP_AUDIO_OUT_Init() and BSP_AUDIO_OUT_SetFrequency()\r
+ * Being __weak it can be overwritten by the application\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_OUT_ClockConfig(SAI_HandleTypeDef *hsai, uint32_t AudioFreq, void *Params)\r
+{\r
+ RCC_PeriphCLKInitTypeDef rcc_ex_clk_init_struct;\r
+\r
+ HAL_RCCEx_GetPeriphCLKConfig(&rcc_ex_clk_init_struct);\r
+\r
+ /* Set the PLL configuration according to the audio frequency */\r
+ if((AudioFreq == AUDIO_FREQUENCY_11K) || (AudioFreq == AUDIO_FREQUENCY_22K) || (AudioFreq == AUDIO_FREQUENCY_44K))\r
+ {\r
+ /* SAI clock config:\r
+ PLL2_VCO Input = HSE_VALUE/PLL2M = 1 Mhz\r
+ PLL2_VCO Output = PLL2_VCO Input * PLL2N = 429 Mhz\r
+ SAI_CLK_x = PLL2_VCO Output/PLL2P = 429/38 = 11.289 Mhz */\r
+ rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI2;\r
+ rcc_ex_clk_init_struct.Sai23ClockSelection = RCC_SAI2CLKSOURCE_PLL2;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2P = 38;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2Q = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2R = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2N = 429;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2M = 25;\r
+ HAL_RCCEx_PeriphCLKConfig(&rcc_ex_clk_init_struct);\r
+ }\r
+ else /* AUDIO_FREQUENCY_8K, AUDIO_FREQUENCY_16K, AUDIO_FREQUENCY_48K, AUDIO_FREQUENCY_96K */\r
+ {\r
+ /* SAI clock config:\r
+ PLL2_VCO Input = HSE_VALUE/PLL2M = 1 Mhz\r
+ PLL2_VCO Output = PLL2_VCO Input * PLL2N = 344 Mhz\r
+ SAI_CLK_x = PLL2_VCO Output/PLL2P = 344/7 = 49.142 Mhz */\r
+ rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI2;\r
+ rcc_ex_clk_init_struct.Sai23ClockSelection = RCC_SAI2CLKSOURCE_PLL2;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2P = 7;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2Q = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2R = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2N = 344;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2M = 25;\r
+ HAL_RCCEx_PeriphCLKConfig(&rcc_ex_clk_init_struct);\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_OUT_Private_Functions OUT Private Functions\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ HAL Callbacks\r
+*******************************************************************************/\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param hsai: SAI handle\r
+ * @retval None\r
+ */\r
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Manage the remaining file size and new address offset: This function\r
+ should be coded by user (its prototype is already declared in stm32h745i_discovery_audio.h) */\r
+ BSP_AUDIO_OUT_TransferComplete_CallBack();\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param hsai: SAI handle\r
+ * @retval None\r
+ */\r
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Manage the remaining file size and new address offset: This function\r
+ should be coded by user (its prototype is already declared in stm32h745i_discovery_audio.h) */\r
+ BSP_AUDIO_OUT_HalfTransfer_CallBack();\r
+}\r
+\r
+/**\r
+ * @brief SAI error callbacks.\r
+ * @param hsai: SAI handle\r
+ * @retval None\r
+ */\r
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->Instance == AUDIO_OUT_SAIx)\r
+ {\r
+ BSP_AUDIO_OUT_Error_CallBack();\r
+ }\r
+ else\r
+ {\r
+ BSP_AUDIO_IN_Error_CallBack();\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+ Static Functions\r
+*******************************************************************************/\r
+\r
+/**\r
+ * @brief Initializes the Audio Codec audio interface (SAI).\r
+ * @param SaiOutMode: Audio mode to be configured for the SAI peripheral.\r
+ * @param SlotActive: Audio active slot to be configured for the SAI peripheral.\r
+ * @param AudioFreq: Audio frequency to be configured for the SAI peripheral.\r
+ * @note The default SlotActive configuration is set to CODEC_AUDIOFRAME_SLOT_0123\r
+ * and user can update this configuration using\r
+ * @retval None\r
+ */\r
+static void SAIx_Out_Init(uint32_t SaiOutMode, uint32_t SlotActive, uint32_t AudioFreq)\r
+{\r
+ /* Disable SAI peripheral to allow access to SAI internal registers */\r
+ __HAL_SAI_DISABLE(&haudio_out_sai);\r
+\r
+ /* Configure SAI_Block_x\r
+ LSBFirst: Disabled\r
+ DataSize: 16 */\r
+ haudio_out_sai.Init.MonoStereoMode = SAI_STEREOMODE;\r
+ haudio_out_sai.Init.AudioFrequency = AudioFreq;\r
+ haudio_out_sai.Init.AudioMode = SaiOutMode;\r
+ haudio_out_sai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;\r
+ haudio_out_sai.Init.Protocol = SAI_FREE_PROTOCOL;\r
+ haudio_out_sai.Init.DataSize = SAI_DATASIZE_16;\r
+ haudio_out_sai.Init.FirstBit = SAI_FIRSTBIT_MSB;\r
+ haudio_out_sai.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;\r
+ haudio_out_sai.Init.Synchro = SAI_ASYNCHRONOUS;\r
+ haudio_out_sai.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE;\r
+ haudio_out_sai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF;\r
+ haudio_out_sai.Init.SynchroExt = SAI_SYNCEXT_DISABLE;\r
+ haudio_out_sai.Init.CompandingMode = SAI_NOCOMPANDING;\r
+ haudio_out_sai.Init.TriState = SAI_OUTPUT_NOTRELEASED;\r
+ haudio_out_sai.Init.Mckdiv = 0;\r
+ haudio_out_sai.Init.MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE;\r
+ haudio_out_sai.Init.PdmInit.Activation = DISABLE;\r
+ haudio_out_sai.Init.PdmInit.ClockEnable = 0;\r
+ haudio_out_sai.Init.PdmInit.MicPairsNbr = 0;\r
+\r
+ /* Configure SAI_Block_x Frame\r
+ Frame Length: 64\r
+ Frame active Length: 32\r
+ FS Definition: Start frame + Channel Side identification\r
+ FS Polarity: FS active Low\r
+ FS Offset: FS asserted one bit before the first bit of slot 0 */\r
+ haudio_out_sai.FrameInit.FrameLength = 128;\r
+ haudio_out_sai.FrameInit.ActiveFrameLength = 64;\r
+ haudio_out_sai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;\r
+ haudio_out_sai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;\r
+ haudio_out_sai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;\r
+\r
+ /* Configure SAI Block_x Slot\r
+ Slot First Bit Offset: 0\r
+ Slot Size : 16\r
+ Slot Number: 4\r
+ Slot Active: All slot actives */\r
+ haudio_out_sai.SlotInit.FirstBitOffset = 0;\r
+ haudio_out_sai.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;\r
+ haudio_out_sai.SlotInit.SlotNumber = 4;\r
+ haudio_out_sai.SlotInit.SlotActive = SlotActive;\r
+ HAL_SAI_Init(&haudio_out_sai);\r
+\r
+ /* Enable SAI peripheral to generate MCLK */\r
+ __HAL_SAI_ENABLE(&haudio_out_sai);\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the Audio Codec audio interface (SAI).\r
+ * @retval None\r
+ */\r
+static void SAIx_Out_DeInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Disable SAI peripheral */\r
+ __HAL_SAI_DISABLE(hsai);\r
+\r
+ HAL_SAI_DeInit(hsai);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_IN_Exported_Functions IN Exported Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize wave recording.\r
+ * @param AudioFreq: Audio frequency to be configured for the DFSDM peripheral.\r
+ * @param BitRes: Audio frequency to be configured for the DFSDM peripheral.\r
+ * @param ChnlNbr: Audio frequency to be configured for the DFSDM peripheral.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr)\r
+{\r
+ /* Set audio in interface to default one */\r
+ BSP_AUDIO_IN_SelectInterface(AUDIO_IN_INTERFACE_PDM);\r
+ return BSP_AUDIO_IN_InitEx(INPUT_DEVICE_DIGITAL_MIC, AudioFreq, BitRes, ChnlNbr);\r
+}\r
+\r
+/**\r
+ * @brief Initialize wave recording.\r
+ * @param InputDevice: INPUT_DEVICE_DIGITAL_MIC or INPUT_DEVICE_ANALOG_MIC.\r
+ * @param AudioFreq: Audio frequency to be configured.\r
+ * @param BitRes: Audio bit resolution to be configured..\r
+ * @param ChnlNbr: Number of channel to be configured.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_InitEx(uint16_t InputDevice, uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr)\r
+{\r
+ uint8_t ret = AUDIO_OK;\r
+ uint32_t slot_active;\r
+\r
+ /* Store the audio record context */\r
+ hAudioIn.Frequency = AudioFreq;\r
+ hAudioIn.BitResolution = BitRes;\r
+ hAudioIn.InputDevice = InputDevice;\r
+ hAudioIn.ChannelNbr = ChnlNbr;\r
+\r
+ if(hAudioIn.InputDevice == INPUT_DEVICE_DIGITAL_MIC)\r
+ {\r
+ if(hAudioIn.Interface == AUDIO_IN_INTERFACE_SAI)\r
+ {\r
+ /* Initialize SAI2 block B as SLAVE RX synchrounous with SAI2 block A */\r
+ haudio_in_sai.Instance = AUDIO_IN_SAIx;\r
+\r
+ /* Disable SAI */\r
+ SAIx_In_DeInit(&haudio_in_sai);\r
+\r
+ /* PLL clock is set depending on the AudioFreq (44.1khz vs 48khz groups) */\r
+ BSP_AUDIO_IN_ClockConfig(AudioFreq, NULL); /* Clock config is shared between AUDIO IN and OUT */\r
+\r
+ /* SAI data transfer preparation:\r
+ Prepare the Media to be used for the audio transfer from SAI peripheral to memory */\r
+ if(HAL_SAI_GetState(&haudio_in_sai) == HAL_SAI_STATE_RESET)\r
+ {\r
+ /* Init the SAI MSP: this __weak function can be redefined by the application*/\r
+ BSP_AUDIO_IN_MspInit();\r
+ }\r
+\r
+ /* Configure SAI in master mode :\r
+ * - SAI2_block_B in slave RX mode synchronous from SAI2_block_A\r
+ */\r
+ slot_active = CODEC_AUDIOFRAME_SLOT_13;\r
+ SAIx_In_Init(SAI_MODESLAVE_RX, slot_active, AudioFreq);\r
+ }\r
+ else if(hAudioIn.Interface == AUDIO_IN_INTERFACE_PDM)\r
+ {\r
+ /* Initialize SAI2 block A as MASTER RX */\r
+ haudio_in_sai.Instance = AUDIO_IN_SAI_PDMx;\r
+\r
+ /* Disable SAI */\r
+ SAIx_In_DeInit(&haudio_in_sai);\r
+\r
+ /* PLL clock is set depending on the AudioFreq (44.1khz vs 48khz groups) */\r
+ BSP_AUDIO_IN_ClockConfig(AudioFreq, NULL);\r
+\r
+ /* SAI data transfer preparation:\r
+ Prepare the Media to be used for the audio transfer from SAI peripheral to memory */\r
+ /* Initialize the haudio_in_sai Instance parameter */\r
+\r
+ if(HAL_SAI_GetState(&haudio_in_sai) == HAL_SAI_STATE_RESET)\r
+ {\r
+ /* Init the SAI MSP: this __weak function can be redefined by the application*/\r
+ BSP_AUDIO_IN_MspInit();\r
+ }\r
+\r
+ /* Configure SAI in master mode :\r
+ * - SAI4_block_A in master RX mode\r
+ */\r
+ slot_active = CODEC_AUDIOFRAME_SLOT_1;\r
+ SAIx_In_Init(SAI_MODEMASTER_RX, slot_active, AudioFreq);\r
+\r
+ if(BSP_AUDIO_IN_PDMToPCM_Init(AudioFreq, hAudioIn.ChannelNbr, hAudioIn.ChannelNbr) != AUDIO_OK)\r
+ {\r
+ ret = AUDIO_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ret = AUDIO_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Analog Input */\r
+ ret = AUDIO_ERROR;\r
+ }\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Initializes wave recording and playback in parallel.\r
+ * @param InputDevice: INPUT_DEVICE_DIGITAL_MICROPHONE_2\r
+ * @param OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,\r
+ * or OUTPUT_DEVICE_BOTH.\r
+ * @param AudioFreq: Audio frequency to be configured for the SAI peripheral.\r
+ * @param BitRes: Audio frequency to be configured.\r
+ * @param ChnlNbr: Channel number.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_OUT_Init(uint32_t InputDevice, uint32_t OutputDevice, uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr)\r
+{\r
+ uint32_t slot_active;\r
+ uint32_t deviceid = 0, ret = AUDIO_OK;\r
+\r
+ /* Store the audio record context */\r
+ hAudioIn.Frequency = AudioFreq;\r
+ hAudioIn.BitResolution = BitRes;\r
+ hAudioIn.InputDevice = InputDevice;\r
+ hAudioIn.ChannelNbr = ChnlNbr;\r
+\r
+ /* Input device is Digital MIC2 and Codec interface is SAI */\r
+ if (hAudioIn.InputDevice == INPUT_DEVICE_DIGITAL_MICROPHONE_2)\r
+ {\r
+ haudio_in_sai.Instance = AUDIO_IN_SAIx;\r
+ haudio_out_sai.Instance = AUDIO_OUT_SAIx;\r
+\r
+ /* PLL clock is set depending on the AudioFreq (44.1khz vs 48khz groups) */\r
+ BSP_AUDIO_OUT_ClockConfig(&haudio_in_sai, AudioFreq, NULL);\r
+ /* SAI data transfer preparation:\r
+ Prepare the Media to be used for the audio transfer from SAI peripheral to memory */\r
+ if(HAL_SAI_GetState(&haudio_in_sai) == HAL_SAI_STATE_RESET)\r
+ {\r
+ /* Init the SAI MSP: this __weak function can be redefined by the application*/\r
+ BSP_AUDIO_IN_MspInit();\r
+ }\r
+\r
+ /* SAI data transfer preparation:\r
+ Prepare the Media to be used for the audio transfer from memory to SAI peripheral */\r
+ if(HAL_SAI_GetState(&haudio_out_sai) == HAL_SAI_STATE_RESET)\r
+ {\r
+ /* Init the SAI MSP: this __weak function can be redefined by the application*/\r
+ BSP_AUDIO_OUT_MspInit(&haudio_out_sai, NULL);\r
+ }\r
+\r
+ /* Configure SAI in master TX mode :\r
+ * - SAI2_block_A in master TX mode\r
+ * - SAI2_block_B in slave RX mode synchronous from SAI2_block_A\r
+ */\r
+ slot_active = CODEC_AUDIOFRAME_SLOT_13;\r
+ SAIx_In_Init(SAI_MODESLAVE_RX, slot_active, AudioFreq);\r
+\r
+ slot_active = CODEC_AUDIOFRAME_SLOT_02;\r
+ SAIx_Out_Init(SAI_MODEMASTER_TX, slot_active, AudioFreq);\r
+\r
+ /* wm8994 codec initialization */\r
+ deviceid = wm8994_drv.ReadID(AUDIO_I2C_ADDRESS);\r
+\r
+ if((deviceid) == WM8994_ID)\r
+ {\r
+ /* Reset the Codec Registers */\r
+ wm8994_drv.Reset(AUDIO_I2C_ADDRESS);\r
+ /* Initialize the audio driver structure */\r
+ audio_drv = &wm8994_drv;\r
+ ret = AUDIO_OK;\r
+ }\r
+ else\r
+ {\r
+ ret = AUDIO_ERROR;\r
+ }\r
+\r
+ if(ret == AUDIO_OK)\r
+ {\r
+ /* Initialize the codec internal registers */\r
+ audio_drv->Init(AUDIO_I2C_ADDRESS, InputDevice|OutputDevice, 90, AudioFreq);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ret = AUDIO_ERROR;\r
+ }\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Link digital mic to specified source\r
+ * @param Interface : Audio In interface for Digital mic. It can be:\r
+ * AUDIO_IN_INTERFACE_SAI\r
+ * AUDIO_IN_INTERFACE_PDM\r
+ * @retval None\r
+ */\r
+void BSP_AUDIO_IN_SelectInterface(uint32_t Interface)\r
+{\r
+ hAudioIn.Interface = Interface;\r
+}\r
+\r
+/**\r
+ * @brief Get digital mic interface\r
+ * @retval Digital mic interface.\r
+ */\r
+uint32_t BSP_AUDIO_IN_GetInterface(void)\r
+{\r
+ return (hAudioIn.Interface);\r
+}\r
+\r
+/**\r
+ * @brief Return audio in channel number\r
+ * @retval Number of channel\r
+ */\r
+uint8_t BSP_AUDIO_IN_GetChannelNumber(void)\r
+{\r
+ return hAudioIn.ChannelNbr;\r
+}\r
+\r
+/**\r
+ * @brief Start audio recording.\r
+ * @param pBuf: Main buffer pointer for the recorded data storing\r
+ * @param size: Current size of the recorded buffer\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_Record(uint16_t *pBuf, uint32_t size)\r
+{\r
+ /* Start the process receive DMA */\r
+ if(HAL_OK != HAL_SAI_Receive_DMA(&haudio_in_sai, (uint8_t*)pBuf, size))\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop audio recording.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_Stop(void)\r
+{\r
+ /* Call the Media layer stop function */\r
+ HAL_SAI_DMAStop(&haudio_in_sai);\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+}\r
+\r
+/**\r
+ * @brief Pause the audio file stream.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_Pause(void)\r
+{\r
+ if (hAudioIn.InputDevice == INPUT_DEVICE_ANALOG_MIC)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Call the Media layer pause function */\r
+ HAL_SAI_DMAPause(&haudio_in_sai);\r
+ }\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the audio file stream.\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_Resume(void)\r
+{\r
+ if (hAudioIn.InputDevice == INPUT_DEVICE_ANALOG_MIC)\r
+ {\r
+ return AUDIO_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Call the Media layer resume function */\r
+ HAL_SAI_DMAResume(&haudio_in_sai);\r
+ }\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+}\r
+\r
+/**\r
+ * @brief Controls the audio in volume level.\r
+ * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for\r
+ * Mute and 100 for Max volume level).\r
+ * @retval AUDIO_OK if correct communication, else wrong communication\r
+ */\r
+uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume)\r
+{\r
+ /* Set the Global variable AudioInVolume */\r
+ AudioInVolume = Volume;\r
+\r
+ /* Return AUDIO_OK when all operations are correctly done */\r
+ return AUDIO_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinit the audio IN peripherals.\r
+ * @retval None\r
+ */\r
+void BSP_AUDIO_IN_DeInit(void)\r
+{\r
+ SAIx_In_DeInit(&haudio_in_sai);\r
+\r
+ BSP_AUDIO_IN_MspDeInit();\r
+}\r
+\r
+/**\r
+* @brief Initialize the PDM library.\r
+* @param AudioFreq: Audio sampling frequency\r
+* @param ChnlNbrIn: Number of input audio channels in the PDM buffer\r
+* @param ChnlNbrOut: Number of desired output audio channels in the resulting PCM buffer\r
+* @retval None\r
+*/\r
+uint8_t BSP_AUDIO_IN_PDMToPCM_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut)\r
+{\r
+ uint32_t index = 0;\r
+\r
+ /* Enable CRC peripheral to unlock the PDM library */\r
+ __HAL_RCC_CRC_CLK_ENABLE();\r
+\r
+ for(index = 0; index < ChnlNbrIn; index++)\r
+ {\r
+ /* Init PDM filters */\r
+ PDM_FilterHandler[index].bit_order = PDM_FILTER_BIT_ORDER_MSB;\r
+ PDM_FilterHandler[index].endianness = PDM_FILTER_ENDIANNESS_LE;\r
+ PDM_FilterHandler[index].high_pass_tap = 2122358088;\r
+ PDM_FilterHandler[index].out_ptr_channels = ChnlNbrOut;\r
+ PDM_FilterHandler[index].in_ptr_channels = ChnlNbrIn;\r
+ PDM_Filter_Init((PDM_Filter_Handler_t *)(&PDM_FilterHandler[index]));\r
+\r
+ /* PDM lib config phase */\r
+ PDM_FilterConfig[index].output_samples_number = AudioFreq/1000;\r
+ PDM_FilterConfig[index].mic_gain = 24;\r
+ PDM_FilterConfig[index].decimation_factor = PDM_FILTER_DEC_FACTOR_64;\r
+ PDM_Filter_setConfig((PDM_Filter_Handler_t *)&PDM_FilterHandler[index], &PDM_FilterConfig[index]);\r
+ }\r
+\r
+ return AUDIO_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Converts audio format from PDM to PCM.\r
+ * @param PDMBuf: Pointer to PDM buffer data\r
+ * @param PCMBuf: Pointer to PCM buffer data\r
+ * @retval AUDIO_OK in case of success, AUDIO_ERROR otherwise\r
+ */\r
+uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t *PDMBuf, uint16_t *PCMBuf)\r
+{\r
+ uint32_t index = 0;\r
+\r
+ for(index = 0; index < hAudioIn.ChannelNbr; index++)\r
+ {\r
+ PDM_Filter(&((uint8_t*)(PDMBuf))[index], (uint16_t*)&(PCMBuf[index]), &PDM_FilterHandler[index]);\r
+ }\r
+\r
+ return AUDIO_OK;\r
+}\r
+\r
+/**\r
+ * @brief User callback when record buffer is filled.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_IN_TransferComplete_CallBack(void)\r
+{\r
+ /* This function should be implemented by the user application.\r
+ It is called into this driver when the current buffer is filled\r
+ to prepare the next buffer pointer and its size. */\r
+}\r
+\r
+/**\r
+ * @brief Manages the DMA Half Transfer complete event.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_IN_HalfTransfer_CallBack(void)\r
+{\r
+ /* This function should be implemented by the user application.\r
+ It is called into this driver when the current buffer is filled\r
+ to prepare the next buffer pointer and its size. */\r
+}\r
+\r
+/**\r
+ * @brief User callback when record buffer is filled.\r
+ * @param InputDevice: INPUT_DEVICE_DIGITAL_MIC1 or INPUT_DEVICE_DIGITAL_MIC2\r
+ */\r
+__weak void BSP_AUDIO_IN_TransferComplete_CallBackEx(uint32_t InputDevice)\r
+{\r
+ /* This function should be implemented by the user application.\r
+ It is called into this driver when the current buffer is filled\r
+ to prepare the next buffer pointer and its size. */\r
+}\r
+\r
+/**\r
+ * @brief User callback when record buffer is filled.\r
+ * @param InputDevice: INPUT_DEVICE_DIGITAL_MIC1 or INPUT_DEVICE_DIGITAL_MIC2\r
+ */\r
+__weak void BSP_AUDIO_IN_HalfTransfer_CallBackEx(uint32_t InputDevice)\r
+{\r
+ /* This function should be implemented by the user application.\r
+ It is called into this driver when the current buffer is filled\r
+ to prepare the next buffer pointer and its size. */\r
+}\r
+\r
+/**\r
+ * @brief Audio IN Error callback function.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_IN_Error_CallBack(void)\r
+{\r
+ /* This function is called when an Interrupt due to transfer error on or peripheral\r
+ error occurs. */\r
+}\r
+\r
+/**\r
+ * @brief Initialize BSP_AUDIO_IN MSP.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_IN_MspInit(void)\r
+{\r
+ SAIx_In_MspInit(&haudio_in_sai, NULL);\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize BSP_AUDIO_IN MSP.\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_IN_MspDeInit(void)\r
+{\r
+ SAIx_In_MspDeInit(&haudio_in_sai, NULL);\r
+}\r
+\r
+/**\r
+ * @brief Clock Config.\r
+ * @param AudioFreq: Audio frequency used to play the audio stream.\r
+ * @param Params: pointer on additional configuration parameters, can be NULL.\r
+ * @note This API is called by BSP_AUDIO_IN_Init()\r
+ * Being __weak it can be overwritten by the application\r
+ * @retval None\r
+ */\r
+__weak void BSP_AUDIO_IN_ClockConfig(uint32_t AudioFreq, void *Params)\r
+{\r
+ RCC_PeriphCLKInitTypeDef rcc_ex_clk_init_struct;\r
+\r
+ HAL_RCCEx_GetPeriphCLKConfig(&rcc_ex_clk_init_struct);\r
+\r
+ /* Set the PLL configuration according to the audio frequency */\r
+ if((AudioFreq == AUDIO_FREQUENCY_11K) || (AudioFreq == AUDIO_FREQUENCY_22K) || (AudioFreq == AUDIO_FREQUENCY_44K))\r
+ {\r
+ /* SAI clock config:\r
+ PLL2_VCO Input = HSE_VALUE/PLL2M = 1 Mhz\r
+ PLL2_VCO Output = PLL2_VCO Input * PLL2N = 429 Mhz\r
+ SAI_CLK_x = PLL2_VCO Output/PLL2P = 429/38 = 11.289 Mhz */\r
+ rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI2;\r
+ rcc_ex_clk_init_struct.Sai23ClockSelection = RCC_SAI2CLKSOURCE_PLL2;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2P = 38;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2Q = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2R = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2N = 429;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2M = 25;\r
+ if (hAudioIn.Interface == AUDIO_IN_INTERFACE_PDM)\r
+ {\r
+ rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI4A;\r
+ rcc_ex_clk_init_struct.Sai4AClockSelection = RCC_SAI4ACLKSOURCE_PLL2;\r
+ }\r
+ HAL_RCCEx_PeriphCLKConfig(&rcc_ex_clk_init_struct);\r
+\r
+ }\r
+ else /* AUDIO_FREQUENCY_8K, AUDIO_FREQUENCY_16K, AUDIO_FREQUENCY_32K, AUDIO_FREQUENCY_48K, AUDIO_FREQUENCY_96K */\r
+ {\r
+ /* SAI clock config:\r
+ PLL2_VCO Input = HSE_VALUE/PLL2M = 1 Mhz\r
+ PLL2_VCO Output = PLL2_VCO Input * PLL2N = 344 Mhz\r
+ SAI_CLK_x = PLL2_VCO Output/PLL2P = 344/7 = 49.142 Mhz */\r
+ rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI2;\r
+ rcc_ex_clk_init_struct.Sai23ClockSelection = RCC_SAI2CLKSOURCE_PLL2;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2P = 7;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2Q = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2R = 1;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2N = 344;\r
+ rcc_ex_clk_init_struct.PLL2.PLL2M = 25;\r
+ if (hAudioIn.Interface == AUDIO_IN_INTERFACE_PDM)\r
+ {\r
+ rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI4A;\r
+ rcc_ex_clk_init_struct.Sai4AClockSelection = RCC_SAI4ACLKSOURCE_PLL2;\r
+ }\r
+ HAL_RCCEx_PeriphCLKConfig(&rcc_ex_clk_init_struct);\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_IN_Private_Functions IN Private Functions\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ HAL Callbacks\r
+*******************************************************************************/\r
+\r
+/**\r
+ * @brief Half reception complete callback.\r
+ * @param hsai: SAI handle.\r
+ * @retval None\r
+ */\r
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Manage the remaining file size and new address offset: This function should be coded by user */\r
+ BSP_AUDIO_IN_HalfTransfer_CallBack();\r
+}\r
+\r
+/**\r
+ * @brief Reception complete callback.\r
+ * @param hsai: SAI handle.\r
+ * @retval None\r
+ */\r
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Call the record update function to get the next buffer to fill and its size (size is ignored) */\r
+ BSP_AUDIO_IN_TransferComplete_CallBack();\r
+}\r
+\r
+/*******************************************************************************\r
+ Static Functions\r
+*******************************************************************************/\r
+/**\r
+ * @brief Initializes SAI Audio IN MSP.\r
+ * @param hsai: SAI handle\r
+ * @param Params: pointer on additional configuration parameters, can be NULL.\r
+ * @retval None\r
+ */\r
+static void SAIx_In_MspInit(SAI_HandleTypeDef *hsai, void *Params)\r
+{\r
+ static DMA_HandleTypeDef hdma_sai_rx;\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ if(hsai->Instance == AUDIO_IN_SAI_PDMx)\r
+ {\r
+ /* Enable SAI clock */\r
+ AUDIO_IN_SAI_PDMx_CLK_ENABLE();\r
+\r
+ /* Enable PDM clock */\r
+ AUDIO_IN_SAI_PDMx_CLK_IN_ENABLE();\r
+ gpio_init_structure.Pin = AUDIO_IN_SAI_PDMx_CLK_IN_PIN;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;\r
+ gpio_init_structure.Alternate = AUDIO_IN_SAI_PDMx_DATA_CLK_AF;\r
+ HAL_GPIO_Init(AUDIO_IN_SAI_PDMx_CLK_IN_PORT, &gpio_init_structure);\r
+\r
+ /* Enable PDM data */\r
+ AUDIO_IN_SAI_PDMx_DATA_IN_ENABLE();\r
+ gpio_init_structure.Pull = GPIO_PULLUP;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_MEDIUM;\r
+ gpio_init_structure.Pin = AUDIO_IN_SAI_PDMx_DATA_IN_PIN;\r
+ HAL_GPIO_Init(AUDIO_IN_SAI_PDMx_DATA_IN_PORT, &gpio_init_structure);\r
+\r
+ /* Enable the DMA clock */\r
+ AUDIO_IN_SAI_PDMx_DMAx_CLK_ENABLE();\r
+\r
+ /* Configure the hdma_sai_rx handle parameters */\r
+ hdma_sai_rx.Init.Request = AUDIO_IN_SAI_PDMx_DMAx_REQUEST;\r
+ hdma_sai_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\r
+ hdma_sai_rx.Init.PeriphInc = DMA_PINC_DISABLE;\r
+ hdma_sai_rx.Init.MemInc = DMA_MINC_ENABLE;\r
+ hdma_sai_rx.Init.PeriphDataAlignment = AUDIO_IN_SAI_PDMx_DMAx_PERIPH_DATA_SIZE;\r
+ hdma_sai_rx.Init.MemDataAlignment = AUDIO_IN_SAI_PDMx_DMAx_MEM_DATA_SIZE;\r
+ hdma_sai_rx.Init.Mode = DMA_CIRCULAR;\r
+ hdma_sai_rx.Init.Priority = DMA_PRIORITY_HIGH;\r
+ hdma_sai_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\r
+ hdma_sai_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;\r
+ hdma_sai_rx.Init.MemBurst = DMA_MBURST_SINGLE;\r
+ hdma_sai_rx.Init.PeriphBurst = DMA_MBURST_SINGLE;\r
+\r
+ hdma_sai_rx.Instance = AUDIO_IN_SAI_PDMx_DMAx_STREAM;\r
+\r
+ /* Associate the DMA handle */\r
+ __HAL_LINKDMA(hsai, hdmarx, hdma_sai_rx);\r
+\r
+ /* Deinitialize the Stream for new transfer */\r
+ HAL_DMA_DeInit(&hdma_sai_rx);\r
+\r
+ /* Configure the DMA Stream */\r
+ HAL_DMA_Init(&hdma_sai_rx);\r
+\r
+ /* SAI DMA IRQ Channel configuration */\r
+ HAL_NVIC_SetPriority(AUDIO_IN_SAI_PDMx_DMAx_IRQ, AUDIO_IN_IRQ_PREPRIO, 0);\r
+ HAL_NVIC_EnableIRQ(AUDIO_IN_SAI_PDMx_DMAx_IRQ);\r
+ }\r
+ else\r
+ {\r
+ /* Enable SAI clock */\r
+ AUDIO_IN_SAIx_CLK_ENABLE();\r
+\r
+ /* Enable SD GPIO clock */\r
+ AUDIO_IN_SAIx_SD_ENABLE();\r
+ /* CODEC_SAI pin configuration: SD pin */\r
+ gpio_init_structure.Pin = AUDIO_IN_SAIx_SD_PIN;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;\r
+ gpio_init_structure.Alternate = AUDIO_IN_SAIx_AF;\r
+ HAL_GPIO_Init(AUDIO_IN_SAIx_SD_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* Enable the DMA clock */\r
+ AUDIO_IN_SAIx_DMAx_CLK_ENABLE();\r
+\r
+ /* Configure the hdma_sai_rx handle parameters */\r
+ hdma_sai_rx.Init.Request = AUDIO_IN_SAIx_DMAx_REQUEST;\r
+ hdma_sai_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\r
+ hdma_sai_rx.Init.PeriphInc = DMA_PINC_DISABLE;\r
+ hdma_sai_rx.Init.MemInc = DMA_MINC_ENABLE;\r
+ hdma_sai_rx.Init.PeriphDataAlignment = AUDIO_IN_SAIx_DMAx_PERIPH_DATA_SIZE;\r
+ hdma_sai_rx.Init.MemDataAlignment = AUDIO_IN_SAIx_DMAx_MEM_DATA_SIZE;\r
+ hdma_sai_rx.Init.Mode = DMA_CIRCULAR;\r
+ hdma_sai_rx.Init.Priority = DMA_PRIORITY_HIGH;\r
+ hdma_sai_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\r
+ hdma_sai_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;\r
+ hdma_sai_rx.Init.MemBurst = DMA_MBURST_SINGLE;\r
+ hdma_sai_rx.Init.PeriphBurst = DMA_MBURST_SINGLE;\r
+\r
+ hdma_sai_rx.Instance = AUDIO_IN_SAIx_DMAx_STREAM;\r
+\r
+ /* Associate the DMA handle */\r
+ __HAL_LINKDMA(hsai, hdmarx, hdma_sai_rx);\r
+\r
+ /* Deinitialize the Stream for new transfer */\r
+ HAL_DMA_DeInit(&hdma_sai_rx);\r
+\r
+ /* Configure the DMA Stream */\r
+ HAL_DMA_Init(&hdma_sai_rx);\r
+\r
+ /* SAI DMA IRQ Channel configuration */\r
+ HAL_NVIC_SetPriority(AUDIO_IN_SAIx_DMAx_IRQ, AUDIO_IN_IRQ_PREPRIO, 0);\r
+ HAL_NVIC_EnableIRQ(AUDIO_IN_SAIx_DMAx_IRQ);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes SAI Audio IN MSP.\r
+ * @param hsai: SAI handle\r
+ * @param Params: pointer on additional configuration parameters, can be NULL.\r
+ * @retval None\r
+ */\r
+static void SAIx_In_MspDeInit(SAI_HandleTypeDef *hsai, void *Params)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ if(hsai->Instance == AUDIO_IN_SAI_PDMx)\r
+ {\r
+ /* Deinitialize the DMA stream */\r
+ HAL_DMA_Abort(hsai->hdmarx);\r
+\r
+ HAL_SAI_DeInit(hsai);\r
+ /* Disable SAI peripheral */\r
+ __HAL_SAI_DISABLE(hsai);\r
+\r
+ /* Deinitialize the DMA stream */\r
+ HAL_DMA_DeInit(hsai->hdmarx);\r
+\r
+ gpio_init_structure.Pin = AUDIO_IN_SAI_PDMx_CLK_IN_PIN;\r
+ HAL_GPIO_DeInit(AUDIO_IN_SAI_PDMx_CLK_IN_PORT, gpio_init_structure.Pin);\r
+\r
+ gpio_init_structure.Pin = AUDIO_IN_SAI_PDMx_DATA_IN_PIN;\r
+ HAL_GPIO_DeInit(AUDIO_IN_SAI_PDMx_DATA_IN_PORT, gpio_init_structure.Pin);\r
+\r
+ /* Disable SAI clock */\r
+ AUDIO_IN_SAI_PDMx_CLK_DISABLE();\r
+ }\r
+ else\r
+ {\r
+ /* SAI DMA IRQ Channel deactivation */\r
+ HAL_NVIC_DisableIRQ(AUDIO_IN_SAIx_DMAx_IRQ);\r
+\r
+ if(hsai->Instance == AUDIO_IN_SAIx)\r
+ {\r
+ /* Deinitialize the DMA stream */\r
+ HAL_DMA_DeInit(hsai->hdmatx);\r
+ }\r
+\r
+ /* Disable SAI peripheral */\r
+ __HAL_SAI_DISABLE(hsai);\r
+\r
+ /* Deactivates CODEC_SAI pin SD by putting them in input mode */\r
+ gpio_init_structure.Pin = AUDIO_IN_SAIx_SD_PIN;\r
+ HAL_GPIO_DeInit(AUDIO_IN_SAIx_SD_GPIO_PORT, gpio_init_structure.Pin);\r
+\r
+ /* Disable SAI clock */\r
+ AUDIO_IN_SAIx_CLK_DISABLE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the Audio Codec audio interface (SAI).\r
+ * @param SaiInMode: Audio mode to be configured for the SAI peripheral.\r
+ * @param SlotActive: Audio active slot to be configured for the SAI peripheral.\r
+ * @param AudioFreq: Audio frequency to be configured for the SAI peripheral.\r
+ * @retval None\r
+ */\r
+static void SAIx_In_Init(uint32_t SaiInMode, uint32_t SlotActive, uint32_t AudioFreq)\r
+{\r
+ /* Disable SAI peripheral to allow access to SAI internal registers */\r
+ __HAL_SAI_DISABLE(&haudio_in_sai);\r
+\r
+ /* Configure SAI_Block_x\r
+ LSBFirst: Disabled\r
+ DataSize: 16 */\r
+ haudio_in_sai.Init.MonoStereoMode = SAI_STEREOMODE;\r
+ haudio_in_sai.Init.AudioFrequency = AudioFreq;\r
+ haudio_in_sai.Init.AudioMode = SaiInMode;\r
+ haudio_in_sai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;\r
+ haudio_in_sai.Init.Protocol = SAI_FREE_PROTOCOL;\r
+ haudio_in_sai.Init.DataSize = SAI_DATASIZE_16;\r
+ haudio_in_sai.Init.FirstBit = SAI_FIRSTBIT_MSB;\r
+ haudio_in_sai.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;\r
+ haudio_in_sai.Init.Synchro = SAI_SYNCHRONOUS;\r
+ haudio_in_sai.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE;\r
+ haudio_in_sai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF;\r
+ haudio_in_sai.Init.SynchroExt = SAI_SYNCEXT_DISABLE;\r
+ haudio_in_sai.Init.CompandingMode = SAI_NOCOMPANDING;\r
+ haudio_in_sai.Init.TriState = SAI_OUTPUT_RELEASED;\r
+ haudio_in_sai.Init.Mckdiv = 0;\r
+ haudio_in_sai.Init.MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE;\r
+ haudio_in_sai.Init.PdmInit.Activation = DISABLE;\r
+\r
+ /* Configure SAI_Block_x Frame\r
+ Frame Length: 64\r
+ Frame active Length: 32\r
+ FS Definition: Start frame + Channel Side identification\r
+ FS Polarity: FS active Low\r
+ FS Offset: FS asserted one bit before the first bit of slot 0 */\r
+ haudio_in_sai.FrameInit.FrameLength = 128;\r
+ haudio_in_sai.FrameInit.ActiveFrameLength = 64;\r
+ haudio_in_sai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;\r
+ haudio_in_sai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;\r
+ haudio_in_sai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;\r
+\r
+ /* Configure SAI Block_x Slot\r
+ Slot First Bit Offset: 0\r
+ Slot Size : 16\r
+ Slot Number: 4\r
+ Slot Active: All slot active */\r
+ haudio_in_sai.SlotInit.FirstBitOffset = 0;\r
+ haudio_in_sai.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;\r
+ haudio_in_sai.SlotInit.SlotNumber = 4;\r
+ haudio_in_sai.SlotInit.SlotActive = SlotActive;\r
+\r
+ if(hAudioIn.Interface == AUDIO_IN_INTERFACE_PDM)\r
+ {\r
+ haudio_in_sai.Init.AudioFrequency = AudioFreq * 8;\r
+ haudio_in_sai.Init.Synchro = SAI_ASYNCHRONOUS;\r
+ haudio_in_sai.Init.NoDivider = SAI_MASTERDIVIDER_DISABLE;\r
+\r
+ haudio_in_sai.Init.PdmInit.Activation = ENABLE;\r
+ haudio_in_sai.Init.PdmInit.MicPairsNbr = 2;\r
+ haudio_in_sai.Init.PdmInit.ClockEnable = SAI_PDM_CLOCK2_ENABLE;\r
+ haudio_in_sai.Init.FirstBit = SAI_FIRSTBIT_LSB;\r
+ haudio_in_sai.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;\r
+\r
+ haudio_in_sai.FrameInit.FrameLength = 32;\r
+ haudio_in_sai.FrameInit.ActiveFrameLength = 1;\r
+ haudio_in_sai.FrameInit.FSDefinition = SAI_FS_STARTFRAME;\r
+ haudio_in_sai.FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;\r
+ haudio_in_sai.FrameInit.FSOffset = SAI_FS_FIRSTBIT;\r
+\r
+ haudio_in_sai.SlotInit.SlotNumber = 2;\r
+ haudio_in_sai.SlotInit.SlotActive = SlotActive;\r
+ }\r
+\r
+ HAL_SAI_Init(&haudio_in_sai);\r
+\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(&haudio_in_sai);\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the output Audio Codec audio interface (SAI).\r
+ * @retval None\r
+ */\r
+static void SAIx_In_DeInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Disable SAI peripheral */\r
+ __HAL_SAI_DISABLE(hsai);\r
+\r
+ HAL_SAI_DeInit(hsai);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_audio.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the common defines and functions prototypes for\r
+ * the stm32h745i_discovery_audio.c driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H745I_DISCOVERY_AUDIO_H\r
+#define __STM32H745I_DISCOVERY_AUDIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Include audio component Driver */\r
+#include "../Components/wm8994/wm8994.h"\r
+#include "stm32h745i_discovery.h"\r
+#include <stdlib.h>\r
+/* Include PDM to PCM lib header file */\r
+#include "pdm2pcm_glo.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_AUDIO\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_Exported_Types Exported Types\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Frequency; /* Record Frequency */\r
+ uint32_t BitResolution; /* Record bit resolution */\r
+ uint32_t ChannelNbr; /* Record Channel Number */\r
+ uint16_t *pRecBuf; /* Pointer to record user buffer */\r
+ uint32_t RecSize; /* Size to record in mono, double size to record in stereo */\r
+ uint32_t InputDevice; /* Audio Input Device */\r
+ uint32_t Interface; /* Audio Input Interface */\r
+ uint32_t MultiBuffMode; /* Multi buffer mode selection */\r
+}AUDIOIN_ContextTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_Exported_Constants Exported Constants\r
+ * @{\r
+ */\r
+#define BSP_AUDIO_FREQUENCY_96K SAI_AUDIO_FREQUENCY_96K\r
+#define BSP_AUDIO_FREQUENCY_48K SAI_AUDIO_FREQUENCY_48K\r
+#define BSP_AUDIO_FREQUENCY_44K SAI_AUDIO_FREQUENCY_44K\r
+#define BSP_AUDIO_FREQUENCY_32K SAI_AUDIO_FREQUENCY_32K\r
+#define BSP_AUDIO_FREQUENCY_22K SAI_AUDIO_FREQUENCY_22K\r
+#define BSP_AUDIO_FREQUENCY_16K SAI_AUDIO_FREQUENCY_16K\r
+#define BSP_AUDIO_FREQUENCY_11K SAI_AUDIO_FREQUENCY_11K\r
+#define BSP_AUDIO_FREQUENCY_8K SAI_AUDIO_FREQUENCY_8K\r
+\r
+/*------------------------------------------------------------------------------\r
+ USER SAI defines parameters\r
+ -----------------------------------------------------------------------------*/\r
+/** In W8994 codec the Audio frame contains 4 slots : TDM Mode\r
+ * TDM format :\r
+ * +------------------|------------------|--------------------|-------------------+\r
+ * | CODEC_SLOT0 Left | CODEC_SLOT1 Left | CODEC_SLOT0 Right | CODEC_SLOT1 Right |\r
+ * +------------------------------------------------------------------------------+\r
+ */\r
+/* To have 2 separate audio stream in Both headphone and speaker the 4 slot must be activated */\r
+#define CODEC_AUDIOFRAME_SLOT_0123 SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_2 | SAI_SLOTACTIVE_3\r
+\r
+/* To have an audio stream in headphone only SAI Slot 0 and Slot 2 must be activated */\r
+#define CODEC_AUDIOFRAME_SLOT_02 SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_2\r
+/* To have an audio stream in speaker only SAI Slot 1 and Slot 3 must be activated */\r
+#define CODEC_AUDIOFRAME_SLOT_13 SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_3\r
+/* To have an audio stream in SAI PDM input Slot 0 must be activated */\r
+#define CODEC_AUDIOFRAME_SLOT_0 SAI_SLOTACTIVE_0\r
+/* To have an audio stream in SAI PDM input Slot 1 must be activated */\r
+#define CODEC_AUDIOFRAME_SLOT_1 SAI_SLOTACTIVE_1\r
+\r
+/*------------------------------------------------------------------------------\r
+ AUDIO OUT CONFIGURATION\r
+------------------------------------------------------------------------------*/\r
+/* SAI peripheral configuration defines */\r
+#define AUDIO_OUT_SAIx SAI2_Block_A\r
+#define AUDIO_OUT_SAIx_CLK_ENABLE() __HAL_RCC_SAI2_CLK_ENABLE()\r
+#define AUDIO_OUT_SAIx_CLK_DISABLE() __HAL_RCC_SAI2_CLK_DISABLE()\r
+#define AUDIO_OUT_SAIx_AF GPIO_AF10_SAI2\r
+\r
+#define AUDIO_OUT_SAIx_MCLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE()\r
+#define AUDIO_OUT_SAIx_MCLK_GPIO_PORT GPIOI\r
+#define AUDIO_OUT_SAIx_MCLK_PIN GPIO_PIN_4\r
+#define AUDIO_OUT_SAIx_SD_FS_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE()\r
+#define AUDIO_OUT_SAIx_SD_FS_SCK_GPIO_PORT GPIOI\r
+#define AUDIO_OUT_SAIx_FS_PIN GPIO_PIN_7\r
+#define AUDIO_OUT_SAIx_SCK_PIN GPIO_PIN_5\r
+#define AUDIO_OUT_SAIx_SD_PIN GPIO_PIN_6\r
+\r
+/* SAI DMA Stream definitions */\r
+#define AUDIO_OUT_SAIx_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()\r
+#define AUDIO_OUT_SAIx_DMAx_STREAM DMA2_Stream1\r
+#define AUDIO_OUT_SAIx_DMAx_REQUEST DMA_REQUEST_SAI2_A\r
+#define AUDIO_OUT_SAIx_DMAx_IRQ DMA2_Stream1_IRQn\r
+#define AUDIO_OUT_SAIx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD\r
+#define AUDIO_OUT_SAIx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD\r
+#define AUDIO_OUT_SAIx_DMAx_IRQHandler DMA2_Stream1_IRQHandler\r
+\r
+/* Select the interrupt preemption priority and subpriority for the DMA interrupt */\r
+#define AUDIO_OUT_IRQ_PREPRIO ((uint32_t)0x0E)\r
+\r
+/*------------------------------------------------------------------------------\r
+ AUDIO IN CONFIGURATION\r
+------------------------------------------------------------------------------*/\r
+/* SAI peripheral configuration defines */\r
+#define AUDIO_IN_SAIx SAI2_Block_B\r
+#define AUDIO_IN_SAIx_CLK_ENABLE() __HAL_RCC_SAI2_CLK_ENABLE()\r
+#define AUDIO_IN_SAIx_CLK_DISABLE() __HAL_RCC_SAI2_CLK_DISABLE()\r
+#define AUDIO_IN_SAIx_AF GPIO_AF10_SAI2\r
+#define AUDIO_IN_SAIx_SD_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()\r
+#define AUDIO_IN_SAIx_SD_GPIO_PORT GPIOG\r
+#define AUDIO_IN_SAIx_SD_PIN GPIO_PIN_10\r
+\r
+/* SAI DMA Stream definitions */\r
+#define AUDIO_IN_SAIx_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()\r
+#define AUDIO_IN_SAIx_DMAx_STREAM DMA2_Stream4\r
+#define AUDIO_IN_SAIx_DMAx_REQUEST DMA_REQUEST_SAI2_B\r
+#define AUDIO_IN_SAIx_DMAx_IRQ DMA2_Stream4_IRQn\r
+#define AUDIO_IN_SAIx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD\r
+#define AUDIO_IN_SAIx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD\r
+\r
+#define AUDIO_IN_SAIx_DMAx_IRQHandler DMA2_Stream4_IRQHandler\r
+\r
+/* SAI PDM input definitions */\r
+#define AUDIO_IN_SAI_PDMx SAI4_Block_A\r
+#define AUDIO_IN_SAI_PDMx_CLK_ENABLE() __HAL_RCC_SAI4_CLK_ENABLE()\r
+#define AUDIO_IN_SAI_PDMx_CLK_DISABLE() __HAL_RCC_SAI4_CLK_DISABLE()\r
+#define AUDIO_IN_SAI_PDMx_CLK_IN_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()\r
+#define AUDIO_IN_SAI_PDMx_CLK_IN_PIN GPIO_PIN_5\r
+#define AUDIO_IN_SAI_PDMx_CLK_IN_PORT GPIOE\r
+#define AUDIO_IN_SAI_PDMx_DATA_IN_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()\r
+#define AUDIO_IN_SAI_PDMx_DATA_IN_PIN GPIO_PIN_4\r
+#define AUDIO_IN_SAI_PDMx_DATA_IN_PORT GPIOE\r
+#define AUDIO_IN_SAI_PDMx_DATA_CLK_AF GPIO_AF10_SAI4\r
+#define AUDIO_IN_SAI_PDMx_IRQHandler SAI4_IRQHandler\r
+#define AUDIO_IN_SAI_PDMx_IRQ SAI4_IRQn\r
+\r
+/* SAI PDM DMA Stream definitions */\r
+#define AUDIO_IN_SAI_PDMx_DMAx_CLK_ENABLE() __HAL_RCC_BDMA_CLK_ENABLE()\r
+#define AUDIO_IN_SAI_PDMx_DMAx_STREAM BDMA_Channel1\r
+#define AUDIO_IN_SAI_PDMx_DMAx_REQUEST BDMA_REQUEST_SAI4_A\r
+#define AUDIO_IN_SAI_PDMx_DMAx_IRQ BDMA_Channel1_IRQn\r
+#define AUDIO_IN_SAI_PDMx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD\r
+#define AUDIO_IN_SAI_PDMx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD\r
+#define AUDIO_IN_SAI_PDMx_DMAx_IRQHandler BDMA_Channel1_IRQHandler\r
+\r
+/* Select the interrupt preemption priority and subpriority for the DMA interrupt */\r
+#define AUDIO_IN_IRQ_PREPRIO ((uint32_t)0x0F)\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ CONFIGURATION: Audio Driver Configuration parameters\r
+------------------------------------------------------------------------------*/\r
+\r
+#define AUDIODATA_SIZE ((uint32_t)2) /* 16-bits audio data size */\r
+\r
+/* Audio status definition */\r
+#define AUDIO_OK ((uint8_t)0)\r
+#define AUDIO_ERROR ((uint8_t)1)\r
+#define AUDIO_TIMEOUT ((uint8_t)2)\r
+\r
+/* Audio In default settings */\r
+#define DEFAULT_AUDIO_IN_FREQ BSP_AUDIO_FREQUENCY_16K\r
+#define DEFAULT_AUDIO_IN_BIT_RESOLUTION ((uint8_t)16)\r
+#define DEFAULT_AUDIO_IN_CHANNEL_NBR ((uint8_t)2)\r
+#define DEFAULT_AUDIO_IN_VOLUME ((uint16_t)64)\r
+\r
+/*------------------------------------------------------------------------------\r
+ OUTPUT DEVICES definition\r
+------------------------------------------------------------------------------*/\r
+/* Alias on existing output devices to adapt for 2 headphones output */\r
+#define OUTPUT_DEVICE_HEADPHONE1 OUTPUT_DEVICE_HEADPHONE\r
+#define OUTPUT_DEVICE_HEADPHONE2 OUTPUT_DEVICE_SPEAKER /* Headphone2 is connected to Speaker output of the wm8994 */\r
+\r
+/*------------------------------------------------------------------------------\r
+ INPUT DEVICES definition\r
+------------------------------------------------------------------------------*/\r
+/* Analog microphone input from 3.5 audio jack connector */\r
+#define INPUT_DEVICE_ANALOG_MIC ((uint32_t)0x00000001)\r
+/* MP34DT01TR digital microphone on PCB top side */\r
+#define INPUT_DEVICE_DIGITAL_MIC1 ((uint32_t)0x00000010)\r
+#define INPUT_DEVICE_DIGITAL_MIC2 ((uint32_t)0x00000020)\r
+#define INPUT_DEVICE_DIGITAL_MIC ((uint32_t)(INPUT_DEVICE_DIGITAL_MIC1 | INPUT_DEVICE_DIGITAL_MIC2))\r
+\r
+/* Audio In interface for Digital mic */\r
+#define AUDIO_IN_INTERFACE_SAI ((uint16_t)0)\r
+#define AUDIO_IN_INTERFACE_PDM ((uint16_t)1)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_AUDIO_Exported_Macros Exported Macros\r
+ * @{\r
+ */\r
+#define DMA_MAX_SIZE 0xFFFF\r
+#define DMA_MAX(x) (((x) <= DMA_MAX_SIZE)? (x):DMA_MAX_SIZE)\r
+#define POS_VAL(VAL) (POSITION_VAL(VAL) - 4)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_AUDIO_OUT_Exported_Functions\r
+ * @{\r
+ */\r
+uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);\r
+void BSP_AUDIO_OUT_DeInit(void);\r
+uint8_t BSP_AUDIO_OUT_Play(uint16_t* pBuffer, uint32_t Size);\r
+void BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size);\r
+uint8_t BSP_AUDIO_OUT_Pause(void);\r
+uint8_t BSP_AUDIO_OUT_Resume(void);\r
+uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option);\r
+uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume);\r
+void BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq);\r
+void BSP_AUDIO_OUT_SetAudioFrameSlot(uint32_t AudioFrameSlot);\r
+uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd);\r
+uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output);\r
+\r
+/* User Callbacks: user has to implement these functions in his code if they are needed. */\r
+/* This function is called when the requested data has been completely transferred.*/\r
+void BSP_AUDIO_OUT_TransferComplete_CallBack(void);\r
+\r
+/* This function is called when half of the requested buffer has been transferred. */\r
+void BSP_AUDIO_OUT_HalfTransfer_CallBack(void);\r
+\r
+/* This function is called when an Interrupt due to transfer error on or peripheral\r
+ error occurs. */\r
+void BSP_AUDIO_OUT_Error_CallBack(void);\r
+\r
+/* These function can be modified in case the current settings (e.g. DMA stream)\r
+ need to be changed for specific application needs */\r
+void BSP_AUDIO_OUT_ClockConfig(SAI_HandleTypeDef *hsai, uint32_t AudioFreq, void *Params);\r
+void BSP_AUDIO_OUT_MspInit(SAI_HandleTypeDef *hsai, void *Params);\r
+void BSP_AUDIO_OUT_MspDeInit(SAI_HandleTypeDef *hsai, void *Params);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_AUDIO_IN_Exported_Functions\r
+ * @{\r
+ */\r
+uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);\r
+uint8_t BSP_AUDIO_IN_InitEx(uint16_t InputDevice, uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);\r
+uint8_t BSP_AUDIO_IN_AllocScratch (int32_t *pScratch, uint32_t size);\r
+uint8_t BSP_AUDIO_IN_Record(uint16_t *pBuf, uint32_t Size);\r
+uint8_t BSP_AUDIO_IN_RecordEx(uint32_t *pBuf, uint32_t Size);\r
+uint8_t BSP_AUDIO_IN_SetFrequency(uint32_t AudioFreq);\r
+uint8_t BSP_AUDIO_IN_Stop(void);\r
+uint8_t BSP_AUDIO_IN_StopEx(uint32_t InputDevice);\r
+uint8_t BSP_AUDIO_IN_Pause(void);\r
+uint8_t BSP_AUDIO_IN_PauseEx(uint32_t InputDevice);\r
+uint8_t BSP_AUDIO_IN_Resume(void);\r
+uint8_t BSP_AUDIO_IN_ResumeEx(uint32_t *pBuf, uint32_t InputDevice);\r
+uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume);\r
+void BSP_AUDIO_IN_DeInit(void);\r
+uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t *PDMBuf, uint16_t *PCMBuf);\r
+uint8_t BSP_AUDIO_IN_PDMToPCM_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut);\r
+void BSP_AUDIO_IN_SelectInterface(uint32_t Interface);\r
+uint32_t BSP_AUDIO_IN_GetInterface(void);\r
+uint8_t BSP_AUDIO_IN_GetChannelNumber(void);\r
+uint8_t BSP_AUDIO_IN_OUT_Init(uint32_t InputDevice, uint32_t OutputDevice, uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);\r
+\r
+/* User Callbacks: user has to implement these functions in his code if they are needed. */\r
+/* This function should be implemented by the user application.\r
+ It is called into this driver when the current buffer is filled to prepare the next\r
+ buffer pointer and its size. */\r
+void BSP_AUDIO_IN_TransferComplete_CallBack(void);\r
+void BSP_AUDIO_IN_HalfTransfer_CallBack(void);\r
+void BSP_AUDIO_IN_TransferComplete_CallBackEx(uint32_t InputDevice);\r
+void BSP_AUDIO_IN_HalfTransfer_CallBackEx(uint32_t InputDevice);\r
+\r
+/* This function is called when an Interrupt due to transfer error on or peripheral\r
+ error occurs. */\r
+void BSP_AUDIO_IN_Error_CallBack(void);\r
+\r
+/* These function can be modified in case the current settings (e.g. DMA stream)\r
+ need to be changed for specific application needs */\r
+void BSP_AUDIO_IN_ClockConfig(uint32_t AudioFreq, void *Params);\r
+void BSP_AUDIO_IN_MspInit(void);\r
+void BSP_AUDIO_IN_MspDeInit(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H745I_DISCOVERY_AUDIO_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_lcd.c\r
+ * @author MCD Application Team\r
+ * @brief This file includes the driver for Liquid Crystal Display (LCD) module\r
+ * mounted on STM32H745I_DISCOVERY board.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+ /*\r
+ How To use this driver:\r
+ -----------------------\r
+ - This driver is used to drive directly an LCD TFT using the LTDC controller.\r
+ - This driver uses timing and setting for RK043FN48H LCD.\r
+ \r
+ Driver description:\r
+ ------------------\r
+ + Initialization steps:\r
+ o Initialize the LCD using the BSP_LCD_Init() function.\r
+ o Apply the Layer configuration using the BSP_LCD_LayerDefaultInit() function.\r
+ o Select the LCD layer to be used using the BSP_LCD_SelectLayer() function.\r
+ o Enable the LCD display using the BSP_LCD_DisplayOn() function.\r
+ \r
+ + Options\r
+ o Configure and enable the colour keying functionality using the\r
+ BSP_LCD_SetColorKeying() function.\r
+ o Modify in the fly the transparency and/or the frame buffer address\r
+ using the following functions:\r
+ - BSP_LCD_SetTransparency()\r
+ - BSP_LCD_SetLayerAddress()\r
+\r
+ + Display on LCD\r
+ o Clear the whole LCD using BSP_LCD_Clear() function or only one specified string\r
+ line using the BSP_LCD_ClearStringLine() function.\r
+ o Display a character on the specified line and column using the BSP_LCD_DisplayChar()\r
+ function or a complete string line using the BSP_LCD_DisplayStringAtLine() function.\r
+ o Display a string line on the specified position (x,y in pixel) and align mode\r
+ using the BSP_LCD_DisplayStringAtLine() function.\r
+ o Draw and fill a basic shapes (dot, line, rectangle, circle, ellipse, .. bitmap)\r
+ on LCD using the available set of functions.\r
+ */\r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery_lcd.h"\r
+#include "../../../Utilities/Fonts/fonts.h"\r
+#include "../../../Utilities/Fonts/font24.c"\r
+#include "../../../Utilities/Fonts/font20.c"\r
+#include "../../../Utilities/Fonts/font16.c"\r
+#include "../../../Utilities/Fonts/font12.c"\r
+#include "../../../Utilities/Fonts/font8.c"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD STM32H745I_DISCOVERY_LCD\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Private_Defines Private Defines\r
+ * @{\r
+ */\r
+#define POLY_X(Z) ((int32_t)((Points + Z)->X))\r
+#define POLY_Y(Z) ((int32_t)((Points + Z)->Y))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Private_Macros Private Macros\r
+ * @{\r
+ */\r
+#define ABS(X) ((X) > 0 ? (X) : -(X))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Private_Variables Private Variables\r
+ * @{\r
+ */\r
+DMA2D_HandleTypeDef hdma2d_discovery;\r
+LTDC_HandleTypeDef hltdc_discovery;\r
+\r
+/* Timer handler declaration */\r
+static TIM_HandleTypeDef LCD_TimHandle;\r
+\r
+/* Default LCD configuration with LCD Layer 1 */\r
+static uint32_t ActiveLayer = 0;\r
+static LCD_DrawPropTypeDef DrawProp[MAX_LAYER_NUMBER];\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Private_FunctionPrototypes Private FunctionPrototypes\r
+ * @{\r
+ */\r
+static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c);\r
+static void FillTriangle(uint16_t x1, uint16_t x2, uint16_t x3, uint16_t y1, uint16_t y2, uint16_t y3);\r
+static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex);\r
+static void LL_ConvertLineToARGB8888(void * pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode);\r
+static void TIMx_PWM_MspInit(TIM_HandleTypeDef *htim);\r
+static void TIMx_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
+static void TIMx_PWM_DeInit(TIM_HandleTypeDef *htim);\r
+static void TIMx_PWM_Init(TIM_HandleTypeDef *htim);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Exported_Functions Exported Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the LCD.\r
+ * @retval LCD state\r
+ */\r
+uint8_t BSP_LCD_Init(void)\r
+{\r
+ /* The RK043FN48H LCD 480x272 is used*/\r
+ /* Timing Configuration */\r
+ hltdc_discovery.Init.HorizontalSync = (RK043FN48H_HSYNC - 1);\r
+ hltdc_discovery.Init.VerticalSync = (RK043FN48H_VSYNC - 1);\r
+ hltdc_discovery.Init.AccumulatedHBP = (RK043FN48H_HSYNC + (RK043FN48H_HBP-11) - 1); /*RK043FN48H_HBP-11: adjust timing to be updated in the component*/\r
+ hltdc_discovery.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1);\r
+ hltdc_discovery.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1);\r
+ hltdc_discovery.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + (RK043FN48H_HBP-11) - 1);/*RK043FN48H_HBP-11: adjust timing to be updated in the component*/\r
+ hltdc_discovery.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1);\r
+ hltdc_discovery.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + (RK043FN48H_HBP-11) + RK043FN48H_HFP - 1);/*RK043FN48H_HBP-11: adjust timing to be updated in the component*/\r
+ \r
+\r
+\r
+ /* Initialize the LCD pixel width and pixel height */\r
+ hltdc_discovery.LayerCfg->ImageWidth = RK043FN48H_WIDTH;\r
+ hltdc_discovery.LayerCfg->ImageHeight = RK043FN48H_HEIGHT;\r
+\r
+\r
+ /* Background value */\r
+ hltdc_discovery.Init.Backcolor.Blue = 0;\r
+ hltdc_discovery.Init.Backcolor.Green = 0;\r
+ hltdc_discovery.Init.Backcolor.Red = 0;\r
+\r
+ /* Polarity */\r
+ hltdc_discovery.Init.HSPolarity = LTDC_HSPOLARITY_AL;\r
+ hltdc_discovery.Init.VSPolarity = LTDC_VSPOLARITY_AL;\r
+ hltdc_discovery.Init.DEPolarity = LTDC_DEPOLARITY_AL;\r
+ hltdc_discovery.Init.PCPolarity = LTDC_PCPOLARITY_IPC;\r
+ hltdc_discovery.Instance = LTDC;\r
+\r
+ /* LCD clock configuration */\r
+ BSP_LCD_ClockConfig(&hltdc_discovery, NULL);\r
+\r
+ if(HAL_LTDC_GetState(&hltdc_discovery) == HAL_LTDC_STATE_RESET)\r
+ {\r
+ /* Initialize the LCD Msp: this __weak function can be rewritten by the application */\r
+ BSP_LCD_MspInit(&hltdc_discovery, NULL);\r
+ }\r
+ HAL_LTDC_Init(&hltdc_discovery);\r
+\r
+#if !defined(DATA_IN_ExtSDRAM)\r
+ /* When DATA_IN_ExtSDRAM define is enabled, the SDRAM will be configured in SystemInit()\r
+ function (from system_stm32h7xx.c) before branch to main() routine. In such case, there\r
+ is no need to reconfigure the SDRAM within the LCD driver, since it's already initialized.\r
+ Otherwise the SDRAM must be configured. */\r
+ BSP_SDRAM_Init();\r
+#endif\r
+\r
+ /* Initialize the font */\r
+ BSP_LCD_SetFont(&LCD_DEFAULT_FONT);\r
+\r
+ /* Initialize TIM in PWM mode to control brightness */\r
+ TIMx_PWM_Init(&LCD_TimHandle);\r
+\r
+ return LCD_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the LCD.\r
+ * @retval LCD state\r
+ */\r
+uint8_t BSP_LCD_DeInit(void)\r
+{\r
+ /* Initialize the hltdc_discovery Instance parameter */\r
+ hltdc_discovery.Instance = LTDC;\r
+\r
+ /* Disable LTDC block */\r
+ __HAL_LTDC_DISABLE(&hltdc_discovery);\r
+\r
+ /* DeInit the LTDC */\r
+ HAL_LTDC_DeInit(&hltdc_discovery);\r
+\r
+ /* DeInit the LTDC MSP : this __weak function can be rewritten by the application */\r
+ BSP_LCD_MspDeInit(&hltdc_discovery, NULL);\r
+\r
+ /* DeInit TIM PWM */\r
+ TIMx_PWM_DeInit(&LCD_TimHandle);\r
+\r
+ return LCD_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets the LCD X size.\r
+ * @retval Used LCD X size\r
+ */\r
+uint32_t BSP_LCD_GetXSize(void)\r
+{\r
+ return hltdc_discovery.LayerCfg[ActiveLayer].ImageWidth;\r
+}\r
+\r
+/**\r
+ * @brief Gets the LCD Y size.\r
+ * @retval Used LCD Y size\r
+ */\r
+uint32_t BSP_LCD_GetYSize(void)\r
+{\r
+ return hltdc_discovery.LayerCfg[ActiveLayer].ImageHeight;\r
+}\r
+\r
+/**\r
+ * @brief Set the LCD X size.\r
+ * @param imageWidthPixels : image width in pixels unit\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetXSize(uint32_t imageWidthPixels)\r
+{\r
+ hltdc_discovery.LayerCfg[ActiveLayer].ImageWidth = imageWidthPixels;\r
+}\r
+\r
+/**\r
+ * @brief Set the LCD Y size.\r
+ * @param imageHeightPixels : image height in lines unit\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetYSize(uint32_t imageHeightPixels)\r
+{\r
+ hltdc_discovery.LayerCfg[ActiveLayer].ImageHeight = imageHeightPixels;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LCD layers.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @param FB_Address: Layer frame buffer\r
+ * @retval None\r
+ */\r
+void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address)\r
+{\r
+ LCD_LayerCfgTypeDef layer_cfg;\r
+\r
+ /* Layer Init */\r
+ layer_cfg.WindowX0 = 0;\r
+ layer_cfg.WindowX1 = BSP_LCD_GetXSize();\r
+ layer_cfg.WindowY0 = 0;\r
+ layer_cfg.WindowY1 = BSP_LCD_GetYSize();\r
+ layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;\r
+ layer_cfg.FBStartAdress = FB_Address;\r
+ layer_cfg.Alpha = 255;\r
+ layer_cfg.Alpha0 = 0;\r
+ layer_cfg.Backcolor.Blue = 0;\r
+ layer_cfg.Backcolor.Green = 0;\r
+ layer_cfg.Backcolor.Red = 0;\r
+ layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;\r
+ layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;\r
+ layer_cfg.ImageWidth = BSP_LCD_GetXSize();\r
+ layer_cfg.ImageHeight = BSP_LCD_GetYSize();\r
+\r
+ HAL_LTDC_ConfigLayer(&hltdc_discovery, &layer_cfg, LayerIndex);\r
+\r
+ DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE;\r
+ DrawProp[LayerIndex].pFont = &Font24;\r
+ DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK;\r
+}\r
+\r
+/**\r
+ * @brief Selects the LCD Layer.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SelectLayer(uint32_t LayerIndex)\r
+{\r
+ ActiveLayer = LayerIndex;\r
+}\r
+\r
+/**\r
+ * @brief Sets an LCD Layer visible\r
+ * @param LayerIndex: Visible Layer\r
+ * @param State: New state of the specified layer\r
+ * This parameter can be one of the following values:\r
+ * @arg ENABLE\r
+ * @arg DISABLE\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetLayerVisible(uint32_t LayerIndex, FunctionalState State)\r
+{\r
+ if(State == ENABLE)\r
+ {\r
+ __HAL_LTDC_LAYER_ENABLE(&hltdc_discovery, LayerIndex);\r
+ }\r
+ else\r
+ {\r
+ __HAL_LTDC_LAYER_DISABLE(&hltdc_discovery, LayerIndex);\r
+ }\r
+ __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(&(hltdc_discovery));\r
+}\r
+\r
+/**\r
+ * @brief Sets an LCD Layer visible without reloading.\r
+ * @param LayerIndex: Visible Layer\r
+ * @param State: New state of the specified layer\r
+ * This parameter can be one of the following values:\r
+ * @arg ENABLE\r
+ * @arg DISABLE\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetLayerVisible_NoReload(uint32_t LayerIndex, FunctionalState State)\r
+{\r
+ if(State == ENABLE)\r
+ {\r
+ __HAL_LTDC_LAYER_ENABLE(&hltdc_discovery, LayerIndex);\r
+ }\r
+ else\r
+ {\r
+ __HAL_LTDC_LAYER_DISABLE(&hltdc_discovery, LayerIndex);\r
+ }\r
+ /* Do not Sets the Reload */\r
+}\r
+\r
+/**\r
+ * @brief Configures the transparency.\r
+ * @param LayerIndex: Layer foreground or background.\r
+ * @param Transparency: Transparency\r
+ * This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetTransparency(uint32_t LayerIndex, uint8_t Transparency)\r
+{\r
+ HAL_LTDC_SetAlpha(&hltdc_discovery, Transparency, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Configures the transparency without reloading.\r
+ * @param LayerIndex: Layer foreground or background.\r
+ * @param Transparency: Transparency\r
+ * This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetTransparency_NoReload(uint32_t LayerIndex, uint8_t Transparency)\r
+{\r
+ HAL_LTDC_SetAlpha_NoReload(&hltdc_discovery, Transparency, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Sets an LCD layer frame buffer address.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @param Address: New LCD frame buffer value\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetLayerAddress(uint32_t LayerIndex, uint32_t Address)\r
+{\r
+ HAL_LTDC_SetAddress(&hltdc_discovery, Address, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Sets an LCD layer frame buffer address without reloading.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @param Address: New LCD frame buffer value\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetLayerAddress_NoReload(uint32_t LayerIndex, uint32_t Address)\r
+{\r
+ HAL_LTDC_SetAddress_NoReload(&hltdc_discovery, Address, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Sets display window.\r
+ * @param LayerIndex: Layer index\r
+ * @param Xpos: LCD X position\r
+ * @param Ypos: LCD Y position\r
+ * @param Width: LCD window width\r
+ * @param Height: LCD window height\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetLayerWindow(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)\r
+{\r
+ /* Reconfigure the layer size */\r
+ HAL_LTDC_SetWindowSize(&hltdc_discovery, Width, Height, LayerIndex);\r
+\r
+ /* Reconfigure the layer position */\r
+ HAL_LTDC_SetWindowPosition(&hltdc_discovery, Xpos, Ypos, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Sets display window without reloading.\r
+ * @param LayerIndex: Layer index\r
+ * @param Xpos: LCD X position\r
+ * @param Ypos: LCD Y position\r
+ * @param Width: LCD window width\r
+ * @param Height: LCD window height\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetLayerWindow_NoReload(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)\r
+{\r
+ /* Reconfigure the layer size */\r
+ HAL_LTDC_SetWindowSize_NoReload(&hltdc_discovery, Width, Height, LayerIndex);\r
+\r
+ /* Reconfigure the layer position */\r
+ HAL_LTDC_SetWindowPosition_NoReload(&hltdc_discovery, Xpos, Ypos, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Configures and sets the color keying.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @param RGBValue: Color reference\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetColorKeying(uint32_t LayerIndex, uint32_t RGBValue)\r
+{\r
+ /* Configure and Enable the color Keying for LCD Layer */\r
+ HAL_LTDC_ConfigColorKeying(&hltdc_discovery, RGBValue, LayerIndex);\r
+ HAL_LTDC_EnableColorKeying(&hltdc_discovery, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Configures and sets the color keying without reloading.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @param RGBValue: Color reference\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetColorKeying_NoReload(uint32_t LayerIndex, uint32_t RGBValue)\r
+{\r
+ /* Configure and Enable the color Keying for LCD Layer */\r
+ HAL_LTDC_ConfigColorKeying_NoReload(&hltdc_discovery, RGBValue, LayerIndex);\r
+ HAL_LTDC_EnableColorKeying_NoReload(&hltdc_discovery, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Disables the color keying.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @retval None\r
+ */\r
+void BSP_LCD_ResetColorKeying(uint32_t LayerIndex)\r
+{\r
+ /* Disable the color Keying for LCD Layer */\r
+ HAL_LTDC_DisableColorKeying(&hltdc_discovery, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Disables the color keying without reloading.\r
+ * @param LayerIndex: Layer foreground or background\r
+ * @retval None\r
+ */\r
+void BSP_LCD_ResetColorKeying_NoReload(uint32_t LayerIndex)\r
+{\r
+ /* Disable the color Keying for LCD Layer */\r
+ HAL_LTDC_DisableColorKeying_NoReload(&hltdc_discovery, LayerIndex);\r
+}\r
+\r
+/**\r
+ * @brief Disables the color keying without reloading.\r
+ * @param ReloadType: can be one of the following values\r
+ * - LCD_RELOAD_IMMEDIATE\r
+ * - LCD_RELOAD_VERTICAL_BLANKING\r
+ * @retval None\r
+ */\r
+void BSP_LCD_Relaod(uint32_t ReloadType)\r
+{\r
+ HAL_LTDC_Reload (&hltdc_discovery, ReloadType);\r
+}\r
+\r
+/**\r
+ * @brief Sets the LCD text color.\r
+ * @param Color: Text color code ARGB(8-8-8-8)\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetTextColor(uint32_t Color)\r
+{\r
+ DrawProp[ActiveLayer].TextColor = Color;\r
+}\r
+\r
+/**\r
+ * @brief Gets the LCD text color.\r
+ * @retval Used text color.\r
+ */\r
+uint32_t BSP_LCD_GetTextColor(void)\r
+{\r
+ return DrawProp[ActiveLayer].TextColor;\r
+}\r
+\r
+/**\r
+ * @brief Sets the LCD background color.\r
+ * @param Color: Layer background color code ARGB(8-8-8-8)\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetBackColor(uint32_t Color)\r
+{\r
+ DrawProp[ActiveLayer].BackColor = Color;\r
+}\r
+\r
+/**\r
+ * @brief Gets the LCD background color.\r
+ * @retval Used background color\r
+ */\r
+uint32_t BSP_LCD_GetBackColor(void)\r
+{\r
+ return DrawProp[ActiveLayer].BackColor;\r
+}\r
+\r
+/**\r
+ * @brief Sets the LCD text font.\r
+ * @param fonts: Layer font to be used\r
+ * @retval None\r
+ */\r
+void BSP_LCD_SetFont(sFONT *fonts)\r
+{\r
+ DrawProp[ActiveLayer].pFont = fonts;\r
+}\r
+\r
+/**\r
+ * @brief Gets the LCD text font.\r
+ * @retval Used layer font\r
+ */\r
+sFONT *BSP_LCD_GetFont(void)\r
+{\r
+ return DrawProp[ActiveLayer].pFont;\r
+}\r
+\r
+/**\r
+ * @brief Reads an LCD pixel.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @retval RGB pixel color\r
+ */\r
+uint32_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos)\r
+{\r
+ uint32_t ret = 0;\r
+\r
+ if(hltdc_discovery.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r
+ {\r
+ /* Read data value from SDRAM memory */\r
+ ret = *(__IO uint32_t*) (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos)));\r
+ }\r
+ else if(hltdc_discovery.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r
+ {\r
+ /* Read data value from SDRAM memory */\r
+ ret = (*(__IO uint32_t*) (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) & 0x00FFFFFF);\r
+ }\r
+ else if((hltdc_discovery.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \\r
+ (hltdc_discovery.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\r
+ (hltdc_discovery.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_AL88))\r
+ {\r
+ /* Read data value from SDRAM memory */\r
+ ret = *(__IO uint16_t*) (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos)));\r
+ }\r
+ else\r
+ {\r
+ /* Read data value from SDRAM memory */\r
+ ret = *(__IO uint8_t*) (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos)));\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Clears the hole LCD.\r
+ * @param Color: Color of the background\r
+ * @retval None\r
+ */\r
+void BSP_LCD_Clear(uint32_t Color)\r
+{\r
+ /* Clear the LCD */\r
+ LL_FillBuffer(ActiveLayer, (uint32_t *)(hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color);\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected line.\r
+ * @param Line: Line to be cleared\r
+ * @retval None\r
+ */\r
+void BSP_LCD_ClearStringLine(uint32_t Line)\r
+{\r
+ uint32_t color_backup = DrawProp[ActiveLayer].TextColor;\r
+ DrawProp[ActiveLayer].TextColor = DrawProp[ActiveLayer].BackColor;\r
+\r
+ /* Draw rectangle with background color */\r
+ BSP_LCD_FillRect(0, (Line * DrawProp[ActiveLayer].pFont->Height), BSP_LCD_GetXSize(), DrawProp[ActiveLayer].pFont->Height);\r
+\r
+ DrawProp[ActiveLayer].TextColor = color_backup;\r
+ BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);\r
+}\r
+\r
+/**\r
+ * @brief Displays one character.\r
+ * @param Xpos: Start column address\r
+ * @param Ypos: Line where to display the character shape.\r
+ * @param Ascii: Character ascii code\r
+ * This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii)\r
+{\r
+ DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\\r
+ DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]);\r
+}\r
+\r
+/**\r
+ * @brief Displays characters on the LCD.\r
+ * @param Xpos: X position (in pixel)\r
+ * @param Ypos: Y position (in pixel)\r
+ * @param Text: Pointer to string to display on LCD\r
+ * @param Mode: Display mode\r
+ * This parameter can be one of the following values:\r
+ * @arg CENTER_MODE\r
+ * @arg RIGHT_MODE\r
+ * @arg LEFT_MODE\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode)\r
+{\r
+ uint16_t ref_column = 1, i = 0;\r
+ uint32_t size = 0, xsize = 0;\r
+ uint8_t *ptr = Text;\r
+\r
+ /* Get the text size */\r
+ while (*ptr++) size ++ ;\r
+\r
+ /* Characters number per line */\r
+ xsize = (BSP_LCD_GetXSize()/DrawProp[ActiveLayer].pFont->Width);\r
+\r
+ switch (Mode)\r
+ {\r
+ case CENTER_MODE:\r
+ {\r
+ ref_column = Xpos + ((xsize - size)* DrawProp[ActiveLayer].pFont->Width) / 2;\r
+ break;\r
+ }\r
+ case LEFT_MODE:\r
+ {\r
+ ref_column = Xpos;\r
+ break;\r
+ }\r
+ case RIGHT_MODE:\r
+ {\r
+ ref_column = - Xpos + ((xsize - size)*DrawProp[ActiveLayer].pFont->Width);\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ ref_column = Xpos;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Check that the Start column is located in the screen */\r
+ if ((ref_column < 1) || (ref_column >= 0x8000))\r
+ {\r
+ ref_column = 1;\r
+ }\r
+\r
+ /* Send the string character by character on LCD */\r
+ while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width))\r
+ {\r
+ /* Display one character on LCD */\r
+ BSP_LCD_DisplayChar(ref_column, Ypos, *Text);\r
+ /* Decrement the column position by 16 */\r
+ ref_column += DrawProp[ActiveLayer].pFont->Width;\r
+ /* Point on the next character */\r
+ Text++;\r
+ i++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Displays a maximum of 60 characters on the LCD.\r
+ * @param Line: Line where to display the character shape\r
+ * @param ptr: Pointer to string to display on LCD\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr)\r
+{\r
+ BSP_LCD_DisplayStringAt(0, LINE(Line), ptr, LEFT_MODE);\r
+}\r
+\r
+/**\r
+ * @brief Draws an horizontal line.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param Length: Line length\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)\r
+{\r
+ uint32_t Xaddress = 0;\r
+\r
+ /* Get the line address */\r
+ Xaddress = (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);\r
+\r
+ /* Write line */\r
+ LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor);\r
+}\r
+\r
+/**\r
+ * @brief Draws a vertical line.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param Length: Line length\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)\r
+{\r
+ uint32_t Xaddress = 0;\r
+\r
+ /* Get the line address */\r
+ Xaddress = (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);\r
+\r
+ /* Write line */\r
+ LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, 1, Length, (BSP_LCD_GetXSize() - 1), DrawProp[ActiveLayer].TextColor);\r
+}\r
+\r
+/**\r
+ * @brief Draws an uni-line (between two points).\r
+ * @param x1: Point 1 X position\r
+ * @param y1: Point 1 Y position\r
+ * @param x2: Point 2 X position\r
+ * @param y2: Point 2 Y position\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)\r
+{\r
+ int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,\r
+ yinc1 = 0, yinc2 = 0, den = 0, num = 0, num_add = 0, num_pixels = 0,\r
+ curpixel = 0;\r
+\r
+ deltax = ABS(x2 - x1); /* The difference between the x's */\r
+ deltay = ABS(y2 - y1); /* The difference between the y's */\r
+ x = x1; /* Start x off at the first pixel */\r
+ y = y1; /* Start y off at the first pixel */\r
+\r
+ if (x2 >= x1) /* The x-values are increasing */\r
+ {\r
+ xinc1 = 1;\r
+ xinc2 = 1;\r
+ }\r
+ else /* The x-values are decreasing */\r
+ {\r
+ xinc1 = -1;\r
+ xinc2 = -1;\r
+ }\r
+\r
+ if (y2 >= y1) /* The y-values are increasing */\r
+ {\r
+ yinc1 = 1;\r
+ yinc2 = 1;\r
+ }\r
+ else /* The y-values are decreasing */\r
+ {\r
+ yinc1 = -1;\r
+ yinc2 = -1;\r
+ }\r
+\r
+ if (deltax >= deltay) /* There is at least one x-value for every y-value */\r
+ {\r
+ xinc1 = 0; /* Don't change the x when numerator >= denominator */\r
+ yinc2 = 0; /* Don't change the y for every iteration */\r
+ den = deltax;\r
+ num = deltax / 2;\r
+ num_add = deltay;\r
+ num_pixels = deltax; /* There are more x-values than y-values */\r
+ }\r
+ else /* There is at least one y-value for every x-value */\r
+ {\r
+ xinc2 = 0; /* Don't change the x for every iteration */\r
+ yinc1 = 0; /* Don't change the y when numerator >= denominator */\r
+ den = deltay;\r
+ num = deltay / 2;\r
+ num_add = deltax;\r
+ num_pixels = deltay; /* There are more y-values than x-values */\r
+ }\r
+\r
+ for (curpixel = 0; curpixel <= num_pixels; curpixel++)\r
+ {\r
+ BSP_LCD_DrawPixel(x, y, DrawProp[ActiveLayer].TextColor); /* Draw the current pixel */\r
+ num += num_add; /* Increase the numerator by the top of the fraction */\r
+ if (num >= den) /* Check if numerator >= denominator */\r
+ {\r
+ num -= den; /* Calculate the new numerator value */\r
+ x += xinc1; /* Change the x as appropriate */\r
+ y += yinc1; /* Change the y as appropriate */\r
+ }\r
+ x += xinc2; /* Change the x as appropriate */\r
+ y += yinc2; /* Change the y as appropriate */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Draws a rectangle.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param Width: Rectangle width\r
+ * @param Height: Rectangle height\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)\r
+{\r
+ /* Draw horizontal lines */\r
+ BSP_LCD_DrawHLine(Xpos, Ypos, Width);\r
+ BSP_LCD_DrawHLine(Xpos, (Ypos+ Height), Width);\r
+\r
+ /* Draw vertical lines */\r
+ BSP_LCD_DrawVLine(Xpos, Ypos, Height);\r
+ BSP_LCD_DrawVLine((Xpos + Width), Ypos, Height);\r
+}\r
+\r
+/**\r
+ * @brief Draws a circle.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param Radius: Circle radius\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)\r
+{\r
+ int32_t decision; /* Decision Variable */\r
+ uint32_t current_x; /* Current X Value */\r
+ uint32_t current_y; /* Current Y Value */\r
+\r
+ decision = 3 - (Radius << 1);\r
+ current_x = 0;\r
+ current_y = Radius;\r
+\r
+ while (current_x <= current_y)\r
+ {\r
+ BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);\r
+\r
+ BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);\r
+\r
+ BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);\r
+\r
+ BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);\r
+\r
+ BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);\r
+\r
+ BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);\r
+\r
+ BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);\r
+\r
+ BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);\r
+\r
+ if (decision < 0)\r
+ {\r
+ decision += (current_x << 2) + 6;\r
+ }\r
+ else\r
+ {\r
+ decision += ((current_x - current_y) << 2) + 10;\r
+ current_y--;\r
+ }\r
+ current_x++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Draws an poly-line (between many points).\r
+ * @param Points: Pointer to the points array\r
+ * @param PointCount: Number of points\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawPolygon(pPoint Points, uint16_t PointCount)\r
+{\r
+ int16_t x = 0, y = 0;\r
+\r
+ if(PointCount < 2)\r
+ {\r
+ return;\r
+ }\r
+\r
+ BSP_LCD_DrawLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);\r
+\r
+ while(--PointCount)\r
+ {\r
+ x = Points->X;\r
+ y = Points->Y;\r
+ Points++;\r
+ BSP_LCD_DrawLine(x, y, Points->X, Points->Y);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Draws an ellipse on LCD.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param XRadius: Ellipse X radius\r
+ * @param YRadius: Ellipse Y radius\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius)\r
+{\r
+ int x = 0, y = -YRadius, err = 2-2*XRadius, e2;\r
+ float k = 0, rad1 = 0, rad2 = 0;\r
+\r
+ rad1 = XRadius;\r
+ rad2 = YRadius;\r
+\r
+ k = (float)(rad2/rad1);\r
+\r
+ do {\r
+ BSP_LCD_DrawPixel((Xpos-(uint16_t)(x/k)), (Ypos+y), DrawProp[ActiveLayer].TextColor);\r
+ BSP_LCD_DrawPixel((Xpos+(uint16_t)(x/k)), (Ypos+y), DrawProp[ActiveLayer].TextColor);\r
+ BSP_LCD_DrawPixel((Xpos+(uint16_t)(x/k)), (Ypos-y), DrawProp[ActiveLayer].TextColor);\r
+ BSP_LCD_DrawPixel((Xpos-(uint16_t)(x/k)), (Ypos-y), DrawProp[ActiveLayer].TextColor);\r
+\r
+ e2 = err;\r
+ if (e2 <= x) {\r
+ err += ++x*2+1;\r
+ if (-y == x && e2 <= y) e2 = 0;\r
+ }\r
+ if (e2 > y) err += ++y*2+1;\r
+ }\r
+ while (y <= 0);\r
+}\r
+\r
+/**\r
+ * @brief Draws a pixel on LCD.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param RGB_Code: Pixel color in ARGB mode (8-8-8-8)\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code)\r
+{\r
+ /* Write data value to all SDRAM memory */\r
+ *(__IO uint32_t*) (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;\r
+}\r
+\r
+/**\r
+ * @brief Draws a bitmap picture loaded in the internal Flash (32 bpp).\r
+ * @param Xpos: Bmp X position in the LCD\r
+ * @param Ypos: Bmp Y position in the LCD\r
+ * @param pbmp: Pointer to Bmp picture address in the internal Flash\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)\r
+{\r
+ uint32_t index = 0, width = 0, height = 0, bit_pixel = 0;\r
+ uint32_t address;\r
+ uint32_t input_color_mode = 0;\r
+\r
+ /* Get bitmap data address offset */\r
+ index = pbmp[10] + (pbmp[11] << 8) + (pbmp[12] << 16) + (pbmp[13] << 24);\r
+\r
+ /* Read bitmap width */\r
+ width = pbmp[18] + (pbmp[19] << 8) + (pbmp[20] << 16) + (pbmp[21] << 24);\r
+\r
+ /* Read bitmap height */\r
+ height = pbmp[22] + (pbmp[23] << 8) + (pbmp[24] << 16) + (pbmp[25] << 24);\r
+\r
+ /* Read bit/pixel */\r
+ bit_pixel = pbmp[28] + (pbmp[29] << 8);\r
+\r
+ /* Set the address */\r
+ address = hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress + (((BSP_LCD_GetXSize()*Ypos) + Xpos)*(4));\r
+\r
+ /* Get the layer pixel format */\r
+ if ((bit_pixel/8) == 4)\r
+ {\r
+ input_color_mode = DMA2D_INPUT_ARGB8888;\r
+ }\r
+ else if ((bit_pixel/8) == 2)\r
+ {\r
+ input_color_mode = DMA2D_INPUT_RGB565;\r
+ }\r
+ else\r
+ {\r
+ input_color_mode = DMA2D_INPUT_RGB888;\r
+ }\r
+\r
+ /* Bypass the bitmap header */\r
+ pbmp += (index + (width * (height - 1) * (bit_pixel/8)));\r
+\r
+ /* Convert picture to ARGB8888 pixel format */\r
+ for(index=0; index < height; index++)\r
+ {\r
+ /* Pixel format conversion */\r
+ LL_ConvertLineToARGB8888((uint32_t *)pbmp, (uint32_t *)address, width, input_color_mode);\r
+\r
+ /* Increment the source and destination buffers */\r
+ address+= (BSP_LCD_GetXSize()*4);\r
+ pbmp -= width*(bit_pixel/8);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Draws a full rectangle.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param Width: Rectangle width\r
+ * @param Height: Rectangle height\r
+ * @retval None\r
+ */\r
+void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)\r
+{\r
+ uint32_t x_address = 0;\r
+\r
+ /* Set the text color */\r
+ BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);\r
+\r
+ /* Get the rectangle start address */\r
+ x_address = (hltdc_discovery.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);\r
+\r
+ /* Fill the rectangle */\r
+ LL_FillBuffer(ActiveLayer, (uint32_t *)x_address, Width, Height, (BSP_LCD_GetXSize() - Width), DrawProp[ActiveLayer].TextColor);\r
+}\r
+\r
+/**\r
+ * @brief Draws a full circle.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param Radius: Circle radius\r
+ * @retval None\r
+ */\r
+void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)\r
+{\r
+ int32_t decision; /* Decision Variable */\r
+ uint32_t current_x; /* Current X Value */\r
+ uint32_t current_y; /* Current Y Value */\r
+\r
+ decision = 3 - (Radius << 1);\r
+\r
+ current_x = 0;\r
+ current_y = Radius;\r
+\r
+ BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);\r
+\r
+ while (current_x <= current_y)\r
+ {\r
+ if(current_y > 0)\r
+ {\r
+ BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y);\r
+ BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y);\r
+ }\r
+\r
+ if(current_x > 0)\r
+ {\r
+ BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x);\r
+ BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x);\r
+ }\r
+ if (decision < 0)\r
+ {\r
+ decision += (current_x << 2) + 6;\r
+ }\r
+ else\r
+ {\r
+ decision += ((current_x - current_y) << 2) + 10;\r
+ current_y--;\r
+ }\r
+ current_x++;\r
+ }\r
+\r
+ BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);\r
+ BSP_LCD_DrawCircle(Xpos, Ypos, Radius);\r
+}\r
+\r
+/**\r
+ * @brief Draws a full poly-line (between many points).\r
+ * @param Points: Pointer to the points array\r
+ * @param PointCount: Number of points\r
+ * @retval None\r
+ */\r
+void BSP_LCD_FillPolygon(pPoint Points, uint16_t PointCount)\r
+{\r
+ int16_t X = 0, Y = 0, X2 = 0, Y2 = 0, X_center = 0, Y_center = 0, X_first = 0, Y_first = 0, pixelX = 0, pixelY = 0, counter = 0;\r
+ uint16_t image_left = 0, image_right = 0, image_top = 0, image_bottom = 0;\r
+\r
+ image_left = image_right = Points->X;\r
+ image_top= image_bottom = Points->Y;\r
+\r
+ for(counter = 1; counter < PointCount; counter++)\r
+ {\r
+ pixelX = POLY_X(counter);\r
+ if(pixelX < image_left)\r
+ {\r
+ image_left = pixelX;\r
+ }\r
+ if(pixelX > image_right)\r
+ {\r
+ image_right = pixelX;\r
+ }\r
+\r
+ pixelY = POLY_Y(counter);\r
+ if(pixelY < image_top)\r
+ {\r
+ image_top = pixelY;\r
+ }\r
+ if(pixelY > image_bottom)\r
+ {\r
+ image_bottom = pixelY;\r
+ }\r
+ }\r
+\r
+ if(PointCount < 2)\r
+ {\r
+ return;\r
+ }\r
+\r
+ X_center = (image_left + image_right)/2;\r
+ Y_center = (image_bottom + image_top)/2;\r
+\r
+ X_first = Points->X;\r
+ Y_first = Points->Y;\r
+\r
+ while(--PointCount)\r
+ {\r
+ X = Points->X;\r
+ Y = Points->Y;\r
+ Points++;\r
+ X2 = Points->X;\r
+ Y2 = Points->Y;\r
+\r
+ FillTriangle(X, X2, X_center, Y, Y2, Y_center);\r
+ FillTriangle(X, X_center, X2, Y, Y_center, Y2);\r
+ FillTriangle(X_center, X2, X, Y_center, Y2, Y);\r
+ }\r
+\r
+ FillTriangle(X_first, X2, X_center, Y_first, Y2, Y_center);\r
+ FillTriangle(X_first, X_center, X2, Y_first, Y_center, Y2);\r
+ FillTriangle(X_center, X2, X_first, Y_center, Y2, Y_first);\r
+}\r
+\r
+/**\r
+ * @brief Draws a full ellipse.\r
+ * @param Xpos: X position\r
+ * @param Ypos: Y position\r
+ * @param XRadius: Ellipse X radius\r
+ * @param YRadius: Ellipse Y radius\r
+ * @retval None\r
+ */\r
+void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius)\r
+{\r
+ int x = 0, y = -YRadius, err = 2-2*XRadius, e2;\r
+ float k = 0, rad1 = 0, rad2 = 0;\r
+\r
+ rad1 = XRadius;\r
+ rad2 = YRadius;\r
+\r
+ k = (float)(rad2/rad1);\r
+\r
+ do\r
+ {\r
+ BSP_LCD_DrawHLine((Xpos-(uint16_t)(x/k)), (Ypos+y), (2*(uint16_t)(x/k) + 1));\r
+ BSP_LCD_DrawHLine((Xpos-(uint16_t)(x/k)), (Ypos-y), (2*(uint16_t)(x/k) + 1));\r
+\r
+ e2 = err;\r
+ if (e2 <= x)\r
+ {\r
+ err += ++x*2+1;\r
+ if (-y == x && e2 <= y) e2 = 0;\r
+ }\r
+ if (e2 > y) err += ++y*2+1;\r
+ }\r
+ while (y <= 0);\r
+}\r
+\r
+/**\r
+ * @brief Enables the display.\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DisplayOn(void)\r
+{\r
+ /* Display On */\r
+ __HAL_LTDC_ENABLE(&hltdc_discovery);\r
+}\r
+\r
+/**\r
+ * @brief Disables the display.\r
+ * @retval None\r
+ */\r
+void BSP_LCD_DisplayOff(void)\r
+{\r
+ /* Display Off */\r
+ __HAL_LTDC_DISABLE(&hltdc_discovery);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LTDC MSP.\r
+ * @param hltdc: LTDC handle\r
+ * @param Params: Pointer to void\r
+ * @retval None\r
+ */\r
+__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ /* Enable the LTDC and DMA2D clocks */\r
+ __HAL_RCC_LTDC_CLK_ENABLE();\r
+ __HAL_RCC_DMA2D_CLK_ENABLE();\r
+\r
+ /* Enable GPIOs clock */\r
+ __HAL_RCC_GPIOI_CLK_ENABLE();\r
+ __HAL_RCC_GPIOJ_CLK_ENABLE();\r
+ __HAL_RCC_GPIOK_CLK_ENABLE();\r
+ __HAL_RCC_GPIOH_CLK_ENABLE();\r
+ __HAL_RCC_GPIOD_CLK_ENABLE();\r
+ /*** LTDC Pins configuration ***/\r
+ /* GPIOI configuration */\r
+ gpio_init_structure.Pin = GPIO_PIN_0 |GPIO_PIN_1 |GPIO_PIN_9 |GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_15;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;\r
+ gpio_init_structure.Alternate = GPIO_AF14_LTDC;\r
+ HAL_GPIO_Init(GPIOI, &gpio_init_structure);\r
+\r
+ /* GPIOJ configuration */\r
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | \\r
+ GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \\r
+ GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \\r
+ GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;\r
+ gpio_init_structure.Alternate = GPIO_AF14_LTDC;\r
+ HAL_GPIO_Init(GPIOJ, &gpio_init_structure);\r
+\r
+ /* GPIOK configuration */\r
+ gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | \\r
+ GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 ;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;\r
+ gpio_init_structure.Alternate = GPIO_AF14_LTDC;\r
+ HAL_GPIO_Init(GPIOK, &gpio_init_structure);\r
+ \r
+ /* GPIOH configuration */\r
+ gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_1;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH;\r
+ gpio_init_structure.Alternate = GPIO_AF14_LTDC;\r
+ HAL_GPIO_Init(GPIOH, &gpio_init_structure);\r
+\r
+ \r
+ gpio_init_structure.Pin = GPIO_PIN_7; /* LCD_DISP pin has to be manually controlled */\r
+ gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;\r
+ HAL_GPIO_Init(GPIOD, &gpio_init_structure); \r
+ /* Assert display enable LCD_DISP pin */\r
+ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes BSP_LCD MSP.\r
+ * @param hltdc: LTDC handle\r
+ * @param Params: Pointer to void\r
+ * @retval None\r
+ */\r
+__weak void BSP_LCD_MspDeInit(LTDC_HandleTypeDef *hltdc, void *Params)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ /* Disable LTDC block */\r
+ __HAL_LTDC_DISABLE(hltdc);\r
+\r
+ /* LTDC Pins deactivation */\r
+ /* GPIOI deactivation */\r
+ gpio_init_structure.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;\r
+ HAL_GPIO_DeInit(GPIOI, gpio_init_structure.Pin);\r
+ /* GPIOJ deactivation */\r
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \\r
+ GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \\r
+ GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \\r
+ GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;\r
+ HAL_GPIO_DeInit(GPIOJ, gpio_init_structure.Pin);\r
+ /* GPIOK deactivation */\r
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \\r
+ GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;\r
+ HAL_GPIO_DeInit(GPIOK, gpio_init_structure.Pin);\r
+\r
+ /* Disable LTDC clock */\r
+ __HAL_RCC_LTDC_CLK_DISABLE();\r
+\r
+ /* GPIO pins clock can be shut down in the application\r
+ by surcharging this __weak function */\r
+}\r
+\r
+/**\r
+ * @brief Clock Config.\r
+ * @param hltdc: LTDC handle\r
+ * @param Params: Pointer to void\r
+ * @note This API is called by BSP_LCD_Init()\r
+ * Being __weak it can be overwritten by the application\r
+ * @retval None\r
+ */\r
+__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params)\r
+{\r
+ static RCC_PeriphCLKInitTypeDef periph_clk_init_struct;\r
+\r
+ /* RK043FN48H LCD clock configuration */\r
+ /* LCD clock configuration */\r
+ /* PLL3_VCO Input = HSE_VALUE/PLL3M = 5 Mhz */\r
+ /* PLL3_VCO Output = PLL3_VCO Input * PLL3N = 800 Mhz */\r
+ /* PLLLCDCLK = PLL3_VCO Output/PLL3R = 800/83 = 9.63 Mhz */\r
+ /* LTDC clock frequency = PLLLCDCLK = 9.63 Mhz */\r
+ periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;\r
+ periph_clk_init_struct.PLL3.PLL3M = 5;\r
+ periph_clk_init_struct.PLL3.PLL3N = 160;\r
+ periph_clk_init_struct.PLL3.PLL3P = 2;\r
+ periph_clk_init_struct.PLL3.PLL3Q = 2;\r
+ periph_clk_init_struct.PLL3.PLL3R = 83;\r
+ HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct);\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Set the brightness value\r
+ * @param BrightnessValue: [00: Min (black), 100 Max]\r
+ */\r
+void BSP_LCD_SetBrightness(uint8_t BrightnessValue)\r
+{\r
+ /* Timer Configuration */\r
+ TIM_OC_InitTypeDef LCD_TIM_Config;\r
+\r
+ /* Stop PWM Timer channel */\r
+ HAL_TIM_PWM_Stop(&LCD_TimHandle, LCD_TIMx_CHANNEL);\r
+\r
+ /* Common configuration for all channels */\r
+ LCD_TIM_Config.OCMode = TIM_OCMODE_PWM1;\r
+ LCD_TIM_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
+ LCD_TIM_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
+ LCD_TIM_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
+ LCD_TIM_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
+ LCD_TIM_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
+\r
+ /* Set the pulse value for channel */\r
+ LCD_TIM_Config.Pulse = (uint32_t)((LCD_TIMX_PERIOD_VALUE * BrightnessValue) / 100);\r
+\r
+ HAL_TIM_PWM_ConfigChannel(&LCD_TimHandle, &LCD_TIM_Config, LCD_TIMx_CHANNEL);\r
+\r
+ /* Start PWM Timer channel */\r
+ HAL_TIM_PWM_Start(&LCD_TimHandle, LCD_TIMx_CHANNEL);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*******************************************************************************\r
+ Static Functions\r
+*******************************************************************************/\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Private_Functions Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Draws a character on LCD.\r
+ * @param Xpos: Line where to display the character shape\r
+ * @param Ypos: Start column address\r
+ * @param c: Pointer to the character data\r
+ * @retval None\r
+ */\r
+static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c)\r
+{\r
+ uint32_t i = 0, j = 0;\r
+ uint16_t height, width;\r
+ uint8_t offset;\r
+ uint8_t *pchar;\r
+ uint32_t line;\r
+\r
+ height = DrawProp[ActiveLayer].pFont->Height;\r
+ width = DrawProp[ActiveLayer].pFont->Width;\r
+\r
+ offset = 8 *((width + 7)/8) - width ;\r
+\r
+ for(i = 0; i < height; i++)\r
+ {\r
+ pchar = ((uint8_t *)c + (width + 7)/8 * i);\r
+\r
+ switch(((width + 7)/8))\r
+ {\r
+\r
+ case 1:\r
+ line = pchar[0];\r
+ break;\r
+\r
+ case 2:\r
+ line = (pchar[0]<< 8) | pchar[1];\r
+ break;\r
+\r
+ case 3:\r
+ default:\r
+ line = (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2];\r
+ break;\r
+ }\r
+\r
+ for (j = 0; j < width; j++)\r
+ {\r
+ if(line & (1 << (width- j + offset- 1)))\r
+ {\r
+ BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].TextColor);\r
+ }\r
+ else\r
+ {\r
+ BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].BackColor);\r
+ }\r
+ }\r
+ Ypos++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills a triangle (between 3 points).\r
+ * @param x1: Point 1 X position\r
+ * @param y1: Point 1 Y position\r
+ * @param x2: Point 2 X position\r
+ * @param y2: Point 2 Y position\r
+ * @param x3: Point 3 X position\r
+ * @param y3: Point 3 Y position\r
+ * @retval None\r
+ */\r
+static void FillTriangle(uint16_t x1, uint16_t x2, uint16_t x3, uint16_t y1, uint16_t y2, uint16_t y3)\r
+{\r
+ int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,\r
+ yinc1 = 0, yinc2 = 0, den = 0, num = 0, num_add = 0, num_pixels = 0,\r
+ curpixel = 0;\r
+\r
+ deltax = ABS(x2 - x1); /* The difference between the x's */\r
+ deltay = ABS(y2 - y1); /* The difference between the y's */\r
+ x = x1; /* Start x off at the first pixel */\r
+ y = y1; /* Start y off at the first pixel */\r
+\r
+ if (x2 >= x1) /* The x-values are increasing */\r
+ {\r
+ xinc1 = 1;\r
+ xinc2 = 1;\r
+ }\r
+ else /* The x-values are decreasing */\r
+ {\r
+ xinc1 = -1;\r
+ xinc2 = -1;\r
+ }\r
+\r
+ if (y2 >= y1) /* The y-values are increasing */\r
+ {\r
+ yinc1 = 1;\r
+ yinc2 = 1;\r
+ }\r
+ else /* The y-values are decreasing */\r
+ {\r
+ yinc1 = -1;\r
+ yinc2 = -1;\r
+ }\r
+\r
+ if (deltax >= deltay) /* There is at least one x-value for every y-value */\r
+ {\r
+ xinc1 = 0; /* Don't change the x when numerator >= denominator */\r
+ yinc2 = 0; /* Don't change the y for every iteration */\r
+ den = deltax;\r
+ num = deltax / 2;\r
+ num_add = deltay;\r
+ num_pixels = deltax; /* There are more x-values than y-values */\r
+ }\r
+ else /* There is at least one y-value for every x-value */\r
+ {\r
+ xinc2 = 0; /* Don't change the x for every iteration */\r
+ yinc1 = 0; /* Don't change the y when numerator >= denominator */\r
+ den = deltay;\r
+ num = deltay / 2;\r
+ num_add = deltax;\r
+ num_pixels = deltay; /* There are more y-values than x-values */\r
+ }\r
+\r
+ for (curpixel = 0; curpixel <= num_pixels; curpixel++)\r
+ {\r
+ BSP_LCD_DrawLine(x, y, x3, y3);\r
+\r
+ num += num_add; /* Increase the numerator by the top of the fraction */\r
+ if (num >= den) /* Check if numerator >= denominator */\r
+ {\r
+ num -= den; /* Calculate the new numerator value */\r
+ x += xinc1; /* Change the x as appropriate */\r
+ y += yinc1; /* Change the y as appropriate */\r
+ }\r
+ x += xinc2; /* Change the x as appropriate */\r
+ y += yinc2; /* Change the y as appropriate */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills a buffer.\r
+ * @param LayerIndex: Layer index\r
+ * @param pDst: Pointer to destination buffer\r
+ * @param xSize: Buffer width\r
+ * @param ySize: Buffer height\r
+ * @param OffLine: Offset\r
+ * @param ColorIndex: Color index\r
+ * @retval None\r
+ */\r
+static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex)\r
+{\r
+ /* Register to memory mode with ARGB8888 as color Mode */\r
+ hdma2d_discovery.Init.Mode = DMA2D_R2M;\r
+ hdma2d_discovery.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;\r
+ hdma2d_discovery.Init.OutputOffset = OffLine;\r
+\r
+ hdma2d_discovery.Instance = DMA2D;\r
+\r
+ /* DMA2D Initialization */\r
+ if(HAL_DMA2D_Init(&hdma2d_discovery) == HAL_OK)\r
+ {\r
+ if(HAL_DMA2D_ConfigLayer(&hdma2d_discovery, 1) == HAL_OK)\r
+ {\r
+ if (HAL_DMA2D_Start(&hdma2d_discovery, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK)\r
+ {\r
+ /* Polling For DMA transfer */\r
+ HAL_DMA2D_PollForTransfer(&hdma2d_discovery, 20);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Converts a line to an ARGB8888 pixel format.\r
+ * @param pSrc: Pointer to source buffer\r
+ * @param pDst: Output color\r
+ * @param xSize: Buffer width\r
+ * @param ColorMode: Input color mode\r
+ * @retval None\r
+ */\r
+static void LL_ConvertLineToARGB8888(void *pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode)\r
+{\r
+ /* Configure the DMA2D Mode, Color Mode and output offset */\r
+ hdma2d_discovery.Init.Mode = DMA2D_M2M_PFC;\r
+ hdma2d_discovery.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;\r
+ hdma2d_discovery.Init.OutputOffset = 0;\r
+\r
+ /* Foreground Configuration */\r
+ hdma2d_discovery.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;\r
+ hdma2d_discovery.LayerCfg[1].InputAlpha = 0xFF;\r
+ hdma2d_discovery.LayerCfg[1].InputColorMode = ColorMode;\r
+ hdma2d_discovery.LayerCfg[1].InputOffset = 0;\r
+\r
+ hdma2d_discovery.Instance = DMA2D;\r
+\r
+ /* DMA2D Initialization */\r
+ if(HAL_DMA2D_Init(&hdma2d_discovery) == HAL_OK)\r
+ {\r
+ if(HAL_DMA2D_ConfigLayer(&hdma2d_discovery, 1) == HAL_OK)\r
+ {\r
+ if (HAL_DMA2D_Start(&hdma2d_discovery, (uint32_t)pSrc, (uint32_t)pDst, xSize, 1) == HAL_OK)\r
+ {\r
+ /* Polling For DMA transfer */\r
+ HAL_DMA2D_PollForTransfer(&hdma2d_discovery, 20);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes TIM MSP.\r
+ * @param htim: TIM handle\r
+ * @retval None\r
+ */\r
+static void TIMx_PWM_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+\r
+ __HAL_RCC_GPIOK_CLK_ENABLE();\r
+\r
+ /* TIMx Peripheral clock enable */\r
+ LCD_TIMx_CLK_ENABLE();\r
+\r
+ /* Timer channel configuration */\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ GPIO_InitStruct.Alternate = LCD_TIMx_CHANNEL_AF;\r
+ GPIO_InitStruct.Pin = GPIO_PIN_0; /* BL_CTRL */\r
+\r
+ HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes TIM MSP.\r
+ * @param htim: TIM handle\r
+ * @retval None\r
+ */\r
+static void TIMx_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+\r
+ /* TIMx Peripheral clock enable */\r
+ LCD_TIMx_CLK_DISABLE();\r
+\r
+ /* Timer channel configuration */\r
+ GPIO_InitStruct.Pin = GPIO_PIN_0; /* BL_CTRL */\r
+ HAL_GPIO_DeInit(GPIOK, GPIO_InitStruct.Pin);\r
+}\r
+\r
+/**\r
+ * @brief Initializes TIM in PWM mode\r
+ * @param htim: TIM handle\r
+ * @retval None\r
+ */\r
+static void TIMx_PWM_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Timer_Clock = 2 x APB2_clock = 200 MHz */\r
+ /* PWM_freq = Timer_Clock /(Period x (Prescaler + 1))*/\r
+ /* PWM_freq = 200 MHz /(50000 x 5) = 800 Hz*/\r
+\r
+ htim->Instance = LCD_TIMx;\r
+ HAL_TIM_PWM_DeInit(htim);\r
+\r
+ TIMx_PWM_MspInit(htim);\r
+\r
+ htim->Init.Prescaler = LCD_TIMX_PRESCALER_VALUE;\r
+ htim->Init.Period = LCD_TIMX_PERIOD_VALUE;\r
+ htim->Init.ClockDivision = 0;\r
+ htim->Init.CounterMode = TIM_COUNTERMODE_UP;\r
+ htim->Init.RepetitionCounter = 0;\r
+\r
+ HAL_TIM_PWM_Init(htim);\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes TIM in PWM mode\r
+ * @param htim: TIM handle\r
+ * @retval None\r
+ */\r
+static void TIMx_PWM_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ htim->Instance = LCD_TIMx;\r
+ /* Timer de-intialization */\r
+ HAL_TIM_PWM_DeInit(htim);\r
+\r
+ /* Timer Msp de-intialization */\r
+ TIMx_PWM_MspDeInit(htim);\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_lcd.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the common defines and functions prototypes for\r
+ * the stm32h745i_discovery_lcd.c driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H745I_DISCOVERY_LCD_H\r
+#define __STM32H745I_DISCOVERY_LCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Include LCD component Driver */\r
+/* LCD RK043FN48H-CT672B 4,3" 480x272 pixels */\r
+#include "../Components/rk043fn48h/rk043fn48h.h"\r
+\r
+/* Include SDRAM Driver */\r
+#include "stm32h745i_discovery_sdram.h"\r
+\r
+#include "stm32h745i_discovery.h"\r
+#include "../../../Utilities/Fonts/fonts.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_LCD\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Exported_Types Exported Types\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TextColor;\r
+ uint32_t BackColor;\r
+ sFONT *pFont;\r
+}LCD_DrawPropTypeDef;\r
+\r
+typedef struct\r
+{\r
+ int16_t X;\r
+ int16_t Y;\r
+}Point, * pPoint;\r
+\r
+/**\r
+ * @brief Line mode structures definition\r
+ */\r
+typedef enum\r
+{\r
+ CENTER_MODE = 0x01, /* Center mode */\r
+ RIGHT_MODE = 0x02, /* Right mode */\r
+ LEFT_MODE = 0x03 /* Left mode */\r
+}Text_AlignModeTypdef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_LCD_Exported_Constants Exported Constants\r
+ * @{\r
+ */\r
+#define MAX_LAYER_NUMBER ((uint32_t)2)\r
+\r
+#define LCD_LayerCfgTypeDef LTDC_LayerCfgTypeDef\r
+\r
+#define LTDC_ACTIVE_LAYER ((uint32_t)1) /* Layer 1 */\r
+/**\r
+ * @brief LCD status structure definition\r
+ */\r
+#define LCD_OK ((uint8_t)0x00)\r
+#define LCD_ERROR ((uint8_t)0x01)\r
+#define LCD_TIMEOUT ((uint8_t)0x02)\r
+\r
+/**\r
+ * @brief LCD FB_StartAddress\r
+ */\r
+#define LCD_FB_START_ADDRESS ((uint32_t)0xD0000000)\r
+\r
+/**\r
+ * @brief LCD color\r
+ */\r
+#define LCD_COLOR_BLUE ((uint32_t)0xFF0000FF)\r
+#define LCD_COLOR_GREEN ((uint32_t)0xFF00FF00)\r
+#define LCD_COLOR_RED ((uint32_t)0xFFFF0000)\r
+#define LCD_COLOR_CYAN ((uint32_t)0xFF00FFFF)\r
+#define LCD_COLOR_MAGENTA ((uint32_t)0xFFFF00FF)\r
+#define LCD_COLOR_YELLOW ((uint32_t)0xFFFFFF00)\r
+#define LCD_COLOR_LIGHTBLUE ((uint32_t)0xFF8080FF)\r
+#define LCD_COLOR_LIGHTGREEN ((uint32_t)0xFF80FF80)\r
+#define LCD_COLOR_LIGHTRED ((uint32_t)0xFFFF8080)\r
+#define LCD_COLOR_LIGHTCYAN ((uint32_t)0xFF80FFFF)\r
+#define LCD_COLOR_LIGHTMAGENTA ((uint32_t)0xFFFF80FF)\r
+#define LCD_COLOR_LIGHTYELLOW ((uint32_t)0xFFFFFF80)\r
+#define LCD_COLOR_DARKBLUE ((uint32_t)0xFF000080)\r
+#define LCD_COLOR_DARKGREEN ((uint32_t)0xFF008000)\r
+#define LCD_COLOR_DARKRED ((uint32_t)0xFF800000)\r
+#define LCD_COLOR_DARKCYAN ((uint32_t)0xFF008080)\r
+#define LCD_COLOR_DARKMAGENTA ((uint32_t)0xFF800080)\r
+#define LCD_COLOR_DARKYELLOW ((uint32_t)0xFF808000)\r
+#define LCD_COLOR_WHITE ((uint32_t)0xFFFFFFFF)\r
+#define LCD_COLOR_LIGHTGRAY ((uint32_t)0xFFD3D3D3)\r
+#define LCD_COLOR_GRAY ((uint32_t)0xFF808080)\r
+#define LCD_COLOR_DARKGRAY ((uint32_t)0xFF404040)\r
+#define LCD_COLOR_BLACK ((uint32_t)0xFF000000)\r
+#define LCD_COLOR_BROWN ((uint32_t)0xFFA52A2A)\r
+#define LCD_COLOR_ORANGE ((uint32_t)0xFFFFA500)\r
+#define LCD_COLOR_TRANSPARENT ((uint32_t)0xFF000000)\r
+\r
+/**\r
+ * @brief LCD default font\r
+ */\r
+#define LCD_DEFAULT_FONT Font24\r
+\r
+/**\r
+ * @brief LCD Reload Types\r
+ */\r
+#define LCD_RELOAD_IMMEDIATE ((uint32_t)LTDC_SRCR_IMR)\r
+#define LCD_RELOAD_VERTICAL_BLANKING ((uint32_t)LTDC_SRCR_VBR)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_LCD_Exported_Functions\r
+ * @{\r
+ */\r
+uint8_t BSP_LCD_Init(void);\r
+uint8_t BSP_LCD_InitEx(uint32_t PclkConfig);\r
+\r
+uint8_t BSP_LCD_DeInit(void);\r
+uint32_t BSP_LCD_GetXSize(void);\r
+uint32_t BSP_LCD_GetYSize(void);\r
+void BSP_LCD_SetXSize(uint32_t imageWidthPixels);\r
+void BSP_LCD_SetYSize(uint32_t imageHeightPixels);\r
+\r
+/* Functions using the LTDC controller */\r
+void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FrameBuffer);\r
+void BSP_LCD_SetTransparency(uint32_t LayerIndex, uint8_t Transparency);\r
+void BSP_LCD_SetTransparency_NoReload(uint32_t LayerIndex, uint8_t Transparency);\r
+void BSP_LCD_SetLayerAddress(uint32_t LayerIndex, uint32_t Address);\r
+void BSP_LCD_SetLayerAddress_NoReload(uint32_t LayerIndex, uint32_t Address);\r
+void BSP_LCD_SetColorKeying(uint32_t LayerIndex, uint32_t RGBValue);\r
+void BSP_LCD_SetColorKeying_NoReload(uint32_t LayerIndex, uint32_t RGBValue);\r
+void BSP_LCD_ResetColorKeying(uint32_t LayerIndex);\r
+void BSP_LCD_ResetColorKeying_NoReload(uint32_t LayerIndex);\r
+void BSP_LCD_SetLayerWindow(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);\r
+void BSP_LCD_SetLayerWindow_NoReload(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);\r
+void BSP_LCD_SelectLayer(uint32_t LayerIndex);\r
+void BSP_LCD_SetLayerVisible(uint32_t LayerIndex, FunctionalState State);\r
+void BSP_LCD_SetLayerVisible_NoReload(uint32_t LayerIndex, FunctionalState State);\r
+void BSP_LCD_Relaod(uint32_t ReloadType);\r
+\r
+void BSP_LCD_SetTextColor(uint32_t Color);\r
+uint32_t BSP_LCD_GetTextColor(void);\r
+void BSP_LCD_SetBackColor(uint32_t Color);\r
+uint32_t BSP_LCD_GetBackColor(void);\r
+void BSP_LCD_SetFont(sFONT *fonts);\r
+sFONT *BSP_LCD_GetFont(void);\r
+\r
+uint32_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos);\r
+void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t pixel);\r
+void BSP_LCD_Clear(uint32_t Color);\r
+void BSP_LCD_ClearStringLine(uint32_t Line);\r
+void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr);\r
+void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode);\r
+void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii);\r
+\r
+void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);\r
+void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);\r
+void BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);\r
+void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);\r
+void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);\r
+void BSP_LCD_DrawPolygon(pPoint Points, uint16_t PointCount);\r
+void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius);\r
+void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp);\r
+\r
+void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);\r
+void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);\r
+void BSP_LCD_FillPolygon(pPoint Points, uint16_t PointCount);\r
+void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius);\r
+\r
+void BSP_LCD_DisplayOff(void);\r
+void BSP_LCD_DisplayOn(void);\r
+\r
+void BSP_LCD_SetBrightness(uint8_t BrightnessValue);\r
+\r
+/* These functions can be modified in case the current settings\r
+ need to be changed for specific application needs */\r
+void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params);\r
+void BSP_LCD_MspDeInit(LTDC_HandleTypeDef *hltdc, void *Params);\r
+void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H745I_DISCOVERY_LCD_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_mmc.c\r
+ * @author MCD Application Team\r
+ * @brief This file includes the EMMC driver mounted on STM32H745I-DISCOVERY\r
+ * board.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* File Info : -----------------------------------------------------------------\r
+ User NOTES\r
+1. How To use this driver:\r
+--------------------------\r
+ - This driver is used to drive the EMMC mounted on STM32H745I-DISCOVERY\r
+ board.\r
+ - This driver does not need a specific component driver for the EMMC device\r
+ to be included with.\r
+\r
+2. Driver description:\r
+---------------------\r
+ + Initialization steps:\r
+ o Initialize the external EMMC memory using the BSP_MMC_Init() function. This\r
+ function includes the MSP layer hardware resources initialization and the\r
+ SDIO interface configuration to interface with the external EMMC. It\r
+ also includes the EMMC initialization sequence.\r
+ o The function BSP_MMC_GetCardInfo() is used to get the MMC information\r
+ which is stored in the structure "HAL_MMC_CardInfoTypedef".\r
+\r
+ + Micro MMC card operations\r
+ o The micro MMC card can be accessed with read/write block(s) operations once\r
+ it is ready for access. The access can be performed whether using the polling\r
+ mode by calling the functions BSP_MMC_ReadBlocks()/BSP_MMC_WriteBlocks(), or by DMA\r
+ transfer using the functions BSP_MMC_ReadBlocks_DMA()/BSP_MMC_WriteBlocks_DMA()\r
+ o The DMA transfer complete is used with interrupt mode. Once the MMC transfer\r
+ is complete, the MMC interrupt is handled using the function BSP_MMC_IRQHandler(),\r
+ the DMA Tx/Rx transfer complete are handled using the functions\r
+ MMC_DMA_Tx_IRQHandler()/MMC_DMA_Rx_IRQHandler() that should be defined by user.\r
+ The corresponding user callbacks are implemented by the user at application level.\r
+ o The MMC erase block(s) is performed using the function BSP_MMC_Erase() with specifying\r
+ the number of blocks to erase.\r
+ o The MMC runtime status is returned when calling the function BSP_MMC_GetStatus().\r
+\r
+------------------------------------------------------------------------------*/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery_mmc.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_MMC STM32H745I_DISCOVERY_MMC\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Variables Exported Variables\r
+ * @{\r
+ */\r
+MMC_HandleTypeDef uSdHandle;\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Functions Exported Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the MMC card device.\r
+ * @retval MMC status\r
+ */\r
+uint8_t BSP_MMC_Init(void)\r
+{\r
+ uint8_t mmc_state = MMC_OK;\r
+\r
+ /* uMMC device interface configuration */\r
+ uSdHandle.Instance = SDMMC1;\r
+\r
+ /* if CLKDIV = 0 then SDMMC Clock frequency = SDMMC Kernel Clock\r
+ else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV].\r
+ */\r
+ uSdHandle.Init.ClockDiv = 2;\r
+ uSdHandle.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;\r
+ uSdHandle.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;\r
+ uSdHandle.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;\r
+ uSdHandle.Init.BusWide = SDMMC_BUS_WIDE_8B;\r
+\r
+ /* Msp MMC initialization */\r
+ BSP_MMC_MspInit(&uSdHandle, NULL);\r
+\r
+ /* HAL MMC initialization */\r
+ if(HAL_MMC_Init(&uSdHandle) != HAL_OK)\r
+ {\r
+ mmc_state = MMC_ERROR;\r
+ }\r
+\r
+ return mmc_state;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the MMC card device.\r
+ * @retval MMC status\r
+ */\r
+uint8_t BSP_MMC_DeInit(void)\r
+{\r
+ uint8_t mmc_state = MMC_OK;\r
+\r
+ uSdHandle.Instance = SDMMC1;\r
+\r
+ /* HAL MMC deinitialization */\r
+ if(HAL_MMC_DeInit(&uSdHandle) != HAL_OK)\r
+ {\r
+ mmc_state = MMC_ERROR;\r
+ }\r
+\r
+ /* Msp MMC deinitialization */\r
+ uSdHandle.Instance = SDMMC1;\r
+ BSP_MMC_MspDeInit(&uSdHandle, NULL);\r
+\r
+ return mmc_state;\r
+}\r
+\r
+/**\r
+ * @brief Reads block(s) from a specified address in an MMC card, in polling mode.\r
+ * @param pData: Pointer to the buffer that will contain the data to transmit\r
+ * @param ReadAddr: Address from where data is to be read\r
+ * @param NumOfBlocks: Number of MMC blocks to read\r
+ * @param Timeout: Timeout for read operation\r
+ * @retval MMC status\r
+ */\r
+uint8_t BSP_MMC_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)\r
+{\r
+\r
+ if( HAL_MMC_ReadBlocks(&uSdHandle, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) == HAL_OK)\r
+ {\r
+ return MMC_OK;\r
+ }\r
+ else\r
+ {\r
+ return MMC_ERROR;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Writes block(s) to a specified address in an MMC card, in polling mode.\r
+ * @param pData: Pointer to the buffer that will contain the data to transmit\r
+ * @param WriteAddr: Address from where data is to be written\r
+ * @param NumOfBlocks: Number of MMC blocks to write\r
+ * @param Timeout: Timeout for write operation\r
+ * @retval MMC status\r
+ */\r
+uint8_t BSP_MMC_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)\r
+{\r
+\r
+ if( HAL_MMC_WriteBlocks(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) == HAL_OK)\r
+ {\r
+ return MMC_OK;\r
+ }\r
+ else\r
+ {\r
+ return MMC_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Reads block(s) from a specified address in an MMC card, in DMA mode.\r
+ * @param pData: Pointer to the buffer that will contain the data to transmit\r
+ * @param ReadAddr: Address from where data is to be read\r
+ * @param NumOfBlocks: Number of MMC blocks to read\r
+ * @retval MMC status\r
+ */\r
+uint8_t BSP_MMC_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)\r
+{\r
+\r
+ if( HAL_MMC_ReadBlocks_DMA(&uSdHandle, (uint8_t *)pData, ReadAddr, NumOfBlocks) == HAL_OK)\r
+ {\r
+ return MMC_OK;\r
+ }\r
+ else\r
+ {\r
+ return MMC_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes block(s) to a specified address in an MMC card, in DMA mode.\r
+ * @param pData: Pointer to the buffer that will contain the data to transmit\r
+ * @param WriteAddr: Address from where data is to be written\r
+ * @param NumOfBlocks: Number of MMC blocks to write\r
+ * @retval MMC status\r
+ */\r
+uint8_t BSP_MMC_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)\r
+{\r
+\r
+ if( HAL_MMC_WriteBlocks_DMA(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks) == HAL_OK)\r
+ {\r
+ return MMC_OK;\r
+ }\r
+ else\r
+ {\r
+ return MMC_ERROR;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Erases the specified memory area of the given MMC card.\r
+ * @param StartAddr: Start byte address\r
+ * @param EndAddr: End byte address\r
+ * @retval MMC status\r
+ */\r
+uint8_t BSP_MMC_Erase(uint32_t StartAddr, uint32_t EndAddr)\r
+{\r
+\r
+ if( HAL_MMC_Erase(&uSdHandle, StartAddr, EndAddr) == HAL_OK)\r
+ {\r
+ return MMC_OK;\r
+ }\r
+ else\r
+ {\r
+ return MMC_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the MMC MSP.\r
+ * @param hmmc: MMC handle\r
+ * @param Params User parameters\r
+ * @retval None\r
+ */\r
+__weak void BSP_MMC_MspInit(MMC_HandleTypeDef *hmmc, void *Params)\r
+{\r
+ /* __weak function can be modified by the application */\r
+\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ /* Enable SDIO clock */\r
+ __HAL_RCC_SDMMC1_CLK_ENABLE();\r
+\r
+ /* Enable GPIOs clock */\r
+ __HAL_RCC_GPIOB_CLK_ENABLE();\r
+ __HAL_RCC_GPIOC_CLK_ENABLE();\r
+ __HAL_RCC_GPIOD_CLK_ENABLE();\r
+\r
+\r
+ /* Common GPIO configuration */\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_PULLUP;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ gpio_init_structure.Alternate = GPIO_AF12_SDIO1;\r
+\r
+ /* SDMMC GPIO CLKIN PB8, D0 PC8, D1 PC9, D2 PC10, D3 PC11, CK PC12, CMD PD2 */\r
+ /* GPIOC configuration */\r
+ gpio_init_structure.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;\r
+ HAL_GPIO_Init(GPIOC, &gpio_init_structure);\r
+\r
+ /* GPIOD configuration */\r
+ gpio_init_structure.Pin = GPIO_PIN_2;\r
+ HAL_GPIO_Init(GPIOD, &gpio_init_structure);\r
+\r
+ gpio_init_structure.Pin = GPIO_PIN_8 | GPIO_PIN_9;\r
+ HAL_GPIO_Init(GPIOB, &gpio_init_structure);\r
+\r
+\r
+ /* NVIC configuration for SDIO interrupts */\r
+ HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0);\r
+ HAL_NVIC_EnableIRQ(SDMMC1_IRQn);\r
+\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the MMC MSP.\r
+ * @param hmmc: MMC handle\r
+ * @param Params User parameters\r
+ * @retval None\r
+ */\r
+__weak void BSP_MMC_MspDeInit(MMC_HandleTypeDef *hmmc, void *Params)\r
+{\r
+ /* Disable NVIC for SDIO interrupts */\r
+ HAL_NVIC_DisableIRQ(SDMMC1_IRQn);\r
+\r
+ /* DeInit GPIO pins can be done in the application\r
+ (by surcharging this __weak function) */\r
+\r
+ /* Disable SDMMC1 clock */\r
+ __HAL_RCC_SDMMC1_CLK_DISABLE();\r
+\r
+ /* GPIO pins clock and DMA clocks can be shut down in the application\r
+ by surcharging this __weak function */\r
+}\r
+\r
+/**\r
+ * @brief Handles MMC card interrupt request.\r
+ * @retval None\r
+ */\r
+void BSP_MMC_IRQHandler(void)\r
+{\r
+ HAL_MMC_IRQHandler(&uSdHandle);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Gets the current MMC card data status.\r
+ * @retval Data transfer state.\r
+ * This value can be one of the following values:\r
+ * @arg MMC_TRANSFER_OK: No data transfer is acting\r
+ * @arg MMC_TRANSFER_BUSY: Data transfer is acting\r
+ * @arg MMC_TRANSFER_ERROR: Data transfer error\r
+ */\r
+uint8_t BSP_MMC_GetCardState(void)\r
+{\r
+ return((HAL_MMC_GetCardState(&uSdHandle) == HAL_MMC_CARD_TRANSFER ) ? MMC_TRANSFER_OK : MMC_TRANSFER_BUSY);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Get MMC information about specific MMC card.\r
+ * @param CardInfo: Pointer to HAL_MMC_CardInfoTypedef structure\r
+ * @retval None\r
+ */\r
+void BSP_MMC_GetCardInfo(BSP_MMC_CardInfo *CardInfo)\r
+{\r
+ HAL_MMC_GetCardInfo(&uSdHandle, CardInfo);\r
+}\r
+\r
+/**\r
+ * @brief MMC Abort callbacks\r
+ * @param hmmc: MMC handle\r
+ * @retval None\r
+ */\r
+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)\r
+{\r
+ BSP_MMC_AbortCallback();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param hmmc: MMC handle\r
+ * @retval None\r
+ */\r
+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)\r
+{\r
+ BSP_MMC_WriteCpltCallback();\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param hmmc: MMC handle\r
+ * @retval None\r
+ */\r
+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)\r
+{\r
+ BSP_MMC_ReadCpltCallback();\r
+}\r
+\r
+/**\r
+ * @brief BSP MMC Abort callbacks\r
+ * @retval None\r
+ */\r
+__weak void BSP_MMC_AbortCallback(void)\r
+{\r
+\r
+}\r
+\r
+/**\r
+ * @brief BSP Tx Transfer completed callbacks\r
+ * @retval None\r
+ */\r
+__weak void BSP_MMC_WriteCpltCallback(void)\r
+{\r
+\r
+}\r
+\r
+/**\r
+ * @brief BSP Rx Transfer completed callbacks\r
+ * @retval None\r
+ */\r
+__weak void BSP_MMC_ReadCpltCallback(void)\r
+{\r
+\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_mmc.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the common defines and functions prototypes for\r
+ * the stm32h745i_discovery_mmc.c driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H745I_DISCOVERY_MMC_H\r
+#define STM32H745I_DISCOVERY_MMC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+#include "stm32h745i_discovery.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup STM32H745I_DISCOVERY_MMC\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Types Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SD Card information structure \r
+ */\r
+#define BSP_MMC_CardInfo HAL_MMC_CardInfoTypeDef\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Constants Exported Constants\r
+ * @{\r
+ */ \r
+/** \r
+ * @brief SD status structure definition \r
+ */ \r
+#define MMC_OK ((uint8_t)0x00)\r
+#define MMC_ERROR ((uint8_t)0x01)\r
+#define MMC_ERROR_MMC_NOT_PRESENT ((uint8_t)0x02)\r
+\r
+/** \r
+ * @brief MMC transfer state definition \r
+ */ \r
+#define MMC_TRANSFER_OK ((uint8_t)0x00)\r
+#define MMC_TRANSFER_BUSY ((uint8_t)0x01)\r
+\r
+\r
+#define MMC_PRESENT ((uint8_t)0x01)\r
+#define MMC_NOT_PRESENT ((uint8_t)0x00)\r
+\r
+#define MMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+/** @addtogroup STM32H745I_DISCOVERY_MMC_Exported_Functions\r
+ * @{\r
+ */ \r
+uint8_t BSP_MMC_Init(void);\r
+uint8_t BSP_MMC_DeInit(void);\r
+uint8_t BSP_MMC_ITConfig(void);\r
+\r
+uint8_t BSP_MMC_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);\r
+uint8_t BSP_MMC_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);\r
+uint8_t BSP_MMC_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks);\r
+uint8_t BSP_MMC_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks);\r
+uint8_t BSP_MMC_Erase(uint32_t StartAddr, uint32_t EndAddr);\r
+uint8_t BSP_MMC_GetCardState(void);\r
+void BSP_MMC_GetCardInfo(BSP_MMC_CardInfo *CardInfo);\r
+uint8_t BSP_MMC_IsDetected(void);\r
+void BSP_MMC_IRQHandler(void);\r
+\r
+/* These functions can be modified in case the current settings (e.g. DMA stream)\r
+ need to be changed for specific application needs */\r
+void BSP_MMC_MspInit(MMC_HandleTypeDef *hmmc, void *Params);\r
+void BSP_MMC_MspDeInit(MMC_HandleTypeDef *hmmc, void *Params);\r
+void BSP_MMC_AbortCallback(void);\r
+void BSP_MMC_WriteCpltCallback(void);\r
+void BSP_MMC_ReadCpltCallback(void);\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H745I_DISCOVERY_MMC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_qspi.c\r
+ * @author MCD Application Team\r
+ * @brief This file includes a standard driver for the MT25TL01G QSPI\r
+ * memory mounted on STM32H745I-DISCOVERY board.\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) This driver is used to drive the MT25TL01G QSPI external\r
+ memory mounted on STM32H745I_DISCOVERY board.\r
+\r
+ (#) This driver need a specific component driver (MT25TL01G) to be included with.\r
+\r
+ (#) Initialization steps:\r
+ (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This\r
+ function includes the MSP layer hardware resources initialization and the\r
+ QSPI interface with the external memory.\r
+\r
+ (#) QSPI memory operations\r
+ (++) QSPI memory can be accessed with read/write operations once it is\r
+ initialized.\r
+ Read/write operation can be performed with AHB access using the functions\r
+ BSP_QSPI_Read()/BSP_QSPI_Write().\r
+ (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.\r
+ (see the QSPI memory data sheet)\r
+ (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by\r
+ specifying the block address. You can perform an erase operation of the whole\r
+ chip by calling the function BSP_QSPI_Erase_Chip().\r
+ (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.\r
+ (see the QSPI memory data sheet)\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery_qspi.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_QSPI STM32H745I_DISCOVERY_QSPI\r
+ * @{\r
+ */\r
+\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_QSPI_Private_Variables Private Variables\r
+ * @{\r
+ */\r
+QSPI_HandleTypeDef QSPIHandle;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_QSPI_Private_Functions Private Functions\r
+ * @{\r
+ */\r
+static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);\r
+static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi);\r
+static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);\r
+static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);\r
+static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);\r
+static uint8_t QSPI_EnterQPI(QSPI_HandleTypeDef *hqspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_QSPI_Exported_Functions Exported Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the QSPI interface.\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_Init(void)\r
+{\r
+ QSPIHandle.Instance = QUADSPI;\r
+\r
+ /* Call the DeInit function to reset the driver */\r
+ if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* System level initialization */\r
+ BSP_QSPI_MspInit(&QSPIHandle, NULL);\r
+\r
+ /* QSPI initialization */\r
+ /* ClockPrescaler set to 1, so QSPI clock = 200MHz / (1+3) = 50MHz */\r
+ QSPIHandle.Init.ClockPrescaler = 3;\r
+ QSPIHandle.Init.FifoThreshold = 1;\r
+ QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;\r
+ QSPIHandle.Init.FlashSize = POSITION_VAL(MT25TL01G_FLASH_SIZE) - 1;\r
+ QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE;\r
+ QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;\r
+ QSPIHandle.Init.FlashID = QSPI_FLASH_ID_2;\r
+ QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_ENABLE;\r
+\r
+ if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* QSPI memory reset */\r
+ if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)\r
+ {\r
+ return QSPI_NOT_SUPPORTED;\r
+ }\r
+\r
+ /* Set the QSPI memory in 4-bytes address mode */\r
+ if (QSPI_EnterFourBytesAddress(&QSPIHandle) != QSPI_OK)\r
+ {\r
+ return QSPI_NOT_SUPPORTED;\r
+ }\r
+\r
+ /* Configuration of the dummy cycles on QSPI memory side */\r
+ if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)\r
+ {\r
+ return QSPI_NOT_SUPPORTED;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the QSPI interface.\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_DeInit(void)\r
+{\r
+ QSPIHandle.Instance = QUADSPI;\r
+\r
+ /* Call the DeInit function to reset the driver */\r
+ if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* System level De-initialization */\r
+ BSP_QSPI_MspDeInit(&QSPIHandle, NULL);\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reads an amount of data from the QSPI memory.\r
+ * @param pData: Pointer to data to be read\r
+ * @param ReadAddr: Read start address\r
+ * @param Size: Size of data to read\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+\r
+ /* Initialize the read command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = QUAD_INOUT_FAST_READ_DTR_CMD; /* DTR QUAD INPUT/OUTPUT FAST READ and 4-BYTE DTR FAST READ commands */\r
+ s_command.AddressMode = QSPI_ADDRESS_4_LINES;\r
+ s_command.AddressSize = QSPI_ADDRESS_32_BITS;\r
+ s_command.Address = ReadAddr;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_4_LINES;\r
+ s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;\r
+ s_command.NbData = Size;\r
+ s_command.DdrMode = QSPI_DDR_MODE_ENABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_HALF_CLK_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Configure the command */\r
+ if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Reception of the data */\r
+ if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief Writes an amount of data to the QSPI memory.\r
+ * @param pData: Pointer to data to be written\r
+ * @param WriteAddr: Write start address\r
+ * @param Size: Size of data to write\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+ uint32_t end_addr, current_size, current_addr;\r
+\r
+ /* Calculation of the size between the write address and the end of the page */\r
+ current_size = MT25TL01G_PAGE_SIZE - (WriteAddr % MT25TL01G_PAGE_SIZE);\r
+\r
+ /* Check if the size of the data is less than the remaining place in the page */\r
+ if (current_size > Size)\r
+ {\r
+ current_size = Size;\r
+ }\r
+\r
+ /* Initialize the address variables */\r
+ current_addr = WriteAddr;\r
+ end_addr = WriteAddr + Size;\r
+\r
+ /* Initialize the program command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_4_LINES;\r
+ s_command.AddressSize = QSPI_ADDRESS_32_BITS;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_4_LINES;\r
+ s_command.DummyCycles = 0;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Perform the write page by page */\r
+ do\r
+ {\r
+ s_command.Address = current_addr;\r
+ s_command.NbData = current_size;\r
+\r
+ /* Enable write operations */\r
+ if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Configure the command */\r
+ if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Transmission of the data */\r
+ if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Configure automatic polling mode to wait for end of program */\r
+ if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Update the address and size variables for next page programming */\r
+ current_addr += current_size;\r
+ pData += current_size;\r
+ current_size = ((current_addr + MT25TL01G_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MT25TL01G_PAGE_SIZE;\r
+ } while (current_addr < end_addr);\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief Erases the specified block of the QSPI memory.\r
+ * @param BlockAddress: Block address to erase\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+\r
+ /* Initialize the erase command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = SUBSECTOR_ERASE_4_BYTE_ADDR_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_4_LINES;\r
+ s_command.AddressSize = QSPI_ADDRESS_32_BITS;\r
+ s_command.Address = BlockAddress;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_NONE;\r
+ s_command.DummyCycles = 0;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Enable write operations */\r
+ if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Send the command */\r
+ if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Configure automatic polling mode to wait for end of erase */\r
+ if (QSPI_AutoPollingMemReady(&QSPIHandle, MT25TL01G_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief Erases the entire QSPI memory.\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_Erase_Chip(void)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+\r
+ /* Initialize the erase command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = DIE_ERASE_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_NONE;\r
+ s_command.DummyCycles = 0;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Enable write operations */\r
+ if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Send the command */\r
+ if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Configure automatic polling mode to wait for end of erase */\r
+ if (QSPI_AutoPollingMemReady(&QSPIHandle, MT25TL01G_DIE_ERASE_MAX_TIME) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reads current status of the QSPI memory.\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_GetStatus(void)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+ uint16_t reg;\r
+\r
+ /* Initialize the read flag status register command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = READ_FLAG_STATUS_REG_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_4_LINES;\r
+ s_command.DummyCycles = 0;\r
+ s_command.NbData = 1;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Configure the command */\r
+ if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Reception of the data */\r
+ if (HAL_QSPI_Receive(&QSPIHandle, (uint8_t*)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Check the value of the register */\r
+ if ((reg & (MT25TL01G_FSR_PRERR | MT25TL01G_FSR_PGERR | MT25TL01G_FSR_ERERR)) != 0)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+ else if ((reg & (MT25TL01G_FSR_PGSUS | MT25TL01G_FSR_ERSUS)) != 0)\r
+ {\r
+ return QSPI_SUSPENDED;\r
+ }\r
+ else if ((reg & MT25TL01G_FSR_READY) != 0)\r
+ {\r
+ return QSPI_OK;\r
+ }\r
+ else\r
+ {\r
+ return QSPI_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the configuration of the QSPI memory.\r
+ * @param pInfo: pointer on the configuration structure\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)\r
+{\r
+ /* Configure the structure with the memory configuration */\r
+ pInfo->FlashSize = MT25TL01G_FLASH_SIZE;\r
+ pInfo->EraseSectorSize = (2 * MT25TL01G_SUBSECTOR_SIZE);\r
+ pInfo->ProgPageSize = MT25TL01G_PAGE_SIZE;\r
+ pInfo->EraseSectorsNumber = (MT25TL01G_FLASH_SIZE/pInfo->EraseSectorSize);\r
+ pInfo->ProgPagesNumber = (MT25TL01G_FLASH_SIZE/pInfo->ProgPageSize);\r
+ \r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the QSPI in memory-mapped mode\r
+ * @retval QSPI memory status\r
+ */\r
+uint8_t BSP_QSPI_EnableMemoryMappedMode(void)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+ QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;\r
+\r
+ /* Configure the command for the read instruction */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = QUAD_INOUT_FAST_READ_DTR_CMD; /* DTR QUAD INPUT/OUTPUT FAST READ and 4-BYTE DTR FAST READ commands */\r
+ s_command.AddressMode = QSPI_ADDRESS_4_LINES;\r
+ s_command.AddressSize = QSPI_ADDRESS_32_BITS;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_4_LINES;\r
+ s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;\r
+ \r
+ s_command.DdrMode = QSPI_DDR_MODE_ENABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_HALF_CLK_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Configure the memory mapped mode */\r
+ s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;\r
+ s_mem_mapped_cfg.TimeOutPeriod = 0;\r
+\r
+ if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief QSPI MSP Initialization\r
+ * This function configures the hardware resources used in this example:\r
+ * - Peripheral's clock enable\r
+ * - Peripheral's GPIO Configuration\r
+ * - NVIC configuration for QSPI interrupt\r
+ * @retval None\r
+ */\r
+__weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ /*##-1- Enable peripherals and GPIO Clocks #################################*/\r
+ /* Enable the QuadSPI memory interface clock */\r
+ QSPI_CLK_ENABLE();\r
+ /* Reset the QuadSPI memory interface */\r
+ QSPI_FORCE_RESET();\r
+ QSPI_RELEASE_RESET();\r
+ /* Enable GPIO clocks */\r
+ QSPI_CLK_GPIO_CLK_ENABLE();\r
+ QSPI_BK1_CS_GPIO_CLK_ENABLE();\r
+ QSPI_BK1_D0_GPIO_CLK_ENABLE();\r
+ QSPI_BK1_D1_GPIO_CLK_ENABLE();\r
+ QSPI_BK1_D2_GPIO_CLK_ENABLE();\r
+ QSPI_BK1_D3_GPIO_CLK_ENABLE();\r
+\r
+ QSPI_BK2_CS_GPIO_CLK_ENABLE();\r
+ QSPI_BK2_D0_GPIO_CLK_ENABLE();\r
+ QSPI_BK2_D1_GPIO_CLK_ENABLE();\r
+ QSPI_BK2_D2_GPIO_CLK_ENABLE();\r
+ QSPI_BK2_D3_GPIO_CLK_ENABLE();\r
+\r
+ /*##-2- Configure peripheral GPIO ##########################################*/\r
+ /* QSPI CLK GPIO pin configuration */\r
+ gpio_init_structure.Pin = QSPI_CLK_PIN;\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;\r
+ HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* QSPI CS GPIO pin configuration */\r
+ gpio_init_structure.Pin = QSPI_BK1_CS_PIN;\r
+ gpio_init_structure.Pull = GPIO_PULLUP;\r
+ gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;\r
+ HAL_GPIO_Init(QSPI_BK1_CS_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* QSPI D0 GPIO pin configuration */\r
+ gpio_init_structure.Pin = QSPI_BK1_D0_PIN;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;\r
+ HAL_GPIO_Init(QSPI_BK1_D0_GPIO_PORT, &gpio_init_structure);\r
+\r
+ gpio_init_structure.Pin = QSPI_BK2_D0_PIN;\r
+ gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;\r
+ HAL_GPIO_Init(QSPI_BK2_D0_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* QSPI D1 GPIO pin configuration */\r
+ gpio_init_structure.Pin = QSPI_BK1_D1_PIN;\r
+ gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;\r
+ HAL_GPIO_Init(QSPI_BK1_D1_GPIO_PORT, &gpio_init_structure);\r
+\r
+ gpio_init_structure.Pin = QSPI_BK2_D1_PIN;\r
+ gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;\r
+ HAL_GPIO_Init(QSPI_BK2_D1_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* QSPI D2 GPIO pin configuration */\r
+ gpio_init_structure.Pin = QSPI_BK1_D2_PIN;\r
+ gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;\r
+ HAL_GPIO_Init(QSPI_BK1_D2_GPIO_PORT, &gpio_init_structure);\r
+\r
+ gpio_init_structure.Pin = QSPI_BK2_D2_PIN;\r
+ HAL_GPIO_Init(QSPI_BK2_D2_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* QSPI D3 GPIO pin configuration */\r
+ gpio_init_structure.Pin = QSPI_BK1_D3_PIN;\r
+ HAL_GPIO_Init(QSPI_BK1_D3_GPIO_PORT, &gpio_init_structure);\r
+\r
+ gpio_init_structure.Pin = QSPI_BK2_D3_PIN;\r
+ HAL_GPIO_Init(QSPI_BK2_D3_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /*##-3- Configure the NVIC for QSPI #########################################*/\r
+ /* NVIC configuration for QSPI interrupt */\r
+ HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);\r
+ HAL_NVIC_EnableIRQ(QUADSPI_IRQn);\r
+\r
+}\r
+\r
+/**\r
+ * @brief QSPI MSP De-Initialization\r
+ * This function frees the hardware resources used in this example:\r
+ * - Disable the Peripheral's clock\r
+ * - Revert GPIO and NVIC configuration to their default state\r
+ * @retval None\r
+ */\r
+__weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)\r
+{\r
+ /*##-1- Disable the NVIC for QSPI ###########################################*/\r
+ HAL_NVIC_DisableIRQ(QUADSPI_IRQn);\r
+\r
+ /*##-2- Disable peripherals and GPIO Clocks ################################*/\r
+ /* De-Configure QSPI pins */\r
+ HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK1_CS_GPIO_PORT, QSPI_BK1_CS_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK1_D0_GPIO_PORT, QSPI_BK1_D0_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK1_D1_GPIO_PORT, QSPI_BK1_D1_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK1_D2_GPIO_PORT, QSPI_BK1_D2_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK1_D3_GPIO_PORT, QSPI_BK1_D3_PIN);\r
+\r
+ HAL_GPIO_DeInit(QSPI_BK2_CS_GPIO_PORT, QSPI_BK2_CS_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK2_D0_GPIO_PORT, QSPI_BK2_D0_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK2_D1_GPIO_PORT, QSPI_BK2_D1_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK2_D2_GPIO_PORT, QSPI_BK2_D2_PIN);\r
+ HAL_GPIO_DeInit(QSPI_BK2_D3_GPIO_PORT, QSPI_BK2_D3_PIN);\r
+\r
+ /*##-3- Reset peripherals ##################################################*/\r
+ /* Reset the QuadSPI memory interface */\r
+ QSPI_FORCE_RESET();\r
+ QSPI_RELEASE_RESET();\r
+\r
+ /* Disable the QuadSPI memory interface clock */\r
+ QSPI_CLK_DISABLE();\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_QSPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function reset the QSPI memory.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+\r
+ /* Initialize the reset enable command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;\r
+ s_command.Instruction = RESET_ENABLE_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_NONE;\r
+ s_command.DummyCycles = 0;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Send the command */\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Send the reset memory command */\r
+ s_command.Instruction = RESET_MEMORY_CMD;\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+ \r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = RESET_ENABLE_CMD;\r
+ /* Send the command */\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Send the reset memory command */\r
+ s_command.Instruction = RESET_MEMORY_CMD;\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+ \r
+ /* Enter QSPI memory in QPI mode */\r
+ if(QSPI_EnterQPI(&QSPIHandle) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+ \r
+ /* Configure automatic polling mode to wait the memory is ready */\r
+ if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function set the QSPI memory in 4-byte address mode\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+\r
+ /* Initialize the command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = ENTER_4_BYTE_ADDR_MODE_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_NONE;\r
+ s_command.DummyCycles = 0;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Enable write operations */\r
+ if (QSPI_WriteEnable(hqspi) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Send the command */\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Configure automatic polling mode to wait the memory is ready */\r
+ if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function configure the dummy cycles on memory side.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+ uint16_t reg = 0;\r
+\r
+ /* Initialize the read volatile configuration register command */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = READ_VOL_CFG_REG_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_4_LINES;\r
+ s_command.DummyCycles = 0;\r
+ s_command.NbData = 2;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ /* Configure the command */\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Reception of the data */\r
+ if (HAL_QSPI_Receive(hqspi, (uint8_t *)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Enable write operations */\r
+ if (QSPI_WriteEnable(hqspi) != QSPI_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Update volatile configuration register (with new dummy cycles) */\r
+ s_command.Instruction = WRITE_VOL_CFG_REG_CMD;\r
+ MODIFY_REG(reg, 0xF0F0, ((MT25TL01G_DUMMY_CYCLES_READ_QUAD << 4) |\r
+ (MT25TL01G_DUMMY_CYCLES_READ_QUAD << 12)));\r
+\r
+ /* Configure the write volatile configuration register command */\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Transmission of the data */\r
+ if (HAL_QSPI_Transmit(hqspi, (uint8_t *)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function send a Write Enable and wait it is effective.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+ QSPI_AutoPollingTypeDef s_config;\r
+\r
+ /* Enable write operations */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = WRITE_ENABLE_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_NONE;\r
+ s_command.DummyCycles = 0;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ /* Configure automatic polling mode to wait for write enabling */\r
+ s_config.Match = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);\r
+ s_config.Mask = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);\r
+ s_config.MatchMode = QSPI_MATCH_MODE_AND;\r
+ s_config.StatusBytesSize = 2;\r
+ s_config.Interval = 0x10;\r
+ s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;\r
+\r
+ s_command.Instruction = READ_STATUS_REG_CMD;\r
+ s_command.DataMode = QSPI_DATA_4_LINES;\r
+\r
+ if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function read the SR of the memory and wait the EOP.\r
+ * @param hqspi QSPI handle\r
+ * @param Timeout Autopolling timeout\r
+ * @retval None\r
+ */\r
+static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+ QSPI_AutoPollingTypeDef s_config;\r
+\r
+ /* Configure automatic polling mode to wait for memory ready */\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;\r
+ s_command.Instruction = READ_STATUS_REG_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_4_LINES;\r
+ s_command.DummyCycles = 2;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ s_config.Match = 0;\r
+ s_config.MatchMode = QSPI_MATCH_MODE_AND;\r
+ s_config.Interval = 0x10;\r
+ s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;\r
+ s_config.Mask = MT25TL01G_SR_WIP | (MT25TL01G_SR_WIP <<8);\r
+ s_config.StatusBytesSize = 2;\r
+\r
+ if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+\r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function enter the QPSI memory in QPI mode\r
+ * @param hqspi QSPI handle \r
+ * @retval QSPI status\r
+ */\r
+static uint8_t QSPI_EnterQPI(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ QSPI_CommandTypeDef s_command;\r
+\r
+ s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;\r
+ s_command.Instruction = ENTER_QUAD_CMD;\r
+ s_command.AddressMode = QSPI_ADDRESS_NONE;\r
+ s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;\r
+ s_command.DataMode = QSPI_DATA_NONE;\r
+ s_command.DummyCycles = 0;\r
+ s_command.DdrMode = QSPI_DDR_MODE_DISABLE;\r
+ s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;\r
+ s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;\r
+\r
+ if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)\r
+ {\r
+ return QSPI_ERROR;\r
+ }\r
+ \r
+ return QSPI_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_qspi.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the common defines and functions prototypes for\r
+ * the stm32H745i_discovery_qspi.c driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H745I_DISCOVERY_QSPI_H\r
+#define __STM32H745I_DISCOVERY_QSPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+#include "../Components/mt25tl01g/mt25tl01g.h"\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_QSPI\r
+ * @{\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup STM32H745I_DISCOVERY_QSPI_Exported_Constants Exported Constants\r
+ * @{\r
+ */\r
+\r
+/* QSPI Error codes */\r
+#define QSPI_OK ((uint8_t)0x00)\r
+#define QSPI_ERROR ((uint8_t)0x01)\r
+#define QSPI_BUSY ((uint8_t)0x02)\r
+#define QSPI_NOT_SUPPORTED ((uint8_t)0x04)\r
+#define QSPI_SUSPENDED ((uint8_t)0x08)\r
+\r
+\r
+/* Definition for QSPI clock resources */\r
+#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()\r
+#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()\r
+#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()\r
+#define QSPI_BK1_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()\r
+#define QSPI_BK1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()\r
+#define QSPI_BK1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()\r
+#define QSPI_BK1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()\r
+#define QSPI_BK1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()\r
+#define QSPI_BK2_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()\r
+#define QSPI_BK2_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()\r
+#define QSPI_BK2_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()\r
+#define QSPI_BK2_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()\r
+#define QSPI_BK2_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()\r
+\r
+\r
+#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()\r
+#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()\r
+\r
+/* Definition for QSPI Pins */\r
+#define QSPI_CLK_PIN GPIO_PIN_10\r
+#define QSPI_CLK_GPIO_PORT GPIOF\r
+/* Bank 1 */\r
+#define QSPI_BK1_CS_PIN GPIO_PIN_6\r
+#define QSPI_BK1_CS_GPIO_PORT GPIOG\r
+#define QSPI_BK1_D0_PIN GPIO_PIN_11\r
+#define QSPI_BK1_D0_GPIO_PORT GPIOD\r
+#define QSPI_BK1_D1_PIN GPIO_PIN_9\r
+#define QSPI_BK1_D1_GPIO_PORT GPIOF\r
+#define QSPI_BK1_D2_PIN GPIO_PIN_7\r
+#define QSPI_BK1_D2_GPIO_PORT GPIOF\r
+#define QSPI_BK1_D3_PIN GPIO_PIN_6\r
+#define QSPI_BK1_D3_GPIO_PORT GPIOF\r
+\r
+/* Bank 2 */\r
+#define QSPI_BK2_CS_PIN GPIO_PIN_6\r
+#define QSPI_BK2_CS_GPIO_PORT GPIOG\r
+#define QSPI_BK2_D0_PIN GPIO_PIN_2\r
+#define QSPI_BK2_D0_GPIO_PORT GPIOH\r
+#define QSPI_BK2_D1_PIN GPIO_PIN_3\r
+#define QSPI_BK2_D1_GPIO_PORT GPIOH\r
+#define QSPI_BK2_D2_PIN GPIO_PIN_9\r
+#define QSPI_BK2_D2_GPIO_PORT GPIOG\r
+#define QSPI_BK2_D3_PIN GPIO_PIN_14\r
+#define QSPI_BK2_D3_GPIO_PORT GPIOG\r
+\r
+\r
+/* MT25TL01G Micron memory */\r
+/* Size of the flash */\r
+#define QSPI_FLASH_SIZE 26 /* Address bus width to access whole memory space */\r
+#define QSPI_PAGE_SIZE 256\r
+\r
+/* QSPI Base Address */\r
+#define QSPI_BASE_ADDRESS 0x90000000\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup STM32H745I_DISCOVERY_QSPI_Exported_Types Exported Types\r
+ * @{\r
+ */\r
+/* QSPI Info */\r
+typedef struct {\r
+ uint32_t FlashSize; /*!< Size of the flash */\r
+ uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */\r
+ uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */\r
+ uint32_t ProgPageSize; /*!< Size of pages for the program operation */\r
+ uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */\r
+} QSPI_Info;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup STM32H745I_DISCOVERY_QSPI_Exported_Functions\r
+ * @{\r
+ */\r
+uint8_t BSP_QSPI_Init (void);\r
+uint8_t BSP_QSPI_DeInit (void);\r
+uint8_t BSP_QSPI_Read (uint8_t* pData, uint32_t ReadAddr, uint32_t Size);\r
+uint8_t BSP_QSPI_Write (uint8_t* pData, uint32_t WriteAddr, uint32_t Size);\r
+uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress);\r
+uint8_t BSP_QSPI_Erase_Chip (void);\r
+uint8_t BSP_QSPI_GetStatus (void);\r
+uint8_t BSP_QSPI_GetInfo (QSPI_Info* pInfo);\r
+uint8_t BSP_QSPI_EnableMemoryMappedMode(void);\r
+\r
+/* These functions can be modified in case the current settings\r
+ need to be changed for specific application needs */\r
+void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params);\r
+void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H745I_DISCOVERY_QSPI_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_sdram.c\r
+ * @author MCD Application Team\r
+ * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-6A memory \r
+ * device mounted on STM32H745I_DISCOVERY boards.\r
+ ******************************************************************************\r
+ @verbatim\r
+ How To use this driver:\r
+ -----------------------\r
+ - This driver is used to drive the MT48LC4M32B2B5-6A SDRAM external memory mounted\r
+ on STM32H745I_DISCOVERY board.\r
+ - This driver does not need a specific component driver for the SDRAM device\r
+ to be included with.\r
+\r
+ Driver description:\r
+ ------------------\r
+ + Initialization steps:\r
+ o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This \r
+ function includes the MSP layer hardware resources initialization and the\r
+ FMC controller configuration to interface with the external SDRAM memory.\r
+ o It contains the SDRAM initialization sequence to program the SDRAM external \r
+ device using the function BSP_SDRAM_Initialization_sequence(). Note that this \r
+ sequence is standard for all SDRAM devices, but can include some differences\r
+ from a device to another. If it is the case, the right sequence should be \r
+ implemented separately.\r
+ \r
+ + SDRAM read/write operations\r
+ o SDRAM external memory can be accessed with read/write operations once it is\r
+ initialized.\r
+ Read/write operation can be performed with AHB access using the functions\r
+ BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by MDMA transfer using the functions\r
+ BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().\r
+ o The AHB access is performed with 32-bit width transaction, the MDMA transfer\r
+ configuration is fixed at single (no burst) word transfer (see the \r
+ SDRAM_MspInit() static function).\r
+ o User can implement his own functions for read/write access with his desired \r
+ configurations.\r
+ o If interrupt mode is used for MDMA transfer, the function BSP_SDRAM_MDMA_IRQHandler()\r
+ is called in IRQ handler file, to serve the generated interrupt once the MDMA \r
+ transfer is complete.\r
+ o You can send a command to the SDRAM device in runtime using the function \r
+ BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between \r
+ the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery_sdram.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup STM32H745I_DISCOVERY_SDRAM STM32H745I_DISCOVERY_SDRAM\r
+ * @{\r
+ */ \r
+\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_SDRAM_Private_Variables Private Variables\r
+ * @{\r
+ */ \r
+SDRAM_HandleTypeDef sdramHandle;\r
+static FMC_SDRAM_TimingTypeDef Timing;\r
+static FMC_SDRAM_CommandTypeDef Command;\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ \r
+/** @defgroup STM32H745I_DISCOVERY_SDRAM_Exported_Functions Exported Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Initializes the SDRAM device.\r
+ * @retval SDRAM status\r
+ */\r
+uint8_t BSP_SDRAM_Init(void)\r
+{ \r
+ static uint8_t sdramstatus = SDRAM_OK;\r
+ /* SDRAM device configuration */\r
+ sdramHandle.Instance = FMC_SDRAM_DEVICE;\r
+ \r
+ /* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is up to 200Mhz) */\r
+ Timing.LoadToActiveDelay = 2;\r
+ Timing.ExitSelfRefreshDelay = 7;\r
+ Timing.SelfRefreshTime = 4;\r
+ Timing.RowCycleDelay = 7;\r
+ Timing.WriteRecoveryTime = 2;\r
+ Timing.RPDelay = 2;\r
+ Timing.RCDDelay = 2;\r
+ \r
+ sdramHandle.Init.SDBank = FMC_SDRAM_BANK2;\r
+ sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;\r
+ sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;\r
+ sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;\r
+ sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;\r
+ sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;\r
+ sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;\r
+ sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;\r
+ sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;\r
+ sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;\r
+ \r
+ /* SDRAM controller initialization */\r
+\r
+ BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */\r
+\r
+ if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)\r
+ {\r
+ sdramstatus = SDRAM_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* SDRAM initialization sequence */\r
+ BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);\r
+ }\r
+\r
+ return sdramstatus;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SDRAM device.\r
+ * @retval SDRAM status\r
+ */\r
+uint8_t BSP_SDRAM_DeInit(void)\r
+{ \r
+ static uint8_t sdramstatus = SDRAM_OK;\r
+ /* SDRAM device de-initialization */\r
+ sdramHandle.Instance = FMC_SDRAM_DEVICE;\r
+\r
+ if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)\r
+ {\r
+ sdramstatus = SDRAM_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* SDRAM controller de-initialization */\r
+ BSP_SDRAM_MspDeInit(&sdramHandle, NULL);\r
+ }\r
+ \r
+ return sdramstatus;\r
+}\r
+\r
+/**\r
+ * @brief Programs the SDRAM device.\r
+ * @param RefreshCount: SDRAM refresh counter value \r
+ * @retval None\r
+ */\r
+void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)\r
+{\r
+ __IO uint32_t tmpmrd = 0;\r
+ \r
+ /* Step 1: Configure a clock configuration enable command */\r
+ Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;\r
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;\r
+ Command.AutoRefreshNumber = 1;\r
+ Command.ModeRegisterDefinition = 0;\r
+\r
+ /* Send the command */\r
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);\r
+\r
+ /* Step 2: Insert 100 us minimum delay */ \r
+ /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */\r
+ HAL_Delay(1);\r
+ \r
+ /* Step 3: Configure a PALL (precharge all) command */ \r
+ Command.CommandMode = FMC_SDRAM_CMD_PALL;\r
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;\r
+ Command.AutoRefreshNumber = 1;\r
+ Command.ModeRegisterDefinition = 0;\r
+\r
+ /* Send the command */\r
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); \r
+ \r
+ /* Step 4: Configure an Auto Refresh command */ \r
+ Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;\r
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;\r
+ Command.AutoRefreshNumber = 8;\r
+ Command.ModeRegisterDefinition = 0;\r
+\r
+ /* Send the command */\r
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);\r
+ \r
+ /* Step 5: Program the external memory mode register */\r
+ tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\\r
+ SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\\r
+ SDRAM_MODEREG_CAS_LATENCY_3 |\\r
+ SDRAM_MODEREG_OPERATING_MODE_STANDARD |\\r
+ SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;\r
+ \r
+ Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;\r
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;\r
+ Command.AutoRefreshNumber = 1;\r
+ Command.ModeRegisterDefinition = tmpmrd;\r
+\r
+ /* Send the command */\r
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);\r
+ \r
+ /* Step 6: Set the refresh rate counter */\r
+ /* Set the device refresh rate */\r
+ HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); \r
+}\r
+\r
+/**\r
+ * @brief Reads an amount of data from the SDRAM memory in polling mode.\r
+ * @param uwStartAddress: Read start address\r
+ * @param pData: Pointer to data to be read \r
+ * @param uwDataSize: Size of read data from the memory\r
+ * @retval SDRAM status\r
+ */\r
+uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)\r
+{\r
+ if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)\r
+ {\r
+ return SDRAM_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return SDRAM_OK;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Reads an amount of data from the SDRAM memory in DMA mode.\r
+ * @param uwStartAddress: Read start address\r
+ * @param pData: Pointer to data to be read \r
+ * @param uwDataSize: Size of read data from the memory\r
+ * @retval SDRAM status\r
+ */\r
+uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)\r
+{\r
+ if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)\r
+ {\r
+ return SDRAM_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return SDRAM_OK;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Writes an amount of data to the SDRAM memory in polling mode.\r
+ * @param uwStartAddress: Write start address\r
+ * @param pData: Pointer to data to be written \r
+ * @param uwDataSize: Size of written data from the memory\r
+ * @retval SDRAM status\r
+ */\r
+uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) \r
+{\r
+ if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)\r
+ {\r
+ return SDRAM_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return SDRAM_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes an amount of data to the SDRAM memory in DMA mode.\r
+ * @param uwStartAddress: Write start address\r
+ * @param pData: Pointer to data to be written \r
+ * @param uwDataSize: Size of written data from the memory\r
+ * @retval SDRAM status\r
+ */\r
+uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) \r
+{\r
+ if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)\r
+ {\r
+ return SDRAM_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return SDRAM_OK;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Sends command to the SDRAM bank.\r
+ * @param SdramCmd: Pointer to SDRAM command structure \r
+ * @retval SDRAM status\r
+ */ \r
+uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)\r
+{\r
+ if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)\r
+ {\r
+ return SDRAM_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return SDRAM_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes SDRAM MSP.\r
+ * @param hsdram SDRAM handle\r
+ * @param Params User parameters\r
+ * @retval None\r
+ */\r
+__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)\r
+{ \r
+ static MDMA_HandleTypeDef mdma_handle;\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+ \r
+ /* Enable FMC clock */\r
+ __HAL_RCC_FMC_CLK_ENABLE();\r
+ \r
+ /* Enable chosen MDMAx clock */\r
+ __MDMAx_CLK_ENABLE();\r
+\r
+ /* Enable GPIOs clock */\r
+ __HAL_RCC_GPIOD_CLK_ENABLE();\r
+ __HAL_RCC_GPIOE_CLK_ENABLE();\r
+ __HAL_RCC_GPIOF_CLK_ENABLE();\r
+ __HAL_RCC_GPIOG_CLK_ENABLE();\r
+ __HAL_RCC_GPIOH_CLK_ENABLE();\r
+ \r
+ /* Common GPIO configuration */\r
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;\r
+ gpio_init_structure.Pull = GPIO_PULLUP;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ gpio_init_structure.Alternate = GPIO_AF12_FMC;\r
+ \r
+ /* GPIOD configuration */\r
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\\r
+ GPIO_PIN_14 | GPIO_PIN_15;\r
+ \r
+ \r
+ HAL_GPIO_Init(GPIOD, &gpio_init_structure);\r
+\r
+ /* GPIOE configuration */ \r
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\\r
+ GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\\r
+ GPIO_PIN_15;\r
+ \r
+ HAL_GPIO_Init(GPIOE, &gpio_init_structure);\r
+ \r
+ /* GPIOF configuration */ \r
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\\r
+ GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\\r
+ GPIO_PIN_15;\r
+ \r
+ HAL_GPIO_Init(GPIOF, &gpio_init_structure);\r
+ \r
+ /* GPIOG configuration */ \r
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;\r
+ HAL_GPIO_Init(GPIOG, &gpio_init_structure);\r
+\r
+ /* GPIOH configuration */ \r
+ gpio_init_structure.Pin = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 ;\r
+ HAL_GPIO_Init(GPIOH, &gpio_init_structure); \r
+ \r
+\r
+ \r
+ /* Configure common MDMA parameters */\r
+ mdma_handle.Init.Request = MDMA_REQUEST_SW;\r
+ mdma_handle.Init.TransferTriggerMode = MDMA_BLOCK_TRANSFER;\r
+ mdma_handle.Init.Priority = MDMA_PRIORITY_HIGH;\r
+ mdma_handle.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;\r
+ mdma_handle.Init.SourceInc = MDMA_SRC_INC_WORD;\r
+ mdma_handle.Init.DestinationInc = MDMA_DEST_INC_WORD;\r
+ mdma_handle.Init.SourceDataSize = MDMA_SRC_DATASIZE_WORD;\r
+ mdma_handle.Init.DestDataSize = MDMA_DEST_DATASIZE_WORD;\r
+ mdma_handle.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE; \r
+ mdma_handle.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;\r
+ mdma_handle.Init.DestBurst = MDMA_DEST_BURST_SINGLE;\r
+ mdma_handle.Init.BufferTransferLength = 128;\r
+ mdma_handle.Init.SourceBlockAddressOffset = 0;\r
+ mdma_handle.Init.DestBlockAddressOffset = 0; \r
+ \r
+ \r
+ mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;\r
+ \r
+ /* Associate the DMA handle */\r
+ __HAL_LINKDMA(hsdram, hmdma, mdma_handle);\r
+ \r
+ /* Deinitialize the stream for new transfer */\r
+ HAL_MDMA_DeInit(&mdma_handle);\r
+ \r
+ /* Configure the DMA stream */\r
+ HAL_MDMA_Init(&mdma_handle); \r
+ \r
+ /* NVIC configuration for DMA transfer complete interrupt */\r
+ HAL_NVIC_SetPriority(SDRAM_MDMAx_IRQn, 0x0F, 0);\r
+ HAL_NVIC_EnableIRQ(SDRAM_MDMAx_IRQn);\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes SDRAM MSP.\r
+ * @param hsdram SDRAM handle\r
+ * @param Params User parameters\r
+ * @retval None\r
+ */\r
+__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)\r
+{ \r
+ static MDMA_HandleTypeDef mdma_handle;\r
+ \r
+ /* Disable NVIC configuration for DMA interrupt */\r
+ HAL_NVIC_DisableIRQ(SDRAM_MDMAx_IRQn);\r
+\r
+ /* Deinitialize the stream for new transfer */\r
+ mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;\r
+ HAL_MDMA_DeInit(&mdma_handle);\r
+\r
+ /* GPIO pins clock, FMC clock and MDMA clock can be shut down in the applications\r
+ by surcharging this __weak function */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_sdram.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the common defines and functions prototypes for\r
+ * the stm32h745i_discovery_sdram.c driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H745I_DISCOVERY_SDRAM_H\r
+#define __STM32H745I_DISCOVERY_SDRAM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup STM32H745I_DISCOVERY_SDRAM\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup STM32H745I_DISCOVERY_SDRAM_Exported_Constants Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief SDRAM status structure definition \r
+ */ \r
+#define SDRAM_OK ((uint8_t)0x00)\r
+#define SDRAM_ERROR ((uint8_t)0x01)\r
+\r
+#define SDRAM_DEVICE_ADDR ((uint32_t)0xD0000000)\r
+#define SDRAM_DEVICE_SIZE ((uint32_t)0x2000000) /* SDRAM device size in MBytes */\r
+\r
+/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */\r
+#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 \r
+/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32 */\r
+\r
+#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2\r
+/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ \r
+\r
+#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */\r
+ \r
+#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)\r
+\r
+/* DMA definitions for SDRAM DMA transfer */\r
+#define __MDMAx_CLK_ENABLE __HAL_RCC_MDMA_CLK_ENABLE\r
+#define __MDMAx_CLK_DISABLE __HAL_RCC_MDMA_CLK_DISABLE\r
+#define SDRAM_MDMAx_CHANNEL MDMA_Channel0 \r
+#define SDRAM_MDMAx_IRQn MDMA_IRQn\r
+ \r
+/**\r
+ * @brief FMC SDRAM Mode definition register defines\r
+ */\r
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)\r
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)\r
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)\r
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)\r
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)\r
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)\r
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)\r
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)\r
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)\r
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) \r
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ \r
+/** @defgroup STM32H745I_DISCOVERY_SDRAM_Exported_Functions Exported Functions\r
+ * @{\r
+ */ \r
+uint8_t BSP_SDRAM_Init(void);\r
+uint8_t BSP_SDRAM_DeInit(void);\r
+void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);\r
+uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);\r
+uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);\r
+uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);\r
+uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);\r
+uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);\r
+ \r
+/* These functions can be modified in case the current settings (e.g. DMA stream)\r
+ need to be changed for specific application needs */\r
+void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);\r
+void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H745I_DISCOVERY_SDRAM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_ts.c\r
+ * @author MCD Application Team\r
+ * @brief This file provides a set of functions needed to manage the Touch\r
+ * Screen on STM32H745I_DISCOVERY discovery board.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+ /*\r
+ @verbatim\r
+ 1. How To use this driver:\r
+ --------------------------\r
+ - This driver is used to drive the touch screen module of the STM32H745I_Discovery\r
+ board on the RK043FN48H-CT672B 480x272 LCD screen with capacitive touch screen.\r
+ - The FT5336 component driver must be included in project files according to\r
+ the touch screen driver present on this board.\r
+ \r
+ 2. Driver description:\r
+ ---------------------\r
+ + Initialization steps:\r
+ o Initialize the TS module using the BSP_TS_Init() function. This \r
+ function includes the MSP layer hardware resources initialization and the\r
+ communication layer configuration to start the TS use. The LCD size properties\r
+ (x and y) are passed as parameters.\r
+ o If TS interrupt mode is desired, you must configure the TS interrupt mode\r
+ by calling the function BSP_TS_ITConfig(). The TS interrupt mode is generated\r
+ as an external interrupt whenever a touch is detected. \r
+ The interrupt mode internally uses the IO functionalities driver driven by\r
+ the IO expander, to configure the IT line.\r
+ \r
+ + Touch screen use\r
+ o The touch screen state is captured whenever the function BSP_TS_GetState() is \r
+ used. This function returns information about the last LCD touch occurred\r
+ in the TS_StateTypeDef structure.\r
+ o If TS interrupt mode is used, the function BSP_TS_ITGetStatus() is needed to get\r
+ the interrupt status. To clear the IT pending bits, you should call the \r
+ function BSP_TS_ITClear().\r
+ o The IT is handled using the corresponding external interrupt IRQ handler,\r
+ the user IT callback treatment is implemented on the same external interrupt\r
+ callback.\r
+*/\r
+\r
+/* Dependencies\r
+- stm32h745_discovery_lcd.c\r
+- ft5336.c\r
+EndDependencies */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery.h"\r
+#include "stm32h745i_discovery_ts.h"\r
+\r
+/** @addtogroup BSP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup STM32H745I_DISCOVERY_TS STM32H745I_DISCOVERY_TS\r
+ * @{\r
+ */ \r
+\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_TS_Private_Variables Private Variables\r
+ * @{\r
+ */ \r
+static TS_DrvTypeDef *tsDriver;\r
+static uint16_t tsXBoundary, tsYBoundary; \r
+static uint8_t tsOrientation;\r
+static uint8_t I2cAddress;\r
+\r
+/* Table for touchscreen event information display on LCD : table indexed on enum @ref TS_TouchEventTypeDef information */\r
+char * ts_event_string_tab[TOUCH_EVENT_NB_MAX] = { "None",\r
+ "Press down",\r
+ "Lift up",\r
+ "Contact"\r
+ };\r
+\r
+/* Table for touchscreen gesture Id information display on LCD : table indexed on enum @ref TS_GestureIdTypeDef information */\r
+char * ts_gesture_id_string_tab[GEST_ID_NB_MAX] = { "None",\r
+ "Move Up",\r
+ "Move Right",\r
+ "Move Down",\r
+ "Move Left",\r
+ "Zoom In",\r
+ "Zoom Out"\r
+ };\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup STM32H745I_DISCOVERY_TS_Private_Function_Prototypes Private Function Prototypes\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup STM32H745I_DISCOVERY_TS_Exported_Functions Exported Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Initializes and configures the touch screen functionalities and \r
+ * configures all necessary hardware resources (GPIOs, I2C, clocks..).\r
+ * @param ts_SizeX: Maximum X size of the TS area on LCD\r
+ * @param ts_SizeY: Maximum Y size of the TS area on LCD\r
+ * @retval TS_OK if all initializations are OK. Other value if error.\r
+ */\r
+uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)\r
+{\r
+ uint8_t status = TS_OK;\r
+ tsXBoundary = ts_SizeX;\r
+ tsYBoundary = ts_SizeY;\r
+ \r
+ /* Read ID and verify if the touch screen driver is ready */\r
+ ft5336_ts_drv.Init(TS_I2C_ADDRESS);\r
+ if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE)\r
+ { \r
+ /* Initialize the TS driver structure */\r
+ tsDriver = &ft5336_ts_drv;\r
+ I2cAddress = TS_I2C_ADDRESS;\r
+ tsOrientation = TS_SWAP_XY;\r
+\r
+ /* Initialize the TS driver */\r
+ tsDriver->Start(I2cAddress);\r
+ }\r
+ else\r
+ {\r
+ status = TS_DEVICE_NOT_FOUND;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TouchScreen.\r
+ * @retval TS state\r
+ */\r
+uint8_t BSP_TS_DeInit(void)\r
+{ \r
+ /* Actually ts_driver does not provide a DeInit function */\r
+ return TS_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures and enables the touch screen interrupts.\r
+ * @retval TS_OK if all initializations are OK. Other value if error.\r
+ */\r
+uint8_t BSP_TS_ITConfig(void)\r
+{\r
+ GPIO_InitTypeDef gpio_init_structure;\r
+\r
+ /* Configure Interrupt mode for SD detection pin */\r
+ gpio_init_structure.Pin = TS_INT_PIN;\r
+ gpio_init_structure.Pull = GPIO_NOPULL;\r
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ gpio_init_structure.Mode = GPIO_MODE_IT_RISING;\r
+ HAL_GPIO_Init(TS_INT_GPIO_PORT, &gpio_init_structure);\r
+\r
+ /* Enable and set Touch screen EXTI Interrupt to the lowest priority */\r
+ HAL_NVIC_SetPriority((IRQn_Type)(TS_INT_EXTI_IRQn), 0x0F, 0x00);\r
+ HAL_NVIC_EnableIRQ((IRQn_Type)(TS_INT_EXTI_IRQn));\r
+\r
+ /* Enable the TS ITs */\r
+ tsDriver->EnableIT(I2cAddress);\r
+\r
+ return TS_OK; \r
+}\r
+\r
+/**\r
+ * @brief Gets the touch screen interrupt status.\r
+ * @retval TS_OK if all initializations are OK. Other value if error.\r
+ */\r
+uint8_t BSP_TS_ITGetStatus(void)\r
+{\r
+ /* Return the TS IT status */\r
+ return (tsDriver->GetITStatus(I2cAddress));\r
+}\r
+\r
+/**\r
+ * @brief Returns status and positions of the touch screen.\r
+ * @param TS_State: Pointer to touch screen current state structure\r
+ * @retval TS_OK if all initializations are OK. Other value if error.\r
+ */\r
+uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)\r
+{\r
+ static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};\r
+ static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};\r
+ uint8_t ts_status = TS_OK;\r
+ uint16_t x[TS_MAX_NB_TOUCH];\r
+ uint16_t y[TS_MAX_NB_TOUCH];\r
+ uint16_t brute_x[TS_MAX_NB_TOUCH];\r
+ uint16_t brute_y[TS_MAX_NB_TOUCH];\r
+ uint16_t x_diff;\r
+ uint16_t y_diff;\r
+ uint32_t index;\r
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)\r
+ uint32_t weight = 0;\r
+ uint32_t area = 0;\r
+ uint32_t event = 0;\r
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */\r
+\r
+ /* Check and update the number of touches active detected */\r
+ TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress);\r
+ \r
+ if(TS_State->touchDetected)\r
+ {\r
+ for(index=0; index < TS_State->touchDetected; index++)\r
+ {\r
+ /* Get each touch coordinates */\r
+ tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index]));\r
+\r
+ if(tsOrientation == TS_SWAP_NONE)\r
+ {\r
+ x[index] = brute_x[index];\r
+ y[index] = brute_y[index];\r
+ }\r
+\r
+ if(tsOrientation & TS_SWAP_X)\r
+ {\r
+ x[index] = 4096 - brute_x[index];\r
+ }\r
+\r
+ if(tsOrientation & TS_SWAP_Y)\r
+ {\r
+ y[index] = 4096 - brute_y[index];\r
+ }\r
+\r
+ if(tsOrientation & TS_SWAP_XY)\r
+ {\r
+ y[index] = brute_x[index];\r
+ x[index] = brute_y[index];\r
+ }\r
+\r
+ x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]);\r
+ y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]);\r
+\r
+ if ((x_diff + y_diff) > 5)\r
+ {\r
+ _x[index] = x[index];\r
+ _y[index] = y[index];\r
+ }\r
+\r
+ if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS)\r
+ {\r
+ TS_State->touchX[index] = x[index];\r
+ TS_State->touchY[index] = y[index];\r
+ }\r
+ else\r
+ {\r
+ /* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */\r
+ TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12;\r
+ TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12;\r
+ }\r
+\r
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)\r
+\r
+ /* Get touch info related to the current touch */\r
+ ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event);\r
+\r
+ /* Update TS_State structure */\r
+ TS_State->touchWeight[index] = weight;\r
+ TS_State->touchArea[index] = area;\r
+\r
+ /* Remap touch event */\r
+ switch(event)\r
+ {\r
+ case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN :\r
+ TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;\r
+ break;\r
+ case FT5336_TOUCH_EVT_FLAG_LIFT_UP :\r
+ TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;\r
+ break;\r
+ case FT5336_TOUCH_EVT_FLAG_CONTACT :\r
+ TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;\r
+ break;\r
+ case FT5336_TOUCH_EVT_FLAG_NO_EVENT :\r
+ TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;\r
+ break;\r
+ default :\r
+ ts_status = TS_ERROR;\r
+ break;\r
+ } /* of switch(event) */\r
+\r
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */\r
+\r
+ } /* of for(index=0; index < TS_State->touchDetected; index++) */\r
+\r
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)\r
+ /* Get gesture Id */\r
+ ts_status = BSP_TS_Get_GestureId(TS_State);\r
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */\r
+\r
+ } /* end of if(TS_State->touchDetected != 0) */\r
+\r
+ return (ts_status);\r
+}\r
+\r
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)\r
+/**\r
+ * @brief Update gesture Id following a touch detected.\r
+ * @param TS_State: Pointer to touch screen current state structure\r
+ * @retval TS_OK if all initializations are OK. Other value if error.\r
+ */\r
+uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)\r
+{\r
+ uint32_t gestureId = 0;\r
+ uint8_t ts_status = TS_OK;\r
+\r
+ /* Get gesture Id */\r
+ ft5336_TS_GetGestureID(I2cAddress, &gestureId);\r
+\r
+ /* Remap gesture Id to a TS_GestureIdTypeDef value */\r
+ switch(gestureId)\r
+ {\r
+ case FT5336_GEST_ID_NO_GESTURE :\r
+ TS_State->gestureId = GEST_ID_NO_GESTURE;\r
+ break;\r
+ case FT5336_GEST_ID_MOVE_UP :\r
+ TS_State->gestureId = GEST_ID_MOVE_UP;\r
+ break;\r
+ case FT5336_GEST_ID_MOVE_RIGHT :\r
+ TS_State->gestureId = GEST_ID_MOVE_RIGHT;\r
+ break;\r
+ case FT5336_GEST_ID_MOVE_DOWN :\r
+ TS_State->gestureId = GEST_ID_MOVE_DOWN;\r
+ break;\r
+ case FT5336_GEST_ID_MOVE_LEFT :\r
+ TS_State->gestureId = GEST_ID_MOVE_LEFT;\r
+ break;\r
+ case FT5336_GEST_ID_ZOOM_IN :\r
+ TS_State->gestureId = GEST_ID_ZOOM_IN;\r
+ break;\r
+ case FT5336_GEST_ID_ZOOM_OUT :\r
+ TS_State->gestureId = GEST_ID_ZOOM_OUT;\r
+ break;\r
+ default :\r
+ ts_status = TS_ERROR;\r
+ break;\r
+ } /* of switch(gestureId) */\r
+\r
+ return(ts_status);\r
+}\r
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */\r
+\r
+/**\r
+ * @brief Clears all touch screen interrupts.\r
+ */\r
+void BSP_TS_ITClear(void)\r
+{\r
+ /* Clear TS IT pending bits */\r
+ tsDriver->ClearIT(I2cAddress); \r
+}\r
+\r
+/**\r
+ * @brief Function used to reset all touch data before a new acquisition\r
+ * of touch information.\r
+ * @param TS_State: Pointer to touch screen current state structure\r
+ * @retval TS_OK if OK, TE_ERROR if problem found.\r
+ */\r
+uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State)\r
+{\r
+ uint8_t ts_status = TS_ERROR;\r
+ uint32_t index;\r
+\r
+ if (TS_State != (TS_StateTypeDef *)NULL)\r
+ {\r
+ TS_State->gestureId = GEST_ID_NO_GESTURE;\r
+ TS_State->touchDetected = 0;\r
+\r
+ for(index = 0; index < TS_MAX_NB_TOUCH; index++)\r
+ {\r
+ TS_State->touchX[index] = 0;\r
+ TS_State->touchY[index] = 0;\r
+ TS_State->touchArea[index] = 0;\r
+ TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;\r
+ TS_State->touchWeight[index] = 0;\r
+ }\r
+\r
+ ts_status = TS_OK;\r
+\r
+ } /* of if (TS_State != (TS_StateTypeDef *)NULL) */\r
+\r
+ return (ts_status);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745i_discovery_ts.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains the common defines and functions prototypes for\r
+ * the stm32h745i_discovery_ts.c driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32H745I_DISCOVERY_TS_H\r
+#define __STM32H745I_DISCOVERY_TS_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h745i_discovery.h"\r
+/* Include touch screen FT5336 component Driver */\r
+#include "../Components/ft5336/ft5336.h"\r
+ \r
+/** @addtogroup BSP\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup STM32H745I_DISCOVERY\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup STM32H745I_DISCOVERY_TS\r
+ * @{\r
+ */\r
+\r
+ /** @defgroup STM32H745I_DISCOVERY_TS_Exported_Constants Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @brief With FT5336 : maximum 5 touches detected simultaneously\r
+ */\r
+#define TS_MAX_NB_TOUCH ((uint32_t) FT5336_MAX_DETECTABLE_TOUCH)\r
+\r
+#define TS_NO_IRQ_PENDING ((uint8_t) 0)\r
+#define TS_IRQ_PENDING ((uint8_t) 1)\r
+\r
+#define TS_SWAP_NONE ((uint8_t) 0x01)\r
+#define TS_SWAP_X ((uint8_t) 0x02)\r
+#define TS_SWAP_Y ((uint8_t) 0x04)\r
+#define TS_SWAP_XY ((uint8_t) 0x08)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM32H745I_DISCOVERY_TS_Exported_Types Exported Types\r
+ * @{\r
+ */\r
+/**\r
+* @brief TS_StateTypeDef\r
+* Define TS State structure\r
+*/\r
+typedef struct\r
+{\r
+ uint8_t touchDetected; /*!< Total number of active touches detected at last scan */\r
+ uint16_t touchX[TS_MAX_NB_TOUCH]; /*!< Touch X[0], X[1] coordinates on 12 bits */\r
+ uint16_t touchY[TS_MAX_NB_TOUCH]; /*!< Touch Y[0], Y[1] coordinates on 12 bits */\r
+\r
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)\r
+ uint8_t touchWeight[TS_MAX_NB_TOUCH]; /*!< Touch_Weight[0], Touch_Weight[1] : weight property of touches */\r
+ uint8_t touchEventId[TS_MAX_NB_TOUCH]; /*!< Touch_EventId[0], Touch_EventId[1] : take value of type @ref TS_TouchEventTypeDef */\r
+ uint8_t touchArea[TS_MAX_NB_TOUCH]; /*!< Touch_Area[0], Touch_Area[1] : touch area of each touch */\r
+ uint32_t gestureId; /*!< type of gesture detected : take value of type @ref TS_GestureIdTypeDef */\r
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */\r
+\r
+} TS_StateTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup STM32H745I_DISCOVERY_TS_Exported_Constants Exported Constants\r
+ * @{\r
+ */\r
+\r
+typedef enum \r
+{\r
+ TS_OK = 0x00, /*!< Touch Ok */\r
+ TS_ERROR = 0x01, /*!< Touch Error */\r
+ TS_TIMEOUT = 0x02, /*!< Touch Timeout */\r
+ TS_DEVICE_NOT_FOUND = 0x03 /*!< Touchscreen device not found */\r
+}TS_StatusTypeDef;\r
+\r
+/**\r
+ * @brief TS_GestureIdTypeDef\r
+ * Define Possible managed gesture identification values returned by touch screen\r
+ * driver.\r
+ */\r
+typedef enum\r
+{\r
+ GEST_ID_NO_GESTURE = 0x00, /*!< Gesture not defined / recognized */\r
+ GEST_ID_MOVE_UP = 0x01, /*!< Gesture Move Up */\r
+ GEST_ID_MOVE_RIGHT = 0x02, /*!< Gesture Move Right */\r
+ GEST_ID_MOVE_DOWN = 0x03, /*!< Gesture Move Down */\r
+ GEST_ID_MOVE_LEFT = 0x04, /*!< Gesture Move Left */\r
+ GEST_ID_ZOOM_IN = 0x05, /*!< Gesture Zoom In */\r
+ GEST_ID_ZOOM_OUT = 0x06, /*!< Gesture Zoom Out */\r
+ GEST_ID_NB_MAX = 0x07 /*!< max number of gesture id */\r
+\r
+} TS_GestureIdTypeDef;\r
+\r
+/**\r
+ * @brief TS_TouchEventTypeDef\r
+ * Define Possible touch events kind as returned values\r
+ * by touch screen IC Driver.\r
+ */\r
+typedef enum\r
+{\r
+ TOUCH_EVENT_NO_EVT = 0x00, /*!< Touch Event : undetermined */\r
+ TOUCH_EVENT_PRESS_DOWN = 0x01, /*!< Touch Event Press Down */\r
+ TOUCH_EVENT_LIFT_UP = 0x02, /*!< Touch Event Lift Up */\r
+ TOUCH_EVENT_CONTACT = 0x03, /*!< Touch Event Contact */\r
+ TOUCH_EVENT_NB_MAX = 0x04 /*!< max number of touch events kind */\r
+\r
+} TS_TouchEventTypeDef;\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup STM32H745I_DISCOVERY_TS_Imported_Variables Imported Variables\r
+ * @{\r
+ */ \r
+/**\r
+ * @brief Table for touchscreen event information display on LCD :\r
+ * table indexed on enum @ref TS_TouchEventTypeDef information\r
+ */\r
+extern char * ts_event_string_tab[TOUCH_EVENT_NB_MAX];\r
+\r
+/**\r
+ * @brief Table for touchscreen gesture Id information display on LCD : table indexed\r
+ * on enum @ref TS_GestureIdTypeDef information\r
+ */\r
+extern char * ts_gesture_id_string_tab[GEST_ID_NB_MAX];\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup STM32H745I_DISCOVERY_TS_Exported_Functions\r
+ * @{\r
+ */\r
+uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY);\r
+uint8_t BSP_TS_DeInit(void);\r
+uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State);\r
+\r
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)\r
+uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State);\r
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */\r
+\r
+uint8_t BSP_TS_ITConfig(void);\r
+uint8_t BSP_TS_ITGetStatus(void);\r
+void BSP_TS_ITClear(void);\r
+uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32H745I_DISCOVERY_TS_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h745xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS STM32H745xx Device Peripheral Access Layer Header File.\r
+ *\r
+ * This file contains:\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral's registers hardware\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS_Device\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32h745xx\r
+ * @{\r
+ */\r
+\r
+#ifndef STM32H745xx_H\r
+#define STM32H745xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Peripheral_interrupt_number_definition\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device\r
+ * in @ref Library_configuration_section\r
+ */\r
+typedef enum\r
+{\r
+/****** Cortex-M Processor Exceptions Numbers *****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */\r
+ PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */\r
+ FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */\r
+ FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */\r
+ FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */\r
+ FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+ FMC_IRQn = 48, /*!< FMC global Interrupt */\r
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */\r
+ CM7_SEV_IRQn = 64, /*!< CM7 Send event interrupt for CM4 */\r
+ CM4_SEV_IRQn = 65, /*!< CM4 Send event interrupt for CM7 */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */\r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
+ RNG_IRQn = 80, /*!< RNG global interrupt */\r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */\r
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */\r
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */\r
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */\r
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */\r
+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */\r
+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */\r
+ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */\r
+ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */\r
+ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */\r
+ SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */\r
+ OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */\r
+ OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */\r
+ OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */\r
+ OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */\r
+ DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */\r
+ HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */\r
+ HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */\r
+ HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */\r
+ HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */\r
+ HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */\r
+ HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */\r
+ HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */\r
+ DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */\r
+ DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */\r
+ DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */\r
+ DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */\r
+ SAI3_IRQn = 114, /*!< SAI3 global Interrupt */\r
+ SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */\r
+ TIM15_IRQn = 116, /*!< TIM15 global Interrupt */\r
+ TIM16_IRQn = 117, /*!< TIM16 global Interrupt */\r
+ TIM17_IRQn = 118, /*!< TIM17 global Interrupt */\r
+ MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */\r
+ MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */\r
+ JPEG_IRQn = 121, /*!< JPEG global Interrupt */\r
+ MDMA_IRQn = 122, /*!< MDMA global Interrupt */\r
+ SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */\r
+ HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */\r
+ HSEM2_IRQn = 126, /*!< HSEM2 global Interrupt */\r
+ ADC3_IRQn = 127, /*!< ADC3 global Interrupt */\r
+ DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */\r
+ BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */\r
+ BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */\r
+ BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */\r
+ BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */\r
+ BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */\r
+ BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */\r
+ BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */\r
+ BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */\r
+ COMP_IRQn = 137 , /*!< COMP global Interrupt */\r
+ LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */\r
+ LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */\r
+ LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */\r
+ LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */\r
+ LPUART1_IRQn = 142, /*!< LP UART1 interrupt */\r
+ WWDG_RST_IRQn = 143, /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */\r
+ CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */\r
+ ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */\r
+ SAI4_IRQn = 146, /*!< SAI4 global interrupt */\r
+ HOLD_CORE_IRQn = 148, /*!< Hold core interrupt */\r
+ WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+#define DUAL_CORE /*!< Dual core line feature */\r
+\r
+#define SMPS /*!< Switched mode power supply feature */\r
+\r
+\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals\r
+ */\r
+#ifdef CORE_CM4\r
+#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */\r
+#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+\r
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */\r
+#else /* CORE_CM7 */\r
+#ifdef CORE_CM7\r
+#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */\r
+#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */\r
+#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */\r
+#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */\r
+#else /* UNKNOWN_CORE */\r
+#error Please #define CORE_CM4 or CORE_CM7\r
+#endif /* CORE_CM7 */\r
+#endif /* CORE_CM4 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+#include "system_stm32h7xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Analog to Digital Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */\r
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */\r
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */\r
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */\r
+ __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */\r
+ __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */\r
+ __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */\r
+ uint32_t RESERVED1; /*!< Reserved, 0x028 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */\r
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */\r
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */\r
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */\r
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */\r
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */\r
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */\r
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */\r
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */\r
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */\r
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */\r
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */\r
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */\r
+ __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */\r
+ __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */\r
+ __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */\r
+ __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */\r
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */\r
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */\r
+ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */\r
+} ADC_TypeDef;\r
+\r
+\r
+typedef struct\r
+{\r
+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */\r
+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */\r
+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */\r
+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */\r
+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */\r
+\r
+} ADC_Common_TypeDef;\r
+\r
+/**\r
+ * @brief VREFBUF\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */\r
+ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */\r
+} VREFBUF_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief FD Controller Area Network\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */\r
+ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */\r
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */\r
+ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */\r
+ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */\r
+ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */\r
+ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */\r
+ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */\r
+ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */\r
+ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */\r
+ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */\r
+ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */\r
+ __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */\r
+ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */\r
+ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */\r
+ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */\r
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */\r
+ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */\r
+ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */\r
+ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */\r
+ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */\r
+ __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */\r
+ __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */\r
+ __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */\r
+ __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */\r
+ __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */\r
+ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */\r
+ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */\r
+ __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */\r
+ __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */\r
+ __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */\r
+ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */\r
+ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */\r
+ __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */\r
+ __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */\r
+ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */\r
+ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */\r
+ __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */\r
+ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */\r
+ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */\r
+ __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */\r
+ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */\r
+ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */\r
+ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */\r
+ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */\r
+ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */\r
+ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */\r
+ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */\r
+ __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */\r
+ __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */\r
+ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */\r
+ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */\r
+ __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */\r
+} FDCAN_GlobalTypeDef;\r
+\r
+/**\r
+ * @brief TTFD Controller Area Network\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */\r
+ __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */\r
+ __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */\r
+ __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */\r
+ __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */\r
+ __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */\r
+ __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */\r
+ __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */\r
+ __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */\r
+ __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */\r
+ __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */\r
+ __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */\r
+ __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */\r
+ __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */\r
+ __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */\r
+ __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */\r
+ __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */\r
+ __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */\r
+ __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */\r
+} TTCAN_TypeDef;\r
+\r
+/**\r
+ * @brief FD Controller Area Network\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */\r
+ __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */\r
+ __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */\r
+ __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */\r
+ __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */\r
+} FDCAN_ClockCalibrationUnit_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Consumer Electronics Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */\r
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */\r
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */\r
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */\r
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */\r
+}CEC_TypeDef;\r
+\r
+/**\r
+ * @brief CRC calculation unit\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */\r
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\r
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\r
+} CRC_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Clock Recovery System\r
+ */\r
+typedef struct\r
+{\r
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */\r
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */\r
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */\r
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */\r
+} CRS_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */\r
+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */\r
+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */\r
+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */\r
+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */\r
+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */\r
+} DAC_TypeDef;\r
+\r
+/**\r
+ * @brief DFSDM module registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */\r
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */\r
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */\r
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */\r
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */\r
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */\r
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */\r
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */\r
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */\r
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */\r
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */\r
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */\r
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */\r
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */\r
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */\r
+} DFSDM_Filter_TypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel configuration registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */\r
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */\r
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and\r
+ short circuit detector register, Address offset: 0x08 */\r
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */\r
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */\r
+} DFSDM_Channel_TypeDef;\r
+\r
+/**\r
+ * @brief Debug MCU\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */\r
+ __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */\r
+ __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */\r
+ __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */\r
+ __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */\r
+ __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */\r
+ __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */\r
+ __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */\r
+ __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */\r
+ __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */\r
+ __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */\r
+\r
+}DBGMCU_TypeDef;\r
+/**\r
+ * @brief DCMI\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/**\r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */\r
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */\r
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */\r
+ __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */\r
+ __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */\r
+} BDMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */\r
+} BDMA_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */\r
+}DMAMUX_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< DMA Channel Status Register */\r
+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */\r
+}DMAMUX_ChannelStatus_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */\r
+}DMAMUX_RequestGen_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */\r
+ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */\r
+}DMAMUX_RequestGenStatus_TypeDef;\r
+\r
+/**\r
+ * @brief MDMA Controller\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */\r
+}MDMA_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */\r
+ __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */\r
+ __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */\r
+ __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */\r
+ __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */\r
+ __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */\r
+ __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */\r
+ __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */\r
+ __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */\r
+ __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */\r
+ __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x68 */\r
+ __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */\r
+ __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */\r
+}MDMA_Channel_TypeDef;\r
+\r
+/**\r
+ * @brief DMA2D Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */\r
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */\r
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */\r
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */\r
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */\r
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */\r
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */\r
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */\r
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */\r
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */\r
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */\r
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */\r
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */\r
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */\r
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */\r
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */\r
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */\r
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */\r
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */\r
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */\r
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */\r
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */\r
+} DMA2D_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Ethernet MAC\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACECR;\r
+ __IO uint32_t MACPFR;\r
+ __IO uint32_t MACWTR;\r
+ __IO uint32_t MACHT0R;\r
+ __IO uint32_t MACHT1R;\r
+ uint32_t RESERVED1[14];\r
+ __IO uint32_t MACVTR;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t MACVHTR;\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t MACVIR;\r
+ __IO uint32_t MACIVIR;\r
+ uint32_t RESERVED4[2];\r
+ __IO uint32_t MACTFCR;\r
+ uint32_t RESERVED5[7];\r
+ __IO uint32_t MACRFCR;\r
+ uint32_t RESERVED6[7];\r
+ __IO uint32_t MACISR;\r
+ __IO uint32_t MACIER;\r
+ __IO uint32_t MACRXTXSR;\r
+ uint32_t RESERVED7;\r
+ __IO uint32_t MACPCSR;\r
+ __IO uint32_t MACRWKPFR;\r
+ uint32_t RESERVED8[2];\r
+ __IO uint32_t MACLCSR;\r
+ __IO uint32_t MACLTCR;\r
+ __IO uint32_t MACLETR;\r
+ __IO uint32_t MAC1USTCR;\r
+ uint32_t RESERVED9[12];\r
+ __IO uint32_t MACVR;\r
+ __IO uint32_t MACDR;\r
+ uint32_t RESERVED10;\r
+ __IO uint32_t MACHWF0R;\r
+ __IO uint32_t MACHWF1R;\r
+ __IO uint32_t MACHWF2R;\r
+ uint32_t RESERVED11[54];\r
+ __IO uint32_t MACMDIOAR;\r
+ __IO uint32_t MACMDIODR;\r
+ uint32_t RESERVED12[2];\r
+ __IO uint32_t MACARPAR;\r
+ uint32_t RESERVED13[59];\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR;\r
+ uint32_t RESERVED14[248];\r
+ __IO uint32_t MMCCR;\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR;\r
+ uint32_t RESERVED15[14];\r
+ __IO uint32_t MMCTSCGPR;\r
+ __IO uint32_t MMCTMCGPR;\r
+ int32_t RESERVED16[5];\r
+ __IO uint32_t MMCTPCGR;\r
+ uint32_t RESERVED17[10];\r
+ __IO uint32_t MMCRCRCEPR;\r
+ __IO uint32_t MMCRAEPR;\r
+ uint32_t RESERVED18[10];\r
+ __IO uint32_t MMCRUPGR;\r
+ uint32_t RESERVED19[9];\r
+ __IO uint32_t MMCTLPIMSTR;\r
+ __IO uint32_t MMCTLPITCR;\r
+ __IO uint32_t MMCRLPIMSTR;\r
+ __IO uint32_t MMCRLPITCR;\r
+ uint32_t RESERVED20[65];\r
+ __IO uint32_t MACL3L4C0R;\r
+ __IO uint32_t MACL4A0R;\r
+ uint32_t RESERVED21[2];\r
+ __IO uint32_t MACL3A0R0R;\r
+ __IO uint32_t MACL3A1R0R;\r
+ __IO uint32_t MACL3A2R0R;\r
+ __IO uint32_t MACL3A3R0R;\r
+ uint32_t RESERVED22[4];\r
+ __IO uint32_t MACL3L4C1R;\r
+ __IO uint32_t MACL4A1R;\r
+ uint32_t RESERVED23[2];\r
+ __IO uint32_t MACL3A0R1R;\r
+ __IO uint32_t MACL3A1R1R;\r
+ __IO uint32_t MACL3A2R1R;\r
+ __IO uint32_t MACL3A3R1R;\r
+ uint32_t RESERVED24[108];\r
+ __IO uint32_t MACTSCR;\r
+ __IO uint32_t MACSSIR;\r
+ __IO uint32_t MACSTSR;\r
+ __IO uint32_t MACSTNR;\r
+ __IO uint32_t MACSTSUR;\r
+ __IO uint32_t MACSTNUR;\r
+ __IO uint32_t MACTSAR;\r
+ uint32_t RESERVED25;\r
+ __IO uint32_t MACTSSR;\r
+ uint32_t RESERVED26[3];\r
+ __IO uint32_t MACTTSSNR;\r
+ __IO uint32_t MACTTSSSR;\r
+ uint32_t RESERVED27[2];\r
+ __IO uint32_t MACACR;\r
+ uint32_t RESERVED28;\r
+ __IO uint32_t MACATSNR;\r
+ __IO uint32_t MACATSSR;\r
+ __IO uint32_t MACTSIACR;\r
+ __IO uint32_t MACTSEACR;\r
+ __IO uint32_t MACTSICNR;\r
+ __IO uint32_t MACTSECNR;\r
+ uint32_t RESERVED29[4];\r
+ __IO uint32_t MACPPSCR;\r
+ uint32_t RESERVED30[3];\r
+ __IO uint32_t MACPPSTTSR;\r
+ __IO uint32_t MACPPSTTNR;\r
+ __IO uint32_t MACPPSIR;\r
+ __IO uint32_t MACPPSWR;\r
+ uint32_t RESERVED31[12];\r
+ __IO uint32_t MACPOCR;\r
+ __IO uint32_t MACSPI0R;\r
+ __IO uint32_t MACSPI1R;\r
+ __IO uint32_t MACSPI2R;\r
+ __IO uint32_t MACLMIR;\r
+ uint32_t RESERVED32[11];\r
+ __IO uint32_t MTLOMR;\r
+ uint32_t RESERVED33[7];\r
+ __IO uint32_t MTLISR;\r
+ uint32_t RESERVED34[55];\r
+ __IO uint32_t MTLTQOMR;\r
+ __IO uint32_t MTLTQUR;\r
+ __IO uint32_t MTLTQDR;\r
+ uint32_t RESERVED35[8];\r
+ __IO uint32_t MTLQICSR;\r
+ __IO uint32_t MTLRQOMR;\r
+ __IO uint32_t MTLRQMPOCR;\r
+ __IO uint32_t MTLRQDR;\r
+ uint32_t RESERVED36[177];\r
+ __IO uint32_t DMAMR;\r
+ __IO uint32_t DMASBMR;\r
+ __IO uint32_t DMAISR;\r
+ __IO uint32_t DMADSR;\r
+ uint32_t RESERVED37[60];\r
+ __IO uint32_t DMACCR;\r
+ __IO uint32_t DMACTCR;\r
+ __IO uint32_t DMACRCR;\r
+ uint32_t RESERVED38[2];\r
+ __IO uint32_t DMACTDLAR;\r
+ uint32_t RESERVED39;\r
+ __IO uint32_t DMACRDLAR;\r
+ __IO uint32_t DMACTDTPR;\r
+ uint32_t RESERVED40;\r
+ __IO uint32_t DMACRDTPR;\r
+ __IO uint32_t DMACTDRLR;\r
+ __IO uint32_t DMACRDRLR;\r
+ __IO uint32_t DMACIER;\r
+ __IO uint32_t DMACRIWTR;\r
+__IO uint32_t DMACSFCSR;\r
+ uint32_t RESERVED41;\r
+ __IO uint32_t DMACCATDR;\r
+ uint32_t RESERVED42;\r
+ __IO uint32_t DMACCARDR;\r
+ uint32_t RESERVED43;\r
+ __IO uint32_t DMACCATBR;\r
+ uint32_t RESERVED44;\r
+ __IO uint32_t DMACCARBR;\r
+ __IO uint32_t DMACSR;\r
+uint32_t RESERVED45[2];\r
+__IO uint32_t DMACMFCR;\r
+}ETH_TypeDef;\r
+/**\r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */\r
+__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */\r
+__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */\r
+__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */\r
+__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */\r
+__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */\r
+uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */\r
+__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */\r
+__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */\r
+__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */\r
+__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */\r
+__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */\r
+__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */\r
+uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */\r
+__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */\r
+__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */\r
+__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */\r
+__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */\r
+__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */\r
+__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */\r
+uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */\r
+__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */\r
+__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */\r
+__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */\r
+uint32_t RESERVED4; /*!< Reserved, 0x8C */\r
+__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */\r
+__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */\r
+__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */\r
+uint32_t RESERVED5; /*!< Reserved, 0x9C */\r
+__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */\r
+__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */\r
+__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */\r
+uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */\r
+__IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */\r
+__IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */\r
+__IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */\r
+uint32_t RESERVED7; /*!< Reserved, 0xCC */\r
+__IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */\r
+__IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */\r
+__IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */\r
+uint32_t RESERVED8; /*!< Reserved, 0xDC */\r
+__IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */\r
+__IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */\r
+__IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */\r
+\r
+}EXTI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */\r
+uint32_t RESERVED1; /*!< Reserved, 0x0C */\r
+__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */\r
+__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */\r
+__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */\r
+uint32_t RESERVED2; /*!< Reserved, 0x1C */\r
+__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */\r
+__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */\r
+__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */\r
+}EXTI_Core_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */\r
+ __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */\r
+ __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */\r
+ __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */\r
+ __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */\r
+ __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */\r
+ __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */\r
+ __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */\r
+ __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */\r
+ __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */\r
+ __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */\r
+ __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */\r
+ __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */\r
+ __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */\r
+ __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */\r
+ __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */\r
+ __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */\r
+ __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */\r
+ __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */\r
+ __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */\r
+ __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */\r
+ __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */\r
+ __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */\r
+ uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */\r
+ __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x108 */\r
+ __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */\r
+ __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */\r
+ __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */\r
+ uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */\r
+ __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */\r
+ __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */\r
+ __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */\r
+ __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */\r
+ __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */\r
+ __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */\r
+ uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */\r
+ __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */\r
+ __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */\r
+ __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */\r
+ __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */\r
+ __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */\r
+} FLASH_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r
+} FMC_Bank1_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank1E\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank2\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */\r
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r
+} FMC_Bank2_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank3\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */\r
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
+ uint32_t RESERVED; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank5 and 6\r
+ */\r
+\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
+} FMC_Bank5_6_TypeDef;\r
+\r
+/**\r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/**\r
+ * @brief Operational Amplifier (OPAMP)\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */\r
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */\r
+ __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */\r
+} OPAMP_TypeDef;\r
+\r
+/**\r
+ * @brief System configuration controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */\r
+ __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */\r
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */\r
+ __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */\r
+ __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */\r
+ __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */\r
+ __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */\r
+ uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */\r
+ __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */\r
+ uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */\r
+ __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */\r
+ __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */\r
+ __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */\r
+ __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */\r
+ __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */\r
+ __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */\r
+ __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */\r
+ __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */\r
+ __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */\r
+ __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */\r
+ __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */\r
+ __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */\r
+ __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */\r
+ __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */\r
+ __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */\r
+ __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */\r
+ __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */\r
+ __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */\r
+\r
+} SYSCFG_TypeDef;\r
+\r
+/**\r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\r
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\r
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\r
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\r
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\r
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\r
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */\r
+} I2C_TypeDef;\r
+\r
+/**\r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief JPEG Codec\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */\r
+ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */\r
+ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */\r
+ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */\r
+ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */\r
+ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */\r
+ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */\r
+ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */\r
+ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */\r
+ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */\r
+ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */\r
+ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */\r
+ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */\r
+ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */\r
+ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */\r
+ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */\r
+ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */\r
+ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */\r
+ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */\r
+ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */\r
+ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */\r
+ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */\r
+ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */\r
+ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */\r
+ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */\r
+ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */\r
+ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */\r
+ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */\r
+ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */\r
+\r
+} JPEG_TypeDef;\r
+\r
+/**\r
+ * @brief LCD-TFT Display Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */\r
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */\r
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */\r
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */\r
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */\r
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */\r
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */\r
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */\r
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */\r
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */\r
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */\r
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */\r
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */\r
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */\r
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */\r
+} LTDC_TypeDef;\r
+\r
+/**\r
+ * @brief LCD-TFT Display layer x Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */\r
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */\r
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */\r
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */\r
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */\r
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */\r
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */\r
+ uint32_t RESERVED0[2]; /*!< Reserved */\r
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */\r
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */\r
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */\r
+ uint32_t RESERVED1[3]; /*!< Reserved */\r
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */\r
+\r
+} LTDC_Layer_TypeDef;\r
+\r
+/**\r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */\r
+ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */\r
+ __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */\r
+ __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */\r
+ __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */\r
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */\r
+ __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */\r
+ __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */\r
+ __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */\r
+} PWR_TypeDef;\r
+\r
+/**\r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */\r
+ __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */\r
+ __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */\r
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */\r
+ __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */\r
+ __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */\r
+ __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */\r
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */\r
+ __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */\r
+ __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */\r
+ __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */\r
+ __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */\r
+ __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */\r
+ __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */\r
+ __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */\r
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */\r
+ __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */\r
+ __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */\r
+ __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */\r
+ __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */\r
+ __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */\r
+ __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */\r
+ __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */\r
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */\r
+ __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */\r
+ __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */\r
+ __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */\r
+ __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */\r
+ __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */\r
+ __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */\r
+ uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */\r
+ __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */\r
+ uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */\r
+ __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */\r
+ __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */\r
+ __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */\r
+ __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */\r
+ __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */\r
+ __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */\r
+ uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */\r
+ __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */\r
+ __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */\r
+ __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */\r
+ __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */\r
+ __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */\r
+ uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */\r
+\r
+} RCC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */\r
+ __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */\r
+ __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */\r
+ __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */\r
+ __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */\r
+ __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */\r
+ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */\r
+ __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */\r
+ __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */\r
+ __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */\r
+ __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */\r
+ __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */\r
+ uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */\r
+\r
+} RCC_Core_TypeDef;\r
+\r
+/**\r
+ * @brief Real-Time Clock\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+/**\r
+ * @brief Serial Audio Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
+ uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */\r
+ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */\r
+ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+\r
+/**\r
+ * @brief SPDIF-RX Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */\r
+ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */\r
+ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */\r
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */\r
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x1A */\r
+} SPDIFRX_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Secure digital input/output Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */\r
+ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */\r
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */\r
+ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */\r
+ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */\r
+ __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */\r
+ __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */\r
+ uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */\r
+ uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */\r
+ __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */\r
+} SDMMC_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Delay Block DLYB\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */\r
+ __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */\r
+} DLYB_TypeDef;\r
+\r
+/**\r
+ * @brief HW Semaphore HSEM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */\r
+ __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */\r
+ __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */\r
+ __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */\r
+ __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */\r
+ __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */\r
+ __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */\r
+ __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */\r
+ __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */\r
+ __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */\r
+ uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/\r
+ __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */\r
+ __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */\r
+\r
+} HSEM_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */\r
+ __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */\r
+ __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */\r
+ __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */\r
+} HSEM_Common_TypeDef;\r
+\r
+/**\r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */\r
+ __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */\r
+ __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */\r
+ __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */\r
+ __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */\r
+ uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */\r
+ __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */\r
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */\r
+ __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */\r
+ __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */\r
+ __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */\r
+ __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */\r
+ __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */\r
+\r
+} SPI_TypeDef;\r
+/**\r
+ * @brief QUAD Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */\r
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */\r
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */\r
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */\r
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */\r
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */\r
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */\r
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */\r
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */\r
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */\r
+} QUADSPI_TypeDef;\r
+\r
+/**\r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ uint32_t RESERVED1; /*!< Reserved, 0x50 */\r
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */\r
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */\r
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */\r
+ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */\r
+ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */\r
+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */\r
+} TIM_TypeDef;\r
+\r
+/**\r
+ * @brief LPTIMIMER\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\r
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\r
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\r
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\r
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\r
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\r
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\r
+ uint32_t RESERVED1; /*!< Reserved, 0x20 */\r
+ __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */\r
+} LPTIM_TypeDef;\r
+\r
+/**\r
+ * @brief Comparator\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */\r
+ __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */\r
+ __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */\r
+} COMPOPT_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */\r
+} COMP_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\r
+} COMP_Common_TypeDef;\r
+/**\r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\r
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */\r
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */\r
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\r
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\r
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\r
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\r
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\r
+ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */\r
+} USART_TypeDef;\r
+\r
+/**\r
+ * @brief Single Wire Protocol Master Interface SPWMI\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */\r
+ __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */\r
+ uint32_t RESERVED1; /*!< Reserved, 0x08 */\r
+ __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */\r
+ __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */\r
+ __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */\r
+ __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */\r
+ __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */\r
+ __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */\r
+} SWPMI_TypeDef;\r
+\r
+/**\r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief RAM_ECC_Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RAMECC monitor configuration register */\r
+ __IO uint32_t SR; /*!< RAMECC monitor status register */\r
+ __IO uint32_t FAR; /*!< RAMECC monitor failing address register */\r
+ __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */\r
+ __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */\r
+ __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */\r
+} RAMECC_MonitorTypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IER; /*!< RAMECC interrupt enable register */\r
+} RAMECC_TypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/**\r
+ * @brief High resolution Timer (HRTIM)\r
+ */\r
+/* HRTIM master registers definition */\r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */\r
+ __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */\r
+ __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */\r
+ __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */\r
+ __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */\r
+ __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */\r
+ __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x20 */\r
+ __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */\r
+ __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */\r
+ __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */\r
+ uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */\r
+}HRTIM_Master_TypeDef;\r
+\r
+/* HRTIM Timer A to E registers definition */\r
+typedef struct\r
+{\r
+ __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */\r
+ __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */\r
+ __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */\r
+ __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */\r
+ __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */\r
+ __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */\r
+ __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */\r
+ __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */\r
+ __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */\r
+ __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */\r
+ __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */\r
+ __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */\r
+ __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */\r
+ __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */\r
+ __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */\r
+ __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */\r
+ __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */\r
+ __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */\r
+ __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */\r
+ __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */\r
+ __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */\r
+ __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */\r
+ __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */\r
+ __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */\r
+ __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */\r
+ uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */\r
+}HRTIM_Timerx_TypeDef;\r
+\r
+/* HRTIM common register definition */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */\r
+ __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */\r
+ __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */\r
+ __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */\r
+ __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */\r
+ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */\r
+ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */\r
+ __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */\r
+ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */\r
+ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */\r
+ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */\r
+ __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */\r
+ __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */\r
+ __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */\r
+ __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */\r
+ __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */\r
+ __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */\r
+ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */\r
+ __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */\r
+ __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */\r
+ __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */\r
+ __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */\r
+ __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */\r
+ __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */\r
+ __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */\r
+ __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */\r
+ __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */\r
+}HRTIM_Common_TypeDef;\r
+\r
+/* HRTIM register definition */\r
+typedef struct {\r
+ HRTIM_Master_TypeDef sMasterRegs;\r
+ HRTIM_Timerx_TypeDef sTimerxRegs[5];\r
+ uint32_t RESERVED0[32];\r
+ HRTIM_Common_TypeDef sCommonRegs;\r
+}HRTIM_TypeDef;\r
+/**\r
+ * @brief RNG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+ * @brief MDIOS\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t WRFR;\r
+ __IO uint32_t CWRFR;\r
+ __IO uint32_t RDFR;\r
+ __IO uint32_t CRDFR;\r
+ __IO uint32_t SR;\r
+ __IO uint32_t CLRFR;\r
+ uint32_t RESERVED[57];\r
+ __IO uint32_t DINR0;\r
+ __IO uint32_t DINR1;\r
+ __IO uint32_t DINR2;\r
+ __IO uint32_t DINR3;\r
+ __IO uint32_t DINR4;\r
+ __IO uint32_t DINR5;\r
+ __IO uint32_t DINR6;\r
+ __IO uint32_t DINR7;\r
+ __IO uint32_t DINR8;\r
+ __IO uint32_t DINR9;\r
+ __IO uint32_t DINR10;\r
+ __IO uint32_t DINR11;\r
+ __IO uint32_t DINR12;\r
+ __IO uint32_t DINR13;\r
+ __IO uint32_t DINR14;\r
+ __IO uint32_t DINR15;\r
+ __IO uint32_t DINR16;\r
+ __IO uint32_t DINR17;\r
+ __IO uint32_t DINR18;\r
+ __IO uint32_t DINR19;\r
+ __IO uint32_t DINR20;\r
+ __IO uint32_t DINR21;\r
+ __IO uint32_t DINR22;\r
+ __IO uint32_t DINR23;\r
+ __IO uint32_t DINR24;\r
+ __IO uint32_t DINR25;\r
+ __IO uint32_t DINR26;\r
+ __IO uint32_t DINR27;\r
+ __IO uint32_t DINR28;\r
+ __IO uint32_t DINR29;\r
+ __IO uint32_t DINR30;\r
+ __IO uint32_t DINR31;\r
+ __IO uint32_t DOUTR0;\r
+ __IO uint32_t DOUTR1;\r
+ __IO uint32_t DOUTR2;\r
+ __IO uint32_t DOUTR3;\r
+ __IO uint32_t DOUTR4;\r
+ __IO uint32_t DOUTR5;\r
+ __IO uint32_t DOUTR6;\r
+ __IO uint32_t DOUTR7;\r
+ __IO uint32_t DOUTR8;\r
+ __IO uint32_t DOUTR9;\r
+ __IO uint32_t DOUTR10;\r
+ __IO uint32_t DOUTR11;\r
+ __IO uint32_t DOUTR12;\r
+ __IO uint32_t DOUTR13;\r
+ __IO uint32_t DOUTR14;\r
+ __IO uint32_t DOUTR15;\r
+ __IO uint32_t DOUTR16;\r
+ __IO uint32_t DOUTR17;\r
+ __IO uint32_t DOUTR18;\r
+ __IO uint32_t DOUTR19;\r
+ __IO uint32_t DOUTR20;\r
+ __IO uint32_t DOUTR21;\r
+ __IO uint32_t DOUTR22;\r
+ __IO uint32_t DOUTR23;\r
+ __IO uint32_t DOUTR24;\r
+ __IO uint32_t DOUTR25;\r
+ __IO uint32_t DOUTR26;\r
+ __IO uint32_t DOUTR27;\r
+ __IO uint32_t DOUTR28;\r
+ __IO uint32_t DOUTR29;\r
+ __IO uint32_t DOUTR30;\r
+ __IO uint32_t DOUTR31;\r
+} MDIOS_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_Core_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */\r
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */\r
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */\r
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */\r
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */\r
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */\r
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */\r
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */\r
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */\r
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */\r
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */\r
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */\r
+ uint32_t Reserved30[2]; /*!< Reserved 030h */\r
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */\r
+ __IO uint32_t CID; /*!< User ID Register 03Ch */\r
+ __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/\r
+ __IO uint32_t GHWCFG1; /* User HW config1 044h*/\r
+ __IO uint32_t GHWCFG2; /* User HW config2 048h*/\r
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */\r
+ uint32_t Reserved6; /*!< Reserved 050h */\r
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */\r
+ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */\r
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */\r
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */\r
+ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */\r
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */\r
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */\r
+} USB_OTG_GlobalTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_device_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */\r
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */\r
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */\r
+ uint32_t Reserved0C; /*!< Reserved 80Ch */\r
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */\r
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */\r
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */\r
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */\r
+ uint32_t Reserved20; /*!< Reserved 820h */\r
+ uint32_t Reserved9; /*!< Reserved 824h */\r
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */\r
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */\r
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */\r
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */\r
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */\r
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */\r
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */\r
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */\r
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */\r
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */\r
+} USB_OTG_DeviceTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_IN_Endpoint-Specific_Register\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */\r
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r
+} USB_OTG_INEndpointTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */\r
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r
+} USB_OTG_OUTEndpointTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_Host_Mode_Register_Structures\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */\r
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */\r
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */\r
+ uint32_t Reserved40C; /*!< Reserved 40Ch */\r
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */\r
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */\r
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */\r
+} USB_OTG_HostTypeDef;\r
+\r
+/**\r
+ * @brief USB_OTG_Host_Channel_Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */\r
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */\r
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */\r
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */\r
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */\r
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */\r
+ uint32_t Reserved[2]; /*!< Reserved */\r
+} USB_OTG_HostChannelTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */\r
+#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */\r
+#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */\r
+#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */\r
+#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */\r
+#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */\r
+\r
+#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */\r
+#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */\r
+\r
+#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */\r
+#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */\r
+\r
+#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */\r
+#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */\r
+\r
+#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */\r
+#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */\r
+#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */\r
+\r
+/* Legacy define */\r
+#define FLASH_BASE FLASH_BANK1_BASE\r
+\r
+/*!< Device electronic signature memory map */\r
+#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */\r
+#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */\r
+\r
+\r
+/*!< Peripheral memory map */\r
+#define D2_APB1PERIPH_BASE PERIPH_BASE\r
+#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\r
+#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)\r
+#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)\r
+\r
+#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)\r
+#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)\r
+\r
+#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)\r
+#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)\r
+\r
+/*!< Legacy Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)\r
+\r
+\r
+/*!< D1_AHB1PERIPH peripherals */\r
+\r
+#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)\r
+#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)\r
+#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)\r
+#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)\r
+#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)\r
+#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)\r
+#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)\r
+#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)\r
+#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)\r
+#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)\r
+\r
+/*!< D2_AHB1PERIPH peripherals */\r
+\r
+#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)\r
+#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)\r
+#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)\r
+#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)\r
+#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)\r
+#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)\r
+#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)\r
+#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+\r
+/*!< USB registers base address */\r
+#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)\r
+#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)\r
+#define USB_OTG_GLOBAL_BASE (0x000UL)\r
+#define USB_OTG_DEVICE_BASE (0x800UL)\r
+#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)\r
+#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)\r
+#define USB_OTG_EP_REG_SIZE (0x20UL)\r
+#define USB_OTG_HOST_BASE (0x400UL)\r
+#define USB_OTG_HOST_PORT_BASE (0x440UL)\r
+#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)\r
+#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)\r
+#define USB_OTG_PCGCCTL_BASE (0xE00UL)\r
+#define USB_OTG_FIFO_BASE (0x1000UL)\r
+#define USB_OTG_FIFO_SIZE (0x1000UL)\r
+\r
+/*!< D2_AHB2PERIPH peripherals */\r
+\r
+#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)\r
+#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)\r
+#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)\r
+#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)\r
+#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)\r
+\r
+/*!< D3_AHB1PERIPH peripherals */\r
+#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)\r
+#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)\r
+#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)\r
+#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)\r
+#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)\r
+#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)\r
+#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)\r
+#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)\r
+#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)\r
+#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)\r
+#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)\r
+#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)\r
+#define RCC_C1_BASE (RCC_BASE + 0x130UL)\r
+#define RCC_C2_BASE (RCC_BASE + 0x190UL)\r
+#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)\r
+#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)\r
+#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)\r
+#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)\r
+#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)\r
+#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)\r
+#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)\r
+#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)\r
+\r
+/*!< D1_APB1PERIPH peripherals */\r
+#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)\r
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)\r
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)\r
+#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)\r
+\r
+/*!< D2_APB1PERIPH peripherals */\r
+#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)\r
+#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)\r
+#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)\r
+#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)\r
+#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)\r
+#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)\r
+#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)\r
+#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)\r
+#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)\r
+#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)\r
+\r
+#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL)\r
+\r
+#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)\r
+#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)\r
+#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)\r
+#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)\r
+#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)\r
+#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)\r
+#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)\r
+#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)\r
+#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)\r
+#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)\r
+#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)\r
+#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)\r
+#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)\r
+#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)\r
+#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)\r
+#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)\r
+#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)\r
+#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)\r
+#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)\r
+#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)\r
+#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)\r
+#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)\r
+#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)\r
+#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)\r
+\r
+/*!< D2_APB2PERIPH peripherals */\r
+\r
+#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)\r
+#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)\r
+#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)\r
+#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)\r
+#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)\r
+#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)\r
+#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)\r
+#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)\r
+#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)\r
+#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)\r
+#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)\r
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)\r
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)\r
+#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)\r
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)\r
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)\r
+#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)\r
+#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)\r
+#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)\r
+#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)\r
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)\r
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)\r
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)\r
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)\r
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)\r
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)\r
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)\r
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)\r
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)\r
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)\r
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)\r
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)\r
+#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)\r
+#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)\r
+#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)\r
+#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)\r
+#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)\r
+#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)\r
+#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)\r
+\r
+\r
+/*!< D3_APB1PERIPH peripherals */\r
+#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)\r
+#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)\r
+#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)\r
+#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)\r
+#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)\r
+#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)\r
+#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)\r
+#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)\r
+#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)\r
+#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)\r
+#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)\r
+#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)\r
+#define COMP1_BASE (COMP12_BASE + 0x0CUL)\r
+#define COMP2_BASE (COMP12_BASE + 0x10UL)\r
+#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)\r
+#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)\r
+#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)\r
+\r
+#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL)\r
+\r
+#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)\r
+#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)\r
+#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)\r
+\r
+\r
+\r
+\r
+#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)\r
+#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)\r
+#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)\r
+#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)\r
+#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)\r
+#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)\r
+#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)\r
+#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)\r
+\r
+#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)\r
+#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)\r
+#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)\r
+#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)\r
+#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)\r
+#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)\r
+#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)\r
+#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)\r
+\r
+#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)\r
+#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)\r
+#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)\r
+#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)\r
+#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)\r
+#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)\r
+#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)\r
+#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)\r
+\r
+#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)\r
+#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)\r
+\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)\r
+\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)\r
+\r
+#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)\r
+#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)\r
+#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)\r
+#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)\r
+#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)\r
+#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)\r
+#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)\r
+#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)\r
+#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)\r
+#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)\r
+#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)\r
+#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)\r
+#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)\r
+#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)\r
+#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)\r
+#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)\r
+\r
+#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)\r
+#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)\r
+#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)\r
+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)\r
+#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)\r
+#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)\r
+#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)\r
+#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)\r
+\r
+#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)\r
+#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)\r
+\r
+/*!< FMC Banks registers base address */\r
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)\r
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)\r
+#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)\r
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)\r
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE (0x5C001000UL)\r
+\r
+#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)\r
+#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)\r
+#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)\r
+#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)\r
+#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)\r
+#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)\r
+#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)\r
+#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)\r
+#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)\r
+#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)\r
+#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)\r
+#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)\r
+#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)\r
+#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)\r
+#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)\r
+#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)\r
+\r
+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)\r
+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)\r
+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)\r
+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)\r
+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)\r
+\r
+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)\r
+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)\r
+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)\r
+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)\r
+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)\r
+\r
+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)\r
+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)\r
+\r
+#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)\r
+#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)\r
+\r
+#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define UART7 ((USART_TypeDef *) UART7_BASE)\r
+#define UART8 ((USART_TypeDef *) UART8_BASE)\r
+#define CRS ((CRS_TypeDef *) CRS_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)\r
+#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)\r
+#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)\r
+#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)\r
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)\r
+#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)\r
+#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)\r
+#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)\r
+#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)\r
+#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)\r
+\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)\r
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)\r
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)\r
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)\r
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)\r
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)\r
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)\r
+\r
+\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)\r
+#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)\r
+#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\r
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\r
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\r
+#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)\r
+#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)\r
+#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)\r
+#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)\r
+#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)\r
+#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)\r
+#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)\r
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)\r
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
+#define SAI3 ((SAI_TypeDef *) SAI3_BASE)\r
+#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)\r
+#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)\r
+#define SAI4 ((SAI_TypeDef *) SAI4_BASE)\r
+#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)\r
+#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)\r
+\r
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)\r
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\r
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\r
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\r
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\r
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\r
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\r
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\r
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\r
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\r
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\r
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\r
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\r
+#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)\r
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)\r
+#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)\r
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)\r
+\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)\r
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)\r
+\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)\r
+#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)\r
+\r
+#define BDMA ((BDMA_TypeDef *) BDMA_BASE)\r
+#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)\r
+#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)\r
+#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)\r
+#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)\r
+#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)\r
+#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)\r
+#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)\r
+#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)\r
+\r
+#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)\r
+#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)\r
+#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)\r
+#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)\r
+#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)\r
+#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)\r
+\r
+#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)\r
+#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)\r
+#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)\r
+#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)\r
+#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)\r
+#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)\r
+\r
+#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)\r
+#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)\r
+#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)\r
+\r
+#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)\r
+#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)\r
+#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)\r
+#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)\r
+#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)\r
+#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)\r
+#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)\r
+#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)\r
+#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)\r
+\r
+\r
+#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)\r
+#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)\r
+#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)\r
+#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)\r
+#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)\r
+#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)\r
+#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)\r
+#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)\r
+\r
+#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)\r
+#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)\r
+\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+\r
+\r
+#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\r
+#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\r
+#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\r
+#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\r
+#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)\r
+#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)\r
+#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)\r
+#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)\r
+#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)\r
+#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)\r
+#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)\r
+#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)\r
+#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)\r
+#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)\r
+#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)\r
+#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)\r
+#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)\r
+\r
+#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\r
+#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\r
+#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\r
+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)\r
+#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)\r
+#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)\r
+#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)\r
+#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)\r
+\r
+#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)\r
+#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\r
+\r
+\r
+#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)\r
+#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+\r
+\r
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
+#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)\r
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)\r
+#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)\r
+\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)\r
+#define HSEM ((HSEM_TypeDef *) HSEM_BASE)\r
+#if defined(CORE_CM4)\r
+#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))\r
+#else /* CORE_CM7 */\r
+#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))\r
+#endif /* CORE_CM4 */\r
+\r
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)\r
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
+\r
+#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)\r
+\r
+#define ETH ((ETH_TypeDef *)ETH_BASE)\r
+#define MDMA ((MDMA_TypeDef *)MDMA_BASE)\r
+#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)\r
+#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)\r
+#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)\r
+#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)\r
+#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)\r
+#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)\r
+#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)\r
+#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)\r
+#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)\r
+#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)\r
+#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)\r
+#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)\r
+#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)\r
+#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)\r
+#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)\r
+#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)\r
+\r
+\r
+#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)\r
+#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)\r
+\r
+/* Legacy defines */\r
+#define USB_OTG_HS USB1_OTG_HS\r
+#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE\r
+#define USB_OTG_FS USB2_OTG_FS\r
+#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+\r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************************* ADC VERSION ********************************/\r
+#define ADC_VER_V5_X\r
+/******************** Bit definition for ADC_ISR register ********************/\r
+#define ADC_ISR_ADRDY_Pos (0U)\r
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */\r
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */\r
+#define ADC_ISR_EOSMP_Pos (1U)\r
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */\r
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */\r
+#define ADC_ISR_EOC_Pos (2U)\r
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */\r
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */\r
+#define ADC_ISR_EOS_Pos (3U)\r
+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */\r
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */\r
+#define ADC_ISR_OVR_Pos (4U)\r
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */\r
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */\r
+#define ADC_ISR_JEOC_Pos (5U)\r
+#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */\r
+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */\r
+#define ADC_ISR_JEOS_Pos (6U)\r
+#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */\r
+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */\r
+#define ADC_ISR_AWD1_Pos (7U)\r
+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */\r
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */\r
+#define ADC_ISR_AWD2_Pos (8U)\r
+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */\r
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */\r
+#define ADC_ISR_AWD3_Pos (9U)\r
+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */\r
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */\r
+#define ADC_ISR_JQOVF_Pos (10U)\r
+#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */\r
+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */\r
+\r
+/******************** Bit definition for ADC_IER register ********************/\r
+#define ADC_IER_ADRDYIE_Pos (0U)\r
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */\r
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */\r
+#define ADC_IER_EOSMPIE_Pos (1U)\r
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */\r
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */\r
+#define ADC_IER_EOCIE_Pos (2U)\r
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */\r
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */\r
+#define ADC_IER_EOSIE_Pos (3U)\r
+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */\r
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */\r
+#define ADC_IER_OVRIE_Pos (4U)\r
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */\r
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */\r
+#define ADC_IER_JEOCIE_Pos (5U)\r
+#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */\r
+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */\r
+#define ADC_IER_JEOSIE_Pos (6U)\r
+#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */\r
+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */\r
+#define ADC_IER_AWD1IE_Pos (7U)\r
+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */\r
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */\r
+#define ADC_IER_AWD2IE_Pos (8U)\r
+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */\r
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */\r
+#define ADC_IER_AWD3IE_Pos (9U)\r
+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */\r
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */\r
+#define ADC_IER_JQOVFIE_Pos (10U)\r
+#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */\r
+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */\r
+\r
+/******************** Bit definition for ADC_CR register ********************/\r
+#define ADC_CR_ADEN_Pos (0U)\r
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */\r
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */\r
+#define ADC_CR_ADDIS_Pos (1U)\r
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */\r
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */\r
+#define ADC_CR_ADSTART_Pos (2U)\r
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */\r
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */\r
+#define ADC_CR_JADSTART_Pos (3U)\r
+#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */\r
+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */\r
+#define ADC_CR_ADSTP_Pos (4U)\r
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */\r
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */\r
+#define ADC_CR_JADSTP_Pos (5U)\r
+#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */\r
+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */\r
+#define ADC_CR_BOOST_Pos (8U)\r
+#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */\r
+#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */\r
+#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */\r
+#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */\r
+#define ADC_CR_ADCALLIN_Pos (16U)\r
+#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */\r
+#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */\r
+#define ADC_CR_LINCALRDYW1_Pos (22U)\r
+#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */\r
+#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */\r
+#define ADC_CR_LINCALRDYW2_Pos (23U)\r
+#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */\r
+#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */\r
+#define ADC_CR_LINCALRDYW3_Pos (24U)\r
+#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */\r
+#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */\r
+#define ADC_CR_LINCALRDYW4_Pos (25U)\r
+#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */\r
+#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */\r
+#define ADC_CR_LINCALRDYW5_Pos (26U)\r
+#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */\r
+#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */\r
+#define ADC_CR_LINCALRDYW6_Pos (27U)\r
+#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */\r
+#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */\r
+#define ADC_CR_ADVREGEN_Pos (28U)\r
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */\r
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */\r
+#define ADC_CR_DEEPPWD_Pos (29U)\r
+#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */\r
+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */\r
+#define ADC_CR_ADCALDIF_Pos (30U)\r
+#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */\r
+#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */\r
+#define ADC_CR_ADCAL_Pos (31U)\r
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */\r
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */\r
+\r
+/******************** Bit definition for ADC_CFGR register ********************/\r
+#define ADC_CFGR_DMNGT_Pos (0U)\r
+#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */\r
+#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */\r
+#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */\r
+#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */\r
+\r
+#define ADC_CFGR_RES_Pos (2U)\r
+#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */\r
+#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */\r
+#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */\r
+#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */\r
+#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_CFGR_EXTSEL_Pos (5U)\r
+#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */\r
+#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */\r
+#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */\r
+#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */\r
+#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */\r
+#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */\r
+#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */\r
+\r
+#define ADC_CFGR_EXTEN_Pos (10U)\r
+#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */\r
+#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */\r
+#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */\r
+#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */\r
+\r
+#define ADC_CFGR_OVRMOD_Pos (12U)\r
+#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */\r
+#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */\r
+#define ADC_CFGR_CONT_Pos (13U)\r
+#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */\r
+#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */\r
+#define ADC_CFGR_AUTDLY_Pos (14U)\r
+#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */\r
+#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */\r
+\r
+#define ADC_CFGR_DISCEN_Pos (16U)\r
+#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */\r
+#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */\r
+\r
+#define ADC_CFGR_DISCNUM_Pos (17U)\r
+#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */\r
+#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */\r
+#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */\r
+#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */\r
+#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_CFGR_JDISCEN_Pos (20U)\r
+#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */\r
+#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */\r
+#define ADC_CFGR_JQM_Pos (21U)\r
+#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */\r
+#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */\r
+#define ADC_CFGR_AWD1SGL_Pos (22U)\r
+#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */\r
+#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */\r
+#define ADC_CFGR_AWD1EN_Pos (23U)\r
+#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */\r
+#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */\r
+#define ADC_CFGR_JAWD1EN_Pos (24U)\r
+#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */\r
+#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */\r
+#define ADC_CFGR_JAUTO_Pos (25U)\r
+#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */\r
+#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */\r
+\r
+#define ADC_CFGR_AWD1CH_Pos (26U)\r
+#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */\r
+#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */\r
+#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */\r
+#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */\r
+#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */\r
+#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */\r
+#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */\r
+\r
+#define ADC_CFGR_JQDIS_Pos (31U)\r
+#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */\r
+#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */\r
+\r
+/******************** Bit definition for ADC_CFGR2 register ********************/\r
+#define ADC_CFGR2_ROVSE_Pos (0U)\r
+#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */\r
+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */\r
+#define ADC_CFGR2_JOVSE_Pos (1U)\r
+#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */\r
+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */\r
+\r
+#define ADC_CFGR2_OVSS_Pos (5U)\r
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */\r
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */\r
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */\r
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */\r
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */\r
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */\r
+\r
+#define ADC_CFGR2_TROVS_Pos (9U)\r
+#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */\r
+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */\r
+#define ADC_CFGR2_ROVSM_Pos (10U)\r
+#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */\r
+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */\r
+\r
+#define ADC_CFGR2_RSHIFT1_Pos (11U)\r
+#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */\r
+#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */\r
+#define ADC_CFGR2_RSHIFT2_Pos (12U)\r
+#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */\r
+#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */\r
+#define ADC_CFGR2_RSHIFT3_Pos (13U)\r
+#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */\r
+#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */\r
+#define ADC_CFGR2_RSHIFT4_Pos (14U)\r
+#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */\r
+#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */\r
+\r
+#define ADC_CFGR2_OVSR_Pos (16U)\r
+#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */\r
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */\r
+#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */\r
+#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */\r
+#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */\r
+#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */\r
+#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */\r
+#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */\r
+#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */\r
+#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */\r
+#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */\r
+#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */\r
+\r
+#define ADC_CFGR2_LSHIFT_Pos (28U)\r
+#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */\r
+#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */\r
+#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */\r
+#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */\r
+#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */\r
+#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for ADC_SMPR1 register ********************/\r
+#define ADC_SMPR1_SMP0_Pos (0U)\r
+#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */\r
+#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */\r
+\r
+#define ADC_SMPR1_SMP1_Pos (3U)\r
+#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */\r
+#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */\r
+\r
+#define ADC_SMPR1_SMP2_Pos (6U)\r
+#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */\r
+#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */\r
+\r
+#define ADC_SMPR1_SMP3_Pos (9U)\r
+#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */\r
+#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */\r
+\r
+#define ADC_SMPR1_SMP4_Pos (12U)\r
+#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */\r
+#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SMPR1_SMP5_Pos (15U)\r
+#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */\r
+#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */\r
+\r
+#define ADC_SMPR1_SMP6_Pos (18U)\r
+#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */\r
+#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */\r
+\r
+#define ADC_SMPR1_SMP7_Pos (21U)\r
+#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */\r
+#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */\r
+\r
+#define ADC_SMPR1_SMP8_Pos (24U)\r
+#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */\r
+#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */\r
+\r
+#define ADC_SMPR1_SMP9_Pos (27U)\r
+#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */\r
+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */\r
+#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */\r
+#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */\r
+#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */\r
+\r
+/******************** Bit definition for ADC_SMPR2 register ********************/\r
+#define ADC_SMPR2_SMP10_Pos (0U)\r
+#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */\r
+#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */\r
+\r
+#define ADC_SMPR2_SMP11_Pos (3U)\r
+#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */\r
+#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */\r
+\r
+#define ADC_SMPR2_SMP12_Pos (6U)\r
+#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */\r
+#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */\r
+\r
+#define ADC_SMPR2_SMP13_Pos (9U)\r
+#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */\r
+#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */\r
+\r
+#define ADC_SMPR2_SMP14_Pos (12U)\r
+#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */\r
+#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */\r
+\r
+#define ADC_SMPR2_SMP15_Pos (15U)\r
+#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */\r
+#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */\r
+\r
+#define ADC_SMPR2_SMP16_Pos (18U)\r
+#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */\r
+#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */\r
+\r
+#define ADC_SMPR2_SMP17_Pos (21U)\r
+#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */\r
+#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */\r
+\r
+#define ADC_SMPR2_SMP18_Pos (24U)\r
+#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */\r
+#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */\r
+\r
+#define ADC_SMPR2_SMP19_Pos (27U)\r
+#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */\r
+#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */\r
+#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */\r
+#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */\r
+#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */\r
+\r
+/******************** Bit definition for ADC_PCSEL register ********************/\r
+#define ADC_PCSEL_PCSEL_Pos (0U)\r
+#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */\r
+#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */\r
+#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */\r
+#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */\r
+#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */\r
+#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */\r
+#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */\r
+#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */\r
+#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */\r
+#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */\r
+#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */\r
+#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */\r
+#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */\r
+#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */\r
+#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */\r
+#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */\r
+#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */\r
+#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */\r
+#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */\r
+#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */\r
+#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */\r
+#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */\r
+\r
+/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/\r
+#define ADC_LTR_LT_Pos (0U)\r
+#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */\r
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */\r
+\r
+/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/\r
+#define ADC_HTR_HT_Pos (0U)\r
+#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */\r
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */\r
+\r
+/******************** Bit definition for ADC_SQR1 register ********************/\r
+#define ADC_SQR1_L_Pos (0U)\r
+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */\r
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */\r
+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */\r
+\r
+#define ADC_SQR1_SQ1_Pos (6U)\r
+#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */\r
+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */\r
+#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */\r
+\r
+#define ADC_SQR1_SQ2_Pos (12U)\r
+#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */\r
+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */\r
+#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */\r
+\r
+#define ADC_SQR1_SQ3_Pos (18U)\r
+#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */\r
+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */\r
+#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */\r
+\r
+#define ADC_SQR1_SQ4_Pos (24U)\r
+#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */\r
+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */\r
+#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */\r
+#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */\r
+\r
+/******************** Bit definition for ADC_SQR2 register ********************/\r
+#define ADC_SQR2_SQ5_Pos (0U)\r
+#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */\r
+#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_SQR2_SQ6_Pos (6U)\r
+#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */\r
+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */\r
+#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */\r
+\r
+#define ADC_SQR2_SQ7_Pos (12U)\r
+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */\r
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */\r
+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */\r
+\r
+#define ADC_SQR2_SQ8_Pos (18U)\r
+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */\r
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */\r
+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */\r
+\r
+#define ADC_SQR2_SQ9_Pos (24U)\r
+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */\r
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */\r
+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */\r
+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */\r
+\r
+/******************** Bit definition for ADC_SQR3 register ********************/\r
+#define ADC_SQR3_SQ10_Pos (0U)\r
+#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */\r
+#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_SQR3_SQ11_Pos (6U)\r
+#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */\r
+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */\r
+#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */\r
+\r
+#define ADC_SQR3_SQ12_Pos (12U)\r
+#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */\r
+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */\r
+#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */\r
+\r
+#define ADC_SQR3_SQ13_Pos (18U)\r
+#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */\r
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */\r
+#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */\r
+\r
+#define ADC_SQR3_SQ14_Pos (24U)\r
+#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */\r
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */\r
+#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */\r
+#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */\r
+\r
+/******************** Bit definition for ADC_SQR4 register ********************/\r
+#define ADC_SQR4_SQ15_Pos (0U)\r
+#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */\r
+#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_SQR4_SQ16_Pos (6U)\r
+#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */\r
+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */\r
+#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_RDATA_Pos (0U)\r
+#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */\r
+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */\r
+\r
+/******************** Bit definition for ADC_JSQR register ********************/\r
+#define ADC_JSQR_JL_Pos (0U)\r
+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */\r
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */\r
+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */\r
+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */\r
+\r
+#define ADC_JSQR_JEXTSEL_Pos (2U)\r
+#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */\r
+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */\r
+#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */\r
+#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */\r
+#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */\r
+#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */\r
+#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */\r
+\r
+#define ADC_JSQR_JEXTEN_Pos (7U)\r
+#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */\r
+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */\r
+#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */\r
+#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */\r
+\r
+#define ADC_JSQR_JSQ1_Pos (9U)\r
+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */\r
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */\r
+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */\r
+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */\r
+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */\r
+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */\r
+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */\r
+\r
+#define ADC_JSQR_JSQ2_Pos (15U)\r
+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */\r
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */\r
+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */\r
+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */\r
+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */\r
+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */\r
+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */\r
+\r
+#define ADC_JSQR_JSQ3_Pos (21U)\r
+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */\r
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */\r
+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */\r
+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */\r
+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */\r
+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */\r
+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */\r
+\r
+#define ADC_JSQR_JSQ4_Pos (27U)\r
+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */\r
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */\r
+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */\r
+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */\r
+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */\r
+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */\r
+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for ADC_OFR1 register ********************/\r
+#define ADC_OFR1_OFFSET1_Pos (0U)\r
+#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */\r
+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */\r
+#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */\r
+#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */\r
+#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */\r
+#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */\r
+#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */\r
+#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */\r
+#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */\r
+#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */\r
+#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */\r
+#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */\r
+#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */\r
+#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */\r
+#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */\r
+#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */\r
+#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */\r
+#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */\r
+#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */\r
+#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */\r
+#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */\r
+#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */\r
+#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */\r
+#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */\r
+#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */\r
+#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */\r
+#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */\r
+#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */\r
+\r
+#define ADC_OFR1_OFFSET1_CH_Pos (26U)\r
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */\r
+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */\r
+#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */\r
+#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */\r
+#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */\r
+#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */\r
+#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */\r
+\r
+#define ADC_OFR1_SSATE_Pos (31U)\r
+#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */\r
+#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */\r
+\r
+/******************** Bit definition for ADC_OFR2 register ********************/\r
+#define ADC_OFR2_OFFSET2_Pos (0U)\r
+#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */\r
+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */\r
+#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */\r
+#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */\r
+#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */\r
+#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */\r
+#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */\r
+#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */\r
+#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */\r
+#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */\r
+#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */\r
+#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */\r
+#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */\r
+#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */\r
+#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */\r
+#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */\r
+#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */\r
+#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */\r
+#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */\r
+#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */\r
+#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */\r
+#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */\r
+#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */\r
+#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */\r
+#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */\r
+#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */\r
+#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */\r
+#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */\r
+\r
+#define ADC_OFR2_OFFSET2_CH_Pos (26U)\r
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */\r
+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */\r
+#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */\r
+#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */\r
+#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */\r
+#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */\r
+#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */\r
+\r
+#define ADC_OFR2_SSATE_Pos (31U)\r
+#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */\r
+#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */\r
+\r
+/******************** Bit definition for ADC_OFR3 register ********************/\r
+#define ADC_OFR3_OFFSET3_Pos (0U)\r
+#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */\r
+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */\r
+#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */\r
+#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */\r
+#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */\r
+#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */\r
+#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */\r
+#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */\r
+#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */\r
+#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */\r
+#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */\r
+#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */\r
+#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */\r
+#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */\r
+#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */\r
+#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */\r
+#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */\r
+#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */\r
+#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */\r
+#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */\r
+#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */\r
+#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */\r
+#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */\r
+#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */\r
+#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */\r
+#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */\r
+#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */\r
+#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */\r
+\r
+#define ADC_OFR3_OFFSET3_CH_Pos (26U)\r
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */\r
+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */\r
+#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */\r
+#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */\r
+#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */\r
+#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */\r
+#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */\r
+\r
+#define ADC_OFR3_SSATE_Pos (31U)\r
+#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */\r
+#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */\r
+\r
+/******************** Bit definition for ADC_OFR4 register ********************/\r
+#define ADC_OFR4_OFFSET4_Pos (0U)\r
+#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */\r
+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */\r
+#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */\r
+#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */\r
+#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */\r
+#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */\r
+#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */\r
+#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */\r
+#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */\r
+#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */\r
+#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */\r
+#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */\r
+#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */\r
+#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */\r
+#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */\r
+#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */\r
+#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */\r
+#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */\r
+#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */\r
+#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */\r
+#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */\r
+#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */\r
+#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */\r
+#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */\r
+#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */\r
+#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */\r
+#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */\r
+#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */\r
+\r
+#define ADC_OFR4_OFFSET4_CH_Pos (26U)\r
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */\r
+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */\r
+#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */\r
+#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */\r
+#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */\r
+#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */\r
+#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */\r
+\r
+#define ADC_OFR4_SSATE_Pos (31U)\r
+#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */\r
+#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */\r
+\r
+/******************** Bit definition for ADC_JDR1 register ********************/\r
+#define ADC_JDR1_JDATA_Pos (0U)\r
+#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */\r
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */\r
+#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */\r
+#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */\r
+#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */\r
+#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */\r
+#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */\r
+#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */\r
+#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */\r
+#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */\r
+#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */\r
+#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */\r
+#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */\r
+#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */\r
+#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */\r
+#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */\r
+#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */\r
+#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */\r
+#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */\r
+#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */\r
+#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */\r
+#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */\r
+#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */\r
+#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */\r
+#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */\r
+#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */\r
+#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */\r
+#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */\r
+#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */\r
+#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */\r
+#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */\r
+#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */\r
+#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */\r
+#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for ADC_JDR2 register ********************/\r
+#define ADC_JDR2_JDATA_Pos (0U)\r
+#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */\r
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */\r
+#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */\r
+#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */\r
+#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */\r
+#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */\r
+#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */\r
+#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */\r
+#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */\r
+#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */\r
+#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */\r
+#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */\r
+#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */\r
+#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */\r
+#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */\r
+#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */\r
+#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */\r
+#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */\r
+#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */\r
+#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */\r
+#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */\r
+#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */\r
+#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */\r
+#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */\r
+#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */\r
+#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */\r
+#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */\r
+#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */\r
+#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */\r
+#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */\r
+#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */\r
+#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */\r
+#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */\r
+#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for ADC_JDR3 register ********************/\r
+#define ADC_JDR3_JDATA_Pos (0U)\r
+#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */\r
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */\r
+#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */\r
+#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */\r
+#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */\r
+#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */\r
+#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */\r
+#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */\r
+#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */\r
+#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */\r
+#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */\r
+#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */\r
+#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */\r
+#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */\r
+#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */\r
+#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */\r
+#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */\r
+#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */\r
+#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */\r
+#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */\r
+#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */\r
+#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */\r
+#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */\r
+#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */\r
+#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */\r
+#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */\r
+#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */\r
+#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */\r
+#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */\r
+#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */\r
+#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */\r
+#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */\r
+#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */\r
+#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for ADC_JDR4 register ********************/\r
+#define ADC_JDR4_JDATA_Pos (0U)\r
+#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */\r
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */\r
+#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */\r
+#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */\r
+#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */\r
+#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */\r
+#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */\r
+#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */\r
+#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */\r
+#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */\r
+#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */\r
+#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */\r
+#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */\r
+#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */\r
+#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */\r
+#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */\r
+#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */\r
+#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */\r
+#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */\r
+#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */\r
+#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */\r
+#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */\r
+#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */\r
+#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */\r
+#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */\r
+#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */\r
+#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */\r
+#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */\r
+#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */\r
+#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */\r
+#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */\r
+#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */\r
+#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */\r
+#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for ADC_AWD2CR register ********************/\r
+#define ADC_AWD2CR_AWD2CH_Pos (0U)\r
+#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */\r
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */\r
+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */\r
+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */\r
+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */\r
+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */\r
+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */\r
+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */\r
+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */\r
+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */\r
+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */\r
+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */\r
+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */\r
+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */\r
+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */\r
+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */\r
+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */\r
+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */\r
+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */\r
+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */\r
+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */\r
+#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */\r
+\r
+/******************** Bit definition for ADC_AWD3CR register ********************/\r
+#define ADC_AWD3CR_AWD3CH_Pos (0U)\r
+#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */\r
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */\r
+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */\r
+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */\r
+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */\r
+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */\r
+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */\r
+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */\r
+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */\r
+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */\r
+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */\r
+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */\r
+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */\r
+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */\r
+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */\r
+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */\r
+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */\r
+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */\r
+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */\r
+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */\r
+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */\r
+#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */\r
+\r
+/******************** Bit definition for ADC_DIFSEL register ********************/\r
+#define ADC_DIFSEL_DIFSEL_Pos (0U)\r
+#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */\r
+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */\r
+#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */\r
+#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */\r
+#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */\r
+#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */\r
+#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */\r
+#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */\r
+#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */\r
+#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */\r
+#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */\r
+#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */\r
+#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */\r
+#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */\r
+#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */\r
+#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */\r
+#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */\r
+#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */\r
+#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */\r
+#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */\r
+#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */\r
+#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */\r
+\r
+/******************** Bit definition for ADC_CALFACT register ********************/\r
+#define ADC_CALFACT_CALFACT_S_Pos (0U)\r
+#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */\r
+#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */\r
+#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */\r
+#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */\r
+#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */\r
+#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */\r
+#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */\r
+#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */\r
+#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */\r
+#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */\r
+#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */\r
+#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */\r
+#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */\r
+#define ADC_CALFACT_CALFACT_D_Pos (16U)\r
+#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */\r
+#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */\r
+#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */\r
+#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */\r
+#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */\r
+#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */\r
+#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */\r
+#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */\r
+#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */\r
+#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */\r
+#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */\r
+#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */\r
+#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */\r
+\r
+/******************** Bit definition for ADC_CALFACT2 register ********************/\r
+#define ADC_CALFACT2_LINCALFACT_Pos (0U)\r
+#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */\r
+#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */\r
+#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */\r
+#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */\r
+#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */\r
+#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */\r
+#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */\r
+#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */\r
+#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */\r
+#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */\r
+#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */\r
+#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */\r
+#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */\r
+#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */\r
+#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */\r
+#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */\r
+#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */\r
+#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */\r
+#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */\r
+#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */\r
+#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */\r
+#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */\r
+#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */\r
+#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */\r
+#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */\r
+#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */\r
+#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */\r
+#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */\r
+#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */\r
+#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */\r
+#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */\r
+#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */\r
+\r
+/************************* ADC Common registers *****************************/\r
+/******************** Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_ADRDY_MST_Pos (0U)\r
+#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */\r
+#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */\r
+#define ADC_CSR_EOSMP_MST_Pos (1U)\r
+#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */\r
+#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */\r
+#define ADC_CSR_EOC_MST_Pos (2U)\r
+#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */\r
+#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */\r
+#define ADC_CSR_EOS_MST_Pos (3U)\r
+#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */\r
+#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */\r
+#define ADC_CSR_OVR_MST_Pos (4U)\r
+#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */\r
+#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */\r
+#define ADC_CSR_JEOC_MST_Pos (5U)\r
+#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */\r
+#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */\r
+#define ADC_CSR_JEOS_MST_Pos (6U)\r
+#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */\r
+#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */\r
+#define ADC_CSR_AWD1_MST_Pos (7U)\r
+#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */\r
+#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */\r
+#define ADC_CSR_AWD2_MST_Pos (8U)\r
+#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */\r
+#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */\r
+#define ADC_CSR_AWD3_MST_Pos (9U)\r
+#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */\r
+#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */\r
+#define ADC_CSR_JQOVF_MST_Pos (10U)\r
+#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */\r
+#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */\r
+#define ADC_CSR_ADRDY_SLV_Pos (16U)\r
+#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */\r
+#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */\r
+#define ADC_CSR_EOSMP_SLV_Pos (17U)\r
+#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */\r
+#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */\r
+#define ADC_CSR_EOC_SLV_Pos (18U)\r
+#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */\r
+#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */\r
+#define ADC_CSR_EOS_SLV_Pos (19U)\r
+#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */\r
+#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */\r
+#define ADC_CSR_OVR_SLV_Pos (20U)\r
+#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */\r
+#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */\r
+#define ADC_CSR_JEOC_SLV_Pos (21U)\r
+#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */\r
+#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */\r
+#define ADC_CSR_JEOS_SLV_Pos (22U)\r
+#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */\r
+#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */\r
+#define ADC_CSR_AWD1_SLV_Pos (23U)\r
+#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */\r
+#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */\r
+#define ADC_CSR_AWD2_SLV_Pos (24U)\r
+#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */\r
+#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */\r
+#define ADC_CSR_AWD3_SLV_Pos (25U)\r
+#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */\r
+#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */\r
+#define ADC_CSR_JQOVF_SLV_Pos (26U)\r
+#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */\r
+#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */\r
+\r
+/******************** Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_DUAL_Pos (0U)\r
+#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */\r
+#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */\r
+#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */\r
+#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */\r
+#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */\r
+#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */\r
+#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */\r
+\r
+#define ADC_CCR_DELAY_Pos (8U)\r
+#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */\r
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */\r
+#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */\r
+#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */\r
+#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */\r
+#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */\r
+\r
+\r
+#define ADC_CCR_DAMDF_Pos (14U)\r
+#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */\r
+#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */\r
+#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */\r
+#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */\r
+\r
+#define ADC_CCR_CKMODE_Pos (16U)\r
+#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */\r
+#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */\r
+#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */\r
+#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */\r
+\r
+#define ADC_CCR_PRESC_Pos (18U)\r
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */\r
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */\r
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */\r
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */\r
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */\r
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */\r
+\r
+#define ADC_CCR_VREFEN_Pos (22U)\r
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */\r
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */\r
+#define ADC_CCR_TSEN_Pos (23U)\r
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */\r
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */\r
+#define ADC_CCR_VBATEN_Pos (24U)\r
+#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */\r
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */\r
+\r
+/******************** Bit definition for ADC_CDR register *******************/\r
+#define ADC_CDR_RDATA_MST_Pos (0U)\r
+#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */\r
+#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */\r
+\r
+#define ADC_CDR_RDATA_SLV_Pos (16U)\r
+#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */\r
+#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */\r
+\r
+/******************** Bit definition for ADC_CDR2 register ******************/\r
+#define ADC_CDR2_RDATA_ALT_Pos (0U)\r
+#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */\r
+#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* VREFBUF */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for VREFBUF_CSR register ****************/\r
+#define VREFBUF_CSR_ENVR_Pos (0U)\r
+#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */\r
+#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */\r
+#define VREFBUF_CSR_HIZ_Pos (1U)\r
+#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */\r
+#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */\r
+#define VREFBUF_CSR_VRR_Pos (3U)\r
+#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */\r
+#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */\r
+#define VREFBUF_CSR_VRS_Pos (4U)\r
+#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */\r
+#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */\r
+\r
+#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */\r
+#define VREFBUF_CSR_VRS_OUT2_Pos (4U)\r
+#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */\r
+#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */\r
+#define VREFBUF_CSR_VRS_OUT3_Pos (5U)\r
+#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */\r
+#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */\r
+#define VREFBUF_CSR_VRS_OUT4_Pos (4U)\r
+#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */\r
+#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */\r
+\r
+/******************* Bit definition for VREFBUF_CCR register ****************/\r
+#define VREFBUF_CCR_TRIM_Pos (0U)\r
+#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */\r
+#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Datarate Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<FDCAN control and status registers */\r
+/***************** Bit definition for FDCAN_CREL register *******************/\r
+#define FDCAN_CREL_DAY_Pos (0U)\r
+#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */\r
+#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */\r
+#define FDCAN_CREL_MON_Pos (8U)\r
+#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */\r
+#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */\r
+#define FDCAN_CREL_YEAR_Pos (16U)\r
+#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */\r
+#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */\r
+#define FDCAN_CREL_SUBSTEP_Pos (20U)\r
+#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */\r
+#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */\r
+#define FDCAN_CREL_STEP_Pos (24U)\r
+#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */\r
+#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */\r
+#define FDCAN_CREL_REL_Pos (28U)\r
+#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */\r
+#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */\r
+\r
+/***************** Bit definition for FDCAN_ENDN register *******************/\r
+#define FDCAN_ENDN_ETV_Pos (0U)\r
+#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */\r
+\r
+/***************** Bit definition for FDCAN_DBTP register *******************/\r
+#define FDCAN_DBTP_DSJW_Pos (0U)\r
+#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */\r
+#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */\r
+#define FDCAN_DBTP_DTSEG2_Pos (4U)\r
+#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */\r
+#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */\r
+#define FDCAN_DBTP_DTSEG1_Pos (8U)\r
+#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */\r
+#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */\r
+#define FDCAN_DBTP_DBRP_Pos (16U)\r
+#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */\r
+#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */\r
+#define FDCAN_DBTP_TDC_Pos (23U)\r
+#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */\r
+#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */\r
+\r
+/***************** Bit definition for FDCAN_TEST register *******************/\r
+#define FDCAN_TEST_LBCK_Pos (4U)\r
+#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */\r
+#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */\r
+#define FDCAN_TEST_TX_Pos (5U)\r
+#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */\r
+#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */\r
+#define FDCAN_TEST_RX_Pos (7U)\r
+#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */\r
+#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */\r
+\r
+/***************** Bit definition for FDCAN_RWD register ********************/\r
+#define FDCAN_RWD_WDC_Pos (0U)\r
+#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */\r
+#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */\r
+#define FDCAN_RWD_WDV_Pos (8U)\r
+#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */\r
+#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */\r
+\r
+/***************** Bit definition for FDCAN_CCCR register ********************/\r
+#define FDCAN_CCCR_INIT_Pos (0U)\r
+#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */\r
+#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */\r
+#define FDCAN_CCCR_CCE_Pos (1U)\r
+#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */\r
+#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */\r
+#define FDCAN_CCCR_ASM_Pos (2U)\r
+#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */\r
+#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */\r
+#define FDCAN_CCCR_CSA_Pos (3U)\r
+#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */\r
+#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */\r
+#define FDCAN_CCCR_CSR_Pos (4U)\r
+#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */\r
+#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */\r
+#define FDCAN_CCCR_MON_Pos (5U)\r
+#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */\r
+#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */\r
+#define FDCAN_CCCR_DAR_Pos (6U)\r
+#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */\r
+#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */\r
+#define FDCAN_CCCR_TEST_Pos (7U)\r
+#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */\r
+#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */\r
+#define FDCAN_CCCR_FDOE_Pos (8U)\r
+#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */\r
+#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */\r
+#define FDCAN_CCCR_BRSE_Pos (9U)\r
+#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */\r
+#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */\r
+#define FDCAN_CCCR_PXHD_Pos (12U)\r
+#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */\r
+#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */\r
+#define FDCAN_CCCR_EFBI_Pos (13U)\r
+#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */\r
+#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */\r
+#define FDCAN_CCCR_TXP_Pos (14U)\r
+#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */\r
+#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */\r
+#define FDCAN_CCCR_NISO_Pos (15U)\r
+#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */\r
+#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */\r
+\r
+/***************** Bit definition for FDCAN_NBTP register ********************/\r
+#define FDCAN_NBTP_NTSEG2_Pos (0U)\r
+#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */\r
+#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */\r
+#define FDCAN_NBTP_NTSEG1_Pos (8U)\r
+#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */\r
+#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */\r
+#define FDCAN_NBTP_NBRP_Pos (16U)\r
+#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */\r
+#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */\r
+#define FDCAN_NBTP_NSJW_Pos (25U)\r
+#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */\r
+#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */\r
+\r
+/***************** Bit definition for FDCAN_TSCC register ********************/\r
+#define FDCAN_TSCC_TSS_Pos (0U)\r
+#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */\r
+#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */\r
+#define FDCAN_TSCC_TCP_Pos (16U)\r
+#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */\r
+#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */\r
+\r
+/***************** Bit definition for FDCAN_TSCV register ********************/\r
+#define FDCAN_TSCV_TSC_Pos (0U)\r
+#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */\r
+\r
+/***************** Bit definition for FDCAN_TOCC register ********************/\r
+#define FDCAN_TOCC_ETOC_Pos (0U)\r
+#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */\r
+#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */\r
+#define FDCAN_TOCC_TOS_Pos (1U)\r
+#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */\r
+#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */\r
+#define FDCAN_TOCC_TOP_Pos (16U)\r
+#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */\r
+#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */\r
+\r
+/***************** Bit definition for FDCAN_TOCV register ********************/\r
+#define FDCAN_TOCV_TOC_Pos (0U)\r
+#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */\r
+\r
+/***************** Bit definition for FDCAN_ECR register *********************/\r
+#define FDCAN_ECR_TEC_Pos (0U)\r
+#define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */\r
+#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */\r
+#define FDCAN_ECR_REC_Pos (8U)\r
+#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */\r
+#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */\r
+#define FDCAN_ECR_RP_Pos (15U)\r
+#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */\r
+#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */\r
+#define FDCAN_ECR_CEL_Pos (16U)\r
+#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */\r
+#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */\r
+\r
+/***************** Bit definition for FDCAN_PSR register *********************/\r
+#define FDCAN_PSR_LEC_Pos (0U)\r
+#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */\r
+#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */\r
+#define FDCAN_PSR_ACT_Pos (3U)\r
+#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */\r
+#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */\r
+#define FDCAN_PSR_EP_Pos (5U)\r
+#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */\r
+#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */\r
+#define FDCAN_PSR_EW_Pos (6U)\r
+#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */\r
+#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */\r
+#define FDCAN_PSR_BO_Pos (7U)\r
+#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */\r
+#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */\r
+#define FDCAN_PSR_DLEC_Pos (8U)\r
+#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */\r
+#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */\r
+#define FDCAN_PSR_RESI_Pos (11U)\r
+#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */\r
+#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */\r
+#define FDCAN_PSR_RBRS_Pos (12U)\r
+#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */\r
+#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */\r
+#define FDCAN_PSR_REDL_Pos (13U)\r
+#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */\r
+#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */\r
+#define FDCAN_PSR_PXE_Pos (14U)\r
+#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */\r
+#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */\r
+#define FDCAN_PSR_TDCV_Pos (16U)\r
+#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */\r
+#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */\r
+\r
+/***************** Bit definition for FDCAN_TDCR register ********************/\r
+#define FDCAN_TDCR_TDCF_Pos (0U)\r
+#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */\r
+#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */\r
+#define FDCAN_TDCR_TDCO_Pos (8U)\r
+#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */\r
+#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */\r
+\r
+/***************** Bit definition for FDCAN_IR register **********************/\r
+#define FDCAN_IR_RF0N_Pos (0U)\r
+#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */\r
+#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */\r
+#define FDCAN_IR_RF0W_Pos (1U)\r
+#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */\r
+#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */\r
+#define FDCAN_IR_RF0F_Pos (2U)\r
+#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */\r
+#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */\r
+#define FDCAN_IR_RF0L_Pos (3U)\r
+#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */\r
+#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */\r
+#define FDCAN_IR_RF1N_Pos (4U)\r
+#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */\r
+#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */\r
+#define FDCAN_IR_RF1W_Pos (5U)\r
+#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */\r
+#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */\r
+#define FDCAN_IR_RF1F_Pos (6U)\r
+#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */\r
+#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */\r
+#define FDCAN_IR_RF1L_Pos (7U)\r
+#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */\r
+#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */\r
+#define FDCAN_IR_HPM_Pos (8U)\r
+#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */\r
+#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */\r
+#define FDCAN_IR_TC_Pos (9U)\r
+#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */\r
+#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */\r
+#define FDCAN_IR_TCF_Pos (10U)\r
+#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */\r
+#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */\r
+#define FDCAN_IR_TFE_Pos (11U)\r
+#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */\r
+#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */\r
+#define FDCAN_IR_TEFN_Pos (12U)\r
+#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */\r
+#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */\r
+#define FDCAN_IR_TEFW_Pos (13U)\r
+#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */\r
+#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */\r
+#define FDCAN_IR_TEFF_Pos (14U)\r
+#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */\r
+#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */\r
+#define FDCAN_IR_TEFL_Pos (15U)\r
+#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */\r
+#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */\r
+#define FDCAN_IR_TSW_Pos (16U)\r
+#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */\r
+#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */\r
+#define FDCAN_IR_MRAF_Pos (17U)\r
+#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */\r
+#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */\r
+#define FDCAN_IR_TOO_Pos (18U)\r
+#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */\r
+#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */\r
+#define FDCAN_IR_DRX_Pos (19U)\r
+#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */\r
+#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */\r
+#define FDCAN_IR_ELO_Pos (22U)\r
+#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */\r
+#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */\r
+#define FDCAN_IR_EP_Pos (23U)\r
+#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */\r
+#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */\r
+#define FDCAN_IR_EW_Pos (24U)\r
+#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */\r
+#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */\r
+#define FDCAN_IR_BO_Pos (25U)\r
+#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */\r
+#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */\r
+#define FDCAN_IR_WDI_Pos (26U)\r
+#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */\r
+#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */\r
+#define FDCAN_IR_PEA_Pos (27U)\r
+#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */\r
+#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */\r
+#define FDCAN_IR_PED_Pos (28U)\r
+#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */\r
+#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */\r
+#define FDCAN_IR_ARA_Pos (29U)\r
+#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */\r
+#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */\r
+\r
+/***************** Bit definition for FDCAN_IE register **********************/\r
+#define FDCAN_IE_RF0NE_Pos (0U)\r
+#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */\r
+#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */\r
+#define FDCAN_IE_RF0WE_Pos (1U)\r
+#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */\r
+#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */\r
+#define FDCAN_IE_RF0FE_Pos (2U)\r
+#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */\r
+#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */\r
+#define FDCAN_IE_RF0LE_Pos (3U)\r
+#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */\r
+#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */\r
+#define FDCAN_IE_RF1NE_Pos (4U)\r
+#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */\r
+#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */\r
+#define FDCAN_IE_RF1WE_Pos (5U)\r
+#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */\r
+#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */\r
+#define FDCAN_IE_RF1FE_Pos (6U)\r
+#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */\r
+#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */\r
+#define FDCAN_IE_RF1LE_Pos (7U)\r
+#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */\r
+#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */\r
+#define FDCAN_IE_HPME_Pos (8U)\r
+#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */\r
+#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */\r
+#define FDCAN_IE_TCE_Pos (9U)\r
+#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */\r
+#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */\r
+#define FDCAN_IE_TCFE_Pos (10U)\r
+#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */\r
+#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */\r
+#define FDCAN_IE_TFEE_Pos (11U)\r
+#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */\r
+#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */\r
+#define FDCAN_IE_TEFNE_Pos (12U)\r
+#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */\r
+#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */\r
+#define FDCAN_IE_TEFWE_Pos (13U)\r
+#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */\r
+#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */\r
+#define FDCAN_IE_TEFFE_Pos (14U)\r
+#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */\r
+#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */\r
+#define FDCAN_IE_TEFLE_Pos (15U)\r
+#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */\r
+#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */\r
+#define FDCAN_IE_TSWE_Pos (16U)\r
+#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */\r
+#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */\r
+#define FDCAN_IE_MRAFE_Pos (17U)\r
+#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */\r
+#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */\r
+#define FDCAN_IE_TOOE_Pos (18U)\r
+#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */\r
+#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */\r
+#define FDCAN_IE_DRXE_Pos (19U)\r
+#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */\r
+#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */\r
+#define FDCAN_IE_BECE_Pos (20U)\r
+#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */\r
+#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */\r
+#define FDCAN_IE_BEUE_Pos (21U)\r
+#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */\r
+#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */\r
+#define FDCAN_IE_ELOE_Pos (22U)\r
+#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */\r
+#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */\r
+#define FDCAN_IE_EPE_Pos (23U)\r
+#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */\r
+#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */\r
+#define FDCAN_IE_EWE_Pos (24U)\r
+#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */\r
+#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */\r
+#define FDCAN_IE_BOE_Pos (25U)\r
+#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */\r
+#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */\r
+#define FDCAN_IE_WDIE_Pos (26U)\r
+#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */\r
+#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */\r
+#define FDCAN_IE_PEAE_Pos (27U)\r
+#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */\r
+#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */\r
+#define FDCAN_IE_PEDE_Pos (28U)\r
+#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */\r
+#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */\r
+#define FDCAN_IE_ARAE_Pos (29U)\r
+#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */\r
+#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */\r
+\r
+/***************** Bit definition for FDCAN_ILS register **********************/\r
+#define FDCAN_ILS_RF0NL_Pos (0U)\r
+#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */\r
+#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */\r
+#define FDCAN_ILS_RF0WL_Pos (1U)\r
+#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */\r
+#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */\r
+#define FDCAN_ILS_RF0FL_Pos (2U)\r
+#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */\r
+#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */\r
+#define FDCAN_ILS_RF0LL_Pos (3U)\r
+#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */\r
+#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */\r
+#define FDCAN_ILS_RF1NL_Pos (4U)\r
+#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */\r
+#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */\r
+#define FDCAN_ILS_RF1WL_Pos (5U)\r
+#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */\r
+#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */\r
+#define FDCAN_ILS_RF1FL_Pos (6U)\r
+#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */\r
+#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */\r
+#define FDCAN_ILS_RF1LL_Pos (7U)\r
+#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */\r
+#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */\r
+#define FDCAN_ILS_HPML_Pos (8U)\r
+#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */\r
+#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */\r
+#define FDCAN_ILS_TCL_Pos (9U)\r
+#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */\r
+#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */\r
+#define FDCAN_ILS_TCFL_Pos (10U)\r
+#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */\r
+#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */\r
+#define FDCAN_ILS_TFEL_Pos (11U)\r
+#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */\r
+#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */\r
+#define FDCAN_ILS_TEFNL_Pos (12U)\r
+#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */\r
+#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */\r
+#define FDCAN_ILS_TEFWL_Pos (13U)\r
+#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */\r
+#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */\r
+#define FDCAN_ILS_TEFFL_Pos (14U)\r
+#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */\r
+#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */\r
+#define FDCAN_ILS_TEFLL_Pos (15U)\r
+#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */\r
+#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */\r
+#define FDCAN_ILS_TSWL_Pos (16U)\r
+#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */\r
+#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */\r
+#define FDCAN_ILS_MRAFE_Pos (17U)\r
+#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */\r
+#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */\r
+#define FDCAN_ILS_TOOE_Pos (18U)\r
+#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */\r
+#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */\r
+#define FDCAN_ILS_DRXE_Pos (19U)\r
+#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */\r
+#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */\r
+#define FDCAN_ILS_BECE_Pos (20U)\r
+#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */\r
+#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */\r
+#define FDCAN_ILS_BEUE_Pos (21U)\r
+#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */\r
+#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */\r
+#define FDCAN_ILS_ELOE_Pos (22U)\r
+#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */\r
+#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */\r
+#define FDCAN_ILS_EPE_Pos (23U)\r
+#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */\r
+#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */\r
+#define FDCAN_ILS_EWE_Pos (24U)\r
+#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */\r
+#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */\r
+#define FDCAN_ILS_BOE_Pos (25U)\r
+#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */\r
+#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */\r
+#define FDCAN_ILS_WDIE_Pos (26U)\r
+#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */\r
+#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */\r
+#define FDCAN_ILS_PEAE_Pos (27U)\r
+#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */\r
+#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */\r
+#define FDCAN_ILS_PEDE_Pos (28U)\r
+#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */\r
+#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */\r
+#define FDCAN_ILS_ARAE_Pos (29U)\r
+#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */\r
+#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */\r
+\r
+/***************** Bit definition for FDCAN_ILE register **********************/\r
+#define FDCAN_ILE_EINT0_Pos (0U)\r
+#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */\r
+#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */\r
+#define FDCAN_ILE_EINT1_Pos (1U)\r
+#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */\r
+#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */\r
+\r
+/***************** Bit definition for FDCAN_GFC register **********************/\r
+#define FDCAN_GFC_RRFE_Pos (0U)\r
+#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */\r
+#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */\r
+#define FDCAN_GFC_RRFS_Pos (1U)\r
+#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */\r
+#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */\r
+#define FDCAN_GFC_ANFE_Pos (2U)\r
+#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */\r
+#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */\r
+#define FDCAN_GFC_ANFS_Pos (4U)\r
+#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */\r
+#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */\r
+\r
+/***************** Bit definition for FDCAN_SIDFC register ********************/\r
+#define FDCAN_SIDFC_FLSSA_Pos (2U)\r
+#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */\r
+#define FDCAN_SIDFC_LSS_Pos (16U)\r
+#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */\r
+#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */\r
+\r
+/***************** Bit definition for FDCAN_XIDFC register ********************/\r
+#define FDCAN_XIDFC_FLESA_Pos (2U)\r
+#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */\r
+#define FDCAN_XIDFC_LSE_Pos (16U)\r
+#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */\r
+#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */\r
+\r
+/***************** Bit definition for FDCAN_XIDAM register ********************/\r
+#define FDCAN_XIDAM_EIDM_Pos (0U)\r
+#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */\r
+#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */\r
+\r
+/***************** Bit definition for FDCAN_HPMS register *********************/\r
+#define FDCAN_HPMS_BIDX_Pos (0U)\r
+#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */\r
+#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */\r
+#define FDCAN_HPMS_MSI_Pos (6U)\r
+#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */\r
+#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */\r
+#define FDCAN_HPMS_FIDX_Pos (8U)\r
+#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */\r
+#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */\r
+#define FDCAN_HPMS_FLST_Pos (15U)\r
+#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */\r
+#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */\r
+\r
+/***************** Bit definition for FDCAN_NDAT1 register ********************/\r
+#define FDCAN_NDAT1_ND0_Pos (0U)\r
+#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */\r
+#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */\r
+#define FDCAN_NDAT1_ND1_Pos (1U)\r
+#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */\r
+#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */\r
+#define FDCAN_NDAT1_ND2_Pos (2U)\r
+#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */\r
+#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */\r
+#define FDCAN_NDAT1_ND3_Pos (3U)\r
+#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */\r
+#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */\r
+#define FDCAN_NDAT1_ND4_Pos (4U)\r
+#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */\r
+#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */\r
+#define FDCAN_NDAT1_ND5_Pos (5U)\r
+#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */\r
+#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */\r
+#define FDCAN_NDAT1_ND6_Pos (6U)\r
+#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */\r
+#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */\r
+#define FDCAN_NDAT1_ND7_Pos (7U)\r
+#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */\r
+#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */\r
+#define FDCAN_NDAT1_ND8_Pos (8U)\r
+#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */\r
+#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */\r
+#define FDCAN_NDAT1_ND9_Pos (9U)\r
+#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */\r
+#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */\r
+#define FDCAN_NDAT1_ND10_Pos (10U)\r
+#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */\r
+#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */\r
+#define FDCAN_NDAT1_ND11_Pos (11U)\r
+#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */\r
+#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */\r
+#define FDCAN_NDAT1_ND12_Pos (12U)\r
+#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */\r
+#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */\r
+#define FDCAN_NDAT1_ND13_Pos (13U)\r
+#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */\r
+#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */\r
+#define FDCAN_NDAT1_ND14_Pos (14U)\r
+#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */\r
+#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */\r
+#define FDCAN_NDAT1_ND15_Pos (15U)\r
+#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */\r
+#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */\r
+#define FDCAN_NDAT1_ND16_Pos (16U)\r
+#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */\r
+#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */\r
+#define FDCAN_NDAT1_ND17_Pos (17U)\r
+#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */\r
+#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */\r
+#define FDCAN_NDAT1_ND18_Pos (18U)\r
+#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */\r
+#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */\r
+#define FDCAN_NDAT1_ND19_Pos (19U)\r
+#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */\r
+#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */\r
+#define FDCAN_NDAT1_ND20_Pos (20U)\r
+#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */\r
+#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */\r
+#define FDCAN_NDAT1_ND21_Pos (21U)\r
+#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */\r
+#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */\r
+#define FDCAN_NDAT1_ND22_Pos (22U)\r
+#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */\r
+#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */\r
+#define FDCAN_NDAT1_ND23_Pos (23U)\r
+#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */\r
+#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */\r
+#define FDCAN_NDAT1_ND24_Pos (24U)\r
+#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */\r
+#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */\r
+#define FDCAN_NDAT1_ND25_Pos (25U)\r
+#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */\r
+#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */\r
+#define FDCAN_NDAT1_ND26_Pos (26U)\r
+#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */\r
+#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */\r
+#define FDCAN_NDAT1_ND27_Pos (27U)\r
+#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */\r
+#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */\r
+#define FDCAN_NDAT1_ND28_Pos (28U)\r
+#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */\r
+#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */\r
+#define FDCAN_NDAT1_ND29_Pos (29U)\r
+#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */\r
+#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */\r
+#define FDCAN_NDAT1_ND30_Pos (30U)\r
+#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */\r
+#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */\r
+#define FDCAN_NDAT1_ND31_Pos (31U)\r
+#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */\r
+#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */\r
+\r
+/***************** Bit definition for FDCAN_NDAT2 register ********************/\r
+#define FDCAN_NDAT2_ND32_Pos (0U)\r
+#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */\r
+#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */\r
+#define FDCAN_NDAT2_ND33_Pos (1U)\r
+#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */\r
+#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */\r
+#define FDCAN_NDAT2_ND34_Pos (2U)\r
+#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */\r
+#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */\r
+#define FDCAN_NDAT2_ND35_Pos (3U)\r
+#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */\r
+#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */\r
+#define FDCAN_NDAT2_ND36_Pos (4U)\r
+#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */\r
+#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */\r
+#define FDCAN_NDAT2_ND37_Pos (5U)\r
+#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */\r
+#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */\r
+#define FDCAN_NDAT2_ND38_Pos (6U)\r
+#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */\r
+#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */\r
+#define FDCAN_NDAT2_ND39_Pos (7U)\r
+#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */\r
+#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */\r
+#define FDCAN_NDAT2_ND40_Pos (8U)\r
+#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */\r
+#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */\r
+#define FDCAN_NDAT2_ND41_Pos (9U)\r
+#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */\r
+#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */\r
+#define FDCAN_NDAT2_ND42_Pos (10U)\r
+#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */\r
+#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */\r
+#define FDCAN_NDAT2_ND43_Pos (11U)\r
+#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */\r
+#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */\r
+#define FDCAN_NDAT2_ND44_Pos (12U)\r
+#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */\r
+#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */\r
+#define FDCAN_NDAT2_ND45_Pos (13U)\r
+#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */\r
+#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */\r
+#define FDCAN_NDAT2_ND46_Pos (14U)\r
+#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */\r
+#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */\r
+#define FDCAN_NDAT2_ND47_Pos (15U)\r
+#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */\r
+#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */\r
+#define FDCAN_NDAT2_ND48_Pos (16U)\r
+#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */\r
+#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */\r
+#define FDCAN_NDAT2_ND49_Pos (17U)\r
+#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */\r
+#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */\r
+#define FDCAN_NDAT2_ND50_Pos (18U)\r
+#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */\r
+#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */\r
+#define FDCAN_NDAT2_ND51_Pos (19U)\r
+#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */\r
+#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */\r
+#define FDCAN_NDAT2_ND52_Pos (20U)\r
+#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */\r
+#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */\r
+#define FDCAN_NDAT2_ND53_Pos (21U)\r
+#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */\r
+#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */\r
+#define FDCAN_NDAT2_ND54_Pos (22U)\r
+#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */\r
+#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */\r
+#define FDCAN_NDAT2_ND55_Pos (23U)\r
+#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */\r
+#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */\r
+#define FDCAN_NDAT2_ND56_Pos (24U)\r
+#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */\r
+#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */\r
+#define FDCAN_NDAT2_ND57_Pos (25U)\r
+#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */\r
+#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */\r
+#define FDCAN_NDAT2_ND58_Pos (26U)\r
+#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */\r
+#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */\r
+#define FDCAN_NDAT2_ND59_Pos (27U)\r
+#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */\r
+#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */\r
+#define FDCAN_NDAT2_ND60_Pos (28U)\r
+#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */\r
+#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */\r
+#define FDCAN_NDAT2_ND61_Pos (29U)\r
+#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */\r
+#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */\r
+#define FDCAN_NDAT2_ND62_Pos (30U)\r
+#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */\r
+#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */\r
+#define FDCAN_NDAT2_ND63_Pos (31U)\r
+#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */\r
+#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */\r
+\r
+/***************** Bit definition for FDCAN_RXF0C register ********************/\r
+#define FDCAN_RXF0C_F0SA_Pos (2U)\r
+#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */\r
+#define FDCAN_RXF0C_F0S_Pos (16U)\r
+#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */\r
+#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */\r
+#define FDCAN_RXF0C_F0WM_Pos (24U)\r
+#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */\r
+#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */\r
+#define FDCAN_RXF0C_F0OM_Pos (31U)\r
+#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */\r
+#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */\r
+\r
+/***************** Bit definition for FDCAN_RXF0S register ********************/\r
+#define FDCAN_RXF0S_F0FL_Pos (0U)\r
+#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */\r
+#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */\r
+#define FDCAN_RXF0S_F0GI_Pos (8U)\r
+#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */\r
+#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */\r
+#define FDCAN_RXF0S_F0PI_Pos (16U)\r
+#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */\r
+#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */\r
+#define FDCAN_RXF0S_F0F_Pos (24U)\r
+#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */\r
+#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */\r
+#define FDCAN_RXF0S_RF0L_Pos (25U)\r
+#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */\r
+#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */\r
+\r
+/***************** Bit definition for FDCAN_RXF0A register ********************/\r
+#define FDCAN_RXF0A_F0AI_Pos (0U)\r
+#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */\r
+#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */\r
+\r
+/***************** Bit definition for FDCAN_RXBC register ********************/\r
+#define FDCAN_RXBC_RBSA_Pos (2U)\r
+#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */\r
+\r
+/***************** Bit definition for FDCAN_RXF1C register ********************/\r
+#define FDCAN_RXF1C_F1SA_Pos (2U)\r
+#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */\r
+#define FDCAN_RXF1C_F1S_Pos (16U)\r
+#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */\r
+#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */\r
+#define FDCAN_RXF1C_F1WM_Pos (24U)\r
+#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */\r
+#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */\r
+#define FDCAN_RXF1C_F1OM_Pos (31U)\r
+#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */\r
+#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */\r
+\r
+/***************** Bit definition for FDCAN_RXF1S register ********************/\r
+#define FDCAN_RXF1S_F1FL_Pos (0U)\r
+#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */\r
+#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */\r
+#define FDCAN_RXF1S_F1GI_Pos (8U)\r
+#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */\r
+#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */\r
+#define FDCAN_RXF1S_F1PI_Pos (16U)\r
+#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */\r
+#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */\r
+#define FDCAN_RXF1S_F1F_Pos (24U)\r
+#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */\r
+#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */\r
+#define FDCAN_RXF1S_RF1L_Pos (25U)\r
+#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */\r
+#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */\r
+\r
+/***************** Bit definition for FDCAN_RXF1A register ********************/\r
+#define FDCAN_RXF1A_F1AI_Pos (0U)\r
+#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */\r
+#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */\r
+\r
+/***************** Bit definition for FDCAN_RXESC register ********************/\r
+#define FDCAN_RXESC_F0DS_Pos (0U)\r
+#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */\r
+#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */\r
+#define FDCAN_RXESC_F1DS_Pos (4U)\r
+#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */\r
+#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */\r
+#define FDCAN_RXESC_RBDS_Pos (8U)\r
+#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */\r
+#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */\r
+\r
+/***************** Bit definition for FDCAN_TXBC register *********************/\r
+#define FDCAN_TXBC_TBSA_Pos (2U)\r
+#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */\r
+#define FDCAN_TXBC_NDTB_Pos (16U)\r
+#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */\r
+#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */\r
+#define FDCAN_TXBC_TFQS_Pos (24U)\r
+#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */\r
+#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */\r
+#define FDCAN_TXBC_TFQM_Pos (30U)\r
+#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */\r
+#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */\r
+\r
+/***************** Bit definition for FDCAN_TXFQS register *********************/\r
+#define FDCAN_TXFQS_TFFL_Pos (0U)\r
+#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */\r
+#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */\r
+#define FDCAN_TXFQS_TFGI_Pos (8U)\r
+#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */\r
+#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */\r
+#define FDCAN_TXFQS_TFQPI_Pos (16U)\r
+#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */\r
+#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */\r
+#define FDCAN_TXFQS_TFQF_Pos (21U)\r
+#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */\r
+#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */\r
+\r
+/***************** Bit definition for FDCAN_TXESC register *********************/\r
+#define FDCAN_TXESC_TBDS_Pos (0U)\r
+#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */\r
+#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */\r
+\r
+/***************** Bit definition for FDCAN_TXBRP register *********************/\r
+#define FDCAN_TXBRP_TRP_Pos (0U)\r
+#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */\r
+\r
+/***************** Bit definition for FDCAN_TXBAR register *********************/\r
+#define FDCAN_TXBAR_AR_Pos (0U)\r
+#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */\r
+\r
+/***************** Bit definition for FDCAN_TXBCR register *********************/\r
+#define FDCAN_TXBCR_CR_Pos (0U)\r
+#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */\r
+\r
+/***************** Bit definition for FDCAN_TXBTO register *********************/\r
+#define FDCAN_TXBTO_TO_Pos (0U)\r
+#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */\r
+\r
+/***************** Bit definition for FDCAN_TXBCF register *********************/\r
+#define FDCAN_TXBCF_CF_Pos (0U)\r
+#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */\r
+\r
+/***************** Bit definition for FDCAN_TXBTIE register ********************/\r
+#define FDCAN_TXBTIE_TIE_Pos (0U)\r
+#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */\r
+\r
+/***************** Bit definition for FDCAN_ TXBCIE register *******************/\r
+#define FDCAN_TXBCIE_CFIE_Pos (0U)\r
+#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */\r
+#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */\r
+\r
+/***************** Bit definition for FDCAN_TXEFC register *********************/\r
+#define FDCAN_TXEFC_EFSA_Pos (2U)\r
+#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */\r
+#define FDCAN_TXEFC_EFS_Pos (16U)\r
+#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */\r
+#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */\r
+#define FDCAN_TXEFC_EFWM_Pos (24U)\r
+#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */\r
+#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */\r
+\r
+/***************** Bit definition for FDCAN_TXEFS register *********************/\r
+#define FDCAN_TXEFS_EFFL_Pos (0U)\r
+#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */\r
+#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */\r
+#define FDCAN_TXEFS_EFGI_Pos (8U)\r
+#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */\r
+#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */\r
+#define FDCAN_TXEFS_EFPI_Pos (16U)\r
+#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */\r
+#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */\r
+#define FDCAN_TXEFS_EFF_Pos (24U)\r
+#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */\r
+#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */\r
+#define FDCAN_TXEFS_TEFL_Pos (25U)\r
+#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */\r
+#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */\r
+\r
+/***************** Bit definition for FDCAN_TXEFA register *********************/\r
+#define FDCAN_TXEFA_EFAI_Pos (0U)\r
+#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */\r
+#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */\r
+\r
+/***************** Bit definition for FDCAN_TTTMC register *********************/\r
+#define FDCAN_TTTMC_TMSA_Pos (2U)\r
+#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */\r
+#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */\r
+#define FDCAN_TTTMC_TME_Pos (16U)\r
+#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */\r
+#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */\r
+\r
+/***************** Bit definition for FDCAN_TTRMC register *********************/\r
+#define FDCAN_TTRMC_RID_Pos (0U)\r
+#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */\r
+#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */\r
+#define FDCAN_TTRMC_XTD_Pos (30U)\r
+#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */\r
+#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */\r
+#define FDCAN_TTRMC_RMPS_Pos (31U)\r
+#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */\r
+#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */\r
+\r
+/***************** Bit definition for FDCAN_TTOCF register *********************/\r
+#define FDCAN_TTOCF_OM_Pos (0U)\r
+#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */\r
+#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */\r
+#define FDCAN_TTOCF_GEN_Pos (3U)\r
+#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */\r
+#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */\r
+#define FDCAN_TTOCF_TM_Pos (4U)\r
+#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */\r
+#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */\r
+#define FDCAN_TTOCF_LDSDL_Pos (5U)\r
+#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */\r
+#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */\r
+#define FDCAN_TTOCF_IRTO_Pos (8U)\r
+#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */\r
+#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */\r
+#define FDCAN_TTOCF_EECS_Pos (15U)\r
+#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */\r
+#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */\r
+#define FDCAN_TTOCF_AWL_Pos (16U)\r
+#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */\r
+#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */\r
+#define FDCAN_TTOCF_EGTF_Pos (24U)\r
+#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */\r
+#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */\r
+#define FDCAN_TTOCF_ECC_Pos (25U)\r
+#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */\r
+#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */\r
+#define FDCAN_TTOCF_EVTP_Pos (26U)\r
+#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */\r
+#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */\r
+\r
+/***************** Bit definition for FDCAN_TTMLM register *********************/\r
+#define FDCAN_TTMLM_CCM_Pos (0U)\r
+#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */\r
+#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */\r
+#define FDCAN_TTMLM_CSS_Pos (6U)\r
+#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */\r
+#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */\r
+#define FDCAN_TTMLM_TXEW_Pos (8U)\r
+#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */\r
+#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */\r
+#define FDCAN_TTMLM_ENTT_Pos (16U)\r
+#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */\r
+#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */\r
+\r
+/***************** Bit definition for FDCAN_TURCF register *********************/\r
+#define FDCAN_TURCF_NCL_Pos (0U)\r
+#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */\r
+#define FDCAN_TURCF_DC_Pos (16U)\r
+#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */\r
+#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */\r
+#define FDCAN_TURCF_ELT_Pos (31U)\r
+#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */\r
+#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */\r
+\r
+/***************** Bit definition for FDCAN_TTOCN register ********************/\r
+#define FDCAN_TTOCN_SGT_Pos (0U)\r
+#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */\r
+#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */\r
+#define FDCAN_TTOCN_ECS_Pos (1U)\r
+#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */\r
+#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */\r
+#define FDCAN_TTOCN_SWP_Pos (2U)\r
+#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */\r
+#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */\r
+#define FDCAN_TTOCN_SWS_Pos (3U)\r
+#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */\r
+#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */\r
+#define FDCAN_TTOCN_RTIE_Pos (5U)\r
+#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */\r
+#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */\r
+#define FDCAN_TTOCN_TMC_Pos (6U)\r
+#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */\r
+#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */\r
+#define FDCAN_TTOCN_TTIE_Pos (8U)\r
+#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */\r
+#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */\r
+#define FDCAN_TTOCN_GCS_Pos (9U)\r
+#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */\r
+#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */\r
+#define FDCAN_TTOCN_FGP_Pos (10U)\r
+#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */\r
+#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */\r
+#define FDCAN_TTOCN_TMG_Pos (11U)\r
+#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */\r
+#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */\r
+#define FDCAN_TTOCN_NIG_Pos (12U)\r
+#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */\r
+#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */\r
+#define FDCAN_TTOCN_ESCN_Pos (13U)\r
+#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */\r
+#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */\r
+#define FDCAN_TTOCN_LCKC_Pos (15U)\r
+#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */\r
+#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */\r
+\r
+/***************** Bit definition for FDCAN_TTGTP register ********************/\r
+#define FDCAN_TTGTP_TP_Pos (0U)\r
+#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */\r
+#define FDCAN_TTGTP_CTP_Pos (16U)\r
+#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */\r
+#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */\r
+\r
+/***************** Bit definition for FDCAN_TTTMK register ********************/\r
+#define FDCAN_TTTMK_TM_Pos (0U)\r
+#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */\r
+#define FDCAN_TTTMK_TICC_Pos (16U)\r
+#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */\r
+#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */\r
+#define FDCAN_TTTMK_LCKM_Pos (31U)\r
+#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */\r
+#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */\r
+\r
+/***************** Bit definition for FDCAN_TTIR register ********************/\r
+#define FDCAN_TTIR_SBC_Pos (0U)\r
+#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */\r
+#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */\r
+#define FDCAN_TTIR_SMC_Pos (1U)\r
+#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */\r
+#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */\r
+#define FDCAN_TTIR_CSM_Pos (2U)\r
+#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */\r
+#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */\r
+#define FDCAN_TTIR_SOG_Pos (3U)\r
+#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */\r
+#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */\r
+#define FDCAN_TTIR_RTMI_Pos (4U)\r
+#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */\r
+#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */\r
+#define FDCAN_TTIR_TTMI_Pos (5U)\r
+#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */\r
+#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */\r
+#define FDCAN_TTIR_SWE_Pos (6U)\r
+#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */\r
+#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */\r
+#define FDCAN_TTIR_GTW_Pos (7U)\r
+#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */\r
+#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */\r
+#define FDCAN_TTIR_GTD_Pos (8U)\r
+#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */\r
+#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */\r
+#define FDCAN_TTIR_GTE_Pos (9U)\r
+#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */\r
+#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */\r
+#define FDCAN_TTIR_TXU_Pos (10U)\r
+#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */\r
+#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */\r
+#define FDCAN_TTIR_TXO_Pos (11U)\r
+#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */\r
+#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */\r
+#define FDCAN_TTIR_SE1_Pos (12U)\r
+#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */\r
+#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */\r
+#define FDCAN_TTIR_SE2_Pos (13U)\r
+#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */\r
+#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */\r
+#define FDCAN_TTIR_ELC_Pos (14U)\r
+#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */\r
+#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */\r
+#define FDCAN_TTIR_IWT_Pos (15U)\r
+#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */\r
+#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */\r
+#define FDCAN_TTIR_WT_Pos (16U)\r
+#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */\r
+#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */\r
+#define FDCAN_TTIR_AW_Pos (17U)\r
+#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */\r
+#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */\r
+#define FDCAN_TTIR_CER_Pos (18U)\r
+#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */\r
+#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */\r
+\r
+/***************** Bit definition for FDCAN_TTIE register ********************/\r
+#define FDCAN_TTIE_SBCE_Pos (0U)\r
+#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */\r
+#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */\r
+#define FDCAN_TTIE_SMCE_Pos (1U)\r
+#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */\r
+#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */\r
+#define FDCAN_TTIE_CSME_Pos (2U)\r
+#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */\r
+#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */\r
+#define FDCAN_TTIE_SOGE_Pos (3U)\r
+#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */\r
+#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */\r
+#define FDCAN_TTIE_RTMIE_Pos (4U)\r
+#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */\r
+#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */\r
+#define FDCAN_TTIE_TTMIE_Pos (5U)\r
+#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */\r
+#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */\r
+#define FDCAN_TTIE_SWEE_Pos (6U)\r
+#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */\r
+#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */\r
+#define FDCAN_TTIE_GTWE_Pos (7U)\r
+#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */\r
+#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */\r
+#define FDCAN_TTIE_GTDE_Pos (8U)\r
+#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */\r
+#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */\r
+#define FDCAN_TTIE_GTEE_Pos (9U)\r
+#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */\r
+#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */\r
+#define FDCAN_TTIE_TXUE_Pos (10U)\r
+#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */\r
+#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */\r
+#define FDCAN_TTIE_TXOE_Pos (11U)\r
+#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */\r
+#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */\r
+#define FDCAN_TTIE_SE1E_Pos (12U)\r
+#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */\r
+#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */\r
+#define FDCAN_TTIE_SE2E_Pos (13U)\r
+#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */\r
+#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */\r
+#define FDCAN_TTIE_ELCE_Pos (14U)\r
+#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */\r
+#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */\r
+#define FDCAN_TTIE_IWTE_Pos (15U)\r
+#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */\r
+#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */\r
+#define FDCAN_TTIE_WTE_Pos (16U)\r
+#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */\r
+#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */\r
+#define FDCAN_TTIE_AWE_Pos (17U)\r
+#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */\r
+#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */\r
+#define FDCAN_TTIE_CERE_Pos (18U)\r
+#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */\r
+#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */\r
+\r
+/***************** Bit definition for FDCAN_TTILS register ********************/\r
+#define FDCAN_TTILS_SBCS_Pos (0U)\r
+#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */\r
+#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */\r
+#define FDCAN_TTILS_SMCS_Pos (1U)\r
+#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */\r
+#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */\r
+#define FDCAN_TTILS_CSMS_Pos (2U)\r
+#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */\r
+#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */\r
+#define FDCAN_TTILS_SOGS_Pos (3U)\r
+#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */\r
+#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */\r
+#define FDCAN_TTILS_RTMIS_Pos (4U)\r
+#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */\r
+#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */\r
+#define FDCAN_TTILS_TTMIS_Pos (5U)\r
+#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */\r
+#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */\r
+#define FDCAN_TTILS_SWES_Pos (6U)\r
+#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */\r
+#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */\r
+#define FDCAN_TTILS_GTWS_Pos (7U)\r
+#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */\r
+#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */\r
+#define FDCAN_TTILS_GTDS_Pos (8U)\r
+#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */\r
+#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */\r
+#define FDCAN_TTILS_GTES_Pos (9U)\r
+#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */\r
+#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */\r
+#define FDCAN_TTILS_TXUS_Pos (10U)\r
+#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */\r
+#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */\r
+#define FDCAN_TTILS_TXOS_Pos (11U)\r
+#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */\r
+#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */\r
+#define FDCAN_TTILS_SE1S_Pos (12U)\r
+#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */\r
+#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */\r
+#define FDCAN_TTILS_SE2S_Pos (13U)\r
+#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */\r
+#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */\r
+#define FDCAN_TTILS_ELCS_Pos (14U)\r
+#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */\r
+#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */\r
+#define FDCAN_TTILS_IWTS_Pos (15U)\r
+#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */\r
+#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */\r
+#define FDCAN_TTILS_WTS_Pos (16U)\r
+#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */\r
+#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */\r
+#define FDCAN_TTILS_AWS_Pos (17U)\r
+#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */\r
+#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */\r
+#define FDCAN_TTILS_CERS_Pos (18U)\r
+#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */\r
+#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */\r
+\r
+/***************** Bit definition for FDCAN_TTOST register ********************/\r
+#define FDCAN_TTOST_EL_Pos (0U)\r
+#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */\r
+#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */\r
+#define FDCAN_TTOST_MS_Pos (2U)\r
+#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */\r
+#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */\r
+#define FDCAN_TTOST_SYS_Pos (4U)\r
+#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */\r
+#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */\r
+#define FDCAN_TTOST_QGTP_Pos (6U)\r
+#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */\r
+#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */\r
+#define FDCAN_TTOST_QCS_Pos (7U)\r
+#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */\r
+#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */\r
+#define FDCAN_TTOST_RTO_Pos (8U)\r
+#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */\r
+#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */\r
+#define FDCAN_TTOST_WGTD_Pos (22U)\r
+#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */\r
+#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */\r
+#define FDCAN_TTOST_GFI_Pos (23U)\r
+#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */\r
+#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */\r
+#define FDCAN_TTOST_TMP_Pos (24U)\r
+#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */\r
+#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */\r
+#define FDCAN_TTOST_GSI_Pos (27U)\r
+#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */\r
+#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */\r
+#define FDCAN_TTOST_WFE_Pos (28U)\r
+#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */\r
+#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */\r
+#define FDCAN_TTOST_AWE_Pos (29U)\r
+#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */\r
+#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */\r
+#define FDCAN_TTOST_WECS_Pos (30U)\r
+#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */\r
+#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */\r
+#define FDCAN_TTOST_SPL_Pos (31U)\r
+#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */\r
+#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */\r
+\r
+/***************** Bit definition for FDCAN_TURNA register ********************/\r
+#define FDCAN_TURNA_NAV_Pos (0U)\r
+#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */\r
+#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */\r
+\r
+/***************** Bit definition for FDCAN_TTLGT register ********************/\r
+#define FDCAN_TTLGT_LT_Pos (0U)\r
+#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */\r
+#define FDCAN_TTLGT_GT_Pos (16U)\r
+#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */\r
+#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */\r
+\r
+/***************** Bit definition for FDCAN_TTCTC register ********************/\r
+#define FDCAN_TTCTC_CT_Pos (0U)\r
+#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */\r
+#define FDCAN_TTCTC_CC_Pos (16U)\r
+#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */\r
+#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */\r
+\r
+/***************** Bit definition for FDCAN_TTCPT register ********************/\r
+#define FDCAN_TTCPT_CCV_Pos (0U)\r
+#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */\r
+#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */\r
+#define FDCAN_TTCPT_SWV_Pos (16U)\r
+#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */\r
+#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */\r
+\r
+/***************** Bit definition for FDCAN_TTCSM register ********************/\r
+#define FDCAN_TTCSM_CSM_Pos (0U)\r
+#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */\r
+#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */\r
+\r
+/***************** Bit definition for FDCAN_TTTS register *********************/\r
+#define FDCAN_TTTS_SWTSEL_Pos (0U)\r
+#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */\r
+#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */\r
+#define FDCAN_TTTS_EVTSEL_Pos (4U)\r
+#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */\r
+#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */\r
+\r
+/********************************************************************************/\r
+/* */\r
+/* FDCANCCU (Clock Calibration unit) */\r
+/* */\r
+/********************************************************************************/\r
+\r
+/***************** Bit definition for FDCANCCU_CREL register ******************/\r
+#define FDCANCCU_CREL_DAY_Pos (0U)\r
+#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */\r
+#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */\r
+#define FDCANCCU_CREL_MON_Pos (8U)\r
+#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */\r
+#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */\r
+#define FDCANCCU_CREL_YEAR_Pos (16U)\r
+#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */\r
+#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */\r
+#define FDCANCCU_CREL_SUBSTEP_Pos (20U)\r
+#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */\r
+#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */\r
+#define FDCANCCU_CREL_STEP_Pos (24U)\r
+#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */\r
+#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */\r
+#define FDCANCCU_CREL_REL_Pos (28U)\r
+#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */\r
+#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */\r
+\r
+/***************** Bit definition for FDCANCCU_CCFG register ******************/\r
+#define FDCANCCU_CCFG_TQBT_Pos (0U)\r
+#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */\r
+#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */\r
+#define FDCANCCU_CCFG_BCC_Pos (6U)\r
+#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */\r
+#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */\r
+#define FDCANCCU_CCFG_CFL_Pos (7U)\r
+#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */\r
+#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */\r
+#define FDCANCCU_CCFG_OCPM_Pos (8U)\r
+#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */\r
+#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */\r
+#define FDCANCCU_CCFG_CDIV_Pos (16U)\r
+#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */\r
+#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */\r
+#define FDCANCCU_CCFG_SWR_Pos (31U)\r
+#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */\r
+#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */\r
+\r
+/***************** Bit definition for FDCANCCU_CSTAT register *****************/\r
+#define FDCANCCU_CSTAT_OCPC_Pos (0U)\r
+#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */\r
+#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */\r
+#define FDCANCCU_CSTAT_TQC_Pos (18U)\r
+#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */\r
+#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */\r
+#define FDCANCCU_CSTAT_CALS_Pos (30U)\r
+#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */\r
+#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */\r
+\r
+/****************** Bit definition for FDCANCCU_CWD register ******************/\r
+#define FDCANCCU_CWD_WDC_Pos (0U)\r
+#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */\r
+#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */\r
+#define FDCANCCU_CWD_WDV_Pos (16U)\r
+#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */\r
+#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */\r
+\r
+/****************** Bit definition for FDCANCCU_IR register *******************/\r
+#define FDCANCCU_IR_CWE_Pos (0U)\r
+#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */\r
+#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */\r
+#define FDCANCCU_IR_CSC_Pos (1U)\r
+#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */\r
+#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */\r
+\r
+/****************** Bit definition for FDCANCCU_IE register *******************/\r
+#define FDCANCCU_IE_CWEE_Pos (0U)\r
+#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */\r
+#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */\r
+#define FDCANCCU_IE_CSCE_Pos (1U)\r
+#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */\r
+#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HDMI-CEC (CEC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CEC_CR register *********************/\r
+#define CEC_CR_CECEN_Pos (0U)\r
+#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */\r
+#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */\r
+#define CEC_CR_TXSOM_Pos (1U)\r
+#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */\r
+#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */\r
+#define CEC_CR_TXEOM_Pos (2U)\r
+#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */\r
+#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */\r
+\r
+/******************* Bit definition for CEC_CFGR register *******************/\r
+#define CEC_CFGR_SFT_Pos (0U)\r
+#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */\r
+#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */\r
+#define CEC_CFGR_RXTOL_Pos (3U)\r
+#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */\r
+#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */\r
+#define CEC_CFGR_BRESTP_Pos (4U)\r
+#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */\r
+#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */\r
+#define CEC_CFGR_BREGEN_Pos (5U)\r
+#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */\r
+#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */\r
+#define CEC_CFGR_LBPEGEN_Pos (6U)\r
+#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */\r
+#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */\r
+#define CEC_CFGR_SFTOPT_Pos (8U)\r
+#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */\r
+#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */\r
+#define CEC_CFGR_BRDNOGEN_Pos (7U)\r
+#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */\r
+#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */\r
+#define CEC_CFGR_OAR_Pos (16U)\r
+#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */\r
+#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */\r
+#define CEC_CFGR_LSTN_Pos (31U)\r
+#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */\r
+#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */\r
+\r
+/******************* Bit definition for CEC_TXDR register *******************/\r
+#define CEC_TXDR_TXD_Pos (0U)\r
+#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */\r
+#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */\r
+\r
+/******************* Bit definition for CEC_RXDR register *******************/\r
+#define CEC_RXDR_RXD_Pos (0U)\r
+#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */\r
+#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */\r
+\r
+/******************* Bit definition for CEC_ISR register ********************/\r
+#define CEC_ISR_RXBR_Pos (0U)\r
+#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */\r
+#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */\r
+#define CEC_ISR_RXEND_Pos (1U)\r
+#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */\r
+#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */\r
+#define CEC_ISR_RXOVR_Pos (2U)\r
+#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */\r
+#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */\r
+#define CEC_ISR_BRE_Pos (3U)\r
+#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */\r
+#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */\r
+#define CEC_ISR_SBPE_Pos (4U)\r
+#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */\r
+#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */\r
+#define CEC_ISR_LBPE_Pos (5U)\r
+#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */\r
+#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */\r
+#define CEC_ISR_RXACKE_Pos (6U)\r
+#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */\r
+#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */\r
+#define CEC_ISR_ARBLST_Pos (7U)\r
+#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */\r
+#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */\r
+#define CEC_ISR_TXBR_Pos (8U)\r
+#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */\r
+#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */\r
+#define CEC_ISR_TXEND_Pos (9U)\r
+#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */\r
+#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */\r
+#define CEC_ISR_TXUDR_Pos (10U)\r
+#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */\r
+#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */\r
+#define CEC_ISR_TXERR_Pos (11U)\r
+#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */\r
+#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */\r
+#define CEC_ISR_TXACKE_Pos (12U)\r
+#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */\r
+#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */\r
+\r
+/******************* Bit definition for CEC_IER register ********************/\r
+#define CEC_IER_RXBRIE_Pos (0U)\r
+#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */\r
+#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */\r
+#define CEC_IER_RXENDIE_Pos (1U)\r
+#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */\r
+#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */\r
+#define CEC_IER_RXOVRIE_Pos (2U)\r
+#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */\r
+#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */\r
+#define CEC_IER_BREIE_Pos (3U)\r
+#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */\r
+#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */\r
+#define CEC_IER_SBPEIE_Pos (4U)\r
+#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */\r
+#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */\r
+#define CEC_IER_LBPEIE_Pos (5U)\r
+#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */\r
+#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */\r
+#define CEC_IER_RXACKEIE_Pos (6U)\r
+#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */\r
+#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */\r
+#define CEC_IER_ARBLSTIE_Pos (7U)\r
+#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */\r
+#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */\r
+#define CEC_IER_TXBRIE_Pos (8U)\r
+#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */\r
+#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */\r
+#define CEC_IER_TXENDIE_Pos (9U)\r
+#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */\r
+#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */\r
+#define CEC_IER_TXUDRIE_Pos (10U)\r
+#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */\r
+#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */\r
+#define CEC_IER_TXERRIE_Pos (11U)\r
+#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */\r
+#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */\r
+#define CEC_IER_TXACKEIE_Pos (12U)\r
+#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */\r
+#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR_Pos (0U)\r
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR_Pos (0U)\r
+#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET_Pos (0U)\r
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\r
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_POLYSIZE_Pos (3U)\r
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */\r
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */\r
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */\r
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */\r
+#define CRC_CR_REV_IN_Pos (5U)\r
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */\r
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */\r
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */\r
+#define CRC_CR_REV_OUT_Pos (7U)\r
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */\r
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/******************* Bit definition for CRC_INIT register *******************/\r
+#define CRC_INIT_INIT_Pos (0U)\r
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */\r
+\r
+/******************* Bit definition for CRC_POL register ********************/\r
+#define CRC_POL_POL_Pos (0U)\r
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRS Clock Recovery System */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CRS_CR register *********************/\r
+#define CRS_CR_SYNCOKIE_Pos (0U)\r
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */\r
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */\r
+#define CRS_CR_SYNCWARNIE_Pos (1U)\r
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */\r
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */\r
+#define CRS_CR_ERRIE_Pos (2U)\r
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */\r
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */\r
+#define CRS_CR_ESYNCIE_Pos (3U)\r
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */\r
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */\r
+#define CRS_CR_CEN_Pos (5U)\r
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */\r
+#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */\r
+#define CRS_CR_AUTOTRIMEN_Pos (6U)\r
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */\r
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */\r
+#define CRS_CR_SWSYNC_Pos (7U)\r
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */\r
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */\r
+#define CRS_CR_TRIM_Pos (8U)\r
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */\r
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */\r
+\r
+/******************* Bit definition for CRS_CFGR register *********************/\r
+#define CRS_CFGR_RELOAD_Pos (0U)\r
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */\r
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */\r
+#define CRS_CFGR_FELIM_Pos (16U)\r
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */\r
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */\r
+\r
+#define CRS_CFGR_SYNCDIV_Pos (24U)\r
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */\r
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */\r
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */\r
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */\r
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */\r
+\r
+#define CRS_CFGR_SYNCSRC_Pos (28U)\r
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */\r
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */\r
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */\r
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */\r
+\r
+#define CRS_CFGR_SYNCPOL_Pos (31U)\r
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */\r
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */\r
+\r
+/******************* Bit definition for CRS_ISR register *********************/\r
+#define CRS_ISR_SYNCOKF_Pos (0U)\r
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */\r
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */\r
+#define CRS_ISR_SYNCWARNF_Pos (1U)\r
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */\r
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */\r
+#define CRS_ISR_ERRF_Pos (2U)\r
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */\r
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */\r
+#define CRS_ISR_ESYNCF_Pos (3U)\r
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */\r
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */\r
+#define CRS_ISR_SYNCERR_Pos (8U)\r
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */\r
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */\r
+#define CRS_ISR_SYNCMISS_Pos (9U)\r
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */\r
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */\r
+#define CRS_ISR_TRIMOVF_Pos (10U)\r
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */\r
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */\r
+#define CRS_ISR_FEDIR_Pos (15U)\r
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */\r
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */\r
+#define CRS_ISR_FECAP_Pos (16U)\r
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */\r
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */\r
+\r
+/******************* Bit definition for CRS_ICR register *********************/\r
+#define CRS_ICR_SYNCOKC_Pos (0U)\r
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */\r
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */\r
+#define CRS_ICR_SYNCWARNC_Pos (1U)\r
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */\r
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */\r
+#define CRS_ICR_ERRC_Pos (2U)\r
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */\r
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */\r
+#define CRS_ICR_ESYNCC_Pos (3U)\r
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */\r
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1_Pos (0U)\r
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\r
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */\r
+#define DAC_CR_TEN1_Pos (1U)\r
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */\r
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1_Pos (2U)\r
+#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */\r
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */\r
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */\r
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */\r
+#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */\r
+\r
+\r
+#define DAC_CR_WAVE1_Pos (6U)\r
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */\r
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */\r
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */\r
+\r
+#define DAC_CR_MAMP1_Pos (8U)\r
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */\r
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */\r
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */\r
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */\r
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */\r
+\r
+#define DAC_CR_DMAEN1_Pos (12U)\r
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */\r
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1_Pos (13U)\r
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */\r
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/\r
+#define DAC_CR_CEN1_Pos (14U)\r
+#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */\r
+#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/\r
+\r
+#define DAC_CR_EN2_Pos (16U)\r
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\r
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */\r
+#define DAC_CR_TEN2_Pos (17U)\r
+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */\r
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2_Pos (18U)\r
+#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */\r
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */\r
+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */\r
+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */\r
+#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */\r
+\r
+\r
+#define DAC_CR_WAVE2_Pos (22U)\r
+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */\r
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */\r
+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */\r
+\r
+#define DAC_CR_MAMP2_Pos (24U)\r
+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */\r
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */\r
+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */\r
+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */\r
+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */\r
+\r
+#define DAC_CR_DMAEN2_Pos (28U)\r
+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */\r
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */\r
+#define DAC_CR_DMAUDRIE2_Pos (29U)\r
+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */\r
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/\r
+#define DAC_CR_CEN2_Pos (30U)\r
+#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */\r
+#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)\r
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\r
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)\r
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */\r
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)\r
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)\r
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)\r
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)\r
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)\r
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)\r
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)\r
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)\r
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */\r
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)\r
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)\r
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */\r
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)\r
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)\r
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */\r
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR_Pos (0U)\r
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR_Pos (0U)\r
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1_Pos (13U)\r
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */\r
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_CAL_FLAG1_Pos (14U)\r
+#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */\r
+#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */\r
+#define DAC_SR_BWST1_Pos (15U)\r
+#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */\r
+#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */\r
+\r
+#define DAC_SR_DMAUDR2_Pos (29U)\r
+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */\r
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */\r
+#define DAC_SR_CAL_FLAG2_Pos (30U)\r
+#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */\r
+#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */\r
+#define DAC_SR_BWST2_Pos (31U)\r
+#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */\r
+#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */\r
+\r
+/******************* Bit definition for DAC_CCR register ********************/\r
+#define DAC_CCR_OTRIM1_Pos (0U)\r
+#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */\r
+#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */\r
+#define DAC_CCR_OTRIM2_Pos (16U)\r
+#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */\r
+#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */\r
+\r
+/******************* Bit definition for DAC_MCR register *******************/\r
+#define DAC_MCR_MODE1_Pos (0U)\r
+#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */\r
+#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */\r
+#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */\r
+#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */\r
+#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */\r
+\r
+#define DAC_MCR_MODE2_Pos (16U)\r
+#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */\r
+#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */\r
+#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */\r
+#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */\r
+#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */\r
+\r
+/****************** Bit definition for DAC_SHSR1 register ******************/\r
+#define DAC_SHSR1_TSAMPLE1_Pos (0U)\r
+#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */\r
+#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */\r
+\r
+/****************** Bit definition for DAC_SHSR2 register ******************/\r
+#define DAC_SHSR2_TSAMPLE2_Pos (0U)\r
+#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */\r
+#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */\r
+\r
+/****************** Bit definition for DAC_SHHR register ******************/\r
+#define DAC_SHHR_THOLD1_Pos (0U)\r
+#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */\r
+#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */\r
+#define DAC_SHHR_THOLD2_Pos (16U)\r
+#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */\r
+#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */\r
+\r
+/****************** Bit definition for DAC_SHRR register ******************/\r
+#define DAC_SHRR_TREFRESH1_Pos (0U)\r
+#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */\r
+#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */\r
+#define DAC_SHRR_TREFRESH2_Pos (16U)\r
+#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */\r
+#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DCMI */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DCMI_CR register ******************/\r
+#define DCMI_CR_CAPTURE_Pos (0U)\r
+#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */\r
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk\r
+#define DCMI_CR_CM_Pos (1U)\r
+#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */\r
+#define DCMI_CR_CM DCMI_CR_CM_Msk\r
+#define DCMI_CR_CROP_Pos (2U)\r
+#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */\r
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk\r
+#define DCMI_CR_JPEG_Pos (3U)\r
+#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */\r
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk\r
+#define DCMI_CR_ESS_Pos (4U)\r
+#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */\r
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk\r
+#define DCMI_CR_PCKPOL_Pos (5U)\r
+#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */\r
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk\r
+#define DCMI_CR_HSPOL_Pos (6U)\r
+#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */\r
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk\r
+#define DCMI_CR_VSPOL_Pos (7U)\r
+#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */\r
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk\r
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)\r
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)\r
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)\r
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)\r
+#define DCMI_CR_CRE_Pos (12U)\r
+#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */\r
+#define DCMI_CR_CRE DCMI_CR_CRE_Msk\r
+#define DCMI_CR_ENABLE_Pos (14U)\r
+#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */\r
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk\r
+#define DCMI_CR_BSM_Pos (16U)\r
+#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */\r
+#define DCMI_CR_BSM DCMI_CR_BSM_Msk\r
+#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */\r
+#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */\r
+#define DCMI_CR_OEBS_Pos (18U)\r
+#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */\r
+#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk\r
+#define DCMI_CR_LSM_Pos (19U)\r
+#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */\r
+#define DCMI_CR_LSM DCMI_CR_LSM_Msk\r
+#define DCMI_CR_OELS_Pos (20U)\r
+#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */\r
+#define DCMI_CR_OELS DCMI_CR_OELS_Msk\r
+\r
+/******************** Bits definition for DCMI_SR register ******************/\r
+#define DCMI_SR_HSYNC_Pos (0U)\r
+#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */\r
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk\r
+#define DCMI_SR_VSYNC_Pos (1U)\r
+#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */\r
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk\r
+#define DCMI_SR_FNE_Pos (2U)\r
+#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */\r
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk\r
+\r
+/******************** Bits definition for DCMI_RIS register ****************/\r
+#define DCMI_RIS_FRAME_RIS_Pos (0U)\r
+#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */\r
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk\r
+#define DCMI_RIS_OVR_RIS_Pos (1U)\r
+#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */\r
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk\r
+#define DCMI_RIS_ERR_RIS_Pos (2U)\r
+#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */\r
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk\r
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)\r
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */\r
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk\r
+#define DCMI_RIS_LINE_RIS_Pos (4U)\r
+#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */\r
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk\r
+\r
+/******************** Bits definition for DCMI_IER register *****************/\r
+#define DCMI_IER_FRAME_IE_Pos (0U)\r
+#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */\r
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk\r
+#define DCMI_IER_OVR_IE_Pos (1U)\r
+#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */\r
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk\r
+#define DCMI_IER_ERR_IE_Pos (2U)\r
+#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */\r
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk\r
+#define DCMI_IER_VSYNC_IE_Pos (3U)\r
+#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */\r
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk\r
+#define DCMI_IER_LINE_IE_Pos (4U)\r
+#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */\r
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk\r
+\r
+\r
+/******************** Bits definition for DCMI_MIS register *****************/\r
+#define DCMI_MIS_FRAME_MIS_Pos (0U)\r
+#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */\r
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk\r
+#define DCMI_MIS_OVR_MIS_Pos (1U)\r
+#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */\r
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk\r
+#define DCMI_MIS_ERR_MIS_Pos (2U)\r
+#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */\r
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk\r
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)\r
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */\r
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk\r
+#define DCMI_MIS_LINE_MIS_Pos (4U)\r
+#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */\r
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk\r
+\r
+\r
+/******************** Bits definition for DCMI_ICR register *****************/\r
+#define DCMI_ICR_FRAME_ISC_Pos (0U)\r
+#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */\r
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk\r
+#define DCMI_ICR_OVR_ISC_Pos (1U)\r
+#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */\r
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk\r
+#define DCMI_ICR_ERR_ISC_Pos (2U)\r
+#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */\r
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk\r
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)\r
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */\r
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk\r
+#define DCMI_ICR_LINE_ISC_Pos (4U)\r
+#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */\r
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk\r
+\r
+\r
+/******************** Bits definition for DCMI_ESCR register ******************/\r
+#define DCMI_ESCR_FSC_Pos (0U)\r
+#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */\r
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk\r
+#define DCMI_ESCR_LSC_Pos (8U)\r
+#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */\r
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk\r
+#define DCMI_ESCR_LEC_Pos (16U)\r
+#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */\r
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk\r
+#define DCMI_ESCR_FEC_Pos (24U)\r
+#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */\r
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk\r
+\r
+/******************** Bits definition for DCMI_ESUR register ******************/\r
+#define DCMI_ESUR_FSU_Pos (0U)\r
+#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */\r
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk\r
+#define DCMI_ESUR_LSU_Pos (8U)\r
+#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */\r
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk\r
+#define DCMI_ESUR_LEU_Pos (16U)\r
+#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */\r
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk\r
+#define DCMI_ESUR_FEU_Pos (24U)\r
+#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */\r
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk\r
+\r
+/******************** Bits definition for DCMI_CWSTRT register ******************/\r
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)\r
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */\r
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk\r
+#define DCMI_CWSTRT_VST_Pos (16U)\r
+#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */\r
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk\r
+\r
+/******************** Bits definition for DCMI_CWSIZE register ******************/\r
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)\r
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */\r
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk\r
+#define DCMI_CWSIZE_VLINE_Pos (16U)\r
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */\r
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk\r
+\r
+/******************** Bits definition for DCMI_DR register ******************/\r
+#define DCMI_DR_BYTE0_Pos (0U)\r
+#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */\r
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk\r
+#define DCMI_DR_BYTE1_Pos (8U)\r
+#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */\r
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk\r
+#define DCMI_DR_BYTE2_Pos (16U)\r
+#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */\r
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk\r
+#define DCMI_DR_BYTE3_Pos (24U)\r
+#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */\r
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital Filter for Sigma Delta Modulators */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** DFSDM channel configuration registers ********************/\r
+\r
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/\r
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)\r
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */\r
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */\r
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)\r
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */\r
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */\r
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)\r
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */\r
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U)\r
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */\r
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */\r
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */\r
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */\r
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U)\r
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */\r
+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */\r
+#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */\r
+#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */\r
+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)\r
+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */\r
+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */\r
+#define DFSDM_CHCFGR1_CHEN_Pos (7U)\r
+#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */\r
+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */\r
+#define DFSDM_CHCFGR1_CKABEN_Pos (6U)\r
+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */\r
+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SCDEN_Pos (5U)\r
+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */\r
+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)\r
+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */\r
+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */\r
+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */\r
+#define DFSDM_CHCFGR1_SITP_Pos (0U)\r
+#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */\r
+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */\r
+#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */\r
+#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */\r
+\r
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/\r
+#define DFSDM_CHCFGR2_OFFSET_Pos (8U)\r
+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\r
+#define DFSDM_CHCFGR2_DTRBS_Pos (3U)\r
+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */\r
+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */\r
+\r
+/****************** Bit definition for DFSDM_CHAWSCDR register *****************/\r
+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)\r
+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */\r
+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\r
+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */\r
+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */\r
+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)\r
+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */\r
+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\r
+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)\r
+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */\r
+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\r
+#define DFSDM_CHAWSCDR_SCDT_Pos (0U)\r
+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */\r
+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */\r
+\r
+/**************** Bit definition for DFSDM_CHWDATR register *******************/\r
+#define DFSDM_CHWDATR_WDATA_Pos (0U)\r
+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */\r
+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */\r
+\r
+/**************** Bit definition for DFSDM_CHDATINR register *****************/\r
+#define DFSDM_CHDATINR_INDAT0_Pos (0U)\r
+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\r
+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\r
+#define DFSDM_CHDATINR_INDAT1_Pos (16U)\r
+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\r
+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */\r
+\r
+/************************ DFSDM module registers ****************************/\r
+\r
+/******************** Bit definition for DFSDM_FLTCR1 register *******************/\r
+#define DFSDM_FLTCR1_AWFSEL_Pos (30U)\r
+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */\r
+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */\r
+#define DFSDM_FLTCR1_FAST_Pos (29U)\r
+#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */\r
+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */\r
+#define DFSDM_FLTCR1_RCH_Pos (24U)\r
+#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */\r
+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */\r
+#define DFSDM_FLTCR1_RDMAEN_Pos (21U)\r
+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */\r
+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */\r
+#define DFSDM_FLTCR1_RSYNC_Pos (19U)\r
+#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */\r
+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */\r
+#define DFSDM_FLTCR1_RCONT_Pos (18U)\r
+#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */\r
+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */\r
+#define DFSDM_FLTCR1_RSWSTART_Pos (17U)\r
+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */\r
+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */\r
+#define DFSDM_FLTCR1_JEXTEN_Pos (13U)\r
+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */\r
+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\r
+#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */\r
+#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */\r
+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)\r
+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */\r
+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */\r
+#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */\r
+#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */\r
+#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */\r
+#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */\r
+#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */\r
+\r
+#define DFSDM_FLTCR1_JDMAEN_Pos (5U)\r
+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */\r
+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */\r
+#define DFSDM_FLTCR1_JSCAN_Pos (4U)\r
+#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */\r
+#define DFSDM_FLTCR1_JSYNC_Pos (3U)\r
+#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */\r
+#define DFSDM_FLTCR1_JSWSTART_Pos (1U)\r
+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */\r
+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */\r
+#define DFSDM_FLTCR1_DFEN_Pos (0U)\r
+#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */\r
+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */\r
+\r
+/******************** Bit definition for DFSDM_FLTCR2 register *******************/\r
+#define DFSDM_FLTCR2_AWDCH_Pos (16U)\r
+#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */\r
+#define DFSDM_FLTCR2_EXCH_Pos (8U)\r
+#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */\r
+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */\r
+#define DFSDM_FLTCR2_CKABIE_Pos (6U)\r
+#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */\r
+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */\r
+#define DFSDM_FLTCR2_SCDIE_Pos (5U)\r
+#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */\r
+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */\r
+#define DFSDM_FLTCR2_AWDIE_Pos (4U)\r
+#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */\r
+#define DFSDM_FLTCR2_ROVRIE_Pos (3U)\r
+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_JOVRIE_Pos (2U)\r
+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */\r
+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_REOCIE_Pos (1U)\r
+#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */\r
+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */\r
+#define DFSDM_FLTCR2_JEOCIE_Pos (0U)\r
+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */\r
+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */\r
+\r
+/******************** Bit definition for DFSDM_FLTISR register *******************/\r
+#define DFSDM_FLTISR_SCDF_Pos (24U)\r
+#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */\r
+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */\r
+#define DFSDM_FLTISR_CKABF_Pos (16U)\r
+#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */\r
+#define DFSDM_FLTISR_RCIP_Pos (14U)\r
+#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */\r
+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */\r
+#define DFSDM_FLTISR_JCIP_Pos (13U)\r
+#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */\r
+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */\r
+#define DFSDM_FLTISR_AWDF_Pos (4U)\r
+#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */\r
+#define DFSDM_FLTISR_ROVRF_Pos (3U)\r
+#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */\r
+#define DFSDM_FLTISR_JOVRF_Pos (2U)\r
+#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */\r
+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */\r
+#define DFSDM_FLTISR_REOCF_Pos (1U)\r
+#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */\r
+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */\r
+#define DFSDM_FLTISR_JEOCF_Pos (0U)\r
+#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */\r
+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */\r
+\r
+/******************** Bit definition for DFSDM_FLTICR register *******************/\r
+#define DFSDM_FLTICR_CLRSCDF_Pos (24U)\r
+#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */\r
+#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\r
+#define DFSDM_FLTICR_CLRCKABF_Pos (16U)\r
+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */\r
+#define DFSDM_FLTICR_CLRROVRF_Pos (3U)\r
+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */\r
+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)\r
+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */\r
+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */\r
+\r
+/******************* Bit definition for DFSDM_FLTJCHGR register ******************/\r
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U)\r
+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */\r
+\r
+/******************** Bit definition for DFSDM_FLTFCR register *******************/\r
+#define DFSDM_FLTFCR_FORD_Pos (29U)\r
+#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */\r
+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */\r
+#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */\r
+#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */\r
+#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */\r
+#define DFSDM_FLTFCR_FOSR_Pos (16U)\r
+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */\r
+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\r
+#define DFSDM_FLTFCR_IOSR_Pos (0U)\r
+#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\r
+\r
+/****************** Bit definition for DFSDM_FLTJDATAR register *****************/\r
+#define DFSDM_FLTJDATAR_JDATA_Pos (8U)\r
+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */\r
+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)\r
+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */\r
+\r
+/****************** Bit definition for DFSDM_FLTRDATAR register *****************/\r
+#define DFSDM_FLTRDATAR_RDATA_Pos (8U)\r
+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */\r
+#define DFSDM_FLTRDATAR_RPEND_Pos (4U)\r
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */\r
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)\r
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWHTR register ******************/\r
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U)\r
+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */\r
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)\r
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */\r
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWLTR register ******************/\r
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U)\r
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */\r
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)\r
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */\r
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWSR register ******************/\r
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U)\r
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */\r
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\r
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U)\r
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/\r
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)\r
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\r
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\r
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)\r
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\r
+\r
+/****************** Bit definition for DFSDM_FLTEXMAX register ******************/\r
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)\r
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */\r
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)\r
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\r
+\r
+/****************** Bit definition for DFSDM_FLTEXMIN register ******************/\r
+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)\r
+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */\r
+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)\r
+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */\r
+\r
+/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/\r
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)\r
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\r
+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* BDMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for BDMA_ISR register ********************/\r
+#define BDMA_ISR_GIF0_Pos (0U)\r
+#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */\r
+#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */\r
+#define BDMA_ISR_TCIF0_Pos (1U)\r
+#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */\r
+#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF0_Pos (2U)\r
+#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */\r
+#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */\r
+#define BDMA_ISR_TEIF0_Pos (3U)\r
+#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */\r
+#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */\r
+#define BDMA_ISR_GIF1_Pos (4U)\r
+#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */\r
+#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */\r
+#define BDMA_ISR_TCIF1_Pos (5U)\r
+#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */\r
+#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF1_Pos (6U)\r
+#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */\r
+#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */\r
+#define BDMA_ISR_TEIF1_Pos (7U)\r
+#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */\r
+#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */\r
+#define BDMA_ISR_GIF2_Pos (8U)\r
+#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */\r
+#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */\r
+#define BDMA_ISR_TCIF2_Pos (9U)\r
+#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */\r
+#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF2_Pos (10U)\r
+#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */\r
+#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */\r
+#define BDMA_ISR_TEIF2_Pos (11U)\r
+#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */\r
+#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */\r
+#define BDMA_ISR_GIF3_Pos (12U)\r
+#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */\r
+#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */\r
+#define BDMA_ISR_TCIF3_Pos (13U)\r
+#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */\r
+#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF3_Pos (14U)\r
+#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */\r
+#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */\r
+#define BDMA_ISR_TEIF3_Pos (15U)\r
+#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */\r
+#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */\r
+#define BDMA_ISR_GIF4_Pos (16U)\r
+#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */\r
+#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */\r
+#define BDMA_ISR_TCIF4_Pos (17U)\r
+#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */\r
+#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF4_Pos (18U)\r
+#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */\r
+#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */\r
+#define BDMA_ISR_TEIF4_Pos (19U)\r
+#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */\r
+#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */\r
+#define BDMA_ISR_GIF5_Pos (20U)\r
+#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */\r
+#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */\r
+#define BDMA_ISR_TCIF5_Pos (21U)\r
+#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */\r
+#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF5_Pos (22U)\r
+#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */\r
+#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */\r
+#define BDMA_ISR_TEIF5_Pos (23U)\r
+#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */\r
+#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */\r
+#define BDMA_ISR_GIF6_Pos (24U)\r
+#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */\r
+#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */\r
+#define BDMA_ISR_TCIF6_Pos (25U)\r
+#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */\r
+#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF6_Pos (26U)\r
+#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */\r
+#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */\r
+#define BDMA_ISR_TEIF6_Pos (27U)\r
+#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */\r
+#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */\r
+#define BDMA_ISR_GIF7_Pos (28U)\r
+#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */\r
+#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */\r
+#define BDMA_ISR_TCIF7_Pos (29U)\r
+#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */\r
+#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */\r
+#define BDMA_ISR_HTIF7_Pos (30U)\r
+#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */\r
+#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */\r
+#define BDMA_ISR_TEIF7_Pos (31U)\r
+#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */\r
+#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */\r
+\r
+/******************* Bit definition for BDMA_IFCR register *******************/\r
+#define BDMA_IFCR_CGIF0_Pos (0U)\r
+#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */\r
+#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */\r
+#define BDMA_IFCR_CTCIF0_Pos (1U)\r
+#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */\r
+#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF0_Pos (2U)\r
+#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */\r
+#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF0_Pos (3U)\r
+#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */\r
+#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */\r
+#define BDMA_IFCR_CGIF1_Pos (4U)\r
+#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */\r
+#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */\r
+#define BDMA_IFCR_CTCIF1_Pos (5U)\r
+#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */\r
+#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF1_Pos (6U)\r
+#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */\r
+#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF1_Pos (7U)\r
+#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */\r
+#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */\r
+#define BDMA_IFCR_CGIF2_Pos (8U)\r
+#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */\r
+#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */\r
+#define BDMA_IFCR_CTCIF2_Pos (9U)\r
+#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */\r
+#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF2_Pos (10U)\r
+#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */\r
+#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF2_Pos (11U)\r
+#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */\r
+#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */\r
+#define BDMA_IFCR_CGIF3_Pos (12U)\r
+#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */\r
+#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */\r
+#define BDMA_IFCR_CTCIF3_Pos (13U)\r
+#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */\r
+#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF3_Pos (14U)\r
+#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */\r
+#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF3_Pos (15U)\r
+#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */\r
+#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */\r
+#define BDMA_IFCR_CGIF4_Pos (16U)\r
+#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */\r
+#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */\r
+#define BDMA_IFCR_CTCIF4_Pos (17U)\r
+#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */\r
+#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF4_Pos (18U)\r
+#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */\r
+#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF4_Pos (19U)\r
+#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */\r
+#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */\r
+#define BDMA_IFCR_CGIF5_Pos (20U)\r
+#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */\r
+#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */\r
+#define BDMA_IFCR_CTCIF5_Pos (21U)\r
+#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */\r
+#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF5_Pos (22U)\r
+#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */\r
+#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF5_Pos (23U)\r
+#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */\r
+#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */\r
+#define BDMA_IFCR_CGIF6_Pos (24U)\r
+#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */\r
+#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */\r
+#define BDMA_IFCR_CTCIF6_Pos (25U)\r
+#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */\r
+#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF6_Pos (26U)\r
+#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */\r
+#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF6_Pos (27U)\r
+#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */\r
+#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */\r
+#define BDMA_IFCR_CGIF7_Pos (28U)\r
+#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */\r
+#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */\r
+#define BDMA_IFCR_CTCIF7_Pos (29U)\r
+#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */\r
+#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */\r
+#define BDMA_IFCR_CHTIF7_Pos (30U)\r
+#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */\r
+#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */\r
+#define BDMA_IFCR_CTEIF7_Pos (31U)\r
+#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */\r
+#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */\r
+\r
+/******************* Bit definition for BDMA_CCR register ********************/\r
+#define BDMA_CCR_EN_Pos (0U)\r
+#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */\r
+#define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */\r
+#define BDMA_CCR_TCIE_Pos (1U)\r
+#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */\r
+#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */\r
+#define BDMA_CCR_HTIE_Pos (2U)\r
+#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */\r
+#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */\r
+#define BDMA_CCR_TEIE_Pos (3U)\r
+#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */\r
+#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */\r
+#define BDMA_CCR_DIR_Pos (4U)\r
+#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */\r
+#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */\r
+#define BDMA_CCR_CIRC_Pos (5U)\r
+#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */\r
+#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */\r
+#define BDMA_CCR_PINC_Pos (6U)\r
+#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */\r
+#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */\r
+#define BDMA_CCR_MINC_Pos (7U)\r
+#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */\r
+#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */\r
+\r
+#define BDMA_CCR_PSIZE_Pos (8U)\r
+#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */\r
+#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */\r
+#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */\r
+\r
+#define BDMA_CCR_MSIZE_Pos (10U)\r
+#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */\r
+#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */\r
+#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */\r
+#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */\r
+\r
+#define BDMA_CCR_PL_Pos (12U)\r
+#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */\r
+#define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/\r
+#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */\r
+#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */\r
+\r
+#define BDMA_CCR_MEM2MEM_Pos (14U)\r
+#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */\r
+#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */\r
+#define BDMA_CCR_DBM_Pos (15U)\r
+#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */\r
+#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */\r
+#define BDMA_CCR_CT_Pos (16U)\r
+#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */\r
+#define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */\r
+\r
+/****************** Bit definition for BDMA_CNDTR register *******************/\r
+#define BDMA_CNDTR_NDT_Pos (0U)\r
+#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */\r
+#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for BDMA_CPAR register ********************/\r
+#define BDMA_CPAR_PA_Pos (0U)\r
+#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for BDMA_CM0AR register ********************/\r
+#define BDMA_CM0AR_MA_Pos (0U)\r
+#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for BDMA_CM1AR register ********************/\r
+#define BDMA_CM1AR_MA_Pos (0U)\r
+#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Ethernet MAC Registers bits definitions */\r
+/* */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Configuration Register register */\r
+#define ETH_MACCR_ARP_Pos (31U)\r
+#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */\r
+#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */\r
+#define ETH_MACCR_SARC_Pos (28U)\r
+#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */\r
+#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */\r
+#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */\r
+#define ETH_MACCR_SARC_INSADDR0_Pos (29U)\r
+#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */\r
+#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */\r
+#define ETH_MACCR_SARC_INSADDR1_Pos (29U)\r
+#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */\r
+#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */\r
+#define ETH_MACCR_SARC_REPADDR0_Pos (28U)\r
+#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */\r
+#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */\r
+#define ETH_MACCR_SARC_REPADDR1_Pos (28U)\r
+#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */\r
+#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */\r
+#define ETH_MACCR_IPC_Pos (27U)\r
+#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */\r
+#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */\r
+#define ETH_MACCR_IPG_Pos (24U)\r
+#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */\r
+#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */\r
+#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */\r
+#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */\r
+#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */\r
+#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */\r
+#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */\r
+#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */\r
+#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */\r
+#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */\r
+#define ETH_MACCR_GPSLCE_Pos (23U)\r
+#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */\r
+#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */\r
+#define ETH_MACCR_S2KP_Pos (22U)\r
+#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */\r
+#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */\r
+#define ETH_MACCR_CST_Pos (21U)\r
+#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */\r
+#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */\r
+#define ETH_MACCR_ACS_Pos (20U)\r
+#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */\r
+#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */\r
+#define ETH_MACCR_WD_Pos (19U)\r
+#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */\r
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */\r
+#define ETH_MACCR_JD_Pos (17U)\r
+#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */\r
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */\r
+#define ETH_MACCR_JE_Pos (16U)\r
+#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */\r
+#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */\r
+#define ETH_MACCR_FES_Pos (14U)\r
+#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\r
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */\r
+#define ETH_MACCR_DM_Pos (13U)\r
+#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */\r
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */\r
+#define ETH_MACCR_LM_Pos (12U)\r
+#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\r
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */\r
+#define ETH_MACCR_ECRSFD_Pos (11U)\r
+#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */\r
+#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */\r
+#define ETH_MACCR_DO_Pos (10U)\r
+#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */\r
+#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */\r
+#define ETH_MACCR_DCRS_Pos (9U)\r
+#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */\r
+#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */\r
+#define ETH_MACCR_DR_Pos (8U)\r
+#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */\r
+#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */\r
+#define ETH_MACCR_BL_Pos (5U)\r
+#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */\r
+#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */\r
+#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */\r
+#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */\r
+#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r
+#define ETH_MACCR_DC_Pos (4U)\r
+#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\r
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */\r
+#define ETH_MACCR_PRELEN_Pos (2U)\r
+#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */\r
+#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */\r
+#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */\r
+#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */\r
+#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */\r
+#define ETH_MACCR_TE_Pos (1U)\r
+#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */\r
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */\r
+#define ETH_MACCR_RE_Pos (0U)\r
+#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */\r
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Extended Configuration Register register */\r
+#define ETH_MACECR_EIPG_Pos (25U)\r
+#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */\r
+#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */\r
+#define ETH_MACECR_EIPGEN_Pos (24U)\r
+#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */\r
+#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */\r
+#define ETH_MACECR_USP_Pos (18U)\r
+#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */\r
+#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */\r
+#define ETH_MACECR_SPEN_Pos (17U)\r
+#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */\r
+#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */\r
+#define ETH_MACECR_DCRCC_Pos (16U)\r
+#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */\r
+#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */\r
+#define ETH_MACECR_GPSL_Pos (0U)\r
+#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */\r
+#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */\r
+\r
+/* Bit definition for Ethernet MAC Packet Filter Register */\r
+#define ETH_MACPFR_RA_Pos (31U)\r
+#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */\r
+#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */\r
+#define ETH_MACPFR_DNTU_Pos (21U)\r
+#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */\r
+#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */\r
+#define ETH_MACPFR_IPFE_Pos (20U)\r
+#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */\r
+#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */\r
+#define ETH_MACPFR_VTFE_Pos (16U)\r
+#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */\r
+#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */\r
+#define ETH_MACPFR_HPF_Pos (10U)\r
+#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */\r
+#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */\r
+#define ETH_MACPFR_SAF_Pos (9U)\r
+#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */\r
+#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */\r
+#define ETH_MACPFR_SAIF_Pos (8U)\r
+#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */\r
+#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */\r
+#define ETH_MACPFR_PCF_Pos (6U)\r
+#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */\r
+#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */\r
+#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */\r
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)\r
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */\r
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */\r
+#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)\r
+#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */\r
+#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)\r
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */\r
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */\r
+#define ETH_MACPFR_DBF_Pos (5U)\r
+#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */\r
+#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */\r
+#define ETH_MACPFR_PM_Pos (4U)\r
+#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */\r
+#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */\r
+#define ETH_MACPFR_DAIF_Pos (3U)\r
+#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */\r
+#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */\r
+#define ETH_MACPFR_HMC_Pos (2U)\r
+#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */\r
+#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */\r
+#define ETH_MACPFR_HUC_Pos (1U)\r
+#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */\r
+#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */\r
+#define ETH_MACPFR_PR_Pos (0U)\r
+#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */\r
+#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Watchdog Timeout Register */\r
+#define ETH_MACWTR_PWE_Pos (8U)\r
+#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */\r
+#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */\r
+#define ETH_MACWTR_WTO_Pos (0U)\r
+#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */\r
+#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */\r
+#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/\r
+#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */\r
+#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */\r
+#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */\r
+#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */\r
+#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */\r
+#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */\r
+#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */\r
+#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */\r
+#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */\r
+#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */\r
+#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */\r
+#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */\r
+#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */\r
+#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH_Pos (0U)\r
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL_Pos (0U)\r
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVTR_EIVLRXS_Pos (31U)\r
+#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */\r
+#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */\r
+#define ETH_MACVTR_EIVLS_Pos (28U)\r
+#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */\r
+#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */\r
+#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */\r
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)\r
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */\r
+#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\r
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)\r
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */\r
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\r
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)\r
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */\r
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */\r
+#define ETH_MACVTR_ERIVLT_Pos (27U)\r
+#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */\r
+#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */\r
+#define ETH_MACVTR_EDVLP_Pos (26U)\r
+#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */\r
+#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */\r
+#define ETH_MACVTR_VTHM_Pos (25U)\r
+#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */\r
+#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */\r
+#define ETH_MACVTR_EVLRXS_Pos (24U)\r
+#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */\r
+#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */\r
+#define ETH_MACVTR_EVLS_Pos (21U)\r
+#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */\r
+#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */\r
+#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */\r
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)\r
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */\r
+#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\r
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)\r
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */\r
+#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\r
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)\r
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */\r
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */\r
+#define ETH_MACVTR_DOVLTC_Pos (20U)\r
+#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */\r
+#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */\r
+#define ETH_MACVTR_ERSVLM_Pos (19U)\r
+#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */\r
+#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */\r
+#define ETH_MACVTR_ESVL_Pos (18U)\r
+#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */\r
+#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */\r
+#define ETH_MACVTR_VTIM_Pos (17U)\r
+#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */\r
+#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */\r
+#define ETH_MACVTR_ETV_Pos (16U)\r
+#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */\r
+#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */\r
+#define ETH_MACVTR_VL_Pos (0U)\r
+#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */\r
+#define ETH_MACVTR_VL_UP_Pos (13U)\r
+#define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */\r
+#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */\r
+#define ETH_MACVTR_VL_CFIDEI_Pos (12U)\r
+#define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */\r
+#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r
+#define ETH_MACVTR_VL_VID_Pos (0U)\r
+#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */\r
+#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Hash Table Register */\r
+#define ETH_MACVHTR_VLHT_Pos (0U)\r
+#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Incl Register */\r
+#define ETH_MACVIR_VLTI_Pos (20U)\r
+#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */\r
+#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */\r
+#define ETH_MACVIR_CSVL_Pos (19U)\r
+#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */\r
+#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */\r
+#define ETH_MACVIR_VLP_Pos (18U)\r
+#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */\r
+#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */\r
+#define ETH_MACVIR_VLC_Pos (16U)\r
+#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */\r
+#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */\r
+#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */\r
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)\r
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\r
+#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\r
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)\r
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\r
+#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\r
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)\r
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\r
+#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\r
+#define ETH_MACVIR_VLT_Pos (0U)\r
+#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */\r
+#define ETH_MACVIR_VLT_UP_Pos (13U)\r
+#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */\r
+#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */\r
+#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)\r
+#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\r
+#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r
+#define ETH_MACVIR_VLT_VID_Pos (0U)\r
+#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */\r
+#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */\r
+\r
+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */\r
+#define ETH_MACIVIR_VLTI_Pos (20U)\r
+#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */\r
+#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */\r
+#define ETH_MACIVIR_CSVL_Pos (19U)\r
+#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */\r
+#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */\r
+#define ETH_MACIVIR_VLP_Pos (18U)\r
+#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */\r
+#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */\r
+#define ETH_MACIVIR_VLC_Pos (16U)\r
+#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */\r
+#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */\r
+#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */\r
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)\r
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\r
+#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\r
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)\r
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\r
+#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\r
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)\r
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\r
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\r
+#define ETH_MACIVIR_VLT_Pos (0U)\r
+#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */\r
+#define ETH_MACIVIR_VLT_UP_Pos (13U)\r
+#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */\r
+#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */\r
+#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)\r
+#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\r
+#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r
+#define ETH_MACIVIR_VLT_VID_Pos (0U)\r
+#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */\r
+#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */\r
+\r
+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */\r
+#define ETH_MACTFCR_PT_Pos (16U)\r
+#define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */\r
+#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */\r
+#define ETH_MACTFCR_DZPQ_Pos (7U)\r
+#define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */\r
+#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */\r
+#define ETH_MACTFCR_PLT_Pos (4U)\r
+#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */\r
+#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */\r
+#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
+#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)\r
+#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */\r
+#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */\r
+#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)\r
+#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */\r
+#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */\r
+#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)\r
+#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */\r
+#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */\r
+#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)\r
+#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */\r
+#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */\r
+#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)\r
+#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */\r
+#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */\r
+#define ETH_MACTFCR_TFE_Pos (1U)\r
+#define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */\r
+#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */\r
+#define ETH_MACTFCR_FCB_Pos (0U)\r
+#define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */\r
+#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */\r
+\r
+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */\r
+#define ETH_MACRFCR_UP_Pos (1U)\r
+#define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */\r
+#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */\r
+#define ETH_MACRFCR_RFE_Pos (0U)\r
+#define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */\r
+#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Status Register */\r
+#define ETH_MACISR_RXSTSIS_Pos (14U)\r
+#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */\r
+#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */\r
+#define ETH_MACISR_TXSTSIS_Pos (13U)\r
+#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */\r
+#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */\r
+#define ETH_MACISR_TSIS_Pos (12U)\r
+#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */\r
+#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */\r
+#define ETH_MACISR_MMCTXIS_Pos (10U)\r
+#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */\r
+#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */\r
+#define ETH_MACISR_MMCRXIS_Pos (9U)\r
+#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */\r
+#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */\r
+#define ETH_MACISR_MMCIS_Pos (8U)\r
+#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */\r
+#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */\r
+#define ETH_MACISR_LPIIS_Pos (5U)\r
+#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */\r
+#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */\r
+#define ETH_MACISR_PMTIS_Pos (4U)\r
+#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */\r
+#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */\r
+#define ETH_MACISR_PHYIS_Pos (3U)\r
+#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */\r
+#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Enable Register */\r
+#define ETH_MACIER_RXSTSIE_Pos (14U)\r
+#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */\r
+#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */\r
+#define ETH_MACIER_TXSTSIE_Pos (13U)\r
+#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */\r
+#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */\r
+#define ETH_MACIER_TSIE_Pos (12U)\r
+#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */\r
+#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */\r
+#define ETH_MACIER_LPIIE_Pos (5U)\r
+#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */\r
+#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */\r
+#define ETH_MACIER_PMTIE_Pos (4U)\r
+#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */\r
+#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */\r
+#define ETH_MACIER_PHYIE_Pos (3U)\r
+#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */\r
+#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */\r
+\r
+/* Bit definition for Ethernet MAC Rx Tx Status Register */\r
+#define ETH_MACRXTXSR_RWT_Pos (8U)\r
+#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */\r
+#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */\r
+#define ETH_MACRXTXSR_EXCOL_Pos (5U)\r
+#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */\r
+#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */\r
+#define ETH_MACRXTXSR_LCOL_Pos (4U)\r
+#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */\r
+#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */\r
+#define ETH_MACRXTXSR_EXDEF_Pos (3U)\r
+#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */\r
+#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */\r
+#define ETH_MACRXTXSR_LCARR_Pos (2U)\r
+#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */\r
+#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */\r
+#define ETH_MACRXTXSR_NCARR_Pos (1U)\r
+#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */\r
+#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */\r
+#define ETH_MACRXTXSR_TJT_Pos (0U)\r
+#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */\r
+#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control Status Register */\r
+#define ETH_MACPCSR_RWKFILTRST_Pos (31U)\r
+#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */\r
+#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */\r
+#define ETH_MACPCSR_RWKPTR_Pos (24U)\r
+#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */\r
+#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */\r
+#define ETH_MACPCSR_RWKPFE_Pos (10U)\r
+#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */\r
+#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */\r
+#define ETH_MACPCSR_GLBLUCAST_Pos (9U)\r
+#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */\r
+#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */\r
+#define ETH_MACPCSR_RWKPRCVD_Pos (6U)\r
+#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */\r
+#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */\r
+#define ETH_MACPCSR_MGKPRCVD_Pos (5U)\r
+#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */\r
+#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */\r
+#define ETH_MACPCSR_RWKPKTEN_Pos (2U)\r
+#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */\r
+#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */\r
+#define ETH_MACPCSR_MGKPKTEN_Pos (1U)\r
+#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */\r
+#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */\r
+#define ETH_MACPCSR_PWRDWN_Pos (0U)\r
+#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */\r
+#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */\r
+#define ETH_MACRWUPFR_D_Pos (0U)\r
+#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */\r
+\r
+/* Bit definition for Ethernet MAC LPI Control Status Register */\r
+#define ETH_MACLCSR_LPITCSE_Pos (21U)\r
+#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */\r
+#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */\r
+#define ETH_MACLCSR_LPITE_Pos (20U)\r
+#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */\r
+#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */\r
+#define ETH_MACLCSR_LPITXA_Pos (19U)\r
+#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */\r
+#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */\r
+#define ETH_MACLCSR_PLS_Pos (17U)\r
+#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */\r
+#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */\r
+#define ETH_MACLCSR_LPIEN_Pos (16U)\r
+#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */\r
+#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */\r
+#define ETH_MACLCSR_RLPIST_Pos (9U)\r
+#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */\r
+#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */\r
+#define ETH_MACLCSR_TLPIST_Pos (8U)\r
+#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */\r
+#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */\r
+#define ETH_MACLCSR_RLPIEX_Pos (3U)\r
+#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */\r
+#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */\r
+#define ETH_MACLCSR_RLPIEN_Pos (2U)\r
+#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */\r
+#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */\r
+#define ETH_MACLCSR_TLPIEX_Pos (1U)\r
+#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */\r
+#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */\r
+#define ETH_MACLCSR_TLPIEN_Pos (0U)\r
+#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */\r
+#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */\r
+\r
+/* Bit definition for Ethernet MAC LPI Timers Control Register */\r
+#define ETH_MACLTCR_LST_Pos (16U)\r
+#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */\r
+#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */\r
+#define ETH_MACLTCR_TWT_Pos (0U)\r
+#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */\r
+\r
+/* Bit definition for Ethernet MAC LPI Entry Timer Register */\r
+#define ETH_MACLETR_LPIET_Pos (0U)\r
+#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */\r
+#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */\r
+\r
+/* Bit definition for Ethernet MAC 1US Tic Counter Register */\r
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)\r
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */\r
+#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */\r
+\r
+/* Bit definition for Ethernet MAC Version Register */\r
+#define ETH_MACVR_USERVER_Pos (8U)\r
+#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */\r
+#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */\r
+#define ETH_MACVR_SNPSVER_Pos (0U)\r
+#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */\r
+#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */\r
+\r
+/* Bit definition for Ethernet MAC Debug Register */\r
+#define ETH_MACDR_TFCSTS_Pos (17U)\r
+#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */\r
+#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */\r
+#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */\r
+#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)\r
+#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */\r
+#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */\r
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)\r
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */\r
+#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */\r
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)\r
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */\r
+#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */\r
+#define ETH_MACDR_TPESTS_Pos (16U)\r
+#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */\r
+#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */\r
+#define ETH_MACDR_RFCFCSTS_Pos (1U)\r
+#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */\r
+#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */\r
+#define ETH_MACDR_RPESTS_Pos (0U)\r
+#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */\r
+#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */\r
+\r
+/* Bit definition for Ethernet MAC HW Feature0 Register */\r
+#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)\r
+#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */\r
+#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */\r
+#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */\r
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)\r
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */\r
+#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */\r
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)\r
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */\r
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */\r
+#define ETH_MACHWF0R_SAVLANINS_Pos (27U)\r
+#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */\r
+#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */\r
+#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)\r
+#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */\r
+#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */\r
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)\r
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */\r
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */\r
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)\r
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */\r
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */\r
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)\r
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */\r
+#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */\r
+#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)\r
+#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */\r
+#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */\r
+#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)\r
+#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */\r
+#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */\r
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)\r
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */\r
+#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */\r
+#define ETH_MACHWF0R_RXCOESEL_Pos (16U)\r
+#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */\r
+#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */\r
+#define ETH_MACHWF0R_TXCOESEL_Pos (14U)\r
+#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */\r
+#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */\r
+#define ETH_MACHWF0R_EEESEL_Pos (13U)\r
+#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */\r
+#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */\r
+#define ETH_MACHWF0R_TSSEL_Pos (12U)\r
+#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */\r
+#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */\r
+#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)\r
+#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */\r
+#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */\r
+#define ETH_MACHWF0R_MMCSEL_Pos (8U)\r
+#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */\r
+#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */\r
+#define ETH_MACHWF0R_MGKSEL_Pos (7U)\r
+#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */\r
+#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */\r
+#define ETH_MACHWF0R_RWKSEL_Pos (6U)\r
+#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */\r
+#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */\r
+#define ETH_MACHWF0R_SMASEL_Pos (5U)\r
+#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */\r
+#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */\r
+#define ETH_MACHWF0R_VLHASH_Pos (4U)\r
+#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */\r
+#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */\r
+#define ETH_MACHWF0R_PCSSEL_Pos (3U)\r
+#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */\r
+#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */\r
+#define ETH_MACHWF0R_HDSEL_Pos (2U)\r
+#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */\r
+#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */\r
+#define ETH_MACHWF0R_GMIISEL_Pos (1U)\r
+#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */\r
+#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */\r
+#define ETH_MACHWF0R_MIISEL_Pos (0U)\r
+#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */\r
+#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */\r
+\r
+/* Bit definition for Ethernet MAC HW Feature1 Register */\r
+#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)\r
+#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */\r
+#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */\r
+#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)\r
+#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */\r
+#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */\r
+#define ETH_MACHWF1R_AVSEL_Pos (20U)\r
+#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */\r
+#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */\r
+#define ETH_MACHWF1R_DBGMEMA_Pos (19U)\r
+#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */\r
+#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */\r
+#define ETH_MACHWF1R_TSOEN_Pos (18U)\r
+#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */\r
+#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */\r
+#define ETH_MACHWF1R_SPHEN_Pos (17U)\r
+#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */\r
+#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */\r
+#define ETH_MACHWF1R_DCBEN_Pos (16U)\r
+#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */\r
+#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */\r
+#define ETH_MACHWF1R_ADDR64_Pos (14U)\r
+#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */\r
+#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */\r
+#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */\r
+#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */\r
+#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */\r
+#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)\r
+#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */\r
+#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */\r
+#define ETH_MACHWF1R_PTOEN_Pos (12U)\r
+#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */\r
+#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */\r
+#define ETH_MACHWF1R_OSTEN_Pos (11U)\r
+#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */\r
+#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */\r
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)\r
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */\r
+#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */\r
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)\r
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */\r
+#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */\r
+\r
+/* Bit definition for Ethernet MAC HW Feature2 Register */\r
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)\r
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */\r
+#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */\r
+#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)\r
+#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */\r
+#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */\r
+#define ETH_MACHWF2R_TXCHCNT_Pos (18U)\r
+#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */\r
+#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */\r
+#define ETH_MACHWF2R_RXCHCNT_Pos (13U)\r
+#define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */\r
+#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */\r
+#define ETH_MACHWF2R_TXQCNT_Pos (6U)\r
+#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */\r
+#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */\r
+#define ETH_MACHWF2R_RXQCNT_Pos (0U)\r
+#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */\r
+#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */\r
+\r
+/* Bit definition for Ethernet MAC MDIO Address Register */\r
+#define ETH_MACMDIOAR_PSE_Pos (27U)\r
+#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */\r
+#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */\r
+#define ETH_MACMDIOAR_BTB_Pos (26U)\r
+#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */\r
+#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */\r
+#define ETH_MACMDIOAR_PA_Pos (21U)\r
+#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */\r
+#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */\r
+#define ETH_MACMDIOAR_RDA_Pos (16U)\r
+#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */\r
+#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */\r
+#define ETH_MACMDIOAR_NTC_Pos (12U)\r
+#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */\r
+#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */\r
+#define ETH_MACMDIOAR_CR_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */\r
+#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */\r
+#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */\r
+#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */\r
+#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */\r
+#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)\r
+#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */\r
+#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */\r
+#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */\r
+#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */\r
+#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)\r
+#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */\r
+#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */\r
+#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */\r
+#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */\r
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)\r
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */\r
+#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */\r
+#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)\r
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */\r
+#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */\r
+#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)\r
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */\r
+#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */\r
+#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)\r
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */\r
+#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)\r
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */\r
+#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */\r
+#define ETH_MACMDIOAR_SKAP_Pos (4U)\r
+#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */\r
+#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */\r
+#define ETH_MACMDIOAR_MOC_Pos (2U)\r
+#define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */\r
+#define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */\r
+#define ETH_MACMDIOAR_MOC_WR_Pos (2U)\r
+#define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */\r
+#define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */\r
+#define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)\r
+#define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */\r
+#define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */\r
+#define ETH_MACMDIOAR_MOC_RD_Pos (2U)\r
+#define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */\r
+#define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */\r
+#define ETH_MACMDIOAR_C45E_Pos (1U)\r
+#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */\r
+#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */\r
+#define ETH_MACMDIOAR_MB_Pos (0U)\r
+#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */\r
+#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */\r
+\r
+/* Bit definition for Ethernet MAC MDIO Data Register */\r
+#define ETH_MACMDIODR_RA_Pos (16U)\r
+#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */\r
+#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */\r
+#define ETH_MACMDIODR_MD_Pos (0U)\r
+#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */\r
+\r
+/* Bit definition for Ethernet ARP Address Register */\r
+#define ETH_MACARPAR_ARPPA_Pos (0U)\r
+#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */\r
+\r
+/* Bit definition for Ethernet MAC Address 0 High Register */\r
+#define ETH_MACA0HR_AE_Pos (31U)\r
+#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/\r
+#define ETH_MACA0HR_ADDRHI_Pos (0U)\r
+#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/\r
+\r
+/* Bit definition for Ethernet MAC Address 0 Low Register */\r
+#define ETH_MACA0LR_ADDRLO_Pos (0U)\r
+#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/\r
+\r
+/* Bit definition for Ethernet MAC Address 1 High Register */\r
+#define ETH_MACA1HR_AE_Pos (31U)\r
+#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/\r
+#define ETH_MACA1HR_SA_Pos (30U)\r
+#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\r
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */\r
+#define ETH_MACA1HR_MBC_Pos (24U)\r
+#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\r
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */\r
+#define ETH_MACA1HR_ADDRHI_Pos (0U)\r
+#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/\r
+\r
+/* Bit definition for Ethernet MAC Address 1 Low Register */\r
+#define ETH_MACA1LR_ADDRLO_Pos (0U)\r
+#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/\r
+\r
+/* Bit definition for Ethernet MAC Address 2 High Register */\r
+#define ETH_MACA2HR_AE_Pos (31U)\r
+#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/\r
+#define ETH_MACA2HR_SA_Pos (30U)\r
+#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\r
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */\r
+#define ETH_MACA2HR_MBC_Pos (24U)\r
+#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\r
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */\r
+#define ETH_MACA2HR_ADDRHI_Pos (0U)\r
+#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/\r
+\r
+/* Bit definition for Ethernet MAC Address 2 Low Register */\r
+#define ETH_MACA2LR_ADDRLO_Pos (0U)\r
+#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/\r
+\r
+/* Bit definition for Ethernet MAC Address 3 High Register */\r
+#define ETH_MACA3HR_AE_Pos (31U)\r
+#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/\r
+#define ETH_MACA3HR_SA_Pos (30U)\r
+#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\r
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */\r
+#define ETH_MACA3HR_MBC_Pos (24U)\r
+#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\r
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */\r
+#define ETH_MACA3HR_ADDRHI_Pos (0U)\r
+#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/\r
+\r
+/* Bit definition for Ethernet MAC Address 3 Low Register */\r
+#define ETH_MACA3LR_ADDRLO_Pos (0U)\r
+#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/\r
+\r
+/* Bit definition for Ethernet MAC Address High Register */\r
+#define ETH_MACAHR_AE_Pos (31U)\r
+#define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */\r
+#define ETH_MACAHR_SA_Pos (30U)\r
+#define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */\r
+#define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */\r
+#define ETH_MACAHR_MBC_Pos (24U)\r
+#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */\r
+#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */\r
+#define ETH_MACAHR_MACAH_Pos (0U)\r
+#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */\r
+\r
+/* Bit definition for Ethernet MAC Address Low Register */\r
+#define ETH_MACALR_MACAL_Pos (0U)\r
+#define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */\r
+\r
+/* Bit definition for Ethernet MMC Control Register */\r
+#define ETH_MMCCR_UCDBC_Pos (8U)\r
+#define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */\r
+#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */\r
+#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)\r
+#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */\r
+#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */\r
+#define ETH_MMCCR_CNTPRST_Pos (4U)\r
+#define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */\r
+#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */\r
+#define ETH_MMCCR_CNTFREEZ_Pos (3U)\r
+#define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */\r
+#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */\r
+#define ETH_MMCCR_RSTONRD_Pos (2U)\r
+#define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */\r
+#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */\r
+#define ETH_MMCCR_CNTSTOPRO_Pos (1U)\r
+#define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */\r
+#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CNTRST_Pos (0U)\r
+#define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */\r
+#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Rx Interrupt Register */\r
+#define ETH_MMCRIR_RXLPITRCIS_Pos (27U)\r
+#define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */\r
+#define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */\r
+#define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)\r
+#define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */\r
+#define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */\r
+#define ETH_MMCRIR_RXUCGPIS_Pos (17U)\r
+#define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */\r
+#define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */\r
+#define ETH_MMCRIR_RXALGNERPIS_Pos (6U)\r
+#define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */\r
+#define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */\r
+#define ETH_MMCRIR_RXCRCERPIS_Pos (5U)\r
+#define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */\r
+#define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */\r
+\r
+/* Bit definition for Ethernet MMC Tx Interrupt Register */\r
+#define ETH_MMCTIR_TXLPITRCIS_Pos (27U)\r
+#define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */\r
+#define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */\r
+#define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)\r
+#define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */\r
+#define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */\r
+#define ETH_MMCTIR_TXGPKTIS_Pos (21U)\r
+#define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */\r
+#define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */\r
+#define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)\r
+#define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */\r
+#define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */\r
+#define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)\r
+#define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */\r
+#define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */\r
+\r
+/* Bit definition for Ethernet MMC Rx interrupt Mask register */\r
+#define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)\r
+#define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */\r
+#define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */\r
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)\r
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */\r
+#define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */\r
+#define ETH_MMCRIMR_RXUCGPIM_Pos (17U)\r
+#define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */\r
+#define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */\r
+#define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)\r
+#define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */\r
+#define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */\r
+#define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)\r
+#define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */\r
+#define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */\r
+\r
+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)\r
+#define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */\r
+#define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/\r
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)\r
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */\r
+#define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/\r
+#define ETH_MMCTIMR_TXGPKTIM_Pos (21U)\r
+#define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */\r
+#define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/\r
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)\r
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */\r
+#define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */\r
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)\r
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */\r
+#define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */\r
+\r
+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */\r
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)\r
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */\r
+\r
+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */\r
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)\r
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */\r
+\r
+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */\r
+#define ETH_MMCTPCGR_TXPKTG_Pos (0U)\r
+#define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */\r
+\r
+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */\r
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)\r
+#define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */\r
+\r
+/* Bit definition for Ethernet MMC Rx alignment error packets register */\r
+#define ETH_MMCRAEPR_RXALGNERR_Pos (0U)\r
+#define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */\r
+\r
+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */\r
+#define ETH_MMCRUPGR_RXUCASTG_Pos (0U)\r
+#define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */\r
+\r
+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */\r
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)\r
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */\r
+\r
+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */\r
+#define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)\r
+#define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */\r
+\r
+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */\r
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)\r
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */\r
+\r
+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */\r
+#define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)\r
+#define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */\r
+\r
+/* Bit definition for Ethernet MAC L3 L4 Control Register */\r
+#define ETH_MACL3L4CR_L4DPIM_Pos (21U)\r
+#define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */\r
+#define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */\r
+#define ETH_MACL3L4CR_L4DPM_Pos (20U)\r
+#define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */\r
+#define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */\r
+#define ETH_MACL3L4CR_L4SPIM_Pos (19U)\r
+#define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */\r
+#define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */\r
+#define ETH_MACL3L4CR_L4SPM_Pos (18U)\r
+#define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */\r
+#define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */\r
+#define ETH_MACL3L4CR_L4PEN_Pos (16U)\r
+#define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */\r
+#define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */\r
+#define ETH_MACL3L4CR_L3HDBM_Pos (11U)\r
+#define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */\r
+#define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */\r
+#define ETH_MACL3L4CR_L3HSBM_Pos (6U)\r
+#define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */\r
+#define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */\r
+#define ETH_MACL3L4CR_L3DAIM_Pos (5U)\r
+#define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */\r
+#define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */\r
+#define ETH_MACL3L4CR_L3DAM_Pos (4U)\r
+#define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */\r
+#define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */\r
+#define ETH_MACL3L4CR_L3SAIM_Pos (3U)\r
+#define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */\r
+#define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */\r
+#define ETH_MACL3L4CR_L3SAM_Pos (2U)\r
+#define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */\r
+#define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/\r
+#define ETH_MACL3L4CR_L3PEN_Pos (0U)\r
+#define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */\r
+#define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */\r
+\r
+/* Bit definition for Ethernet MAC L4 Address Register */\r
+#define ETH_MACL4AR_L4DP_Pos (16U)\r
+#define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */\r
+#define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */\r
+#define ETH_MACL4AR_L4SP_Pos (0U)\r
+#define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */\r
+\r
+/* Bit definition for Ethernet MAC L3 Address0 Register */\r
+#define ETH_MACL3A0R_L3A0_Pos (0U)\r
+#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */\r
+\r
+/* Bit definition for Ethernet MAC L4 Address1 Register */\r
+#define ETH_MACL3A1R_L3A1_Pos (0U)\r
+#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */\r
+\r
+/* Bit definition for Ethernet MAC L4 Address2 Register */\r
+#define ETH_MACL3A2R_L3A2_Pos (0U)\r
+#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */\r
+\r
+/* Bit definition for Ethernet MAC L4 Address3 Register */\r
+#define ETH_MACL3A3R_L3A3_Pos (0U)\r
+#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */\r
+\r
+/* Bit definition for Ethernet MAC Timestamp Control Register */\r
+#define ETH_MACTSCR_TXTSSTSM_Pos (24U)\r
+#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */\r
+#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */\r
+#define ETH_MACTSCR_CSC_Pos (19U)\r
+#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */\r
+#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */\r
+#define ETH_MACTSCR_TSENMACADDR_Pos (18U)\r
+#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */\r
+#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */\r
+#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)\r
+#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */\r
+#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */\r
+#define ETH_MACTSCR_TSMSTRENA_Pos (15U)\r
+#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */\r
+#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */\r
+#define ETH_MACTSCR_TSEVNTENA_Pos (14U)\r
+#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */\r
+#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */\r
+#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)\r
+#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */\r
+#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */\r
+#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)\r
+#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */\r
+#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */\r
+#define ETH_MACTSCR_TSIPENA_Pos (11U)\r
+#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */\r
+#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */\r
+#define ETH_MACTSCR_TSVER2ENA_Pos (10U)\r
+#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */\r
+#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */\r
+#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)\r
+#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */\r
+#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */\r
+#define ETH_MACTSCR_TSENALL_Pos (8U)\r
+#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */\r
+#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */\r
+#define ETH_MACTSCR_TSADDREG_Pos (5U)\r
+#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */\r
+#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */\r
+#define ETH_MACTSCR_TSUPDT_Pos (3U)\r
+#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */\r
+#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */\r
+#define ETH_MACTSCR_TSINIT_Pos (2U)\r
+#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */\r
+#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */\r
+#define ETH_MACTSCR_TSCFUPDT_Pos (1U)\r
+#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */\r
+#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/\r
+#define ETH_MACTSCR_TSENA_Pos (0U)\r
+#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */\r
+#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */\r
+\r
+/* Bit definition for Ethernet MAC Sub-second Increment Register */\r
+#define ETH_MACMACSSIR_SSINC_Pos (16U)\r
+#define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */\r
+#define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */\r
+#define ETH_MACMACSSIR_SNSINC_Pos (8U)\r
+#define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */\r
+#define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */\r
+\r
+/* Bit definition for Ethernet MAC System Time Seconds Register */\r
+#define ETH_MACSTSR_TSS_Pos (0U)\r
+#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */\r
+\r
+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */\r
+#define ETH_MACSTNR_TSSS_Pos (0U)\r
+#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */\r
+#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */\r
+\r
+/* Bit definition for Ethernet MAC System Time Seconds Update Register */\r
+#define ETH_MACSTSUR_TSS_Pos (0U)\r
+#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */\r
+\r
+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */\r
+#define ETH_MACSTNUR_ADDSUB_Pos (31U)\r
+#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */\r
+#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */\r
+#define ETH_MACSTNUR_TSSS_Pos (0U)\r
+#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */\r
+#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */\r
+\r
+/* Bit definition for Ethernet MAC Timestamp Addend Register */\r
+#define ETH_MACTSAR_TSAR_Pos (0U)\r
+#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */\r
+\r
+/* Bit definition for Ethernet MAC Timestamp Status Register */\r
+#define ETH_MACTSSR_ATSNS_Pos (25U)\r
+#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */\r
+#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */\r
+#define ETH_MACTSSR_ATSSTM_Pos (24U)\r
+#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */\r
+#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */\r
+#define ETH_MACTSSR_ATSSTN_Pos (16U)\r
+#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */\r
+#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */\r
+#define ETH_MACTSSR_TXTSSIS_Pos (15U)\r
+#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */\r
+#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */\r
+#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)\r
+#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */\r
+#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */\r
+#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)\r
+#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */\r
+#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/\r
+#define ETH_MACTSSR_TSTARGT0_Pos (1U)\r
+#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */\r
+#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */\r
+#define ETH_MACTSSR_TSSOVF_Pos (0U)\r
+#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */\r
+#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */\r
+\r
+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */\r
+#define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)\r
+#define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */\r
+#define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */\r
+#define ETH_MACTTSSNR_TXTSSLO_Pos (0U)\r
+#define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */\r
+#define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */\r
+\r
+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */\r
+#define ETH_MACTTSSSR_TXTSSHI_Pos (0U)\r
+#define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */\r
+\r
+/* Bit definition for Ethernet MAC Auxiliary Control Register*/\r
+#define ETH_MACACR_ATSEN3_Pos (7U)\r
+#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */\r
+#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */\r
+#define ETH_MACACR_ATSEN2_Pos (6U)\r
+#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */\r
+#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */\r
+#define ETH_MACACR_ATSEN1_Pos (5U)\r
+#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */\r
+#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */\r
+#define ETH_MACACR_ATSEN0_Pos (4U)\r
+#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */\r
+#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */\r
+#define ETH_MACACR_ATSFC_Pos (0U)\r
+#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */\r
+#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */\r
+\r
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */\r
+#define ETH_MACATSNR_AUXTSLO_Pos (0U)\r
+#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */\r
+#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */\r
+\r
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */\r
+#define ETH_MACATSSR_AUXTSHI_Pos (0U)\r
+#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */\r
+\r
+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */\r
+#define ETH_MACTSIACR_OSTIAC_Pos (0U)\r
+#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */\r
+\r
+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */\r
+#define ETH_MACTSEACR_OSTEAC_Pos (0U)\r
+#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */\r
+\r
+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */\r
+#define ETH_MACTSICNR_TSIC_Pos (0U)\r
+#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */\r
+\r
+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */\r
+#define ETH_MACTSECNR_TSEC_Pos (0U)\r
+#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */\r
+\r
+/* Bit definition for Ethernet MAC PPS Control Register */\r
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)\r
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */\r
+#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */\r
+#define ETH_MACPPSCR_PPSEN0_Pos (4U)\r
+#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */\r
+#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */\r
+#define ETH_MACPPSCR_PPSCTRL_Pos (0U)\r
+#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */\r
+#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */\r
+\r
+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */\r
+#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)\r
+#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */\r
+\r
+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */\r
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)\r
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */\r
+#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */\r
+#define ETH_MACPPSTTNR_TTSL0_Pos (0U)\r
+#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */\r
+#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */\r
+\r
+/* Bit definition for Ethernet MAC PPS Interval Register */\r
+#define ETH_MACPPSIR_PPSINT0_Pos (0U)\r
+#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */\r
+\r
+/* Bit definition for Ethernet MAC PPS Width Register */\r
+#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)\r
+#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */\r
+\r
+/* Bit definition for Ethernet MAC PTP Offload Control Register */\r
+#define ETH_MACPOCR_DN_Pos (8U)\r
+#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */\r
+#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */\r
+#define ETH_MACPOCR_DRRDIS_Pos (6U)\r
+#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */\r
+#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */\r
+#define ETH_MACPOCR_APDREQTRIG_Pos (5U)\r
+#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */\r
+#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */\r
+#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)\r
+#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */\r
+#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */\r
+#define ETH_MACPOCR_APDREQEN_Pos (2U)\r
+#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */\r
+#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */\r
+#define ETH_MACPOCR_ASYNCEN_Pos (1U)\r
+#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */\r
+#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */\r
+#define ETH_MACPOCR_PTOEN_Pos (0U)\r
+#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */\r
+#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */\r
+\r
+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */\r
+#define ETH_MACSPI0R_SPI0_Pos (0U)\r
+#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */\r
+\r
+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */\r
+#define ETH_MACSPI1R_SPI1_Pos (0U)\r
+#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */\r
+\r
+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */\r
+#define ETH_MACSPI2R_SPI2_Pos (0U)\r
+#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */\r
+\r
+/* Bit definition for Ethernet MAC Log Message Interval Register */\r
+#define ETH_MACLMIR_LMPDRI_Pos (24U)\r
+#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */\r
+#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */\r
+#define ETH_MACLMIR_DRSYNCR_Pos (8U)\r
+#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */\r
+#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */\r
+#define ETH_MACLMIR_LSI_Pos (0U)\r
+#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */\r
+#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */\r
+\r
+/* Bit definition for Ethernet MTL Operation Mode Register */\r
+#define ETH_MTLOMR_CNTCLR_Pos (9U)\r
+#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */\r
+#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */\r
+#define ETH_MTLOMR_CNTPRST_Pos (8U)\r
+#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */\r
+#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */\r
+#define ETH_MTLOMR_DTXSTS_Pos (1U)\r
+#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */\r
+#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */\r
+\r
+/* Bit definition for Ethernet MTL Interrupt Status Register */\r
+#define ETH_MTLISR_MACIS_Pos (16U)\r
+#define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */\r
+#define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */\r
+#define ETH_MTLISR_QIS_Pos (0U)\r
+#define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */\r
+#define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */\r
+\r
+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */\r
+#define ETH_MTLTQOMR_TTC_Pos (4U)\r
+#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */\r
+#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */\r
+#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */\r
+#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */\r
+#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */\r
+#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */\r
+#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */\r
+#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */\r
+#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */\r
+#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */\r
+#define ETH_MTLTQOMR_TSF_Pos (1U)\r
+#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */\r
+#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */\r
+#define ETH_MTLTQOMR_FTQ_Pos (0U)\r
+#define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */\r
+#define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */\r
+\r
+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */\r
+#define ETH_MTLTQUR_UFCNTOVF_Pos (11U)\r
+#define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */\r
+#define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */\r
+#define ETH_MTLTQUR_UFPKTCNT_Pos (0U)\r
+#define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */\r
+#define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */\r
+\r
+/* Bit definition for Ethernet MTL Tx Queue Debug Register */\r
+#define ETH_MTLTQDR_STXSTSF_Pos (20U)\r
+#define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */\r
+#define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */\r
+#define ETH_MTLTQDR_PTXQ_Pos (16U)\r
+#define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */\r
+#define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */\r
+#define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)\r
+#define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */\r
+#define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */\r
+#define ETH_MTLTQDR_TXQSTS_Pos (4U)\r
+#define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */\r
+#define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */\r
+#define ETH_MTLTQDR_TWCSTS_Pos (3U)\r
+#define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */\r
+#define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */\r
+#define ETH_MTLTQDR_TRCSTS_Pos (1U)\r
+#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */\r
+#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */\r
+#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */\r
+#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */\r
+#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */\r
+#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */\r
+#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)\r
+#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */\r
+#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */\r
+\r
+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */\r
+#define ETH_MTLQICSR_RXOIE_Pos (24U)\r
+#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */\r
+#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */\r
+#define ETH_MTLQICSR_RXOVFIS_Pos (16U)\r
+#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */\r
+#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */\r
+#define ETH_MTLQICSR_TXUIE_Pos (8U)\r
+#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */\r
+#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */\r
+#define ETH_MTLQICSR_TXUNFIS_Pos (0U)\r
+#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */\r
+#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */\r
+\r
+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */\r
+#define ETH_MTLRQOMR_RQS_Pos (20U)\r
+#define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */\r
+#define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */\r
+#define ETH_MTLRQOMR_RFD_Pos (14U)\r
+#define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */\r
+#define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */\r
+#define ETH_MTLRQOMR_RFA_Pos (8U)\r
+#define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */\r
+#define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */\r
+#define ETH_MTLRQOMR_EHFC_Pos (7U)\r
+#define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */\r
+#define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */\r
+#define ETH_MTLRQOMR_DISTCPEF_Pos (6U)\r
+#define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */\r
+#define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */\r
+#define ETH_MTLRQOMR_RSF_Pos (5U)\r
+#define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */\r
+#define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */\r
+#define ETH_MTLRQOMR_FEP_Pos (4U)\r
+#define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */\r
+#define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */\r
+#define ETH_MTLRQOMR_FUP_Pos (3U)\r
+#define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */\r
+#define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */\r
+#define ETH_MTLRQOMR_RTC_Pos (0U)\r
+#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */\r
+#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */\r
+#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */\r
+#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */\r
+#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */\r
+#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */\r
+\r
+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */\r
+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)\r
+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */\r
+#define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */\r
+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)\r
+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */\r
+#define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */\r
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)\r
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */\r
+#define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */\r
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)\r
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */\r
+#define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */\r
+\r
+/* Bit definition for Ethernet MTL Rx Queue Debug Register */\r
+#define ETH_MTLRQDR_PRXQ_Pos (16U)\r
+#define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */\r
+#define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */\r
+#define ETH_MTLRQDR_RXQSTS_Pos (4U)\r
+#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */\r
+#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */\r
+#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */\r
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)\r
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */\r
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */\r
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)\r
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */\r
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */\r
+#define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)\r
+#define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */\r
+#define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */\r
+#define ETH_MTLRQDR_RRCSTS_Pos (1U)\r
+#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */\r
+#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */\r
+#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */\r
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)\r
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */\r
+#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */\r
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)\r
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */\r
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */\r
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)\r
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */\r
+#define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */\r
+#define ETH_MTLRQDR_RWCSTS_Pos (0U)\r
+#define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */\r
+#define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */\r
+\r
+/* Bit definition for Ethernet MTL Rx Queue Control Register */\r
+#define ETH_MTLRQCR_RQPA_Pos (3U)\r
+#define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */\r
+#define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */\r
+#define ETH_MTLRQCR_RQW_Pos (0U)\r
+#define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */\r
+#define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */\r
+\r
+/* Bit definition for Ethernet DMA Mode Register */\r
+#define ETH_DMAMR_INTM_Pos (16U)\r
+#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */\r
+#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */\r
+#define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */\r
+#define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */\r
+#define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */\r
+#define ETH_DMAMR_PR_Pos (12U)\r
+#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */\r
+#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */\r
+#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */\r
+#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */\r
+#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */\r
+#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */\r
+#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */\r
+#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */\r
+#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */\r
+#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */\r
+#define ETH_DMAMR_TXPR_Pos (11U)\r
+#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */\r
+#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */\r
+#define ETH_DMAMR_DA_Pos (1U)\r
+#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */\r
+#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */\r
+#define ETH_DMAMR_SWR_Pos (0U)\r
+#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */\r
+#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */\r
+\r
+/* Bit definition for Ethernet DMA SysBus Mode Register */\r
+#define ETH_DMASBMR_RB_Pos (15U)\r
+#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */\r
+#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */\r
+#define ETH_DMASBMR_MB_Pos (14U)\r
+#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */\r
+#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */\r
+#define ETH_DMASBMR_AAL_Pos (12U)\r
+#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */\r
+#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */\r
+#define ETH_DMASBMR_FB_Pos (0U)\r
+#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */\r
+#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Status Register */\r
+#define ETH_DMAISR_MACIS_Pos (17U)\r
+#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */\r
+#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */\r
+#define ETH_DMAISR_MTLIS_Pos (16U)\r
+#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */\r
+#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */\r
+#define ETH_DMAISR_DMACIS_Pos (0U)\r
+#define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */\r
+#define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */\r
+\r
+/* Bit definition for Ethernet DMA Debug Status Register */\r
+#define ETH_DMADSR_TPS_Pos (12U)\r
+#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */\r
+#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */\r
+#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */\r
+#define ETH_DMADSR_TPS_FETCHING_Pos (12U)\r
+#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */\r
+#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */\r
+#define ETH_DMADSR_TPS_WAITING_Pos (13U)\r
+#define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */\r
+#define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */\r
+#define ETH_DMADSR_TPS_READING_Pos (12U)\r
+#define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */\r
+#define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */\r
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)\r
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */\r
+#define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */\r
+#define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)\r
+#define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */\r
+#define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */\r
+#define ETH_DMADSR_TPS_CLOSING_Pos (12U)\r
+#define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */\r
+#define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */\r
+#define ETH_DMADSR_RPS_Pos (8U)\r
+#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */\r
+#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */\r
+#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */\r
+#define ETH_DMADSR_RPS_FETCHING_Pos (12U)\r
+#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */\r
+#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */\r
+#define ETH_DMADSR_RPS_WAITING_Pos (12U)\r
+#define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */\r
+#define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */\r
+#define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)\r
+#define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */\r
+#define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */\r
+#define ETH_DMADSR_RPS_CLOSING_Pos (12U)\r
+#define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */\r
+#define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */\r
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)\r
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */\r
+#define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */\r
+#define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)\r
+#define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */\r
+#define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */\r
+\r
+/* Bit definition for Ethernet DMA Channel Control Register */\r
+#define ETH_DMACCR_DSL_Pos (18U)\r
+#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */\r
+#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */\r
+#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)\r
+#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)\r
+#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)\r
+#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)\r
+#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */\r
+#define ETH_DMACCR_MSS_Pos (0U)\r
+#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */\r
+#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */\r
+\r
+/* Bit definition for Ethernet DMA Channel Tx Control Register */\r
+#define ETH_DMACTCR_TPBL_Pos (16U)\r
+#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */\r
+#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */\r
+#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */\r
+#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */\r
+#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */\r
+#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */\r
+#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */\r
+#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */\r
+#define ETH_DMACTCR_TSE_Pos (12U)\r
+#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */\r
+#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */\r
+#define ETH_DMACTCR_OSP_Pos (4U)\r
+#define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */\r
+#define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */\r
+#define ETH_DMACTCR_ST_Pos (0U)\r
+#define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */\r
+#define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */\r
+\r
+/* Bit definition for Ethernet DMA Channel Rx Control Register */\r
+#define ETH_DMACRCR_RPF_Pos (31U)\r
+#define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */\r
+#define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */\r
+#define ETH_DMACRCR_RPBL_Pos (16U)\r
+#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */\r
+#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */\r
+#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */\r
+#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */\r
+#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */\r
+#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */\r
+#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */\r
+#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */\r
+#define ETH_DMACRCR_RBSZ_Pos (1U)\r
+#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */\r
+#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */\r
+#define ETH_DMACRCR_SR_Pos (0U)\r
+#define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */\r
+#define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */\r
+\r
+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */\r
+#define ETH_DMACTDLAR_TDESLA_Pos (2U)\r
+#define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */\r
+#define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */\r
+\r
+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */\r
+#define ETH_DMACRDLAR_RDESLA_Pos (2U)\r
+#define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */\r
+#define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */\r
+\r
+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */\r
+#define ETH_DMACTDTPR_TDT_Pos (2U)\r
+#define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */\r
+#define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */\r
+\r
+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */\r
+#define ETH_DMACRDTPR_RDT_Pos (2U)\r
+#define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */\r
+#define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */\r
+\r
+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */\r
+#define ETH_DMACTDRLR_TDRL_Pos (0U)\r
+#define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */\r
+#define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */\r
+\r
+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */\r
+#define ETH_DMACRDRLR_RDRL_Pos (0U)\r
+#define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */\r
+#define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */\r
+\r
+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */\r
+#define ETH_DMACIER_NIE_Pos (15U)\r
+#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */\r
+#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */\r
+#define ETH_DMACIER_AIE_Pos (14U)\r
+#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */\r
+#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */\r
+#define ETH_DMACIER_CDEE_Pos (13U)\r
+#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */\r
+#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */\r
+#define ETH_DMACIER_FBEE_Pos (12U)\r
+#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */\r
+#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */\r
+#define ETH_DMACIER_ERIE_Pos (11U)\r
+#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */\r
+#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */\r
+#define ETH_DMACIER_ETIE_Pos (10U)\r
+#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */\r
+#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */\r
+#define ETH_DMACIER_RWTE_Pos (9U)\r
+#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */\r
+#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */\r
+#define ETH_DMACIER_RSE_Pos (8U)\r
+#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */\r
+#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */\r
+#define ETH_DMACIER_RBUE_Pos (7U)\r
+#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */\r
+#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */\r
+#define ETH_DMACIER_RIE_Pos (6U)\r
+#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */\r
+#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */\r
+#define ETH_DMACIER_TBUE_Pos (2U)\r
+#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */\r
+#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */\r
+#define ETH_DMACIER_TXSE_Pos (1U)\r
+#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */\r
+#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */\r
+#define ETH_DMACIER_TIE_Pos (0U)\r
+#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */\r
+#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */\r
+\r
+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */\r
+#define ETH_DMACRIWTR_RWT_Pos (0U)\r
+#define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */\r
+#define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */\r
+\r
+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */\r
+#define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)\r
+#define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */\r
+\r
+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */\r
+#define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)\r
+#define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */\r
+\r
+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */\r
+#define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)\r
+#define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */\r
+\r
+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */\r
+#define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)\r
+#define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */\r
+\r
+/* Bit definition for Ethernet DMA Channel Status Register */\r
+#define ETH_DMACSR_REB_Pos (19U)\r
+#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */\r
+#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */\r
+#define ETH_DMACSR_TEB_Pos (16U)\r
+#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */\r
+#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */\r
+#define ETH_DMACSR_NIS_Pos (15U)\r
+#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */\r
+#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */\r
+#define ETH_DMACSR_AIS_Pos (14U)\r
+#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */\r
+#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */\r
+#define ETH_DMACSR_CDE_Pos (13U)\r
+#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */\r
+#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */\r
+#define ETH_DMACSR_FBE_Pos (12U)\r
+#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */\r
+#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */\r
+#define ETH_DMACSR_ERI_Pos (11U)\r
+#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */\r
+#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */\r
+#define ETH_DMACSR_ETI_Pos (10U)\r
+#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */\r
+#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */\r
+#define ETH_DMACSR_RWT_Pos (9U)\r
+#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */\r
+#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */\r
+#define ETH_DMACSR_RPS_Pos (8U)\r
+#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */\r
+#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */\r
+#define ETH_DMACSR_RBU_Pos (7U)\r
+#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */\r
+#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */\r
+#define ETH_DMACSR_RI_Pos (6U)\r
+#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */\r
+#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */\r
+#define ETH_DMACSR_TBU_Pos (2U)\r
+#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */\r
+#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */\r
+#define ETH_DMACSR_TPS_Pos (1U)\r
+#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */\r
+#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */\r
+#define ETH_DMACSR_TI_Pos (0U)\r
+#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */\r
+#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */\r
+\r
+/* Bit definition for Ethernet DMA Channel missed frame count register */\r
+#define ETH_DMACMFCR_MFCO_Pos (15U)\r
+#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */\r
+#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */\r
+#define ETH_DMACMFCR_MFC_Pos (0U)\r
+#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */\r
+#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/\r
+#define DMA_SxCR_MBURST_Pos (23U)\r
+#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */\r
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */\r
+#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */\r
+#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */\r
+#define DMA_SxCR_PBURST_Pos (21U)\r
+#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */\r
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */\r
+#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */\r
+#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */\r
+#define DMA_SxCR_CT_Pos (19U)\r
+#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */\r
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */\r
+#define DMA_SxCR_DBM_Pos (18U)\r
+#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */\r
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */\r
+#define DMA_SxCR_PL_Pos (16U)\r
+#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */\r
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */\r
+#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */\r
+#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */\r
+#define DMA_SxCR_PINCOS_Pos (15U)\r
+#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */\r
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */\r
+#define DMA_SxCR_MSIZE_Pos (13U)\r
+#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */\r
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */\r
+#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */\r
+#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */\r
+#define DMA_SxCR_PSIZE_Pos (11U)\r
+#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */\r
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */\r
+#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */\r
+#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */\r
+#define DMA_SxCR_MINC_Pos (10U)\r
+#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */\r
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */\r
+#define DMA_SxCR_PINC_Pos (9U)\r
+#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */\r
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */\r
+#define DMA_SxCR_CIRC_Pos (8U)\r
+#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */\r
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */\r
+#define DMA_SxCR_DIR_Pos (6U)\r
+#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */\r
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */\r
+#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */\r
+#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */\r
+#define DMA_SxCR_PFCTRL_Pos (5U)\r
+#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */\r
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */\r
+#define DMA_SxCR_TCIE_Pos (4U)\r
+#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */\r
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */\r
+#define DMA_SxCR_HTIE_Pos (3U)\r
+#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */\r
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */\r
+#define DMA_SxCR_TEIE_Pos (2U)\r
+#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */\r
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */\r
+#define DMA_SxCR_DMEIE_Pos (1U)\r
+#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */\r
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */\r
+#define DMA_SxCR_EN_Pos (0U)\r
+#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */\r
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */\r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT_Pos (0U)\r
+#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */\r
+#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */\r
+#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */\r
+#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */\r
+#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */\r
+#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */\r
+#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */\r
+#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */\r
+#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */\r
+#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */\r
+#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */\r
+#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */\r
+#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */\r
+#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */\r
+#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */\r
+#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */\r
+#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/\r
+#define DMA_SxFCR_FEIE_Pos (7U)\r
+#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */\r
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */\r
+#define DMA_SxFCR_FS_Pos (3U)\r
+#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */\r
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */\r
+#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */\r
+#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */\r
+#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */\r
+#define DMA_SxFCR_DMDIS_Pos (2U)\r
+#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */\r
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */\r
+#define DMA_SxFCR_FTH_Pos (0U)\r
+#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */\r
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */\r
+#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */\r
+#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/\r
+#define DMA_LISR_TCIF3_Pos (27U)\r
+#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */\r
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */\r
+#define DMA_LISR_HTIF3_Pos (26U)\r
+#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */\r
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */\r
+#define DMA_LISR_TEIF3_Pos (25U)\r
+#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */\r
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */\r
+#define DMA_LISR_DMEIF3_Pos (24U)\r
+#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */\r
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */\r
+#define DMA_LISR_FEIF3_Pos (22U)\r
+#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */\r
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */\r
+#define DMA_LISR_TCIF2_Pos (21U)\r
+#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */\r
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */\r
+#define DMA_LISR_HTIF2_Pos (20U)\r
+#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */\r
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */\r
+#define DMA_LISR_TEIF2_Pos (19U)\r
+#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */\r
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */\r
+#define DMA_LISR_DMEIF2_Pos (18U)\r
+#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */\r
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */\r
+#define DMA_LISR_FEIF2_Pos (16U)\r
+#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */\r
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */\r
+#define DMA_LISR_TCIF1_Pos (11U)\r
+#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */\r
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */\r
+#define DMA_LISR_HTIF1_Pos (10U)\r
+#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */\r
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */\r
+#define DMA_LISR_TEIF1_Pos (9U)\r
+#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */\r
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */\r
+#define DMA_LISR_DMEIF1_Pos (8U)\r
+#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */\r
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */\r
+#define DMA_LISR_FEIF1_Pos (6U)\r
+#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */\r
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */\r
+#define DMA_LISR_TCIF0_Pos (5U)\r
+#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */\r
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */\r
+#define DMA_LISR_HTIF0_Pos (4U)\r
+#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */\r
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */\r
+#define DMA_LISR_TEIF0_Pos (3U)\r
+#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */\r
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */\r
+#define DMA_LISR_DMEIF0_Pos (2U)\r
+#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */\r
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */\r
+#define DMA_LISR_FEIF0_Pos (0U)\r
+#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */\r
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */\r
+\r
+/******************** Bits definition for DMA_HISR register *****************/\r
+#define DMA_HISR_TCIF7_Pos (27U)\r
+#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */\r
+#define DMA_HISR_HTIF7_Pos (26U)\r
+#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */\r
+#define DMA_HISR_TEIF7_Pos (25U)\r
+#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */\r
+#define DMA_HISR_DMEIF7_Pos (24U)\r
+#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */\r
+#define DMA_HISR_FEIF7_Pos (22U)\r
+#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */\r
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */\r
+#define DMA_HISR_TCIF6_Pos (21U)\r
+#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */\r
+#define DMA_HISR_HTIF6_Pos (20U)\r
+#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */\r
+#define DMA_HISR_TEIF6_Pos (19U)\r
+#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */\r
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */\r
+#define DMA_HISR_DMEIF6_Pos (18U)\r
+#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */\r
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */\r
+#define DMA_HISR_FEIF6_Pos (16U)\r
+#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */\r
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */\r
+#define DMA_HISR_TCIF5_Pos (11U)\r
+#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */\r
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */\r
+#define DMA_HISR_HTIF5_Pos (10U)\r
+#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */\r
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */\r
+#define DMA_HISR_TEIF5_Pos (9U)\r
+#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */\r
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */\r
+#define DMA_HISR_DMEIF5_Pos (8U)\r
+#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */\r
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */\r
+#define DMA_HISR_FEIF5_Pos (6U)\r
+#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */\r
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */\r
+#define DMA_HISR_TCIF4_Pos (5U)\r
+#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */\r
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */\r
+#define DMA_HISR_HTIF4_Pos (4U)\r
+#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */\r
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */\r
+#define DMA_HISR_TEIF4_Pos (3U)\r
+#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */\r
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */\r
+#define DMA_HISR_DMEIF4_Pos (2U)\r
+#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */\r
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */\r
+#define DMA_HISR_FEIF4_Pos (0U)\r
+#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */\r
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */\r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/\r
+#define DMA_LIFCR_CTCIF3_Pos (27U)\r
+#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */\r
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */\r
+#define DMA_LIFCR_CHTIF3_Pos (26U)\r
+#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */\r
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */\r
+#define DMA_LIFCR_CTEIF3_Pos (25U)\r
+#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */\r
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */\r
+#define DMA_LIFCR_CDMEIF3_Pos (24U)\r
+#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */\r
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */\r
+#define DMA_LIFCR_CFEIF3_Pos (22U)\r
+#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */\r
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */\r
+#define DMA_LIFCR_CTCIF2_Pos (21U)\r
+#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */\r
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */\r
+#define DMA_LIFCR_CHTIF2_Pos (20U)\r
+#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */\r
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */\r
+#define DMA_LIFCR_CTEIF2_Pos (19U)\r
+#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */\r
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */\r
+#define DMA_LIFCR_CDMEIF2_Pos (18U)\r
+#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */\r
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */\r
+#define DMA_LIFCR_CFEIF2_Pos (16U)\r
+#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */\r
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */\r
+#define DMA_LIFCR_CTCIF1_Pos (11U)\r
+#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */\r
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */\r
+#define DMA_LIFCR_CHTIF1_Pos (10U)\r
+#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */\r
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */\r
+#define DMA_LIFCR_CTEIF1_Pos (9U)\r
+#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */\r
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */\r
+#define DMA_LIFCR_CDMEIF1_Pos (8U)\r
+#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */\r
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */\r
+#define DMA_LIFCR_CFEIF1_Pos (6U)\r
+#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */\r
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */\r
+#define DMA_LIFCR_CTCIF0_Pos (5U)\r
+#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */\r
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */\r
+#define DMA_LIFCR_CHTIF0_Pos (4U)\r
+#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */\r
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */\r
+#define DMA_LIFCR_CTEIF0_Pos (3U)\r
+#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */\r
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */\r
+#define DMA_LIFCR_CDMEIF0_Pos (2U)\r
+#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */\r
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */\r
+#define DMA_LIFCR_CFEIF0_Pos (0U)\r
+#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */\r
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */\r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/\r
+#define DMA_HIFCR_CTCIF7_Pos (27U)\r
+#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */\r
+#define DMA_HIFCR_CHTIF7_Pos (26U)\r
+#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */\r
+#define DMA_HIFCR_CTEIF7_Pos (25U)\r
+#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */\r
+#define DMA_HIFCR_CDMEIF7_Pos (24U)\r
+#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */\r
+#define DMA_HIFCR_CFEIF7_Pos (22U)\r
+#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */\r
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */\r
+#define DMA_HIFCR_CTCIF6_Pos (21U)\r
+#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */\r
+#define DMA_HIFCR_CHTIF6_Pos (20U)\r
+#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */\r
+#define DMA_HIFCR_CTEIF6_Pos (19U)\r
+#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */\r
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */\r
+#define DMA_HIFCR_CDMEIF6_Pos (18U)\r
+#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */\r
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */\r
+#define DMA_HIFCR_CFEIF6_Pos (16U)\r
+#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */\r
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */\r
+#define DMA_HIFCR_CTCIF5_Pos (11U)\r
+#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */\r
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */\r
+#define DMA_HIFCR_CHTIF5_Pos (10U)\r
+#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */\r
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */\r
+#define DMA_HIFCR_CTEIF5_Pos (9U)\r
+#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */\r
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */\r
+#define DMA_HIFCR_CDMEIF5_Pos (8U)\r
+#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */\r
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */\r
+#define DMA_HIFCR_CFEIF5_Pos (6U)\r
+#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */\r
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */\r
+#define DMA_HIFCR_CTCIF4_Pos (5U)\r
+#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */\r
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */\r
+#define DMA_HIFCR_CHTIF4_Pos (4U)\r
+#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */\r
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */\r
+#define DMA_HIFCR_CTEIF4_Pos (3U)\r
+#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */\r
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */\r
+#define DMA_HIFCR_CDMEIF4_Pos (2U)\r
+#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */\r
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */\r
+#define DMA_HIFCR_CFEIF4_Pos (0U)\r
+#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */\r
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */\r
+\r
+/****************** Bit definition for DMA_SxPAR register ********************/\r
+#define DMA_SxPAR_PA_Pos (0U)\r
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_SxM0AR register ********************/\r
+#define DMA_SxM0AR_M0A_Pos (0U)\r
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */\r
+\r
+/****************** Bit definition for DMA_SxM1AR register ********************/\r
+#define DMA_SxM1AR_M1A_Pos (0U)\r
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMAMUX Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMAMUX_CxCR register **************/\r
+#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)\r
+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */\r
+#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */\r
+#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */\r
+#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */\r
+#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */\r
+#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */\r
+#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */\r
+#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */\r
+#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */\r
+#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */\r
+#define DMAMUX_CxCR_SOIE_Pos (8U)\r
+#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */\r
+#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */\r
+#define DMAMUX_CxCR_EGE_Pos (9U)\r
+#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */\r
+#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */\r
+#define DMAMUX_CxCR_SE_Pos (16U)\r
+#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */\r
+#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */\r
+#define DMAMUX_CxCR_SPOL_Pos (17U)\r
+#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */\r
+#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */\r
+#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */\r
+#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */\r
+#define DMAMUX_CxCR_NBREQ_Pos (19U)\r
+#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */\r
+#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */\r
+#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */\r
+#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */\r
+#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */\r
+#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */\r
+#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */\r
+#define DMAMUX_CxCR_SYNC_ID_Pos (24U)\r
+#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */\r
+#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */\r
+#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */\r
+#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */\r
+#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */\r
+#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */\r
+#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */\r
+\r
+/******************** Bits definition for DMAMUX_CSR register **************/\r
+#define DMAMUX_CSR_SOF0_Pos (0U)\r
+#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */\r
+#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF1_Pos (1U)\r
+#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */\r
+#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF2_Pos (2U)\r
+#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */\r
+#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF3_Pos (3U)\r
+#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */\r
+#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF4_Pos (4U)\r
+#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */\r
+#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF5_Pos (5U)\r
+#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */\r
+#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF6_Pos (6U)\r
+#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */\r
+#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF7_Pos (7U)\r
+#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */\r
+#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF8_Pos (8U)\r
+#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */\r
+#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF9_Pos (9U)\r
+#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */\r
+#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF10_Pos (10U)\r
+#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */\r
+#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF11_Pos (11U)\r
+#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */\r
+#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF12_Pos (12U)\r
+#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */\r
+#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF13_Pos (13U)\r
+#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */\r
+#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF14_Pos (14U)\r
+#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */\r
+#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */\r
+#define DMAMUX_CSR_SOF15_Pos (15U)\r
+#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */\r
+#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */\r
+\r
+/******************** Bits definition for DMAMUX_CFR register **************/\r
+#define DMAMUX_CFR_CSOF0_Pos (0U)\r
+#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */\r
+#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF1_Pos (1U)\r
+#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */\r
+#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF2_Pos (2U)\r
+#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */\r
+#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF3_Pos (3U)\r
+#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */\r
+#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF4_Pos (4U)\r
+#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */\r
+#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF5_Pos (5U)\r
+#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */\r
+#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF6_Pos (6U)\r
+#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */\r
+#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF7_Pos (7U)\r
+#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */\r
+#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF8_Pos (8U)\r
+#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */\r
+#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF9_Pos (9U)\r
+#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */\r
+#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF10_Pos (10U)\r
+#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */\r
+#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF11_Pos (11U)\r
+#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */\r
+#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF12_Pos (12U)\r
+#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */\r
+#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF13_Pos (13U)\r
+#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */\r
+#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF14_Pos (14U)\r
+#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */\r
+#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */\r
+#define DMAMUX_CFR_CSOF15_Pos (15U)\r
+#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */\r
+#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */\r
+\r
+/******************** Bits definition for DMAMUX_RGxCR register ************/\r
+#define DMAMUX_RGxCR_SIG_ID_Pos (0U)\r
+#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */\r
+#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */\r
+#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */\r
+#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */\r
+#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */\r
+#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */\r
+#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */\r
+#define DMAMUX_RGxCR_OIE_Pos (8U)\r
+#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */\r
+#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */\r
+#define DMAMUX_RGxCR_GE_Pos (16U)\r
+#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */\r
+#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */\r
+#define DMAMUX_RGxCR_GPOL_Pos (17U)\r
+#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */\r
+#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */\r
+#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */\r
+#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */\r
+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)\r
+#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */\r
+#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */\r
+#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */\r
+#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */\r
+#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */\r
+#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */\r
+#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */\r
+\r
+/******************** Bits definition for DMAMUX_RGSR register **************/\r
+#define DMAMUX_RGSR_OF0_Pos (0U)\r
+#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */\r
+#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */\r
+#define DMAMUX_RGSR_OF1_Pos (1U)\r
+#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */\r
+#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */\r
+#define DMAMUX_RGSR_OF2_Pos (2U)\r
+#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */\r
+#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */\r
+#define DMAMUX_RGSR_OF3_Pos (3U)\r
+#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */\r
+#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */\r
+#define DMAMUX_RGSR_OF4_Pos (4U)\r
+#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */\r
+#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */\r
+#define DMAMUX_RGSR_OF5_Pos (5U)\r
+#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */\r
+#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */\r
+#define DMAMUX_RGSR_OF6_Pos (6U)\r
+#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */\r
+#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */\r
+#define DMAMUX_RGSR_OF7_Pos (7U)\r
+#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */\r
+#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */\r
+\r
+/******************** Bits definition for DMAMUX_RGCFR register **************/\r
+#define DMAMUX_RGCFR_COF0_Pos (0U)\r
+#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */\r
+#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */\r
+#define DMAMUX_RGCFR_COF1_Pos (1U)\r
+#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */\r
+#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */\r
+#define DMAMUX_RGCFR_COF2_Pos (2U)\r
+#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */\r
+#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */\r
+#define DMAMUX_RGCFR_COF3_Pos (3U)\r
+#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */\r
+#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */\r
+#define DMAMUX_RGCFR_COF4_Pos (4U)\r
+#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */\r
+#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */\r
+#define DMAMUX_RGCFR_COF5_Pos (5U)\r
+#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */\r
+#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */\r
+#define DMAMUX_RGCFR_COF6_Pos (6U)\r
+#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */\r
+#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */\r
+#define DMAMUX_RGCFR_COF7_Pos (7U)\r
+#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */\r
+#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* AHB Master DMA2D Controller (DMA2D) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DMA2D_CR register ******************/\r
+\r
+#define DMA2D_CR_START_Pos (0U)\r
+#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */\r
+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */\r
+#define DMA2D_CR_SUSP_Pos (1U)\r
+#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */\r
+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */\r
+#define DMA2D_CR_ABORT_Pos (2U)\r
+#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */\r
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */\r
+#define DMA2D_CR_TEIE_Pos (8U)\r
+#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */\r
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */\r
+#define DMA2D_CR_TCIE_Pos (9U)\r
+#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */\r
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_TWIE_Pos (10U)\r
+#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */\r
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */\r
+#define DMA2D_CR_CAEIE_Pos (11U)\r
+#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */\r
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */\r
+#define DMA2D_CR_CTCIE_Pos (12U)\r
+#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */\r
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_CEIE_Pos (13U)\r
+#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */\r
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */\r
+#define DMA2D_CR_MODE_Pos (16U)\r
+#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */\r
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */\r
+#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */\r
+#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */\r
+\r
+/******************** Bit definition for DMA2D_ISR register *****************/\r
+\r
+#define DMA2D_ISR_TEIF_Pos (0U)\r
+#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */\r
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */\r
+#define DMA2D_ISR_TCIF_Pos (1U)\r
+#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */\r
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_TWIF_Pos (2U)\r
+#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */\r
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_ISR_CAEIF_Pos (3U)\r
+#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */\r
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */\r
+#define DMA2D_ISR_CTCIF_Pos (4U)\r
+#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */\r
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_CEIF_Pos (5U)\r
+#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */\r
+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_IFCR register ****************/\r
+\r
+#define DMA2D_IFCR_CTEIF_Pos (0U)\r
+#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */\r
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFCR_CTCIF_Pos (1U)\r
+#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */\r
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFCR_CTWIF_Pos (2U)\r
+#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */\r
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFCR_CAECIF_Pos (3U)\r
+#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */\r
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFCR_CCTCIF_Pos (4U)\r
+#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */\r
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFCR_CCEIF_Pos (5U)\r
+#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */\r
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_FGMAR register ***************/\r
+\r
+#define DMA2D_FGMAR_MA_Pos (0U)\r
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_FGOR register ****************/\r
+\r
+#define DMA2D_FGOR_LO_Pos (0U)\r
+#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */\r
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_BGMAR register ***************/\r
+\r
+#define DMA2D_BGMAR_MA_Pos (0U)\r
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGOR register ****************/\r
+\r
+#define DMA2D_BGOR_LO_Pos (0U)\r
+#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */\r
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_FGPFCCR register *************/\r
+\r
+#define DMA2D_FGPFCCR_CM_Pos (0U)\r
+#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */\r
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */\r
+#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */\r
+#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */\r
+#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */\r
+#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */\r
+#define DMA2D_FGPFCCR_CCM_Pos (4U)\r
+#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */\r
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */\r
+#define DMA2D_FGPFCCR_START_Pos (5U)\r
+#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */\r
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */\r
+#define DMA2D_FGPFCCR_CS_Pos (8U)\r
+#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */\r
+#define DMA2D_FGPFCCR_AM_Pos (16U)\r
+#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */\r
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */\r
+#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */\r
+#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */\r
+#define DMA2D_FGPFCCR_CSS_Pos (18U)\r
+#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */\r
+#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */\r
+#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */\r
+#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */\r
+#define DMA2D_FGPFCCR_AI_Pos (20U)\r
+#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */\r
+#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */\r
+#define DMA2D_FGPFCCR_RBS_Pos (21U)\r
+#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */\r
+#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */\r
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U)\r
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */\r
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_FGCOLR register **************/\r
+\r
+#define DMA2D_FGCOLR_BLUE_Pos (0U)\r
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */\r
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */\r
+#define DMA2D_FGCOLR_GREEN_Pos (8U)\r
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */\r
+#define DMA2D_FGCOLR_RED_Pos (16U)\r
+#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */\r
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */\r
+\r
+/******************** Bit definition for DMA2D_BGPFCCR register *************/\r
+\r
+#define DMA2D_BGPFCCR_CM_Pos (0U)\r
+#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */\r
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */\r
+#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */\r
+#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */\r
+#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */\r
+#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */\r
+#define DMA2D_BGPFCCR_CCM_Pos (4U)\r
+#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */\r
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */\r
+#define DMA2D_BGPFCCR_START_Pos (5U)\r
+#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */\r
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */\r
+#define DMA2D_BGPFCCR_CS_Pos (8U)\r
+#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */\r
+#define DMA2D_BGPFCCR_AM_Pos (16U)\r
+#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */\r
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */\r
+#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */\r
+#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */\r
+#define DMA2D_BGPFCCR_AI_Pos (20U)\r
+#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */\r
+#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */\r
+#define DMA2D_BGPFCCR_RBS_Pos (21U)\r
+#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */\r
+#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */\r
+#define DMA2D_BGPFCCR_ALPHA_Pos (24U)\r
+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */\r
+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_BGCOLR register **************/\r
+\r
+#define DMA2D_BGCOLR_BLUE_Pos (0U)\r
+#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */\r
+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */\r
+#define DMA2D_BGCOLR_GREEN_Pos (8U)\r
+#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */\r
+#define DMA2D_BGCOLR_RED_Pos (16U)\r
+#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */\r
+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */\r
+\r
+/******************** Bit definition for DMA2D_FGCMAR register **************/\r
+\r
+#define DMA2D_FGCMAR_MA_Pos (0U)\r
+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGCMAR register **************/\r
+\r
+#define DMA2D_BGCMAR_MA_Pos (0U)\r
+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OPFCCR register **************/\r
+\r
+#define DMA2D_OPFCCR_CM_Pos (0U)\r
+#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */\r
+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */\r
+#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */\r
+#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */\r
+#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */\r
+#define DMA2D_OPFCCR_AI_Pos (20U)\r
+#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */\r
+#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */\r
+#define DMA2D_OPFCCR_RBS_Pos (21U)\r
+#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */\r
+#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */\r
+\r
+/******************** Bit definition for DMA2D_OCOLR register ***************/\r
+\r
+/*!<Mode_ARGB8888/RGB888 */\r
+\r
+#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FFU) /*!< Output BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00U) /*!< Output GREEN Value */\r
+#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000U) /*!< Output Red Value */\r
+#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000U) /*!< Output Alpha Channel Value */\r
+\r
+/*!<Mode_RGB565 */\r
+#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0U) /*!< Output GREEN Value */\r
+#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800U) /*!< Output Red Value */\r
+\r
+/*!<Mode_ARGB1555 */\r
+#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0U) /*!< Output GREEN Value */\r
+#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00U) /*!< Output Red Value */\r
+#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000U) /*!< Output Alpha Channel Value */\r
+\r
+/*!<Mode_ARGB4444 */\r
+#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000FU) /*!< Output BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0U) /*!< Output GREEN Value */\r
+#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00U) /*!< Output Red Value */\r
+#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000U) /*!< Output Alpha Channel Value */\r
+\r
+/******************** Bit definition for DMA2D_OMAR register ****************/\r
+\r
+#define DMA2D_OMAR_MA_Pos (0U)\r
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OOR register *****************/\r
+\r
+#define DMA2D_OOR_LO_Pos (0U)\r
+#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */\r
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_NLR register *****************/\r
+\r
+#define DMA2D_NLR_NL_Pos (0U)\r
+#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */\r
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */\r
+#define DMA2D_NLR_PL_Pos (16U)\r
+#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */\r
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */\r
+\r
+/******************** Bit definition for DMA2D_LWR register *****************/\r
+\r
+#define DMA2D_LWR_LW_Pos (0U)\r
+#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */\r
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */\r
+\r
+/******************** Bit definition for DMA2D_AMTCR register ***************/\r
+\r
+#define DMA2D_AMTCR_EN_Pos (0U)\r
+#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */\r
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */\r
+#define DMA2D_AMTCR_DT_Pos (8U)\r
+#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */\r
+\r
+\r
+/******************** Bit definition for DMA2D_FGCLUT register **************/\r
+\r
+/******************** Bit definition for DMA2D_BGCLUT register **************/\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for EXTI_RTSR1 register *******************/\r
+#define EXTI_RTSR1_TR_Pos (0U)\r
+#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */\r
+#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */\r
+#define EXTI_RTSR1_TR0_Pos (0U)\r
+#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR1_TR1_Pos (1U)\r
+#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR1_TR2_Pos (2U)\r
+#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR1_TR3_Pos (3U)\r
+#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR1_TR4_Pos (4U)\r
+#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR1_TR5_Pos (5U)\r
+#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR1_TR6_Pos (6U)\r
+#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR1_TR7_Pos (7U)\r
+#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR1_TR8_Pos (8U)\r
+#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR1_TR9_Pos (9U)\r
+#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR1_TR10_Pos (10U)\r
+#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR1_TR11_Pos (11U)\r
+#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR1_TR12_Pos (12U)\r
+#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR1_TR13_Pos (13U)\r
+#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR1_TR14_Pos (14U)\r
+#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR1_TR15_Pos (15U)\r
+#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR1_TR16_Pos (16U)\r
+#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR1_TR17_Pos (17U)\r
+#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR1_TR18_Pos (18U)\r
+#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR1_TR19_Pos (19U)\r
+#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR1_TR20_Pos (20U)\r
+#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR1_TR21_Pos (21U)\r
+#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */\r
+\r
+/****************** Bit definition for EXTI_FTSR1 register *******************/\r
+#define EXTI_FTSR1_TR_Pos (0U)\r
+#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */\r
+#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */\r
+#define EXTI_FTSR1_TR0_Pos (0U)\r
+#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR1_TR1_Pos (1U)\r
+#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR1_TR2_Pos (2U)\r
+#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR1_TR3_Pos (3U)\r
+#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR1_TR4_Pos (4U)\r
+#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR1_TR5_Pos (5U)\r
+#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR1_TR6_Pos (6U)\r
+#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR1_TR7_Pos (7U)\r
+#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR1_TR8_Pos (8U)\r
+#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR1_TR9_Pos (9U)\r
+#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR1_TR10_Pos (10U)\r
+#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR1_TR11_Pos (11U)\r
+#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR1_TR12_Pos (12U)\r
+#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR1_TR13_Pos (13U)\r
+#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR1_TR14_Pos (14U)\r
+#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR1_TR15_Pos (15U)\r
+#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR1_TR16_Pos (16U)\r
+#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR1_TR17_Pos (17U)\r
+#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR1_TR18_Pos (18U)\r
+#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR1_TR19_Pos (19U)\r
+#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR1_TR20_Pos (20U)\r
+#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR1_TR21_Pos (21U)\r
+#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */\r
+\r
+/****************** Bit definition for EXTI_SWIER1 register ******************/\r
+#define EXTI_SWIER1_SWIER0_Pos (0U)\r
+#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */\r
+#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER1_SWIER1_Pos (1U)\r
+#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */\r
+#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER1_SWIER2_Pos (2U)\r
+#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */\r
+#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER1_SWIER3_Pos (3U)\r
+#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */\r
+#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER1_SWIER4_Pos (4U)\r
+#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */\r
+#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER1_SWIER5_Pos (5U)\r
+#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */\r
+#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER1_SWIER6_Pos (6U)\r
+#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */\r
+#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER1_SWIER7_Pos (7U)\r
+#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */\r
+#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER1_SWIER8_Pos (8U)\r
+#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */\r
+#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER1_SWIER9_Pos (9U)\r
+#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */\r
+#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER1_SWIER10_Pos (10U)\r
+#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */\r
+#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER1_SWIER11_Pos (11U)\r
+#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */\r
+#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER1_SWIER12_Pos (12U)\r
+#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */\r
+#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER1_SWIER13_Pos (13U)\r
+#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */\r
+#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER1_SWIER14_Pos (14U)\r
+#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */\r
+#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER1_SWIER15_Pos (15U)\r
+#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */\r
+#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER1_SWIER16_Pos (16U)\r
+#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */\r
+#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER1_SWIER17_Pos (17U)\r
+#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */\r
+#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER1_SWIER18_Pos (18U)\r
+#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */\r
+#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER1_SWIER19_Pos (19U)\r
+#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */\r
+#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER1_SWIER20_Pos (20U)\r
+#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */\r
+#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER1_SWIER21_Pos (21U)\r
+#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */\r
+#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */\r
+\r
+/****************** Bit definition for EXTI_D3PMR1 register ******************/\r
+#define EXTI_D3PMR1_MR0_Pos (0U)\r
+#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */\r
+#define EXTI_D3PMR1_MR1_Pos (1U)\r
+#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */\r
+#define EXTI_D3PMR1_MR2_Pos (2U)\r
+#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */\r
+#define EXTI_D3PMR1_MR3_Pos (3U)\r
+#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */\r
+#define EXTI_D3PMR1_MR4_Pos (4U)\r
+#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */\r
+#define EXTI_D3PMR1_MR5_Pos (5U)\r
+#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */\r
+#define EXTI_D3PMR1_MR6_Pos (6U)\r
+#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */\r
+#define EXTI_D3PMR1_MR7_Pos (7U)\r
+#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */\r
+#define EXTI_D3PMR1_MR8_Pos (8U)\r
+#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */\r
+#define EXTI_D3PMR1_MR9_Pos (9U)\r
+#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */\r
+#define EXTI_D3PMR1_MR10_Pos (10U)\r
+#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */\r
+#define EXTI_D3PMR1_MR11_Pos (11U)\r
+#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */\r
+#define EXTI_D3PMR1_MR12_Pos (12U)\r
+#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */\r
+#define EXTI_D3PMR1_MR13_Pos (13U)\r
+#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */\r
+#define EXTI_D3PMR1_MR14_Pos (14U)\r
+#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */\r
+#define EXTI_D3PMR1_MR15_Pos (15U)\r
+#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */\r
+#define EXTI_D3PMR1_MR19_Pos (19U)\r
+#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */\r
+#define EXTI_D3PMR1_MR20_Pos (20U)\r
+#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */\r
+#define EXTI_D3PMR1_MR21_Pos (21U)\r
+#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */\r
+#define EXTI_D3PMR1_MR25_Pos (24U)\r
+#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */\r
+#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */\r
+\r
+/******************* Bit definition for EXTI_D3PCR1L register ****************/\r
+#define EXTI_D3PCR1L_PCS0_Pos (0U)\r
+#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */\r
+#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */\r
+#define EXTI_D3PCR1L_PCS1_Pos (2U)\r
+#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */\r
+#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */\r
+#define EXTI_D3PCR1L_PCS2_Pos (4U)\r
+#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */\r
+#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */\r
+#define EXTI_D3PCR1L_PCS3_Pos (6U)\r
+#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */\r
+#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */\r
+#define EXTI_D3PCR1L_PCS4_Pos (8U)\r
+#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */\r
+#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */\r
+#define EXTI_D3PCR1L_PCS5_Pos (10U)\r
+#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */\r
+#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */\r
+#define EXTI_D3PCR1L_PCS6_Pos (12U)\r
+#define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */\r
+#define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */\r
+#define EXTI_D3PCR1L_PCS7_Pos (14U)\r
+#define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */\r
+#define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */\r
+#define EXTI_D3PCR1L_PCS8_Pos (16U)\r
+#define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */\r
+#define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */\r
+#define EXTI_D3PCR1L_PCS9_Pos (18U)\r
+#define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */\r
+#define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */\r
+#define EXTI_D3PCR1L_PCS10_Pos (20U)\r
+#define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */\r
+#define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/\r
+#define EXTI_D3PCR1L_PCS11_Pos (22U)\r
+#define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */\r
+#define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/\r
+#define EXTI_D3PCR1L_PCS12_Pos (24U)\r
+#define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */\r
+#define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/\r
+#define EXTI_D3PCR1L_PCS13_Pos (26U)\r
+#define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */\r
+#define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/\r
+#define EXTI_D3PCR1L_PCS14_Pos (28U)\r
+#define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */\r
+#define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/\r
+#define EXTI_D3PCR1L_PCS15_Pos (30U)\r
+#define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */\r
+#define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/\r
+\r
+/******************* Bit definition for EXTI_D3PCR1H register ****************/\r
+#define EXTI_D3PCR1H_PCS19_Pos (6U)\r
+#define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */\r
+#define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */\r
+#define EXTI_D3PCR1H_PCS20_Pos (8U)\r
+#define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */\r
+#define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */\r
+#define EXTI_D3PCR1H_PCS21_Pos (10U)\r
+#define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */\r
+#define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */\r
+#define EXTI_D3PCR1H_PCS25_Pos (18U)\r
+#define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */\r
+#define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */\r
+\r
+/****************** Bit definition for EXTI_RTSR2 register *******************/\r
+#define EXTI_RTSR2_TR_Pos (17U)\r
+#define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */\r
+#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */\r
+#define EXTI_RTSR2_TR49_Pos (17U)\r
+#define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */\r
+#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */\r
+#define EXTI_RTSR2_TR51_Pos (19U)\r
+#define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */\r
+#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */\r
+\r
+/****************** Bit definition for EXTI_FTSR2 register *******************/\r
+#define EXTI_FTSR2_TR_Pos (17U)\r
+#define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */\r
+#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */\r
+#define EXTI_FTSR2_TR49_Pos (17U)\r
+#define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */\r
+#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */\r
+#define EXTI_FTSR2_TR51_Pos (19U)\r
+#define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */\r
+#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */\r
+\r
+/****************** Bit definition for EXTI_SWIER2 register ******************/\r
+#define EXTI_SWIER2_SWIER49_Pos (17U)\r
+#define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */\r
+#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */\r
+#define EXTI_SWIER2_SWIER51_Pos (19U)\r
+#define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */\r
+#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */\r
+\r
+/****************** Bit definition for EXTI_D3PMR2 register ******************/\r
+#define EXTI_D3PMR2_MR34_Pos (2U)\r
+#define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */\r
+#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */\r
+#define EXTI_D3PMR2_MR35_Pos (3U)\r
+#define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */\r
+#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */\r
+#define EXTI_D3PMR2_MR41_Pos (9U)\r
+#define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */\r
+#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */\r
+#define EXTI_D3PMR2_MR48_Pos (16U)\r
+#define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */\r
+#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */\r
+#define EXTI_D3PMR2_MR49_Pos (17U)\r
+#define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */\r
+#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */\r
+#define EXTI_D3PMR2_MR50_Pos (18U)\r
+#define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */\r
+#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */\r
+#define EXTI_D3PMR2_MR51_Pos (19U)\r
+#define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */\r
+#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */\r
+#define EXTI_D3PMR2_MR52_Pos (20U)\r
+#define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) /*!< 0x00100000 */\r
+#define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk /*!< Pending Mask Event for line 52 */\r
+#define EXTI_D3PMR2_MR53_Pos (21U)\r
+#define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) /*!< 0x00200000 */\r
+#define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk /*!< Pending Mask Event for line 53 */\r
+/******************* Bit definition for EXTI_D3PCR2L register ****************/\r
+#define EXTI_D3PCR2L_PCS34_Pos (4U)\r
+#define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */\r
+#define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */\r
+#define EXTI_D3PCR2L_PCS35_Pos (6U)\r
+#define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */\r
+#define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */\r
+#define EXTI_D3PCR2L_PCS41_Pos (18U)\r
+#define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */\r
+#define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */\r
+\r
+\r
+/******************* Bit definition for EXTI_D3PCR2H register ****************/\r
+#define EXTI_D3PCR2H_PCS48_Pos (0U)\r
+#define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */\r
+#define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */\r
+#define EXTI_D3PCR2H_PCS49_Pos (2U)\r
+#define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */\r
+#define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */\r
+#define EXTI_D3PCR2H_PCS50_Pos (4U)\r
+#define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */\r
+#define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */\r
+#define EXTI_D3PCR2H_PCS51_Pos (6U)\r
+#define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */\r
+#define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */\r
+#define EXTI_D3PCR2H_PCS52_Pos (8U)\r
+#define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) /*!< 0x00000300 */\r
+#define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk /*!< D3 Pending request clear input signal selection on line 52 */\r
+#define EXTI_D3PCR2H_PCS53_Pos (10U)\r
+#define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) /*!< 0x00000C00 */\r
+#define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk /*!< D3 Pending request clear input signal selection on line 53 */\r
+/****************** Bit definition for EXTI_RTSR3 register *******************/\r
+#define EXTI_RTSR3_TR_Pos (18U)\r
+#define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) /*!< 0x00740000 */\r
+#define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */\r
+#define EXTI_RTSR3_TR82_Pos (18U)\r
+#define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */\r
+#define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */\r
+#define EXTI_RTSR3_TR84_Pos (20U)\r
+#define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) /*!< 0x00100000 */\r
+#define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk /*!< Rising trigger event configuration bit of line 84 */\r
+#define EXTI_RTSR3_TR85_Pos (21U)\r
+#define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */\r
+#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */\r
+#define EXTI_RTSR3_TR86_Pos (22U)\r
+#define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */\r
+#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */\r
+\r
+/****************** Bit definition for EXTI_FTSR3 register *******************/\r
+#define EXTI_FTSR3_TR_Pos (18U)\r
+#define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) /*!< 0x00740000 */\r
+#define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */\r
+#define EXTI_FTSR3_TR82_Pos (18U)\r
+#define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */\r
+#define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */\r
+#define EXTI_FTSR3_TR84_Pos (20U)\r
+#define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) /*!< 0x00100000 */\r
+#define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk /*!< Falling trigger event configuration bit of line 84 */\r
+#define EXTI_FTSR3_TR85_Pos (21U)\r
+#define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */\r
+#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */\r
+#define EXTI_FTSR3_TR86_Pos (22U)\r
+#define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */\r
+#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */\r
+\r
+/****************** Bit definition for EXTI_SWIER3 register ******************/\r
+#define EXTI_SWIER3_SWI_Pos (18U)\r
+#define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) /*!< 0x00740000 */\r
+#define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */\r
+#define EXTI_SWIER3_SWIER82_Pos (18U)\r
+#define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */\r
+#define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */\r
+#define EXTI_SWIER3_SWIER84_Pos (20U)\r
+#define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) /*!< 0x00100000 */\r
+#define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk /*!< Software Interrupt on line 84 */\r
+#define EXTI_SWIER3_SWIER85_Pos (21U)\r
+#define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */\r
+#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */\r
+#define EXTI_SWIER3_SWIER86_Pos (22U)\r
+#define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */\r
+#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */\r
+\r
+/******************* Bit definition for EXTI_IMR1 register *******************/\r
+#define EXTI_IMR1_IM_Pos (0U)\r
+#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */\r
+#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */\r
+#define EXTI_IMR1_IM0_Pos (0U)\r
+#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */\r
+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR1_IM1_Pos (1U)\r
+#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */\r
+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR1_IM2_Pos (2U)\r
+#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */\r
+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR1_IM3_Pos (3U)\r
+#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */\r
+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR1_IM4_Pos (4U)\r
+#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */\r
+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR1_IM5_Pos (5U)\r
+#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */\r
+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR1_IM6_Pos (6U)\r
+#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */\r
+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR1_IM7_Pos (7U)\r
+#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */\r
+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR1_IM8_Pos (8U)\r
+#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */\r
+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR1_IM9_Pos (9U)\r
+#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */\r
+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR1_IM10_Pos (10U)\r
+#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */\r
+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR1_IM11_Pos (11U)\r
+#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */\r
+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR1_IM12_Pos (12U)\r
+#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */\r
+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR1_IM13_Pos (13U)\r
+#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */\r
+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR1_IM14_Pos (14U)\r
+#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */\r
+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR1_IM15_Pos (15U)\r
+#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */\r
+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR1_IM16_Pos (16U)\r
+#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */\r
+#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR1_IM17_Pos (17U)\r
+#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */\r
+#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR1_IM18_Pos (18U)\r
+#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */\r
+#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR1_IM19_Pos (19U)\r
+#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */\r
+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR1_IM20_Pos (20U)\r
+#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */\r
+#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR1_IM21_Pos (21U)\r
+#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */\r
+#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR1_IM22_Pos (22U)\r
+#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */\r
+#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR1_IM23_Pos (23U)\r
+#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */\r
+#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */\r
+#define EXTI_IMR1_IM24_Pos (24U)\r
+#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */\r
+#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */\r
+#define EXTI_IMR1_IM25_Pos (25U)\r
+#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */\r
+#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */\r
+#define EXTI_IMR1_IM26_Pos (26U)\r
+#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */\r
+#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */\r
+#define EXTI_IMR1_IM27_Pos (27U)\r
+#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */\r
+#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */\r
+#define EXTI_IMR1_IM28_Pos (28U)\r
+#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */\r
+#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */\r
+#define EXTI_IMR1_IM29_Pos (29U)\r
+#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */\r
+#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */\r
+#define EXTI_IMR1_IM30_Pos (30U)\r
+#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */\r
+#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */\r
+#define EXTI_IMR1_IM31_Pos (31U)\r
+#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */\r
+#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */\r
+\r
+/******************* Bit definition for EXTI_EMR1 register *******************/\r
+#define EXTI_EMR1_EM_Pos (0U)\r
+#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */\r
+#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */\r
+#define EXTI_EMR1_EM0_Pos (0U)\r
+#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */\r
+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */\r
+#define EXTI_EMR1_EM1_Pos (1U)\r
+#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */\r
+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */\r
+#define EXTI_EMR1_EM2_Pos (2U)\r
+#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */\r
+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */\r
+#define EXTI_EMR1_EM3_Pos (3U)\r
+#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */\r
+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */\r
+#define EXTI_EMR1_EM4_Pos (4U)\r
+#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */\r
+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */\r
+#define EXTI_EMR1_EM5_Pos (5U)\r
+#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */\r
+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */\r
+#define EXTI_EMR1_EM6_Pos (6U)\r
+#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */\r
+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */\r
+#define EXTI_EMR1_EM7_Pos (7U)\r
+#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */\r
+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */\r
+#define EXTI_EMR1_EM8_Pos (8U)\r
+#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */\r
+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */\r
+#define EXTI_EMR1_EM9_Pos (9U)\r
+#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */\r
+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */\r
+#define EXTI_EMR1_EM10_Pos (10U)\r
+#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */\r
+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */\r
+#define EXTI_EMR1_EM11_Pos (11U)\r
+#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */\r
+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */\r
+#define EXTI_EMR1_EM12_Pos (12U)\r
+#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */\r
+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */\r
+#define EXTI_EMR1_EM13_Pos (13U)\r
+#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */\r
+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */\r
+#define EXTI_EMR1_EM14_Pos (14U)\r
+#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */\r
+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */\r
+#define EXTI_EMR1_EM15_Pos (15U)\r
+#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */\r
+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */\r
+#define EXTI_EMR1_EM16_Pos (16U)\r
+#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */\r
+#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */\r
+#define EXTI_EMR1_EM17_Pos (17U)\r
+#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */\r
+#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */\r
+#define EXTI_EMR1_EM18_Pos (18U)\r
+#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */\r
+#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */\r
+#define EXTI_EMR1_EM20_Pos (20U)\r
+#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */\r
+#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */\r
+#define EXTI_EMR1_EM21_Pos (21U)\r
+#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */\r
+#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */\r
+#define EXTI_EMR1_EM22_Pos (22U)\r
+#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */\r
+#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */\r
+#define EXTI_EMR1_EM23_Pos (23U)\r
+#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */\r
+#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */\r
+#define EXTI_EMR1_EM24_Pos (24U)\r
+#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */\r
+#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */\r
+#define EXTI_EMR1_EM25_Pos (25U)\r
+#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */\r
+#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */\r
+#define EXTI_EMR1_EM26_Pos (26U)\r
+#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */\r
+#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */\r
+#define EXTI_EMR1_EM27_Pos (27U)\r
+#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */\r
+#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */\r
+#define EXTI_EMR1_EM28_Pos (28U)\r
+#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */\r
+#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */\r
+#define EXTI_EMR1_EM29_Pos (29U)\r
+#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */\r
+#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */\r
+#define EXTI_EMR1_EM30_Pos (30U)\r
+#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */\r
+#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */\r
+#define EXTI_EMR1_EM31_Pos (31U)\r
+#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */\r
+#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */\r
+\r
+/******************* Bit definition for EXTI_PR1 register ********************/\r
+#define EXTI_PR1_PR_Pos (0U)\r
+#define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */\r
+#define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */\r
+#define EXTI_PR1_PR0_Pos (0U)\r
+#define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */\r
+#define EXTI_PR1_PR1_Pos (1U)\r
+#define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */\r
+#define EXTI_PR1_PR2_Pos (2U)\r
+#define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */\r
+#define EXTI_PR1_PR3_Pos (3U)\r
+#define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */\r
+#define EXTI_PR1_PR4_Pos (4U)\r
+#define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */\r
+#define EXTI_PR1_PR5_Pos (5U)\r
+#define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */\r
+#define EXTI_PR1_PR6_Pos (6U)\r
+#define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */\r
+#define EXTI_PR1_PR7_Pos (7U)\r
+#define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */\r
+#define EXTI_PR1_PR8_Pos (8U)\r
+#define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */\r
+#define EXTI_PR1_PR9_Pos (9U)\r
+#define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */\r
+#define EXTI_PR1_PR10_Pos (10U)\r
+#define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */\r
+#define EXTI_PR1_PR11_Pos (11U)\r
+#define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */\r
+#define EXTI_PR1_PR12_Pos (12U)\r
+#define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */\r
+#define EXTI_PR1_PR13_Pos (13U)\r
+#define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */\r
+#define EXTI_PR1_PR14_Pos (14U)\r
+#define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */\r
+#define EXTI_PR1_PR15_Pos (15U)\r
+#define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */\r
+#define EXTI_PR1_PR16_Pos (16U)\r
+#define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */\r
+#define EXTI_PR1_PR17_Pos (17U)\r
+#define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */\r
+#define EXTI_PR1_PR18_Pos (18U)\r
+#define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */\r
+#define EXTI_PR1_PR19_Pos (19U)\r
+#define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */\r
+#define EXTI_PR1_PR20_Pos (20U)\r
+#define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */\r
+#define EXTI_PR1_PR21_Pos (21U)\r
+#define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */\r
+\r
+/******************* Bit definition for EXTI_IMR2 register *******************/\r
+#define EXTI_IMR2_IM_Pos (0U)\r
+#define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFFDFFF */\r
+#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */\r
+#define EXTI_IMR2_IM32_Pos (0U)\r
+#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */\r
+#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */\r
+#define EXTI_IMR2_IM33_Pos (1U)\r
+#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */\r
+#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */\r
+#define EXTI_IMR2_IM34_Pos (2U)\r
+#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */\r
+#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */\r
+#define EXTI_IMR2_IM35_Pos (3U)\r
+#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */\r
+#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */\r
+#define EXTI_IMR2_IM36_Pos (4U)\r
+#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */\r
+#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */\r
+#define EXTI_IMR2_IM37_Pos (5U)\r
+#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */\r
+#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */\r
+#define EXTI_IMR2_IM38_Pos (6U)\r
+#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */\r
+#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */\r
+#define EXTI_IMR2_IM39_Pos (7U)\r
+#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */\r
+#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */\r
+#define EXTI_IMR2_IM40_Pos (8U)\r
+#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */\r
+#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */\r
+#define EXTI_IMR2_IM41_Pos (9U)\r
+#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */\r
+#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */\r
+#define EXTI_IMR2_IM42_Pos (10U)\r
+#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */\r
+#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */\r
+#define EXTI_IMR2_IM43_Pos (11U)\r
+#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */\r
+#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */\r
+#define EXTI_IMR2_IM44_Pos (12U)\r
+#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */\r
+#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */\r
+#define EXTI_IMR2_IM46_Pos (14U)\r
+#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */\r
+#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */\r
+#define EXTI_IMR2_IM47_Pos (15U)\r
+#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */\r
+#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */\r
+#define EXTI_IMR2_IM48_Pos (16U)\r
+#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */\r
+#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */\r
+#define EXTI_IMR2_IM49_Pos (17U)\r
+#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */\r
+#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */\r
+#define EXTI_IMR2_IM50_Pos (18U)\r
+#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */\r
+#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */\r
+#define EXTI_IMR2_IM51_Pos (19U)\r
+#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */\r
+#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */\r
+#define EXTI_IMR2_IM52_Pos (20U)\r
+#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */\r
+#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */\r
+#define EXTI_IMR2_IM53_Pos (21U)\r
+#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */\r
+#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */\r
+#define EXTI_IMR2_IM54_Pos (22U)\r
+#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */\r
+#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */\r
+#define EXTI_IMR2_IM55_Pos (23U)\r
+#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */\r
+#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */\r
+#define EXTI_IMR2_IM56_Pos (24U)\r
+#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */\r
+#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */\r
+#define EXTI_IMR2_IM57_Pos (25U)\r
+#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */\r
+#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */\r
+#define EXTI_IMR2_IM58_Pos (26U)\r
+#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */\r
+#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */\r
+#define EXTI_IMR2_IM59_Pos (27U)\r
+#define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */\r
+#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */\r
+#define EXTI_IMR2_IM60_Pos (28U)\r
+#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */\r
+#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */\r
+#define EXTI_IMR2_IM61_Pos (29U)\r
+#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */\r
+#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */\r
+#define EXTI_IMR2_IM62_Pos (30U)\r
+#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */\r
+#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */\r
+#define EXTI_IMR2_IM63_Pos (31U)\r
+#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */\r
+#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */\r
+\r
+/******************* Bit definition for EXTI_EMR2 register *******************/\r
+#define EXTI_EMR2_EM_Pos (0U)\r
+#define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFFDFFF */\r
+#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */\r
+#define EXTI_EMR2_EM32_Pos (0U)\r
+#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */\r
+#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/\r
+#define EXTI_EMR2_EM33_Pos (1U)\r
+#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */\r
+#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/\r
+#define EXTI_EMR2_EM34_Pos (2U)\r
+#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */\r
+#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/\r
+#define EXTI_EMR2_EM35_Pos (3U)\r
+#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */\r
+#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/\r
+#define EXTI_EMR2_EM36_Pos (4U)\r
+#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */\r
+#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/\r
+#define EXTI_EMR2_EM37_Pos (5U)\r
+#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */\r
+#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/\r
+#define EXTI_EMR2_EM38_Pos (6U)\r
+#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */\r
+#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/\r
+#define EXTI_EMR2_EM39_Pos (7U)\r
+#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */\r
+#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/\r
+#define EXTI_EMR2_EM40_Pos (8U)\r
+#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */\r
+#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/\r
+#define EXTI_EMR2_EM41_Pos (9U)\r
+#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */\r
+#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/\r
+#define EXTI_EMR2_EM42_Pos (10U)\r
+#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */\r
+#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */\r
+#define EXTI_EMR2_EM43_Pos (11U)\r
+#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */\r
+#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */\r
+#define EXTI_EMR2_EM44_Pos (12U)\r
+#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */\r
+#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */\r
+#define EXTI_EMR2_EM46_Pos (14U)\r
+#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */\r
+#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */\r
+#define EXTI_EMR2_EM47_Pos (15U)\r
+#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */\r
+#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */\r
+#define EXTI_EMR2_EM48_Pos (16U)\r
+#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */\r
+#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */\r
+#define EXTI_EMR2_EM49_Pos (17U)\r
+#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */\r
+#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */\r
+#define EXTI_EMR2_EM50_Pos (18U)\r
+#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */\r
+#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */\r
+#define EXTI_EMR2_EM51_Pos (19U)\r
+#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */\r
+#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */\r
+#define EXTI_EMR2_EM52_Pos (20U)\r
+#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */\r
+#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */\r
+#define EXTI_EMR2_EM53_Pos (21U)\r
+#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */\r
+#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */\r
+#define EXTI_EMR2_EM54_Pos (22U)\r
+#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */\r
+#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */\r
+#define EXTI_EMR2_EM55_Pos (23U)\r
+#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */\r
+#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */\r
+#define EXTI_EMR2_EM56_Pos (24U)\r
+#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */\r
+#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */\r
+#define EXTI_EMR2_EM57_Pos (25U)\r
+#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */\r
+#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */\r
+#define EXTI_EMR2_EM58_Pos (26U)\r
+#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */\r
+#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */\r
+#define EXTI_EMR2_EM59_Pos (27U)\r
+#define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */\r
+#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */\r
+#define EXTI_EMR2_EM60_Pos (28U)\r
+#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */\r
+#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */\r
+#define EXTI_EMR2_EM61_Pos (29U)\r
+#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */\r
+#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */\r
+#define EXTI_EMR2_EM62_Pos (30U)\r
+#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */\r
+#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */\r
+#define EXTI_EMR2_EM63_Pos (31U)\r
+#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */\r
+#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */\r
+\r
+/******************* Bit definition for EXTI_PR2 register ********************/\r
+#define EXTI_PR2_PR_Pos (17U)\r
+#define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */\r
+#define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */\r
+#define EXTI_PR2_PR49_Pos (17U)\r
+#define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */\r
+#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */\r
+#define EXTI_PR2_PR51_Pos (19U)\r
+#define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */\r
+#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */\r
+\r
+/******************* Bit definition for EXTI_IMR3 register *******************/\r
+#define EXTI_IMR3_IM_Pos (0U)\r
+#define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) /*!< 0x00F5FFFF */\r
+#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */\r
+#define EXTI_IMR3_IM64_Pos (0U)\r
+#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */\r
+#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */\r
+#define EXTI_IMR3_IM65_Pos (1U)\r
+#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */\r
+#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */\r
+#define EXTI_IMR3_IM66_Pos (2U)\r
+#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */\r
+#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */\r
+#define EXTI_IMR3_IM67_Pos (3U)\r
+#define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */\r
+#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */\r
+#define EXTI_IMR3_IM68_Pos (4U)\r
+#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */\r
+#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */\r
+#define EXTI_IMR3_IM69_Pos (5U)\r
+#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */\r
+#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */\r
+#define EXTI_IMR3_IM70_Pos (6U)\r
+#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */\r
+#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */\r
+#define EXTI_IMR3_IM71_Pos (7U)\r
+#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */\r
+#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */\r
+#define EXTI_IMR3_IM72_Pos (8U)\r
+#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */\r
+#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */\r
+#define EXTI_IMR3_IM73_Pos (9U)\r
+#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */\r
+#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */\r
+#define EXTI_IMR3_IM74_Pos (10U)\r
+#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */\r
+#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */\r
+#define EXTI_IMR3_IM75_Pos (11U)\r
+#define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */\r
+#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */\r
+#define EXTI_IMR3_IM76_Pos (12U)\r
+#define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */\r
+#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */\r
+#define EXTI_IMR3_IM77_Pos (13U)\r
+#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */\r
+#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */\r
+#define EXTI_IMR3_IM78_Pos (14U)\r
+#define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */\r
+#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */\r
+#define EXTI_IMR3_IM79_Pos (15U)\r
+#define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */\r
+#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */\r
+#define EXTI_IMR3_IM80_Pos (16U)\r
+#define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */\r
+#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */\r
+#define EXTI_IMR3_IM82_Pos (18U)\r
+#define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */\r
+#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */\r
+#define EXTI_IMR3_IM84_Pos (20U)\r
+#define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */\r
+#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */\r
+#define EXTI_IMR3_IM85_Pos (21U)\r
+#define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */\r
+#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */\r
+#define EXTI_IMR3_IM86_Pos (22U)\r
+#define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */\r
+#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */\r
+#define EXTI_IMR3_IM87_Pos (23U)\r
+#define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */\r
+#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */\r
+\r
+\r
+/******************* Bit definition for EXTI_EMR3 register *******************/\r
+#define EXTI_EMR3_EM_Pos (0U)\r
+#define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) /*!< 0x00F5FFFF */\r
+#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */\r
+#define EXTI_EMR3_EM64_Pos (0U)\r
+#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */\r
+#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/\r
+#define EXTI_EMR3_EM65_Pos (1U)\r
+#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */\r
+#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/\r
+#define EXTI_EMR3_EM66_Pos (2U)\r
+#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */\r
+#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/\r
+#define EXTI_EMR3_EM67_Pos (3U)\r
+#define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */\r
+#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/\r
+#define EXTI_EMR3_EM68_Pos (4U)\r
+#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */\r
+#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/\r
+#define EXTI_EMR3_EM69_Pos (5U)\r
+#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */\r
+#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/\r
+#define EXTI_EMR3_EM70_Pos (6U)\r
+#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */\r
+#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/\r
+#define EXTI_EMR3_EM71_Pos (7U)\r
+#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */\r
+#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/\r
+#define EXTI_EMR3_EM72_Pos (8U)\r
+#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */\r
+#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/\r
+#define EXTI_EMR3_EM73_Pos (9U)\r
+#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */\r
+#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/\r
+#define EXTI_EMR3_EM74_Pos (10U)\r
+#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */\r
+#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */\r
+#define EXTI_EMR3_EM75_Pos (11U)\r
+#define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */\r
+#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */\r
+#define EXTI_EMR3_EM76_Pos (12U)\r
+#define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */\r
+#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */\r
+#define EXTI_EMR3_EM77_Pos (13U)\r
+#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */\r
+#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */\r
+#define EXTI_EMR3_EM78_Pos (14U)\r
+#define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */\r
+#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */\r
+#define EXTI_EMR3_EM79_Pos (15U)\r
+#define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */\r
+#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */\r
+#define EXTI_EMR3_EM80_Pos (16U)\r
+#define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */\r
+#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */\r
+#define EXTI_EMR3_EM81_Pos (17U)\r
+#define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */\r
+#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */\r
+#define EXTI_EMR3_EM82_Pos (18U)\r
+#define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */\r
+#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */\r
+#define EXTI_EMR3_EM84_Pos (20U)\r
+#define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */\r
+#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */\r
+#define EXTI_EMR3_EM85_Pos (21U)\r
+#define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */\r
+#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */\r
+#define EXTI_EMR3_EM86_Pos (22U)\r
+#define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */\r
+#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */\r
+#define EXTI_EMR3_EM87_Pos (23U)\r
+#define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */\r
+#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */\r
+\r
+/******************* Bit definition for EXTI_PR3 register ********************/\r
+#define EXTI_PR3_PR_Pos (18U)\r
+#define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) /*!< 0x00740000 */\r
+#define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */\r
+#define EXTI_PR3_PR82_Pos (18U)\r
+#define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */\r
+#define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */\r
+#define EXTI_PR3_PR84_Pos (20U)\r
+#define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) /*!< 0x00100000 */\r
+#define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk /*!< Pending bit for line 84 */\r
+#define EXTI_PR3_PR85_Pos (21U)\r
+#define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */\r
+#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */\r
+#define EXTI_PR3_PR86_Pos (22U)\r
+#define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) /*!< 0x00400000 */\r
+#define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk /*!< Pending bit for line 86 */\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+* @brief FLASH Total Sectors Number\r
+*/\r
+#define FLASH_SECTOR_TOTAL 8U\r
+#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U\r
+\r
+/******************* Bits definition for FLASH_ACR register **********************/\r
+#define FLASH_ACR_LATENCY_Pos (0U)\r
+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */\r
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk\r
+#define FLASH_ACR_LATENCY_0WS (0x00000000UL)\r
+#define FLASH_ACR_LATENCY_1WS (0x00000001UL)\r
+#define FLASH_ACR_LATENCY_2WS (0x00000002UL)\r
+#define FLASH_ACR_LATENCY_3WS (0x00000003UL)\r
+#define FLASH_ACR_LATENCY_4WS (0x00000004UL)\r
+#define FLASH_ACR_LATENCY_5WS (0x00000005UL)\r
+#define FLASH_ACR_LATENCY_6WS (0x00000006UL)\r
+#define FLASH_ACR_LATENCY_7WS (0x00000007UL)\r
+#define FLASH_ACR_LATENCY_8WS (0x00000008UL)\r
+#define FLASH_ACR_LATENCY_9WS (0x00000009UL)\r
+#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)\r
+#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)\r
+#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)\r
+#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)\r
+#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)\r
+#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)\r
+#define FLASH_ACR_WRHIGHFREQ_Pos (4U)\r
+#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */\r
+#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk\r
+#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */\r
+#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */\r
+\r
+/******************* Bits definition for FLASH_CR register ***********************/\r
+#define FLASH_CR_LOCK_Pos (0U)\r
+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */\r
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk\r
+#define FLASH_CR_PG_Pos (1U)\r
+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */\r
+#define FLASH_CR_PG FLASH_CR_PG_Msk\r
+#define FLASH_CR_SER_Pos (2U)\r
+#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */\r
+#define FLASH_CR_SER FLASH_CR_SER_Msk\r
+#define FLASH_CR_BER_Pos (3U)\r
+#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */\r
+#define FLASH_CR_BER FLASH_CR_BER_Msk\r
+#define FLASH_CR_PSIZE_Pos (4U)\r
+#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */\r
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk\r
+#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */\r
+#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */\r
+#define FLASH_CR_FW_Pos (6U)\r
+#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */\r
+#define FLASH_CR_FW FLASH_CR_FW_Msk\r
+#define FLASH_CR_START_Pos (7U)\r
+#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */\r
+#define FLASH_CR_START FLASH_CR_START_Msk\r
+#define FLASH_CR_SNB_Pos (8U)\r
+#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */\r
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk\r
+#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */\r
+#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */\r
+#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */\r
+#define FLASH_CR_CRC_EN_Pos (15U)\r
+#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */\r
+#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk\r
+#define FLASH_CR_EOPIE_Pos (16U)\r
+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */\r
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk\r
+#define FLASH_CR_WRPERRIE_Pos (17U)\r
+#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */\r
+#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk\r
+#define FLASH_CR_PGSERRIE_Pos (18U)\r
+#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */\r
+#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk\r
+#define FLASH_CR_STRBERRIE_Pos (19U)\r
+#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */\r
+#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk\r
+#define FLASH_CR_INCERRIE_Pos (21U)\r
+#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */\r
+#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk\r
+#define FLASH_CR_OPERRIE_Pos (22U)\r
+#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */\r
+#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk\r
+#define FLASH_CR_RDPERRIE_Pos (23U)\r
+#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */\r
+#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk\r
+#define FLASH_CR_RDSERRIE_Pos (24U)\r
+#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */\r
+#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk\r
+#define FLASH_CR_SNECCERRIE_Pos (25U)\r
+#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */\r
+#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk\r
+#define FLASH_CR_DBECCERRIE_Pos (26U)\r
+#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */\r
+#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk\r
+#define FLASH_CR_CRCENDIE_Pos (27U)\r
+#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */\r
+#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk\r
+#define FLASH_CR_CRCRDERRIE_Pos (28U)\r
+#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */\r
+#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk\r
+\r
+/******************* Bits definition for FLASH_SR register ***********************/\r
+#define FLASH_SR_BSY_Pos (0U)\r
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */\r
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk\r
+#define FLASH_SR_WBNE_Pos (1U)\r
+#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */\r
+#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk\r
+#define FLASH_SR_QW_Pos (2U)\r
+#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */\r
+#define FLASH_SR_QW FLASH_SR_QW_Msk\r
+#define FLASH_SR_CRC_BUSY_Pos (3U)\r
+#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */\r
+#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk\r
+#define FLASH_SR_EOP_Pos (16U)\r
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */\r
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk\r
+#define FLASH_SR_WRPERR_Pos (17U)\r
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */\r
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk\r
+#define FLASH_SR_PGSERR_Pos (18U)\r
+#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */\r
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk\r
+#define FLASH_SR_STRBERR_Pos (19U)\r
+#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */\r
+#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk\r
+#define FLASH_SR_INCERR_Pos (21U)\r
+#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */\r
+#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk\r
+#define FLASH_SR_OPERR_Pos (22U)\r
+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */\r
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk\r
+#define FLASH_SR_RDPERR_Pos (23U)\r
+#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */\r
+#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk\r
+#define FLASH_SR_RDSERR_Pos (24U)\r
+#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */\r
+#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk\r
+#define FLASH_SR_SNECCERR_Pos (25U)\r
+#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */\r
+#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk\r
+#define FLASH_SR_DBECCERR_Pos (26U)\r
+#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */\r
+#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk\r
+#define FLASH_SR_CRCEND_Pos (27U)\r
+#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */\r
+#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk\r
+#define FLASH_SR_CRCRDERR_Pos (28U)\r
+#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */\r
+#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk\r
+\r
+/******************* Bits definition for FLASH_CCR register *******************/\r
+#define FLASH_CCR_CLR_EOP_Pos (16U)\r
+#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */\r
+#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk\r
+#define FLASH_CCR_CLR_WRPERR_Pos (17U)\r
+#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */\r
+#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk\r
+#define FLASH_CCR_CLR_PGSERR_Pos (18U)\r
+#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */\r
+#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk\r
+#define FLASH_CCR_CLR_STRBERR_Pos (19U)\r
+#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */\r
+#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk\r
+#define FLASH_CCR_CLR_INCERR_Pos (21U)\r
+#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */\r
+#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk\r
+#define FLASH_CCR_CLR_OPERR_Pos (22U)\r
+#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */\r
+#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk\r
+#define FLASH_CCR_CLR_RDPERR_Pos (23U)\r
+#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */\r
+#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk\r
+#define FLASH_CCR_CLR_RDSERR_Pos (24U)\r
+#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */\r
+#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk\r
+#define FLASH_CCR_CLR_SNECCERR_Pos (25U)\r
+#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */\r
+#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk\r
+#define FLASH_CCR_CLR_DBECCERR_Pos (26U)\r
+#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */\r
+#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk\r
+#define FLASH_CCR_CLR_CRCEND_Pos (27U)\r
+#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */\r
+#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk\r
+#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)\r
+#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */\r
+#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk\r
+\r
+/******************* Bits definition for FLASH_OPTCR register *******************/\r
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)\r
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */\r
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk\r
+#define FLASH_OPTCR_OPTSTART_Pos (1U)\r
+#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */\r
+#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk\r
+#define FLASH_OPTCR_MER_Pos (4U)\r
+#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */\r
+#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk\r
+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)\r
+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */\r
+#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk\r
+#define FLASH_OPTCR_SWAP_BANK_Pos (31U)\r
+#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */\r
+#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk\r
+\r
+/******************* Bits definition for FLASH_OPTSR register ***************/\r
+#define FLASH_OPTSR_OPT_BUSY_Pos (0U)\r
+#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */\r
+#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk\r
+#define FLASH_OPTSR_BOR_LEV_Pos (2U)\r
+#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */\r
+#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk\r
+#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */\r
+#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */\r
+#define FLASH_OPTSR_IWDG1_SW_Pos (4U)\r
+#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */\r
+#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk\r
+#define FLASH_OPTSR_IWDG2_SW_Pos (5U)\r
+#define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */\r
+#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk\r
+#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)\r
+#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */\r
+#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk\r
+#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)\r
+#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */\r
+#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk\r
+#define FLASH_OPTSR_RDP_Pos (8U)\r
+#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */\r
+#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk\r
+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)\r
+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */\r
+#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk\r
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)\r
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */\r
+#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk\r
+#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)\r
+#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */\r
+#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk\r
+#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */\r
+#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */\r
+#define FLASH_OPTSR_SECURITY_Pos (21U)\r
+#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */\r
+#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk\r
+#define FLASH_OPTSR_BCM4_Pos (22U)\r
+#define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos) /*!< 0x00400000 */\r
+#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk\r
+#define FLASH_OPTSR_BCM7_Pos (23U)\r
+#define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos) /*!< 0x00800000 */\r
+#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk\r
+#define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)\r
+#define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */\r
+#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk\r
+#define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)\r
+#define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */\r
+#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk\r
+#define FLASH_OPTSR_IO_HSLV_Pos (29U)\r
+#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */\r
+#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk\r
+#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)\r
+#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\r
+#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk\r
+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)\r
+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */\r
+#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk\r
+\r
+/******************* Bits definition for FLASH_OPTCCR register *******************/\r
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)\r
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\r
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk\r
+\r
+/******************* Bits definition for FLASH_PRAR register *********************/\r
+#define FLASH_PRAR_PROT_AREA_START_Pos (0U)\r
+#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */\r
+#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk\r
+#define FLASH_PRAR_PROT_AREA_END_Pos (16U)\r
+#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */\r
+#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk\r
+#define FLASH_PRAR_DMEP_Pos (31U)\r
+#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */\r
+#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk\r
+\r
+/******************* Bits definition for FLASH_SCAR register *********************/\r
+#define FLASH_SCAR_SEC_AREA_START_Pos (0U)\r
+#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */\r
+#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk\r
+#define FLASH_SCAR_SEC_AREA_END_Pos (16U)\r
+#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */\r
+#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk\r
+#define FLASH_SCAR_DMES_Pos (31U)\r
+#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */\r
+#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk\r
+\r
+/******************* Bits definition for FLASH_WPSN register *********************/\r
+#define FLASH_WPSN_WRPSN_Pos (0U)\r
+#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */\r
+#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk\r
+\r
+/******************* Bits definition for FLASH_BOOT7_CUR register ****************/\r
+#define FLASH_BOOT7_BCM7_ADD0_Pos (0U)\r
+#define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk\r
+#define FLASH_BOOT7_BCM7_ADD1_Pos (16U)\r
+#define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */\r
+#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk\r
+\r
+/******************* Bits definition for FLASH_BOOT4 register ********************/\r
+#define FLASH_BOOT4_BCM4_ADD0_Pos (0U)\r
+#define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk\r
+#define FLASH_BOOT4_BCM4_ADD1_Pos (16U)\r
+#define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */\r
+#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk\r
+\r
+/******************* Bits definition for FLASH_CRCCR register ********************/\r
+#define FLASH_CRCCR_CRC_SECT_Pos (0U)\r
+#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */\r
+#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk\r
+#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)\r
+#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */\r
+#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk\r
+#define FLASH_CRCCR_ADD_SECT_Pos (9U)\r
+#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */\r
+#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk\r
+#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)\r
+#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */\r
+#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk\r
+#define FLASH_CRCCR_START_CRC_Pos (16U)\r
+#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */\r
+#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk\r
+#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)\r
+#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */\r
+#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk\r
+#define FLASH_CRCCR_CRC_BURST_Pos (20U)\r
+#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */\r
+#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk\r
+#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */\r
+#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */\r
+#define FLASH_CRCCR_ALL_BANK_Pos (22U)\r
+#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */\r
+#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk\r
+\r
+/******************* Bits definition for FLASH_CRCSADD register ****************/\r
+#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)\r
+#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk\r
+\r
+/******************* Bits definition for FLASH_CRCEADD register ****************/\r
+#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)\r
+#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk\r
+\r
+/******************* Bits definition for FLASH_CRCDATA register ***************/\r
+#define FLASH_CRCDATA_CRC_DATA_Pos (0U)\r
+#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk\r
+\r
+/******************* Bits definition for FLASH_ECC_FA register *******************/\r
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)\r
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */\r
+#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FMC_BCR1 register *******************/\r
+#define FMC_BCR1_CCLKEN_Pos (20U)\r
+#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */\r
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */\r
+#define FMC_BCR1_WFDIS_Pos (21U)\r
+#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */\r
+#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */\r
+\r
+#define FMC_BCR1_BMAP_Pos (24U)\r
+#define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */\r
+#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */\r
+#define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */\r
+#define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */\r
+\r
+#define FMC_BCR1_FMCEN_Pos (31U)\r
+#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */\r
+#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */\r
+/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/\r
+#define FMC_BCRx_MBKEN_Pos (0U)\r
+#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCRx_MUXEN_Pos (1U)\r
+#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCRx_MTYP_Pos (2U)\r
+#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */\r
+\r
+#define FMC_BCRx_MWID_Pos (4U)\r
+#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */\r
+\r
+#define FMC_BCRx_FACCEN_Pos (6U)\r
+#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCRx_BURSTEN_Pos (8U)\r
+#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCRx_WAITPOL_Pos (9U)\r
+#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCRx_WAITCFG_Pos (11U)\r
+#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCRx_WREN_Pos (12U)\r
+#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCRx_WAITEN_Pos (13U)\r
+#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCRx_EXTMOD_Pos (14U)\r
+#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCRx_ASYNCWAIT_Pos (15U)\r
+#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+\r
+#define FMC_BCRx_CPSIZE_Pos (16U)\r
+#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */\r
+#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */\r
+\r
+#define FMC_BCRx_CBURSTRW_Pos (19U)\r
+#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/\r
+#define FMC_BTRx_ADDSET_Pos (0U)\r
+#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */\r
+\r
+#define FMC_BTRx_ADDHLD_Pos (4U)\r
+#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */\r
+\r
+#define FMC_BTRx_DATAST_Pos (8U)\r
+#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */\r
+\r
+#define FMC_BTRx_BUSTURN_Pos (16U)\r
+#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */\r
+\r
+#define FMC_BTRx_CLKDIV_Pos (20U)\r
+#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */\r
+\r
+#define FMC_BTRx_DATLAT_Pos (24U)\r
+#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */\r
+\r
+#define FMC_BTRx_ACCMOD_Pos (28U)\r
+#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/\r
+#define FMC_BWTRx_ADDSET_Pos (0U)\r
+#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */\r
+\r
+#define FMC_BWTRx_ADDHLD_Pos (4U)\r
+#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */\r
+\r
+#define FMC_BWTRx_DATAST_Pos (8U)\r
+#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */\r
+\r
+#define FMC_BWTRx_BUSTURN_Pos (16U)\r
+#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */\r
+\r
+#define FMC_BWTRx_ACCMOD_Pos (28U)\r
+#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_PCR register *******************/\r
+#define FMC_PCR_PWAITEN_Pos (1U)\r
+#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */\r
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */\r
+#define FMC_PCR_PBKEN_Pos (2U)\r
+#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */\r
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */\r
+\r
+#define FMC_PCR_PWID_Pos (4U)\r
+#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */\r
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */\r
+#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */\r
+\r
+#define FMC_PCR_ECCEN_Pos (6U)\r
+#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */\r
+\r
+#define FMC_PCR_TCLR_Pos (9U)\r
+#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */\r
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */\r
+#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */\r
+#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */\r
+#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */\r
+\r
+#define FMC_PCR_TAR_Pos (13U)\r
+#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */\r
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */\r
+#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */\r
+#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */\r
+#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */\r
+\r
+#define FMC_PCR_ECCPS_Pos (17U)\r
+#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */\r
+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */\r
+#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */\r
+#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */\r
+#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */\r
+\r
+/******************* Bit definition for FMC_SR register *******************/\r
+#define FMC_SR_IRS_Pos (0U)\r
+#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */\r
+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */\r
+#define FMC_SR_ILS_Pos (1U)\r
+#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */\r
+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */\r
+#define FMC_SR_IFS_Pos (2U)\r
+#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */\r
+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */\r
+#define FMC_SR_IREN_Pos (3U)\r
+#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */\r
+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR_ILEN_Pos (4U)\r
+#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */\r
+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR_IFEN_Pos (5U)\r
+#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */\r
+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR_FEMPT_Pos (6U)\r
+#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */\r
+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FMC_PMEM register ******************/\r
+#define FMC_PMEM_MEMSET_Pos (0U)\r
+#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */\r
+#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */\r
+#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */\r
+#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */\r
+#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */\r
+#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */\r
+#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */\r
+#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */\r
+#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */\r
+#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */\r
+\r
+#define FMC_PMEM_MEMWAIT_Pos (8U)\r
+#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */\r
+#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */\r
+#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */\r
+#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */\r
+#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */\r
+#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */\r
+#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */\r
+#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */\r
+#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */\r
+#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */\r
+\r
+#define FMC_PMEM_MEMHOLD_Pos (16U)\r
+#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */\r
+#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */\r
+#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */\r
+#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */\r
+#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */\r
+#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */\r
+#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */\r
+#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */\r
+#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */\r
+#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */\r
+\r
+#define FMC_PMEM_MEMHIZ_Pos (24U)\r
+#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */\r
+#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */\r
+#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */\r
+#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */\r
+#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */\r
+#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */\r
+#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */\r
+#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */\r
+#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */\r
+#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for FMC_PATT register ******************/\r
+#define FMC_PATT_ATTSET_Pos (0U)\r
+#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */\r
+#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */\r
+#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */\r
+#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */\r
+#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */\r
+#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */\r
+#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */\r
+#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */\r
+#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */\r
+#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */\r
+\r
+#define FMC_PATT_ATTWAIT_Pos (8U)\r
+#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */\r
+#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */\r
+#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */\r
+#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */\r
+#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */\r
+#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */\r
+#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */\r
+#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */\r
+#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */\r
+#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */\r
+\r
+#define FMC_PATT_ATTHOLD_Pos (16U)\r
+#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */\r
+#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */\r
+#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */\r
+#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */\r
+#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */\r
+#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */\r
+#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */\r
+#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */\r
+#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */\r
+#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */\r
+\r
+#define FMC_PATT_ATTHIZ_Pos (24U)\r
+#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */\r
+#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */\r
+#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */\r
+#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */\r
+#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */\r
+#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */\r
+#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */\r
+#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */\r
+#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */\r
+#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for FMC_ECCR3 register ******************/\r
+#define FMC_ECCR3_ECC3_Pos (0U)\r
+#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */\r
+#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/\r
+#define FMC_SDCRx_NC_Pos (0U)\r
+#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */\r
+#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */\r
+\r
+#define FMC_SDCRx_NR_Pos (2U)\r
+#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */\r
+#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */\r
+#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */\r
+\r
+#define FMC_SDCRx_MWID_Pos (4U)\r
+#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */\r
+\r
+#define FMC_SDCRx_NB_Pos (6U)\r
+#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */\r
+\r
+#define FMC_SDCRx_CAS_Pos (7U)\r
+#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */\r
+#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */\r
+\r
+#define FMC_SDCRx_WP_Pos (9U)\r
+#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */\r
+#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */\r
+\r
+#define FMC_SDCRx_SDCLK_Pos (10U)\r
+#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */\r
+#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */\r
+#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */\r
+#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */\r
+\r
+#define FMC_SDCRx_RBURST_Pos (12U)\r
+#define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */\r
+#define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */\r
+\r
+#define FMC_SDCRx_RPIPE_Pos (13U)\r
+#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */\r
+#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */\r
+#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */\r
+#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */\r
+\r
+/****************** Bit definition for FMC_SDTRx(1,2) register ******************/\r
+#define FMC_SDTRx_TMRD_Pos (0U)\r
+#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */\r
+#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */\r
+#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */\r
+#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */\r
+#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */\r
+\r
+#define FMC_SDTRx_TXSR_Pos (4U)\r
+#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */\r
+#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */\r
+#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */\r
+#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */\r
+#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */\r
+\r
+#define FMC_SDTRx_TRAS_Pos (8U)\r
+#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */\r
+#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */\r
+#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */\r
+#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */\r
+\r
+#define FMC_SDTRx_TRC_Pos (12U)\r
+#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */\r
+#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */\r
+#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */\r
+#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */\r
+\r
+#define FMC_SDTRx_TWR_Pos (16U)\r
+#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */\r
+#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */\r
+#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */\r
+#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */\r
+\r
+#define FMC_SDTRx_TRP_Pos (20U)\r
+#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */\r
+#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */\r
+#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */\r
+#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */\r
+\r
+#define FMC_SDTRx_TRCD_Pos (24U)\r
+#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */\r
+#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */\r
+#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */\r
+#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */\r
+\r
+/****************** Bit definition for FMC_SDCMR register ******************/\r
+#define FMC_SDCMR_MODE_Pos (0U)\r
+#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */\r
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */\r
+#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */\r
+#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */\r
+\r
+#define FMC_SDCMR_CTB2_Pos (3U)\r
+#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */\r
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */\r
+\r
+#define FMC_SDCMR_CTB1_Pos (4U)\r
+#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */\r
+\r
+#define FMC_SDCMR_NRFS_Pos (5U)\r
+#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */\r
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */\r
+#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */\r
+\r
+#define FMC_SDCMR_MRD_Pos (9U)\r
+#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */\r
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/****************** Bit definition for FMC_SDRTR register ******************/\r
+#define FMC_SDRTR_CRE_Pos (0U)\r
+#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */\r
+\r
+#define FMC_SDRTR_COUNT_Pos (1U)\r
+#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */\r
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */\r
+\r
+#define FMC_SDRTR_REIE_Pos (14U)\r
+#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */\r
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */\r
+\r
+/****************** Bit definition for FMC_SDSR register ******************/\r
+#define FMC_SDSR_RE_Pos (0U)\r
+#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */\r
+\r
+#define FMC_SDSR_MODES1_Pos (1U)\r
+#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */\r
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */\r
+#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */\r
+\r
+#define FMC_SDSR_MODES2_Pos (3U)\r
+#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */\r
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */\r
+#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODE0_Pos (0U)\r
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */\r
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk\r
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */\r
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */\r
+\r
+#define GPIO_MODER_MODE1_Pos (2U)\r
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */\r
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk\r
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */\r
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */\r
+\r
+#define GPIO_MODER_MODE2_Pos (4U)\r
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */\r
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk\r
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */\r
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */\r
+\r
+#define GPIO_MODER_MODE3_Pos (6U)\r
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk\r
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */\r
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */\r
+\r
+#define GPIO_MODER_MODE4_Pos (8U)\r
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */\r
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk\r
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */\r
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */\r
+\r
+#define GPIO_MODER_MODE5_Pos (10U)\r
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk\r
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */\r
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */\r
+\r
+#define GPIO_MODER_MODE6_Pos (12U)\r
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */\r
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk\r
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */\r
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */\r
+\r
+#define GPIO_MODER_MODE7_Pos (14U)\r
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk\r
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */\r
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */\r
+\r
+#define GPIO_MODER_MODE8_Pos (16U)\r
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */\r
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk\r
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */\r
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */\r
+\r
+#define GPIO_MODER_MODE9_Pos (18U)\r
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk\r
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */\r
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */\r
+\r
+#define GPIO_MODER_MODE10_Pos (20U)\r
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */\r
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk\r
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */\r
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */\r
+\r
+#define GPIO_MODER_MODE11_Pos (22U)\r
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk\r
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */\r
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */\r
+\r
+#define GPIO_MODER_MODE12_Pos (24U)\r
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */\r
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk\r
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */\r
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */\r
+\r
+#define GPIO_MODER_MODE13_Pos (26U)\r
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk\r
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */\r
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */\r
+\r
+#define GPIO_MODER_MODE14_Pos (28U)\r
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */\r
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk\r
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */\r
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */\r
+\r
+#define GPIO_MODER_MODE15_Pos (30U)\r
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk\r
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */\r
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT0_Pos (0U)\r
+#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */\r
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk\r
+#define GPIO_OTYPER_OT1_Pos (1U)\r
+#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */\r
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk\r
+#define GPIO_OTYPER_OT2_Pos (2U)\r
+#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */\r
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk\r
+#define GPIO_OTYPER_OT3_Pos (3U)\r
+#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */\r
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk\r
+#define GPIO_OTYPER_OT4_Pos (4U)\r
+#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */\r
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk\r
+#define GPIO_OTYPER_OT5_Pos (5U)\r
+#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */\r
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk\r
+#define GPIO_OTYPER_OT6_Pos (6U)\r
+#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */\r
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk\r
+#define GPIO_OTYPER_OT7_Pos (7U)\r
+#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */\r
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk\r
+#define GPIO_OTYPER_OT8_Pos (8U)\r
+#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */\r
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk\r
+#define GPIO_OTYPER_OT9_Pos (9U)\r
+#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */\r
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk\r
+#define GPIO_OTYPER_OT10_Pos (10U)\r
+#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */\r
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk\r
+#define GPIO_OTYPER_OT11_Pos (11U)\r
+#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */\r
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk\r
+#define GPIO_OTYPER_OT12_Pos (12U)\r
+#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */\r
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk\r
+#define GPIO_OTYPER_OT13_Pos (13U)\r
+#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */\r
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk\r
+#define GPIO_OTYPER_OT14_Pos (14U)\r
+#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */\r
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk\r
+#define GPIO_OTYPER_OT15_Pos (15U)\r
+#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */\r
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk\r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)\r
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */\r
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk\r
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */\r
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)\r
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */\r
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk\r
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */\r
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)\r
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */\r
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk\r
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */\r
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)\r
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk\r
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */\r
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)\r
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */\r
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk\r
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */\r
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)\r
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk\r
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */\r
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)\r
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */\r
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk\r
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */\r
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)\r
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk\r
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */\r
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)\r
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */\r
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk\r
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */\r
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)\r
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk\r
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */\r
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)\r
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */\r
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk\r
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */\r
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)\r
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk\r
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */\r
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)\r
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */\r
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk\r
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */\r
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)\r
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk\r
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */\r
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)\r
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */\r
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk\r
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */\r
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */\r
+\r
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)\r
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk\r
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */\r
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPD0_Pos (0U)\r
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */\r
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk\r
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */\r
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */\r
+\r
+#define GPIO_PUPDR_PUPD1_Pos (2U)\r
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */\r
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk\r
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */\r
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */\r
+\r
+#define GPIO_PUPDR_PUPD2_Pos (4U)\r
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */\r
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk\r
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */\r
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */\r
+\r
+#define GPIO_PUPDR_PUPD3_Pos (6U)\r
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk\r
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */\r
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */\r
+\r
+#define GPIO_PUPDR_PUPD4_Pos (8U)\r
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */\r
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk\r
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */\r
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */\r
+\r
+#define GPIO_PUPDR_PUPD5_Pos (10U)\r
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk\r
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */\r
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */\r
+\r
+#define GPIO_PUPDR_PUPD6_Pos (12U)\r
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */\r
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk\r
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */\r
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */\r
+\r
+#define GPIO_PUPDR_PUPD7_Pos (14U)\r
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk\r
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */\r
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */\r
+\r
+#define GPIO_PUPDR_PUPD8_Pos (16U)\r
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */\r
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk\r
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */\r
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */\r
+\r
+#define GPIO_PUPDR_PUPD9_Pos (18U)\r
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk\r
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */\r
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */\r
+\r
+#define GPIO_PUPDR_PUPD10_Pos (20U)\r
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */\r
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk\r
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */\r
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */\r
+\r
+#define GPIO_PUPDR_PUPD11_Pos (22U)\r
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk\r
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */\r
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */\r
+\r
+#define GPIO_PUPDR_PUPD12_Pos (24U)\r
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */\r
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk\r
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */\r
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */\r
+\r
+#define GPIO_PUPDR_PUPD13_Pos (26U)\r
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk\r
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */\r
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */\r
+\r
+#define GPIO_PUPDR_PUPD14_Pos (28U)\r
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */\r
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk\r
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */\r
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */\r
+\r
+#define GPIO_PUPDR_PUPD15_Pos (30U)\r
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk\r
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */\r
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_ID0_Pos (0U)\r
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */\r
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk\r
+#define GPIO_IDR_ID1_Pos (1U)\r
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */\r
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk\r
+#define GPIO_IDR_ID2_Pos (2U)\r
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */\r
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk\r
+#define GPIO_IDR_ID3_Pos (3U)\r
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */\r
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk\r
+#define GPIO_IDR_ID4_Pos (4U)\r
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */\r
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk\r
+#define GPIO_IDR_ID5_Pos (5U)\r
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */\r
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk\r
+#define GPIO_IDR_ID6_Pos (6U)\r
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */\r
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk\r
+#define GPIO_IDR_ID7_Pos (7U)\r
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */\r
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk\r
+#define GPIO_IDR_ID8_Pos (8U)\r
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */\r
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk\r
+#define GPIO_IDR_ID9_Pos (9U)\r
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */\r
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk\r
+#define GPIO_IDR_ID10_Pos (10U)\r
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */\r
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk\r
+#define GPIO_IDR_ID11_Pos (11U)\r
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */\r
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk\r
+#define GPIO_IDR_ID12_Pos (12U)\r
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */\r
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk\r
+#define GPIO_IDR_ID13_Pos (13U)\r
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */\r
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk\r
+#define GPIO_IDR_ID14_Pos (14U)\r
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */\r
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk\r
+#define GPIO_IDR_ID15_Pos (15U)\r
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */\r
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_OD0_Pos (0U)\r
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */\r
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk\r
+#define GPIO_ODR_OD1_Pos (1U)\r
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */\r
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk\r
+#define GPIO_ODR_OD2_Pos (2U)\r
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */\r
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk\r
+#define GPIO_ODR_OD3_Pos (3U)\r
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */\r
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk\r
+#define GPIO_ODR_OD4_Pos (4U)\r
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */\r
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk\r
+#define GPIO_ODR_OD5_Pos (5U)\r
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */\r
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk\r
+#define GPIO_ODR_OD6_Pos (6U)\r
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */\r
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk\r
+#define GPIO_ODR_OD7_Pos (7U)\r
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */\r
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk\r
+#define GPIO_ODR_OD8_Pos (8U)\r
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */\r
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk\r
+#define GPIO_ODR_OD9_Pos (9U)\r
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */\r
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk\r
+#define GPIO_ODR_OD10_Pos (10U)\r
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */\r
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk\r
+#define GPIO_ODR_OD11_Pos (11U)\r
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */\r
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk\r
+#define GPIO_ODR_OD12_Pos (12U)\r
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */\r
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk\r
+#define GPIO_ODR_OD13_Pos (13U)\r
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */\r
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk\r
+#define GPIO_ODR_OD14_Pos (14U)\r
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */\r
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk\r
+#define GPIO_ODR_OD15_Pos (15U)\r
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */\r
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk\r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS0_Pos (0U)\r
+#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */\r
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk\r
+#define GPIO_BSRR_BS1_Pos (1U)\r
+#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */\r
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk\r
+#define GPIO_BSRR_BS2_Pos (2U)\r
+#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */\r
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk\r
+#define GPIO_BSRR_BS3_Pos (3U)\r
+#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */\r
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk\r
+#define GPIO_BSRR_BS4_Pos (4U)\r
+#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */\r
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk\r
+#define GPIO_BSRR_BS5_Pos (5U)\r
+#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */\r
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk\r
+#define GPIO_BSRR_BS6_Pos (6U)\r
+#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */\r
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk\r
+#define GPIO_BSRR_BS7_Pos (7U)\r
+#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */\r
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk\r
+#define GPIO_BSRR_BS8_Pos (8U)\r
+#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */\r
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk\r
+#define GPIO_BSRR_BS9_Pos (9U)\r
+#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */\r
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk\r
+#define GPIO_BSRR_BS10_Pos (10U)\r
+#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */\r
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk\r
+#define GPIO_BSRR_BS11_Pos (11U)\r
+#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */\r
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk\r
+#define GPIO_BSRR_BS12_Pos (12U)\r
+#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */\r
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk\r
+#define GPIO_BSRR_BS13_Pos (13U)\r
+#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */\r
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk\r
+#define GPIO_BSRR_BS14_Pos (14U)\r
+#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */\r
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk\r
+#define GPIO_BSRR_BS15_Pos (15U)\r
+#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */\r
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk\r
+#define GPIO_BSRR_BR0_Pos (16U)\r
+#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */\r
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk\r
+#define GPIO_BSRR_BR1_Pos (17U)\r
+#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */\r
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk\r
+#define GPIO_BSRR_BR2_Pos (18U)\r
+#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */\r
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk\r
+#define GPIO_BSRR_BR3_Pos (19U)\r
+#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */\r
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk\r
+#define GPIO_BSRR_BR4_Pos (20U)\r
+#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */\r
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk\r
+#define GPIO_BSRR_BR5_Pos (21U)\r
+#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */\r
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk\r
+#define GPIO_BSRR_BR6_Pos (22U)\r
+#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */\r
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk\r
+#define GPIO_BSRR_BR7_Pos (23U)\r
+#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */\r
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk\r
+#define GPIO_BSRR_BR8_Pos (24U)\r
+#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */\r
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk\r
+#define GPIO_BSRR_BR9_Pos (25U)\r
+#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */\r
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk\r
+#define GPIO_BSRR_BR10_Pos (26U)\r
+#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */\r
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk\r
+#define GPIO_BSRR_BR11_Pos (27U)\r
+#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */\r
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk\r
+#define GPIO_BSRR_BR12_Pos (28U)\r
+#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */\r
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk\r
+#define GPIO_BSRR_BR13_Pos (29U)\r
+#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */\r
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk\r
+#define GPIO_BSRR_BR14_Pos (30U)\r
+#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */\r
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk\r
+#define GPIO_BSRR_BR15_Pos (31U)\r
+#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */\r
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk\r
+\r
+/****************** Bit definition for GPIO_LCKR register *********************/\r
+#define GPIO_LCKR_LCK0_Pos (0U)\r
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */\r
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk\r
+#define GPIO_LCKR_LCK1_Pos (1U)\r
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */\r
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk\r
+#define GPIO_LCKR_LCK2_Pos (2U)\r
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */\r
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk\r
+#define GPIO_LCKR_LCK3_Pos (3U)\r
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */\r
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk\r
+#define GPIO_LCKR_LCK4_Pos (4U)\r
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */\r
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk\r
+#define GPIO_LCKR_LCK5_Pos (5U)\r
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */\r
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk\r
+#define GPIO_LCKR_LCK6_Pos (6U)\r
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */\r
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk\r
+#define GPIO_LCKR_LCK7_Pos (7U)\r
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */\r
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk\r
+#define GPIO_LCKR_LCK8_Pos (8U)\r
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */\r
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk\r
+#define GPIO_LCKR_LCK9_Pos (9U)\r
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */\r
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk\r
+#define GPIO_LCKR_LCK10_Pos (10U)\r
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */\r
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk\r
+#define GPIO_LCKR_LCK11_Pos (11U)\r
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */\r
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk\r
+#define GPIO_LCKR_LCK12_Pos (12U)\r
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */\r
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk\r
+#define GPIO_LCKR_LCK13_Pos (13U)\r
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */\r
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk\r
+#define GPIO_LCKR_LCK14_Pos (14U)\r
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */\r
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk\r
+#define GPIO_LCKR_LCK15_Pos (15U)\r
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */\r
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk\r
+#define GPIO_LCKR_LCKK_Pos (16U)\r
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */\r
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk\r
+\r
+/****************** Bit definition for GPIO_AFRL register ********************/\r
+#define GPIO_AFRL_AFSEL0_Pos (0U)\r
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk\r
+#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */\r
+#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */\r
+#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */\r
+#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */\r
+#define GPIO_AFRL_AFSEL1_Pos (4U)\r
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk\r
+#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */\r
+#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */\r
+#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */\r
+#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */\r
+#define GPIO_AFRL_AFSEL2_Pos (8U)\r
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk\r
+#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */\r
+#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */\r
+#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */\r
+#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */\r
+#define GPIO_AFRL_AFSEL3_Pos (12U)\r
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk\r
+#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */\r
+#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */\r
+#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */\r
+#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */\r
+#define GPIO_AFRL_AFSEL4_Pos (16U)\r
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk\r
+#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */\r
+#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */\r
+#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */\r
+#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */\r
+#define GPIO_AFRL_AFSEL5_Pos (20U)\r
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk\r
+#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */\r
+#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */\r
+#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */\r
+#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */\r
+#define GPIO_AFRL_AFSEL6_Pos (24U)\r
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk\r
+#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */\r
+#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */\r
+#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */\r
+#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */\r
+#define GPIO_AFRL_AFSEL7_Pos (28U)\r
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk\r
+#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */\r
+#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */\r
+#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */\r
+#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */\r
+\r
+/* Legacy defines */\r
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0\r
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1\r
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2\r
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3\r
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4\r
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5\r
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6\r
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7\r
+\r
+/****************** Bit definition for GPIO_AFRH register ********************/\r
+#define GPIO_AFRH_AFSEL8_Pos (0U)\r
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk\r
+#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */\r
+#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */\r
+#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */\r
+#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */\r
+#define GPIO_AFRH_AFSEL9_Pos (4U)\r
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk\r
+#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */\r
+#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */\r
+#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */\r
+#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */\r
+#define GPIO_AFRH_AFSEL10_Pos (8U)\r
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk\r
+#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */\r
+#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */\r
+#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */\r
+#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */\r
+#define GPIO_AFRH_AFSEL11_Pos (12U)\r
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk\r
+#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */\r
+#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */\r
+#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */\r
+#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */\r
+#define GPIO_AFRH_AFSEL12_Pos (16U)\r
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk\r
+#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */\r
+#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */\r
+#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */\r
+#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */\r
+#define GPIO_AFRH_AFSEL13_Pos (20U)\r
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk\r
+#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */\r
+#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */\r
+#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */\r
+#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */\r
+#define GPIO_AFRH_AFSEL14_Pos (24U)\r
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk\r
+#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */\r
+#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */\r
+#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */\r
+#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */\r
+#define GPIO_AFRH_AFSEL15_Pos (28U)\r
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk\r
+#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */\r
+#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */\r
+#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */\r
+#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */\r
+\r
+/* Legacy defines */\r
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8\r
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9\r
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10\r
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11\r
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12\r
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13\r
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14\r
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HSEM HW Semaphore */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for HSEM_R register ********************/\r
+#define HSEM_R_PROCID_Pos (0U)\r
+#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */\r
+#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */\r
+#define HSEM_R_COREID_Pos (8U)\r
+#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */\r
+#define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */\r
+#define HSEM_R_LOCK_Pos (31U)\r
+#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */\r
+#define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */\r
+\r
+/******************** Bit definition for HSEM_RLR register ******************/\r
+#define HSEM_RLR_PROCID_Pos (0U)\r
+#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */\r
+#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */\r
+#define HSEM_RLR_COREID_Pos (8U)\r
+#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */\r
+#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */\r
+#define HSEM_RLR_LOCK_Pos (31U)\r
+#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */\r
+#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */\r
+\r
+/******************** Bit definition for HSEM_C1IER register *****************/\r
+#define HSEM_C1IER_ISE0_Pos (0U)\r
+#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE1_Pos (1U)\r
+#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE2_Pos (2U)\r
+#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE3_Pos (3U)\r
+#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE4_Pos (4U)\r
+#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE5_Pos (5U)\r
+#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE6_Pos (6U)\r
+#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE7_Pos (7U)\r
+#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE8_Pos (8U)\r
+#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE9_Pos (9U)\r
+#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE10_Pos (10U)\r
+#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE11_Pos (11U)\r
+#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE12_Pos (12U)\r
+#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE13_Pos (13U)\r
+#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE14_Pos (14U)\r
+#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE15_Pos (15U)\r
+#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE16_Pos (16U)\r
+#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE17_Pos (17U)\r
+#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE18_Pos (18U)\r
+#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE19_Pos (19U)\r
+#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE20_Pos (20U)\r
+#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE21_Pos (21U)\r
+#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE22_Pos (22U)\r
+#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE23_Pos (23U)\r
+#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE24_Pos (24U)\r
+#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE25_Pos (25U)\r
+#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE26_Pos (26U)\r
+#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE27_Pos (27U)\r
+#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE28_Pos (28U)\r
+#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE29_Pos (29U)\r
+#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE30_Pos (30U)\r
+#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */\r
+#define HSEM_C1IER_ISE31_Pos (31U)\r
+#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */\r
+\r
+/******************** Bit definition for HSEM_C1ICR register *****************/\r
+#define HSEM_C1ICR_ISC0_Pos (0U)\r
+#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC1_Pos (1U)\r
+#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC2_Pos (2U)\r
+#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC3_Pos (3U)\r
+#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC4_Pos (4U)\r
+#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC5_Pos (5U)\r
+#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC6_Pos (6U)\r
+#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC7_Pos (7U)\r
+#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC8_Pos (8U)\r
+#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC9_Pos (9U)\r
+#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC10_Pos (10U)\r
+#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC11_Pos (11U)\r
+#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC12_Pos (12U)\r
+#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC13_Pos (13U)\r
+#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC14_Pos (14U)\r
+#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC15_Pos (15U)\r
+#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC16_Pos (16U)\r
+#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC17_Pos (17U)\r
+#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC18_Pos (18U)\r
+#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC19_Pos (19U)\r
+#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC20_Pos (20U)\r
+#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC21_Pos (21U)\r
+#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC22_Pos (22U)\r
+#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC23_Pos (23U)\r
+#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC24_Pos (24U)\r
+#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC25_Pos (25U)\r
+#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC26_Pos (26U)\r
+#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC27_Pos (27U)\r
+#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC28_Pos (28U)\r
+#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC29_Pos (29U)\r
+#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC30_Pos (30U)\r
+#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */\r
+#define HSEM_C1ICR_ISC31_Pos (31U)\r
+#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */\r
+\r
+/******************** Bit definition for HSEM_C1ISR register *****************/\r
+#define HSEM_C1ISR_ISF0_Pos (0U)\r
+#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF1_Pos (1U)\r
+#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF2_Pos (2U)\r
+#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF3_Pos (3U)\r
+#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF4_Pos (4U)\r
+#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF5_Pos (5U)\r
+#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF6_Pos (6U)\r
+#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF7_Pos (7U)\r
+#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF8_Pos (8U)\r
+#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF9_Pos (9U)\r
+#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF10_Pos (10U)\r
+#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF11_Pos (11U)\r
+#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF12_Pos (12U)\r
+#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF13_Pos (13U)\r
+#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF14_Pos (14U)\r
+#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF15_Pos (15U)\r
+#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF16_Pos (16U)\r
+#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF17_Pos (17U)\r
+#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF18_Pos (18U)\r
+#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF19_Pos (19U)\r
+#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF20_Pos (20U)\r
+#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF21_Pos (21U)\r
+#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF22_Pos (22U)\r
+#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF23_Pos (23U)\r
+#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF24_Pos (24U)\r
+#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF25_Pos (25U)\r
+#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF26_Pos (26U)\r
+#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF27_Pos (27U)\r
+#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF28_Pos (28U)\r
+#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF29_Pos (29U)\r
+#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF30_Pos (30U)\r
+#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */\r
+#define HSEM_C1ISR_ISF31_Pos (31U)\r
+#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */\r
+\r
+/******************** Bit definition for HSEM_C1MISR register *****************/\r
+#define HSEM_C1MISR_MISF0_Pos (0U)\r
+#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF1_Pos (1U)\r
+#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF2_Pos (2U)\r
+#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF3_Pos (3U)\r
+#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF4_Pos (4U)\r
+#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF5_Pos (5U)\r
+#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF6_Pos (6U)\r
+#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF7_Pos (7U)\r
+#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF8_Pos (8U)\r
+#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF9_Pos (9U)\r
+#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF10_Pos (10U)\r
+#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF11_Pos (11U)\r
+#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF12_Pos (12U)\r
+#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF13_Pos (13U)\r
+#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF14_Pos (14U)\r
+#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF15_Pos (15U)\r
+#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF16_Pos (16U)\r
+#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF17_Pos (17U)\r
+#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF18_Pos (18U)\r
+#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF19_Pos (19U)\r
+#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF20_Pos (20U)\r
+#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF21_Pos (21U)\r
+#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF22_Pos (22U)\r
+#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF23_Pos (23U)\r
+#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF24_Pos (24U)\r
+#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF25_Pos (25U)\r
+#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF26_Pos (26U)\r
+#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF27_Pos (27U)\r
+#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF28_Pos (28U)\r
+#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF29_Pos (29U)\r
+#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF30_Pos (30U)\r
+#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */\r
+#define HSEM_C1MISR_MISF31_Pos (31U)\r
+#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */\r
+\r
+/******************** Bit definition for HSEM_C2IER register *****************/\r
+#define HSEM_C2IER_ISE0_Pos (0U)\r
+#define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk /*!<semaphore 0 , interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE1_Pos (1U)\r
+#define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk /*!<semaphore 1 , interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE2_Pos (2U)\r
+#define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk /*!<semaphore 2 , interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE3_Pos (3U)\r
+#define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk /*!<semaphore 3 , interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE4_Pos (4U)\r
+#define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk /*!<semaphore 4 , interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE5_Pos (5U)\r
+#define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk /*!<semaphore 5 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE6_Pos (6U)\r
+#define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk /*!<semaphore 6 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE7_Pos (7U)\r
+#define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk /*!<semaphore 7 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE8_Pos (8U)\r
+#define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk /*!<semaphore 8 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE9_Pos (9U)\r
+#define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk /*!<semaphore 9 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE10_Pos (10U)\r
+#define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk /*!<semaphore 10 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE11_Pos (11U)\r
+#define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk /*!<semaphore 11 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE12_Pos (12U)\r
+#define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk /*!<semaphore 12 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE13_Pos (13U)\r
+#define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk /*!<semaphore 13 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE14_Pos (14U)\r
+#define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk /*!<semaphore 14 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE15_Pos (15U)\r
+#define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk /*!<semaphore 15 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE16_Pos (16U)\r
+#define HSEM_C2IER_ISE16_Msk (0x1UL << HSEM_C2IER_ISE16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C2IER_ISE16 HSEM_C2IER_ISE16_Msk /*!<semaphore 16 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE17_Pos (17U)\r
+#define HSEM_C2IER_ISE17_Msk (0x1UL << HSEM_C2IER_ISE17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C2IER_ISE17 HSEM_C2IER_ISE17_Msk /*!<semaphore 17 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE18_Pos (18U)\r
+#define HSEM_C2IER_ISE18_Msk (0x1UL << HSEM_C2IER_ISE18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C2IER_ISE18 HSEM_C2IER_ISE18_Msk /*!<semaphore 18 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE19_Pos (19U)\r
+#define HSEM_C2IER_ISE19_Msk (0x1UL << HSEM_C2IER_ISE19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C2IER_ISE19 HSEM_C2IER_ISE19_Msk /*!<semaphore 19 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE20_Pos (20U)\r
+#define HSEM_C2IER_ISE20_Msk (0x1UL << HSEM_C2IER_ISE20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C2IER_ISE20 HSEM_C2IER_ISE20_Msk /*!<semaphore 20 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE21_Pos (21U)\r
+#define HSEM_C2IER_ISE21_Msk (0x1UL << HSEM_C2IER_ISE21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C2IER_ISE21 HSEM_C2IER_ISE21_Msk /*!<semaphore 21 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE22_Pos (22U)\r
+#define HSEM_C2IER_ISE22_Msk (0x1UL << HSEM_C2IER_ISE22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C2IER_ISE22 HSEM_C2IER_ISE22_Msk /*!<semaphore 22 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE23_Pos (23U)\r
+#define HSEM_C2IER_ISE23_Msk (0x1UL << HSEM_C2IER_ISE23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C2IER_ISE23 HSEM_C2IER_ISE23_Msk /*!<semaphore 23 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE24_Pos (24U)\r
+#define HSEM_C2IER_ISE24_Msk (0x1UL << HSEM_C2IER_ISE24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C2IER_ISE24 HSEM_C2IER_ISE24_Msk /*!<semaphore 24 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE25_Pos (25U)\r
+#define HSEM_C2IER_ISE25_Msk (0x1UL << HSEM_C2IER_ISE25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C2IER_ISE25 HSEM_C2IER_ISE25_Msk /*!<semaphore 25 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE26_Pos (26U)\r
+#define HSEM_C2IER_ISE26_Msk (0x1UL << HSEM_C2IER_ISE26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C2IER_ISE26 HSEM_C2IER_ISE26_Msk /*!<semaphore 26 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE27_Pos (27U)\r
+#define HSEM_C2IER_ISE27_Msk (0x1UL << HSEM_C2IER_ISE27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C2IER_ISE27 HSEM_C2IER_ISE27_Msk /*!<semaphore 27 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE28_Pos (28U)\r
+#define HSEM_C2IER_ISE28_Msk (0x1UL << HSEM_C2IER_ISE28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C2IER_ISE28 HSEM_C2IER_ISE28_Msk /*!<semaphore 28 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE29_Pos (29U)\r
+#define HSEM_C2IER_ISE29_Msk (0x1UL << HSEM_C2IER_ISE29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C2IER_ISE29 HSEM_C2IER_ISE29_Msk /*!<semaphore 29 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE30_Pos (30U)\r
+#define HSEM_C2IER_ISE30_Msk (0x1UL << HSEM_C2IER_ISE30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C2IER_ISE30 HSEM_C2IER_ISE30_Msk /*!<semaphore 30 interrupt 1 enable bit. */\r
+#define HSEM_C2IER_ISE31_Pos (31U)\r
+#define HSEM_C2IER_ISE31_Msk (0x1UL << HSEM_C2IER_ISE31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C2IER_ISE31 HSEM_C2IER_ISE31_Msk /*!<semaphore 31 interrupt 1 enable bit. */\r
+\r
+/******************** Bit definition for HSEM_C2ICR register *****************/\r
+#define HSEM_C2ICR_ISC0_Pos (0U)\r
+#define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk /*!<semaphore 0 , interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC1_Pos (1U)\r
+#define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk /*!<semaphore 1 , interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC2_Pos (2U)\r
+#define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk /*!<semaphore 2 , interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC3_Pos (3U)\r
+#define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk /*!<semaphore 3 , interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC4_Pos (4U)\r
+#define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk /*!<semaphore 4 , interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC5_Pos (5U)\r
+#define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk /*!<semaphore 5 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC6_Pos (6U)\r
+#define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk /*!<semaphore 6 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC7_Pos (7U)\r
+#define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk /*!<semaphore 7 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC8_Pos (8U)\r
+#define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk /*!<semaphore 8 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC9_Pos (9U)\r
+#define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk /*!<semaphore 9 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC10_Pos (10U)\r
+#define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk /*!<semaphore 10 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC11_Pos (11U)\r
+#define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk /*!<semaphore 11 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC12_Pos (12U)\r
+#define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk /*!<semaphore 12 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC13_Pos (13U)\r
+#define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk /*!<semaphore 13 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC14_Pos (14U)\r
+#define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk /*!<semaphore 14 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC15_Pos (15U)\r
+#define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk /*!<semaphore 15 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC16_Pos (16U)\r
+#define HSEM_C2ICR_ISC16_Msk (0x1UL << HSEM_C2ICR_ISC16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C2ICR_ISC16 HSEM_C2ICR_ISC16_Msk /*!<semaphore 16 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC17_Pos (17U)\r
+#define HSEM_C2ICR_ISC17_Msk (0x1UL << HSEM_C2ICR_ISC17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C2ICR_ISC17 HSEM_C2ICR_ISC17_Msk /*!<semaphore 17 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC18_Pos (18U)\r
+#define HSEM_C2ICR_ISC18_Msk (0x1UL << HSEM_C2ICR_ISC18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C2ICR_ISC18 HSEM_C2ICR_ISC18_Msk /*!<semaphore 18 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC19_Pos (19U)\r
+#define HSEM_C2ICR_ISC19_Msk (0x1UL << HSEM_C2ICR_ISC19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C2ICR_ISC19 HSEM_C2ICR_ISC19_Msk /*!<semaphore 19 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC20_Pos (20U)\r
+#define HSEM_C2ICR_ISC20_Msk (0x1UL << HSEM_C2ICR_ISC20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C2ICR_ISC20 HSEM_C2ICR_ISC20_Msk /*!<semaphore 20 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC21_Pos (21U)\r
+#define HSEM_C2ICR_ISC21_Msk (0x1UL << HSEM_C2ICR_ISC21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C2ICR_ISC21 HSEM_C2ICR_ISC21_Msk /*!<semaphore 21 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC22_Pos (22U)\r
+#define HSEM_C2ICR_ISC22_Msk (0x1UL << HSEM_C2ICR_ISC22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C2ICR_ISC22 HSEM_C2ICR_ISC22_Msk /*!<semaphore 22 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC23_Pos (23U)\r
+#define HSEM_C2ICR_ISC23_Msk (0x1UL << HSEM_C2ICR_ISC23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C2ICR_ISC23 HSEM_C2ICR_ISC23_Msk /*!<semaphore 23 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC24_Pos (24U)\r
+#define HSEM_C2ICR_ISC24_Msk (0x1UL << HSEM_C2ICR_ISC24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C2ICR_ISC24 HSEM_C2ICR_ISC24_Msk /*!<semaphore 24 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC25_Pos (25U)\r
+#define HSEM_C2ICR_ISC25_Msk (0x1UL << HSEM_C2ICR_ISC25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C2ICR_ISC25 HSEM_C2ICR_ISC25_Msk /*!<semaphore 25 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC26_Pos (26U)\r
+#define HSEM_C2ICR_ISC26_Msk (0x1UL << HSEM_C2ICR_ISC26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C2ICR_ISC26 HSEM_C2ICR_ISC26_Msk /*!<semaphore 26 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC27_Pos (27U)\r
+#define HSEM_C2ICR_ISC27_Msk (0x1UL << HSEM_C2ICR_ISC27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C2ICR_ISC27 HSEM_C2ICR_ISC27_Msk /*!<semaphore 27 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC28_Pos (28U)\r
+#define HSEM_C2ICR_ISC28_Msk (0x1UL << HSEM_C2ICR_ISC28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C2ICR_ISC28 HSEM_C2ICR_ISC28_Msk /*!<semaphore 28 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC29_Pos (29U)\r
+#define HSEM_C2ICR_ISC29_Msk (0x1UL << HSEM_C2ICR_ISC29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C2ICR_ISC29 HSEM_C2ICR_ISC29_Msk /*!<semaphore 29 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC30_Pos (30U)\r
+#define HSEM_C2ICR_ISC30_Msk (0x1UL << HSEM_C2ICR_ISC30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C2ICR_ISC30 HSEM_C2ICR_ISC30_Msk /*!<semaphore 30 interrupt 1 clear bit. */\r
+#define HSEM_C2ICR_ISC31_Pos (31U)\r
+#define HSEM_C2ICR_ISC31_Msk (0x1UL << HSEM_C2ICR_ISC31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C2ICR_ISC31 HSEM_C2ICR_ISC31_Msk /*!<semaphore 31 interrupt 1 clear bit. */\r
+\r
+/******************** Bit definition for HSEM_C2ISR register *****************/\r
+#define HSEM_C2ISR_ISF0_Pos (0U)\r
+#define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk /*!<semaphore 0 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF1_Pos (1U)\r
+#define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk /*!<semaphore 1 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF2_Pos (2U)\r
+#define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk /*!<semaphore 2 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF3_Pos (3U)\r
+#define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk /*!<semaphore 3 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF4_Pos (4U)\r
+#define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk /*!<semaphore 4 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF5_Pos (5U)\r
+#define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk /*!<semaphore 5 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF6_Pos (6U)\r
+#define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk /*!<semaphore 6 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF7_Pos (7U)\r
+#define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk /*!<semaphore 7 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF8_Pos (8U)\r
+#define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk /*!<semaphore 8 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF9_Pos (9U)\r
+#define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk /*!<semaphore 9 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF10_Pos (10U)\r
+#define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk /*!<semaphore 10 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF11_Pos (11U)\r
+#define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk /*!<semaphore 11 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF12_Pos (12U)\r
+#define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk /*!<semaphore 12 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF13_Pos (13U)\r
+#define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk /*!<semaphore 13 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF14_Pos (14U)\r
+#define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk /*!<semaphore 14 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF15_Pos (15U)\r
+#define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk /*!<semaphore 15 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF16_Pos (16U)\r
+#define HSEM_C2ISR_ISF16_Msk (0x1UL << HSEM_C2ISR_ISF16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C2ISR_ISF16 HSEM_C2ISR_ISF16_Msk /*!<semaphore 16 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF17_Pos (17U)\r
+#define HSEM_C2ISR_ISF17_Msk (0x1UL << HSEM_C2ISR_ISF17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C2ISR_ISF17 HSEM_C2ISR_ISF17_Msk /*!<semaphore 17 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF18_Pos (18U)\r
+#define HSEM_C2ISR_ISF18_Msk (0x1UL << HSEM_C2ISR_ISF18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C2ISR_ISF18 HSEM_C2ISR_ISF18_Msk /*!<semaphore 18 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF19_Pos (19U)\r
+#define HSEM_C2ISR_ISF19_Msk (0x1UL << HSEM_C2ISR_ISF19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C2ISR_ISF19 HSEM_C2ISR_ISF19_Msk /*!<semaphore 19 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF20_Pos (20U)\r
+#define HSEM_C2ISR_ISF20_Msk (0x1UL << HSEM_C2ISR_ISF20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C2ISR_ISF20 HSEM_C2ISR_ISF20_Msk /*!<semaphore 20 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF21_Pos (21U)\r
+#define HSEM_C2ISR_ISF21_Msk (0x1UL << HSEM_C2ISR_ISF21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C2ISR_ISF21 HSEM_C2ISR_ISF21_Msk /*!<semaphore 21 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF22_Pos (22U)\r
+#define HSEM_C2ISR_ISF22_Msk (0x1UL << HSEM_C2ISR_ISF22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C2ISR_ISF22 HSEM_C2ISR_ISF22_Msk /*!<semaphore 22 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF23_Pos (23U)\r
+#define HSEM_C2ISR_ISF23_Msk (0x1UL << HSEM_C2ISR_ISF23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C2ISR_ISF23 HSEM_C2ISR_ISF23_Msk /*!<semaphore 23 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF24_Pos (24U)\r
+#define HSEM_C2ISR_ISF24_Msk (0x1UL << HSEM_C2ISR_ISF24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C2ISR_ISF24 HSEM_C2ISR_ISF24_Msk /*!<semaphore 24 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF25_Pos (25U)\r
+#define HSEM_C2ISR_ISF25_Msk (0x1UL << HSEM_C2ISR_ISF25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C2ISR_ISF25 HSEM_C2ISR_ISF25_Msk /*!<semaphore 25 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF26_Pos (26U)\r
+#define HSEM_C2ISR_ISF26_Msk (0x1UL << HSEM_C2ISR_ISF26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C2ISR_ISF26 HSEM_C2ISR_ISF26_Msk /*!<semaphore 26 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF27_Pos (27U)\r
+#define HSEM_C2ISR_ISF27_Msk (0x1UL << HSEM_C2ISR_ISF27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C2ISR_ISF27 HSEM_C2ISR_ISF27_Msk /*!<semaphore 27 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF28_Pos (28U)\r
+#define HSEM_C2ISR_ISF28_Msk (0x1UL << HSEM_C2ISR_ISF28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C2ISR_ISF28 HSEM_C2ISR_ISF28_Msk /*!<semaphore 28 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF29_Pos (29U)\r
+#define HSEM_C2ISR_ISF29_Msk (0x1UL << HSEM_C2ISR_ISF29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C2ISR_ISF29 HSEM_C2ISR_ISF29_Msk /*!<semaphore 29 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF30_Pos (30U)\r
+#define HSEM_C2ISR_ISF30_Msk (0x1UL << HSEM_C2ISR_ISF30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C2ISR_ISF30 HSEM_C2ISR_ISF30_Msk /*!<semaphore 30 interrupt 1 status bit. */\r
+#define HSEM_C2ISR_ISF31_Pos (31U)\r
+#define HSEM_C2ISR_ISF31_Msk (0x1UL << HSEM_C2ISR_ISF31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C2ISR_ISF31 HSEM_C2ISR_ISF31_Msk /*!<semaphore 31 interrupt 1 status bit. */\r
+\r
+/******************** Bit definition for HSEM_C2MISR register *****************/\r
+#define HSEM_C2MISR_MISF0_Pos (0U)\r
+#define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos) /*!< 0x00000001 */\r
+#define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk /*!<semaphore 0 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF1_Pos (1U)\r
+#define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos) /*!< 0x00000002 */\r
+#define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk /*!<semaphore 1 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF2_Pos (2U)\r
+#define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos) /*!< 0x00000004 */\r
+#define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk /*!<semaphore 2 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF3_Pos (3U)\r
+#define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos) /*!< 0x00000008 */\r
+#define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk /*!<semaphore 3 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF4_Pos (4U)\r
+#define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos) /*!< 0x00000010 */\r
+#define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk /*!<semaphore 4 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF5_Pos (5U)\r
+#define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos) /*!< 0x00000020 */\r
+#define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk /*!<semaphore 5 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF6_Pos (6U)\r
+#define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos) /*!< 0x00000040 */\r
+#define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk /*!<semaphore 6 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF7_Pos (7U)\r
+#define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos) /*!< 0x00000080 */\r
+#define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk /*!<semaphore 7 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF8_Pos (8U)\r
+#define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos) /*!< 0x00000100 */\r
+#define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk /*!<semaphore 8 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF9_Pos (9U)\r
+#define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos) /*!< 0x00000200 */\r
+#define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk /*!<semaphore 9 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF10_Pos (10U)\r
+#define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos) /*!< 0x00000400 */\r
+#define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk /*!<semaphore 10 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF11_Pos (11U)\r
+#define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos) /*!< 0x00000800 */\r
+#define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk /*!<semaphore 11 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF12_Pos (12U)\r
+#define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos) /*!< 0x00001000 */\r
+#define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk /*!<semaphore 12 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF13_Pos (13U)\r
+#define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos) /*!< 0x00002000 */\r
+#define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk /*!<semaphore 13 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF14_Pos (14U)\r
+#define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos) /*!< 0x00004000 */\r
+#define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk /*!<semaphore 14 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF15_Pos (15U)\r
+#define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos) /*!< 0x00008000 */\r
+#define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk /*!<semaphore 15 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF16_Pos (16U)\r
+#define HSEM_C2MISR_MISF16_Msk (0x1UL << HSEM_C2MISR_MISF16_Pos) /*!< 0x00010000 */\r
+#define HSEM_C2MISR_MISF16 HSEM_C2MISR_MISF16_Msk /*!<semaphore 16 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF17_Pos (17U)\r
+#define HSEM_C2MISR_MISF17_Msk (0x1UL << HSEM_C2MISR_MISF17_Pos) /*!< 0x00020000 */\r
+#define HSEM_C2MISR_MISF17 HSEM_C2MISR_MISF17_Msk /*!<semaphore 17 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF18_Pos (18U)\r
+#define HSEM_C2MISR_MISF18_Msk (0x1UL << HSEM_C2MISR_MISF18_Pos) /*!< 0x00040000 */\r
+#define HSEM_C2MISR_MISF18 HSEM_C2MISR_MISF18_Msk /*!<semaphore 18 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF19_Pos (19U)\r
+#define HSEM_C2MISR_MISF19_Msk (0x1UL << HSEM_C2MISR_MISF19_Pos) /*!< 0x00080000 */\r
+#define HSEM_C2MISR_MISF19 HSEM_C2MISR_MISF19_Msk /*!<semaphore 19 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF20_Pos (20U)\r
+#define HSEM_C2MISR_MISF20_Msk (0x1UL << HSEM_C2MISR_MISF20_Pos) /*!< 0x00100000 */\r
+#define HSEM_C2MISR_MISF20 HSEM_C2MISR_MISF20_Msk /*!<semaphore 20 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF21_Pos (21U)\r
+#define HSEM_C2MISR_MISF21_Msk (0x1UL << HSEM_C2MISR_MISF21_Pos) /*!< 0x00200000 */\r
+#define HSEM_C2MISR_MISF21 HSEM_C2MISR_MISF21_Msk /*!<semaphore 21 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF22_Pos (22U)\r
+#define HSEM_C2MISR_MISF22_Msk (0x1UL << HSEM_C2MISR_MISF22_Pos) /*!< 0x00400000 */\r
+#define HSEM_C2MISR_MISF22 HSEM_C2MISR_MISF22_Msk /*!<semaphore 22 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF23_Pos (23U)\r
+#define HSEM_C2MISR_MISF23_Msk (0x1UL << HSEM_C2MISR_MISF23_Pos) /*!< 0x00800000 */\r
+#define HSEM_C2MISR_MISF23 HSEM_C2MISR_MISF23_Msk /*!<semaphore 23 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF24_Pos (24U)\r
+#define HSEM_C2MISR_MISF24_Msk (0x1UL << HSEM_C2MISR_MISF24_Pos) /*!< 0x01000000 */\r
+#define HSEM_C2MISR_MISF24 HSEM_C2MISR_MISF24_Msk /*!<semaphore 24 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF25_Pos (25U)\r
+#define HSEM_C2MISR_MISF25_Msk (0x1UL << HSEM_C2MISR_MISF25_Pos) /*!< 0x02000000 */\r
+#define HSEM_C2MISR_MISF25 HSEM_C2MISR_MISF25_Msk /*!<semaphore 25 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF26_Pos (26U)\r
+#define HSEM_C2MISR_MISF26_Msk (0x1UL << HSEM_C2MISR_MISF26_Pos) /*!< 0x04000000 */\r
+#define HSEM_C2MISR_MISF26 HSEM_C2MISR_MISF26_Msk /*!<semaphore 26 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF27_Pos (27U)\r
+#define HSEM_C2MISR_MISF27_Msk (0x1UL << HSEM_C2MISR_MISF27_Pos) /*!< 0x08000000 */\r
+#define HSEM_C2MISR_MISF27 HSEM_C2MISR_MISF27_Msk /*!<semaphore 27 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF28_Pos (28U)\r
+#define HSEM_C2MISR_MISF28_Msk (0x1UL << HSEM_C2MISR_MISF28_Pos) /*!< 0x10000000 */\r
+#define HSEM_C2MISR_MISF28 HSEM_C2MISR_MISF28_Msk /*!<semaphore 28 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF29_Pos (29U)\r
+#define HSEM_C2MISR_MISF29_Msk (0x1UL << HSEM_C2MISR_MISF29_Pos) /*!< 0x20000000 */\r
+#define HSEM_C2MISR_MISF29 HSEM_C2MISR_MISF29_Msk /*!<semaphore 29 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF30_Pos (30U)\r
+#define HSEM_C2MISR_MISF30_Msk (0x1UL << HSEM_C2MISR_MISF30_Pos) /*!< 0x40000000 */\r
+#define HSEM_C2MISR_MISF30 HSEM_C2MISR_MISF30_Msk /*!<semaphore 30 interrupt 1 masked status bit. */\r
+#define HSEM_C2MISR_MISF31_Pos (31U)\r
+#define HSEM_C2MISR_MISF31_Msk (0x1UL << HSEM_C2MISR_MISF31_Pos) /*!< 0x80000000 */\r
+#define HSEM_C2MISR_MISF31 HSEM_C2MISR_MISF31_Msk /*!<semaphore 31 interrupt 1 masked status bit. */\r
+/******************** Bit definition for HSEM_CR register *****************/\r
+#define HSEM_CR_COREID_Pos (8U)\r
+#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */\r
+#define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */\r
+#define HSEM_CR_KEY_Pos (16U)\r
+#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */\r
+#define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */\r
+\r
+/******************** Bit definition for HSEM_KEYR register *****************/\r
+#define HSEM_KEYR_KEY_Pos (16U)\r
+#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */\r
+#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register *******************/\r
+#define I2C_CR1_PE_Pos (0U)\r
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */\r
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */\r
+#define I2C_CR1_TXIE_Pos (1U)\r
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */\r
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */\r
+#define I2C_CR1_RXIE_Pos (2U)\r
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */\r
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */\r
+#define I2C_CR1_ADDRIE_Pos (3U)\r
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */\r
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */\r
+#define I2C_CR1_NACKIE_Pos (4U)\r
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */\r
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */\r
+#define I2C_CR1_STOPIE_Pos (5U)\r
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */\r
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */\r
+#define I2C_CR1_TCIE_Pos (6U)\r
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */\r
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */\r
+#define I2C_CR1_ERRIE_Pos (7U)\r
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */\r
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */\r
+#define I2C_CR1_DNF_Pos (8U)\r
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */\r
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */\r
+#define I2C_CR1_ANFOFF_Pos (12U)\r
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */\r
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */\r
+#define I2C_CR1_TXDMAEN_Pos (14U)\r
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */\r
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */\r
+#define I2C_CR1_RXDMAEN_Pos (15U)\r
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */\r
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */\r
+#define I2C_CR1_SBC_Pos (16U)\r
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */\r
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */\r
+#define I2C_CR1_NOSTRETCH_Pos (17U)\r
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */\r
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */\r
+#define I2C_CR1_WUPEN_Pos (18U)\r
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */\r
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */\r
+#define I2C_CR1_GCEN_Pos (19U)\r
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */\r
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */\r
+#define I2C_CR1_SMBHEN_Pos (20U)\r
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */\r
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */\r
+#define I2C_CR1_SMBDEN_Pos (21U)\r
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */\r
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN_Pos (22U)\r
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */\r
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */\r
+#define I2C_CR1_PECEN_Pos (23U)\r
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */\r
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */\r
+\r
+/****************** Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_SADD_Pos (0U)\r
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */\r
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */\r
+#define I2C_CR2_RD_WRN_Pos (10U)\r
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */\r
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */\r
+#define I2C_CR2_ADD10_Pos (11U)\r
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */\r
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */\r
+#define I2C_CR2_HEAD10R_Pos (12U)\r
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */\r
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START_Pos (13U)\r
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */\r
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */\r
+#define I2C_CR2_STOP_Pos (14U)\r
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */\r
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */\r
+#define I2C_CR2_NACK_Pos (15U)\r
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */\r
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */\r
+#define I2C_CR2_NBYTES_Pos (16U)\r
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */\r
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */\r
+#define I2C_CR2_RELOAD_Pos (24U)\r
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */\r
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */\r
+#define I2C_CR2_AUTOEND_Pos (25U)\r
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */\r
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */\r
+#define I2C_CR2_PECBYTE_Pos (26U)\r
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */\r
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */\r
+\r
+/******************* Bit definition for I2C_OAR1 register ******************/\r
+#define I2C_OAR1_OA1_Pos (0U)\r
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */\r
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */\r
+#define I2C_OAR1_OA1MODE_Pos (10U)\r
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */\r
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN_Pos (15U)\r
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */\r
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */\r
+\r
+/******************* Bit definition for I2C_OAR2 register ******************/\r
+#define I2C_OAR2_OA2_Pos (1U)\r
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */\r
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */\r
+#define I2C_OAR2_OA2MSK_Pos (8U)\r
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */\r
+#define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */\r
+#define I2C_OAR2_OA2MASK01_Pos (8U)\r
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */\r
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r
+#define I2C_OAR2_OA2MASK02_Pos (9U)\r
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */\r
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r
+#define I2C_OAR2_OA2MASK03_Pos (8U)\r
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */\r
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r
+#define I2C_OAR2_OA2MASK04_Pos (10U)\r
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */\r
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r
+#define I2C_OAR2_OA2MASK05_Pos (8U)\r
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */\r
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r
+#define I2C_OAR2_OA2MASK06_Pos (9U)\r
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */\r
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r
+#define I2C_OAR2_OA2MASK07_Pos (8U)\r
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */\r
+#define I2C_OAR2_OA2EN_Pos (15U)\r
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */\r
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */\r
+\r
+/******************* Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL_Pos (0U)\r
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */\r
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */\r
+#define I2C_TIMINGR_SCLH_Pos (8U)\r
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */\r
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL_Pos (16U)\r
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */\r
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */\r
+#define I2C_TIMINGR_SCLDEL_Pos (20U)\r
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */\r
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */\r
+#define I2C_TIMINGR_PRESC_Pos (28U)\r
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */\r
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)\r
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\r
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */\r
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)\r
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */\r
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */\r
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)\r
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\r
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */\r
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)\r
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\r
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/\r
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)\r
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */\r
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */\r
+\r
+/****************** Bit definition for I2C_ISR register *********************/\r
+#define I2C_ISR_TXE_Pos (0U)\r
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */\r
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */\r
+#define I2C_ISR_TXIS_Pos (1U)\r
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */\r
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */\r
+#define I2C_ISR_RXNE_Pos (2U)\r
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */\r
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR_Pos (3U)\r
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */\r
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/\r
+#define I2C_ISR_NACKF_Pos (4U)\r
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */\r
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */\r
+#define I2C_ISR_STOPF_Pos (5U)\r
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */\r
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */\r
+#define I2C_ISR_TC_Pos (6U)\r
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */\r
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR_Pos (7U)\r
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */\r
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */\r
+#define I2C_ISR_BERR_Pos (8U)\r
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */\r
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */\r
+#define I2C_ISR_ARLO_Pos (9U)\r
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */\r
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */\r
+#define I2C_ISR_OVR_Pos (10U)\r
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */\r
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */\r
+#define I2C_ISR_PECERR_Pos (11U)\r
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */\r
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */\r
+#define I2C_ISR_TIMEOUT_Pos (12U)\r
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */\r
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */\r
+#define I2C_ISR_ALERT_Pos (13U)\r
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */\r
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */\r
+#define I2C_ISR_BUSY_Pos (15U)\r
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */\r
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */\r
+#define I2C_ISR_DIR_Pos (16U)\r
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */\r
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE_Pos (17U)\r
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */\r
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */\r
+\r
+/****************** Bit definition for I2C_ICR register *********************/\r
+#define I2C_ICR_ADDRCF_Pos (3U)\r
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */\r
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */\r
+#define I2C_ICR_NACKCF_Pos (4U)\r
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */\r
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */\r
+#define I2C_ICR_STOPCF_Pos (5U)\r
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */\r
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */\r
+#define I2C_ICR_BERRCF_Pos (8U)\r
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */\r
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */\r
+#define I2C_ICR_ARLOCF_Pos (9U)\r
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */\r
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF_Pos (10U)\r
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */\r
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF_Pos (11U)\r
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */\r
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */\r
+#define I2C_ICR_TIMOUTCF_Pos (12U)\r
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */\r
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */\r
+#define I2C_ICR_ALERTCF_Pos (13U)\r
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */\r
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */\r
+\r
+/****************** Bit definition for I2C_PECR register *********************/\r
+#define I2C_PECR_PEC_Pos (0U)\r
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */\r
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */\r
+\r
+/****************** Bit definition for I2C_RXDR register *********************/\r
+#define I2C_RXDR_RXDATA_Pos (0U)\r
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */\r
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */\r
+\r
+/****************** Bit definition for I2C_TXDR register *********************/\r
+#define I2C_TXDR_TXDATA_Pos (0U)\r
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */\r
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY_Pos (0U)\r
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */\r
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR_Pos (0U)\r
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */\r
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */\r
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */\r
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL_Pos (0U)\r
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */\r
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU_Pos (0U)\r
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */\r
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU_Pos (1U)\r
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */\r
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU_Pos (2U)\r
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */\r
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_WINR_WIN_Pos (0U)\r
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */\r
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* JPEG Encoder/Decoder */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for CONFR0 register ********************/\r
+#define JPEG_CONFR0_START_Pos (0U)\r
+#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */\r
+\r
+/******************** Bit definition for CONFR1 register ********************/\r
+#define JPEG_CONFR1_NF_Pos (0U)\r
+#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */\r
+#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */\r
+#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR1_DE_Pos (3U)\r
+#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */\r
+#define JPEG_CONFR1_COLORSPACE_Pos (4U)\r
+#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */\r
+#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */\r
+#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR1_NS_Pos (6U)\r
+#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */\r
+#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */\r
+#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR1_HDR_Pos (8U)\r
+#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */\r
+#define JPEG_CONFR1_YSIZE_Pos (16U)\r
+#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */\r
+#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */\r
+\r
+/******************** Bit definition for CONFR2 register ********************/\r
+#define JPEG_CONFR2_NMCU_Pos (0U)\r
+#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */\r
+#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */\r
+\r
+/******************** Bit definition for CONFR3 register ********************/\r
+#define JPEG_CONFR3_XSIZE_Pos (16U)\r
+#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */\r
+#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */\r
+\r
+/******************** Bit definition for CONFR4 register ********************/\r
+#define JPEG_CONFR4_HD_Pos (0U)\r
+#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR4_HA_Pos (1U)\r
+#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR4_QT_Pos (2U)\r
+#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR4_NB_Pos (4U)\r
+#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR4_VSF_Pos (8U)\r
+#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */\r
+#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR4_HSF_Pos (12U)\r
+#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */\r
+#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CONFR5 register ********************/\r
+#define JPEG_CONFR5_HD_Pos (0U)\r
+#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR5_HA_Pos (1U)\r
+#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR5_QT_Pos (2U)\r
+#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR5_NB_Pos (4U)\r
+#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR5_VSF_Pos (8U)\r
+#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR5_HSF_Pos (12U)\r
+#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CONFR6 register ********************/\r
+#define JPEG_CONFR6_HD_Pos (0U)\r
+#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR6_HA_Pos (1U)\r
+#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR6_QT_Pos (2U)\r
+#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR6_NB_Pos (4U)\r
+#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR6_VSF_Pos (8U)\r
+#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR6_HSF_Pos (12U)\r
+#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CONFR7 register ********************/\r
+#define JPEG_CONFR7_HD_Pos (0U)\r
+#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR7_HA_Pos (1U)\r
+#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR7_QT_Pos (2U)\r
+#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR7_NB_Pos (4U)\r
+#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR7_VSF_Pos (8U)\r
+#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR7_HSF_Pos (12U)\r
+#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CR register ********************/\r
+#define JPEG_CR_JCEN_Pos (0U)\r
+#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */\r
+#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */\r
+#define JPEG_CR_IFTIE_Pos (1U)\r
+#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */\r
+#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */\r
+#define JPEG_CR_IFNFIE_Pos (2U)\r
+#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */\r
+#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */\r
+#define JPEG_CR_OFTIE_Pos (3U)\r
+#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */\r
+#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */\r
+#define JPEG_CR_OFNEIE_Pos (4U)\r
+#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */\r
+#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */\r
+#define JPEG_CR_EOCIE_Pos (5U)\r
+#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */\r
+#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */\r
+#define JPEG_CR_HPDIE_Pos (6U)\r
+#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */\r
+#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */\r
+#define JPEG_CR_IFF_Pos (13U)\r
+#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */\r
+#define JPEG_CR_OFF_Pos (14U)\r
+#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */\r
+\r
+/******************** Bit definition for SR register ********************/\r
+#define JPEG_SR_IFTF_Pos (1U)\r
+#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */\r
+#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */\r
+#define JPEG_SR_IFNFF_Pos (2U)\r
+#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */\r
+#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */\r
+#define JPEG_SR_OFTF_Pos (3U)\r
+#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */\r
+#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */\r
+#define JPEG_SR_OFNEF_Pos (4U)\r
+#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */\r
+#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */\r
+#define JPEG_SR_EOCF_Pos (5U)\r
+#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */\r
+#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */\r
+#define JPEG_SR_HPDF_Pos (6U)\r
+#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */\r
+#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */\r
+#define JPEG_SR_COF_Pos (7U)\r
+#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */\r
+#define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */\r
+\r
+/******************** Bit definition for CFR register ********************/\r
+#define JPEG_CFR_CEOCF_Pos (4U)\r
+#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */\r
+#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */\r
+#define JPEG_CFR_CHPDF_Pos (5U)\r
+#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */\r
+#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */\r
+\r
+/******************** Bit definition for DIR register ********************/\r
+#define JPEG_DIR_DATAIN_Pos (0U)\r
+#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */\r
+#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */\r
+\r
+/******************** Bit definition for DOR register ********************/\r
+#define JPEG_DOR_DATAOUT_Pos (0U)\r
+#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */\r
+#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD-TFT Display Controller (LTDC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for LTDC_SSCR register *****************/\r
+\r
+#define LTDC_SSCR_VSH_Pos (0U)\r
+#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */\r
+#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */\r
+#define LTDC_SSCR_HSW_Pos (16U)\r
+#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */\r
+\r
+/******************** Bit definition for LTDC_BPCR register *****************/\r
+\r
+#define LTDC_BPCR_AVBP_Pos (0U)\r
+#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */\r
+#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */\r
+#define LTDC_BPCR_AHBP_Pos (16U)\r
+#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */\r
+\r
+/******************** Bit definition for LTDC_AWCR register *****************/\r
+\r
+#define LTDC_AWCR_AAH_Pos (0U)\r
+#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */\r
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */\r
+#define LTDC_AWCR_AAW_Pos (16U)\r
+#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */\r
+\r
+/******************** Bit definition for LTDC_TWCR register *****************/\r
+\r
+#define LTDC_TWCR_TOTALH_Pos (0U)\r
+#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */\r
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */\r
+#define LTDC_TWCR_TOTALW_Pos (16U)\r
+#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */\r
+\r
+/******************** Bit definition for LTDC_GCR register ******************/\r
+\r
+#define LTDC_GCR_LTDCEN_Pos (0U)\r
+#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */\r
+#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */\r
+#define LTDC_GCR_DBW_Pos (4U)\r
+#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */\r
+#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */\r
+#define LTDC_GCR_DGW_Pos (8U)\r
+#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */\r
+#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */\r
+#define LTDC_GCR_DRW_Pos (12U)\r
+#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */\r
+#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */\r
+#define LTDC_GCR_DEN_Pos (16U)\r
+#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */\r
+#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */\r
+#define LTDC_GCR_PCPOL_Pos (28U)\r
+#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */\r
+#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */\r
+#define LTDC_GCR_DEPOL_Pos (29U)\r
+#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */\r
+#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */\r
+#define LTDC_GCR_VSPOL_Pos (30U)\r
+#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */\r
+#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */\r
+#define LTDC_GCR_HSPOL_Pos (31U)\r
+#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */\r
+#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */\r
+\r
+\r
+/******************** Bit definition for LTDC_SRCR register *****************/\r
+\r
+#define LTDC_SRCR_IMR_Pos (0U)\r
+#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */\r
+#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */\r
+#define LTDC_SRCR_VBR_Pos (1U)\r
+#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */\r
+#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */\r
+\r
+/******************** Bit definition for LTDC_BCCR register *****************/\r
+\r
+#define LTDC_BCCR_BCBLUE_Pos (0U)\r
+#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */\r
+#define LTDC_BCCR_BCGREEN_Pos (8U)\r
+#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */\r
+#define LTDC_BCCR_BCRED_Pos (16U)\r
+#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */\r
+\r
+/******************** Bit definition for LTDC_IER register ******************/\r
+\r
+#define LTDC_IER_LIE_Pos (0U)\r
+#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */\r
+#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */\r
+#define LTDC_IER_FUIE_Pos (1U)\r
+#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */\r
+#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */\r
+#define LTDC_IER_TERRIE_Pos (2U)\r
+#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */\r
+#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */\r
+#define LTDC_IER_RRIE_Pos (3U)\r
+#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */\r
+#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */\r
+\r
+/******************** Bit definition for LTDC_ISR register ******************/\r
+\r
+#define LTDC_ISR_LIF_Pos (0U)\r
+#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */\r
+#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */\r
+#define LTDC_ISR_FUIF_Pos (1U)\r
+#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */\r
+#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */\r
+#define LTDC_ISR_TERRIF_Pos (2U)\r
+#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */\r
+#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */\r
+#define LTDC_ISR_RRIF_Pos (3U)\r
+#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */\r
+#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_ICR register ******************/\r
+\r
+#define LTDC_ICR_CLIF_Pos (0U)\r
+#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */\r
+#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */\r
+#define LTDC_ICR_CFUIF_Pos (1U)\r
+#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */\r
+#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */\r
+#define LTDC_ICR_CTERRIF_Pos (2U)\r
+#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */\r
+#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */\r
+#define LTDC_ICR_CRRIF_Pos (3U)\r
+#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */\r
+#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_LIPCR register ****************/\r
+\r
+#define LTDC_LIPCR_LIPOS_Pos (0U)\r
+#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */\r
+#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */\r
+\r
+/******************** Bit definition for LTDC_CPSR register *****************/\r
+\r
+#define LTDC_CPSR_CYPOS_Pos (0U)\r
+#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */\r
+#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */\r
+#define LTDC_CPSR_CXPOS_Pos (16U)\r
+#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */\r
+#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */\r
+\r
+/******************** Bit definition for LTDC_CDSR register *****************/\r
+\r
+#define LTDC_CDSR_VDES_Pos (0U)\r
+#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */\r
+#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */\r
+#define LTDC_CDSR_HDES_Pos (1U)\r
+#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */\r
+#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */\r
+#define LTDC_CDSR_VSYNCS_Pos (2U)\r
+#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */\r
+#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */\r
+#define LTDC_CDSR_HSYNCS_Pos (3U)\r
+#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */\r
+#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */\r
+\r
+/******************** Bit definition for LTDC_LxCR register *****************/\r
+\r
+#define LTDC_LxCR_LEN_Pos (0U)\r
+#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */\r
+#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */\r
+#define LTDC_LxCR_COLKEN_Pos (1U)\r
+#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */\r
+#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */\r
+#define LTDC_LxCR_CLUTEN_Pos (4U)\r
+#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */\r
+#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */\r
+\r
+/******************** Bit definition for LTDC_LxWHPCR register **************/\r
+\r
+#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)\r
+#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */\r
+#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */\r
+#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)\r
+#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */\r
+#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxWVPCR register **************/\r
+\r
+#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)\r
+#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */\r
+#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */\r
+#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)\r
+#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */\r
+#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxCKCR register ***************/\r
+\r
+#define LTDC_LxCKCR_CKBLUE_Pos (0U)\r
+#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */\r
+#define LTDC_LxCKCR_CKGREEN_Pos (8U)\r
+#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */\r
+#define LTDC_LxCKCR_CKRED_Pos (16U)\r
+#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */\r
+\r
+/******************** Bit definition for LTDC_LxPFCR register ***************/\r
+\r
+#define LTDC_LxPFCR_PF_Pos (0U)\r
+#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */\r
+#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */\r
+\r
+/******************** Bit definition for LTDC_LxCACR register ***************/\r
+\r
+#define LTDC_LxCACR_CONSTA_Pos (0U)\r
+#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxDCCR register ***************/\r
+\r
+#define LTDC_LxDCCR_DCBLUE_Pos (0U)\r
+#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */\r
+#define LTDC_LxDCCR_DCGREEN_Pos (8U)\r
+#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */\r
+#define LTDC_LxDCCR_DCRED_Pos (16U)\r
+#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */\r
+#define LTDC_LxDCCR_DCALPHA_Pos (24U)\r
+#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */\r
+#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxBFCR register ***************/\r
+\r
+#define LTDC_LxBFCR_BF2_Pos (0U)\r
+#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */\r
+#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */\r
+#define LTDC_LxBFCR_BF1_Pos (8U)\r
+#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */\r
+#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */\r
+\r
+/******************** Bit definition for LTDC_LxCFBAR register **************/\r
+\r
+#define LTDC_LxCFBAR_CFBADD_Pos (0U)\r
+#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */\r
+#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLR register **************/\r
+\r
+#define LTDC_LxCFBLR_CFBLL_Pos (0U)\r
+#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */\r
+#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */\r
+#define LTDC_LxCFBLR_CFBP_Pos (16U)\r
+#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */\r
+#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLNR register *************/\r
+\r
+#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)\r
+#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */\r
+#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */\r
+\r
+/******************** Bit definition for LTDC_LxCLUTWR register *************/\r
+\r
+#define LTDC_LxCLUTWR_BLUE_Pos (0U)\r
+#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */\r
+#define LTDC_LxCLUTWR_GREEN_Pos (8U)\r
+#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */\r
+#define LTDC_LxCLUTWR_RED_Pos (16U)\r
+#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */\r
+#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)\r
+#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */\r
+#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* MDMA */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for MDMA_GISR0 register ****************/\r
+#define MDMA_GISR0_GIF0_Pos (0U)\r
+#define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */\r
+#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */\r
+#define MDMA_GISR0_GIF1_Pos (1U)\r
+#define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */\r
+#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */\r
+#define MDMA_GISR0_GIF2_Pos (2U)\r
+#define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */\r
+#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */\r
+#define MDMA_GISR0_GIF3_Pos (3U)\r
+#define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */\r
+#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */\r
+#define MDMA_GISR0_GIF4_Pos (4U)\r
+#define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */\r
+#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */\r
+#define MDMA_GISR0_GIF5_Pos (5U)\r
+#define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */\r
+#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */\r
+#define MDMA_GISR0_GIF6_Pos (6U)\r
+#define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */\r
+#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */\r
+#define MDMA_GISR0_GIF7_Pos (7U)\r
+#define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */\r
+#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */\r
+#define MDMA_GISR0_GIF8_Pos (8U)\r
+#define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */\r
+#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */\r
+#define MDMA_GISR0_GIF9_Pos (9U)\r
+#define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */\r
+#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */\r
+#define MDMA_GISR0_GIF10_Pos (10U)\r
+#define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */\r
+#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */\r
+#define MDMA_GISR0_GIF11_Pos (11U)\r
+#define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */\r
+#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */\r
+#define MDMA_GISR0_GIF12_Pos (12U)\r
+#define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */\r
+#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */\r
+#define MDMA_GISR0_GIF13_Pos (13U)\r
+#define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */\r
+#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */\r
+#define MDMA_GISR0_GIF14_Pos (14U)\r
+#define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */\r
+#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */\r
+#define MDMA_GISR0_GIF15_Pos (15U)\r
+#define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */\r
+#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */\r
+\r
+/******************** Bit definition for MDMA_CxISR register ****************/\r
+#define MDMA_CISR_TEIF_Pos (0U)\r
+#define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */\r
+#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */\r
+#define MDMA_CISR_CTCIF_Pos (1U)\r
+#define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */\r
+#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */\r
+#define MDMA_CISR_BRTIF_Pos (2U)\r
+#define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */\r
+#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */\r
+#define MDMA_CISR_BTIF_Pos (3U)\r
+#define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */\r
+#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */\r
+#define MDMA_CISR_TCIF_Pos (4U)\r
+#define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */\r
+#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */\r
+#define MDMA_CISR_CRQA_Pos (16U)\r
+#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */\r
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */\r
+\r
+/******************** Bit definition for MDMA_CxIFCR register ****************/\r
+#define MDMA_CIFCR_CTEIF_Pos (0U)\r
+#define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */\r
+#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */\r
+#define MDMA_CIFCR_CCTCIF_Pos (1U)\r
+#define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */\r
+#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */\r
+#define MDMA_CIFCR_CBRTIF_Pos (2U)\r
+#define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */\r
+#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */\r
+#define MDMA_CIFCR_CBTIF_Pos (3U)\r
+#define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */\r
+#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */\r
+#define MDMA_CIFCR_CLTCIF_Pos (4U)\r
+#define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */\r
+#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */\r
+\r
+/******************** Bit definition for MDMA_CxESR register ****************/\r
+#define MDMA_CESR_TEA_Pos (0U)\r
+#define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */\r
+#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */\r
+#define MDMA_CESR_TED_Pos (7U)\r
+#define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */\r
+#define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */\r
+#define MDMA_CESR_TELD_Pos (8U)\r
+#define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */\r
+#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */\r
+#define MDMA_CESR_TEMD_Pos (9U)\r
+#define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */\r
+#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */\r
+#define MDMA_CESR_ASE_Pos (10U)\r
+#define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */\r
+#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */\r
+#define MDMA_CESR_BSE_Pos (11U)\r
+#define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */\r
+#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */\r
+\r
+/******************** Bit definition for MDMA_CxCR register ****************/\r
+#define MDMA_CCR_EN_Pos (0U)\r
+#define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */\r
+#define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */\r
+#define MDMA_CCR_TEIE_Pos (1U)\r
+#define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */\r
+#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */\r
+#define MDMA_CCR_CTCIE_Pos (2U)\r
+#define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */\r
+#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */\r
+#define MDMA_CCR_BRTIE_Pos (3U)\r
+#define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */\r
+#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */\r
+#define MDMA_CCR_BTIE_Pos (4U)\r
+#define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */\r
+#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */\r
+#define MDMA_CCR_TCIE_Pos (5U)\r
+#define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */\r
+#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */\r
+#define MDMA_CCR_PL_Pos (6U)\r
+#define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */\r
+#define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */\r
+#define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */\r
+#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */\r
+#define MDMA_CCR_BEX_Pos (12U)\r
+#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */\r
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */\r
+#define MDMA_CCR_HEX_Pos (13U)\r
+#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */\r
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */\r
+#define MDMA_CCR_WEX_Pos (14U)\r
+#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */\r
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */\r
+#define MDMA_CCR_SWRQ_Pos (16U)\r
+#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */\r
+#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */\r
+\r
+/******************** Bit definition for MDMA_CxTCR register ****************/\r
+#define MDMA_CTCR_SINC_Pos (0U)\r
+#define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */\r
+#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */\r
+#define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */\r
+#define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */\r
+#define MDMA_CTCR_DINC_Pos (2U)\r
+#define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */\r
+#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */\r
+#define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */\r
+#define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */\r
+#define MDMA_CTCR_SSIZE_Pos (4U)\r
+#define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */\r
+#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */\r
+#define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */\r
+#define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */\r
+#define MDMA_CTCR_DSIZE_Pos (6U)\r
+#define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */\r
+#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */\r
+#define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */\r
+#define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */\r
+#define MDMA_CTCR_SINCOS_Pos (8U)\r
+#define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */\r
+#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */\r
+#define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */\r
+#define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */\r
+#define MDMA_CTCR_DINCOS_Pos (10U)\r
+#define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */\r
+#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */\r
+#define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */\r
+#define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */\r
+#define MDMA_CTCR_SBURST_Pos (12U)\r
+#define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */\r
+#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */\r
+#define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */\r
+#define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */\r
+#define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */\r
+#define MDMA_CTCR_DBURST_Pos (15U)\r
+#define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */\r
+#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */\r
+#define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */\r
+#define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */\r
+#define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */\r
+#define MDMA_CTCR_TLEN_Pos (18U)\r
+#define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */\r
+#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */\r
+#define MDMA_CTCR_PKE_Pos (25U)\r
+#define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */\r
+#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */\r
+#define MDMA_CTCR_PAM_Pos (26U)\r
+#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */\r
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */\r
+#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */\r
+#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */\r
+#define MDMA_CTCR_TRGM_Pos (28U)\r
+#define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */\r
+#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */\r
+#define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */\r
+#define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */\r
+#define MDMA_CTCR_SWRM_Pos (30U)\r
+#define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */\r
+#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */\r
+#define MDMA_CTCR_BWM_Pos (31U)\r
+#define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */\r
+#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */\r
+\r
+/******************** Bit definition for MDMA_CxBNDTR register ****************/\r
+#define MDMA_CBNDTR_BNDT_Pos (0U)\r
+#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */\r
+#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */\r
+#define MDMA_CBNDTR_BRSUM_Pos (18U)\r
+#define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */\r
+#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */\r
+#define MDMA_CBNDTR_BRDUM_Pos (19U)\r
+#define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */\r
+#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */\r
+#define MDMA_CBNDTR_BRC_Pos (20U)\r
+#define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */\r
+#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */\r
+\r
+/******************** Bit definition for MDMA_CxSAR register ****************/\r
+#define MDMA_CSAR_SAR_Pos (0U)\r
+#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */\r
+#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */\r
+\r
+/******************** Bit definition for MDMA_CxDAR register ****************/\r
+#define MDMA_CDAR_DAR_Pos (0U)\r
+#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */\r
+#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */\r
+\r
+/******************** Bit definition for MDMA_CxBRUR ************************/\r
+#define MDMA_CBRUR_SUV_Pos (0U)\r
+#define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */\r
+#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */\r
+#define MDMA_CBRUR_DUV_Pos (16U)\r
+#define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */\r
+#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */\r
+\r
+/******************** Bit definition for MDMA_CxLAR *************************/\r
+#define MDMA_CLAR_LAR_Pos (0U)\r
+#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */\r
+#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */\r
+\r
+/******************** Bit definition for MDMA_CxTBR) ************************/\r
+#define MDMA_CTBR_TSEL_Pos (0U)\r
+#define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */\r
+#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */\r
+#define MDMA_CTBR_SBUS_Pos (16U)\r
+#define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */\r
+#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */\r
+#define MDMA_CTBR_DBUS_Pos (17U)\r
+#define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */\r
+#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */\r
+\r
+/******************** Bit definition for MDMA_CxMAR) ************************/\r
+#define MDMA_CMAR_MAR_Pos (0U)\r
+#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */\r
+#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */\r
+\r
+/******************** Bit definition for MDMA_CxMDR) ************************/\r
+#define MDMA_CMDR_MDR_Pos (0U)\r
+#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */\r
+#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Operational Amplifier (OPAMP) */\r
+/* */\r
+/******************************************************************************/\r
+/********************* Bit definition for OPAMPx_CSR register ***************/\r
+#define OPAMP_CSR_OPAMPxEN_Pos (0U)\r
+#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */\r
+#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */\r
+#define OPAMP_CSR_FORCEVP_Pos (1U)\r
+#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */\r
+#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */\r
+\r
+#define OPAMP_CSR_VPSEL_Pos (2U)\r
+#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */\r
+#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */\r
+#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */\r
+#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */\r
+\r
+#define OPAMP_CSR_VMSEL_Pos (5U)\r
+#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */\r
+#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */\r
+#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */\r
+#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */\r
+\r
+#define OPAMP_CSR_OPAHSM_Pos (8U)\r
+#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */\r
+#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */\r
+#define OPAMP_CSR_CALON_Pos (11U)\r
+#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */\r
+#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */\r
+\r
+#define OPAMP_CSR_CALSEL_Pos (12U)\r
+#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */\r
+#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */\r
+#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */\r
+#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */\r
+\r
+#define OPAMP_CSR_PGGAIN_Pos (14U)\r
+#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */\r
+#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */\r
+#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */\r
+#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */\r
+#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */\r
+#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */\r
+\r
+#define OPAMP_CSR_USERTRIM_Pos (18U)\r
+#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */\r
+#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */\r
+#define OPAMP_CSR_TSTREF_Pos (29U)\r
+#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */\r
+#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */\r
+#define OPAMP_CSR_CALOUT_Pos (30U)\r
+#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */\r
+#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */\r
+\r
+/********************* Bit definition for OPAMP1_CSR register ***************/\r
+#define OPAMP1_CSR_OPAEN_Pos (0U)\r
+#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */\r
+#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */\r
+#define OPAMP1_CSR_FORCEVP_Pos (1U)\r
+#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */\r
+#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */\r
+\r
+#define OPAMP1_CSR_VPSEL_Pos (2U)\r
+#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */\r
+#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */\r
+#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */\r
+#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */\r
+\r
+#define OPAMP1_CSR_VMSEL_Pos (5U)\r
+#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */\r
+#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */\r
+#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */\r
+#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */\r
+\r
+#define OPAMP1_CSR_OPAHSM_Pos (8U)\r
+#define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */\r
+#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */\r
+#define OPAMP1_CSR_CALON_Pos (11U)\r
+#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */\r
+#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */\r
+\r
+#define OPAMP1_CSR_CALSEL_Pos (12U)\r
+#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */\r
+#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */\r
+#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */\r
+#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */\r
+\r
+#define OPAMP1_CSR_PGGAIN_Pos (14U)\r
+#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */\r
+#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */\r
+#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */\r
+#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */\r
+#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */\r
+#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */\r
+\r
+#define OPAMP1_CSR_USERTRIM_Pos (18U)\r
+#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */\r
+#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */\r
+#define OPAMP1_CSR_TSTREF_Pos (29U)\r
+#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */\r
+#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */\r
+#define OPAMP1_CSR_CALOUT_Pos (30U)\r
+#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */\r
+#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */\r
+\r
+/********************* Bit definition for OPAMP2_CSR register ***************/\r
+#define OPAMP2_CSR_OPAEN_Pos (0U)\r
+#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */\r
+#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */\r
+#define OPAMP2_CSR_FORCEVP_Pos (1U)\r
+#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */\r
+#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */\r
+\r
+#define OPAMP2_CSR_VPSEL_Pos (2U)\r
+#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */\r
+#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */\r
+#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */\r
+#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */\r
+\r
+#define OPAMP2_CSR_VMSEL_Pos (5U)\r
+#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */\r
+#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */\r
+#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */\r
+#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */\r
+\r
+#define OPAMP2_CSR_OPAHSM_Pos (8U)\r
+#define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */\r
+#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */\r
+#define OPAMP2_CSR_CALON_Pos (11U)\r
+#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */\r
+#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */\r
+\r
+#define OPAMP2_CSR_CALSEL_Pos (12U)\r
+#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */\r
+#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */\r
+#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */\r
+#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */\r
+\r
+#define OPAMP2_CSR_PGGAIN_Pos (14U)\r
+#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */\r
+#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */\r
+#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */\r
+#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */\r
+#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */\r
+#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */\r
+\r
+#define OPAMP2_CSR_USERTRIM_Pos (18U)\r
+#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */\r
+#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */\r
+#define OPAMP2_CSR_TSTREF_Pos (29U)\r
+#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */\r
+#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */\r
+#define OPAMP2_CSR_CALOUT_Pos (30U)\r
+#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */\r
+#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */\r
+\r
+/******************* Bit definition for OPAMP_OTR register ******************/\r
+#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)\r
+#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */\r
+#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)\r
+#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */\r
+\r
+/******************* Bit definition for OPAMP1_OTR register ******************/\r
+#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)\r
+#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */\r
+#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)\r
+#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */\r
+\r
+/******************* Bit definition for OPAMP2_OTR register ******************/\r
+#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)\r
+#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */\r
+#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)\r
+#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */\r
+\r
+/******************* Bit definition for OPAMP_HSOTR register ****************/\r
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)\r
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */\r
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)\r
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */\r
+\r
+/******************* Bit definition for OPAMP1_HSOTR register ****************/\r
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)\r
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */\r
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)\r
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */\r
+\r
+/******************* Bit definition for OPAMP2_HSOTR register ****************/\r
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)\r
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r
+#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */\r
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)\r
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r
+#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for PWR_CR1 register ********************/\r
+#define PWR_CR1_ALS_Pos (17U)\r
+#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */\r
+#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */\r
+#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */\r
+#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */\r
+#define PWR_CR1_AVDEN_Pos (16U)\r
+#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */\r
+#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */\r
+#define PWR_CR1_SVOS_Pos (14U)\r
+#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */\r
+#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */\r
+#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */\r
+#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */\r
+#define PWR_CR1_FLPS_Pos (9U)\r
+#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */\r
+#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */\r
+#define PWR_CR1_DBP_Pos (8U)\r
+#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */\r
+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */\r
+#define PWR_CR1_PLS_Pos (5U)\r
+#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */\r
+#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */\r
+#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */\r
+#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */\r
+#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */\r
+#define PWR_CR1_PVDEN_Pos (4U)\r
+#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */\r
+#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable. */\r
+#define PWR_CR1_LPDS_Pos (0U)\r
+#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */\r
+#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */\r
+#define PWR_CR1_PLS_LEV1_Pos (5U)\r
+#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */\r
+#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */\r
+#define PWR_CR1_PLS_LEV2_Pos (6U)\r
+#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */\r
+#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */\r
+#define PWR_CR1_PLS_LEV3_Pos (5U)\r
+#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */\r
+#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */\r
+#define PWR_CR1_PLS_LEV4_Pos (7U)\r
+#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */\r
+#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */\r
+#define PWR_CR1_PLS_LEV5_Pos (5U)\r
+#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */\r
+#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */\r
+#define PWR_CR1_PLS_LEV6_Pos (6U)\r
+#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */\r
+#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */\r
+#define PWR_CR1_PLS_LEV7_Pos (5U)\r
+#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */\r
+#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */\r
+\r
+/*!< AVD level configuration */\r
+#define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */\r
+#define PWR_CR1_ALS_LEV1_Pos (17U)\r
+#define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */\r
+#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */\r
+#define PWR_CR1_ALS_LEV2_Pos (18U)\r
+#define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */\r
+#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */\r
+#define PWR_CR1_ALS_LEV3_Pos (17U)\r
+#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */\r
+#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */\r
+\r
+/******************** Bit definition for PWR_CSR1 register ********************/\r
+#define PWR_CSR1_AVDO_Pos (16U)\r
+#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */\r
+#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */\r
+#define PWR_CSR1_ACTVOS_Pos (14U)\r
+#define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */\r
+#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */\r
+#define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */\r
+#define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */\r
+#define PWR_CSR1_ACTVOSRDY_Pos (13U)\r
+#define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */\r
+#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */\r
+#define PWR_CSR1_PVDO_Pos (4U)\r
+#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */\r
+#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */\r
+\r
+/******************** Bit definition for PWR_CR2 register ********************/\r
+#define PWR_CR2_TEMPH_Pos (23U)\r
+#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */\r
+#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */\r
+#define PWR_CR2_TEMPL_Pos (22U)\r
+#define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */\r
+#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */\r
+#define PWR_CR2_VBATH_Pos (21U)\r
+#define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */\r
+#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */\r
+#define PWR_CR2_VBATL_Pos (20U)\r
+#define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */\r
+#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */\r
+#define PWR_CR2_BRRDY_Pos (16U)\r
+#define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */\r
+#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */\r
+#define PWR_CR2_MONEN_Pos (4U)\r
+#define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */\r
+#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */\r
+#define PWR_CR2_BREN_Pos (0U)\r
+#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */\r
+#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */\r
+\r
+/******************** Bit definition for PWR_CR3 register ********************/\r
+#define PWR_CR3_USB33RDY_Pos (26U)\r
+#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */\r
+#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */\r
+#define PWR_CR3_USBREGEN_Pos (25U)\r
+#define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */\r
+#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */\r
+#define PWR_CR3_USB33DEN_Pos (24U)\r
+#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */\r
+#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */\r
+#define PWR_CR3_SMPSEXTRDY_Pos (16U)\r
+#define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos) /*!< 0x00010000 */\r
+#define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk /*!< SMPS External supply ready */\r
+#define PWR_CR3_VBRS_Pos (9U)\r
+#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */\r
+#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */\r
+#define PWR_CR3_VBE_Pos (8U)\r
+#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */\r
+#define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */\r
+#define PWR_CR3_SMPSLEVEL_Pos (4U)\r
+#define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000030 */\r
+#define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk /*!< SMPS output Voltage */\r
+#define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000010 */\r
+#define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000020 */\r
+#define PWR_CR3_SMPSEXTHP_Pos (3U)\r
+#define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos) /*!< 0x00000008 */\r
+#define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk /*!< SMPS forced ON and in High Power MR mode */\r
+#define PWR_CR3_SMPSEN_Pos (2U)\r
+#define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos) /*!< 0x00000004 */\r
+#define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk /*!< SMPS Enable */\r
+#define PWR_CR3_LDOEN_Pos (1U)\r
+#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */\r
+#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */\r
+#define PWR_CR3_BYPASS_Pos (0U)\r
+#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */\r
+#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */\r
+\r
+/******************** Bit definition for PWR_CPUCR register ********************/\r
+#define PWR_CPUCR_RUN_D3_Pos (11U)\r
+#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */\r
+#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */\r
+#define PWR_CPUCR_HOLD2_Pos (10U)\r
+#define PWR_CPUCR_HOLD2_Msk (0x1UL << PWR_CPUCR_HOLD2_Pos) /*!< 0x00000400 */\r
+#define PWR_CPUCR_HOLD2 PWR_CPUCR_HOLD2_Msk /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */\r
+#define PWR_CPUCR_CSSF_Pos (9U)\r
+#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */\r
+#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */\r
+#define PWR_CPUCR_SBF_D2_Pos (8U)\r
+#define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) /*!< 0x00000100 */\r
+#define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */\r
+#define PWR_CPUCR_SBF_D1_Pos (7U)\r
+#define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) /*!< 0x00000080 */\r
+#define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */\r
+#define PWR_CPUCR_SBF_Pos (6U)\r
+#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */\r
+#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */\r
+#define PWR_CPUCR_STOPF_Pos (5U)\r
+#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */\r
+#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */\r
+#define PWR_CPUCR_HOLD2F_Pos (4U)\r
+#define PWR_CPUCR_HOLD2F_Msk (0x1UL << PWR_CPUCR_HOLD2F_Pos) /*!< 0x00000010 */\r
+#define PWR_CPUCR_HOLD2F PWR_CPUCR_HOLD2F_Msk /*!< CPU2 in hold wakeup flag */\r
+#define PWR_CPUCR_PDDS_D3_Pos (2U)\r
+#define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) /*!< 0x00000004 */\r
+#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */\r
+#define PWR_CPUCR_PDDS_D2_Pos (1U)\r
+#define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) /*!< 0x00000002 */\r
+#define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */\r
+#define PWR_CPUCR_PDDS_D1_Pos (0U)\r
+#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */\r
+#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */\r
+\r
+/******************** Bit definition for PWR_CPU2CR register ********************/\r
+#define PWR_CPU2CR_RUN_D3_Pos (11U)\r
+#define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos) /*!< 0x00000800 */\r
+#define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */\r
+#define PWR_CPU2CR_HOLD1_Pos (10U)\r
+#define PWR_CPU2CR_HOLD1_Msk (0x1UL << PWR_CPU2CR_HOLD1_Pos) /*!< 0x00000400 */\r
+#define PWR_CPU2CR_HOLD1 PWR_CPU2CR_HOLD1_Msk /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */\r
+#define PWR_CPU2CR_CSSF_Pos (9U)\r
+#define PWR_CPU2CR_CSSF_Msk (0x1UL << PWR_CPU2CR_CSSF_Pos) /*!< 0x00000200 */\r
+#define PWR_CPU2CR_CSSF PWR_CPU2CR_CSSF_Msk /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */\r
+#define PWR_CPU2CR_SBF_D2_Pos (8U)\r
+#define PWR_CPU2CR_SBF_D2_Msk (0x1UL << PWR_CPU2CR_SBF_D2_Pos) /*!< 0x00000100 */\r
+#define PWR_CPU2CR_SBF_D2 PWR_CPU2CR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */\r
+#define PWR_CPU2CR_SBF_D1_Pos (7U)\r
+#define PWR_CPU2CR_SBF_D1_Msk (0x1UL << PWR_CPU2CR_SBF_D1_Pos) /*!< 0x00000080 */\r
+#define PWR_CPU2CR_SBF_D1 PWR_CPU2CR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */\r
+#define PWR_CPU2CR_SBF_Pos (6U)\r
+#define PWR_CPU2CR_SBF_Msk (0x1UL << PWR_CPU2CR_SBF_Pos) /*!< 0x00000040 */\r
+#define PWR_CPU2CR_SBF PWR_CPU2CR_SBF_Msk /*!< System STANDBY Flag */\r
+#define PWR_CPU2CR_STOPF_Pos (5U)\r
+#define PWR_CPU2CR_STOPF_Msk (0x1UL << PWR_CPU2CR_STOPF_Pos) /*!< 0x00000020 */\r
+#define PWR_CPU2CR_STOPF PWR_CPU2CR_STOPF_Msk /*!< STOP Flag */\r
+#define PWR_CPU2CR_HOLD1F_Pos (4U)\r
+#define PWR_CPU2CR_HOLD1F_Msk (0x1UL << PWR_CPU2CR_HOLD1F_Pos) /*!< 0x00000010 */\r
+#define PWR_CPU2CR_HOLD1F PWR_CPU2CR_HOLD1F_Msk /*!< CPU1 in hold wakeup flag */\r
+#define PWR_CPU2CR_PDDS_D3_Pos (2U)\r
+#define PWR_CPU2CR_PDDS_D3_Msk (0x1UL << PWR_CPU2CR_PDDS_D3_Pos) /*!< 0x00000004 */\r
+#define PWR_CPU2CR_PDDS_D3 PWR_CPU2CR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */\r
+#define PWR_CPU2CR_PDDS_D2_Pos (1U)\r
+#define PWR_CPU2CR_PDDS_D2_Msk (0x1UL << PWR_CPU2CR_PDDS_D2_Pos) /*!< 0x00000002 */\r
+#define PWR_CPU2CR_PDDS_D2 PWR_CPU2CR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */\r
+#define PWR_CPU2CR_PDDS_D1_Pos (0U)\r
+#define PWR_CPU2CR_PDDS_D1_Msk (0x1UL << PWR_CPU2CR_PDDS_D1_Pos) /*!< 0x00000001 */\r
+#define PWR_CPU2CR_PDDS_D1 PWR_CPU2CR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */\r
+\r
+/******************** Bit definition for PWR_D3CR register ********************/\r
+#define PWR_D3CR_VOS_Pos (14U)\r
+#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */\r
+#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */\r
+#define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) /*!< 0x00004000 */\r
+#define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) /*!< 0x00008000 */\r
+#define PWR_D3CR_VOSRDY_Pos (13U)\r
+#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */\r
+#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */\r
+\r
+/******************** Bit definition for PWR_WKUPCR register ********************/\r
+#define PWR_WKUPCR_WKUPC6_Pos (5U)\r
+#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */\r
+#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */\r
+#define PWR_WKUPCR_WKUPC5_Pos (4U)\r
+#define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */\r
+#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */\r
+#define PWR_WKUPCR_WKUPC4_Pos (3U)\r
+#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */\r
+#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */\r
+#define PWR_WKUPCR_WKUPC3_Pos (2U)\r
+#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */\r
+#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */\r
+#define PWR_WKUPCR_WKUPC2_Pos (1U)\r
+#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */\r
+#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */\r
+#define PWR_WKUPCR_WKUPC1_Pos (0U)\r
+#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */\r
+#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */\r
+\r
+/******************** Bit definition for PWR_WKUPFR register ********************/\r
+#define PWR_WKUPFR_WKUPF6_Pos (5U)\r
+#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */\r
+#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */\r
+#define PWR_WKUPFR_WKUPF5_Pos (4U)\r
+#define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */\r
+#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */\r
+#define PWR_WKUPFR_WKUPF4_Pos (3U)\r
+#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */\r
+#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */\r
+#define PWR_WKUPFR_WKUPF3_Pos (2U)\r
+#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */\r
+#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */\r
+#define PWR_WKUPFR_WKUPF2_Pos (1U)\r
+#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */\r
+#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */\r
+#define PWR_WKUPFR_WKUPF1_Pos (0U)\r
+#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */\r
+#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */\r
+\r
+/******************** Bit definition for PWR_WKUPEPR register ********************/\r
+#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)\r
+#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */\r
+#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */\r
+#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */\r
+#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */\r
+#define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)\r
+#define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */\r
+#define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */\r
+#define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */\r
+#define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */\r
+#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)\r
+#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */\r
+#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */\r
+#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */\r
+#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */\r
+#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)\r
+#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */\r
+#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */\r
+#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */\r
+#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */\r
+#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)\r
+#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */\r
+#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */\r
+#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */\r
+#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */\r
+#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)\r
+#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */\r
+#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */\r
+#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */\r
+#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */\r
+#define PWR_WKUPEPR_WKUPP6_Pos (13U)\r
+#define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */\r
+#define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */\r
+#define PWR_WKUPEPR_WKUPP5_Pos (12U)\r
+#define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */\r
+#define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */\r
+#define PWR_WKUPEPR_WKUPP4_Pos (11U)\r
+#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */\r
+#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */\r
+#define PWR_WKUPEPR_WKUPP3_Pos (10U)\r
+#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */\r
+#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */\r
+#define PWR_WKUPEPR_WKUPP2_Pos (9U)\r
+#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */\r
+#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */\r
+#define PWR_WKUPEPR_WKUPP1_Pos (8U)\r
+#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */\r
+#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */\r
+#define PWR_WKUPEPR_WKUPEN6_Pos (5U)\r
+#define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */\r
+#define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */\r
+#define PWR_WKUPEPR_WKUPEN5_Pos (4U)\r
+#define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */\r
+#define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */\r
+#define PWR_WKUPEPR_WKUPEN4_Pos (3U)\r
+#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */\r
+#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */\r
+#define PWR_WKUPEPR_WKUPEN3_Pos (2U)\r
+#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */\r
+#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */\r
+#define PWR_WKUPEPR_WKUPEN2_Pos (1U)\r
+#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */\r
+#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */\r
+#define PWR_WKUPEPR_WKUPEN1_Pos (0U)\r
+#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */\r
+#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */\r
+#define PWR_WKUPEPR_WKUPEN_Pos (0U)\r
+#define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */\r
+#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION_Pos (0U)\r
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */\r
+#define RCC_CR_HSIKERON_Pos (1U)\r
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */\r
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */\r
+#define RCC_CR_HSIRDY_Pos (2U)\r
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */\r
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */\r
+#define RCC_CR_HSIDIV_Pos (3U)\r
+#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */\r
+#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */\r
+#define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */\r
+#define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */\r
+#define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */\r
+#define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */\r
+\r
+#define RCC_CR_HSIDIVF_Pos (5U)\r
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */\r
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */\r
+#define RCC_CR_CSION_Pos (7U)\r
+#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */\r
+#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */\r
+#define RCC_CR_CSIRDY_Pos (8U)\r
+#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */\r
+#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */\r
+#define RCC_CR_CSIKERON_Pos (9U)\r
+#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */\r
+#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */\r
+#define RCC_CR_HSI48ON_Pos (12U)\r
+#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */\r
+#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */\r
+#define RCC_CR_HSI48RDY_Pos (13U)\r
+#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */\r
+#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */\r
+\r
+#define RCC_CR_D1CKRDY_Pos (14U)\r
+#define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) /*!< 0x00004000 */\r
+#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk /*!< D1 domain clocks ready flag */\r
+#define RCC_CR_D2CKRDY_Pos (15U)\r
+#define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) /*!< 0x00008000 */\r
+#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk /*!< D2 domain clocks ready flag */\r
+\r
+#define RCC_CR_HSEON_Pos (16U)\r
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */\r
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */\r
+#define RCC_CR_HSERDY_Pos (17U)\r
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */\r
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */\r
+#define RCC_CR_HSEBYP_Pos (18U)\r
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */\r
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */\r
+#define RCC_CR_CSSHSEON_Pos (19U)\r
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */\r
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */\r
+\r
+\r
+#define RCC_CR_PLL1ON_Pos (24U)\r
+#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */\r
+#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */\r
+#define RCC_CR_PLL1RDY_Pos (25U)\r
+#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */\r
+#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */\r
+#define RCC_CR_PLL2ON_Pos (26U)\r
+#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */\r
+#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */\r
+#define RCC_CR_PLL2RDY_Pos (27U)\r
+#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */\r
+#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */\r
+#define RCC_CR_PLL3ON_Pos (28U)\r
+#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */\r
+#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */\r
+#define RCC_CR_PLL3RDY_Pos (29U)\r
+#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */\r
+#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */\r
+\r
+/*Legacy */\r
+#define RCC_CR_PLLON_Pos (24U)\r
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */\r
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */\r
+#define RCC_CR_PLLRDY_Pos (25U)\r
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */\r
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */\r
+\r
+/******************** Bit definition for RCC_HSICFGR register ***************/\r
+/*!< HSICAL configuration */\r
+#define RCC_HSICFGR_HSICAL_Pos (0U)\r
+#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */\r
+#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */\r
+#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */\r
+#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */\r
+#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */\r
+#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */\r
+#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */\r
+#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */\r
+#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */\r
+#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */\r
+#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */\r
+#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */\r
+#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */\r
+#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */\r
+\r
+/*!< HSITRIM configuration */\r
+#define RCC_HSICFGR_HSITRIM_Pos (24U)\r
+#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */\r
+#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */\r
+#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */\r
+#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */\r
+#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */\r
+#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */\r
+#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */\r
+#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */\r
+#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */\r
+\r
+\r
+/******************** Bit definition for RCC_CRRCR register *****************/\r
+\r
+/*!< HSI48CAL configuration */\r
+#define RCC_CRRCR_HSI48CAL_Pos (0U)\r
+#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */\r
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */\r
+#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */\r
+#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */\r
+#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */\r
+#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */\r
+#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */\r
+#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */\r
+#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */\r
+#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */\r
+#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */\r
+#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */\r
+\r
+\r
+/******************** Bit definition for RCC_CSICFGR register *****************/\r
+/*!< CSICAL configuration */\r
+#define RCC_CSICFGR_CSICAL_Pos (0U)\r
+#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */\r
+#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */\r
+#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */\r
+#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */\r
+#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */\r
+#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */\r
+#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */\r
+#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */\r
+#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */\r
+#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */\r
+\r
+/*!< CSITRIM configuration */\r
+#define RCC_CSICFGR_CSITRIM_Pos (24U)\r
+#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */\r
+#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */\r
+#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */\r
+#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */\r
+#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */\r
+#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */\r
+#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */\r
+#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_Pos (0U)\r
+#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */\r
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */\r
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */\r
+#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */\r
+\r
+#define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */\r
+#define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */\r
+#define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */\r
+#define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_Pos (3U)\r
+#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */\r
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */\r
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */\r
+#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */\r
+\r
+#define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */\r
+#define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */\r
+#define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */\r
+#define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */\r
+\r
+#define RCC_CFGR_STOPWUCK_Pos (6U)\r
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */\r
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */\r
+\r
+#define RCC_CFGR_STOPKERWUCK_Pos (7U)\r
+#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */\r
+#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE_Pos (8U)\r
+#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)\r
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */\r
+#define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */\r
+#define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */\r
+#define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */\r
+#define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */\r
+#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */\r
+#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */\r
+\r
+/*!< HRTIMSEL configuration */\r
+#define RCC_CFGR_HRTIMSEL_Pos (14U)\r
+#define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)\r
+#define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk /*!< 0x00004000 */\r
+\r
+/*!< TIMPRE configuration */\r
+#define RCC_CFGR_TIMPRE_Pos (15U)\r
+#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)\r
+#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1_Pos (22U)\r
+#define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)\r
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */\r
+#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */\r
+#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */\r
+#define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */\r
+\r
+#define RCC_CFGR_MCO1PRE_Pos (18U)\r
+#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)\r
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */\r
+#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */\r
+#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */\r
+#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */\r
+#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */\r
+\r
+#define RCC_CFGR_MCO2PRE_Pos (25U)\r
+#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)\r
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */\r
+#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */\r
+#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */\r
+#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */\r
+#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */\r
+\r
+#define RCC_CFGR_MCO2_Pos (29U)\r
+#define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)\r
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */\r
+#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */\r
+#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */\r
+#define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for RCC_D1CFGR register ******************/\r
+/*!< D1HPRE configuration */\r
+#define RCC_D1CFGR_HPRE_Pos (0U)\r
+#define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) /*!< 0x0000000F */\r
+#define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */\r
+#define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000001 */\r
+#define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000002 */\r
+#define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000004 */\r
+#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */\r
+\r
+\r
+#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */\r
+#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)\r
+#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */\r
+#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */\r
+#define RCC_D1CFGR_HPRE_DIV4_Pos (0U)\r
+#define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */\r
+#define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */\r
+#define RCC_D1CFGR_HPRE_DIV8_Pos (1U)\r
+#define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */\r
+#define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */\r
+#define RCC_D1CFGR_HPRE_DIV16_Pos (0U)\r
+#define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */\r
+#define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */\r
+#define RCC_D1CFGR_HPRE_DIV64_Pos (2U)\r
+#define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */\r
+#define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */\r
+#define RCC_D1CFGR_HPRE_DIV128_Pos (0U)\r
+#define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */\r
+#define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */\r
+#define RCC_D1CFGR_HPRE_DIV256_Pos (1U)\r
+#define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */\r
+#define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */\r
+#define RCC_D1CFGR_HPRE_DIV512_Pos (0U)\r
+#define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */\r
+#define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */\r
+\r
+/*!< D1PPRE configuration */\r
+#define RCC_D1CFGR_D1PPRE_Pos (4U)\r
+#define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */\r
+#define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits (APB3 prescaler) */\r
+#define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */\r
+#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */\r
+#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */\r
+\r
+#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */\r
+#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)\r
+#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */\r
+#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */\r
+#define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)\r
+#define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */\r
+#define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk /*!< APB3 clock divided by 4 */\r
+#define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)\r
+#define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */\r
+#define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk /*!< APB3 clock divided by 8 */\r
+#define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)\r
+#define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */\r
+#define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk /*!< APB3 clock divided by 16 */\r
+\r
+#define RCC_D1CFGR_D1CPRE_Pos (8U)\r
+#define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */\r
+#define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */\r
+#define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */\r
+#define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */\r
+#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */\r
+#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */\r
+\r
+#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */\r
+#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)\r
+#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */\r
+#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */\r
+#define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)\r
+#define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */\r
+#define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */\r
+#define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)\r
+#define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */\r
+#define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */\r
+#define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)\r
+#define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */\r
+#define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */\r
+#define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)\r
+#define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */\r
+#define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */\r
+#define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)\r
+#define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */\r
+#define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */\r
+#define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)\r
+#define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */\r
+#define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */\r
+#define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)\r
+#define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */\r
+#define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */\r
+\r
+/******************** Bit definition for RCC_D2CFGR register ******************/\r
+/*!< D2PPRE1 configuration */\r
+#define RCC_D2CFGR_D2PPRE1_Pos (4U)\r
+#define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */\r
+#define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */\r
+#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */\r
+#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */\r
+\r
+#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */\r
+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)\r
+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */\r
+#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */\r
+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)\r
+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */\r
+#define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */\r
+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)\r
+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */\r
+#define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */\r
+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)\r
+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */\r
+#define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */\r
+\r
+/*!< D2PPRE2 configuration */\r
+#define RCC_D2CFGR_D2PPRE2_Pos (8U)\r
+#define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */\r
+#define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk /*!< D2PPRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */\r
+#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */\r
+#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */\r
+\r
+#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */\r
+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)\r
+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */\r
+#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */\r
+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)\r
+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */\r
+#define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */\r
+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)\r
+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */\r
+#define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */\r
+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)\r
+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */\r
+#define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */\r
+\r
+/******************** Bit definition for RCC_D3CFGR register ******************/\r
+/*!< D3PPRE configuration */\r
+#define RCC_D3CFGR_D3PPRE_Pos (4U)\r
+#define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */\r
+#define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk /*!< D3PPRE1[2:0] bits (APB4 prescaler) */\r
+#define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */\r
+#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */\r
+#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */\r
+\r
+#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */\r
+#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)\r
+#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */\r
+#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */\r
+#define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)\r
+#define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */\r
+#define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk /*!< APB4 clock divided by 4 */\r
+#define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)\r
+#define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */\r
+#define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk /*!< APB4 clock divided by 8 */\r
+#define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)\r
+#define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */\r
+#define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk /*!< APB4 clock divided by 16 */\r
+\r
+/******************** Bit definition for RCC_PLLCKSELR register *************/\r
+\r
+#define RCC_PLLCKSELR_PLLSRC_Pos (0U)\r
+#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */\r
+#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk\r
+\r
+#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */\r
+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)\r
+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */\r
+#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */\r
+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)\r
+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */\r
+#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */\r
+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)\r
+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */\r
+#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */\r
+\r
+#define RCC_PLLCKSELR_DIVM1_Pos (4U)\r
+#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */\r
+#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk\r
+#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */\r
+#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */\r
+#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */\r
+\r
+#define RCC_PLLCKSELR_DIVM2_Pos (12U)\r
+#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */\r
+#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk\r
+#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */\r
+#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */\r
+\r
+#define RCC_PLLCKSELR_DIVM3_Pos (20U)\r
+#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */\r
+#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk\r
+#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */\r
+#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */\r
+#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */\r
+#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */\r
+#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */\r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+\r
+#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)\r
+#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */\r
+#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk\r
+#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)\r
+#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */\r
+#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk\r
+#define RCC_PLLCFGR_PLL1RGE_Pos (2U)\r
+#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\r
+#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk\r
+#define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */\r
+#define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */\r
+#define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */\r
+#define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\r
+\r
+#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)\r
+#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */\r
+#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk\r
+#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)\r
+#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */\r
+#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk\r
+#define RCC_PLLCFGR_PLL2RGE_Pos (6U)\r
+#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\r
+#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk\r
+#define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */\r
+#define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\r
+\r
+#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)\r
+#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk\r
+#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)\r
+#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk\r
+#define RCC_PLLCFGR_PLL3RGE_Pos (10U)\r
+#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\r
+#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk\r
+#define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */\r
+#define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\r
+\r
+#define RCC_PLLCFGR_DIVP1EN_Pos (16U)\r
+#define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk\r
+#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)\r
+#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk\r
+#define RCC_PLLCFGR_DIVR1EN_Pos (18U)\r
+#define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */\r
+#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk\r
+\r
+#define RCC_PLLCFGR_DIVP2EN_Pos (19U)\r
+#define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */\r
+#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk\r
+#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)\r
+#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */\r
+#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk\r
+#define RCC_PLLCFGR_DIVR2EN_Pos (21U)\r
+#define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */\r
+#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk\r
+\r
+#define RCC_PLLCFGR_DIVP3EN_Pos (22U)\r
+#define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */\r
+#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk\r
+#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)\r
+#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */\r
+#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk\r
+#define RCC_PLLCFGR_DIVR3EN_Pos (24U)\r
+#define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_PLL1DIVR register ***************/\r
+#define RCC_PLL1DIVR_N1_Pos (0U)\r
+#define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */\r
+#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk\r
+#define RCC_PLL1DIVR_P1_Pos (9U)\r
+#define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */\r
+#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk\r
+#define RCC_PLL1DIVR_Q1_Pos (16U)\r
+#define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */\r
+#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk\r
+#define RCC_PLL1DIVR_R1_Pos (24U)\r
+#define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */\r
+#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk\r
+\r
+/******************** Bit definition for RCC_PLL1FRACR register ***************/\r
+#define RCC_PLL1FRACR_FRACN1_Pos (3U)\r
+#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */\r
+#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk\r
+\r
+/******************** Bit definition for RCC_PLL2DIVR register ***************/\r
+#define RCC_PLL2DIVR_N2_Pos (0U)\r
+#define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */\r
+#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk\r
+#define RCC_PLL2DIVR_P2_Pos (9U)\r
+#define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */\r
+#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk\r
+#define RCC_PLL2DIVR_Q2_Pos (16U)\r
+#define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */\r
+#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk\r
+#define RCC_PLL2DIVR_R2_Pos (24U)\r
+#define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */\r
+#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk\r
+\r
+/******************** Bit definition for RCC_PLL2FRACR register ***************/\r
+#define RCC_PLL2FRACR_FRACN2_Pos (3U)\r
+#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */\r
+#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk\r
+\r
+/******************** Bit definition for RCC_PLL3DIVR register ***************/\r
+#define RCC_PLL3DIVR_N3_Pos (0U)\r
+#define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */\r
+#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk\r
+#define RCC_PLL3DIVR_P3_Pos (9U)\r
+#define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */\r
+#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk\r
+#define RCC_PLL3DIVR_Q3_Pos (16U)\r
+#define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */\r
+#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk\r
+#define RCC_PLL3DIVR_R3_Pos (24U)\r
+#define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */\r
+#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk\r
+\r
+/******************** Bit definition for RCC_PLL3FRACR register ***************/\r
+#define RCC_PLL3FRACR_FRACN3_Pos (3U)\r
+#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */\r
+#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk\r
+\r
+/******************** Bit definition for RCC_D1CCIPR register ***************/\r
+#define RCC_D1CCIPR_FMCSEL_Pos (0U)\r
+#define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */\r
+#define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk\r
+#define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */\r
+#define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */\r
+#define RCC_D1CCIPR_QSPISEL_Pos (4U)\r
+#define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */\r
+#define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk\r
+#define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */\r
+#define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */\r
+#define RCC_D1CCIPR_SDMMCSEL_Pos (16U)\r
+#define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */\r
+#define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk\r
+#define RCC_D1CCIPR_CKPERSEL_Pos (28U)\r
+#define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */\r
+#define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk\r
+#define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */\r
+#define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */\r
+\r
+/******************** Bit definition for RCC_D2CCIP1R register ***************/\r
+#define RCC_D2CCIP1R_SAI1SEL_Pos (0U)\r
+#define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */\r
+#define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk\r
+#define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */\r
+#define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */\r
+#define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */\r
+\r
+#define RCC_D2CCIP1R_SAI23SEL_Pos (6U)\r
+#define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */\r
+#define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk\r
+#define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */\r
+#define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */\r
+#define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */\r
+\r
+#define RCC_D2CCIP1R_SPI123SEL_Pos (12U)\r
+#define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */\r
+#define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk\r
+#define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */\r
+#define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */\r
+#define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */\r
+\r
+#define RCC_D2CCIP1R_SPI45SEL_Pos (16U)\r
+#define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */\r
+#define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk\r
+#define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */\r
+#define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */\r
+#define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */\r
+\r
+#define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)\r
+#define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */\r
+#define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk\r
+#define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */\r
+#define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */\r
+\r
+#define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)\r
+#define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */\r
+#define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk\r
+\r
+#define RCC_D2CCIP1R_FDCANSEL_Pos (28U)\r
+#define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */\r
+#define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk\r
+#define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */\r
+#define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */\r
+\r
+#define RCC_D2CCIP1R_SWPSEL_Pos (31U)\r
+#define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */\r
+#define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk\r
+\r
+/******************** Bit definition for RCC_D2CCIP2R register ***************/\r
+#define RCC_D2CCIP2R_USART16SEL_Pos (3U)\r
+#define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */\r
+#define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk\r
+#define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */\r
+#define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */\r
+#define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */\r
+\r
+#define RCC_D2CCIP2R_USART28SEL_Pos (0U)\r
+#define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */\r
+#define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk\r
+#define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */\r
+#define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */\r
+#define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */\r
+\r
+#define RCC_D2CCIP2R_RNGSEL_Pos (8U)\r
+#define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */\r
+#define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk\r
+#define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */\r
+#define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */\r
+\r
+#define RCC_D2CCIP2R_I2C123SEL_Pos (12U)\r
+#define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */\r
+#define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk\r
+#define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */\r
+#define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */\r
+\r
+#define RCC_D2CCIP2R_USBSEL_Pos (20U)\r
+#define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */\r
+#define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk\r
+#define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */\r
+#define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */\r
+\r
+#define RCC_D2CCIP2R_CECSEL_Pos (22U)\r
+#define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */\r
+#define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk\r
+#define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */\r
+#define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */\r
+\r
+#define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)\r
+#define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */\r
+#define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk\r
+#define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */\r
+#define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */\r
+#define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for RCC_D3CCIPR register ***************/\r
+#define RCC_D3CCIPR_LPUART1SEL_Pos (0U)\r
+#define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */\r
+#define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk\r
+#define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */\r
+#define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */\r
+#define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */\r
+\r
+#define RCC_D3CCIPR_I2C4SEL_Pos (8U)\r
+#define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */\r
+#define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk\r
+#define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */\r
+#define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */\r
+\r
+#define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)\r
+#define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */\r
+#define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk\r
+#define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */\r
+#define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */\r
+#define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */\r
+\r
+#define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)\r
+#define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */\r
+#define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk\r
+#define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */\r
+#define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */\r
+#define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */\r
+\r
+#define RCC_D3CCIPR_SAI4ASEL_Pos (21U)\r
+#define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */\r
+#define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk\r
+#define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */\r
+#define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */\r
+#define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */\r
+\r
+#define RCC_D3CCIPR_SAI4BSEL_Pos (24U)\r
+#define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */\r
+#define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk\r
+#define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */\r
+#define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */\r
+#define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */\r
+\r
+#define RCC_D3CCIPR_ADCSEL_Pos (16U)\r
+#define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */\r
+#define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk\r
+#define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */\r
+#define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */\r
+\r
+#define RCC_D3CCIPR_SPI6SEL_Pos (28U)\r
+#define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */\r
+#define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk\r
+#define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */\r
+#define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */\r
+#define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */\r
+/******************** Bit definition for RCC_CIER register ******************/\r
+#define RCC_CIER_LSIRDYIE_Pos (0U)\r
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */\r
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk\r
+#define RCC_CIER_LSERDYIE_Pos (1U)\r
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */\r
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk\r
+#define RCC_CIER_HSIRDYIE_Pos (2U)\r
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */\r
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk\r
+#define RCC_CIER_HSERDYIE_Pos (3U)\r
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */\r
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk\r
+#define RCC_CIER_CSIRDYIE_Pos (4U)\r
+#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */\r
+#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk\r
+#define RCC_CIER_HSI48RDYIE_Pos (5U)\r
+#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */\r
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk\r
+#define RCC_CIER_PLL1RDYIE_Pos (6U)\r
+#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */\r
+#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk\r
+#define RCC_CIER_PLL2RDYIE_Pos (7U)\r
+#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */\r
+#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk\r
+#define RCC_CIER_PLL3RDYIE_Pos (8U)\r
+#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */\r
+#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk\r
+#define RCC_CIER_LSECSSIE_Pos (9U)\r
+#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */\r
+#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk\r
+\r
+/******************** Bit definition for RCC_CIFR register ******************/\r
+#define RCC_CIFR_LSIRDYF_Pos (0U)\r
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */\r
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk\r
+#define RCC_CIFR_LSERDYF_Pos (1U)\r
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */\r
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk\r
+#define RCC_CIFR_HSIRDYF_Pos (2U)\r
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */\r
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk\r
+#define RCC_CIFR_HSERDYF_Pos (3U)\r
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */\r
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk\r
+#define RCC_CIFR_CSIRDYF_Pos (4U)\r
+#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */\r
+#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk\r
+#define RCC_CIFR_HSI48RDYF_Pos (5U)\r
+#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */\r
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk\r
+#define RCC_CIFR_PLLRDYF_Pos (6U)\r
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */\r
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk\r
+#define RCC_CIFR_PLL2RDYF_Pos (7U)\r
+#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */\r
+#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk\r
+#define RCC_CIFR_PLL3RDYF_Pos (8U)\r
+#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */\r
+#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk\r
+#define RCC_CIFR_LSECSSF_Pos (9U)\r
+#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */\r
+#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk\r
+#define RCC_CIFR_HSECSSF_Pos (10U)\r
+#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */\r
+#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk\r
+\r
+/******************** Bit definition for RCC_CICR register ******************/\r
+#define RCC_CICR_LSIRDYC_Pos (0U)\r
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */\r
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk\r
+#define RCC_CICR_LSERDYC_Pos (1U)\r
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */\r
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk\r
+#define RCC_CICR_HSIRDYC_Pos (2U)\r
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */\r
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk\r
+#define RCC_CICR_HSERDYC_Pos (3U)\r
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */\r
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk\r
+#define RCC_CICR_CSIRDYC_Pos (4U)\r
+#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */\r
+#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk\r
+#define RCC_CICR_HSI48RDYC_Pos (5U)\r
+#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */\r
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk\r
+#define RCC_CICR_PLLRDYC_Pos (6U)\r
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */\r
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk\r
+#define RCC_CICR_PLL2RDYC_Pos (7U)\r
+#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */\r
+#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk\r
+#define RCC_CICR_PLL3RDYC_Pos (8U)\r
+#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */\r
+#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk\r
+#define RCC_CICR_LSECSSC_Pos (9U)\r
+#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */\r
+#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk\r
+#define RCC_CICR_HSECSSC_Pos (10U)\r
+#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */\r
+#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk\r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON_Pos (0U)\r
+#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */\r
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk\r
+#define RCC_BDCR_LSERDY_Pos (1U)\r
+#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */\r
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk\r
+#define RCC_BDCR_LSEBYP_Pos (2U)\r
+#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */\r
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk\r
+\r
+#define RCC_BDCR_LSEDRV_Pos (3U)\r
+#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */\r
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk\r
+#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */\r
+#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */\r
+\r
+#define RCC_BDCR_LSECSSON_Pos (5U)\r
+#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */\r
+#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk\r
+#define RCC_BDCR_LSECSSD_Pos (6U)\r
+#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */\r
+#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk\r
+\r
+#define RCC_BDCR_RTCSEL_Pos (8U)\r
+#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */\r
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk\r
+#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */\r
+#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */\r
+\r
+#define RCC_BDCR_RTCEN_Pos (15U)\r
+#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */\r
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk\r
+#define RCC_BDCR_BDRST_Pos (16U)\r
+#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */\r
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION_Pos (0U)\r
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk\r
+#define RCC_CSR_LSIRDY_Pos (1U)\r
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */\r
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_AHB3ENR register **************/\r
+#define RCC_AHB3ENR_MDMAEN_Pos (0U)\r
+#define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk\r
+#define RCC_AHB3ENR_DMA2DEN_Pos (4U)\r
+#define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk\r
+#define RCC_AHB3ENR_JPGDECEN_Pos (5U)\r
+#define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk\r
+#define RCC_AHB3ENR_FMCEN_Pos (12U)\r
+#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk\r
+#define RCC_AHB3ENR_QSPIEN_Pos (14U)\r
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00004000 */\r
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk\r
+#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)\r
+#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk\r
+#define RCC_AHB3ENR_FLASHEN_Pos (8U)\r
+#define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk\r
+#define RCC_AHB3ENR_DTCM1EN_Pos (28U)\r
+#define RCC_AHB3ENR_DTCM1EN_Msk (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB3ENR_DTCM1EN RCC_AHB3ENR_DTCM1EN_Msk\r
+#define RCC_AHB3ENR_DTCM2EN_Pos (29U)\r
+#define RCC_AHB3ENR_DTCM2EN_Msk (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB3ENR_DTCM2EN RCC_AHB3ENR_DTCM2EN_Msk\r
+#define RCC_AHB3ENR_ITCMEN_Pos (30U)\r
+#define RCC_AHB3ENR_ITCMEN_Msk (0x1UL << RCC_AHB3ENR_ITCMEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB3ENR_ITCMEN RCC_AHB3ENR_ITCMEN_Msk\r
+#define RCC_AHB3ENR_AXISRAMEN_Pos (31U)\r
+#define RCC_AHB3ENR_AXISRAMEN_Msk (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos) /*!< 0x80000000 */\r
+#define RCC_AHB3ENR_AXISRAMEN RCC_AHB3ENR_AXISRAMEN_Msk\r
+\r
+/* Legacy define */\r
+#define RCC_AHB3ENR_D1SRAM1EN_Pos RCC_AHB3ENR_AXISRAMEN_Pos\r
+#define RCC_AHB3ENR_D1SRAM1EN_Msk RCC_AHB3ENR_AXISRAMEN_Msk\r
+#define RCC_AHB3ENR_D1SRAM1EN RCC_AHB3ENR_AXISRAMEN\r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_DMA1EN_Pos (0U)\r
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk\r
+#define RCC_AHB1ENR_DMA2EN_Pos (1U)\r
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk\r
+#define RCC_AHB1ENR_ADC12EN_Pos (5U)\r
+#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk\r
+#define RCC_AHB1ENR_ARTEN_Pos (14U)\r
+#define RCC_AHB1ENR_ARTEN_Msk (0x1UL << RCC_AHB1ENR_ARTEN_Pos) /*!< 0x00004000 */\r
+#define RCC_AHB1ENR_ARTEN RCC_AHB1ENR_ARTEN_Msk\r
+#define RCC_AHB1ENR_ETH1MACEN_Pos (15U)\r
+#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */\r
+#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk\r
+#define RCC_AHB1ENR_ETH1TXEN_Pos (16U)\r
+#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk\r
+#define RCC_AHB1ENR_ETH1RXEN_Pos (17U)\r
+#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */\r
+#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk\r
+#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)\r
+#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk\r
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)\r
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */\r
+#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk\r
+#define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)\r
+#define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) /*!< 0x08000000 */\r
+#define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk\r
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)\r
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk\r
+\r
+/* Legacy define */\r
+#define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos\r
+#define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk\r
+#define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN\r
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos\r
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk\r
+#define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN\r
+\r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_DCMIEN_Pos (0U)\r
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk\r
+#define RCC_AHB2ENR_CRYPEN_Pos (4U)\r
+#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk\r
+#define RCC_AHB2ENR_HASHEN_Pos (5U)\r
+#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk\r
+#define RCC_AHB2ENR_RNGEN_Pos (6U)\r
+#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk\r
+#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)\r
+#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk\r
+#define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)\r
+#define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk\r
+#define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)\r
+#define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_D2SRAM2EN_Msk\r
+#define RCC_AHB2ENR_D2SRAM3EN_Pos (31U)\r
+#define RCC_AHB2ENR_D2SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM3EN_Pos) /*!< 0x80000000 */\r
+#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_D2SRAM3EN_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_AHB4ENR register ******************/\r
+#define RCC_AHB4ENR_GPIOAEN_Pos (0U)\r
+#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk\r
+#define RCC_AHB4ENR_GPIOBEN_Pos (1U)\r
+#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk\r
+#define RCC_AHB4ENR_GPIOCEN_Pos (2U)\r
+#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk\r
+#define RCC_AHB4ENR_GPIODEN_Pos (3U)\r
+#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk\r
+#define RCC_AHB4ENR_GPIOEEN_Pos (4U)\r
+#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk\r
+#define RCC_AHB4ENR_GPIOFEN_Pos (5U)\r
+#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk\r
+#define RCC_AHB4ENR_GPIOGEN_Pos (6U)\r
+#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk\r
+#define RCC_AHB4ENR_GPIOHEN_Pos (7U)\r
+#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk\r
+#define RCC_AHB4ENR_GPIOIEN_Pos (8U)\r
+#define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk\r
+#define RCC_AHB4ENR_GPIOJEN_Pos (9U)\r
+#define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk\r
+#define RCC_AHB4ENR_GPIOKEN_Pos (10U)\r
+#define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */\r
+#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk\r
+#define RCC_AHB4ENR_CRCEN_Pos (19U)\r
+#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */\r
+#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk\r
+#define RCC_AHB4ENR_BDMAEN_Pos (21U)\r
+#define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk\r
+#define RCC_AHB4ENR_ADC3EN_Pos (24U)\r
+#define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) /*!< 0x01000000 */\r
+#define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk\r
+#define RCC_AHB4ENR_HSEMEN_Pos (25U)\r
+#define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk\r
+#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)\r
+#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk\r
+#define RCC_AHB4ENR_D3SRAM1EN_Pos (29U)\r
+#define RCC_AHB4ENR_D3SRAM1EN_Msk (0x1UL << RCC_AHB4ENR_D3SRAM1EN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB4ENR_D3SRAM1EN RCC_AHB4ENR_D3SRAM1EN_Msk\r
+\r
+/******************** Bit definition for RCC_APB3ENR register ******************/\r
+#define RCC_APB3ENR_LTDCEN_Pos (3U)\r
+#define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk\r
+#define RCC_APB3ENR_WWDG1EN_Pos (6U)\r
+#define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk\r
+\r
+/******************** Bit definition for RCC_APB1LENR register ******************/\r
+\r
+#define RCC_APB1LENR_TIM2EN_Pos (0U)\r
+#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk\r
+#define RCC_APB1LENR_TIM3EN_Pos (1U)\r
+#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk\r
+#define RCC_APB1LENR_TIM4EN_Pos (2U)\r
+#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk\r
+#define RCC_APB1LENR_TIM5EN_Pos (3U)\r
+#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk\r
+#define RCC_APB1LENR_TIM6EN_Pos (4U)\r
+#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk\r
+#define RCC_APB1LENR_TIM7EN_Pos (5U)\r
+#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk\r
+#define RCC_APB1LENR_TIM12EN_Pos (6U)\r
+#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk\r
+#define RCC_APB1LENR_TIM13EN_Pos (7U)\r
+#define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk\r
+#define RCC_APB1LENR_TIM14EN_Pos (8U)\r
+#define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk\r
+#define RCC_APB1LENR_LPTIM1EN_Pos (9U)\r
+#define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk\r
+\r
+#define RCC_APB1LENR_WWDG2EN_Pos (11U)\r
+#define RCC_APB1LENR_WWDG2EN_Msk (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1LENR_WWDG2EN RCC_APB1LENR_WWDG2EN_Msk\r
+\r
+#define RCC_APB1LENR_SPI2EN_Pos (14U)\r
+#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk\r
+#define RCC_APB1LENR_SPI3EN_Pos (15U)\r
+#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk\r
+#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)\r
+#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk\r
+#define RCC_APB1LENR_USART2EN_Pos (17U)\r
+#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk\r
+#define RCC_APB1LENR_USART3EN_Pos (18U)\r
+#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk\r
+#define RCC_APB1LENR_UART4EN_Pos (19U)\r
+#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk\r
+#define RCC_APB1LENR_UART5EN_Pos (20U)\r
+#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk\r
+#define RCC_APB1LENR_I2C1EN_Pos (21U)\r
+#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk\r
+#define RCC_APB1LENR_I2C2EN_Pos (22U)\r
+#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk\r
+#define RCC_APB1LENR_I2C3EN_Pos (23U)\r
+#define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk\r
+#define RCC_APB1LENR_CECEN_Pos (27U)\r
+#define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */\r
+#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk\r
+#define RCC_APB1LENR_DAC12EN_Pos (29U)\r
+#define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk\r
+#define RCC_APB1LENR_UART7EN_Pos (30U)\r
+#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk\r
+#define RCC_APB1LENR_UART8EN_Pos (31U)\r
+#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk\r
+\r
+/******************** Bit definition for RCC_APB1HENR register ******************/\r
+#define RCC_APB1HENR_CRSEN_Pos (1U)\r
+#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk\r
+#define RCC_APB1HENR_SWPMIEN_Pos (2U)\r
+#define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk\r
+#define RCC_APB1HENR_OPAMPEN_Pos (4U)\r
+#define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk\r
+#define RCC_APB1HENR_MDIOSEN_Pos (5U)\r
+#define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk\r
+#define RCC_APB1HENR_FDCANEN_Pos (8U)\r
+#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB2ENR register ******************/\r
+#define RCC_APB2ENR_TIM1EN_Pos (0U)\r
+#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk\r
+#define RCC_APB2ENR_TIM8EN_Pos (1U)\r
+#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk\r
+#define RCC_APB2ENR_USART1EN_Pos (4U)\r
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk\r
+#define RCC_APB2ENR_USART6EN_Pos (5U)\r
+#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk\r
+#define RCC_APB2ENR_SPI1EN_Pos (12U)\r
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk\r
+#define RCC_APB2ENR_SPI4EN_Pos (13U)\r
+#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk\r
+#define RCC_APB2ENR_TIM15EN_Pos (16U)\r
+#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk\r
+#define RCC_APB2ENR_TIM16EN_Pos (17U)\r
+#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk\r
+#define RCC_APB2ENR_TIM17EN_Pos (18U)\r
+#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk\r
+#define RCC_APB2ENR_SPI5EN_Pos (20U)\r
+#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk\r
+#define RCC_APB2ENR_SAI1EN_Pos (22U)\r
+#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk\r
+#define RCC_APB2ENR_SAI2EN_Pos (23U)\r
+#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk\r
+#define RCC_APB2ENR_SAI3EN_Pos (24U)\r
+#define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */\r
+#define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk\r
+#define RCC_APB2ENR_DFSDM1EN_Pos (28U)\r
+#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk\r
+#define RCC_APB2ENR_HRTIMEN_Pos (29U)\r
+#define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB4ENR register ******************/\r
+#define RCC_APB4ENR_SYSCFGEN_Pos (1U)\r
+#define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk\r
+#define RCC_APB4ENR_LPUART1EN_Pos (3U)\r
+#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk\r
+#define RCC_APB4ENR_SPI6EN_Pos (5U)\r
+#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk\r
+#define RCC_APB4ENR_I2C4EN_Pos (7U)\r
+#define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk\r
+#define RCC_APB4ENR_LPTIM2EN_Pos (9U)\r
+#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk\r
+#define RCC_APB4ENR_LPTIM3EN_Pos (10U)\r
+#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk\r
+#define RCC_APB4ENR_LPTIM4EN_Pos (11U)\r
+#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk\r
+#define RCC_APB4ENR_LPTIM5EN_Pos (12U)\r
+#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk\r
+#define RCC_APB4ENR_COMP12EN_Pos (14U)\r
+#define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk\r
+#define RCC_APB4ENR_VREFEN_Pos (15U)\r
+#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk\r
+#define RCC_APB4ENR_RTCAPBEN_Pos (16U)\r
+#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk\r
+#define RCC_APB4ENR_SAI4EN_Pos (21U)\r
+#define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register ***************/\r
+#define RCC_AHB3RSTR_MDMARST_Pos (0U)\r
+#define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk\r
+#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)\r
+#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk\r
+#define RCC_AHB3RSTR_JPGDECRST_Pos (5U)\r
+#define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk\r
+#define RCC_AHB3RSTR_FMCRST_Pos (12U)\r
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk\r
+#define RCC_AHB3RSTR_QSPIRST_Pos (14U)\r
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00004000 */\r
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk\r
+#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)\r
+#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register ***************/\r
+#define RCC_AHB1RSTR_DMA1RST_Pos (0U)\r
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk\r
+#define RCC_AHB1RSTR_DMA2RST_Pos (1U)\r
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk\r
+#define RCC_AHB1RSTR_ADC12RST_Pos (5U)\r
+#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk\r
+#define RCC_AHB1RSTR_ARTRST_Pos (14U)\r
+#define RCC_AHB1RSTR_ARTRST_Msk (0x1UL << RCC_AHB1RSTR_ARTRST_Pos) /*!< 0x00004000 */\r
+#define RCC_AHB1RSTR_ARTRST RCC_AHB1RSTR_ARTRST_Msk\r
+#define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)\r
+#define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) /*!< 0x00008000 */\r
+#define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk\r
+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)\r
+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk\r
+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)\r
+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */\r
+#define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk\r
+\r
+/* Legacy define */\r
+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos\r
+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk\r
+#define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST\r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register ***************/\r
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)\r
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk\r
+#define RCC_AHB2RSTR_CRYPRST_Pos (4U)\r
+#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk\r
+#define RCC_AHB2RSTR_HASHRST_Pos (5U)\r
+#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk\r
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)\r
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk\r
+#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)\r
+#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk\r
+\r
+/******************** Bit definition for RCC_AHB4RSTR register ******************/\r
+#define RCC_AHB4RSTR_GPIOARST_Pos (0U)\r
+#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk\r
+#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)\r
+#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk\r
+#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)\r
+#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk\r
+#define RCC_AHB4RSTR_GPIODRST_Pos (3U)\r
+#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk\r
+#define RCC_AHB4RSTR_GPIOERST_Pos (4U)\r
+#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk\r
+#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)\r
+#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk\r
+#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)\r
+#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk\r
+#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)\r
+#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk\r
+#define RCC_AHB4RSTR_GPIOIRST_Pos (8U)\r
+#define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk\r
+#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)\r
+#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk\r
+#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)\r
+#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */\r
+#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk\r
+#define RCC_AHB4RSTR_CRCRST_Pos (19U)\r
+#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */\r
+#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk\r
+#define RCC_AHB4RSTR_BDMARST_Pos (21U)\r
+#define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk\r
+#define RCC_AHB4RSTR_ADC3RST_Pos (24U)\r
+#define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) /*!< 0x01000000 */\r
+#define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk\r
+#define RCC_AHB4RSTR_HSEMRST_Pos (25U)\r
+#define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_APB3RSTR register ******************/\r
+#define RCC_APB3RSTR_LTDCRST_Pos (3U)\r
+#define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk\r
+\r
+/******************** Bit definition for RCC_APB1LRSTR register ******************/\r
+\r
+#define RCC_APB1LRSTR_TIM2RST_Pos (0U)\r
+#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk\r
+#define RCC_APB1LRSTR_TIM3RST_Pos (1U)\r
+#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk\r
+#define RCC_APB1LRSTR_TIM4RST_Pos (2U)\r
+#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk\r
+#define RCC_APB1LRSTR_TIM5RST_Pos (3U)\r
+#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk\r
+#define RCC_APB1LRSTR_TIM6RST_Pos (4U)\r
+#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk\r
+#define RCC_APB1LRSTR_TIM7RST_Pos (5U)\r
+#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk\r
+#define RCC_APB1LRSTR_TIM12RST_Pos (6U)\r
+#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk\r
+#define RCC_APB1LRSTR_TIM13RST_Pos (7U)\r
+#define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk\r
+#define RCC_APB1LRSTR_TIM14RST_Pos (8U)\r
+#define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk\r
+#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)\r
+#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk\r
+#define RCC_APB1LRSTR_SPI2RST_Pos (14U)\r
+#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk\r
+#define RCC_APB1LRSTR_SPI3RST_Pos (15U)\r
+#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk\r
+#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)\r
+#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */\r
+#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk\r
+#define RCC_APB1LRSTR_USART2RST_Pos (17U)\r
+#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk\r
+#define RCC_APB1LRSTR_USART3RST_Pos (18U)\r
+#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk\r
+#define RCC_APB1LRSTR_UART4RST_Pos (19U)\r
+#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk\r
+#define RCC_APB1LRSTR_UART5RST_Pos (20U)\r
+#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk\r
+#define RCC_APB1LRSTR_I2C1RST_Pos (21U)\r
+#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk\r
+#define RCC_APB1LRSTR_I2C2RST_Pos (22U)\r
+#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk\r
+#define RCC_APB1LRSTR_I2C3RST_Pos (23U)\r
+#define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk\r
+#define RCC_APB1LRSTR_CECRST_Pos (27U)\r
+#define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */\r
+#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk\r
+#define RCC_APB1LRSTR_DAC12RST_Pos (29U)\r
+#define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk\r
+#define RCC_APB1LRSTR_UART7RST_Pos (30U)\r
+#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk\r
+#define RCC_APB1LRSTR_UART8RST_Pos (31U)\r
+#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk\r
+\r
+/******************** Bit definition for RCC_APB1HRSTR register ******************/\r
+#define RCC_APB1HRSTR_CRSRST_Pos (1U)\r
+#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk\r
+#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)\r
+#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk\r
+#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)\r
+#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk\r
+#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)\r
+#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk\r
+#define RCC_APB1HRSTR_FDCANRST_Pos (8U)\r
+#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk\r
+\r
+/******************** Bit definition for RCC_APB2RSTR register ******************/\r
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)\r
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk\r
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)\r
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk\r
+#define RCC_APB2RSTR_USART1RST_Pos (4U)\r
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk\r
+#define RCC_APB2RSTR_USART6RST_Pos (5U)\r
+#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk\r
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)\r
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk\r
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)\r
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk\r
+#define RCC_APB2RSTR_TIM15RST_Pos (16U)\r
+#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk\r
+#define RCC_APB2RSTR_TIM16RST_Pos (17U)\r
+#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk\r
+#define RCC_APB2RSTR_TIM17RST_Pos (18U)\r
+#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk\r
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)\r
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk\r
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)\r
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk\r
+#define RCC_APB2RSTR_SAI2RST_Pos (23U)\r
+#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk\r
+#define RCC_APB2RSTR_SAI3RST_Pos (24U)\r
+#define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */\r
+#define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk\r
+#define RCC_APB2RSTR_DFSDM1RST_Pos (28U)\r
+#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */\r
+#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk\r
+#define RCC_APB2RSTR_HRTIMRST_Pos (29U)\r
+#define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */\r
+#define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk\r
+\r
+/******************** Bit definition for RCC_APB4RSTR register ******************/\r
+#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)\r
+#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk\r
+#define RCC_APB4RSTR_LPUART1RST_Pos (3U)\r
+#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk\r
+#define RCC_APB4RSTR_SPI6RST_Pos (5U)\r
+#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk\r
+#define RCC_APB4RSTR_I2C4RST_Pos (7U)\r
+#define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */\r
+#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk\r
+#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)\r
+#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */\r
+#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk\r
+#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)\r
+#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */\r
+#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk\r
+#define RCC_APB4RSTR_LPTIM4RST_Pos (11U)\r
+#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */\r
+#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk\r
+#define RCC_APB4RSTR_LPTIM5RST_Pos (12U)\r
+#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */\r
+#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk\r
+#define RCC_APB4RSTR_COMP12RST_Pos (14U)\r
+#define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk\r
+#define RCC_APB4RSTR_VREFRST_Pos (15U)\r
+#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */\r
+#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk\r
+#define RCC_APB4RSTR_SAI4RST_Pos (21U)\r
+#define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_GCR register ********************/\r
+#define RCC_GCR_WW1RSC_Pos (0U)\r
+#define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) /*!< 0x00000001 */\r
+#define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk\r
+#define RCC_GCR_WW2RSC_Pos (1U)\r
+#define RCC_GCR_WW2RSC_Msk (0x1UL << RCC_GCR_WW2RSC_Pos) /*!< 0x00000002 */\r
+#define RCC_GCR_WW2RSC RCC_GCR_WW2RSC_Msk\r
+#define RCC_GCR_BOOT_C1_Pos (2U)\r
+#define RCC_GCR_BOOT_C1_Msk (0x1UL << RCC_GCR_BOOT_C1_Pos) /*!< 0x00000004 */\r
+#define RCC_GCR_BOOT_C1 RCC_GCR_BOOT_C1_Msk\r
+#define RCC_GCR_BOOT_C2_Pos (3U)\r
+#define RCC_GCR_BOOT_C2_Msk (0x1UL << RCC_GCR_BOOT_C2_Pos) /*!< 0x00000008 */\r
+#define RCC_GCR_BOOT_C2 RCC_GCR_BOOT_C2_Msk\r
+\r
+/******************** Bit definition for RCC_D3AMR register ********************/\r
+#define RCC_D3AMR_BDMAAMEN_Pos (0U)\r
+#define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */\r
+#define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk\r
+#define RCC_D3AMR_LPUART1AMEN_Pos (3U)\r
+#define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */\r
+#define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk\r
+#define RCC_D3AMR_SPI6AMEN_Pos (5U)\r
+#define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */\r
+#define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk\r
+#define RCC_D3AMR_I2C4AMEN_Pos (7U)\r
+#define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */\r
+#define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk\r
+#define RCC_D3AMR_LPTIM2AMEN_Pos (9U)\r
+#define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */\r
+#define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk\r
+#define RCC_D3AMR_LPTIM3AMEN_Pos (10U)\r
+#define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */\r
+#define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk\r
+#define RCC_D3AMR_LPTIM4AMEN_Pos (11U)\r
+#define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */\r
+#define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk\r
+#define RCC_D3AMR_LPTIM5AMEN_Pos (12U)\r
+#define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */\r
+#define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk\r
+#define RCC_D3AMR_COMP12AMEN_Pos (14U)\r
+#define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */\r
+#define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk\r
+#define RCC_D3AMR_VREFAMEN_Pos (15U)\r
+#define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */\r
+#define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk\r
+#define RCC_D3AMR_RTCAMEN_Pos (16U)\r
+#define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */\r
+#define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk\r
+#define RCC_D3AMR_CRCAMEN_Pos (19U)\r
+#define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */\r
+#define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk\r
+#define RCC_D3AMR_SAI4AMEN_Pos (21U)\r
+#define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */\r
+#define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk\r
+#define RCC_D3AMR_ADC3AMEN_Pos (24U)\r
+#define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */\r
+#define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk\r
+\r
+\r
+#define RCC_D3AMR_BKPRAMAMEN_Pos (28U)\r
+#define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */\r
+#define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk\r
+#define RCC_D3AMR_SRAM4AMEN_Pos (29U)\r
+#define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */\r
+#define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk\r
+/******************** Bit definition for RCC_AHB3LPENR register **************/\r
+#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)\r
+#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk\r
+#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)\r
+#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk\r
+#define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)\r
+#define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk\r
+#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)\r
+#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk\r
+#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)\r
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk\r
+#define RCC_AHB3LPENR_QSPILPEN_Pos (14U)\r
+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk\r
+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)\r
+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk\r
+#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)\r
+#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk\r
+#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)\r
+#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk\r
+#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)\r
+#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk\r
+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)\r
+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */\r
+#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register ***************/\r
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)\r
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk\r
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)\r
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk\r
+#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)\r
+#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk\r
+#define RCC_AHB1LPENR_ARTLPEN_Pos (14U)\r
+#define RCC_AHB1LPENR_ARTLPEN_Msk (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_AHB1LPENR_ARTLPEN RCC_AHB1LPENR_ARTLPEN_Msk\r
+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)\r
+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk\r
+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)\r
+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk\r
+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)\r
+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk\r
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)\r
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk\r
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)\r
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */\r
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk\r
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)\r
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */\r
+#define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk\r
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)\r
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk\r
+\r
+/* Legacy define */\r
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos\r
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk\r
+#define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN\r
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos\r
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk\r
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN\r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register ***************/\r
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)\r
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk\r
+#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)\r
+#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk\r
+#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)\r
+#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk\r
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)\r
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk\r
+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)\r
+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk\r
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos (30U)\r
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM1LPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_D2SRAM1LPEN_Msk\r
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos (30U)\r
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM2LPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_D2SRAM2LPEN_Msk\r
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos (31U)\r
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM3LPEN_Pos) /*!< 0x80000000 */\r
+#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_D2SRAM3LPEN_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_AHB4LPENR register ******************/\r
+#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)\r
+#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)\r
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)\r
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk\r
+#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)\r
+#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)\r
+#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)\r
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)\r
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)\r
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)\r
+#define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)\r
+#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk\r
+#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)\r
+#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\r
+#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk\r
+#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)\r
+#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */\r
+#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk\r
+#define RCC_AHB4LPENR_BDMALPEN_Pos (21U)\r
+#define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk\r
+#define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)\r
+#define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */\r
+#define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk\r
+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)\r
+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk\r
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos (29U)\r
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk (0x1UL << RCC_AHB4LPENR_D3SRAM1LPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_D3SRAM1LPEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB3LPENR register ******************/\r
+#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)\r
+#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk\r
+#define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)\r
+#define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB1LLPENR register ******************/\r
+\r
+#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)\r
+#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)\r
+#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)\r
+#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)\r
+#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)\r
+#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)\r
+#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)\r
+#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)\r
+#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk\r
+#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)\r
+#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk\r
+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)\r
+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk\r
+\r
+#define RCC_APB1LLPENR_WWDG2LPEN_Pos (11U)\r
+#define RCC_APB1LLPENR_WWDG2LPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1LLPENR_WWDG2LPEN RCC_APB1LLPENR_WWDG2LPEN_Msk\r
+\r
+#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)\r
+#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk\r
+#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)\r
+#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk\r
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)\r
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk\r
+#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)\r
+#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk\r
+#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)\r
+#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk\r
+#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)\r
+#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk\r
+#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)\r
+#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk\r
+#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)\r
+#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk\r
+#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)\r
+#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk\r
+#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)\r
+#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk\r
+#define RCC_APB1LLPENR_CECLPEN_Pos (27U)\r
+#define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */\r
+#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk\r
+#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)\r
+#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk\r
+#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)\r
+#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk\r
+#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)\r
+#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB1HLPENR register ******************/\r
+#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)\r
+#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk\r
+#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)\r
+#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk\r
+#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)\r
+#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk\r
+#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)\r
+#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk\r
+#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)\r
+#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB2LPENR register ******************/\r
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)\r
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk\r
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)\r
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk\r
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)\r
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk\r
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)\r
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk\r
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)\r
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk\r
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)\r
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk\r
+#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)\r
+#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk\r
+#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)\r
+#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk\r
+#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)\r
+#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk\r
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)\r
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk\r
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)\r
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk\r
+#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)\r
+#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk\r
+#define RCC_APB2LPENR_SAI3LPEN_Pos (24U)\r
+#define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */\r
+#define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk\r
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)\r
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk\r
+#define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)\r
+#define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB4LPENR register ******************/\r
+#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)\r
+#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk\r
+#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)\r
+#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk\r
+#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)\r
+#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk\r
+#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)\r
+#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk\r
+#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)\r
+#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk\r
+#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)\r
+#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk\r
+#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)\r
+#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk\r
+#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)\r
+#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk\r
+#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)\r
+#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk\r
+#define RCC_APB4LPENR_VREFLPEN_Pos (15U)\r
+#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk\r
+#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)\r
+#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk\r
+#define RCC_APB4LPENR_SAI4LPEN_Pos (21U)\r
+#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk\r
+\r
+\r
+/******************** Bit definition for RCC_RSR register *******************/\r
+#define RCC_RSR_RMVF_Pos (16U)\r
+#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */\r
+#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk\r
+#define RCC_RSR_C1RSTF_Pos (17U)\r
+#define RCC_RSR_C1RSTF_Msk (0x1UL << RCC_RSR_C1RSTF_Pos) /*!< 0x00020000 */\r
+#define RCC_RSR_C1RSTF RCC_RSR_C1RSTF_Msk\r
+#define RCC_RSR_D1RSTF_Pos (19U)\r
+#define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) /*!< 0x00080000 */\r
+#define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk\r
+#define RCC_RSR_D2RSTF_Pos (20U)\r
+#define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) /*!< 0x00100000 */\r
+#define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk\r
+#define RCC_RSR_BORRSTF_Pos (21U)\r
+#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */\r
+#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk\r
+#define RCC_RSR_PINRSTF_Pos (22U)\r
+#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */\r
+#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk\r
+#define RCC_RSR_PORRSTF_Pos (23U)\r
+#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */\r
+#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk\r
+#define RCC_RSR_SFT1RSTF_Pos (24U)\r
+#define RCC_RSR_SFT1RSTF_Msk (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */\r
+#define RCC_RSR_SFT1RSTF RCC_RSR_SFT1RSTF_Msk\r
+#define RCC_RSR_IWDG1RSTF_Pos (26U)\r
+#define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */\r
+#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk\r
+#define RCC_RSR_WWDG1RSTF_Pos (28U)\r
+#define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */\r
+#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk\r
+\r
+#define RCC_RSR_WWDG2RSTF_Pos (29U)\r
+#define RCC_RSR_WWDG2RSTF_Msk (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */\r
+#define RCC_RSR_WWDG2RSTF RCC_RSR_WWDG2RSTF_Msk\r
+#define RCC_RSR_IWDG2RSTF_Pos (27U)\r
+#define RCC_RSR_IWDG2RSTF_Msk (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */\r
+#define RCC_RSR_IWDG2RSTF RCC_RSR_IWDG2RSTF_Msk\r
+#define RCC_RSR_SFT2RSTF_Pos (25U)\r
+#define RCC_RSR_SFT2RSTF_Msk (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */\r
+#define RCC_RSR_SFT2RSTF RCC_RSR_SFT2RSTF_Msk\r
+#define RCC_RSR_C2RSTF_Pos (18U)\r
+#define RCC_RSR_C2RSTF_Msk (0x1UL << RCC_RSR_C2RSTF_Pos) /*!< 0x00040000 */\r
+#define RCC_RSR_C2RSTF RCC_RSR_C2RSTF_Msk\r
+#define RCC_RSR_LPWR1RSTF_Pos (30U)\r
+#define RCC_RSR_LPWR1RSTF_Msk (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */\r
+#define RCC_RSR_LPWR1RSTF RCC_RSR_LPWR1RSTF_Msk\r
+#define RCC_RSR_LPWR2RSTF_Pos (31U)\r
+#define RCC_RSR_LPWR2RSTF_Msk (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */\r
+#define RCC_RSR_LPWR2RSTF RCC_RSR_LPWR2RSTF_Msk\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN_Pos (2U)\r
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */\r
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk\r
+#define RNG_CR_IE_Pos (3U)\r
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */\r
+#define RNG_CR_IE RNG_CR_IE_Msk\r
+#define RNG_CR_CED_Pos (5U)\r
+#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */\r
+#define RNG_CR_CED RNG_CR_CED_Msk\r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY_Pos (0U)\r
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */\r
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk\r
+#define RNG_SR_CECS_Pos (1U)\r
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */\r
+#define RNG_SR_CECS RNG_SR_CECS_Msk\r
+#define RNG_SR_SECS_Pos (2U)\r
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */\r
+#define RNG_SR_SECS RNG_SR_SECS_Msk\r
+#define RNG_SR_CEIS_Pos (5U)\r
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */\r
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk\r
+#define RNG_SR_SEIS_Pos (6U)\r
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */\r
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM_Pos (22U)\r
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TR_PM RTC_TR_PM_Msk\r
+#define RTC_TR_HT_Pos (20U)\r
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TR_HT RTC_TR_HT_Msk\r
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TR_HU_Pos (16U)\r
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TR_HU RTC_TR_HU_Msk\r
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TR_MNT_Pos (12U)\r
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TR_MNT RTC_TR_MNT_Msk\r
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TR_MNU_Pos (8U)\r
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TR_MNU RTC_TR_MNU_Msk\r
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TR_ST_Pos (4U)\r
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TR_ST RTC_TR_ST_Msk\r
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TR_SU_Pos (0U)\r
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TR_SU RTC_TR_SU_Msk\r
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT_Pos (20U)\r
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */\r
+#define RTC_DR_YT RTC_DR_YT_Msk\r
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */\r
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */\r
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */\r
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */\r
+#define RTC_DR_YU_Pos (16U)\r
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */\r
+#define RTC_DR_YU RTC_DR_YU_Msk\r
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */\r
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */\r
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */\r
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */\r
+#define RTC_DR_WDU_Pos (13U)\r
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_DR_WDU RTC_DR_WDU_Msk\r
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_DR_MT_Pos (12U)\r
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_DR_MT RTC_DR_MT_Msk\r
+#define RTC_DR_MU_Pos (8U)\r
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_DR_MU RTC_DR_MU_Msk\r
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_DR_DT_Pos (4U)\r
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_DR_DT RTC_DR_DT_Msk\r
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_DR_DU_Pos (0U)\r
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_DR_DU RTC_DR_DU_Msk\r
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_ITSE_Pos (24U)\r
+#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */\r
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk\r
+#define RTC_CR_COE_Pos (23U)\r
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */\r
+#define RTC_CR_COE RTC_CR_COE_Msk\r
+#define RTC_CR_OSEL_Pos (21U)\r
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */\r
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk\r
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */\r
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */\r
+#define RTC_CR_POL_Pos (20U)\r
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */\r
+#define RTC_CR_POL RTC_CR_POL_Msk\r
+#define RTC_CR_COSEL_Pos (19U)\r
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */\r
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk\r
+#define RTC_CR_BKP_Pos (18U)\r
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */\r
+#define RTC_CR_BKP RTC_CR_BKP_Msk\r
+#define RTC_CR_SUB1H_Pos (17U)\r
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */\r
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk\r
+#define RTC_CR_ADD1H_Pos (16U)\r
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */\r
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk\r
+#define RTC_CR_TSIE_Pos (15U)\r
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */\r
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk\r
+#define RTC_CR_WUTIE_Pos (14U)\r
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */\r
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk\r
+#define RTC_CR_ALRBIE_Pos (13U)\r
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */\r
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk\r
+#define RTC_CR_ALRAIE_Pos (12U)\r
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */\r
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk\r
+#define RTC_CR_TSE_Pos (11U)\r
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */\r
+#define RTC_CR_TSE RTC_CR_TSE_Msk\r
+#define RTC_CR_WUTE_Pos (10U)\r
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */\r
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk\r
+#define RTC_CR_ALRBE_Pos (9U)\r
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */\r
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk\r
+#define RTC_CR_ALRAE_Pos (8U)\r
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */\r
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk\r
+#define RTC_CR_FMT_Pos (6U)\r
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */\r
+#define RTC_CR_FMT RTC_CR_FMT_Msk\r
+#define RTC_CR_BYPSHAD_Pos (5U)\r
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */\r
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk\r
+#define RTC_CR_REFCKON_Pos (4U)\r
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */\r
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk\r
+#define RTC_CR_TSEDGE_Pos (3U)\r
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */\r
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk\r
+#define RTC_CR_WUCKSEL_Pos (0U)\r
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */\r
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk\r
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */\r
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */\r
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_ITSF_Pos (17U)\r
+#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */\r
+#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk\r
+#define RTC_ISR_RECALPF_Pos (16U)\r
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */\r
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk\r
+#define RTC_ISR_TAMP3F_Pos (15U)\r
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */\r
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk\r
+#define RTC_ISR_TAMP2F_Pos (14U)\r
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */\r
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk\r
+#define RTC_ISR_TAMP1F_Pos (13U)\r
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */\r
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk\r
+#define RTC_ISR_TSOVF_Pos (12U)\r
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */\r
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk\r
+#define RTC_ISR_TSF_Pos (11U)\r
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */\r
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk\r
+#define RTC_ISR_WUTF_Pos (10U)\r
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */\r
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk\r
+#define RTC_ISR_ALRBF_Pos (9U)\r
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */\r
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk\r
+#define RTC_ISR_ALRAF_Pos (8U)\r
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */\r
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk\r
+#define RTC_ISR_INIT_Pos (7U)\r
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */\r
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk\r
+#define RTC_ISR_INITF_Pos (6U)\r
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */\r
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk\r
+#define RTC_ISR_RSF_Pos (5U)\r
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */\r
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk\r
+#define RTC_ISR_INITS_Pos (4U)\r
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */\r
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk\r
+#define RTC_ISR_SHPF_Pos (3U)\r
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */\r
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk\r
+#define RTC_ISR_WUTWF_Pos (2U)\r
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */\r
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk\r
+#define RTC_ISR_ALRBWF_Pos (1U)\r
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */\r
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk\r
+#define RTC_ISR_ALRAWF_Pos (0U)\r
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */\r
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A_Pos (16U)\r
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */\r
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk\r
+#define RTC_PRER_PREDIV_S_Pos (0U)\r
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */\r
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT_Pos (0U)\r
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */\r
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4_Pos (31U)\r
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk\r
+#define RTC_ALRMAR_WDSEL_Pos (30U)\r
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk\r
+#define RTC_ALRMAR_DT_Pos (28U)\r
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk\r
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMAR_DU_Pos (24U)\r
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk\r
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMAR_MSK3_Pos (23U)\r
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk\r
+#define RTC_ALRMAR_PM_Pos (22U)\r
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk\r
+#define RTC_ALRMAR_HT_Pos (20U)\r
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk\r
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMAR_HU_Pos (16U)\r
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk\r
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMAR_MSK2_Pos (15U)\r
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk\r
+#define RTC_ALRMAR_MNT_Pos (12U)\r
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk\r
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMAR_MNU_Pos (8U)\r
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk\r
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMAR_MSK1_Pos (7U)\r
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk\r
+#define RTC_ALRMAR_ST_Pos (4U)\r
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk\r
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMAR_SU_Pos (0U)\r
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk\r
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4_Pos (31U)\r
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk\r
+#define RTC_ALRMBR_WDSEL_Pos (30U)\r
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk\r
+#define RTC_ALRMBR_DT_Pos (28U)\r
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk\r
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMBR_DU_Pos (24U)\r
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk\r
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBR_MSK3_Pos (23U)\r
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk\r
+#define RTC_ALRMBR_PM_Pos (22U)\r
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk\r
+#define RTC_ALRMBR_HT_Pos (20U)\r
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk\r
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMBR_HU_Pos (16U)\r
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk\r
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMBR_MSK2_Pos (15U)\r
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk\r
+#define RTC_ALRMBR_MNT_Pos (12U)\r
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk\r
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMBR_MNU_Pos (8U)\r
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk\r
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMBR_MSK1_Pos (7U)\r
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk\r
+#define RTC_ALRMBR_ST_Pos (4U)\r
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk\r
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMBR_SU_Pos (0U)\r
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk\r
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY_Pos (0U)\r
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */\r
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS_Pos (0U)\r
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_SSR_SS RTC_SSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS_Pos (0U)\r
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */\r
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk\r
+#define RTC_SHIFTR_ADD1S_Pos (31U)\r
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */\r
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM_Pos (22U)\r
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk\r
+#define RTC_TSTR_HT_Pos (20U)\r
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk\r
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TSTR_HU_Pos (16U)\r
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk\r
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TSTR_MNT_Pos (12U)\r
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk\r
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TSTR_MNU_Pos (8U)\r
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk\r
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSTR_ST_Pos (4U)\r
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk\r
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TSTR_SU_Pos (0U)\r
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk\r
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU_Pos (13U)\r
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk\r
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_TSDR_MT_Pos (12U)\r
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk\r
+#define RTC_TSDR_MU_Pos (8U)\r
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk\r
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSDR_DT_Pos (4U)\r
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk\r
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_TSDR_DU_Pos (0U)\r
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk\r
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS_Pos (0U)\r
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_CALR register *****************/\r
+#define RTC_CALR_CALP_Pos (15U)\r
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */\r
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk\r
+#define RTC_CALR_CALW8_Pos (14U)\r
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */\r
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk\r
+#define RTC_CALR_CALW16_Pos (13U)\r
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */\r
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk\r
+#define RTC_CALR_CALM_Pos (0U)\r
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */\r
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk\r
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */\r
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */\r
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */\r
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */\r
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */\r
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */\r
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */\r
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */\r
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */\r
+\r
+/******************** Bits definition for RTC_TAMPCR register ***************/\r
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)\r
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */\r
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk\r
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)\r
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */\r
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)\r
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */\r
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk\r
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)\r
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */\r
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk\r
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)\r
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */\r
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)\r
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */\r
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk\r
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)\r
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */\r
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk\r
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)\r
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */\r
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)\r
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */\r
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk\r
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)\r
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */\r
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk\r
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)\r
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */\r
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk\r
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */\r
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */\r
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)\r
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */\r
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk\r
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */\r
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */\r
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)\r
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */\r
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk\r
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */\r
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */\r
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */\r
+#define RTC_TAMPCR_TAMPTS_Pos (7U)\r
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */\r
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk\r
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)\r
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */\r
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk\r
+#define RTC_TAMPCR_TAMP3E_Pos (5U)\r
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */\r
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk\r
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)\r
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */\r
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk\r
+#define RTC_TAMPCR_TAMP2E_Pos (3U)\r
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */\r
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk\r
+#define RTC_TAMPCR_TAMPIE_Pos (2U)\r
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */\r
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk\r
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)\r
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */\r
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk\r
+#define RTC_TAMPCR_TAMP1E_Pos (0U)\r
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */\r
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS_Pos (24U)\r
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk\r
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMASSR_SS_Pos (0U)\r
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)\r
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk\r
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBSSR_SS_Pos (0U)\r
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_OR register *******************/\r
+#define RTC_OR_OUT_RMP_Pos (1U)\r
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */\r
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk\r
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)\r
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */\r
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R_Pos (0U)\r
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP0R RTC_BKP0R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R_Pos (0U)\r
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP1R RTC_BKP1R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R_Pos (0U)\r
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP2R RTC_BKP2R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R_Pos (0U)\r
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP3R RTC_BKP3R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R_Pos (0U)\r
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP4R RTC_BKP4R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R_Pos (0U)\r
+#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP5R RTC_BKP5R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R_Pos (0U)\r
+#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP6R RTC_BKP6R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R_Pos (0U)\r
+#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP7R RTC_BKP7R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R_Pos (0U)\r
+#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP8R RTC_BKP8R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R_Pos (0U)\r
+#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP9R RTC_BKP9R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R_Pos (0U)\r
+#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP10R RTC_BKP10R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R_Pos (0U)\r
+#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP11R RTC_BKP11R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R_Pos (0U)\r
+#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP12R RTC_BKP12R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R_Pos (0U)\r
+#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP13R RTC_BKP13R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R_Pos (0U)\r
+#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP14R RTC_BKP14R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R_Pos (0U)\r
+#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP15R RTC_BKP15R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R_Pos (0U)\r
+#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP16R RTC_BKP16R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R_Pos (0U)\r
+#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP17R RTC_BKP17R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R_Pos (0U)\r
+#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP18R RTC_BKP18R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R_Pos (0U)\r
+#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP19R RTC_BKP19R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R_Pos (0U)\r
+#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP20R RTC_BKP20R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R_Pos (0U)\r
+#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP21R RTC_BKP21R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R_Pos (0U)\r
+#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP22R RTC_BKP22R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R_Pos (0U)\r
+#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP23R RTC_BKP23R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R_Pos (0U)\r
+#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP24R RTC_BKP24R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R_Pos (0U)\r
+#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP25R RTC_BKP25R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R_Pos (0U)\r
+#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP26R RTC_BKP26R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R_Pos (0U)\r
+#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP27R RTC_BKP27R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R_Pos (0U)\r
+#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP28R RTC_BKP28R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R_Pos (0U)\r
+#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP29R RTC_BKP29R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R_Pos (0U)\r
+#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP30R RTC_BKP30R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R_Pos (0U)\r
+#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP31R RTC_BKP31R_Msk\r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER_Pos (5U)\r
+#define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) /*!< 0x00000020 */\r
+#define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SPDIF-RX Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SPDIF_CR register ******************/\r
+#define SPDIFRX_CR_SPDIFEN_Pos (0U)\r
+#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */\r
+#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */\r
+#define SPDIFRX_CR_RXDMAEN_Pos (2U)\r
+#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */\r
+#define SPDIFRX_CR_RXSTEO_Pos (3U)\r
+#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */\r
+#define SPDIFRX_CR_DRFMT_Pos (4U)\r
+#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */\r
+#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */\r
+#define SPDIFRX_CR_PMSK_Pos (6U)\r
+#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */\r
+#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */\r
+#define SPDIFRX_CR_VMSK_Pos (7U)\r
+#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */\r
+#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */\r
+#define SPDIFRX_CR_CUMSK_Pos (8U)\r
+#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */\r
+#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */\r
+#define SPDIFRX_CR_PTMSK_Pos (9U)\r
+#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */\r
+#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */\r
+#define SPDIFRX_CR_CBDMAEN_Pos (10U)\r
+#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */\r
+#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */\r
+#define SPDIFRX_CR_CHSEL_Pos (11U)\r
+#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */\r
+#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */\r
+#define SPDIFRX_CR_NBTR_Pos (12U)\r
+#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */\r
+#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */\r
+#define SPDIFRX_CR_WFA_Pos (14U)\r
+#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */\r
+#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */\r
+#define SPDIFRX_CR_INSEL_Pos (16U)\r
+#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */\r
+#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */\r
+#define SPDIFRX_CR_CKSEN_Pos (20U)\r
+#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */\r
+#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */\r
+#define SPDIFRX_CR_CKSBKPEN_Pos (21U)\r
+#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */\r
+#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */\r
+\r
+/******************* Bit definition for SPDIFRX_IMR register *******************/\r
+#define SPDIFRX_IMR_RXNEIE_Pos (0U)\r
+#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */\r
+#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */\r
+#define SPDIFRX_IMR_CSRNEIE_Pos (1U)\r
+#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */\r
+#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */\r
+#define SPDIFRX_IMR_PERRIE_Pos (2U)\r
+#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */\r
+#define SPDIFRX_IMR_OVRIE_Pos (3U)\r
+#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */\r
+#define SPDIFRX_IMR_SBLKIE_Pos (4U)\r
+#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */\r
+#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */\r
+#define SPDIFRX_IMR_SYNCDIE_Pos (5U)\r
+#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */\r
+#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */\r
+#define SPDIFRX_IMR_IFEIE_Pos (6U)\r
+#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */\r
+#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */\r
+\r
+/******************* Bit definition for SPDIFRX_SR register *******************/\r
+#define SPDIFRX_SR_RXNE_Pos (0U)\r
+#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */\r
+#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */\r
+#define SPDIFRX_SR_CSRNE_Pos (1U)\r
+#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */\r
+#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */\r
+#define SPDIFRX_SR_PERR_Pos (2U)\r
+#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */\r
+#define SPDIFRX_SR_OVR_Pos (3U)\r
+#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */\r
+#define SPDIFRX_SR_SBD_Pos (4U)\r
+#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */\r
+#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */\r
+#define SPDIFRX_SR_SYNCD_Pos (5U)\r
+#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */\r
+#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */\r
+#define SPDIFRX_SR_FERR_Pos (6U)\r
+#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */\r
+#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */\r
+#define SPDIFRX_SR_SERR_Pos (7U)\r
+#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */\r
+#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */\r
+#define SPDIFRX_SR_TERR_Pos (8U)\r
+#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */\r
+#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */\r
+#define SPDIFRX_SR_WIDTH5_Pos (16U)\r
+#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */\r
+#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */\r
+\r
+/******************* Bit definition for SPDIFRX_IFCR register *******************/\r
+#define SPDIFRX_IFCR_PERRCF_Pos (2U)\r
+#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */\r
+#define SPDIFRX_IFCR_OVRCF_Pos (3U)\r
+#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */\r
+#define SPDIFRX_IFCR_SBDCF_Pos (4U)\r
+#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */\r
+#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */\r
+#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)\r
+#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */\r
+#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/\r
+#define SPDIFRX_DR0_DR_Pos (0U)\r
+#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */\r
+#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */\r
+#define SPDIFRX_DR0_PE_Pos (24U)\r
+#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */\r
+#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */\r
+#define SPDIFRX_DR0_V_Pos (25U)\r
+#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */\r
+#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */\r
+#define SPDIFRX_DR0_U_Pos (26U)\r
+#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */\r
+#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */\r
+#define SPDIFRX_DR0_C_Pos (27U)\r
+#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */\r
+#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */\r
+#define SPDIFRX_DR0_PT_Pos (28U)\r
+#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */\r
+#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/\r
+#define SPDIFRX_DR1_DR_Pos (8U)\r
+#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */\r
+#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */\r
+#define SPDIFRX_DR1_PT_Pos (4U)\r
+#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */\r
+#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */\r
+#define SPDIFRX_DR1_C_Pos (3U)\r
+#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */\r
+#define SPDIFRX_DR1_U_Pos (2U)\r
+#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */\r
+#define SPDIFRX_DR1_V_Pos (1U)\r
+#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */\r
+#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */\r
+#define SPDIFRX_DR1_PE_Pos (0U)\r
+#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */\r
+#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/\r
+#define SPDIFRX_DR1_DRNL1_Pos (16U)\r
+#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */\r
+#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */\r
+#define SPDIFRX_DR1_DRNL2_Pos (0U)\r
+#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */\r
+#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */\r
+\r
+/******************* Bit definition for SPDIFRX_CSR register *******************/\r
+#define SPDIFRX_CSR_USR_Pos (0U)\r
+#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */\r
+#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */\r
+#define SPDIFRX_CSR_CS_Pos (16U)\r
+#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */\r
+#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */\r
+#define SPDIFRX_CSR_SOB_Pos (24U)\r
+#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */\r
+#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */\r
+\r
+/******************* Bit definition for SPDIFRX_DIR register *******************/\r
+#define SPDIFRX_DIR_THI_Pos (0U)\r
+#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */\r
+#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */\r
+#define SPDIFRX_DIR_TLO_Pos (16U)\r
+#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */\r
+#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */\r
+\r
+/******************* Bit definition for SPDIFRX_VERR register *******************/\r
+#define SPDIFRX_VERR_MINREV_Pos (0U)\r
+#define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */\r
+#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */\r
+#define SPDIFRX_VERR_MAJREV_Pos (4U)\r
+#define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */\r
+#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */\r
+\r
+/******************* Bit definition for SPDIFRX_IDR register *******************/\r
+#define SPDIFRX_IDR_ID_Pos (0U)\r
+#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */\r
+#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */\r
+\r
+/******************* Bit definition for SPDIFRX_SIDR register *******************/\r
+#define SPDIFRX_SIDR_SID_Pos (0U)\r
+#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */\r
+#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Audio Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************************* SAI VERSION ********************************/\r
+#define SAI_VER_V2_X\r
+\r
+/******************** Bit definition for SAI_GCR register *******************/\r
+#define SAI_GCR_SYNCIN_Pos (0U)\r
+#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */\r
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
+#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */\r
+#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */\r
+\r
+#define SAI_GCR_SYNCOUT_Pos (4U)\r
+#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */\r
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */\r
+#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */\r
+\r
+/******************* Bit definition for SAI_xCR1 register *******************/\r
+#define SAI_xCR1_MODE_Pos (0U)\r
+#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */\r
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */\r
+#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */\r
+#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */\r
+\r
+#define SAI_xCR1_PRTCFG_Pos (2U)\r
+#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */\r
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
+#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */\r
+\r
+#define SAI_xCR1_DS_Pos (5U)\r
+#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */\r
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */\r
+#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */\r
+#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xCR1_LSBFIRST_Pos (8U)\r
+#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */\r
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */\r
+#define SAI_xCR1_CKSTR_Pos (9U)\r
+#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */\r
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */\r
+\r
+#define SAI_xCR1_SYNCEN_Pos (10U)\r
+#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */\r
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */\r
+#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */\r
+\r
+#define SAI_xCR1_MONO_Pos (12U)\r
+#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */\r
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */\r
+#define SAI_xCR1_OUTDRIV_Pos (13U)\r
+#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */\r
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */\r
+#define SAI_xCR1_SAIEN_Pos (16U)\r
+#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */\r
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */\r
+#define SAI_xCR1_DMAEN_Pos (17U)\r
+#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */\r
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */\r
+#define SAI_xCR1_NODIV_Pos (19U)\r
+#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */\r
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */\r
+\r
+#define SAI_xCR1_MCKDIV_Pos (20U)\r
+#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */\r
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */\r
+#define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */\r
+#define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */\r
+#define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */\r
+#define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */\r
+#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */\r
+#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */\r
+\r
+#define SAI_xCR1_MCKEN_Pos (27U)\r
+#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */\r
+#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */\r
+\r
+#define SAI_xCR1_OSR_Pos (26U)\r
+#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */\r
+#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */\r
+\r
+/* Legacy define */\r
+#define SAI_xCR1_NOMCK SAI_xCR1_NODIV\r
+\r
+/******************* Bit definition for SAI_xCR2 register *******************/\r
+#define SAI_xCR2_FTH_Pos (0U)\r
+#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */\r
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */\r
+#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */\r
+#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */\r
+#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */\r
+\r
+#define SAI_xCR2_FFLUSH_Pos (3U)\r
+#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */\r
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */\r
+#define SAI_xCR2_TRIS_Pos (4U)\r
+#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */\r
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE_Pos (5U)\r
+#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */\r
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */\r
+#define SAI_xCR2_MUTEVAL_Pos (6U)\r
+#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */\r
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */\r
+\r
+#define SAI_xCR2_MUTECNT_Pos (7U)\r
+#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */\r
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */\r
+#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */\r
+#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */\r
+#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */\r
+#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */\r
+#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */\r
+\r
+#define SAI_xCR2_CPL_Pos (13U)\r
+#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */\r
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */\r
+\r
+#define SAI_xCR2_COMP_Pos (14U)\r
+#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */\r
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */\r
+#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */\r
+\r
+/****************** Bit definition for SAI_xFRCR register *******************/\r
+#define SAI_xFRCR_FRL_Pos (0U)\r
+#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */\r
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */\r
+#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */\r
+#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */\r
+#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */\r
+#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */\r
+#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */\r
+#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */\r
+#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */\r
+#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xFRCR_FSALL_Pos (8U)\r
+#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */\r
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */\r
+#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */\r
+#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */\r
+#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */\r
+#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */\r
+#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */\r
+#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */\r
+#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */\r
+\r
+#define SAI_xFRCR_FSDEF_Pos (16U)\r
+#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */\r
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPOL_Pos (17U)\r
+#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */\r
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */\r
+#define SAI_xFRCR_FSOFF_Pos (18U)\r
+#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */\r
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */\r
+\r
+/* Legacy define */\r
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL\r
+\r
+/****************** Bit definition for SAI_xSLOTR register *******************/\r
+#define SAI_xSLOTR_FBOFF_Pos (0U)\r
+#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */\r
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */\r
+#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */\r
+#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */\r
+#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */\r
+#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */\r
+#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */\r
+\r
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)\r
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */\r
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */\r
+#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */\r
+#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xSLOTR_NBSLOT_Pos (8U)\r
+#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */\r
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
+#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */\r
+#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */\r
+#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */\r
+#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */\r
+\r
+#define SAI_xSLOTR_SLOTEN_Pos (16U)\r
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */\r
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */\r
+\r
+/******************* Bit definition for SAI_xIMR register *******************/\r
+#define SAI_xIMR_OVRUDRIE_Pos (0U)\r
+#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */\r
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */\r
+#define SAI_xIMR_MUTEDETIE_Pos (1U)\r
+#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */\r
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */\r
+#define SAI_xIMR_WCKCFGIE_Pos (2U)\r
+#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */\r
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */\r
+#define SAI_xIMR_FREQIE_Pos (3U)\r
+#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */\r
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */\r
+#define SAI_xIMR_CNRDYIE_Pos (4U)\r
+#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */\r
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */\r
+#define SAI_xIMR_AFSDETIE_Pos (5U)\r
+#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */\r
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */\r
+#define SAI_xIMR_LFSDETIE_Pos (6U)\r
+#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */\r
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */\r
+\r
+/******************** Bit definition for SAI_xSR register *******************/\r
+#define SAI_xSR_OVRUDR_Pos (0U)\r
+#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */\r
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */\r
+#define SAI_xSR_MUTEDET_Pos (1U)\r
+#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */\r
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */\r
+#define SAI_xSR_WCKCFG_Pos (2U)\r
+#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */\r
+#define SAI_xSR_FREQ_Pos (3U)\r
+#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */\r
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */\r
+#define SAI_xSR_CNRDY_Pos (4U)\r
+#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */\r
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */\r
+#define SAI_xSR_AFSDET_Pos (5U)\r
+#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */\r
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */\r
+#define SAI_xSR_LFSDET_Pos (6U)\r
+#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */\r
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */\r
+\r
+#define SAI_xSR_FLVL_Pos (16U)\r
+#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */\r
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */\r
+#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */\r
+#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */\r
+#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */\r
+\r
+/****************** Bit definition for SAI_xCLRFR register ******************/\r
+#define SAI_xCLRFR_COVRUDR_Pos (0U)\r
+#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */\r
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */\r
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)\r
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */\r
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */\r
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)\r
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */\r
+#define SAI_xCLRFR_CFREQ_Pos (3U)\r
+#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */\r
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */\r
+#define SAI_xCLRFR_CCNRDY_Pos (4U)\r
+#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */\r
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */\r
+#define SAI_xCLRFR_CAFSDET_Pos (5U)\r
+#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */\r
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */\r
+#define SAI_xCLRFR_CLFSDET_Pos (6U)\r
+#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */\r
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */\r
+\r
+/****************** Bit definition for SAI_xDR register *********************/\r
+#define SAI_xDR_DATA_Pos (0U)\r
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk\r
+\r
+/******************* Bit definition for SAI_PDMCR register ******************/\r
+#define SAI_PDMCR_PDMEN_Pos (0U)\r
+#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */\r
+#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */\r
+\r
+#define SAI_PDMCR_MICNBR_Pos (4U)\r
+#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */\r
+#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */\r
+#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */\r
+#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */\r
+\r
+#define SAI_PDMCR_CKEN1_Pos (8U)\r
+#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */\r
+#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */\r
+#define SAI_PDMCR_CKEN2_Pos (9U)\r
+#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */\r
+#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */\r
+#define SAI_PDMCR_CKEN3_Pos (10U)\r
+#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */\r
+#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */\r
+#define SAI_PDMCR_CKEN4_Pos (11U)\r
+#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */\r
+#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */\r
+\r
+/****************** Bit definition for SAI_PDMDLY register ******************/\r
+#define SAI_PDMDLY_DLYM1L_Pos (0U)\r
+#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */\r
+#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */\r
+#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */\r
+#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */\r
+#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */\r
+\r
+#define SAI_PDMDLY_DLYM1R_Pos (4U)\r
+#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */\r
+#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */\r
+#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */\r
+#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */\r
+#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */\r
+\r
+#define SAI_PDMDLY_DLYM2L_Pos (8U)\r
+#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */\r
+#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */\r
+#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */\r
+#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */\r
+#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */\r
+\r
+#define SAI_PDMDLY_DLYM2R_Pos (12U)\r
+#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */\r
+#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/\r
+#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */\r
+#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */\r
+#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */\r
+\r
+#define SAI_PDMDLY_DLYM3L_Pos (16U)\r
+#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */\r
+#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/\r
+#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */\r
+#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */\r
+#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */\r
+\r
+#define SAI_PDMDLY_DLYM3R_Pos (20U)\r
+#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */\r
+#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/\r
+#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */\r
+#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */\r
+#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */\r
+\r
+#define SAI_PDMDLY_DLYM4L_Pos (24U)\r
+#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */\r
+#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/\r
+#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */\r
+#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */\r
+#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */\r
+\r
+#define SAI_PDMDLY_DLYM4R_Pos (28U)\r
+#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */\r
+#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/\r
+#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */\r
+#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */\r
+#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SDMMC Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDMMC_POWER register ******************/\r
+#define SDMMC_POWER_PWRCTRL_Pos (0U)\r
+#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */\r
+#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */\r
+#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */\r
+#define SDMMC_POWER_VSWITCH_Pos (2U)\r
+#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */\r
+#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */\r
+#define SDMMC_POWER_VSWITCHEN_Pos (3U)\r
+#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */\r
+#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */\r
+#define SDMMC_POWER_DIRPOL_Pos (4U)\r
+#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */\r
+#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */\r
+\r
+/****************** Bit definition for SDMMC_CLKCR register ******************/\r
+#define SDMMC_CLKCR_CLKDIV_Pos (0U)\r
+#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */\r
+#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */\r
+#define SDMMC_CLKCR_PWRSAV_Pos (12U)\r
+#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */\r
+#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */\r
+\r
+#define SDMMC_CLKCR_WIDBUS_Pos (14U)\r
+#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */\r
+#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */\r
+#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */\r
+\r
+#define SDMMC_CLKCR_NEGEDGE_Pos (16U)\r
+#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */\r
+#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */\r
+#define SDMMC_CLKCR_HWFC_EN_Pos (17U)\r
+#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */\r
+#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */\r
+#define SDMMC_CLKCR_DDR_Pos (18U)\r
+#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */\r
+#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */\r
+#define SDMMC_CLKCR_BUSSPEED_Pos (19U)\r
+#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */\r
+#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */\r
+#define SDMMC_CLKCR_SELCLKRX_Pos (20U)\r
+#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */\r
+#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */\r
+#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */\r
+#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */\r
+\r
+/******************* Bit definition for SDMMC_ARG register *******************/\r
+#define SDMMC_ARG_CMDARG_Pos (0U)\r
+#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */\r
+\r
+/******************* Bit definition for SDMMC_CMD register *******************/\r
+#define SDMMC_CMD_CMDINDEX_Pos (0U)\r
+#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */\r
+#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */\r
+#define SDMMC_CMD_CMDTRANS_Pos (6U)\r
+#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */\r
+#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */\r
+#define SDMMC_CMD_CMDSTOP_Pos (7U)\r
+#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */\r
+#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */\r
+\r
+#define SDMMC_CMD_WAITRESP_Pos (8U)\r
+#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */\r
+#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */\r
+#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */\r
+\r
+#define SDMMC_CMD_WAITINT_Pos (10U)\r
+#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */\r
+#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */\r
+#define SDMMC_CMD_WAITPEND_Pos (11U)\r
+#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */\r
+#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDMMC_CMD_CPSMEN_Pos (12U)\r
+#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */\r
+#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDMMC_CMD_DTHOLD_Pos (13U)\r
+#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */\r
+#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */\r
+#define SDMMC_CMD_BOOTMODE_Pos (14U)\r
+#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */\r
+#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */\r
+#define SDMMC_CMD_BOOTEN_Pos (15U)\r
+#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */\r
+#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */\r
+#define SDMMC_CMD_CMDSUSPEND_Pos (16U)\r
+#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */\r
+#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */\r
+\r
+/***************** Bit definition for SDMMC_RESPCMD register *****************/\r
+#define SDMMC_RESPCMD_RESPCMD_Pos (0U)\r
+#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */\r
+#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */\r
+\r
+/****************** Bit definition for SDMMC_RESP0 register ******************/\r
+#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)\r
+#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP1 register ******************/\r
+#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)\r
+#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP2 register ******************/\r
+#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)\r
+#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP3 register ******************/\r
+#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)\r
+#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP4 register ******************/\r
+#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)\r
+#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_DTIMER register *****************/\r
+#define SDMMC_DTIMER_DATATIME_Pos (0U)\r
+#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDMMC_DLEN register *******************/\r
+#define SDMMC_DLEN_DATALENGTH_Pos (0U)\r
+#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */\r
+\r
+/****************** Bit definition for SDMMC_DCTRL register ******************/\r
+#define SDMMC_DCTRL_DTEN_Pos (0U)\r
+#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */\r
+#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */\r
+#define SDMMC_DCTRL_DTDIR_Pos (1U)\r
+#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */\r
+#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */\r
+#define SDMMC_DCTRL_DTMODE_Pos (2U)\r
+#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */\r
+#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */\r
+#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */\r
+#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */\r
+\r
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)\r
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */\r
+\r
+#define SDMMC_DCTRL_RWSTART_Pos (8U)\r
+#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */\r
+#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */\r
+#define SDMMC_DCTRL_RWSTOP_Pos (9U)\r
+#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */\r
+#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */\r
+#define SDMMC_DCTRL_RWMOD_Pos (10U)\r
+#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */\r
+#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */\r
+#define SDMMC_DCTRL_SDIOEN_Pos (11U)\r
+#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */\r
+#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */\r
+#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)\r
+#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */\r
+#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */\r
+#define SDMMC_DCTRL_FIFORST_Pos (13U)\r
+#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */\r
+#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */\r
+\r
+/****************** Bit definition for SDMMC_DCOUNT register *****************/\r
+#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)\r
+#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */\r
+\r
+/****************** Bit definition for SDMMC_STA register ********************/\r
+#define SDMMC_STA_CCRCFAIL_Pos (0U)\r
+#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */\r
+#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */\r
+#define SDMMC_STA_DCRCFAIL_Pos (1U)\r
+#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */\r
+#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */\r
+#define SDMMC_STA_CTIMEOUT_Pos (2U)\r
+#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */\r
+#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */\r
+#define SDMMC_STA_DTIMEOUT_Pos (3U)\r
+#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */\r
+#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */\r
+#define SDMMC_STA_TXUNDERR_Pos (4U)\r
+#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */\r
+#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */\r
+#define SDMMC_STA_RXOVERR_Pos (5U)\r
+#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */\r
+#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */\r
+#define SDMMC_STA_CMDREND_Pos (6U)\r
+#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */\r
+#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */\r
+#define SDMMC_STA_CMDSENT_Pos (7U)\r
+#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */\r
+#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */\r
+#define SDMMC_STA_DATAEND_Pos (8U)\r
+#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */\r
+#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDMMC_STA_DHOLD_Pos (9U)\r
+#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */\r
+#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */\r
+#define SDMMC_STA_DBCKEND_Pos (10U)\r
+#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */\r
+#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */\r
+#define SDMMC_STA_DABORT_Pos (11U)\r
+#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */\r
+#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */\r
+#define SDMMC_STA_DPSMACT_Pos (12U)\r
+#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */\r
+#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */\r
+#define SDMMC_STA_CPSMACT_Pos (13U)\r
+#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */\r
+#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */\r
+#define SDMMC_STA_TXFIFOHE_Pos (14U)\r
+#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */\r
+#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDMMC_STA_RXFIFOHF_Pos (15U)\r
+#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */\r
+#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDMMC_STA_TXFIFOF_Pos (16U)\r
+#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */\r
+#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */\r
+#define SDMMC_STA_RXFIFOF_Pos (17U)\r
+#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */\r
+#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */\r
+#define SDMMC_STA_TXFIFOE_Pos (18U)\r
+#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */\r
+#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */\r
+#define SDMMC_STA_RXFIFOE_Pos (19U)\r
+#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */\r
+#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */\r
+#define SDMMC_STA_BUSYD0_Pos (20U)\r
+#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */\r
+#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */\r
+#define SDMMC_STA_BUSYD0END_Pos (21U)\r
+#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */\r
+#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */\r
+#define SDMMC_STA_SDIOIT_Pos (22U)\r
+#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */\r
+#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */\r
+#define SDMMC_STA_ACKFAIL_Pos (23U)\r
+#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */\r
+#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */\r
+#define SDMMC_STA_ACKTIMEOUT_Pos (24U)\r
+#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */\r
+#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */\r
+#define SDMMC_STA_VSWEND_Pos (25U)\r
+#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */\r
+#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */\r
+#define SDMMC_STA_CKSTOP_Pos (26U)\r
+#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */\r
+#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */\r
+#define SDMMC_STA_IDMATE_Pos (27U)\r
+#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */\r
+#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */\r
+#define SDMMC_STA_IDMABTC_Pos (28U)\r
+#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */\r
+#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */\r
+\r
+/******************* Bit definition for SDMMC_ICR register *******************/\r
+#define SDMMC_ICR_CCRCFAILC_Pos (0U)\r
+#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */\r
+#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_DCRCFAILC_Pos (1U)\r
+#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */\r
+#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_CTIMEOUTC_Pos (2U)\r
+#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */\r
+#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_DTIMEOUTC_Pos (3U)\r
+#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */\r
+#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_TXUNDERRC_Pos (4U)\r
+#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */\r
+#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */\r
+#define SDMMC_ICR_RXOVERRC_Pos (5U)\r
+#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */\r
+#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */\r
+#define SDMMC_ICR_CMDRENDC_Pos (6U)\r
+#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */\r
+#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */\r
+#define SDMMC_ICR_CMDSENTC_Pos (7U)\r
+#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */\r
+#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */\r
+#define SDMMC_ICR_DATAENDC_Pos (8U)\r
+#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */\r
+#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */\r
+#define SDMMC_ICR_DHOLDC_Pos (9U)\r
+#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */\r
+#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */\r
+#define SDMMC_ICR_DBCKENDC_Pos (10U)\r
+#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */\r
+#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */\r
+#define SDMMC_ICR_DABORTC_Pos (11U)\r
+#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */\r
+#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */\r
+#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)\r
+#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */\r
+#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */\r
+#define SDMMC_ICR_SDIOITC_Pos (22U)\r
+#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */\r
+#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */\r
+#define SDMMC_ICR_ACKFAILC_Pos (23U)\r
+#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */\r
+#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */\r
+#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)\r
+#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */\r
+#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */\r
+#define SDMMC_ICR_VSWENDC_Pos (25U)\r
+#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */\r
+#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */\r
+#define SDMMC_ICR_CKSTOPC_Pos (26U)\r
+#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */\r
+#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */\r
+#define SDMMC_ICR_IDMATEC_Pos (27U)\r
+#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */\r
+#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */\r
+#define SDMMC_ICR_IDMABTCC_Pos (28U)\r
+#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */\r
+#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */\r
+\r
+/****************** Bit definition for SDMMC_MASK register *******************/\r
+#define SDMMC_MASK_CCRCFAILIE_Pos (0U)\r
+#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */\r
+#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_DCRCFAILIE_Pos (1U)\r
+#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */\r
+#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)\r
+#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */\r
+#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)\r
+#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */\r
+#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_TXUNDERRIE_Pos (4U)\r
+#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */\r
+#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDMMC_MASK_RXOVERRIE_Pos (5U)\r
+#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */\r
+#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDMMC_MASK_CMDRENDIE_Pos (6U)\r
+#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */\r
+#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */\r
+#define SDMMC_MASK_CMDSENTIE_Pos (7U)\r
+#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */\r
+#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */\r
+#define SDMMC_MASK_DATAENDIE_Pos (8U)\r
+#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */\r
+#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */\r
+#define SDMMC_MASK_DHOLDIE_Pos (9U)\r
+#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */\r
+#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */\r
+#define SDMMC_MASK_DBCKENDIE_Pos (10U)\r
+#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */\r
+#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */\r
+#define SDMMC_MASK_DABORTIE_Pos (11U)\r
+#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */\r
+#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */\r
+\r
+#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)\r
+#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */\r
+#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)\r
+#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */\r
+#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */\r
+\r
+#define SDMMC_MASK_RXFIFOFIE_Pos (17U)\r
+#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */\r
+#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOEIE_Pos (18U)\r
+#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */\r
+#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */\r
+\r
+#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)\r
+#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */\r
+#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */\r
+#define SDMMC_MASK_SDIOITIE_Pos (22U)\r
+#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */\r
+#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */\r
+#define SDMMC_MASK_ACKFAILIE_Pos (23U)\r
+#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */\r
+#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */\r
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)\r
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */\r
+#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */\r
+#define SDMMC_MASK_VSWENDIE_Pos (25U)\r
+#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */\r
+#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */\r
+#define SDMMC_MASK_CKSTOPIE_Pos (26U)\r
+#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */\r
+#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */\r
+#define SDMMC_MASK_IDMABTCIE_Pos (28U)\r
+#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */\r
+#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */\r
+\r
+/***************** Bit definition for SDMMC_ACKTIME register *****************/\r
+#define SDMMC_ACKTIME_ACKTIME_Pos (0U)\r
+#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */\r
+\r
+/****************** Bit definition for SDMMC_FIFO register *******************/\r
+#define SDMMC_FIFO_FIFODATA_Pos (0U)\r
+#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */\r
+\r
+/****************** Bit definition for SDMMC_IDMACTRL register ****************/\r
+#define SDMMC_IDMA_IDMAEN_Pos (0U)\r
+#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */\r
+#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */\r
+#define SDMMC_IDMA_IDMABMODE_Pos (1U)\r
+#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */\r
+#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */\r
+#define SDMMC_IDMA_IDMABACT_Pos (2U)\r
+#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */\r
+#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */\r
+\r
+/***************** Bit definition for SDMMC_IDMABSIZE register ***************/\r
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)\r
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */\r
+#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */\r
+\r
+/***************** Bit definition for SDMMC_IDMABASE0 register ***************/\r
+#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */\r
+\r
+/***************** Bit definition for SDMMC_IDMABASE1 register ***************/\r
+#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Delay Block Interface (DLYB) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for DLYB_CR register ********************/\r
+#define DLYB_CR_DEN_Pos (0U)\r
+#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */\r
+#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */\r
+#define DLYB_CR_SEN_Pos (1U)\r
+#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */\r
+#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */\r
+\r
+\r
+/******************* Bit definition for DLYB_CFGR register ********************/\r
+#define DLYB_CFGR_SEL_Pos (0U)\r
+#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */\r
+#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */\r
+#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */\r
+#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */\r
+#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */\r
+#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */\r
+\r
+#define DLYB_CFGR_UNIT_Pos (8U)\r
+#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */\r
+#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */\r
+#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */\r
+#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */\r
+#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */\r
+#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */\r
+#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */\r
+#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */\r
+#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */\r
+\r
+#define DLYB_CFGR_LNG_Pos (16U)\r
+#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */\r
+#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */\r
+#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */\r
+#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */\r
+#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */\r
+#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */\r
+#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */\r
+#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */\r
+#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */\r
+#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */\r
+#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */\r
+#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */\r
+#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */\r
+#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */\r
+\r
+#define DLYB_CFGR_LNGF_Pos (31U)\r
+#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */\r
+#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI/I2S) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_SPE_Pos (0U)\r
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */\r
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */\r
+#define SPI_CR1_MASRX_Pos (8U)\r
+#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */\r
+#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */\r
+#define SPI_CR1_CSTART_Pos (9U)\r
+#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */\r
+#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */\r
+#define SPI_CR1_CSUSP_Pos (10U)\r
+#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */\r
+#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */\r
+#define SPI_CR1_HDDIR_Pos (11U)\r
+#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */\r
+#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */\r
+#define SPI_CR1_SSI_Pos (12U)\r
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */\r
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */\r
+#define SPI_CR1_CRC33_17_Pos (13U)\r
+#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */\r
+#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */\r
+#define SPI_CR1_RCRCINI_Pos (14U)\r
+#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */\r
+#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */\r
+#define SPI_CR1_TCRCINI_Pos (15U)\r
+#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */\r
+#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */\r
+#define SPI_CR1_IOLOCK_Pos (16U)\r
+#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */\r
+#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_TSER_Pos (16U)\r
+#define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */\r
+#define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */\r
+#define SPI_CR2_TSIZE_Pos (0U)\r
+#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */\r
+#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */\r
+\r
+/******************* Bit definition for SPI_CFG1 register ********************/\r
+#define SPI_CFG1_DSIZE_Pos (0U)\r
+#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */\r
+#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */\r
+#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */\r
+#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */\r
+#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */\r
+#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */\r
+#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */\r
+\r
+#define SPI_CFG1_FTHLV_Pos (5U)\r
+#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */\r
+#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/\r
+#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */\r
+#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */\r
+#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */\r
+#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */\r
+\r
+#define SPI_CFG1_UDRCFG_Pos (9U)\r
+#define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */\r
+#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */\r
+#define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */\r
+#define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */\r
+\r
+\r
+#define SPI_CFG1_UDRDET_Pos (11U)\r
+#define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */\r
+#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */\r
+#define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */\r
+#define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */\r
+\r
+#define SPI_CFG1_RXDMAEN_Pos (14U)\r
+#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */\r
+#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */\r
+#define SPI_CFG1_TXDMAEN_Pos (15U)\r
+#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */\r
+#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */\r
+\r
+#define SPI_CFG1_CRCSIZE_Pos (16U)\r
+#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */\r
+#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/\r
+#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */\r
+#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */\r
+#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */\r
+#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */\r
+#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */\r
+\r
+#define SPI_CFG1_CRCEN_Pos (22U)\r
+#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */\r
+#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */\r
+\r
+#define SPI_CFG1_MBR_Pos (28U)\r
+#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */\r
+#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */\r
+#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */\r
+#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */\r
+#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */\r
+\r
+/******************* Bit definition for SPI_CFG2 register ********************/\r
+#define SPI_CFG2_MSSI_Pos (0U)\r
+#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */\r
+#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */\r
+#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */\r
+#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */\r
+#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */\r
+#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */\r
+\r
+#define SPI_CFG2_MIDI_Pos (4U)\r
+#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */\r
+#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */\r
+#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */\r
+#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */\r
+#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */\r
+#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */\r
+\r
+#define SPI_CFG2_IOSWP_Pos (15U)\r
+#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */\r
+#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */\r
+\r
+#define SPI_CFG2_COMM_Pos (17U)\r
+#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */\r
+#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/\r
+#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */\r
+#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */\r
+\r
+#define SPI_CFG2_SP_Pos (19U)\r
+#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */\r
+#define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */\r
+#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */\r
+#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */\r
+#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */\r
+\r
+#define SPI_CFG2_MASTER_Pos (22U)\r
+#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */\r
+#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */\r
+#define SPI_CFG2_LSBFRST_Pos (23U)\r
+#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */\r
+#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */\r
+#define SPI_CFG2_CPHA_Pos (24U)\r
+#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */\r
+#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */\r
+#define SPI_CFG2_CPOL_Pos (25U)\r
+#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */\r
+#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */\r
+#define SPI_CFG2_SSM_Pos (26U)\r
+#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */\r
+#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */\r
+\r
+#define SPI_CFG2_SSIOP_Pos (28U)\r
+#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */\r
+#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */\r
+#define SPI_CFG2_SSOE_Pos (29U)\r
+#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */\r
+#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */\r
+#define SPI_CFG2_SSOM_Pos (30U)\r
+#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */\r
+#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */\r
+\r
+#define SPI_CFG2_AFCNTR_Pos (31U)\r
+#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */\r
+#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */\r
+\r
+/******************* Bit definition for SPI_IER register ********************/\r
+#define SPI_IER_RXPIE_Pos (0U)\r
+#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */\r
+#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */\r
+#define SPI_IER_TXPIE_Pos (1U)\r
+#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */\r
+#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */\r
+#define SPI_IER_DXPIE_Pos (2U)\r
+#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */\r
+#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */\r
+#define SPI_IER_EOTIE_Pos (3U)\r
+#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */\r
+#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */\r
+#define SPI_IER_TXTFIE_Pos (4U)\r
+#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */\r
+#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */\r
+#define SPI_IER_UDRIE_Pos (5U)\r
+#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */\r
+#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */\r
+#define SPI_IER_OVRIE_Pos (6U)\r
+#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */\r
+#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */\r
+#define SPI_IER_CRCEIE_Pos (7U)\r
+#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */\r
+#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */\r
+#define SPI_IER_TIFREIE_Pos (8U)\r
+#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */\r
+#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */\r
+#define SPI_IER_MODFIE_Pos (9U)\r
+#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */\r
+#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */\r
+#define SPI_IER_TSERFIE_Pos (10U)\r
+#define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */\r
+#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */\r
+\r
+/******************* Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXP_Pos (0U)\r
+#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */\r
+#define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */\r
+#define SPI_SR_TXP_Pos (1U)\r
+#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */\r
+#define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */\r
+#define SPI_SR_DXP_Pos (2U)\r
+#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */\r
+#define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */\r
+#define SPI_SR_EOT_Pos (3U)\r
+#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */\r
+#define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */\r
+#define SPI_SR_TXTF_Pos (4U)\r
+#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */\r
+#define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */\r
+#define SPI_SR_UDR_Pos (5U)\r
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */\r
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */\r
+#define SPI_SR_OVR_Pos (6U)\r
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */\r
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */\r
+#define SPI_SR_CRCE_Pos (7U)\r
+#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */\r
+#define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */\r
+#define SPI_SR_TIFRE_Pos (8U)\r
+#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */\r
+#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */\r
+#define SPI_SR_MODF_Pos (9U)\r
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */\r
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */\r
+#define SPI_SR_TSERF_Pos (10U)\r
+#define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */\r
+#define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */\r
+#define SPI_SR_SUSP_Pos (11U)\r
+#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */\r
+#define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */\r
+#define SPI_SR_TXC_Pos (12U)\r
+#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */\r
+#define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */\r
+#define SPI_SR_RXPLVL_Pos (13U)\r
+#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */\r
+#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */\r
+#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */\r
+#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */\r
+#define SPI_SR_RXWNE_Pos (15U)\r
+#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */\r
+#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */\r
+#define SPI_SR_CTSIZE_Pos (16U)\r
+#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */\r
+#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */\r
+\r
+/******************* Bit definition for SPI_IFCR register ********************/\r
+#define SPI_IFCR_EOTC_Pos (3U)\r
+#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */\r
+#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */\r
+#define SPI_IFCR_TXTFC_Pos (4U)\r
+#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */\r
+#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */\r
+#define SPI_IFCR_UDRC_Pos (5U)\r
+#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */\r
+#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */\r
+#define SPI_IFCR_OVRC_Pos (6U)\r
+#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */\r
+#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */\r
+#define SPI_IFCR_CRCEC_Pos (7U)\r
+#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */\r
+#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */\r
+#define SPI_IFCR_TIFREC_Pos (8U)\r
+#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */\r
+#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */\r
+#define SPI_IFCR_MODFC_Pos (9U)\r
+#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */\r
+#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */\r
+#define SPI_IFCR_TSERFC_Pos (10U)\r
+#define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */\r
+#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */\r
+#define SPI_IFCR_SUSPC_Pos (11U)\r
+#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */\r
+#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */\r
+\r
+/******************* Bit definition for SPI_TXDR register ********************/\r
+#define SPI_TXDR_TXDR_Pos (0U)\r
+#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */\r
+#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */\r
+\r
+/******************* Bit definition for SPI_RXDR register ********************/\r
+#define SPI_RXDR_RXDR_Pos (0U)\r
+#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */\r
+#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPOLY register ********************/\r
+#define SPI_CRCPOLY_CRCPOLY_Pos (0U)\r
+#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */\r
+#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */\r
+\r
+/******************* Bit definition for SPI_TXCRC register ********************/\r
+#define SPI_TXCRC_TXCRC_Pos (0U)\r
+#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */\r
+#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */\r
+\r
+/******************* Bit definition for SPI_RXCRC register ********************/\r
+#define SPI_RXCRC_RXCRC_Pos (0U)\r
+#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */\r
+#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */\r
+\r
+/******************* Bit definition for SPI_UDRDR register ********************/\r
+#define SPI_UDRDR_UDRDR_Pos (0U)\r
+#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */\r
+#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_I2SMOD_Pos (0U)\r
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */\r
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */\r
+#define SPI_I2SCFGR_I2SCFG_Pos (1U)\r
+#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */\r
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */\r
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */\r
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */\r
+#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */\r
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)\r
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */\r
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */\r
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */\r
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */\r
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)\r
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */\r
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */\r
+#define SPI_I2SCFGR_DATLEN_Pos (8U)\r
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */\r
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */\r
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */\r
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */\r
+#define SPI_I2SCFGR_CHLEN_Pos (10U)\r
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */\r
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */\r
+#define SPI_I2SCFGR_CKPOL_Pos (11U)\r
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */\r
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */\r
+#define SPI_I2SCFGR_FIXCH_Pos (12U)\r
+#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */\r
+#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */\r
+#define SPI_I2SCFGR_WSINV_Pos (13U)\r
+#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */\r
+#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */\r
+#define SPI_I2SCFGR_DATFMT_Pos (14U)\r
+#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */\r
+#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */\r
+#define SPI_I2SCFGR_I2SDIV_Pos (16U)\r
+#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */\r
+#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */\r
+#define SPI_I2SCFGR_ODD_Pos (24U)\r
+#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */\r
+#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */\r
+#define SPI_I2SCFGR_MCKOE_Pos (25U)\r
+#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */\r
+#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* QUADSPI */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for QUADSPI_CR register *******************/\r
+#define QUADSPI_CR_EN_Pos (0U)\r
+#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */\r
+#define QUADSPI_CR_ABORT_Pos (1U)\r
+#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */\r
+#define QUADSPI_CR_DMAEN_Pos (2U)\r
+#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */\r
+#define QUADSPI_CR_TCEN_Pos (3U)\r
+#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */\r
+#define QUADSPI_CR_SSHIFT_Pos (4U)\r
+#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */\r
+#define QUADSPI_CR_DFM_Pos (6U)\r
+#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */\r
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */\r
+#define QUADSPI_CR_FSEL_Pos (7U)\r
+#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */\r
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */\r
+#define QUADSPI_CR_FTHRES_Pos (8U)\r
+#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */\r
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */\r
+#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_CR_TEIE_Pos (16U)\r
+#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */\r
+#define QUADSPI_CR_TCIE_Pos (17U)\r
+#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */\r
+#define QUADSPI_CR_FTIE_Pos (18U)\r
+#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */\r
+#define QUADSPI_CR_SMIE_Pos (19U)\r
+#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */\r
+#define QUADSPI_CR_TOIE_Pos (20U)\r
+#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */\r
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */\r
+#define QUADSPI_CR_APMS_Pos (22U)\r
+#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */\r
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */\r
+#define QUADSPI_CR_PMM_Pos (23U)\r
+#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */\r
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */\r
+#define QUADSPI_CR_PRESCALER_Pos (24U)\r
+#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */\r
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */\r
+#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */\r
+#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */\r
+#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */\r
+#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */\r
+#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */\r
+#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */\r
+#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */\r
+#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */\r
+\r
+/***************** Bit definition for QUADSPI_DCR register ******************/\r
+#define QUADSPI_DCR_CKMODE_Pos (0U)\r
+#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */\r
+#define QUADSPI_DCR_CSHT_Pos (8U)\r
+#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */\r
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */\r
+#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_DCR_FSIZE_Pos (16U)\r
+#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */\r
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */\r
+#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */\r
+\r
+/****************** Bit definition for QUADSPI_SR register *******************/\r
+#define QUADSPI_SR_TEF_Pos (0U)\r
+#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */\r
+#define QUADSPI_SR_TCF_Pos (1U)\r
+#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */\r
+#define QUADSPI_SR_FTF_Pos (2U)\r
+#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_SMF_Pos (3U)\r
+#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */\r
+#define QUADSPI_SR_TOF_Pos (4U)\r
+#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */\r
+#define QUADSPI_SR_BUSY_Pos (5U)\r
+#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */\r
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */\r
+#define QUADSPI_SR_FLEVEL_Pos (8U)\r
+#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */\r
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */\r
+\r
+/****************** Bit definition for QUADSPI_FCR register ******************/\r
+#define QUADSPI_FCR_CTEF_Pos (0U)\r
+#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */\r
+#define QUADSPI_FCR_CTCF_Pos (1U)\r
+#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */\r
+#define QUADSPI_FCR_CSMF_Pos (3U)\r
+#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */\r
+#define QUADSPI_FCR_CTOF_Pos (4U)\r
+#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */\r
+\r
+/****************** Bit definition for QUADSPI_DLR register ******************/\r
+#define QUADSPI_DLR_DL_Pos (0U)\r
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */\r
+\r
+/****************** Bit definition for QUADSPI_CCR register ******************/\r
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)\r
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\r
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */\r
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\r
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\r
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\r
+#define QUADSPI_CCR_IMODE_Pos (8U)\r
+#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */\r
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_CCR_ADMODE_Pos (10U)\r
+#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */\r
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */\r
+#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_CCR_ADSIZE_Pos (12U)\r
+#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */\r
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */\r
+#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */\r
+#define QUADSPI_CCR_ABMODE_Pos (14U)\r
+#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */\r
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
+#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */\r
+#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */\r
+#define QUADSPI_CCR_ABSIZE_Pos (16U)\r
+#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */\r
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_CCR_DCYC_Pos (18U)\r
+#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */\r
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */\r
+#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */\r
+#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */\r
+#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */\r
+#define QUADSPI_CCR_DMODE_Pos (24U)\r
+#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */\r
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */\r
+#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */\r
+#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */\r
+#define QUADSPI_CCR_FMODE_Pos (26U)\r
+#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */\r
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */\r
+#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */\r
+#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */\r
+#define QUADSPI_CCR_SIOO_Pos (28U)\r
+#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */\r
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */\r
+#define QUADSPI_CCR_DHHC_Pos (30U)\r
+#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */\r
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */\r
+#define QUADSPI_CCR_DDRM_Pos (31U)\r
+#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */\r
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */\r
+\r
+/****************** Bit definition for QUADSPI_AR register *******************/\r
+#define QUADSPI_AR_ADDRESS_Pos (0U)\r
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */\r
+\r
+/****************** Bit definition for QUADSPI_ABR register ******************/\r
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)\r
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */\r
+\r
+/****************** Bit definition for QUADSPI_DR register *******************/\r
+#define QUADSPI_DR_DATA_Pos (0U)\r
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */\r
+\r
+/****************** Bit definition for QUADSPI_PSMKR register ****************/\r
+#define QUADSPI_PSMKR_MASK_Pos (0U)\r
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */\r
+\r
+/****************** Bit definition for QUADSPI_PSMAR register ****************/\r
+#define QUADSPI_PSMAR_MATCH_Pos (0U)\r
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */\r
+\r
+/****************** Bit definition for QUADSPI_PIR register *****************/\r
+#define QUADSPI_PIR_INTERVAL_Pos (0U)\r
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\r
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */\r
+\r
+/****************** Bit definition for QUADSPI_LPTR register *****************/\r
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)\r
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\r
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for SYSCFG_PMCR register ******************/\r
+#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)\r
+#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */\r
+#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)\r
+#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */\r
+#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */\r
+#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)\r
+#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */\r
+#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */\r
+#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)\r
+#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */\r
+#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */\r
+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)\r
+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */\r
+#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */\r
+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)\r
+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */\r
+#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */\r
+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)\r
+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */\r
+#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */\r
+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)\r
+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */\r
+#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */\r
+#define SYSCFG_PMCR_BOOSTEN_Pos (8U)\r
+#define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */\r
+#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */\r
+\r
+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)\r
+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */\r
+#define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk /*!< Analog switch supply source selection : VDD/VDDA */\r
+\r
+#define SYSCFG_PMCR_EPIS_SEL_Pos (21U)\r
+#define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00E00000 */\r
+#define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk /*!< Ethernet PHY Interface Selection */\r
+#define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00200000 */\r
+#define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00400000 */\r
+#define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00800000 */\r
+#define SYSCFG_PMCR_PA0SO_Pos (24U)\r
+#define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */\r
+#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */\r
+#define SYSCFG_PMCR_PA1SO_Pos (25U)\r
+#define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */\r
+#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */\r
+#define SYSCFG_PMCR_PC2SO_Pos (26U)\r
+#define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */\r
+#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */\r
+#define SYSCFG_PMCR_PC3SO_Pos (27U)\r
+#define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */\r
+#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)\r
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)\r
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)\r
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)\r
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */\r
+/**\r
+ * @brief EXTI0 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */\r
+\r
+/**\r
+ * @brief EXTI1 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */\r
+/**\r
+ * @brief EXTI2 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */\r
+\r
+/**\r
+ * @brief EXTI3 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)\r
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)\r
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)\r
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)\r
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */\r
+/**\r
+ * @brief EXTI4 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */\r
+/**\r
+ * @brief EXTI5 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */\r
+/**\r
+ * @brief EXTI6 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */\r
+\r
+/**\r
+ * @brief EXTI7 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)\r
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)\r
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)\r
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)\r
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */\r
+\r
+/**\r
+ * @brief EXTI8 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */\r
+\r
+/**\r
+ * @brief EXTI9 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */\r
+\r
+/**\r
+ * @brief EXTI10 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */\r
+\r
+/**\r
+ * @brief EXTI11 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)\r
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)\r
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)\r
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)\r
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */\r
+/**\r
+ * @brief EXTI12 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */\r
+/**\r
+ * @brief EXTI13 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */\r
+/**\r
+ * @brief EXTI14 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */\r
+/**\r
+ * @brief EXTI15 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */\r
+\r
+/****************** Bit definition for SYSCFG_CFGR register ******************/\r
+#define SYSCFG_CFGR_CM4L_Pos (0U)\r
+#define SYSCFG_CFGR_CM4L_Msk (0x1UL << SYSCFG_CFGR_CM4L_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_CFGR_CM4L SYSCFG_CFGR_CM4L_Msk /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */\r
+#define SYSCFG_CFGR_PVDL_Pos (2U)\r
+#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */\r
+#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */\r
+#define SYSCFG_CFGR_FLASHL_Pos (3U)\r
+#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */\r
+#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */\r
+#define SYSCFG_CFGR_CM7L_Pos (6U)\r
+#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */\r
+#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */\r
+#define SYSCFG_CFGR_BKRAML_Pos (7U)\r
+#define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) /*!< 0x00000080 */\r
+#define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk /*!<Backup SRAM double ECC error lock bit */\r
+#define SYSCFG_CFGR_SRAM4L_Pos (9U)\r
+#define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) /*!< 0x00000200 */\r
+#define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk /*!<SRAM4 double ECC error lock bit */\r
+#define SYSCFG_CFGR_SRAM3L_Pos (10U)\r
+#define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) /*!< 0x00000400 */\r
+#define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk /*!<SRAM3 double ECC error lock bit */\r
+#define SYSCFG_CFGR_SRAM2L_Pos (11U)\r
+#define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) /*!< 0x00000800 */\r
+#define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk /*!<SRAM2 double ECC error lock bit */\r
+#define SYSCFG_CFGR_SRAM1L_Pos (12U)\r
+#define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) /*!< 0x00001000 */\r
+#define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk /*!<SRAM1 double ECC error lock bit */\r
+#define SYSCFG_CFGR_DTCML_Pos (13U)\r
+#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */\r
+#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */\r
+#define SYSCFG_CFGR_ITCML_Pos (14U)\r
+#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */\r
+#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */\r
+#define SYSCFG_CFGR_AXISRAML_Pos (15U)\r
+#define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) /*!< 0x00008000 */\r
+#define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk /*!<AXISRAM double ECC error lock bit */\r
+\r
+/****************** Bit definition for SYSCFG_CCCSR register ******************/\r
+#define SYSCFG_CCCSR_EN_Pos (0U)\r
+#define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */\r
+#define SYSCFG_CCCSR_CS_Pos (1U)\r
+#define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */\r
+#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */\r
+#define SYSCFG_CCCSR_READY_Pos (8U)\r
+#define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */\r
+#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */\r
+#define SYSCFG_CCCSR_HSLV_Pos (16U)\r
+#define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */\r
+\r
+/****************** Bit definition for SYSCFG_CCVR register *******************/\r
+#define SYSCFG_CCVR_NCV_Pos (0U)\r
+#define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */\r
+#define SYSCFG_CCVR_PCV_Pos (4U)\r
+#define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */\r
+\r
+/****************** Bit definition for SYSCFG_CCCR register *******************/\r
+#define SYSCFG_CCCR_NCC_Pos (0U)\r
+#define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */\r
+#define SYSCFG_CCCR_PCC_Pos (4U)\r
+#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */\r
+/****************** Bit definition for SYSCFG_PWRCR register *******************/\r
+#define SYSCFG_PWRCR_ODEN_Pos (0U)\r
+#define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk /*!< PWR overdrive enable */\r
+\r
+/****************** Bit definition for SYSCFG_PKGR register *******************/\r
+#define SYSCFG_PKGR_PKG_Pos (0U)\r
+#define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk /*!< Package type */\r
+\r
+/****************** Bit definition for SYSCFG_UR0 register *******************/\r
+#define SYSCFG_UR0_BKS_Pos (0U)\r
+#define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk /*!< Bank Swap */\r
+#define SYSCFG_UR0_RDP_Pos (16U)\r
+#define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) /*!< 0x00FF0000 */\r
+#define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk /*!< Readout protection */\r
+\r
+/****************** Bit definition for SYSCFG_UR1 register *******************/\r
+#define SYSCFG_UR1_BCM4_Pos (0U)\r
+#define SYSCFG_UR1_BCM4_Msk (0x1UL << SYSCFG_UR1_BCM4_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR1_BCM4 SYSCFG_UR1_BCM4_Msk /*!< Boot Cortex-M4 */\r
+#define SYSCFG_UR1_BCM7_Pos (16U)\r
+#define SYSCFG_UR1_BCM7_Msk (0x1UL << SYSCFG_UR1_BCM7_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR1_BCM7 SYSCFG_UR1_BCM7_Msk /*!< Boot Cortex-M7 */\r
+/****************** Bit definition for SYSCFG_UR2 register *******************/\r
+#define SYSCFG_UR2_BORH_Pos (0U)\r
+#define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000003 */\r
+#define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk /*!< Brown Out Reset High level */\r
+#define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000002 */\r
+#define SYSCFG_UR2_BCM7_ADD0_Pos (16U)\r
+#define SYSCFG_UR2_BCM7_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */\r
+#define SYSCFG_UR2_BCM7_ADD0 SYSCFG_UR2_BCM7_ADD0_Msk /*!< Boot Cortex-M7 Address 0 */\r
+/****************** Bit definition for SYSCFG_UR3 register *******************/\r
+#define SYSCFG_UR3_BCM7_ADD1_Pos (0U)\r
+#define SYSCFG_UR3_BCM7_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */\r
+#define SYSCFG_UR3_BCM7_ADD1 SYSCFG_UR3_BCM7_ADD1_Msk /*!< Boot Cortex-M7 Address 1 */\r
+\r
+#define SYSCFG_UR3_BCM4_ADD0_Pos (16U)\r
+#define SYSCFG_UR3_BCM4_ADD0_Msk (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */\r
+#define SYSCFG_UR3_BCM4_ADD0 SYSCFG_UR3_BCM4_ADD0_Msk /*!< Boot Cortex-M4 Address 0 */\r
+\r
+/****************** Bit definition for SYSCFG_UR4 register *******************/\r
+\r
+#define SYSCFG_UR4_BCM4_ADD1_Pos (0U)\r
+#define SYSCFG_UR4_BCM4_ADD1_Msk (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */\r
+#define SYSCFG_UR4_BCM4_ADD1 SYSCFG_UR4_BCM4_ADD1_Msk /*!< Boot Cortex-M4 Address 1 */\r
+\r
+#define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)\r
+#define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk /*!< Mass Erase Protected Area Disabled for bank 1 */\r
+\r
+/****************** Bit definition for SYSCFG_UR5 register *******************/\r
+#define SYSCFG_UR5_MESAD_BANK1_Pos (0U)\r
+#define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk /*!< Mass erase secured area disabled for bank 1 */\r
+#define SYSCFG_UR5_WRPN_BANK1_Pos (16U)\r
+#define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) /*!< 0x00FF0000 */\r
+#define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk /*!< Write protection for flash bank 1 */\r
+\r
+/****************** Bit definition for SYSCFG_UR6 register *******************/\r
+#define SYSCFG_UR6_PABEG_BANK1_Pos (0U)\r
+#define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */\r
+#define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk /*!< Protected area start address for bank 1 */\r
+#define SYSCFG_UR6_PAEND_BANK1_Pos (16U)\r
+#define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */\r
+#define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk /*!< Protected area end address for bank 1 */\r
+\r
+/****************** Bit definition for SYSCFG_UR7 register *******************/\r
+#define SYSCFG_UR7_SABEG_BANK1_Pos (0U)\r
+#define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */\r
+#define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk /*!< Secured area start address for bank 1 */\r
+#define SYSCFG_UR7_SAEND_BANK1_Pos (16U)\r
+#define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */\r
+#define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk /*!< Secured area end address for bank 1 */\r
+\r
+/****************** Bit definition for SYSCFG_UR8 register *******************/\r
+#define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)\r
+#define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk /*!< Mass erase Protected area disabled for bank 2 */\r
+#define SYSCFG_UR8_MESAD_BANK2_Pos (16U)\r
+#define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk /*!< Mass Erase Secured Area Disabled for bank 2 */\r
+\r
+/****************** Bit definition for SYSCFG_UR9 register *******************/\r
+#define SYSCFG_UR9_WRPN_BANK2_Pos (0U)\r
+#define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) /*!< 0x000000FF */\r
+#define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk /*!< Write protection for flash bank 2 */\r
+#define SYSCFG_UR9_PABEG_BANK2_Pos (16U)\r
+#define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */\r
+#define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk /*!< Protected area start address for bank 2 */\r
+\r
+/****************** Bit definition for SYSCFG_UR10 register *******************/\r
+#define SYSCFG_UR10_PAEND_BANK2_Pos (0U)\r
+#define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */\r
+#define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk /*!< Protected area end address for bank 2 */\r
+#define SYSCFG_UR10_SABEG_BANK2_Pos (16U)\r
+#define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */\r
+#define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk /*!< Secured area start address for bank 2 */\r
+\r
+/****************** Bit definition for SYSCFG_UR11 register *******************/\r
+#define SYSCFG_UR11_SAEND_BANK2_Pos (0U)\r
+#define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */\r
+#define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk /*!< Secured area end address for bank 2 */\r
+#define SYSCFG_UR11_IWDG1M_Pos (16U)\r
+#define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk /*!< Independent Watchdog 1 mode (SW or HW) */\r
+\r
+/****************** Bit definition for SYSCFG_UR12 register *******************/\r
+#define SYSCFG_UR12_IWDG2M_Pos (0U)\r
+#define SYSCFG_UR12_IWDG2M_Msk (0x1UL << SYSCFG_UR12_IWDG2M_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR12_IWDG2M SYSCFG_UR12_IWDG2M_Msk /*!< Independent Watchdog 2 mode (SW or HW) */\r
+\r
+#define SYSCFG_UR12_SECURE_Pos (16U)\r
+#define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk /*!< Secure mode status */\r
+\r
+/****************** Bit definition for SYSCFG_UR13 register *******************/\r
+#define SYSCFG_UR13_SDRS_Pos (0U)\r
+#define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) /*!< 0x00000003 */\r
+#define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk /*!< Secured DTCM RAM Size */\r
+#define SYSCFG_UR13_D1SBRST_Pos (16U)\r
+#define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk /*!< D1 Standby reset */\r
+\r
+/****************** Bit definition for SYSCFG_UR14 register *******************/\r
+#define SYSCFG_UR14_D1STPRST_Pos (0U)\r
+#define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk /*!< D1 Stop Reset */\r
+#define SYSCFG_UR14_D2SBRST_Pos (16U)\r
+#define SYSCFG_UR14_D2SBRST_Msk (0x1UL << SYSCFG_UR14_D2SBRST_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR14_D2SBRST SYSCFG_UR14_D2SBRST_Msk /*!< D2 Standby Reset */\r
+\r
+/****************** Bit definition for SYSCFG_UR15 register *******************/\r
+#define SYSCFG_UR15_D2STPRST_Pos (0U)\r
+#define SYSCFG_UR15_D2STPRST_Msk (0x1UL << SYSCFG_UR15_D2STPRST_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR15_D2STPRST SYSCFG_UR15_D2STPRST_Msk /*!< D2 Stop Reset */\r
+#define SYSCFG_UR15_FZIWDGSTB_Pos (16U)\r
+#define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk /*!< Freeze independent watchdogs in Standby mode */\r
+\r
+/****************** Bit definition for SYSCFG_UR16 register *******************/\r
+#define SYSCFG_UR16_FZIWDGSTP_Pos (0U)\r
+#define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk /*!< Freeze independent watchdogs in Stop mode */\r
+#define SYSCFG_UR16_PKP_Pos (16U)\r
+#define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk /*!< Private key programmed */\r
+\r
+/****************** Bit definition for SYSCFG_UR17 register *******************/\r
+#define SYSCFG_UR17_IOHSLV_Pos (0U)\r
+#define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk /*!< I/O high speed / low voltage */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN_Pos (0U)\r
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */\r
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */\r
+#define TIM_CR1_UDIS_Pos (1U)\r
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */\r
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */\r
+#define TIM_CR1_URS_Pos (2U)\r
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */\r
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */\r
+#define TIM_CR1_OPM_Pos (3U)\r
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */\r
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */\r
+#define TIM_CR1_DIR_Pos (4U)\r
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */\r
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */\r
+\r
+#define TIM_CR1_CMS_Pos (5U)\r
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */\r
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */\r
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */\r
+\r
+#define TIM_CR1_ARPE_Pos (7U)\r
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */\r
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD_Pos (8U)\r
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */\r
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */\r
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CR1_UIFREMAP_Pos (11U)\r
+#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */\r
+#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC_Pos (0U)\r
+#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */\r
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS_Pos (2U)\r
+#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */\r
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS_Pos (3U)\r
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */\r
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS_Pos (4U)\r
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */\r
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */\r
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */\r
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */\r
+\r
+#define TIM_CR2_TI1S_Pos (7U)\r
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */\r
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1_Pos (8U)\r
+#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */\r
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N_Pos (9U)\r
+#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */\r
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2_Pos (10U)\r
+#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */\r
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N_Pos (11U)\r
+#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */\r
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3_Pos (12U)\r
+#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */\r
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N_Pos (13U)\r
+#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */\r
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4_Pos (14U)\r
+#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */\r
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS5_Pos (16U)\r
+#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */\r
+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS6_Pos (17U)\r
+#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */\r
+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */\r
+\r
+#define TIM_CR2_MMS2_Pos (20U)\r
+#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */\r
+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */\r
+#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */\r
+#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */\r
+#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS_Pos (0U)\r
+#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */\r
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */\r
+#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */\r
+#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */\r
+#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_SMCR_TS_Pos (4U)\r
+#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */\r
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */\r
+#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */\r
+#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */\r
+#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */\r
+#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */\r
+\r
+#define TIM_SMCR_MSM_Pos (7U)\r
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */\r
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF_Pos (8U)\r
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */\r
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */\r
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */\r
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */\r
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */\r
+\r
+#define TIM_SMCR_ETPS_Pos (12U)\r
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */\r
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */\r
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */\r
+\r
+#define TIM_SMCR_ECE_Pos (14U)\r
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */\r
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */\r
+#define TIM_SMCR_ETP_Pos (15U)\r
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */\r
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE_Pos (0U)\r
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */\r
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE_Pos (1U)\r
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */\r
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE_Pos (2U)\r
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */\r
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE_Pos (3U)\r
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */\r
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE_Pos (4U)\r
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */\r
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE_Pos (5U)\r
+#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */\r
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE_Pos (6U)\r
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */\r
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE_Pos (7U)\r
+#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */\r
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE_Pos (8U)\r
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */\r
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE_Pos (9U)\r
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */\r
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE_Pos (10U)\r
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */\r
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE_Pos (11U)\r
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */\r
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE_Pos (12U)\r
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */\r
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE_Pos (13U)\r
+#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */\r
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE_Pos (14U)\r
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */\r
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF_Pos (0U)\r
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */\r
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF_Pos (1U)\r
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */\r
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF_Pos (2U)\r
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */\r
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF_Pos (3U)\r
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */\r
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF_Pos (4U)\r
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */\r
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF_Pos (5U)\r
+#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */\r
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF_Pos (6U)\r
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */\r
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF_Pos (7U)\r
+#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */\r
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */\r
+#define TIM_SR_B2IF_Pos (8U)\r
+#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */\r
+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */\r
+#define TIM_SR_CC1OF_Pos (9U)\r
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */\r
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF_Pos (10U)\r
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */\r
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF_Pos (11U)\r
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */\r
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF_Pos (12U)\r
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */\r
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */\r
+#define TIM_SR_CC5IF_Pos (16U)\r
+#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */\r
+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */\r
+#define TIM_SR_CC6IF_Pos (17U)\r
+#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */\r
+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */\r
+#define TIM_SR_SBIF_Pos (13U)\r
+#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */\r
+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG_Pos (0U)\r
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */\r
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */\r
+#define TIM_EGR_CC1G_Pos (1U)\r
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */\r
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G_Pos (2U)\r
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */\r
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G_Pos (3U)\r
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */\r
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G_Pos (4U)\r
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */\r
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG_Pos (5U)\r
+#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */\r
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG_Pos (6U)\r
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */\r
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */\r
+#define TIM_EGR_BG_Pos (7U)\r
+#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */\r
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */\r
+#define TIM_EGR_B2G_Pos (8U)\r
+#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */\r
+#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */\r
+\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S_Pos (0U)\r
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR1_OC1FE_Pos (2U)\r
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE_Pos (3U)\r
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M_Pos (4U)\r
+#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */\r
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR1_OC1CE_Pos (7U)\r
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S_Pos (8U)\r
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR1_OC2FE_Pos (10U)\r
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE_Pos (11U)\r
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M_Pos (12U)\r
+#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */\r
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR1_OC2CE_Pos (15U)\r
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC_Pos (2U)\r
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */\r
+\r
+#define TIM_CCMR1_IC1F_Pos (4U)\r
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */\r
+\r
+#define TIM_CCMR1_IC2PSC_Pos (10U)\r
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */\r
+\r
+#define TIM_CCMR1_IC2F_Pos (12U)\r
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S_Pos (0U)\r
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR2_OC3FE_Pos (2U)\r
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE_Pos (3U)\r
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M_Pos (4U)\r
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */\r
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR2_OC3CE_Pos (7U)\r
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S_Pos (8U)\r
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR2_OC4FE_Pos (10U)\r
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE_Pos (11U)\r
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M_Pos (12U)\r
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */\r
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */\r
+\r
+#define TIM_CCMR2_OC4CE_Pos (15U)\r
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC_Pos (2U)\r
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */\r
+\r
+#define TIM_CCMR2_IC3F_Pos (4U)\r
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */\r
+\r
+#define TIM_CCMR2_IC4PSC_Pos (10U)\r
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */\r
+\r
+#define TIM_CCMR2_IC4F_Pos (12U)\r
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E_Pos (0U)\r
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */\r
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P_Pos (1U)\r
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */\r
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE_Pos (2U)\r
+#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP_Pos (3U)\r
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */\r
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E_Pos (4U)\r
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */\r
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P_Pos (5U)\r
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */\r
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE_Pos (6U)\r
+#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */\r
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP_Pos (7U)\r
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */\r
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E_Pos (8U)\r
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */\r
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P_Pos (9U)\r
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */\r
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE_Pos (10U)\r
+#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP_Pos (11U)\r
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */\r
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E_Pos (12U)\r
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */\r
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P_Pos (13U)\r
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */\r
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP_Pos (15U)\r
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */\r
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */\r
+#define TIM_CCER_CC5E_Pos (16U)\r
+#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */\r
+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */\r
+#define TIM_CCER_CC5P_Pos (17U)\r
+#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */\r
+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */\r
+#define TIM_CCER_CC6E_Pos (20U)\r
+#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */\r
+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */\r
+#define TIM_CCER_CC6P_Pos (21U)\r
+#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */\r
+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT_Pos (0U)\r
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */\r
+#define TIM_CNT_UIFCPY_Pos (31U)\r
+#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */\r
+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC_Pos (0U)\r
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */\r
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR_Pos (0U)\r
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP_Pos (0U)\r
+#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */\r
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1_Pos (0U)\r
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2_Pos (0U)\r
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3_Pos (0U)\r
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4_Pos (0U)\r
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_CCR5 register *******************/\r
+#define TIM_CCR5_CCR5_Pos (0U)\r
+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */\r
+#define TIM_CCR5_GC5C1_Pos (29U)\r
+#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */\r
+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */\r
+#define TIM_CCR5_GC5C2_Pos (30U)\r
+#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */\r
+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */\r
+#define TIM_CCR5_GC5C3_Pos (31U)\r
+#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */\r
+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */\r
+\r
+/******************* Bit definition for TIM_CCR6 register *******************/\r
+#define TIM_CCR6_CCR6_Pos (0U)\r
+#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG_Pos (0U)\r
+#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */\r
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */\r
+#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */\r
+#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */\r
+#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */\r
+#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */\r
+#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */\r
+#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */\r
+#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */\r
+\r
+#define TIM_BDTR_LOCK_Pos (8U)\r
+#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */\r
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */\r
+#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_BDTR_OSSI_Pos (10U)\r
+#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */\r
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR_Pos (11U)\r
+#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */\r
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE_Pos (12U)\r
+#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */\r
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */\r
+#define TIM_BDTR_BKP_Pos (13U)\r
+#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */\r
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */\r
+#define TIM_BDTR_AOE_Pos (14U)\r
+#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */\r
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE_Pos (15U)\r
+#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */\r
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */\r
+\r
+#define TIM_BDTR_BKF_Pos (16U)\r
+#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */\r
+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */\r
+#define TIM_BDTR_BK2F_Pos (20U)\r
+#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */\r
+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */\r
+\r
+#define TIM_BDTR_BK2E_Pos (24U)\r
+#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */\r
+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */\r
+#define TIM_BDTR_BK2P_Pos (25U)\r
+#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */\r
+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA_Pos (0U)\r
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */\r
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */\r
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */\r
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */\r
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */\r
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */\r
+\r
+#define TIM_DCR_DBL_Pos (8U)\r
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */\r
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */\r
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */\r
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */\r
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */\r
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB_Pos (0U)\r
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */\r
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */\r
+\r
+/****************** Bit definition for TIM_CCMR3 register *******************/\r
+#define TIM_CCMR3_OC5FE_Pos (2U)\r
+#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */\r
+#define TIM_CCMR3_OC5PE_Pos (3U)\r
+#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */\r
+\r
+#define TIM_CCMR3_OC5M_Pos (4U)\r
+#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */\r
+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r
+#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR3_OC5CE_Pos (7U)\r
+#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */\r
+\r
+#define TIM_CCMR3_OC6FE_Pos (10U)\r
+#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR3_OC6PE_Pos (11U)\r
+#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR3_OC6M_Pos (12U)\r
+#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */\r
+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */\r
+\r
+#define TIM_CCMR3_OC6CE_Pos (15U)\r
+#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */\r
+/******************* Bit definition for TIM1_AF1 register *********************/\r
+#define TIM1_AF1_BKINE_Pos (0U)\r
+#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */\r
+#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */\r
+#define TIM1_AF1_BKCMP1E_Pos (1U)\r
+#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */\r
+#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */\r
+#define TIM1_AF1_BKCMP2E_Pos (2U)\r
+#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */\r
+#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */\r
+#define TIM1_AF1_BKDF1BK0E_Pos (8U)\r
+#define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */\r
+#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */\r
+#define TIM1_AF1_BKINP_Pos (9U)\r
+#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */\r
+#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */\r
+#define TIM1_AF1_BKCMP1P_Pos (10U)\r
+#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */\r
+#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */\r
+#define TIM1_AF1_BKCMP2P_Pos (11U)\r
+#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */\r
+#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */\r
+\r
+#define TIM1_AF1_ETRSEL_Pos (14U)\r
+#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */\r
+#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */\r
+#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */\r
+#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */\r
+#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */\r
+#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */\r
+\r
+/******************* Bit definition for TIM1_AF2 register *********************/\r
+#define TIM1_AF2_BK2INE_Pos (0U)\r
+#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */\r
+#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */\r
+#define TIM1_AF2_BK2CMP1E_Pos (1U)\r
+#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */\r
+#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */\r
+#define TIM1_AF2_BK2CMP2E_Pos (2U)\r
+#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */\r
+#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */\r
+#define TIM1_AF2_BK2DFBK1E_Pos (8U)\r
+#define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */\r
+#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */\r
+#define TIM1_AF2_BK2INP_Pos (9U)\r
+#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */\r
+#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */\r
+#define TIM1_AF2_BK2CMP1P_Pos (10U)\r
+#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */\r
+#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */\r
+#define TIM1_AF2_BK2CMP2P_Pos (11U)\r
+#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */\r
+#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */\r
+\r
+/******************* Bit definition for TIM_TISEL register *********************/\r
+#define TIM_TISEL_TI1SEL_Pos (0U)\r
+#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */\r
+#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/\r
+#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */\r
+#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */\r
+#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */\r
+#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */\r
+\r
+#define TIM_TISEL_TI2SEL_Pos (8U)\r
+#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */\r
+#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/\r
+#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */\r
+#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */\r
+#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */\r
+#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */\r
+\r
+#define TIM_TISEL_TI3SEL_Pos (16U)\r
+#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */\r
+#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/\r
+#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */\r
+#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */\r
+#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */\r
+#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */\r
+\r
+#define TIM_TISEL_TI4SEL_Pos (24U)\r
+#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */\r
+#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/\r
+#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */\r
+#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */\r
+#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */\r
+#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */\r
+\r
+/******************* Bit definition for TIM8_AF1 register *********************/\r
+#define TIM8_AF1_BKINE_Pos (0U)\r
+#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */\r
+#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */\r
+#define TIM8_AF1_BKCMP1E_Pos (1U)\r
+#define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */\r
+#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */\r
+#define TIM8_AF1_BKCMP2E_Pos (2U)\r
+#define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */\r
+#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */\r
+#define TIM8_AF1_BKDFBK2E_Pos (8U)\r
+#define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */\r
+#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */\r
+#define TIM8_AF1_BKINP_Pos (9U)\r
+#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */\r
+#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */\r
+#define TIM8_AF1_BKCMP1P_Pos (10U)\r
+#define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */\r
+#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */\r
+#define TIM8_AF1_BKCMP2P_Pos (11U)\r
+#define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */\r
+#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */\r
+\r
+#define TIM8_AF1_ETRSEL_Pos (14U)\r
+#define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */\r
+#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */\r
+#define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */\r
+#define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */\r
+#define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */\r
+#define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */\r
+/******************* Bit definition for TIM8_AF2 register *********************/\r
+#define TIM8_AF2_BK2INE_Pos (0U)\r
+#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */\r
+#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */\r
+#define TIM8_AF2_BK2CMP1E_Pos (1U)\r
+#define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */\r
+#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */\r
+#define TIM8_AF2_BK2CMP2E_Pos (2U)\r
+#define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */\r
+#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */\r
+#define TIM8_AF2_BK2DFBK3E_Pos (8U)\r
+#define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */\r
+#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */\r
+#define TIM8_AF2_BK2INP_Pos (9U)\r
+#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */\r
+#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */\r
+#define TIM8_AF2_BK2CMP1P_Pos (10U)\r
+#define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */\r
+#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */\r
+#define TIM8_AF2_BK2CMP2P_Pos (11U)\r
+#define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */\r
+#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */\r
+\r
+/******************* Bit definition for TIM2_AF1 register *********************/\r
+#define TIM2_AF1_ETRSEL_Pos (14U)\r
+#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */\r
+#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */\r
+#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */\r
+#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */\r
+#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */\r
+#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */\r
+\r
+/******************* Bit definition for TIM3_AF1 register *********************/\r
+#define TIM3_AF1_ETRSEL_Pos (14U)\r
+#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */\r
+#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */\r
+#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */\r
+#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */\r
+#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */\r
+#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */\r
+\r
+/******************* Bit definition for TIM5_AF1 register *********************/\r
+#define TIM5_AF1_ETRSEL_Pos (14U)\r
+#define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */\r
+#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */\r
+#define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */\r
+#define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */\r
+#define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */\r
+#define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */\r
+\r
+/******************* Bit definition for TIM15_AF1 register *********************/\r
+#define TIM15_AF1_BKINE_Pos (0U)\r
+#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */\r
+#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */\r
+#define TIM15_AF1_BKCMP1E_Pos (1U)\r
+#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */\r
+#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */\r
+#define TIM15_AF1_BKCMP2E_Pos (2U)\r
+#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */\r
+#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */\r
+#define TIM15_AF1_BKDF1BK2E_Pos (8U)\r
+#define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */\r
+#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */\r
+#define TIM15_AF1_BKINP_Pos (9U)\r
+#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */\r
+#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */\r
+#define TIM15_AF1_BKCMP1P_Pos (10U)\r
+#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */\r
+#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */\r
+#define TIM15_AF1_BKCMP2P_Pos (11U)\r
+#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */\r
+#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */\r
+\r
+/******************* Bit definition for TIM16_ register *********************/\r
+#define TIM16_AF1_BKINE_Pos (0U)\r
+#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */\r
+#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */\r
+#define TIM16_AF1_BKCMP1E_Pos (1U)\r
+#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */\r
+#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */\r
+#define TIM16_AF1_BKCMP2E_Pos (2U)\r
+#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */\r
+#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */\r
+#define TIM16_AF1_BKDF1BK2E_Pos (8U)\r
+#define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */\r
+#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */\r
+#define TIM16_AF1_BKINP_Pos (9U)\r
+#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */\r
+#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */\r
+#define TIM16_AF1_BKCMP1P_Pos (10U)\r
+#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */\r
+#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */\r
+#define TIM16_AF1_BKCMP2P_Pos (11U)\r
+#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */\r
+#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */\r
+\r
+/******************* Bit definition for TIM17_AF1 register *********************/\r
+#define TIM17_AF1_BKINE_Pos (0U)\r
+#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */\r
+#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */\r
+#define TIM17_AF1_BKCMP1E_Pos (1U)\r
+#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */\r
+#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */\r
+#define TIM17_AF1_BKCMP2E_Pos (2U)\r
+#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */\r
+#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */\r
+#define TIM17_AF1_BKDF1BK2E_Pos (8U)\r
+#define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */\r
+#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */\r
+#define TIM17_AF1_BKINP_Pos (9U)\r
+#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */\r
+#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */\r
+#define TIM17_AF1_BKCMP1P_Pos (10U)\r
+#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */\r
+#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */\r
+#define TIM17_AF1_BKCMP2P_Pos (11U)\r
+#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */\r
+#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Low Power Timer (LPTTIM) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for LPTIM_ISR register *******************/\r
+#define LPTIM_ISR_CMPM_Pos (0U)\r
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */\r
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */\r
+#define LPTIM_ISR_ARRM_Pos (1U)\r
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */\r
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */\r
+#define LPTIM_ISR_EXTTRIG_Pos (2U)\r
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */\r
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */\r
+#define LPTIM_ISR_CMPOK_Pos (3U)\r
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */\r
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */\r
+#define LPTIM_ISR_ARROK_Pos (4U)\r
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */\r
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */\r
+#define LPTIM_ISR_UP_Pos (5U)\r
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */\r
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */\r
+#define LPTIM_ISR_DOWN_Pos (6U)\r
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */\r
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */\r
+\r
+/****************** Bit definition for LPTIM_ICR register *******************/\r
+#define LPTIM_ICR_CMPMCF_Pos (0U)\r
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */\r
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */\r
+#define LPTIM_ICR_ARRMCF_Pos (1U)\r
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */\r
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */\r
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)\r
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */\r
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */\r
+#define LPTIM_ICR_CMPOKCF_Pos (3U)\r
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */\r
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */\r
+#define LPTIM_ICR_ARROKCF_Pos (4U)\r
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */\r
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */\r
+#define LPTIM_ICR_UPCF_Pos (5U)\r
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */\r
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */\r
+#define LPTIM_ICR_DOWNCF_Pos (6U)\r
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */\r
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */\r
+\r
+/****************** Bit definition for LPTIM_IER register ********************/\r
+#define LPTIM_IER_CMPMIE_Pos (0U)\r
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */\r
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */\r
+#define LPTIM_IER_ARRMIE_Pos (1U)\r
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */\r
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */\r
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)\r
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */\r
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */\r
+#define LPTIM_IER_CMPOKIE_Pos (3U)\r
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */\r
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */\r
+#define LPTIM_IER_ARROKIE_Pos (4U)\r
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */\r
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */\r
+#define LPTIM_IER_UPIE_Pos (5U)\r
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */\r
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */\r
+#define LPTIM_IER_DOWNIE_Pos (6U)\r
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */\r
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */\r
+\r
+/****************** Bit definition for LPTIM_CFGR register *******************/\r
+#define LPTIM_CFGR_CKSEL_Pos (0U)\r
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */\r
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */\r
+\r
+#define LPTIM_CFGR_CKPOL_Pos (1U)\r
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */\r
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */\r
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */\r
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */\r
+\r
+#define LPTIM_CFGR_CKFLT_Pos (3U)\r
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */\r
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */\r
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */\r
+\r
+#define LPTIM_CFGR_TRGFLT_Pos (6U)\r
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */\r
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */\r
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */\r
+\r
+#define LPTIM_CFGR_PRESC_Pos (9U)\r
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */\r
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */\r
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */\r
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */\r
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */\r
+\r
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)\r
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */\r
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */\r
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */\r
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */\r
+\r
+#define LPTIM_CFGR_TRIGEN_Pos (17U)\r
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */\r
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */\r
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */\r
+\r
+#define LPTIM_CFGR_TIMOUT_Pos (19U)\r
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */\r
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */\r
+#define LPTIM_CFGR_WAVE_Pos (20U)\r
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */\r
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */\r
+#define LPTIM_CFGR_WAVPOL_Pos (21U)\r
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */\r
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */\r
+#define LPTIM_CFGR_PRELOAD_Pos (22U)\r
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */\r
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */\r
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)\r
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */\r
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */\r
+#define LPTIM_CFGR_ENC_Pos (24U)\r
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */\r
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */\r
+\r
+/****************** Bit definition for LPTIM_CR register ********************/\r
+#define LPTIM_CR_ENABLE_Pos (0U)\r
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */\r
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */\r
+#define LPTIM_CR_SNGSTRT_Pos (1U)\r
+#define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */\r
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */\r
+#define LPTIM_CR_CNTSTRT_Pos (2U)\r
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */\r
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */\r
+#define LPTIM_CR_COUNTRST_Pos (3U)\r
+#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */\r
+#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/\r
+#define LPTIM_CR_RSTARE_Pos (4U)\r
+#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */\r
+#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/\r
+\r
+\r
+/****************** Bit definition for LPTIM_CMP register *******************/\r
+#define LPTIM_CMP_CMP_Pos (0U)\r
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */\r
+\r
+/****************** Bit definition for LPTIM_ARR register *******************/\r
+#define LPTIM_ARR_ARR_Pos (0U)\r
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */\r
+\r
+/****************** Bit definition for LPTIM_CNT register *******************/\r
+#define LPTIM_CNT_CNT_Pos (0U)\r
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */\r
+\r
+/****************** Bit definition for LPTIM_CFGR2 register *****************/\r
+#define LPTIM_CFGR2_IN1SEL_Pos (0U)\r
+#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */\r
+#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */\r
+#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */\r
+#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */\r
+#define LPTIM_CFGR2_IN2SEL_Pos (4U)\r
+#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */\r
+#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */\r
+#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */\r
+#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog Comparators (COMP) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for COMP_SR register ********************/\r
+#define COMP_SR_C1VAL_Pos (0U)\r
+#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */\r
+#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk\r
+#define COMP_SR_C2VAL_Pos (1U)\r
+#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */\r
+#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk\r
+#define COMP_SR_C1IF_Pos (16U)\r
+#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */\r
+#define COMP_SR_C1IF COMP_SR_C1IF_Msk\r
+#define COMP_SR_C2IF_Pos (17U)\r
+#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */\r
+#define COMP_SR_C2IF COMP_SR_C2IF_Msk\r
+/******************* Bit definition for COMP_ICFR register ********************/\r
+#define COMP_ICFR_C1IF_Pos (16U)\r
+#define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */\r
+#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk\r
+#define COMP_ICFR_C2IF_Pos (17U)\r
+#define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */\r
+#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk\r
+/******************* Bit definition for COMP_OR register ********************/\r
+#define COMP_OR_AFOPA6_Pos (0U)\r
+#define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */\r
+#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk\r
+#define COMP_OR_AFOPA8_Pos (1U)\r
+#define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */\r
+#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk\r
+#define COMP_OR_AFOPB12_Pos (2U)\r
+#define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */\r
+#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk\r
+#define COMP_OR_AFOPE6_Pos (3U)\r
+#define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */\r
+#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk\r
+#define COMP_OR_AFOPE15_Pos (4U)\r
+#define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */\r
+#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk\r
+#define COMP_OR_AFOPG2_Pos (5U)\r
+#define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */\r
+#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk\r
+#define COMP_OR_AFOPG3_Pos (6U)\r
+#define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */\r
+#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk\r
+#define COMP_OR_AFOPG4_Pos (7U)\r
+#define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */\r
+#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk\r
+#define COMP_OR_AFOPI1_Pos (8U)\r
+#define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */\r
+#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk\r
+#define COMP_OR_AFOPI4_Pos (9U)\r
+#define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */\r
+#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk\r
+#define COMP_OR_AFOPK2_Pos (10U)\r
+#define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */\r
+#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk\r
+\r
+/*!< ****************** Bit definition for COMP_CFGRx register ********************/\r
+#define COMP_CFGRx_EN_Pos (0U)\r
+#define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */\r
+#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */\r
+#define COMP_CFGRx_BRGEN_Pos (1U)\r
+#define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */\r
+#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */\r
+#define COMP_CFGRx_SCALEN_Pos (2U)\r
+#define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */\r
+#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */\r
+#define COMP_CFGRx_POLARITY_Pos (3U)\r
+#define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */\r
+#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */\r
+#define COMP_CFGRx_WINMODE_Pos (4U)\r
+#define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */\r
+#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */\r
+#define COMP_CFGRx_ITEN_Pos (6U)\r
+#define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */\r
+#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */\r
+#define COMP_CFGRx_HYST_Pos (8U)\r
+#define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */\r
+#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */\r
+#define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */\r
+#define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */\r
+#define COMP_CFGRx_PWRMODE_Pos (12U)\r
+#define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */\r
+#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */\r
+#define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */\r
+#define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */\r
+#define COMP_CFGRx_INMSEL_Pos (16U)\r
+#define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */\r
+#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */\r
+#define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */\r
+#define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */\r
+#define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */\r
+#define COMP_CFGRx_INPSEL_Pos (20U)\r
+#define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */\r
+#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */\r
+#define COMP_CFGRx_BLANKING_Pos (24U)\r
+#define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */\r
+#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */\r
+#define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */\r
+#define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */\r
+#define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */\r
+#define COMP_CFGRx_LOCK_Pos (31U)\r
+#define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */\r
+#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_UE_Pos (0U)\r
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */\r
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */\r
+#define USART_CR1_UESM_Pos (1U)\r
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */\r
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */\r
+#define USART_CR1_RE_Pos (2U)\r
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */\r
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */\r
+#define USART_CR1_TE_Pos (3U)\r
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */\r
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE_Pos (4U)\r
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */\r
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)\r
+#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */\r
+#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */\r
+#define USART_CR1_TCIE_Pos (6U)\r
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)\r
+#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */\r
+#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */\r
+#define USART_CR1_PEIE_Pos (8U)\r
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */\r
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS_Pos (9U)\r
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */\r
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */\r
+#define USART_CR1_PCE_Pos (10U)\r
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */\r
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE_Pos (11U)\r
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */\r
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */\r
+#define USART_CR1_M_Pos (12U)\r
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */\r
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */\r
+#define USART_CR1_M0_Pos (12U)\r
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */\r
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */\r
+#define USART_CR1_MME_Pos (13U)\r
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */\r
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE_Pos (14U)\r
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */\r
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8_Pos (15U)\r
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */\r
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT_Pos (16U)\r
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */\r
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */\r
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */\r
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */\r
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */\r
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */\r
+#define USART_CR1_DEAT_Pos (21U)\r
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */\r
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */\r
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */\r
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */\r
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */\r
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */\r
+#define USART_CR1_RTOIE_Pos (26U)\r
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */\r
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE_Pos (27U)\r
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */\r
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */\r
+#define USART_CR1_M1_Pos (28U)\r
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */\r
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */\r
+#define USART_CR1_FIFOEN_Pos (29U)\r
+#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */\r
+#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */\r
+#define USART_CR1_TXFEIE_Pos (30U)\r
+#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */\r
+#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */\r
+#define USART_CR1_RXFFIE_Pos (31U)\r
+#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */\r
+#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */\r
+\r
+/* Legacy define */\r
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE\r
+#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_SLVEN_Pos (0U)\r
+#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */\r
+#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */\r
+#define USART_CR2_DIS_NSS_Pos (3U)\r
+#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */\r
+#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */\r
+#define USART_CR2_ADDM7_Pos (4U)\r
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */\r
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL_Pos (5U)\r
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */\r
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE_Pos (6U)\r
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL_Pos (8U)\r
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */\r
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA_Pos (9U)\r
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */\r
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */\r
+#define USART_CR2_CPOL_Pos (10U)\r
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */\r
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN_Pos (11U)\r
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */\r
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */\r
+#define USART_CR2_STOP_Pos (12U)\r
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */\r
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */\r
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */\r
+#define USART_CR2_LINEN_Pos (14U)\r
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */\r
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */\r
+#define USART_CR2_SWAP_Pos (15U)\r
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */\r
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV_Pos (16U)\r
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */\r
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV_Pos (17U)\r
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */\r
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV_Pos (18U)\r
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */\r
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST_Pos (19U)\r
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */\r
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN_Pos (20U)\r
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */\r
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/\r
+#define USART_CR2_ABRMODE_Pos (21U)\r
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */\r
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */\r
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */\r
+#define USART_CR2_RTOEN_Pos (23U)\r
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */\r
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD_Pos (24U)\r
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */\r
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE_Pos (0U)\r
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */\r
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN_Pos (1U)\r
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */\r
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP_Pos (2U)\r
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */\r
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL_Pos (3U)\r
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */\r
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK_Pos (4U)\r
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */\r
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN_Pos (5U)\r
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */\r
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR_Pos (6U)\r
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */\r
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT_Pos (7U)\r
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */\r
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE_Pos (8U)\r
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */\r
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */\r
+#define USART_CR3_CTSE_Pos (9U)\r
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */\r
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */\r
+#define USART_CR3_CTSIE_Pos (10U)\r
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */\r
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT_Pos (11U)\r
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */\r
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS_Pos (12U)\r
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */\r
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */\r
+#define USART_CR3_DDRE_Pos (13U)\r
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */\r
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM_Pos (14U)\r
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */\r
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP_Pos (15U)\r
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */\r
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT_Pos (17U)\r
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */\r
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */\r
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */\r
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */\r
+#define USART_CR3_WUS_Pos (20U)\r
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */\r
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\r
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */\r
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */\r
+#define USART_CR3_WUFIE_Pos (22U)\r
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */\r
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */\r
+#define USART_CR3_TXFTIE_Pos (23U)\r
+#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */\r
+#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */\r
+#define USART_CR3_TCBGTIE_Pos (24U)\r
+#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */\r
+#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */\r
+#define USART_CR3_RXFTCFG_Pos (25U)\r
+#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */\r
+#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */\r
+#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */\r
+#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */\r
+#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */\r
+#define USART_CR3_RXFTIE_Pos (28U)\r
+#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */\r
+#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */\r
+#define USART_CR3_TXFTCFG_Pos (29U)\r
+#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */\r
+#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */\r
+#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */\r
+#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */\r
+#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION_Pos (0U)\r
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */\r
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA_Pos (4U)\r
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */\r
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC_Pos (0U)\r
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */\r
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT_Pos (8U)\r
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */\r
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */\r
+\r
+/******************* Bit definition for USART_RTOR register *****************/\r
+#define USART_RTOR_RTO_Pos (0U)\r
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */\r
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN_Pos (24U)\r
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */\r
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */\r
+\r
+/******************* Bit definition for USART_RQR register ******************/\r
+#define USART_RQR_ABRRQ_Pos (0U)\r
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */\r
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ_Pos (1U)\r
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */\r
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */\r
+#define USART_RQR_MMRQ_Pos (2U)\r
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */\r
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ_Pos (3U)\r
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */\r
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ_Pos (4U)\r
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */\r
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */\r
+\r
+/******************* Bit definition for USART_ISR register ******************/\r
+#define USART_ISR_PE_Pos (0U)\r
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */\r
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */\r
+#define USART_ISR_FE_Pos (1U)\r
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */\r
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */\r
+#define USART_ISR_NE_Pos (2U)\r
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */\r
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */\r
+#define USART_ISR_ORE_Pos (3U)\r
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */\r
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */\r
+#define USART_ISR_IDLE_Pos (4U)\r
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */\r
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */\r
+#define USART_ISR_RXNE_RXFNE_Pos (5U)\r
+#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */\r
+#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */\r
+#define USART_ISR_TC_Pos (6U)\r
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */\r
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */\r
+#define USART_ISR_TXE_TXFNF_Pos (7U)\r
+#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */\r
+#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */\r
+#define USART_ISR_LBDF_Pos (8U)\r
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */\r
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF_Pos (9U)\r
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */\r
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS_Pos (10U)\r
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */\r
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */\r
+#define USART_ISR_RTOF_Pos (11U)\r
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */\r
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF_Pos (12U)\r
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */\r
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */\r
+#define USART_ISR_UDR_Pos (13U)\r
+#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */\r
+#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */\r
+#define USART_ISR_ABRE_Pos (14U)\r
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */\r
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF_Pos (15U)\r
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */\r
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY_Pos (16U)\r
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */\r
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */\r
+#define USART_ISR_CMF_Pos (17U)\r
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */\r
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */\r
+#define USART_ISR_SBKF_Pos (18U)\r
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */\r
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */\r
+#define USART_ISR_RWU_Pos (19U)\r
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */\r
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_WUF_Pos (20U)\r
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */\r
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */\r
+#define USART_ISR_TEACK_Pos (21U)\r
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */\r
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */\r
+#define USART_ISR_REACK_Pos (22U)\r
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */\r
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */\r
+#define USART_ISR_TXFE_Pos (23U)\r
+#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */\r
+#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */\r
+#define USART_ISR_RXFF_Pos (24U)\r
+#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */\r
+#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */\r
+#define USART_ISR_TCBGT_Pos (25U)\r
+#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */\r
+#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */\r
+#define USART_ISR_RXFT_Pos (26U)\r
+#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */\r
+#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */\r
+#define USART_ISR_TXFT_Pos (27U)\r
+#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */\r
+#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */\r
+\r
+/******************* Bit definition for USART_ICR register ******************/\r
+#define USART_ICR_PECF_Pos (0U)\r
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */\r
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF_Pos (1U)\r
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */\r
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NECF_Pos (2U)\r
+#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */\r
+#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */\r
+#define USART_ICR_ORECF_Pos (3U)\r
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */\r
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF_Pos (4U)\r
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */\r
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TXFECF_Pos (5U)\r
+#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */\r
+#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */\r
+#define USART_ICR_TCCF_Pos (6U)\r
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */\r
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_TCBGTCF_Pos (7U)\r
+#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */\r
+#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */\r
+#define USART_ICR_LBDCF_Pos (8U)\r
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */\r
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF_Pos (9U)\r
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */\r
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF_Pos (11U)\r
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */\r
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF_Pos (12U)\r
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */\r
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */\r
+#define USART_ICR_UDRCF_Pos (13U)\r
+#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */\r
+#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */\r
+#define USART_ICR_CMCF_Pos (17U)\r
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */\r
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */\r
+#define USART_ICR_WUCF_Pos (20U)\r
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */\r
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */\r
+\r
+/******************* Bit definition for USART_RDR register ******************/\r
+#define USART_RDR_RDR_Pos (0U)\r
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */\r
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/******************* Bit definition for USART_TDR register ******************/\r
+#define USART_TDR_TDR_Pos (0U)\r
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */\r
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************* Bit definition for USART_PRESC register ******************/\r
+#define USART_PRESC_PRESCALER_Pos (0U)\r
+#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */\r
+#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */\r
+#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */\r
+#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */\r
+#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */\r
+#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Single Wire Protocol Master Interface (SWPMI) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for SWPMI_CR register ********************/\r
+#define SWPMI_CR_RXDMA_Pos (0U)\r
+#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */\r
+#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */\r
+#define SWPMI_CR_TXDMA_Pos (1U)\r
+#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */\r
+#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */\r
+#define SWPMI_CR_RXMODE_Pos (2U)\r
+#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */\r
+#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */\r
+#define SWPMI_CR_TXMODE_Pos (3U)\r
+#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */\r
+#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */\r
+#define SWPMI_CR_LPBK_Pos (4U)\r
+#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */\r
+#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */\r
+#define SWPMI_CR_SWPACT_Pos (5U)\r
+#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */\r
+#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */\r
+#define SWPMI_CR_DEACT_Pos (10U)\r
+#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */\r
+#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */\r
+#define SWPMI_CR_SWPEN_Pos (11U)\r
+#define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */\r
+#define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */\r
+\r
+/******************* Bit definition for SWPMI_BRR register ********************/\r
+#define SWPMI_BRR_BR_Pos (0U)\r
+#define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */\r
+#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */\r
+\r
+/******************* Bit definition for SWPMI_ISR register ********************/\r
+#define SWPMI_ISR_RXBFF_Pos (0U)\r
+#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */\r
+#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */\r
+#define SWPMI_ISR_TXBEF_Pos (1U)\r
+#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */\r
+#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */\r
+#define SWPMI_ISR_RXBERF_Pos (2U)\r
+#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */\r
+#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */\r
+#define SWPMI_ISR_RXOVRF_Pos (3U)\r
+#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */\r
+#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */\r
+#define SWPMI_ISR_TXUNRF_Pos (4U)\r
+#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */\r
+#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */\r
+#define SWPMI_ISR_RXNE_Pos (5U)\r
+#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */\r
+#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */\r
+#define SWPMI_ISR_TXE_Pos (6U)\r
+#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */\r
+#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */\r
+#define SWPMI_ISR_TCF_Pos (7U)\r
+#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */\r
+#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */\r
+#define SWPMI_ISR_SRF_Pos (8U)\r
+#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */\r
+#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */\r
+#define SWPMI_ISR_SUSP_Pos (9U)\r
+#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */\r
+#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */\r
+#define SWPMI_ISR_DEACTF_Pos (10U)\r
+#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */\r
+#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */\r
+#define SWPMI_ISR_RDYF_Pos (11U)\r
+#define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */\r
+#define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */\r
+\r
+/******************* Bit definition for SWPMI_ICR register ********************/\r
+#define SWPMI_ICR_CRXBFF_Pos (0U)\r
+#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */\r
+#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */\r
+#define SWPMI_ICR_CTXBEF_Pos (1U)\r
+#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */\r
+#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */\r
+#define SWPMI_ICR_CRXBERF_Pos (2U)\r
+#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */\r
+#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */\r
+#define SWPMI_ICR_CRXOVRF_Pos (3U)\r
+#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */\r
+#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */\r
+#define SWPMI_ICR_CTXUNRF_Pos (4U)\r
+#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */\r
+#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */\r
+#define SWPMI_ICR_CTCF_Pos (7U)\r
+#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */\r
+#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */\r
+#define SWPMI_ICR_CSRF_Pos (8U)\r
+#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */\r
+#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */\r
+#define SWPMI_ICR_CRDYF_Pos (11U)\r
+#define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */\r
+#define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */\r
+\r
+/******************* Bit definition for SWPMI_IER register ********************/\r
+#define SWPMI_IER_RXBFIE_Pos (0U)\r
+#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */\r
+#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */\r
+#define SWPMI_IER_TXBEIE_Pos (1U)\r
+#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */\r
+#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */\r
+#define SWPMI_IER_RXBERIE_Pos (2U)\r
+#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */\r
+#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */\r
+#define SWPMI_IER_RXOVRIE_Pos (3U)\r
+#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */\r
+#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */\r
+#define SWPMI_IER_TXUNRIE_Pos (4U)\r
+#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */\r
+#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */\r
+#define SWPMI_IER_RIE_Pos (5U)\r
+#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */\r
+#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */\r
+#define SWPMI_IER_TIE_Pos (6U)\r
+#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */\r
+#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */\r
+#define SWPMI_IER_TCIE_Pos (7U)\r
+#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */\r
+#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */\r
+#define SWPMI_IER_SRIE_Pos (8U)\r
+#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */\r
+#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */\r
+#define SWPMI_IER_RDYIE_Pos (11U)\r
+#define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */\r
+#define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */\r
+\r
+/******************* Bit definition for SWPMI_RFL register ********************/\r
+#define SWPMI_RFL_RFL_Pos (0U)\r
+#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */\r
+#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */\r
+#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */\r
+\r
+/******************* Bit definition for SWPMI_TDR register ********************/\r
+#define SWPMI_TDR_TD_Pos (0U)\r
+#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */\r
+#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */\r
+\r
+/******************* Bit definition for SWPMI_RDR register ********************/\r
+#define SWPMI_RDR_RD_Pos (0U)\r
+#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */\r
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */\r
+\r
+\r
+/******************* Bit definition for SWPMI_OR register ********************/\r
+#define SWPMI_OR_TBYP_Pos (0U)\r
+#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */\r
+#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */\r
+#define SWPMI_OR_CLASS_Pos (1U)\r
+#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */\r
+#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T_Pos (0U)\r
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */\r
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */\r
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */\r
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */\r
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */\r
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */\r
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */\r
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */\r
+\r
+#define WWDG_CR_WDGA_Pos (7U)\r
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */\r
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W_Pos (0U)\r
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */\r
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */\r
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */\r
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */\r
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */\r
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */\r
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */\r
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */\r
+\r
+#define WWDG_CFR_EWI_Pos (9U)\r
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */\r
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */\r
+\r
+#define WWDG_CFR_WDGTB_Pos (11U)\r
+#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */\r
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */\r
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */\r
+#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF_Pos (0U)\r
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */\r
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)\r
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk\r
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)\r
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk\r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)\r
+#define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk\r
+#define DBGMCU_CR_DBG_STOPD1_Pos (1U)\r
+#define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk\r
+#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)\r
+#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk\r
+#define DBGMCU_CR_DBG_SLEEPD2_Pos (3U)\r
+#define DBGMCU_CR_DBG_SLEEPD2_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_CR_DBG_SLEEPD2 DBGMCU_CR_DBG_SLEEPD2_Msk\r
+#define DBGMCU_CR_DBG_STOPD2_Pos (4U)\r
+#define DBGMCU_CR_DBG_STOPD2_Msk (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_CR_DBG_STOPD2 DBGMCU_CR_DBG_STOPD2_Msk\r
+#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)\r
+#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk\r
+#define DBGMCU_CR_DBG_STOPD3_Pos (7U)\r
+#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */\r
+#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk\r
+#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)\r
+#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */\r
+#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk\r
+#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)\r
+#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */\r
+#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk\r
+#define DBGMCU_CR_DBG_CKD1EN_Pos (21U)\r
+#define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk\r
+#define DBGMCU_CR_DBG_CKD3EN_Pos (22U)\r
+#define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk\r
+#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)\r
+#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */\r
+#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk\r
+\r
+/******************** Bit definition for APB3FZ1 register ************/\r
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)\r
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk\r
+/******************** Bit definition for APB3FZ2 register ************/\r
+#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos (6U)\r
+#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_APB3FZ2_DBG_WWDG1 DBGMCU_APB3FZ2_DBG_WWDG1_Msk\r
+/******************** Bit definition for APB1LFZ1 register ************/\r
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)\r
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */\r
+#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)\r
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */\r
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos (11U)\r
+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB1LFZ1_DBG_WWDG2 DBGMCU_APB1LFZ1_DBG_WWDG2_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)\r
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)\r
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk\r
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)\r
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */\r
+#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk\r
+\r
+/******************** Bit definition for APB1LFZ2 register ************/\r
+#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos (0U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM2 DBGMCU_APB1LFZ2_DBG_TIM2_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos (1U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM3 DBGMCU_APB1LFZ2_DBG_TIM3_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos (2U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM4 DBGMCU_APB1LFZ2_DBG_TIM4_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos (3U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM5 DBGMCU_APB1LFZ2_DBG_TIM5_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos (4U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM6 DBGMCU_APB1LFZ2_DBG_TIM6_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos (5U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM7 DBGMCU_APB1LFZ2_DBG_TIM7_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos (6U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM12 DBGMCU_APB1LFZ2_DBG_TIM12_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos (7U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM13 DBGMCU_APB1LFZ2_DBG_TIM13_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos (8U)\r
+#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */\r
+#define DBGMCU_APB1LFZ2_DBG_TIM14 DBGMCU_APB1LFZ2_DBG_TIM14_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos (9U)\r
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */\r
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1 DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos (11U)\r
+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB1LFZ2_DBG_WWDG2 DBGMCU_APB1LFZ2_DBG_WWDG2_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos (21U)\r
+#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_APB1LFZ2_DBG_I2C1 DBGMCU_APB1LFZ2_DBG_I2C1_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos (22U)\r
+#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_APB1LFZ2_DBG_I2C2 DBGMCU_APB1LFZ2_DBG_I2C2_Msk\r
+#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos (23U)\r
+#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */\r
+#define DBGMCU_APB1LFZ2_DBG_I2C3 DBGMCU_APB1LFZ2_DBG_I2C3_Msk\r
+/******************** Bit definition for APB1HFZ1 register ************/\r
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)\r
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */\r
+#define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk\r
+/******************** Bit definition for APB1HFZ2 register ************/\r
+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos (8U)\r
+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */\r
+#define DBGMCU_APB1HFZ2_DBG_FDCAN DBGMCU_APB1HFZ2_DBG_FDCAN_Msk\r
+\r
+/******************** Bit definition for APB2FZ1 register ************/\r
+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)\r
+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk\r
+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)\r
+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk\r
+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)\r
+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk\r
+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)\r
+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */\r
+#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk\r
+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)\r
+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk\r
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)\r
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */\r
+#define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk\r
+\r
+/******************** Bit definition for APB2FZ2 register ************/\r
+#define DBGMCU_APB2FZ2_DBG_TIM1_Pos (0U)\r
+#define DBGMCU_APB2FZ2_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB2FZ2_DBG_TIM1 DBGMCU_APB2FZ2_DBG_TIM1_Msk\r
+#define DBGMCU_APB2FZ2_DBG_TIM8_Pos (1U)\r
+#define DBGMCU_APB2FZ2_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB2FZ2_DBG_TIM8 DBGMCU_APB2FZ2_DBG_TIM8_Msk\r
+#define DBGMCU_APB2FZ2_DBG_TIM15_Pos (16U)\r
+#define DBGMCU_APB2FZ2_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_APB2FZ2_DBG_TIM15 DBGMCU_APB2FZ2_DBG_TIM15_Msk\r
+#define DBGMCU_APB2FZ2_DBG_TIM16_Pos (17U)\r
+#define DBGMCU_APB2FZ2_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */\r
+#define DBGMCU_APB2FZ2_DBG_TIM16 DBGMCU_APB2FZ2_DBG_TIM16_Msk\r
+#define DBGMCU_APB2FZ2_DBG_TIM17_Pos (18U)\r
+#define DBGMCU_APB2FZ2_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_APB2FZ2_DBG_TIM17 DBGMCU_APB2FZ2_DBG_TIM17_Msk\r
+#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos (29U)\r
+#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */\r
+#define DBGMCU_APB2FZ2_DBG_HRTIM DBGMCU_APB2FZ2_DBG_HRTIM_Msk\r
+/******************** Bit definition for APB4FZ1 register ************/\r
+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)\r
+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */\r
+#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */\r
+#define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk\r
+#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)\r
+#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk\r
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)\r
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk\r
+#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos (19U)\r
+#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */\r
+#define DBGMCU_APB4FZ1_DBG_IWDG2 DBGMCU_APB4FZ1_DBG_IWDG2_Msk\r
+/******************** Bit definition for APB4FZ2 register ************/\r
+#define DBGMCU_APB4FZ2_DBG_I2C4_Pos (7U)\r
+#define DBGMCU_APB4FZ2_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */\r
+#define DBGMCU_APB4FZ2_DBG_I2C4 DBGMCU_APB4FZ2_DBG_I2C4_Msk\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos (9U)\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM2 DBGMCU_APB4FZ2_DBG_LPTIM2_Msk\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos (10U)\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM3 DBGMCU_APB4FZ2_DBG_LPTIM3_Msk\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos (11U)\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM4 DBGMCU_APB4FZ2_DBG_LPTIM4_Msk\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos (12U)\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */\r
+#define DBGMCU_APB4FZ2_DBG_LPTIM5 DBGMCU_APB4FZ2_DBG_LPTIM5_Msk\r
+#define DBGMCU_APB4FZ2_DBG_RTC_Pos (16U)\r
+#define DBGMCU_APB4FZ2_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_APB4FZ2_DBG_RTC DBGMCU_APB4FZ2_DBG_RTC_Msk\r
+#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos (18U)\r
+#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_APB4FZ2_DBG_IWDG1 DBGMCU_APB4FZ2_DBG_IWDG1_Msk\r
+#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos (19U)\r
+#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */\r
+#define DBGMCU_APB4FZ2_DBG_IWDG2 DBGMCU_APB4FZ2_DBG_IWDG2_Msk\r
+/******************************************************************************/\r
+/* */\r
+/* High Resolution Timer (HRTIM) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Master Timer control register ***************************/\r
+#define HRTIM_MCR_CK_PSC_Pos (0U)\r
+#define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */\r
+#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */\r
+#define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */\r
+#define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */\r
+\r
+#define HRTIM_MCR_CONT_Pos (3U)\r
+#define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */\r
+#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */\r
+#define HRTIM_MCR_RETRIG_Pos (4U)\r
+#define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */\r
+#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */\r
+#define HRTIM_MCR_HALF_Pos (5U)\r
+#define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */\r
+#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */\r
+\r
+#define HRTIM_MCR_SYNC_IN_Pos (8U)\r
+#define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */\r
+#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */\r
+#define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */\r
+#define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */\r
+#define HRTIM_MCR_SYNCRSTM_Pos (10U)\r
+#define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */\r
+#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */\r
+#define HRTIM_MCR_SYNCSTRTM_Pos (11U)\r
+#define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */\r
+#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */\r
+#define HRTIM_MCR_SYNC_OUT_Pos (12U)\r
+#define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */\r
+#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */\r
+#define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */\r
+#define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */\r
+#define HRTIM_MCR_SYNC_SRC_Pos (14U)\r
+#define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */\r
+#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */\r
+#define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */\r
+#define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */\r
+\r
+#define HRTIM_MCR_MCEN_Pos (16U)\r
+#define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */\r
+#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */\r
+#define HRTIM_MCR_TACEN_Pos (17U)\r
+#define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */\r
+#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */\r
+#define HRTIM_MCR_TBCEN_Pos (18U)\r
+#define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */\r
+#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */\r
+#define HRTIM_MCR_TCCEN_Pos (19U)\r
+#define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */\r
+#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */\r
+#define HRTIM_MCR_TDCEN_Pos (20U)\r
+#define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */\r
+#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */\r
+#define HRTIM_MCR_TECEN_Pos (21U)\r
+#define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */\r
+#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */\r
+\r
+#define HRTIM_MCR_DACSYNC_Pos (25U)\r
+#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */\r
+#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */\r
+#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */\r
+#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */\r
+\r
+#define HRTIM_MCR_PREEN_Pos (27U)\r
+#define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */\r
+#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */\r
+#define HRTIM_MCR_MREPU_Pos (29U)\r
+#define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */\r
+#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */\r
+\r
+#define HRTIM_MCR_BRSTDMA_Pos (30U)\r
+#define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */\r
+#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */\r
+#define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */\r
+#define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Master Timer Interrupt status register ******************/\r
+#define HRTIM_MISR_MCMP1_Pos (0U)\r
+#define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */\r
+#define HRTIM_MISR_MCMP2_Pos (1U)\r
+#define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */\r
+#define HRTIM_MISR_MCMP3_Pos (2U)\r
+#define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */\r
+#define HRTIM_MISR_MCMP4_Pos (3U)\r
+#define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */\r
+#define HRTIM_MISR_MREP_Pos (4U)\r
+#define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */\r
+#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */\r
+#define HRTIM_MISR_SYNC_Pos (5U)\r
+#define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */\r
+#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */\r
+#define HRTIM_MISR_MUPD_Pos (6U)\r
+#define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */\r
+#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */\r
+\r
+/******************** Master Timer Interrupt clear register *******************/\r
+#define HRTIM_MICR_MCMP1_Pos (0U)\r
+#define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */\r
+#define HRTIM_MICR_MCMP2_Pos (1U)\r
+#define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */\r
+#define HRTIM_MICR_MCMP3_Pos (2U)\r
+#define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */\r
+#define HRTIM_MICR_MCMP4_Pos (3U)\r
+#define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */\r
+#define HRTIM_MICR_MREP_Pos (4U)\r
+#define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */\r
+#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */\r
+#define HRTIM_MICR_SYNC_Pos (5U)\r
+#define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */\r
+#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */\r
+#define HRTIM_MICR_MUPD_Pos (6U)\r
+#define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */\r
+#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */\r
+\r
+/******************** Master Timer DMA/Interrupt enable register **************/\r
+#define HRTIM_MDIER_MCMP1IE_Pos (0U)\r
+#define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */\r
+#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */\r
+#define HRTIM_MDIER_MCMP2IE_Pos (1U)\r
+#define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */\r
+#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */\r
+#define HRTIM_MDIER_MCMP3IE_Pos (2U)\r
+#define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */\r
+#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */\r
+#define HRTIM_MDIER_MCMP4IE_Pos (3U)\r
+#define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */\r
+#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */\r
+#define HRTIM_MDIER_MREPIE_Pos (4U)\r
+#define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */\r
+#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */\r
+#define HRTIM_MDIER_SYNCIE_Pos (5U)\r
+#define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */\r
+#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */\r
+#define HRTIM_MDIER_MUPDIE_Pos (6U)\r
+#define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */\r
+#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */\r
+\r
+#define HRTIM_MDIER_MCMP1DE_Pos (16U)\r
+#define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */\r
+#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */\r
+#define HRTIM_MDIER_MCMP2DE_Pos (17U)\r
+#define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */\r
+#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */\r
+#define HRTIM_MDIER_MCMP3DE_Pos (18U)\r
+#define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */\r
+#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */\r
+#define HRTIM_MDIER_MCMP4DE_Pos (19U)\r
+#define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */\r
+#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */\r
+#define HRTIM_MDIER_MREPDE_Pos (20U)\r
+#define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */\r
+#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */\r
+#define HRTIM_MDIER_SYNCDE_Pos (21U)\r
+#define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */\r
+#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */\r
+#define HRTIM_MDIER_MUPDDE_Pos (22U)\r
+#define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */\r
+#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */\r
+\r
+/******************* Bit definition for HRTIM_MCNTR register ****************/\r
+#define HRTIM_MCNTR_MCNTR_Pos (0U)\r
+#define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */\r
+\r
+/******************* Bit definition for HRTIM_MPER register *****************/\r
+#define HRTIM_MPER_MPER_Pos (0U)\r
+#define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */\r
+\r
+/******************* Bit definition for HRTIM_MREP register *****************/\r
+#define HRTIM_MREP_MREP_Pos (0U)\r
+#define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */\r
+#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */\r
+\r
+/******************* Bit definition for HRTIM_MCMP1R register *****************/\r
+#define HRTIM_MCMP1R_MCMP1R_Pos (0U)\r
+#define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_MCMP2R register *****************/\r
+#define HRTIM_MCMP1R_MCMP2R_Pos (0U)\r
+#define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk /*!<Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_MCMP3R register *****************/\r
+#define HRTIM_MCMP1R_MCMP3R_Pos (0U)\r
+#define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk /*!<Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_MCMP4R register *****************/\r
+#define HRTIM_MCMP1R_MCMP4R_Pos (0U)\r
+#define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk /*!<Compare Value */\r
+\r
+/******************** Slave control register **********************************/\r
+#define HRTIM_TIMCR_CK_PSC_Pos (0U)\r
+#define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */\r
+#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/\r
+#define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */\r
+#define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */\r
+\r
+#define HRTIM_TIMCR_CONT_Pos (3U)\r
+#define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */\r
+#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */\r
+#define HRTIM_TIMCR_RETRIG_Pos (4U)\r
+#define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */\r
+#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */\r
+#define HRTIM_TIMCR_HALF_Pos (5U)\r
+#define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */\r
+#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */\r
+#define HRTIM_TIMCR_PSHPLL_Pos (6U)\r
+#define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */\r
+#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */\r
+\r
+#define HRTIM_TIMCR_SYNCRST_Pos (10U)\r
+#define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */\r
+#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */\r
+#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)\r
+#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */\r
+#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */\r
+\r
+#define HRTIM_TIMCR_DELCMP2_Pos (12U)\r
+#define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */\r
+#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */\r
+#define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */\r
+#define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */\r
+#define HRTIM_TIMCR_DELCMP4_Pos (14U)\r
+#define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */\r
+#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */\r
+#define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */\r
+#define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */\r
+\r
+#define HRTIM_TIMCR_TREPU_Pos (17U)\r
+#define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */\r
+#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */\r
+#define HRTIM_TIMCR_TRSTU_Pos (18U)\r
+#define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */\r
+#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */\r
+#define HRTIM_TIMCR_TAU_Pos (19U)\r
+#define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */\r
+#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */\r
+#define HRTIM_TIMCR_TBU_Pos (20U)\r
+#define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */\r
+#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */\r
+#define HRTIM_TIMCR_TCU_Pos (21U)\r
+#define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */\r
+#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */\r
+#define HRTIM_TIMCR_TDU_Pos (22U)\r
+#define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */\r
+#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */\r
+#define HRTIM_TIMCR_TEU_Pos (23U)\r
+#define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */\r
+#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */\r
+#define HRTIM_TIMCR_MSTU_Pos (24U)\r
+#define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */\r
+#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */\r
+\r
+#define HRTIM_TIMCR_DACSYNC_Pos (25U)\r
+#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */\r
+#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */\r
+#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */\r
+#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */\r
+#define HRTIM_TIMCR_PREEN_Pos (27U)\r
+#define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */\r
+#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */\r
+\r
+#define HRTIM_TIMCR_UPDGAT_Pos (28U)\r
+#define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */\r
+#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */\r
+#define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */\r
+#define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */\r
+#define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */\r
+#define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Slave Interrupt status register **************************/\r
+#define HRTIM_TIMISR_CMP1_Pos (0U)\r
+#define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */\r
+#define HRTIM_TIMISR_CMP2_Pos (1U)\r
+#define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */\r
+#define HRTIM_TIMISR_CMP3_Pos (2U)\r
+#define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */\r
+#define HRTIM_TIMISR_CMP4_Pos (3U)\r
+#define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */\r
+#define HRTIM_TIMISR_REP_Pos (4U)\r
+#define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */\r
+#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */\r
+#define HRTIM_TIMISR_UPD_Pos (6U)\r
+#define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */\r
+#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */\r
+#define HRTIM_TIMISR_CPT1_Pos (7U)\r
+#define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */\r
+#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */\r
+#define HRTIM_TIMISR_CPT2_Pos (8U)\r
+#define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */\r
+#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */\r
+#define HRTIM_TIMISR_SET1_Pos (9U)\r
+#define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */\r
+#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */\r
+#define HRTIM_TIMISR_RST1_Pos (10U)\r
+#define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */\r
+#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */\r
+#define HRTIM_TIMISR_SET2_Pos (11U)\r
+#define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */\r
+#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */\r
+#define HRTIM_TIMISR_RST2_Pos (12U)\r
+#define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */\r
+#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */\r
+#define HRTIM_TIMISR_RST_Pos (13U)\r
+#define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */\r
+#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */\r
+#define HRTIM_TIMISR_DLYPRT_Pos (14U)\r
+#define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */\r
+#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */\r
+#define HRTIM_TIMISR_CPPSTAT_Pos (16U)\r
+#define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */\r
+#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */\r
+#define HRTIM_TIMISR_IPPSTAT_Pos (17U)\r
+#define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */\r
+#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */\r
+#define HRTIM_TIMISR_O1STAT_Pos (18U)\r
+#define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */\r
+#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */\r
+#define HRTIM_TIMISR_O2STAT_Pos (19U)\r
+#define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */\r
+#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */\r
+#define HRTIM_TIMISR_O1CPY_Pos (20U)\r
+#define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */\r
+#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */\r
+#define HRTIM_TIMISR_O2CPY_Pos (21U)\r
+#define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */\r
+#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */\r
+\r
+/******************** Slave Interrupt clear register **************************/\r
+#define HRTIM_TIMICR_CMP1C_Pos (0U)\r
+#define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */\r
+#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */\r
+#define HRTIM_TIMICR_CMP2C_Pos (1U)\r
+#define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */\r
+#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */\r
+#define HRTIM_TIMICR_CMP3C_Pos (2U)\r
+#define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */\r
+#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */\r
+#define HRTIM_TIMICR_CMP4C_Pos (3U)\r
+#define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */\r
+#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */\r
+#define HRTIM_TIMICR_REPC_Pos (4U)\r
+#define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */\r
+#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */\r
+#define HRTIM_TIMICR_UPDC_Pos (6U)\r
+#define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */\r
+#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */\r
+#define HRTIM_TIMICR_CPT1C_Pos (7U)\r
+#define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */\r
+#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */\r
+#define HRTIM_TIMICR_CPT2C_Pos (8U)\r
+#define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */\r
+#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */\r
+#define HRTIM_TIMICR_SET1C_Pos (9U)\r
+#define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */\r
+#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */\r
+#define HRTIM_TIMICR_RST1C_Pos (10U)\r
+#define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */\r
+#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */\r
+#define HRTIM_TIMICR_SET2C_Pos (11U)\r
+#define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */\r
+#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */\r
+#define HRTIM_TIMICR_RST2C_Pos (12U)\r
+#define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */\r
+#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */\r
+#define HRTIM_TIMICR_RSTC_Pos (13U)\r
+#define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */\r
+#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */\r
+#define HRTIM_TIMICR_DLYPRTC_Pos (14U)\r
+#define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */\r
+#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output 1 delay protection clear flag */\r
+\r
+/******************** Slave DMA/Interrupt enable register *********************/\r
+#define HRTIM_TIMDIER_CMP1IE_Pos (0U)\r
+#define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */\r
+#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */\r
+#define HRTIM_TIMDIER_CMP2IE_Pos (1U)\r
+#define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */\r
+#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */\r
+#define HRTIM_TIMDIER_CMP3IE_Pos (2U)\r
+#define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */\r
+#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */\r
+#define HRTIM_TIMDIER_CMP4IE_Pos (3U)\r
+#define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */\r
+#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */\r
+#define HRTIM_TIMDIER_REPIE_Pos (4U)\r
+#define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */\r
+#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */\r
+#define HRTIM_TIMDIER_UPDIE_Pos (6U)\r
+#define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */\r
+#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */\r
+#define HRTIM_TIMDIER_CPT1IE_Pos (7U)\r
+#define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */\r
+#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */\r
+#define HRTIM_TIMDIER_CPT2IE_Pos (8U)\r
+#define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */\r
+#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */\r
+#define HRTIM_TIMDIER_SET1IE_Pos (9U)\r
+#define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */\r
+#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */\r
+#define HRTIM_TIMDIER_RST1IE_Pos (10U)\r
+#define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */\r
+#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */\r
+#define HRTIM_TIMDIER_SET2IE_Pos (11U)\r
+#define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */\r
+#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */\r
+#define HRTIM_TIMDIER_RST2IE_Pos (12U)\r
+#define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */\r
+#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */\r
+#define HRTIM_TIMDIER_RSTIE_Pos (13U)\r
+#define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */\r
+#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */\r
+#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)\r
+#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */\r
+#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */\r
+\r
+#define HRTIM_TIMDIER_CMP1DE_Pos (16U)\r
+#define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */\r
+#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */\r
+#define HRTIM_TIMDIER_CMP2DE_Pos (17U)\r
+#define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */\r
+#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */\r
+#define HRTIM_TIMDIER_CMP3DE_Pos (18U)\r
+#define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */\r
+#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */\r
+#define HRTIM_TIMDIER_CMP4DE_Pos (19U)\r
+#define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */\r
+#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */\r
+#define HRTIM_TIMDIER_REPDE_Pos (20U)\r
+#define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */\r
+#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */\r
+#define HRTIM_TIMDIER_UPDDE_Pos (22U)\r
+#define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */\r
+#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */\r
+#define HRTIM_TIMDIER_CPT1DE_Pos (23U)\r
+#define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */\r
+#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */\r
+#define HRTIM_TIMDIER_CPT2DE_Pos (24U)\r
+#define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */\r
+#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */\r
+#define HRTIM_TIMDIER_SET1DE_Pos (25U)\r
+#define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */\r
+#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */\r
+#define HRTIM_TIMDIER_RST1DE_Pos (26U)\r
+#define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */\r
+#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */\r
+#define HRTIM_TIMDIER_SET2DE_Pos (27U)\r
+#define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */\r
+#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */\r
+#define HRTIM_TIMDIER_RST2DE_Pos (28U)\r
+#define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */\r
+#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */\r
+#define HRTIM_TIMDIER_RSTDE_Pos (29U)\r
+#define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */\r
+#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */\r
+#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)\r
+#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */\r
+#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */\r
+\r
+/****************** Bit definition for HRTIM_CNTR register ****************/\r
+#define HRTIM_CNTR_CNTR_Pos (0U)\r
+#define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */\r
+\r
+/******************* Bit definition for HRTIM_PER register *****************/\r
+#define HRTIM_PER_PER_Pos (0U)\r
+#define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */\r
+\r
+/******************* Bit definition for HRTIM_REP register *****************/\r
+#define HRTIM_REP_REP_Pos (0U)\r
+#define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */\r
+#define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */\r
+\r
+/******************* Bit definition for HRTIM_CMP1R register *****************/\r
+#define HRTIM_CMP1R_CMP1R_Pos (0U)\r
+#define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_CMP1CR register *****************/\r
+#define HRTIM_CMP1CR_CMP1CR_Pos (0U)\r
+#define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */\r
+#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_CMP2R register *****************/\r
+#define HRTIM_CMP2R_CMP2R_Pos (0U)\r
+#define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_CMP3R register *****************/\r
+#define HRTIM_CMP3R_CMP3R_Pos (0U)\r
+#define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_CMP4R register *****************/\r
+#define HRTIM_CMP4R_CMP4R_Pos (0U)\r
+#define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_CPT1R register ****************/\r
+#define HRTIM_CPT1R_CPT1R_Pos (0U)\r
+#define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */\r
+\r
+/******************* Bit definition for HRTIM_CPT2R register ****************/\r
+#define HRTIM_CPT2R_CPT2R_Pos (0U)\r
+#define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */\r
+\r
+/******************** Bit definition for Slave Deadtime register **************/\r
+#define HRTIM_DTR_DTR_Pos (0U)\r
+#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */\r
+#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */\r
+#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */\r
+#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */\r
+#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */\r
+#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */\r
+#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */\r
+#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */\r
+#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */\r
+#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */\r
+#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */\r
+#define HRTIM_DTR_SDTR_Pos (9U)\r
+#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */\r
+#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */\r
+#define HRTIM_DTR_DTPRSC_Pos (10U)\r
+#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */\r
+#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */\r
+#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */\r
+#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */\r
+#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */\r
+#define HRTIM_DTR_DTRSLK_Pos (14U)\r
+#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */\r
+#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */\r
+#define HRTIM_DTR_DTRLK_Pos (15U)\r
+#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */\r
+#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */\r
+#define HRTIM_DTR_DTF_Pos (16U)\r
+#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */\r
+#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */\r
+#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */\r
+#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */\r
+#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */\r
+#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */\r
+#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */\r
+#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */\r
+#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */\r
+#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */\r
+#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */\r
+#define HRTIM_DTR_SDTF_Pos (25U)\r
+#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */\r
+#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */\r
+#define HRTIM_DTR_DTFSLK_Pos (30U)\r
+#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */\r
+#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */\r
+#define HRTIM_DTR_DTFLK_Pos (31U)\r
+#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */\r
+#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */\r
+\r
+/**** Bit definition for Slave Output 1 set register **************************/\r
+#define HRTIM_SET1R_SST_Pos (0U)\r
+#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */\r
+#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */\r
+#define HRTIM_SET1R_RESYNC_Pos (1U)\r
+#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */\r
+#define HRTIM_SET1R_PER_Pos (2U)\r
+#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */\r
+#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */\r
+#define HRTIM_SET1R_CMP1_Pos (3U)\r
+#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */\r
+#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */\r
+#define HRTIM_SET1R_CMP2_Pos (4U)\r
+#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */\r
+#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */\r
+#define HRTIM_SET1R_CMP3_Pos (5U)\r
+#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */\r
+#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */\r
+#define HRTIM_SET1R_CMP4_Pos (6U)\r
+#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */\r
+#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */\r
+\r
+#define HRTIM_SET1R_MSTPER_Pos (7U)\r
+#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */\r
+#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */\r
+#define HRTIM_SET1R_MSTCMP1_Pos (8U)\r
+#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */\r
+#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */\r
+#define HRTIM_SET1R_MSTCMP2_Pos (9U)\r
+#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */\r
+#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */\r
+#define HRTIM_SET1R_MSTCMP3_Pos (10U)\r
+#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */\r
+#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */\r
+#define HRTIM_SET1R_MSTCMP4_Pos (11U)\r
+#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */\r
+#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */\r
+\r
+#define HRTIM_SET1R_TIMEVNT1_Pos (12U)\r
+#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */\r
+#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */\r
+#define HRTIM_SET1R_TIMEVNT2_Pos (13U)\r
+#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */\r
+#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */\r
+#define HRTIM_SET1R_TIMEVNT3_Pos (14U)\r
+#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */\r
+#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */\r
+#define HRTIM_SET1R_TIMEVNT4_Pos (15U)\r
+#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */\r
+#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */\r
+#define HRTIM_SET1R_TIMEVNT5_Pos (16U)\r
+#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */\r
+#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */\r
+#define HRTIM_SET1R_TIMEVNT6_Pos (17U)\r
+#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */\r
+#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */\r
+#define HRTIM_SET1R_TIMEVNT7_Pos (18U)\r
+#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */\r
+#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */\r
+#define HRTIM_SET1R_TIMEVNT8_Pos (19U)\r
+#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */\r
+#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */\r
+#define HRTIM_SET1R_TIMEVNT9_Pos (20U)\r
+#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */\r
+#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */\r
+\r
+#define HRTIM_SET1R_EXTVNT1_Pos (21U)\r
+#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */\r
+#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */\r
+#define HRTIM_SET1R_EXTVNT2_Pos (22U)\r
+#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */\r
+#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */\r
+#define HRTIM_SET1R_EXTVNT3_Pos (23U)\r
+#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */\r
+#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */\r
+#define HRTIM_SET1R_EXTVNT4_Pos (24U)\r
+#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */\r
+#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */\r
+#define HRTIM_SET1R_EXTVNT5_Pos (25U)\r
+#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */\r
+#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */\r
+#define HRTIM_SET1R_EXTVNT6_Pos (26U)\r
+#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */\r
+#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */\r
+#define HRTIM_SET1R_EXTVNT7_Pos (27U)\r
+#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */\r
+#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */\r
+#define HRTIM_SET1R_EXTVNT8_Pos (28U)\r
+#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */\r
+#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */\r
+#define HRTIM_SET1R_EXTVNT9_Pos (29U)\r
+#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */\r
+#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */\r
+#define HRTIM_SET1R_EXTVNT10_Pos (30U)\r
+#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */\r
+#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */\r
+\r
+#define HRTIM_SET1R_UPDATE_Pos (31U)\r
+#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */\r
+#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */\r
+\r
+/**** Bit definition for Slave Output 1 reset register ************************/\r
+#define HRTIM_RST1R_SRT_Pos (0U)\r
+#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */\r
+#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */\r
+#define HRTIM_RST1R_RESYNC_Pos (1U)\r
+#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */\r
+#define HRTIM_RST1R_PER_Pos (2U)\r
+#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */\r
+#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */\r
+#define HRTIM_RST1R_CMP1_Pos (3U)\r
+#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */\r
+#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */\r
+#define HRTIM_RST1R_CMP2_Pos (4U)\r
+#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */\r
+#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */\r
+#define HRTIM_RST1R_CMP3_Pos (5U)\r
+#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */\r
+#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */\r
+#define HRTIM_RST1R_CMP4_Pos (6U)\r
+#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */\r
+#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */\r
+\r
+#define HRTIM_RST1R_MSTPER_Pos (7U)\r
+#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */\r
+#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */\r
+#define HRTIM_RST1R_MSTCMP1_Pos (8U)\r
+#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */\r
+#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */\r
+#define HRTIM_RST1R_MSTCMP2_Pos (9U)\r
+#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */\r
+#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */\r
+#define HRTIM_RST1R_MSTCMP3_Pos (10U)\r
+#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */\r
+#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */\r
+#define HRTIM_RST1R_MSTCMP4_Pos (11U)\r
+#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */\r
+#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */\r
+\r
+#define HRTIM_RST1R_TIMEVNT1_Pos (12U)\r
+#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */\r
+#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */\r
+#define HRTIM_RST1R_TIMEVNT2_Pos (13U)\r
+#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */\r
+#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */\r
+#define HRTIM_RST1R_TIMEVNT3_Pos (14U)\r
+#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */\r
+#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */\r
+#define HRTIM_RST1R_TIMEVNT4_Pos (15U)\r
+#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */\r
+#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */\r
+#define HRTIM_RST1R_TIMEVNT5_Pos (16U)\r
+#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */\r
+#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */\r
+#define HRTIM_RST1R_TIMEVNT6_Pos (17U)\r
+#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */\r
+#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */\r
+#define HRTIM_RST1R_TIMEVNT7_Pos (18U)\r
+#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */\r
+#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */\r
+#define HRTIM_RST1R_TIMEVNT8_Pos (19U)\r
+#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */\r
+#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */\r
+#define HRTIM_RST1R_TIMEVNT9_Pos (20U)\r
+#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */\r
+#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */\r
+\r
+#define HRTIM_RST1R_EXTVNT1_Pos (21U)\r
+#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */\r
+#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */\r
+#define HRTIM_RST1R_EXTVNT2_Pos (22U)\r
+#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */\r
+#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */\r
+#define HRTIM_RST1R_EXTVNT3_Pos (23U)\r
+#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */\r
+#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */\r
+#define HRTIM_RST1R_EXTVNT4_Pos (24U)\r
+#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */\r
+#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */\r
+#define HRTIM_RST1R_EXTVNT5_Pos (25U)\r
+#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */\r
+#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */\r
+#define HRTIM_RST1R_EXTVNT6_Pos (26U)\r
+#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */\r
+#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */\r
+#define HRTIM_RST1R_EXTVNT7_Pos (27U)\r
+#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */\r
+#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */\r
+#define HRTIM_RST1R_EXTVNT8_Pos (28U)\r
+#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */\r
+#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */\r
+#define HRTIM_RST1R_EXTVNT9_Pos (29U)\r
+#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */\r
+#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */\r
+#define HRTIM_RST1R_EXTVNT10_Pos (30U)\r
+#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */\r
+#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */\r
+\r
+#define HRTIM_RST1R_UPDATE_Pos (31U)\r
+#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */\r
+#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */\r
+\r
+\r
+/**** Bit definition for Slave Output 2 set register **************************/\r
+#define HRTIM_SET2R_SST_Pos (0U)\r
+#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */\r
+#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */\r
+#define HRTIM_SET2R_RESYNC_Pos (1U)\r
+#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */\r
+#define HRTIM_SET2R_PER_Pos (2U)\r
+#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */\r
+#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */\r
+#define HRTIM_SET2R_CMP1_Pos (3U)\r
+#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */\r
+#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */\r
+#define HRTIM_SET2R_CMP2_Pos (4U)\r
+#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */\r
+#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */\r
+#define HRTIM_SET2R_CMP3_Pos (5U)\r
+#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */\r
+#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */\r
+#define HRTIM_SET2R_CMP4_Pos (6U)\r
+#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */\r
+#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */\r
+\r
+#define HRTIM_SET2R_MSTPER_Pos (7U)\r
+#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */\r
+#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */\r
+#define HRTIM_SET2R_MSTCMP1_Pos (8U)\r
+#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */\r
+#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */\r
+#define HRTIM_SET2R_MSTCMP2_Pos (9U)\r
+#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */\r
+#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */\r
+#define HRTIM_SET2R_MSTCMP3_Pos (10U)\r
+#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */\r
+#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */\r
+#define HRTIM_SET2R_MSTCMP4_Pos (11U)\r
+#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */\r
+#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */\r
+\r
+#define HRTIM_SET2R_TIMEVNT1_Pos (12U)\r
+#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */\r
+#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */\r
+#define HRTIM_SET2R_TIMEVNT2_Pos (13U)\r
+#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */\r
+#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */\r
+#define HRTIM_SET2R_TIMEVNT3_Pos (14U)\r
+#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */\r
+#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */\r
+#define HRTIM_SET2R_TIMEVNT4_Pos (15U)\r
+#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */\r
+#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */\r
+#define HRTIM_SET2R_TIMEVNT5_Pos (16U)\r
+#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */\r
+#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */\r
+#define HRTIM_SET2R_TIMEVNT6_Pos (17U)\r
+#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */\r
+#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */\r
+#define HRTIM_SET2R_TIMEVNT7_Pos (18U)\r
+#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */\r
+#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */\r
+#define HRTIM_SET2R_TIMEVNT8_Pos (19U)\r
+#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */\r
+#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */\r
+#define HRTIM_SET2R_TIMEVNT9_Pos (20U)\r
+#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */\r
+#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */\r
+\r
+#define HRTIM_SET2R_EXTVNT1_Pos (21U)\r
+#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */\r
+#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */\r
+#define HRTIM_SET2R_EXTVNT2_Pos (22U)\r
+#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */\r
+#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */\r
+#define HRTIM_SET2R_EXTVNT3_Pos (23U)\r
+#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */\r
+#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */\r
+#define HRTIM_SET2R_EXTVNT4_Pos (24U)\r
+#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */\r
+#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */\r
+#define HRTIM_SET2R_EXTVNT5_Pos (25U)\r
+#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */\r
+#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */\r
+#define HRTIM_SET2R_EXTVNT6_Pos (26U)\r
+#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */\r
+#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */\r
+#define HRTIM_SET2R_EXTVNT7_Pos (27U)\r
+#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */\r
+#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */\r
+#define HRTIM_SET2R_EXTVNT8_Pos (28U)\r
+#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */\r
+#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */\r
+#define HRTIM_SET2R_EXTVNT9_Pos (29U)\r
+#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */\r
+#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */\r
+#define HRTIM_SET2R_EXTVNT10_Pos (30U)\r
+#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */\r
+#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */\r
+\r
+#define HRTIM_SET2R_UPDATE_Pos (31U)\r
+#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */\r
+#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */\r
+\r
+/**** Bit definition for Slave Output 2 reset register ************************/\r
+#define HRTIM_RST2R_SRT_Pos (0U)\r
+#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */\r
+#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */\r
+#define HRTIM_RST2R_RESYNC_Pos (1U)\r
+#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */\r
+#define HRTIM_RST2R_PER_Pos (2U)\r
+#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */\r
+#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */\r
+#define HRTIM_RST2R_CMP1_Pos (3U)\r
+#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */\r
+#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */\r
+#define HRTIM_RST2R_CMP2_Pos (4U)\r
+#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */\r
+#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */\r
+#define HRTIM_RST2R_CMP3_Pos (5U)\r
+#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */\r
+#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */\r
+#define HRTIM_RST2R_CMP4_Pos (6U)\r
+#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */\r
+#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */\r
+\r
+#define HRTIM_RST2R_MSTPER_Pos (7U)\r
+#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */\r
+#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */\r
+#define HRTIM_RST2R_MSTCMP1_Pos (8U)\r
+#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */\r
+#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */\r
+#define HRTIM_RST2R_MSTCMP2_Pos (9U)\r
+#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */\r
+#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */\r
+#define HRTIM_RST2R_MSTCMP3_Pos (10U)\r
+#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */\r
+#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */\r
+#define HRTIM_RST2R_MSTCMP4_Pos (11U)\r
+#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */\r
+#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */\r
+\r
+#define HRTIM_RST2R_TIMEVNT1_Pos (12U)\r
+#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */\r
+#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */\r
+#define HRTIM_RST2R_TIMEVNT2_Pos (13U)\r
+#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */\r
+#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */\r
+#define HRTIM_RST2R_TIMEVNT3_Pos (14U)\r
+#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */\r
+#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */\r
+#define HRTIM_RST2R_TIMEVNT4_Pos (15U)\r
+#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */\r
+#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */\r
+#define HRTIM_RST2R_TIMEVNT5_Pos (16U)\r
+#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */\r
+#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */\r
+#define HRTIM_RST2R_TIMEVNT6_Pos (17U)\r
+#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */\r
+#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */\r
+#define HRTIM_RST2R_TIMEVNT7_Pos (18U)\r
+#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */\r
+#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */\r
+#define HRTIM_RST2R_TIMEVNT8_Pos (19U)\r
+#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */\r
+#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */\r
+#define HRTIM_RST2R_TIMEVNT9_Pos (20U)\r
+#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */\r
+#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */\r
+\r
+#define HRTIM_RST2R_EXTVNT1_Pos (21U)\r
+#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */\r
+#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */\r
+#define HRTIM_RST2R_EXTVNT2_Pos (22U)\r
+#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */\r
+#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */\r
+#define HRTIM_RST2R_EXTVNT3_Pos (23U)\r
+#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */\r
+#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */\r
+#define HRTIM_RST2R_EXTVNT4_Pos (24U)\r
+#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */\r
+#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */\r
+#define HRTIM_RST2R_EXTVNT5_Pos (25U)\r
+#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */\r
+#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */\r
+#define HRTIM_RST2R_EXTVNT6_Pos (26U)\r
+#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */\r
+#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */\r
+#define HRTIM_RST2R_EXTVNT7_Pos (27U)\r
+#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */\r
+#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */\r
+#define HRTIM_RST2R_EXTVNT8_Pos (28U)\r
+#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */\r
+#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */\r
+#define HRTIM_RST2R_EXTVNT9_Pos (29U)\r
+#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */\r
+#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */\r
+#define HRTIM_RST2R_EXTVNT10_Pos (30U)\r
+#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */\r
+#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */\r
+\r
+#define HRTIM_RST2R_UPDATE_Pos (31U)\r
+#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */\r
+#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */\r
+\r
+/**** Bit definition for Slave external event filtering register 1 ***********/\r
+#define HRTIM_EEFR1_EE1LTCH_Pos (0U)\r
+#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */\r
+#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */\r
+#define HRTIM_EEFR1_EE1FLTR_Pos (1U)\r
+#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */\r
+#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */\r
+#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */\r
+#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */\r
+#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */\r
+#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */\r
+\r
+#define HRTIM_EEFR1_EE2LTCH_Pos (6U)\r
+#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */\r
+#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */\r
+#define HRTIM_EEFR1_EE2FLTR_Pos (7U)\r
+#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */\r
+#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */\r
+#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */\r
+#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */\r
+#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */\r
+#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */\r
+\r
+#define HRTIM_EEFR1_EE3LTCH_Pos (12U)\r
+#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */\r
+#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */\r
+#define HRTIM_EEFR1_EE3FLTR_Pos (13U)\r
+#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */\r
+#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */\r
+#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */\r
+#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */\r
+#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */\r
+#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */\r
+\r
+#define HRTIM_EEFR1_EE4LTCH_Pos (18U)\r
+#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */\r
+#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */\r
+#define HRTIM_EEFR1_EE4FLTR_Pos (19U)\r
+#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */\r
+#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */\r
+#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */\r
+#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */\r
+#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */\r
+#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */\r
+\r
+#define HRTIM_EEFR1_EE5LTCH_Pos (24U)\r
+#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */\r
+#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */\r
+#define HRTIM_EEFR1_EE5FLTR_Pos (25U)\r
+#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */\r
+#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */\r
+#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */\r
+#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */\r
+#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */\r
+#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */\r
+\r
+/**** Bit definition for Slave external event filtering register 2 ***********/\r
+#define HRTIM_EEFR2_EE6LTCH_Pos (0U)\r
+#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */\r
+#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */\r
+#define HRTIM_EEFR2_EE6FLTR_Pos (1U)\r
+#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */\r
+#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */\r
+#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */\r
+#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */\r
+#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */\r
+#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */\r
+\r
+#define HRTIM_EEFR2_EE7LTCH_Pos (6U)\r
+#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */\r
+#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */\r
+#define HRTIM_EEFR2_EE7FLTR_Pos (7U)\r
+#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */\r
+#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */\r
+#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */\r
+#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */\r
+#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */\r
+#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */\r
+\r
+#define HRTIM_EEFR2_EE8LTCH_Pos (12U)\r
+#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */\r
+#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */\r
+#define HRTIM_EEFR2_EE8FLTR_Pos (13U)\r
+#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */\r
+#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */\r
+#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */\r
+#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */\r
+#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */\r
+#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */\r
+\r
+#define HRTIM_EEFR2_EE9LTCH_Pos (18U)\r
+#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */\r
+#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */\r
+#define HRTIM_EEFR2_EE9FLTR_Pos (19U)\r
+#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */\r
+#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */\r
+#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */\r
+#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */\r
+#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */\r
+#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */\r
+\r
+#define HRTIM_EEFR2_EE10LTCH_Pos (24U)\r
+#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */\r
+#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */\r
+#define HRTIM_EEFR2_EE10FLTR_Pos (25U)\r
+#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */\r
+#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */\r
+#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */\r
+#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */\r
+#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */\r
+#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */\r
+\r
+/**** Bit definition for Slave Timer reset register ***************************/\r
+#define HRTIM_RSTR_UPDATE_Pos (1U)\r
+#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */\r
+#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */\r
+#define HRTIM_RSTR_CMP2_Pos (2U)\r
+#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */\r
+#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */\r
+#define HRTIM_RSTR_CMP4_Pos (3U)\r
+#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */\r
+\r
+#define HRTIM_RSTR_MSTPER_Pos (4U)\r
+#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */\r
+#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */\r
+#define HRTIM_RSTR_MSTCMP1_Pos (5U)\r
+#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */\r
+#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */\r
+#define HRTIM_RSTR_MSTCMP2_Pos (6U)\r
+#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */\r
+#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */\r
+#define HRTIM_RSTR_MSTCMP3_Pos (7U)\r
+#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */\r
+#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */\r
+#define HRTIM_RSTR_MSTCMP4_Pos (8U)\r
+#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */\r
+#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */\r
+\r
+#define HRTIM_RSTR_EXTEVNT1_Pos (9U)\r
+#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */\r
+#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */\r
+#define HRTIM_RSTR_EXTEVNT2_Pos (10U)\r
+#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */\r
+#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */\r
+#define HRTIM_RSTR_EXTEVNT3_Pos (11U)\r
+#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */\r
+#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */\r
+#define HRTIM_RSTR_EXTEVNT4_Pos (12U)\r
+#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */\r
+#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */\r
+#define HRTIM_RSTR_EXTEVNT5_Pos (13U)\r
+#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */\r
+#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */\r
+#define HRTIM_RSTR_EXTEVNT6_Pos (14U)\r
+#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */\r
+#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */\r
+#define HRTIM_RSTR_EXTEVNT7_Pos (15U)\r
+#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */\r
+#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */\r
+#define HRTIM_RSTR_EXTEVNT8_Pos (16U)\r
+#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */\r
+#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */\r
+#define HRTIM_RSTR_EXTEVNT9_Pos (17U)\r
+#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */\r
+#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */\r
+#define HRTIM_RSTR_EXTEVNT10_Pos (18U)\r
+#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */\r
+#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */\r
+\r
+#define HRTIM_RSTR_TIMBCMP1_Pos (19U)\r
+#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */\r
+#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */\r
+#define HRTIM_RSTR_TIMBCMP2_Pos (20U)\r
+#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */\r
+#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */\r
+#define HRTIM_RSTR_TIMBCMP4_Pos (21U)\r
+#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */\r
+#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */\r
+\r
+#define HRTIM_RSTR_TIMCCMP1_Pos (22U)\r
+#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */\r
+#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */\r
+#define HRTIM_RSTR_TIMCCMP2_Pos (23U)\r
+#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */\r
+#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */\r
+#define HRTIM_RSTR_TIMCCMP4_Pos (24U)\r
+#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */\r
+#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */\r
+\r
+#define HRTIM_RSTR_TIMDCMP1_Pos (25U)\r
+#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */\r
+#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */\r
+#define HRTIM_RSTR_TIMDCMP2_Pos (26U)\r
+#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */\r
+#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */\r
+#define HRTIM_RSTR_TIMDCMP4_Pos (27U)\r
+#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */\r
+#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */\r
+\r
+#define HRTIM_RSTR_TIMECMP1_Pos (28U)\r
+#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */\r
+#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */\r
+#define HRTIM_RSTR_TIMECMP2_Pos (29U)\r
+#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */\r
+#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */\r
+#define HRTIM_RSTR_TIMECMP4_Pos (30U)\r
+#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */\r
+#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */\r
+\r
+/**** Bit definition for Slave Timer Chopper register *************************/\r
+#define HRTIM_CHPR_CARFRQ_Pos (0U)\r
+#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */\r
+#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */\r
+#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */\r
+#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */\r
+#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */\r
+#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */\r
+\r
+#define HRTIM_CHPR_CARDTY_Pos (4U)\r
+#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */\r
+#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */\r
+#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */\r
+#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */\r
+#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */\r
+\r
+#define HRTIM_CHPR_STRPW_Pos (7U)\r
+#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */\r
+#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */\r
+#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */\r
+#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */\r
+#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */\r
+#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */\r
+\r
+/**** Bit definition for Slave Timer Capture 1 control register ***************/\r
+#define HRTIM_CPT1CR_SWCPT_Pos (0U)\r
+#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */\r
+#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */\r
+#define HRTIM_CPT1CR_UPDCPT_Pos (1U)\r
+#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */\r
+#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */\r
+#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)\r
+#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */\r
+#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */\r
+#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)\r
+#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */\r
+#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */\r
+#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)\r
+#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */\r
+#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */\r
+#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)\r
+#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */\r
+#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */\r
+#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)\r
+#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */\r
+#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */\r
+#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)\r
+#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */\r
+#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */\r
+#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)\r
+#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */\r
+#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */\r
+#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)\r
+#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */\r
+#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */\r
+#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)\r
+#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */\r
+#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */\r
+#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)\r
+#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */\r
+#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */\r
+\r
+#define HRTIM_CPT1CR_TA1SET_Pos (12U)\r
+#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */\r
+#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */\r
+#define HRTIM_CPT1CR_TA1RST_Pos (13U)\r
+#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */\r
+#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */\r
+#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)\r
+#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */\r
+#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */\r
+#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)\r
+#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */\r
+#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */\r
+\r
+#define HRTIM_CPT1CR_TB1SET_Pos (16U)\r
+#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */\r
+#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */\r
+#define HRTIM_CPT1CR_TB1RST_Pos (17U)\r
+#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */\r
+#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */\r
+#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)\r
+#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */\r
+#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */\r
+#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)\r
+#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */\r
+#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */\r
+\r
+#define HRTIM_CPT1CR_TC1SET_Pos (20U)\r
+#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */\r
+#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */\r
+#define HRTIM_CPT1CR_TC1RST_Pos (21U)\r
+#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */\r
+#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */\r
+#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)\r
+#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */\r
+#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */\r
+#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)\r
+#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */\r
+#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */\r
+\r
+#define HRTIM_CPT1CR_TD1SET_Pos (24U)\r
+#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */\r
+#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */\r
+#define HRTIM_CPT1CR_TD1RST_Pos (25U)\r
+#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */\r
+#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */\r
+#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)\r
+#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */\r
+#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */\r
+#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)\r
+#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */\r
+#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */\r
+\r
+#define HRTIM_CPT1CR_TE1SET_Pos (28U)\r
+#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */\r
+#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */\r
+#define HRTIM_CPT1CR_TE1RST_Pos (29U)\r
+#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */\r
+#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */\r
+#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)\r
+#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */\r
+#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */\r
+#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)\r
+#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */\r
+#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */\r
+\r
+/**** Bit definition for Slave Timer Capture 2 control register ***************/\r
+#define HRTIM_CPT2CR_SWCPT_Pos (0U)\r
+#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */\r
+#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */\r
+#define HRTIM_CPT2CR_UPDCPT_Pos (1U)\r
+#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */\r
+#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */\r
+#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)\r
+#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */\r
+#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */\r
+#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)\r
+#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */\r
+#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */\r
+#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)\r
+#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */\r
+#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */\r
+#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)\r
+#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */\r
+#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */\r
+#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)\r
+#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */\r
+#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */\r
+#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)\r
+#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */\r
+#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */\r
+#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)\r
+#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */\r
+#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */\r
+#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)\r
+#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */\r
+#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */\r
+#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)\r
+#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */\r
+#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */\r
+#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)\r
+#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */\r
+#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */\r
+\r
+#define HRTIM_CPT2CR_TA1SET_Pos (12U)\r
+#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */\r
+#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */\r
+#define HRTIM_CPT2CR_TA1RST_Pos (13U)\r
+#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */\r
+#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */\r
+#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)\r
+#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */\r
+#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */\r
+#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)\r
+#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */\r
+#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */\r
+\r
+#define HRTIM_CPT2CR_TB1SET_Pos (16U)\r
+#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */\r
+#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */\r
+#define HRTIM_CPT2CR_TB1RST_Pos (17U)\r
+#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */\r
+#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */\r
+#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)\r
+#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */\r
+#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */\r
+#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)\r
+#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */\r
+#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */\r
+\r
+#define HRTIM_CPT2CR_TC1SET_Pos (20U)\r
+#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */\r
+#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */\r
+#define HRTIM_CPT2CR_TC1RST_Pos (21U)\r
+#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */\r
+#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */\r
+#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)\r
+#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */\r
+#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */\r
+#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)\r
+#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */\r
+#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */\r
+\r
+#define HRTIM_CPT2CR_TD1SET_Pos (24U)\r
+#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */\r
+#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */\r
+#define HRTIM_CPT2CR_TD1RST_Pos (25U)\r
+#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */\r
+#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */\r
+#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)\r
+#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */\r
+#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */\r
+#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)\r
+#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */\r
+#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */\r
+\r
+#define HRTIM_CPT2CR_TE1SET_Pos (28U)\r
+#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */\r
+#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */\r
+#define HRTIM_CPT2CR_TE1RST_Pos (29U)\r
+#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */\r
+#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */\r
+#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)\r
+#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */\r
+#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */\r
+#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)\r
+#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */\r
+#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */\r
+\r
+/**** Bit definition for Slave Timer Output register **************************/\r
+#define HRTIM_OUTR_POL1_Pos (1U)\r
+#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */\r
+#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */\r
+#define HRTIM_OUTR_IDLM1_Pos (2U)\r
+#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */\r
+#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */\r
+#define HRTIM_OUTR_IDLES1_Pos (3U)\r
+#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */\r
+#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */\r
+#define HRTIM_OUTR_FAULT1_Pos (4U)\r
+#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */\r
+#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */\r
+#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */\r
+#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */\r
+#define HRTIM_OUTR_CHP1_Pos (6U)\r
+#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */\r
+#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */\r
+#define HRTIM_OUTR_DIDL1_Pos (7U)\r
+#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */\r
+#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */\r
+\r
+#define HRTIM_OUTR_DTEN_Pos (8U)\r
+#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */\r
+#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */\r
+#define HRTIM_OUTR_DLYPRTEN_Pos (9U)\r
+#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */\r
+#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */\r
+#define HRTIM_OUTR_DLYPRT_Pos (10U)\r
+#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */\r
+#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */\r
+#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */\r
+#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */\r
+#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */\r
+\r
+#define HRTIM_OUTR_POL2_Pos (17U)\r
+#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */\r
+#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */\r
+#define HRTIM_OUTR_IDLM2_Pos (18U)\r
+#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */\r
+#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */\r
+#define HRTIM_OUTR_IDLES2_Pos (19U)\r
+#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */\r
+#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */\r
+#define HRTIM_OUTR_FAULT2_Pos (20U)\r
+#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */\r
+#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */\r
+#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */\r
+#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */\r
+#define HRTIM_OUTR_CHP2_Pos (22U)\r
+#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */\r
+#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */\r
+#define HRTIM_OUTR_DIDL2_Pos (23U)\r
+#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */\r
+#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */\r
+\r
+/**** Bit definition for Slave Timer Fault register ***************************/\r
+#define HRTIM_FLTR_FLT1EN_Pos (0U)\r
+#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */\r
+#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */\r
+#define HRTIM_FLTR_FLT2EN_Pos (1U)\r
+#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */\r
+#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */\r
+#define HRTIM_FLTR_FLT3EN_Pos (2U)\r
+#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */\r
+#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */\r
+#define HRTIM_FLTR_FLT4EN_Pos (3U)\r
+#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */\r
+#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */\r
+#define HRTIM_FLTR_FLT5EN_Pos (4U)\r
+#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */\r
+#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */\r
+#define HRTIM_FLTR_FLTLCK_Pos (31U)\r
+#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */\r
+#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */\r
+\r
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/\r
+#define HRTIM_CR1_MUDIS_Pos (0U)\r
+#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */\r
+#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/\r
+#define HRTIM_CR1_TAUDIS_Pos (1U)\r
+#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */\r
+#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/\r
+#define HRTIM_CR1_TBUDIS_Pos (2U)\r
+#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */\r
+#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/\r
+#define HRTIM_CR1_TCUDIS_Pos (3U)\r
+#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */\r
+#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/\r
+#define HRTIM_CR1_TDUDIS_Pos (4U)\r
+#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */\r
+#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/\r
+#define HRTIM_CR1_TEUDIS_Pos (5U)\r
+#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */\r
+#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/\r
+#define HRTIM_CR1_ADC1USRC_Pos (16U)\r
+#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */\r
+#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */\r
+#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */\r
+#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */\r
+#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */\r
+#define HRTIM_CR1_ADC2USRC_Pos (19U)\r
+#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */\r
+#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */\r
+#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */\r
+#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */\r
+#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */\r
+#define HRTIM_CR1_ADC3USRC_Pos (22U)\r
+#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */\r
+#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */\r
+#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */\r
+#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */\r
+#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */\r
+#define HRTIM_CR1_ADC4USRC_Pos (25U)\r
+#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */\r
+#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */\r
+#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */\r
+#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */\r
+#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */\r
+\r
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/\r
+#define HRTIM_CR2_MSWU_Pos (0U)\r
+#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */\r
+#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */\r
+#define HRTIM_CR2_TASWU_Pos (1U)\r
+#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */\r
+#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */\r
+#define HRTIM_CR2_TBSWU_Pos (2U)\r
+#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */\r
+#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */\r
+#define HRTIM_CR2_TCSWU_Pos (3U)\r
+#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */\r
+#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */\r
+#define HRTIM_CR2_TDSWU_Pos (4U)\r
+#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */\r
+#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */\r
+#define HRTIM_CR2_TESWU_Pos (5U)\r
+#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */\r
+#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */\r
+#define HRTIM_CR2_MRST_Pos (8U)\r
+#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */\r
+#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */\r
+#define HRTIM_CR2_TARST_Pos (9U)\r
+#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */\r
+#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */\r
+#define HRTIM_CR2_TBRST_Pos (10U)\r
+#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */\r
+#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */\r
+#define HRTIM_CR2_TCRST_Pos (11U)\r
+#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */\r
+#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */\r
+#define HRTIM_CR2_TDRST_Pos (12U)\r
+#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */\r
+#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */\r
+#define HRTIM_CR2_TERST_Pos (13U)\r
+#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */\r
+#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */\r
+\r
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/\r
+#define HRTIM_ISR_FLT1_Pos (0U)\r
+#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */\r
+#define HRTIM_ISR_FLT2_Pos (1U)\r
+#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */\r
+#define HRTIM_ISR_FLT3_Pos (2U)\r
+#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */\r
+#define HRTIM_ISR_FLT4_Pos (3U)\r
+#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */\r
+#define HRTIM_ISR_FLT5_Pos (4U)\r
+#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */\r
+#define HRTIM_ISR_SYSFLT_Pos (5U)\r
+#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */\r
+#define HRTIM_ISR_BMPER_Pos (17U)\r
+#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */\r
+#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */\r
+\r
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/\r
+#define HRTIM_ICR_FLT1C_Pos (0U)\r
+#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */\r
+#define HRTIM_ICR_FLT2C_Pos (1U)\r
+#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */\r
+#define HRTIM_ICR_FLT3C_Pos (2U)\r
+#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */\r
+#define HRTIM_ICR_FLT4C_Pos (3U)\r
+#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */\r
+#define HRTIM_ICR_FLT5C_Pos (4U)\r
+#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */\r
+#define HRTIM_ICR_SYSFLTC_Pos (5U)\r
+#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */\r
+#define HRTIM_ICR_BMPERC_Pos (17U)\r
+#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */\r
+#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */\r
+\r
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/\r
+#define HRTIM_IER_FLT1_Pos (0U)\r
+#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */\r
+#define HRTIM_IER_FLT2_Pos (1U)\r
+#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */\r
+#define HRTIM_IER_FLT3_Pos (2U)\r
+#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */\r
+#define HRTIM_IER_FLT4_Pos (3U)\r
+#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */\r
+#define HRTIM_IER_FLT5_Pos (4U)\r
+#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */\r
+#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */\r
+#define HRTIM_IER_SYSFLT_Pos (5U)\r
+#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */\r
+#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */\r
+#define HRTIM_IER_BMPER_Pos (17U)\r
+#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */\r
+#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */\r
+\r
+/**** Bit definition for Common HRTIM Timer output enable register ************/\r
+#define HRTIM_OENR_TA1OEN_Pos (0U)\r
+#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */\r
+#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */\r
+#define HRTIM_OENR_TA2OEN_Pos (1U)\r
+#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */\r
+#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */\r
+#define HRTIM_OENR_TB1OEN_Pos (2U)\r
+#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */\r
+#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */\r
+#define HRTIM_OENR_TB2OEN_Pos (3U)\r
+#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */\r
+#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */\r
+#define HRTIM_OENR_TC1OEN_Pos (4U)\r
+#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */\r
+#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */\r
+#define HRTIM_OENR_TC2OEN_Pos (5U)\r
+#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */\r
+#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */\r
+#define HRTIM_OENR_TD1OEN_Pos (6U)\r
+#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */\r
+#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */\r
+#define HRTIM_OENR_TD2OEN_Pos (7U)\r
+#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */\r
+#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */\r
+#define HRTIM_OENR_TE1OEN_Pos (8U)\r
+#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */\r
+#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */\r
+#define HRTIM_OENR_TE2OEN_Pos (9U)\r
+#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */\r
+#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */\r
+\r
+/**** Bit definition for Common HRTIM Timer output disable register ***********/\r
+#define HRTIM_ODISR_TA1ODIS_Pos (0U)\r
+#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */\r
+#define HRTIM_ODISR_TA2ODIS_Pos (1U)\r
+#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */\r
+#define HRTIM_ODISR_TB1ODIS_Pos (2U)\r
+#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */\r
+#define HRTIM_ODISR_TB2ODIS_Pos (3U)\r
+#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */\r
+#define HRTIM_ODISR_TC1ODIS_Pos (4U)\r
+#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */\r
+#define HRTIM_ODISR_TC2ODIS_Pos (5U)\r
+#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */\r
+#define HRTIM_ODISR_TD1ODIS_Pos (6U)\r
+#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */\r
+#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */\r
+#define HRTIM_ODISR_TD2ODIS_Pos (7U)\r
+#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */\r
+#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */\r
+#define HRTIM_ODISR_TE1ODIS_Pos (8U)\r
+#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */\r
+#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */\r
+#define HRTIM_ODISR_TE2ODIS_Pos (9U)\r
+#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */\r
+#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */\r
+\r
+/**** Bit definition for Common HRTIM Timer output disable status register *****/\r
+#define HRTIM_ODSR_TA1ODS_Pos (0U)\r
+#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */\r
+#define HRTIM_ODSR_TA2ODS_Pos (1U)\r
+#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */\r
+#define HRTIM_ODSR_TB1ODS_Pos (2U)\r
+#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */\r
+#define HRTIM_ODSR_TB2ODS_Pos (3U)\r
+#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */\r
+#define HRTIM_ODSR_TC1ODS_Pos (4U)\r
+#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */\r
+#define HRTIM_ODSR_TC2ODS_Pos (5U)\r
+#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */\r
+#define HRTIM_ODSR_TD1ODS_Pos (6U)\r
+#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */\r
+#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */\r
+#define HRTIM_ODSR_TD2ODS_Pos (7U)\r
+#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */\r
+#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */\r
+#define HRTIM_ODSR_TE1ODS_Pos (8U)\r
+#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */\r
+#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */\r
+#define HRTIM_ODSR_TE2ODS_Pos (9U)\r
+#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */\r
+#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */\r
+\r
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/\r
+#define HRTIM_BMCR_BME_Pos (0U)\r
+#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */\r
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */\r
+#define HRTIM_BMCR_BMOM_Pos (1U)\r
+#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */\r
+#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */\r
+#define HRTIM_BMCR_BMCLK_Pos (2U)\r
+#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */\r
+#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */\r
+#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */\r
+#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */\r
+#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */\r
+#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */\r
+#define HRTIM_BMCR_BMPRSC_Pos (6U)\r
+#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */\r
+#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */\r
+#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */\r
+#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */\r
+#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */\r
+#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */\r
+#define HRTIM_BMCR_BMPREN_Pos (10U)\r
+#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */\r
+#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */\r
+#define HRTIM_BMCR_MTBM_Pos (16U)\r
+#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */\r
+#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */\r
+#define HRTIM_BMCR_TABM_Pos (17U)\r
+#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */\r
+#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */\r
+#define HRTIM_BMCR_TBBM_Pos (18U)\r
+#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */\r
+#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */\r
+#define HRTIM_BMCR_TCBM_Pos (19U)\r
+#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */\r
+#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */\r
+#define HRTIM_BMCR_TDBM_Pos (20U)\r
+#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */\r
+#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */\r
+#define HRTIM_BMCR_TEBM_Pos (21U)\r
+#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */\r
+#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */\r
+#define HRTIM_BMCR_BMSTAT_Pos (31U)\r
+#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */\r
+#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */\r
+\r
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/\r
+#define HRTIM_BMTRGR_SW_Pos (0U)\r
+#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */\r
+#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */\r
+#define HRTIM_BMTRGR_MSTRST_Pos (1U)\r
+#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */\r
+#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */\r
+#define HRTIM_BMTRGR_MSTREP_Pos (2U)\r
+#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */\r
+#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */\r
+#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)\r
+#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */\r
+#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */\r
+#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)\r
+#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */\r
+#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */\r
+#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)\r
+#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */\r
+#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */\r
+#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)\r
+#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */\r
+#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */\r
+#define HRTIM_BMTRGR_TARST_Pos (7U)\r
+#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */\r
+#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */\r
+#define HRTIM_BMTRGR_TAREP_Pos (8U)\r
+#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */\r
+#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */\r
+#define HRTIM_BMTRGR_TACMP1_Pos (9U)\r
+#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */\r
+#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */\r
+#define HRTIM_BMTRGR_TACMP2_Pos (10U)\r
+#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */\r
+#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */\r
+#define HRTIM_BMTRGR_TBRST_Pos (11U)\r
+#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */\r
+#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */\r
+#define HRTIM_BMTRGR_TBREP_Pos (12U)\r
+#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */\r
+#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */\r
+#define HRTIM_BMTRGR_TBCMP1_Pos (13U)\r
+#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */\r
+#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */\r
+#define HRTIM_BMTRGR_TBCMP2_Pos (14U)\r
+#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */\r
+#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */\r
+#define HRTIM_BMTRGR_TCRST_Pos (15U)\r
+#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */\r
+#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */\r
+#define HRTIM_BMTRGR_TCREP_Pos (16U)\r
+#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */\r
+#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */\r
+#define HRTIM_BMTRGR_TCCMP1_Pos (17U)\r
+#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */\r
+#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */\r
+#define HRTIM_BMTRGR_TCCMP2_Pos (18U)\r
+#define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */\r
+#define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */\r
+#define HRTIM_BMTRGR_TDRST_Pos (19U)\r
+#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */\r
+#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */\r
+#define HRTIM_BMTRGR_TDREP_Pos (20U)\r
+#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */\r
+#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */\r
+#define HRTIM_BMTRGR_TDCMP1_Pos (21U)\r
+#define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */\r
+#define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */\r
+#define HRTIM_BMTRGR_TDCMP2_Pos (22U)\r
+#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */\r
+#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */\r
+#define HRTIM_BMTRGR_TERST_Pos (23U)\r
+#define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */\r
+#define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */\r
+#define HRTIM_BMTRGR_TEREP_Pos (24U)\r
+#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */\r
+#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */\r
+#define HRTIM_BMTRGR_TECMP1_Pos (25U)\r
+#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */\r
+#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */\r
+#define HRTIM_BMTRGR_TECMP2_Pos (26U)\r
+#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */\r
+#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */\r
+#define HRTIM_BMTRGR_TAEEV7_Pos (27U)\r
+#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */\r
+#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */\r
+#define HRTIM_BMTRGR_TDEEV8_Pos (28U)\r
+#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */\r
+#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */\r
+#define HRTIM_BMTRGR_EEV7_Pos (29U)\r
+#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */\r
+#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */\r
+#define HRTIM_BMTRGR_EEV8_Pos (30U)\r
+#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */\r
+#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */\r
+#define HRTIM_BMTRGR_OCHPEV_Pos (31U)\r
+#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */\r
+#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */\r
+\r
+/******************* Bit definition for HRTIM_BMCMPR register ***************/\r
+#define HRTIM_BMCMPR_BMCMPR_Pos (0U)\r
+#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */\r
+\r
+/******************* Bit definition for HRTIM_BMPER register ****************/\r
+#define HRTIM_BMPER_BMPER_Pos (0U)\r
+#define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */\r
+#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */\r
+\r
+/******************* Bit definition for HRTIM_EECR1 register ****************/\r
+#define HRTIM_EECR1_EE1SRC_Pos (0U)\r
+#define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */\r
+#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */\r
+#define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */\r
+#define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_EECR1_EE1POL_Pos (2U)\r
+#define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */\r
+#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */\r
+#define HRTIM_EECR1_EE1SNS_Pos (3U)\r
+#define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */\r
+#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */\r
+#define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */\r
+#define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */\r
+#define HRTIM_EECR1_EE1FAST_Pos (5U)\r
+#define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */\r
+#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */\r
+\r
+#define HRTIM_EECR1_EE2SRC_Pos (6U)\r
+#define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */\r
+#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */\r
+#define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */\r
+#define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */\r
+#define HRTIM_EECR1_EE2POL_Pos (8U)\r
+#define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */\r
+#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */\r
+#define HRTIM_EECR1_EE2SNS_Pos (9U)\r
+#define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */\r
+#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */\r
+#define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */\r
+#define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */\r
+#define HRTIM_EECR1_EE2FAST_Pos (11U)\r
+#define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */\r
+#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */\r
+\r
+#define HRTIM_EECR1_EE3SRC_Pos (12U)\r
+#define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */\r
+#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */\r
+#define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */\r
+#define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */\r
+#define HRTIM_EECR1_EE3POL_Pos (14U)\r
+#define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */\r
+#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */\r
+#define HRTIM_EECR1_EE3SNS_Pos (15U)\r
+#define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */\r
+#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */\r
+#define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */\r
+#define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */\r
+#define HRTIM_EECR1_EE3FAST_Pos (17U)\r
+#define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */\r
+#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */\r
+\r
+#define HRTIM_EECR1_EE4SRC_Pos (18U)\r
+#define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */\r
+#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */\r
+#define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */\r
+#define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */\r
+#define HRTIM_EECR1_EE4POL_Pos (20U)\r
+#define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */\r
+#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */\r
+#define HRTIM_EECR1_EE4SNS_Pos (21U)\r
+#define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */\r
+#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */\r
+#define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */\r
+#define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */\r
+#define HRTIM_EECR1_EE4FAST_Pos (23U)\r
+#define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */\r
+#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */\r
+\r
+#define HRTIM_EECR1_EE5SRC_Pos (24U)\r
+#define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */\r
+#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */\r
+#define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */\r
+#define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */\r
+#define HRTIM_EECR1_EE5POL_Pos (26U)\r
+#define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */\r
+#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */\r
+#define HRTIM_EECR1_EE5SNS_Pos (27U)\r
+#define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */\r
+#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */\r
+#define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */\r
+#define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */\r
+#define HRTIM_EECR1_EE5FAST_Pos (29U)\r
+#define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */\r
+#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */\r
+\r
+/******************* Bit definition for HRTIM_EECR2 register ****************/\r
+#define HRTIM_EECR2_EE6SRC_Pos (0U)\r
+#define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */\r
+#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */\r
+#define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */\r
+#define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */\r
+#define HRTIM_EECR2_EE6POL_Pos (2U)\r
+#define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */\r
+#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */\r
+#define HRTIM_EECR2_EE6SNS_Pos (3U)\r
+#define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */\r
+#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */\r
+#define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */\r
+#define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */\r
+\r
+#define HRTIM_EECR2_EE7SRC_Pos (6U)\r
+#define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */\r
+#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */\r
+#define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */\r
+#define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */\r
+#define HRTIM_EECR2_EE7POL_Pos (8U)\r
+#define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */\r
+#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */\r
+#define HRTIM_EECR2_EE7SNS_Pos (9U)\r
+#define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */\r
+#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */\r
+#define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */\r
+#define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */\r
+\r
+#define HRTIM_EECR2_EE8SRC_Pos (12U)\r
+#define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */\r
+#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */\r
+#define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */\r
+#define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */\r
+#define HRTIM_EECR2_EE8POL_Pos (14U)\r
+#define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */\r
+#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */\r
+#define HRTIM_EECR2_EE8SNS_Pos (15U)\r
+#define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */\r
+#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */\r
+#define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */\r
+#define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */\r
+\r
+#define HRTIM_EECR2_EE9SRC_Pos (18U)\r
+#define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */\r
+#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */\r
+#define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */\r
+#define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */\r
+#define HRTIM_EECR2_EE9POL_Pos (20U)\r
+#define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */\r
+#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */\r
+#define HRTIM_EECR2_EE9SNS_Pos (21U)\r
+#define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */\r
+#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */\r
+#define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */\r
+#define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */\r
+\r
+#define HRTIM_EECR2_EE10SRC_Pos (24U)\r
+#define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */\r
+#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */\r
+#define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */\r
+#define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */\r
+#define HRTIM_EECR2_EE10POL_Pos (26U)\r
+#define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */\r
+#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */\r
+#define HRTIM_EECR2_EE10SNS_Pos (27U)\r
+#define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */\r
+#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */\r
+#define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */\r
+#define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */\r
+\r
+/******************* Bit definition for HRTIM_EECR3 register ****************/\r
+#define HRTIM_EECR3_EE6F_Pos (0U)\r
+#define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */\r
+#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */\r
+#define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */\r
+#define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */\r
+#define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */\r
+#define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */\r
+#define HRTIM_EECR3_EE7F_Pos (6U)\r
+#define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */\r
+#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */\r
+#define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */\r
+#define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */\r
+#define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */\r
+#define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */\r
+#define HRTIM_EECR3_EE8F_Pos (12U)\r
+#define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */\r
+#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */\r
+#define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */\r
+#define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */\r
+#define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */\r
+#define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */\r
+#define HRTIM_EECR3_EE9F_Pos (18U)\r
+#define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */\r
+#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */\r
+#define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */\r
+#define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */\r
+#define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */\r
+#define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */\r
+#define HRTIM_EECR3_EE10F_Pos (24U)\r
+#define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */\r
+#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */\r
+#define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */\r
+#define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */\r
+#define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */\r
+#define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */\r
+#define HRTIM_EECR3_EEVSD_Pos (30U)\r
+#define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */\r
+#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */\r
+#define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */\r
+#define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */\r
+\r
+/******************* Bit definition for HRTIM_ADC1R register ****************/\r
+#define HRTIM_ADC1R_AD1MC1_Pos (0U)\r
+#define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */\r
+#define HRTIM_ADC1R_AD1MC2_Pos (1U)\r
+#define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */\r
+#define HRTIM_ADC1R_AD1MC3_Pos (2U)\r
+#define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */\r
+#define HRTIM_ADC1R_AD1MC4_Pos (3U)\r
+#define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */\r
+#define HRTIM_ADC1R_AD1MPER_Pos (4U)\r
+#define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */\r
+#define HRTIM_ADC1R_AD1EEV1_Pos (5U)\r
+#define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */\r
+#define HRTIM_ADC1R_AD1EEV2_Pos (6U)\r
+#define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */\r
+#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */\r
+#define HRTIM_ADC1R_AD1EEV3_Pos (7U)\r
+#define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */\r
+#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */\r
+#define HRTIM_ADC1R_AD1EEV4_Pos (8U)\r
+#define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */\r
+#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */\r
+#define HRTIM_ADC1R_AD1EEV5_Pos (9U)\r
+#define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */\r
+#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */\r
+#define HRTIM_ADC1R_AD1TAC2_Pos (10U)\r
+#define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */\r
+#define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */\r
+#define HRTIM_ADC1R_AD1TAC3_Pos (11U)\r
+#define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */\r
+#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */\r
+#define HRTIM_ADC1R_AD1TAC4_Pos (12U)\r
+#define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */\r
+#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */\r
+#define HRTIM_ADC1R_AD1TAPER_Pos (13U)\r
+#define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */\r
+#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */\r
+#define HRTIM_ADC1R_AD1TARST_Pos (14U)\r
+#define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */\r
+#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */\r
+#define HRTIM_ADC1R_AD1TBC2_Pos (15U)\r
+#define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */\r
+#define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */\r
+#define HRTIM_ADC1R_AD1TBC3_Pos (16U)\r
+#define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */\r
+#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */\r
+#define HRTIM_ADC1R_AD1TBC4_Pos (17U)\r
+#define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */\r
+#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */\r
+#define HRTIM_ADC1R_AD1TBPER_Pos (18U)\r
+#define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */\r
+#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */\r
+#define HRTIM_ADC1R_AD1TBRST_Pos (19U)\r
+#define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */\r
+#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */\r
+#define HRTIM_ADC1R_AD1TCC2_Pos (20U)\r
+#define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */\r
+#define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */\r
+#define HRTIM_ADC1R_AD1TCC3_Pos (21U)\r
+#define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */\r
+#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */\r
+#define HRTIM_ADC1R_AD1TCC4_Pos (22U)\r
+#define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */\r
+#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */\r
+#define HRTIM_ADC1R_AD1TCPER_Pos (23U)\r
+#define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */\r
+#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */\r
+#define HRTIM_ADC1R_AD1TDC2_Pos (24U)\r
+#define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */\r
+#define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */\r
+#define HRTIM_ADC1R_AD1TDC3_Pos (25U)\r
+#define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */\r
+#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */\r
+#define HRTIM_ADC1R_AD1TDC4_Pos (26U)\r
+#define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */\r
+#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */\r
+#define HRTIM_ADC1R_AD1TDPER_Pos (27U)\r
+#define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */\r
+#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */\r
+#define HRTIM_ADC1R_AD1TEC2_Pos (28U)\r
+#define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */\r
+#define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */\r
+#define HRTIM_ADC1R_AD1TEC3_Pos (29U)\r
+#define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */\r
+#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */\r
+#define HRTIM_ADC1R_AD1TEC4_Pos (30U)\r
+#define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */\r
+#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */\r
+#define HRTIM_ADC1R_AD1TEPER_Pos (31U)\r
+#define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */\r
+#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */\r
+\r
+/******************* Bit definition for HRTIM_ADC2R register ****************/\r
+#define HRTIM_ADC2R_AD2MC1_Pos (0U)\r
+#define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */\r
+#define HRTIM_ADC2R_AD2MC2_Pos (1U)\r
+#define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */\r
+#define HRTIM_ADC2R_AD2MC3_Pos (2U)\r
+#define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */\r
+#define HRTIM_ADC2R_AD2MC4_Pos (3U)\r
+#define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */\r
+#define HRTIM_ADC2R_AD2MPER_Pos (4U)\r
+#define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */\r
+#define HRTIM_ADC2R_AD2EEV6_Pos (5U)\r
+#define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */\r
+#define HRTIM_ADC2R_AD2EEV7_Pos (6U)\r
+#define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */\r
+#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */\r
+#define HRTIM_ADC2R_AD2EEV8_Pos (7U)\r
+#define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */\r
+#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */\r
+#define HRTIM_ADC2R_AD2EEV9_Pos (8U)\r
+#define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */\r
+#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */\r
+#define HRTIM_ADC2R_AD2EEV10_Pos (9U)\r
+#define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */\r
+#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */\r
+#define HRTIM_ADC2R_AD2TAC2_Pos (10U)\r
+#define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */\r
+#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */\r
+#define HRTIM_ADC2R_AD2TAC3_Pos (11U)\r
+#define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */\r
+#define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */\r
+#define HRTIM_ADC2R_AD2TAC4_Pos (12U)\r
+#define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */\r
+#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/\r
+#define HRTIM_ADC2R_AD2TAPER_Pos (13U)\r
+#define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */\r
+#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */\r
+#define HRTIM_ADC2R_AD2TBC2_Pos (14U)\r
+#define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */\r
+#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */\r
+#define HRTIM_ADC2R_AD2TBC3_Pos (15U)\r
+#define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */\r
+#define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */\r
+#define HRTIM_ADC2R_AD2TBC4_Pos (16U)\r
+#define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */\r
+#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */\r
+#define HRTIM_ADC2R_AD2TBPER_Pos (17U)\r
+#define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */\r
+#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */\r
+#define HRTIM_ADC2R_AD2TCC2_Pos (18U)\r
+#define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */\r
+#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */\r
+#define HRTIM_ADC2R_AD2TCC3_Pos (19U)\r
+#define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */\r
+#define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */\r
+#define HRTIM_ADC2R_AD2TCC4_Pos (20U)\r
+#define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */\r
+#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */\r
+#define HRTIM_ADC2R_AD2TCPER_Pos (21U)\r
+#define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */\r
+#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */\r
+#define HRTIM_ADC2R_AD2TCRST_Pos (22U)\r
+#define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */\r
+#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */\r
+#define HRTIM_ADC2R_AD2TDC2_Pos (23U)\r
+#define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */\r
+#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */\r
+#define HRTIM_ADC2R_AD2TDC3_Pos (24U)\r
+#define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */\r
+#define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */\r
+#define HRTIM_ADC2R_AD2TDC4_Pos (25U)\r
+#define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */\r
+#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/\r
+#define HRTIM_ADC2R_AD2TDPER_Pos (26U)\r
+#define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */\r
+#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */\r
+#define HRTIM_ADC2R_AD2TDRST_Pos (27U)\r
+#define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */\r
+#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */\r
+#define HRTIM_ADC2R_AD2TEC2_Pos (28U)\r
+#define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */\r
+#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */\r
+#define HRTIM_ADC2R_AD2TEC3_Pos (29U)\r
+#define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */\r
+#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */\r
+#define HRTIM_ADC2R_AD2TEC4_Pos (30U)\r
+#define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */\r
+#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */\r
+#define HRTIM_ADC2R_AD2TERST_Pos (31U)\r
+#define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */\r
+#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */\r
+\r
+/******************* Bit definition for HRTIM_ADC3R register ****************/\r
+#define HRTIM_ADC3R_AD3MC1_Pos (0U)\r
+#define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */\r
+#define HRTIM_ADC3R_AD3MC2_Pos (1U)\r
+#define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */\r
+#define HRTIM_ADC3R_AD3MC3_Pos (2U)\r
+#define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */\r
+#define HRTIM_ADC3R_AD3MC4_Pos (3U)\r
+#define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */\r
+#define HRTIM_ADC3R_AD3MPER_Pos (4U)\r
+#define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */\r
+#define HRTIM_ADC3R_AD3EEV1_Pos (5U)\r
+#define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */\r
+#define HRTIM_ADC3R_AD3EEV2_Pos (6U)\r
+#define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */\r
+#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */\r
+#define HRTIM_ADC3R_AD3EEV3_Pos (7U)\r
+#define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */\r
+#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */\r
+#define HRTIM_ADC3R_AD3EEV4_Pos (8U)\r
+#define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */\r
+#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */\r
+#define HRTIM_ADC3R_AD3EEV5_Pos (9U)\r
+#define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */\r
+#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */\r
+#define HRTIM_ADC3R_AD3TAC2_Pos (10U)\r
+#define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */\r
+#define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */\r
+#define HRTIM_ADC3R_AD3TAC3_Pos (11U)\r
+#define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */\r
+#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */\r
+#define HRTIM_ADC3R_AD3TAC4_Pos (12U)\r
+#define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */\r
+#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */\r
+#define HRTIM_ADC3R_AD3TAPER_Pos (13U)\r
+#define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */\r
+#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */\r
+#define HRTIM_ADC3R_AD3TARST_Pos (14U)\r
+#define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */\r
+#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */\r
+#define HRTIM_ADC3R_AD3TBC2_Pos (15U)\r
+#define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */\r
+#define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */\r
+#define HRTIM_ADC3R_AD3TBC3_Pos (16U)\r
+#define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */\r
+#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */\r
+#define HRTIM_ADC3R_AD3TBC4_Pos (17U)\r
+#define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */\r
+#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */\r
+#define HRTIM_ADC3R_AD3TBPER_Pos (18U)\r
+#define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */\r
+#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */\r
+#define HRTIM_ADC3R_AD3TBRST_Pos (19U)\r
+#define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */\r
+#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */\r
+#define HRTIM_ADC3R_AD3TCC2_Pos (20U)\r
+#define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */\r
+#define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */\r
+#define HRTIM_ADC3R_AD3TCC3_Pos (21U)\r
+#define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */\r
+#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */\r
+#define HRTIM_ADC3R_AD3TCC4_Pos (22U)\r
+#define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */\r
+#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */\r
+#define HRTIM_ADC3R_AD3TCPER_Pos (23U)\r
+#define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */\r
+#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */\r
+#define HRTIM_ADC3R_AD3TDC2_Pos (24U)\r
+#define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */\r
+#define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */\r
+#define HRTIM_ADC3R_AD3TDC3_Pos (25U)\r
+#define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */\r
+#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */\r
+#define HRTIM_ADC3R_AD3TDC4_Pos (26U)\r
+#define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */\r
+#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */\r
+#define HRTIM_ADC3R_AD3TDPER_Pos (27U)\r
+#define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */\r
+#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */\r
+#define HRTIM_ADC3R_AD3TEC2_Pos (28U)\r
+#define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */\r
+#define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */\r
+#define HRTIM_ADC3R_AD3TEC3_Pos (29U)\r
+#define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */\r
+#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */\r
+#define HRTIM_ADC3R_AD3TEC4_Pos (30U)\r
+#define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */\r
+#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */\r
+#define HRTIM_ADC3R_AD3TEPER_Pos (31U)\r
+#define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */\r
+#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */\r
+\r
+/******************* Bit definition for HRTIM_ADC4R register ****************/\r
+#define HRTIM_ADC4R_AD4MC1_Pos (0U)\r
+#define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */\r
+#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */\r
+#define HRTIM_ADC4R_AD4MC2_Pos (1U)\r
+#define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */\r
+#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */\r
+#define HRTIM_ADC4R_AD4MC3_Pos (2U)\r
+#define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */\r
+#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */\r
+#define HRTIM_ADC4R_AD4MC4_Pos (3U)\r
+#define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */\r
+#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */\r
+#define HRTIM_ADC4R_AD4MPER_Pos (4U)\r
+#define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */\r
+#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */\r
+#define HRTIM_ADC4R_AD4EEV6_Pos (5U)\r
+#define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */\r
+#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */\r
+#define HRTIM_ADC4R_AD4EEV7_Pos (6U)\r
+#define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */\r
+#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */\r
+#define HRTIM_ADC4R_AD4EEV8_Pos (7U)\r
+#define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */\r
+#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */\r
+#define HRTIM_ADC4R_AD4EEV9_Pos (8U)\r
+#define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */\r
+#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */\r
+#define HRTIM_ADC4R_AD4EEV10_Pos (9U)\r
+#define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */\r
+#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */\r
+#define HRTIM_ADC4R_AD4TAC2_Pos (10U)\r
+#define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */\r
+#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */\r
+#define HRTIM_ADC4R_AD4TAC3_Pos (11U)\r
+#define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */\r
+#define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */\r
+#define HRTIM_ADC4R_AD4TAC4_Pos (12U)\r
+#define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */\r
+#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/\r
+#define HRTIM_ADC4R_AD4TAPER_Pos (13U)\r
+#define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */\r
+#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */\r
+#define HRTIM_ADC4R_AD4TBC2_Pos (14U)\r
+#define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */\r
+#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */\r
+#define HRTIM_ADC4R_AD4TBC3_Pos (15U)\r
+#define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */\r
+#define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */\r
+#define HRTIM_ADC4R_AD4TBC4_Pos (16U)\r
+#define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */\r
+#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */\r
+#define HRTIM_ADC4R_AD4TBPER_Pos (17U)\r
+#define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */\r
+#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */\r
+#define HRTIM_ADC4R_AD4TCC2_Pos (18U)\r
+#define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */\r
+#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */\r
+#define HRTIM_ADC4R_AD4TCC3_Pos (19U)\r
+#define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */\r
+#define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */\r
+#define HRTIM_ADC4R_AD4TCC4_Pos (20U)\r
+#define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */\r
+#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */\r
+#define HRTIM_ADC4R_AD4TCPER_Pos (21U)\r
+#define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */\r
+#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */\r
+#define HRTIM_ADC4R_AD4TCRST_Pos (22U)\r
+#define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */\r
+#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */\r
+#define HRTIM_ADC4R_AD4TDC2_Pos (23U)\r
+#define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */\r
+#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */\r
+#define HRTIM_ADC4R_AD4TDC3_Pos (24U)\r
+#define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */\r
+#define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */\r
+#define HRTIM_ADC4R_AD4TDC4_Pos (25U)\r
+#define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */\r
+#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/\r
+#define HRTIM_ADC4R_AD4TDPER_Pos (26U)\r
+#define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */\r
+#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */\r
+#define HRTIM_ADC4R_AD4TDRST_Pos (27U)\r
+#define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */\r
+#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */\r
+#define HRTIM_ADC4R_AD4TEC2_Pos (28U)\r
+#define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */\r
+#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */\r
+#define HRTIM_ADC4R_AD4TEC3_Pos (29U)\r
+#define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */\r
+#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */\r
+#define HRTIM_ADC4R_AD4TEC4_Pos (30U)\r
+#define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */\r
+#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */\r
+#define HRTIM_ADC4R_AD4TERST_Pos (31U)\r
+#define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */\r
+#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */\r
+\r
+/******************* Bit definition for HRTIM_FLTINR1 register ***************/\r
+#define HRTIM_FLTINR1_FLT1E_Pos (0U)\r
+#define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */\r
+#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */\r
+#define HRTIM_FLTINR1_FLT1P_Pos (1U)\r
+#define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */\r
+#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */\r
+#define HRTIM_FLTINR1_FLT1SRC_Pos (2U)\r
+#define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */\r
+#define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */\r
+#define HRTIM_FLTINR1_FLT1F_Pos (3U)\r
+#define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */\r
+#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */\r
+#define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */\r
+#define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */\r
+#define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */\r
+#define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */\r
+#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)\r
+#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */\r
+#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */\r
+\r
+#define HRTIM_FLTINR1_FLT2E_Pos (8U)\r
+#define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */\r
+#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */\r
+#define HRTIM_FLTINR1_FLT2P_Pos (9U)\r
+#define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */\r
+#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */\r
+#define HRTIM_FLTINR1_FLT2SRC_Pos (10U)\r
+#define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */\r
+#define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */\r
+#define HRTIM_FLTINR1_FLT2F_Pos (11U)\r
+#define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */\r
+#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */\r
+#define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */\r
+#define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */\r
+#define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */\r
+#define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */\r
+#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)\r
+#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */\r
+#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */\r
+\r
+#define HRTIM_FLTINR1_FLT3E_Pos (16U)\r
+#define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */\r
+#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */\r
+#define HRTIM_FLTINR1_FLT3P_Pos (17U)\r
+#define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */\r
+#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */\r
+#define HRTIM_FLTINR1_FLT3SRC_Pos (18U)\r
+#define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */\r
+#define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */\r
+#define HRTIM_FLTINR1_FLT3F_Pos (19U)\r
+#define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */\r
+#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */\r
+#define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */\r
+#define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */\r
+#define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */\r
+#define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */\r
+#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)\r
+#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */\r
+#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */\r
+\r
+#define HRTIM_FLTINR1_FLT4E_Pos (24U)\r
+#define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */\r
+#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */\r
+#define HRTIM_FLTINR1_FLT4P_Pos (25U)\r
+#define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */\r
+#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */\r
+#define HRTIM_FLTINR1_FLT4SRC_Pos (26U)\r
+#define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */\r
+#define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */\r
+#define HRTIM_FLTINR1_FLT4F_Pos (27U)\r
+#define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */\r
+#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */\r
+#define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */\r
+#define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */\r
+#define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */\r
+#define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */\r
+#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)\r
+#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */\r
+#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */\r
+\r
+/******************* Bit definition for HRTIM_FLTINR2 register ***************/\r
+#define HRTIM_FLTINR2_FLT5E_Pos (0U)\r
+#define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */\r
+#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */\r
+#define HRTIM_FLTINR2_FLT5P_Pos (1U)\r
+#define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */\r
+#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */\r
+#define HRTIM_FLTINR2_FLT5SRC_Pos (2U)\r
+#define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */\r
+#define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */\r
+#define HRTIM_FLTINR2_FLT5F_Pos (3U)\r
+#define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */\r
+#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */\r
+#define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */\r
+#define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */\r
+#define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */\r
+#define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */\r
+#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)\r
+#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */\r
+#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */\r
+#define HRTIM_FLTINR2_FLTSD_Pos (24U)\r
+#define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */\r
+#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */\r
+#define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */\r
+#define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */\r
+\r
+/******************* Bit definition for HRTIM_BDMUPR register ***************/\r
+#define HRTIM_BDMUPR_MCR_Pos (0U)\r
+#define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */\r
+#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */\r
+#define HRTIM_BDMUPR_MICR_Pos (1U)\r
+#define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */\r
+#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */\r
+#define HRTIM_BDMUPR_MDIER_Pos (2U)\r
+#define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */\r
+#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */\r
+#define HRTIM_BDMUPR_MCNT_Pos (3U)\r
+#define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */\r
+#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */\r
+#define HRTIM_BDMUPR_MPER_Pos (4U)\r
+#define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */\r
+#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */\r
+#define HRTIM_BDMUPR_MREP_Pos (5U)\r
+#define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */\r
+#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */\r
+#define HRTIM_BDMUPR_MCMP1_Pos (6U)\r
+#define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */\r
+#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */\r
+#define HRTIM_BDMUPR_MCMP2_Pos (7U)\r
+#define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */\r
+#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */\r
+#define HRTIM_BDMUPR_MCMP3_Pos (8U)\r
+#define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */\r
+#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */\r
+#define HRTIM_BDMUPR_MCMP4_Pos (9U)\r
+#define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */\r
+#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */\r
+\r
+/******************* Bit definition for HRTIM_BDTUPR register ***************/\r
+#define HRTIM_BDTUPR_TIMCR_Pos (0U)\r
+#define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */\r
+#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */\r
+#define HRTIM_BDTUPR_TIMICR_Pos (1U)\r
+#define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */\r
+#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */\r
+#define HRTIM_BDTUPR_TIMDIER_Pos (2U)\r
+#define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */\r
+#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */\r
+#define HRTIM_BDTUPR_TIMCNT_Pos (3U)\r
+#define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */\r
+#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */\r
+#define HRTIM_BDTUPR_TIMPER_Pos (4U)\r
+#define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */\r
+#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */\r
+#define HRTIM_BDTUPR_TIMREP_Pos (5U)\r
+#define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */\r
+#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */\r
+#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)\r
+#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */\r
+#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */\r
+#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)\r
+#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */\r
+#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */\r
+#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)\r
+#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */\r
+#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */\r
+#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)\r
+#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */\r
+#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */\r
+#define HRTIM_BDTUPR_TIMDTR_Pos (10U)\r
+#define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */\r
+#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */\r
+#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)\r
+#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */\r
+#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */\r
+#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)\r
+#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */\r
+#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */\r
+#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)\r
+#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */\r
+#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */\r
+#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)\r
+#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */\r
+#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */\r
+#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)\r
+#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */\r
+#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */\r
+#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)\r
+#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */\r
+#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */\r
+#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)\r
+#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */\r
+#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */\r
+#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)\r
+#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */\r
+#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */\r
+#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)\r
+#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */\r
+#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */\r
+#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)\r
+#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */\r
+#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */\r
+\r
+/******************* Bit definition for HRTIM_BDMADR register ***************/\r
+#define HRTIM_BDMADR_BDMADR_Pos (0U)\r
+#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */\r
+#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RAM ECC monitoring */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for RAMECC_IER register ******************/\r
+#define RAMECC_IER_GECCDEBWIE_Pos (3U)\r
+#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */\r
+#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */\r
+#define RAMECC_IER_GECCDEIE_Pos (2U)\r
+#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */\r
+#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */\r
+#define RAMECC_IER_GECCSEIE_Pos (1U)\r
+#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */\r
+#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */\r
+#define RAMECC_IER_GIE_Pos (0U)\r
+#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */\r
+#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */\r
+\r
+/******************* Bit definition for RAMECC_CR register ******************/\r
+#define RAMECC_CR_ECCELEN_Pos (5U)\r
+#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */\r
+#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */\r
+#define RAMECC_CR_ECCDEBWIE_Pos (4U)\r
+#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */\r
+#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */\r
+#define RAMECC_CR_ECCDEIE_Pos (3U)\r
+#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */\r
+#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */\r
+#define RAMECC_CR_ECCSEIE_Pos (2U)\r
+#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */\r
+#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */\r
+\r
+/******************* Bit definition for RAMECC_SR register ******************/\r
+#define RAMECC_SR_DEBWDF_Pos (2U)\r
+#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */\r
+#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */\r
+#define RAMECC_SR_DEDF_Pos (1U)\r
+#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */\r
+#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */\r
+#define RAMECC_SR_SEDCF_Pos (0U)\r
+#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */\r
+#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */\r
+\r
+/****************** Bit definition for RAMECC_FAR register ******************/\r
+#define RAMECC_FAR_FADD_Pos (0U)\r
+#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */\r
+#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */\r
+\r
+/****************** Bit definition for RAMECC_FDRL register *****************/\r
+#define RAMECC_FAR_FDATAL_Pos (0U)\r
+#define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */\r
+#define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */\r
+\r
+/****************** Bit definition for RAMECC_FDRH register *****************/\r
+#define RAMECC_FAR_FDATAH_Pos (0U)\r
+#define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */\r
+#define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */\r
+\r
+/***************** Bit definition for RAMECC_FECR register ******************/\r
+#define RAMECC_FECR_FEC_Pos (0U)\r
+#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */\r
+#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* MDIOS */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for MDIOS_CR register *******************/\r
+#define MDIOS_CR_EN_Pos (0U)\r
+#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */\r
+#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */\r
+#define MDIOS_CR_WRIE_Pos (1U)\r
+#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */\r
+#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */\r
+#define MDIOS_CR_RDIE_Pos (2U)\r
+#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */\r
+#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */\r
+#define MDIOS_CR_EIE_Pos (3U)\r
+#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */\r
+#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */\r
+#define MDIOS_CR_DPC_Pos (7U)\r
+#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */\r
+#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */\r
+#define MDIOS_CR_PORT_ADDRESS_Pos (8U)\r
+#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */\r
+#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */\r
+#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */\r
+#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */\r
+#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */\r
+#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */\r
+#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */\r
+\r
+/******************** Bit definition for MDIOS_SR register *******************/\r
+#define MDIOS_SR_PERF_Pos (0U)\r
+#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */\r
+#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/\r
+#define MDIOS_SR_SERF_Pos (1U)\r
+#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */\r
+#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */\r
+#define MDIOS_SR_TERF_Pos (2U)\r
+#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */\r
+#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */\r
+\r
+/******************** Bit definition for MDIOS_CLRFR register *******************/\r
+#define MDIOS_SR_CPERF_Pos (0U)\r
+#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */\r
+#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */\r
+#define MDIOS_SR_CSERF_Pos (1U)\r
+#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */\r
+#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */\r
+#define MDIOS_SR_CTERF_Pos (2U)\r
+#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */\r
+#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* USB_OTG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/\r
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)\r
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */\r
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)\r
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */\r
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)\r
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)\r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)\r
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)\r
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)\r
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)\r
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)\r
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)\r
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */\r
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)\r
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)\r
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */\r
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)\r
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */\r
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)\r
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */\r
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)\r
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */\r
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)\r
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */\r
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)\r
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */\r
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)\r
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */\r
+\r
+/******************** Bit definition forUSB_OTG_HCFG register ********************/\r
+\r
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)\r
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */\r
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCFG_FSLSS_Pos (2U)\r
+#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */\r
+\r
+/******************** Bit definition forUSB_OTG_DCFG register ********************/\r
+\r
+#define USB_OTG_DCFG_DSPD_Pos (0U)\r
+#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */\r
+#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)\r
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */\r
+\r
+#define USB_OTG_DCFG_DAD_Pos (4U)\r
+#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */\r
+#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_OTG_DCFG_PFIVL_Pos (11U)\r
+#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */\r
+#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r
+\r
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)\r
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */\r
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r
+\r
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/\r
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)\r
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */\r
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)\r
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */\r
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)\r
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */\r
+\r
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/\r
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)\r
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */\r
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)\r
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */\r
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)\r
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */\r
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)\r
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */\r
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)\r
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */\r
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)\r
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */\r
+\r
+/******************** Bit definition forUSB_OTG_DCTL register ********************/\r
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)\r
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */\r
+#define USB_OTG_DCTL_SDIS_Pos (1U)\r
+#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */\r
+#define USB_OTG_DCTL_GINSTS_Pos (2U)\r
+#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */\r
+#define USB_OTG_DCTL_GONSTS_Pos (3U)\r
+#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */\r
+\r
+#define USB_OTG_DCTL_TCTL_Pos (4U)\r
+#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */\r
+#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCTL_SGINAK_Pos (7U)\r
+#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */\r
+#define USB_OTG_DCTL_CGINAK_Pos (8U)\r
+#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */\r
+#define USB_OTG_DCTL_SGONAK_Pos (9U)\r
+#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */\r
+#define USB_OTG_DCTL_CGONAK_Pos (10U)\r
+#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */\r
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)\r
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */\r
+\r
+/******************** Bit definition forUSB_OTG_HFIR register ********************/\r
+#define USB_OTG_HFIR_FRIVL_Pos (0U)\r
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */\r
+\r
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/\r
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)\r
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */\r
+#define USB_OTG_HFNUM_FTREM_Pos (16U)\r
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */\r
+\r
+/******************** Bit definition forUSB_OTG_DSTS register ********************/\r
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)\r
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */\r
+\r
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)\r
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */\r
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DSTS_EERR_Pos (3U)\r
+#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */\r
+#define USB_OTG_DSTS_FNSOF_Pos (8U)\r
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */\r
+\r
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/\r
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)\r
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */\r
+\r
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)\r
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)\r
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */\r
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)\r
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */\r
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)\r
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */\r
+\r
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/\r
+\r
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)\r
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */\r
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)\r
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)\r
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */\r
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)\r
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */\r
+\r
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)\r
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */\r
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)\r
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)\r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */\r
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)\r
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */\r
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)\r
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */\r
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)\r
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */\r
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)\r
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */\r
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)\r
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */\r
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)\r
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */\r
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)\r
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */\r
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)\r
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */\r
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)\r
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */\r
+\r
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/\r
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)\r
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */\r
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)\r
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */\r
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)\r
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */\r
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)\r
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)\r
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */\r
+\r
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)\r
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */\r
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)\r
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */\r
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)\r
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/\r
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)\r
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)\r
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)\r
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)\r
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)\r
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)\r
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)\r
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/\r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)\r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)\r
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)\r
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition forUSB_OTG_HAINT register ********************/\r
+#define USB_OTG_HAINT_HAINT_Pos (0U)\r
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/\r
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)\r
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)\r
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)\r
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */\r
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)\r
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */\r
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)\r
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */\r
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)\r
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */\r
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)\r
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)\r
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/\r
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)\r
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */\r
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)\r
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */\r
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)\r
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */\r
+#define USB_OTG_GINTSTS_SOF_Pos (3U)\r
+#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */\r
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)\r
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */\r
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)\r
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)\r
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */\r
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)\r
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */\r
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)\r
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */\r
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)\r
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */\r
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)\r
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */\r
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)\r
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */\r
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)\r
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */\r
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)\r
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */\r
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)\r
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */\r
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)\r
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */\r
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)\r
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */\r
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)\r
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */\r
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)\r
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */\r
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)\r
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */\r
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)\r
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)\r
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */\r
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)\r
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */\r
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)\r
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */\r
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)\r
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */\r
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)\r
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/\r
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)\r
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)\r
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */\r
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)\r
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */\r
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)\r
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */\r
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)\r
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)\r
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */\r
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)\r
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */\r
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)\r
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */\r
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)\r
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */\r
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)\r
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */\r
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)\r
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */\r
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)\r
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */\r
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)\r
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */\r
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)\r
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)\r
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)\r
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)\r
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */\r
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)\r
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */\r
+#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)\r
+#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */\r
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)\r
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */\r
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)\r
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */\r
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)\r
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)\r
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */\r
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)\r
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */\r
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)\r
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */\r
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)\r
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */\r
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)\r
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_DAINT register ********************/\r
+#define USB_OTG_DAINT_IEPINT_Pos (0U)\r
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */\r
+#define USB_OTG_DAINT_OEPINT_Pos (16U)\r
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */\r
+\r
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/\r
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)\r
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)\r
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)\r
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)\r
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)\r
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/\r
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)\r
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)\r
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM_Pos (0U)\r
+#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_BCNT_Pos (4U)\r
+#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */\r
+\r
+#define USB_OTG_DPID_Pos (15U)\r
+#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */\r
+#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_PKTSTS_Pos (17U)\r
+#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */\r
+\r
+#define USB_OTG_EPNUM_Pos (0U)\r
+#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */\r
+\r
+#define USB_OTG_FRMNUM_Pos (21U)\r
+#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */\r
+\r
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/\r
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)\r
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/\r
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)\r
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+#define USB_OTG_NPTXFSA_Pos (0U)\r
+#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */\r
+#define USB_OTG_NPTXFD_Pos (16U)\r
+#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */\r
+#define USB_OTG_TX0FSA_Pos (0U)\r
+#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */\r
+#define USB_OTG_TX0FD_Pos (16U)\r
+#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/\r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)\r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r
+\r
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/\r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)\r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)\r
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)\r
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)\r
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r
+\r
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/\r
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)\r
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */\r
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)\r
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */\r
+\r
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/\r
+#define USB_OTG_GCCFG_DCDET_Pos (0U)\r
+#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */\r
+#define USB_OTG_GCCFG_PDET_Pos (1U)\r
+#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */\r
+#define USB_OTG_GCCFG_SDET_Pos (2U)\r
+#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */\r
+#define USB_OTG_GCCFG_PS2DET_Pos (3U)\r
+#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */\r
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)\r
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */\r
+#define USB_OTG_GCCFG_BCDEN_Pos (17U)\r
+#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */\r
+#define USB_OTG_GCCFG_DCDEN_Pos (18U)\r
+#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/\r
+#define USB_OTG_GCCFG_PDEN_Pos (19U)\r
+#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/\r
+#define USB_OTG_GCCFG_SDEN_Pos (20U)\r
+#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */\r
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)\r
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */\r
+\r
+/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/\r
+#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)\r
+#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */\r
+#define USB_OTG_GPWRDN_ADPIF_Pos (23U)\r
+#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */\r
+\r
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r
+\r
+/******************** Bit definition forUSB_OTG_CID register ********************/\r
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)\r
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */\r
+\r
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)\r
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */\r
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)\r
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */\r
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)\r
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)\r
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)\r
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */\r
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)\r
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */\r
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)\r
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */\r
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)\r
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */\r
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)\r
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */\r
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)\r
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)\r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */\r
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)\r
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */\r
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)\r
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */\r
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)\r
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)\r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)\r
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)\r
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)\r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPRT register ********************/\r
+#define USB_OTG_HPRT_PCSTS_Pos (0U)\r
+#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */\r
+#define USB_OTG_HPRT_PCDET_Pos (1U)\r
+#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */\r
+#define USB_OTG_HPRT_PENA_Pos (2U)\r
+#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */\r
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)\r
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */\r
+#define USB_OTG_HPRT_POCA_Pos (4U)\r
+#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */\r
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)\r
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */\r
+#define USB_OTG_HPRT_PRES_Pos (6U)\r
+#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */\r
+#define USB_OTG_HPRT_PSUSP_Pos (7U)\r
+#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */\r
+#define USB_OTG_HPRT_PRST_Pos (8U)\r
+#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */\r
+\r
+#define USB_OTG_HPRT_PLSTS_Pos (10U)\r
+#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */\r
+#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HPRT_PPWR_Pos (12U)\r
+#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */\r
+\r
+#define USB_OTG_HPRT_PTCTL_Pos (13U)\r
+#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */\r
+#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_HPRT_PSPD_Pos (17U)\r
+#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */\r
+#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)\r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)\r
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)\r
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)\r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)\r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)\r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/\r
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)\r
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */\r
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)\r
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/\r
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)\r
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */\r
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)\r
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)\r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\r
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)\r
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */\r
+\r
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)\r
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)\r
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */\r
+\r
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)\r
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */\r
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)\r
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */\r
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)\r
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)\r
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */\r
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)\r
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */\r
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)\r
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/\r
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)\r
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */\r
+\r
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)\r
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */\r
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)\r
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */\r
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)\r
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */\r
+\r
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)\r
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r
+\r
+#define USB_OTG_HCCHAR_MC_Pos (20U)\r
+#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */\r
+#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r
+\r
+#define USB_OTG_HCCHAR_DAD_Pos (22U)\r
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */\r
+#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)\r
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */\r
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)\r
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */\r
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)\r
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/\r
+\r
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)\r
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */\r
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r
+\r
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)\r
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */\r
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)\r
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */\r
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)\r
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */\r
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)\r
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCINT register ********************/\r
+#define USB_OTG_HCINT_XFRC_Pos (0U)\r
+#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */\r
+#define USB_OTG_HCINT_CHH_Pos (1U)\r
+#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */\r
+#define USB_OTG_HCINT_AHBERR_Pos (2U)\r
+#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */\r
+#define USB_OTG_HCINT_STALL_Pos (3U)\r
+#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */\r
+#define USB_OTG_HCINT_NAK_Pos (4U)\r
+#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */\r
+#define USB_OTG_HCINT_ACK_Pos (5U)\r
+#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */\r
+#define USB_OTG_HCINT_NYET_Pos (6U)\r
+#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */\r
+#define USB_OTG_HCINT_TXERR_Pos (7U)\r
+#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */\r
+#define USB_OTG_HCINT_BBERR_Pos (8U)\r
+#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */\r
+#define USB_OTG_HCINT_FRMOR_Pos (9U)\r
+#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */\r
+#define USB_OTG_HCINT_DTERR_Pos (10U)\r
+#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/\r
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)\r
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */\r
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)\r
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DIEPINT_TOC_Pos (3U)\r
+#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */\r
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)\r
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */\r
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)\r
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */\r
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)\r
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r
+#define USB_OTG_DIEPINT_BNA_Pos (9U)\r
+#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)\r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r
+#define USB_OTG_DIEPINT_BERR_Pos (12U)\r
+#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */\r
+#define USB_OTG_DIEPINT_NAK_Pos (13U)\r
+#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/\r
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)\r
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */\r
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)\r
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */\r
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)\r
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */\r
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)\r
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)\r
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)\r
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */\r
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)\r
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)\r
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */\r
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)\r
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */\r
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)\r
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */\r
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)\r
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)\r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */\r
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)\r
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */\r
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/\r
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)\r
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)\r
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */\r
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)\r
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */\r
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)\r
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */\r
+#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/\r
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)\r
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */\r
+\r
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/\r
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)\r
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */\r
+\r
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/\r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)\r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/\r
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)\r
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */\r
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)\r
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/\r
+\r
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)\r
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)\r
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */\r
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)\r
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)\r
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */\r
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)\r
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)\r
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */\r
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)\r
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */\r
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)\r
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */\r
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)\r
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */\r
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)\r
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */\r
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)\r
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/\r
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)\r
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */\r
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)\r
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DOEPINT_STUP_Pos (3U)\r
+#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */\r
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)\r
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */\r
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)\r
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */\r
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)\r
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */\r
+#define USB_OTG_DOEPINT_NYET_Pos (14U)\r
+#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)\r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */\r
+\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for PCGCCTL register ********************/\r
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)\r
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */\r
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)\r
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)\r
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+\r
+/******************************* ADC Instances ********************************/\r
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\r
+ ((INSTANCE) == ADC2) || \\r
+ ((INSTANCE) == ADC3))\r
+\r
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r
+\r
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\\r
+ ((INSTANCE) == ADC3_COMMON))\r
+\r
+/******************************** COMP Instances ******************************/\r
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\r
+ ((INSTANCE) == COMP2))\r
+\r
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)\r
+/******************** COMP Instances with window mode capability **************/\r
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)\r
+\r
+\r
+/******************************* CRC Instances ********************************/\r
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\r
+\r
+/******************************* DAC Instances ********************************/\r
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\r
+/******************************* DCMI Instances *******************************/\r
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r
+\r
+/******************************* DELAYBLOCK Instances *******************************/\r
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \\r
+ ((INSTANCE) == DLYB_SDMMC2) || \\r
+ ((INSTANCE) == DLYB_QUADSPI))\r
+/****************************** DFSDM Instances *******************************/\r
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\r
+ ((INSTANCE) == DFSDM1_Filter1) || \\r
+ ((INSTANCE) == DFSDM1_Filter2) || \\r
+ ((INSTANCE) == DFSDM1_Filter3))\r
+\r
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\r
+ ((INSTANCE) == DFSDM1_Channel1) || \\r
+ ((INSTANCE) == DFSDM1_Channel2) || \\r
+ ((INSTANCE) == DFSDM1_Channel3) || \\r
+ ((INSTANCE) == DFSDM1_Channel4) || \\r
+ ((INSTANCE) == DFSDM1_Channel5) || \\r
+ ((INSTANCE) == DFSDM1_Channel6) || \\r
+ ((INSTANCE) == DFSDM1_Channel7))\r
+/****************************** RAMECC Instances ******************************/\r
+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \\r
+ ((INSTANCE) == RAMECC1_Monitor2) || \\r
+ ((INSTANCE) == RAMECC1_Monitor3) || \\r
+ ((INSTANCE) == RAMECC1_Monitor4) || \\r
+ ((INSTANCE) == RAMECC1_Monitor5) || \\r
+ ((INSTANCE) == RAMECC2_Monitor1) || \\r
+ ((INSTANCE) == RAMECC2_Monitor2) || \\r
+ ((INSTANCE) == RAMECC2_Monitor3) || \\r
+ ((INSTANCE) == RAMECC2_Monitor4) || \\r
+ ((INSTANCE) == RAMECC2_Monitor5) || \\r
+ ((INSTANCE) == RAMECC3_Monitor1) || \\r
+ ((INSTANCE) == RAMECC3_Monitor2))\r
+\r
+/******************************** DMA Instances *******************************/\r
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\r
+ ((INSTANCE) == DMA1_Stream1) || \\r
+ ((INSTANCE) == DMA1_Stream2) || \\r
+ ((INSTANCE) == DMA1_Stream3) || \\r
+ ((INSTANCE) == DMA1_Stream4) || \\r
+ ((INSTANCE) == DMA1_Stream5) || \\r
+ ((INSTANCE) == DMA1_Stream6) || \\r
+ ((INSTANCE) == DMA1_Stream7) || \\r
+ ((INSTANCE) == DMA2_Stream0) || \\r
+ ((INSTANCE) == DMA2_Stream1) || \\r
+ ((INSTANCE) == DMA2_Stream2) || \\r
+ ((INSTANCE) == DMA2_Stream3) || \\r
+ ((INSTANCE) == DMA2_Stream4) || \\r
+ ((INSTANCE) == DMA2_Stream5) || \\r
+ ((INSTANCE) == DMA2_Stream6) || \\r
+ ((INSTANCE) == DMA2_Stream7) || \\r
+ ((INSTANCE) == BDMA_Channel0) || \\r
+ ((INSTANCE) == BDMA_Channel1) || \\r
+ ((INSTANCE) == BDMA_Channel2) || \\r
+ ((INSTANCE) == BDMA_Channel3) || \\r
+ ((INSTANCE) == BDMA_Channel4) || \\r
+ ((INSTANCE) == BDMA_Channel5) || \\r
+ ((INSTANCE) == BDMA_Channel6) || \\r
+ ((INSTANCE) == BDMA_Channel7))\r
+\r
+/****************************** BDMA CHANNEL Instances ***************************/\r
+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \\r
+ ((INSTANCE) == BDMA_Channel1) || \\r
+ ((INSTANCE) == BDMA_Channel2) || \\r
+ ((INSTANCE) == BDMA_Channel3) || \\r
+ ((INSTANCE) == BDMA_Channel4) || \\r
+ ((INSTANCE) == BDMA_Channel5) || \\r
+ ((INSTANCE) == BDMA_Channel6) || \\r
+ ((INSTANCE) == BDMA_Channel7))\r
+\r
+/****************************** DMA DMAMUX ALL Instances ***************************/\r
+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\r
+ ((INSTANCE) == DMA1_Stream1) || \\r
+ ((INSTANCE) == DMA1_Stream2) || \\r
+ ((INSTANCE) == DMA1_Stream3) || \\r
+ ((INSTANCE) == DMA1_Stream4) || \\r
+ ((INSTANCE) == DMA1_Stream5) || \\r
+ ((INSTANCE) == DMA1_Stream6) || \\r
+ ((INSTANCE) == DMA1_Stream7) || \\r
+ ((INSTANCE) == DMA2_Stream0) || \\r
+ ((INSTANCE) == DMA2_Stream1) || \\r
+ ((INSTANCE) == DMA2_Stream2) || \\r
+ ((INSTANCE) == DMA2_Stream3) || \\r
+ ((INSTANCE) == DMA2_Stream4) || \\r
+ ((INSTANCE) == DMA2_Stream5) || \\r
+ ((INSTANCE) == DMA2_Stream6) || \\r
+ ((INSTANCE) == DMA2_Stream7) || \\r
+ ((INSTANCE) == BDMA_Channel0) || \\r
+ ((INSTANCE) == BDMA_Channel1) || \\r
+ ((INSTANCE) == BDMA_Channel2) || \\r
+ ((INSTANCE) == BDMA_Channel3) || \\r
+ ((INSTANCE) == BDMA_Channel4) || \\r
+ ((INSTANCE) == BDMA_Channel5) || \\r
+ ((INSTANCE) == BDMA_Channel6) || \\r
+ ((INSTANCE) == BDMA_Channel7))\r
+\r
+/****************************** BDMA DMAMUX Instances ***************************/\r
+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \\r
+ ((INSTANCE) == BDMA_Channel1) || \\r
+ ((INSTANCE) == BDMA_Channel2) || \\r
+ ((INSTANCE) == BDMA_Channel3) || \\r
+ ((INSTANCE) == BDMA_Channel4) || \\r
+ ((INSTANCE) == BDMA_Channel5) || \\r
+ ((INSTANCE) == BDMA_Channel6) || \\r
+ ((INSTANCE) == BDMA_Channel7))\r
+\r
+/****************************** DMA STREAM Instances ***************************/\r
+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\r
+ ((INSTANCE) == DMA1_Stream1) || \\r
+ ((INSTANCE) == DMA1_Stream2) || \\r
+ ((INSTANCE) == DMA1_Stream3) || \\r
+ ((INSTANCE) == DMA1_Stream4) || \\r
+ ((INSTANCE) == DMA1_Stream5) || \\r
+ ((INSTANCE) == DMA1_Stream6) || \\r
+ ((INSTANCE) == DMA1_Stream7) || \\r
+ ((INSTANCE) == DMA2_Stream0) || \\r
+ ((INSTANCE) == DMA2_Stream1) || \\r
+ ((INSTANCE) == DMA2_Stream2) || \\r
+ ((INSTANCE) == DMA2_Stream3) || \\r
+ ((INSTANCE) == DMA2_Stream4) || \\r
+ ((INSTANCE) == DMA2_Stream5) || \\r
+ ((INSTANCE) == DMA2_Stream6) || \\r
+ ((INSTANCE) == DMA2_Stream7))\r
+\r
+/****************************** DMA DMAMUX Instances ***************************/\r
+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\r
+ ((INSTANCE) == DMA1_Stream1) || \\r
+ ((INSTANCE) == DMA1_Stream2) || \\r
+ ((INSTANCE) == DMA1_Stream3) || \\r
+ ((INSTANCE) == DMA1_Stream4) || \\r
+ ((INSTANCE) == DMA1_Stream5) || \\r
+ ((INSTANCE) == DMA1_Stream6) || \\r
+ ((INSTANCE) == DMA1_Stream7) || \\r
+ ((INSTANCE) == DMA2_Stream0) || \\r
+ ((INSTANCE) == DMA2_Stream1) || \\r
+ ((INSTANCE) == DMA2_Stream2) || \\r
+ ((INSTANCE) == DMA2_Stream3) || \\r
+ ((INSTANCE) == DMA2_Stream4) || \\r
+ ((INSTANCE) == DMA2_Stream5) || \\r
+ ((INSTANCE) == DMA2_Stream6) || \\r
+ ((INSTANCE) == DMA2_Stream7))\r
+\r
+/******************************** DMA Request Generator Instances **************/\r
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \\r
+ ((INSTANCE) == DMAMUX1_RequestGenerator1) || \\r
+ ((INSTANCE) == DMAMUX1_RequestGenerator2) || \\r
+ ((INSTANCE) == DMAMUX1_RequestGenerator3) || \\r
+ ((INSTANCE) == DMAMUX1_RequestGenerator4) || \\r
+ ((INSTANCE) == DMAMUX1_RequestGenerator5) || \\r
+ ((INSTANCE) == DMAMUX1_RequestGenerator6) || \\r
+ ((INSTANCE) == DMAMUX1_RequestGenerator7) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator0) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator1) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator2) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator3) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator4) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator5) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator6) || \\r
+ ((INSTANCE) == DMAMUX2_RequestGenerator7))\r
+\r
+/******************************* DMA2D Instances *******************************/\r
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r
+\r
+/******************************** MDMA Request Generator Instances **************/\r
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \\r
+ ((INSTANCE) == MDMA_Channel1) || \\r
+ ((INSTANCE) == MDMA_Channel2) || \\r
+ ((INSTANCE) == MDMA_Channel3) || \\r
+ ((INSTANCE) == MDMA_Channel4) || \\r
+ ((INSTANCE) == MDMA_Channel5) || \\r
+ ((INSTANCE) == MDMA_Channel6) || \\r
+ ((INSTANCE) == MDMA_Channel7) || \\r
+ ((INSTANCE) == MDMA_Channel8) || \\r
+ ((INSTANCE) == MDMA_Channel9) || \\r
+ ((INSTANCE) == MDMA_Channel10) || \\r
+ ((INSTANCE) == MDMA_Channel11) || \\r
+ ((INSTANCE) == MDMA_Channel12) || \\r
+ ((INSTANCE) == MDMA_Channel13) || \\r
+ ((INSTANCE) == MDMA_Channel14) || \\r
+ ((INSTANCE) == MDMA_Channel15))\r
+\r
+/******************************* QUADSPI Instances *******************************/\r
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r
+\r
+/******************************* FDCAN Instances ******************************/\r
+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \\r
+ ((__INSTANCE__) == FDCAN2))\r
+\r
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\r
+ ((INSTANCE) == GPIOB) || \\r
+ ((INSTANCE) == GPIOC) || \\r
+ ((INSTANCE) == GPIOD) || \\r
+ ((INSTANCE) == GPIOE) || \\r
+ ((INSTANCE) == GPIOF) || \\r
+ ((INSTANCE) == GPIOG) || \\r
+ ((INSTANCE) == GPIOH) || \\r
+ ((INSTANCE) == GPIOI) || \\r
+ ((INSTANCE) == GPIOJ) || \\r
+ ((INSTANCE) == GPIOK))\r
+\r
+/******************************* GPIO AF Instances ****************************/\r
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
+\r
+/**************************** GPIO Lock Instances *****************************/\r
+/* On H7, all GPIO Bank support the Lock mechanism */\r
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r
+\r
+/******************************** HSEM Instances *******************************/\r
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)\r
+/******************** Bit definition for HSEM_CR register *****************/\r
+#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */\r
+#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */\r
+#if defined(CORE_CM4)\r
+#define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)\r
+#else /* CORE_CM7 */\r
+#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)\r
+#endif /* CORE_CM4 */\r
+\r
+#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/\r
+#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */\r
+\r
+#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */\r
+#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */\r
+\r
+#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */\r
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */\r
+\r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
+ ((INSTANCE) == I2C2) || \\r
+ ((INSTANCE) == I2C3) || \\r
+ ((INSTANCE) == I2C4))\r
+/************** I2C Instances : wakeup capability from stop modes *************/\r
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\r
+\r
+/****************************** SMBUS Instances *******************************/\r
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\r
+ ((INSTANCE) == I2C2) || \\r
+ ((INSTANCE) == I2C3) || \\r
+ ((INSTANCE) == I2C4))\r
+/******************************** I2S Instances *******************************/\r
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\r
+ ((INSTANCE) == SPI2) || \\r
+ ((INSTANCE) == SPI3))\r
+\r
+/****************************** LTDC Instances ********************************/\r
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)\r
+\r
+/******************************* RNG Instances ********************************/\r
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)\r
+\r
+/****************************** SDMMC Instances *********************************/\r
+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \\r
+ ((_INSTANCE_) == SDMMC2))\r
+\r
+/******************************** SMBUS Instances *****************************/\r
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)\r
+\r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\r
+ ((INSTANCE) == SPI2) || \\r
+ ((INSTANCE) == SPI3) || \\r
+ ((INSTANCE) == SPI4) || \\r
+ ((INSTANCE) == SPI5) || \\r
+ ((INSTANCE) == SPI6))\r
+\r
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\r
+ ((INSTANCE) == SPI2) || \\r
+ ((INSTANCE) == SPI3))\r
+\r
+/******************************** SWPMI Instances *****************************/\r
+#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)\r
+\r
+/****************** LPTIM Instances : All supported instances *****************/\r
+#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \\r
+ ((INSTANCE) == LPTIM2) || \\r
+ ((INSTANCE) == LPTIM3) || \\r
+ ((INSTANCE) == LPTIM4) || \\r
+ ((INSTANCE) == LPTIM5))\r
+\r
+/****************** LPTIM Instances : supporting encoder interface **************/\r
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \\r
+ ((INSTANCE) == LPTIM2))\r
+\r
+/****************** TIM Instances : All supported instances *******************/\r
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM6) || \\r
+ ((INSTANCE) == TIM7) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM12) || \\r
+ ((INSTANCE) == TIM13) || \\r
+ ((INSTANCE) == TIM14) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+/************* TIM Instances : at least 1 capture/compare channel *************/\r
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM12) || \\r
+ ((INSTANCE) == TIM13) || \\r
+ ((INSTANCE) == TIM14) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+/************ TIM Instances : at least 2 capture/compare channels *************/\r
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM12) || \\r
+ ((INSTANCE) == TIM15))\r
+/************ TIM Instances : at least 3 capture/compare channels *************/\r
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/************ TIM Instances : at least 4 capture/compare channels *************/\r
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+/************ TIM Instances : at least 5 capture/compare channels *************/\r
+#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+/************ TIM Instances : at least 6 capture/compare channels *************/\r
+#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/******************** TIM Instances : Advanced-control timers *****************/\r
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************** TIM Instances : Advanced-control timers *****************/\r
+\r
+/******************* TIM Instances : Timer input XOR function *****************/\r
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15))\r
+\r
+/****************** TIM Instances : DMA requests generation (UDE) *************/\r
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM6) || \\r
+ ((INSTANCE) == TIM7) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+\r
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+\r
+/************ TIM Instances : DMA requests generation (COMDE) *****************/\r
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15))\r
+\r
+/******************** TIM Instances : DMA burst feature ***********************/\r
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/*************** TIM Instances : external trigger reamp input available *******/\r
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+/****************** TIM Instances : remapping capability **********************/\r
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM16) || \\r
+ ((__INSTANCE__) == TIM17))\r
+\r
+/*************** TIM Instances : external trigger reamp input available *******/\r
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM6) || \\r
+ ((INSTANCE) == TIM7) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15))\r
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/\r
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM12))\r
+\r
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/\r
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/\r
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting commutation event *************/\r
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting encoder interface **************/\r
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/\r
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+/******************* TIM Instances : output(s) available **********************/\r
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\r
+ ((((INSTANCE) == TIM1) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4) || \\r
+ ((CHANNEL) == TIM_CHANNEL_5) || \\r
+ ((CHANNEL) == TIM_CHANNEL_6))) \\r
+ || \\r
+ (((INSTANCE) == TIM2) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM3) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1)|| \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM4) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM5) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((INSTANCE) == TIM8) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4) || \\r
+ ((CHANNEL) == TIM_CHANNEL_5) || \\r
+ ((CHANNEL) == TIM_CHANNEL_6))) \\r
+ || \\r
+ (((INSTANCE) == TIM12) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((INSTANCE) == TIM13) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((INSTANCE) == TIM14) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((INSTANCE) == TIM15) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((INSTANCE) == TIM16) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((INSTANCE) == TIM17) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1))))\r
+\r
+/****************** TIM Instances : supporting the break function *************/\r
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+\r
+/************** TIM Instances : supporting Break source selection *************/\r
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting complementary output(s) ********/\r
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\r
+ ((((INSTANCE) == TIM1) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3))) \\r
+ || \\r
+ (((INSTANCE) == TIM8) && \\r
+ (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3))) \\r
+ || \\r
+ (((INSTANCE) == TIM15) && \\r
+ ((CHANNEL) == TIM_CHANNEL_1)) \\r
+ || \\r
+ (((INSTANCE) == TIM16) && \\r
+ ((CHANNEL) == TIM_CHANNEL_1)) \\r
+ || \\r
+ (((INSTANCE) == TIM17) && \\r
+ ((CHANNEL) == TIM_CHANNEL_1)))\r
+\r
+/****************** TIM Instances : supporting counting mode selection ********/\r
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting repetition counter *************/\r
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+\r
+/****************** TIM Instances : supporting synchronization ****************/\r
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM15))\r
+\r
+/****************** TIM Instances : supporting clock division *****************/\r
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15) || \\r
+ ((INSTANCE) == TIM16) || \\r
+ ((INSTANCE) == TIM17))\r
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting external clock mode 2 **********/\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8))\r
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15))\r
+\r
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3) || \\r
+ ((INSTANCE) == TIM4) || \\r
+ ((INSTANCE) == TIM5) || \\r
+ ((INSTANCE) == TIM8) || \\r
+ ((INSTANCE) == TIM15))\r
+\r
+/****************** TIM Instances : supporting OCxREF clear *******************/\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM3))\r
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/\r
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM2) || \\r
+ ((INSTANCE) == TIM5))\r
+\r
+/****************** TIM Instances : TIM_BKIN2 ***************************/\r
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\\r
+ (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting Hall sensor interface **********/\r
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM15) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************************** HRTIM Instances *******************************/\r
+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))\r
+\r
+/******************** USART Instances : Synchronous mode **********************/\r
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == USART6))\r
+\r
+/******************** USART Instances : SPI slave mode ************************/\r
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == USART6))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8))\r
+\r
+/******************** UART Instances : FIFO mode.******************************/\r
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8))\r
+\r
+/****************** UART Instances : Auto Baud Rate detection *****************/\r
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8))\r
+\r
+/*********************** UART Instances : Driver Enable ***********************/\r
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8) || \\r
+ ((INSTANCE) == LPUART1))\r
+\r
+/********************* UART Instances : Half-Duplex mode **********************/\r
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8) || \\r
+ ((INSTANCE) == LPUART1))\r
+\r
+/******************* UART Instances : Hardware Flow control *******************/\r
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8) || \\r
+ ((INSTANCE) == LPUART1))\r
+\r
+/************************* UART Instances : LIN mode **************************/\r
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8))\r
+\r
+/****************** UART Instances : Wake-up from Stop mode *******************/\r
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8) || \\r
+ ((INSTANCE) == LPUART1))\r
+\r
+/************************* UART Instances : IRDA mode *************************/\r
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == UART4) || \\r
+ ((INSTANCE) == UART5) || \\r
+ ((INSTANCE) == USART6) || \\r
+ ((INSTANCE) == UART7) || \\r
+ ((INSTANCE) == UART8))\r
+\r
+/********************* USART Instances : Smard card mode **********************/\r
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\r
+ ((INSTANCE) == USART2) || \\r
+ ((INSTANCE) == USART3) || \\r
+ ((INSTANCE) == USART6))\r
+\r
+/****************************** LPUART Instance *******************************/\r
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)\r
+\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))\r
+/****************************** USB Instances ********************************/\r
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)\r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG1) || \\r
+ ((INSTANCE) == WWDG2))\r
+/****************************** MDIOS Instances ********************************/\r
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)\r
+\r
+/****************************** CEC Instances *********************************/\r
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r
+\r
+/****************************** SAI Instances ********************************/\r
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \\r
+ ((INSTANCE) == SAI1_Block_B) || \\r
+ ((INSTANCE) == SAI2_Block_A) || \\r
+ ((INSTANCE) == SAI2_Block_B) || \\r
+ ((INSTANCE) == SAI3_Block_A) || \\r
+ ((INSTANCE) == SAI3_Block_B) || \\r
+ ((INSTANCE) == SAI4_Block_A) || \\r
+ ((INSTANCE) == SAI4_Block_B))\r
+\r
+/****************************** SPDIFRX Instances ********************************/\r
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)\r
+\r
+/****************************** OPAMP Instances *******************************/\r
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\r
+ ((INSTANCE) == OPAMP2))\r
+\r
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\r
+\r
+/*********************** USB OTG PCD Instances ********************************/\r
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+\r
+/*********************** USB OTG HCD Instances ********************************/\r
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+\r
+/******************************************************************************/\r
+/* For a painless codes migration between the STM32H7xx device product */\r
+/* lines, or with STM32F7xx devices the aliases defined below are put */\r
+/* in place to overcome the differences in the interrupt handlers and IRQn */\r
+/* definitions. No need to update developed interrupt code when moving */\r
+/* across product lines within the same STM32H7 Family */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+#define HASH_RNG_IRQn RNG_IRQn\r
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn\r
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn\r
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn\r
+#define PVD_IRQn PVD_AVD_IRQn\r
+\r
+\r
+/* Aliases for __IRQHandler */\r
+#define HASH_RNG_IRQHandler RNG_IRQHandler\r
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler\r
+#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler\r
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler\r
+#define PVD_IRQHandler PVD_AVD_IRQHandler\r
+\r
+/**\r
+ * @}\r
+ */\r
+/****************************** Product define *********************************/\r
+#define FLASH_SIZE 0x200000UL /* 2 MB */\r
+#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */\r
+#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */\r
+#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* STM32H745xx_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.\r
+ *\r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The STM32H7xx device used in the target application\r
+ * - To use or not the peripheral\92s drivers in application code(i.e.\r
+ * code will be based on direct access to peripheral\92s registers\r
+ * rather than drivers API), this option is controlled by\r
+ * "#define USE_HAL_DRIVER"\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32h7xx\r
+ * @{\r
+ */\r
+\r
+#ifndef STM32H7xx_H\r
+#define STM32H7xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32 Family\r
+ */\r
+#if !defined (STM32H7)\r
+#define STM32H7\r
+#endif /* STM32H7 */\r
+\r
+\r
+/* Uncomment the line below according to the target STM32H7 device used in your\r
+ application\r
+ */\r
+\r
+#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \\r
+ !defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)\r
+ /* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */\r
+ /* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */\r
+ /* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */\r
+ /* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */\r
+ /* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */\r
+ /* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */\r
+ /* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */\r
+ /* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */\r
+#endif\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+\r
+#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)\r
+ #error "Dual core device, please select CORE_CM4 or CORE_CM7"\r
+#endif\r
+\r
+#if !defined (USE_HAL_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will\r
+ be based on direct access to peripherals registers\r
+ */\r
+ /*#define USE_HAL_DRIVER */\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+/**\r
+ * @brief CMSIS Device version number V1.5.0\r
+ */\r
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */\r
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */\r
+#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\\r
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\\r
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\\r
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Device_Included\r
+ * @{\r
+ */\r
+\r
+#if defined(STM32H743xx)\r
+ #include "stm32h743xx.h"\r
+#elif defined(STM32H753xx)\r
+ #include "stm32h753xx.h"\r
+#elif defined(STM32H750xx)\r
+ #include "stm32h750xx.h"\r
+#elif defined(STM32H742xx)\r
+ #include "stm32h742xx.h"\r
+#elif defined(STM32H745xx)\r
+ #include "stm32h745xx.h"\r
+#elif defined(STM32H755xx)\r
+ #include "stm32h755xx.h"\r
+#elif defined(STM32H747xx)\r
+ #include "stm32h747xx.h"\r
+#elif defined(STM32H757xx)\r
+ #include "stm32h757xx.h"\r
+#else\r
+ #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ RESET = 0,\r
+ SET = !RESET\r
+} FlagStatus, ITStatus;\r
+\r
+typedef enum\r
+{\r
+ DISABLE = 0,\r
+ ENABLE = !DISABLE\r
+} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum\r
+{\r
+ ERROR = 0,\r
+ SUCCESS = !ERROR\r
+} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (USE_HAL_DRIVER)\r
+ #include "stm32h7xx_hal.h"\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* STM32H7xx_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32h7xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32h7xx_system\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef SYSTEM_STM32H7XX_H\r
+#define SYSTEM_STM32H7XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** @addtogroup STM32H7xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32H7xx_System_Exported_types\r
+ * @{\r
+ */\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */\r
+extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */\r
+extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SYSTEM_STM32H7XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+<!DOCTYPE html>\r
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">\r
+<head>\r
+ <meta charset="utf-8" />\r
+ <meta name="generator" content="pandoc" />\r
+ <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />\r
+ <title>Release Notes for STM32H7xx CMSIS</title>\r
+ <style type="text/css">\r
+ code{white-space: pre-wrap;}\r
+ span.smallcaps{font-variant: small-caps;}\r
+ span.underline{text-decoration: underline;}\r
+ div.column{display: inline-block; vertical-align: top; width: 50%;}\r
+ </style>\r
+ <link rel="stylesheet" href="../../../../../_htmresc/mini-st.css" />\r
+ <!--[if lt IE 9]>\r
+ <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>\r
+ <![endif]-->\r
+</head>\r
+<body>\r
+<div class="row">\r
+<div class="col-sm-12 col-lg-4">\r
+<div class="card fluid">\r
+<div class="sectione dark">\r
+<center>\r
+<h1 id="release-notes-for-stm32h7xx-cmsis"><strong>Release Notes for STM32H7xx CMSIS</strong></h1>\r
+<p>Copyright © 2017 STMicroelectronics<br />\r
+</p>\r
+<a href="https://www.st.com" class="logo"><img src="../../../../../_htmresc/st_logo.png" alt="ST logo" /></a>\r
+</center>\r
+</div>\r
+</div>\r
+<h1 id="license"><strong>License</strong></h1>\r
+This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:\r
+<center>\r
+<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>\r
+</center>\r
+</div>\r
+<div class="col-sm-12 col-lg-8">\r
+<h1 id="update-history"><strong>Update History</strong></h1>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>\r
+<div>\r
+<h2 id="main-changes">Main Changes</h2>\r
+<ul>\r
+<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>\r
+<li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>\r
+<li>Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx <strong>Dual Core</strong> devices and STM32H742xx (new single core device):\r
+<ul>\r
+<li>Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files</li>\r
+<li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>\r
+<li>Add part numbers list to stm32h7xx.h header file:\r
+<ul>\r
+<li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>\r
+<li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>\r
+<li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>\r
+<li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>\r
+<li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>\r
+<li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>\r
+<li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>\r
+<li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>\r
+<li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>\r
+<li>Add system initialization template source file for dual core lines:\r
+<ul>\r
+<li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>\r
+<li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>\r
+<li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>\r
+</ul></li>\r
+<li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>\r
+<li><p>Add EWARM STM32H742xx devices linker files</p></li>\r
+</ul></li>\r
+</ul></li>\r
+<li><strong>Registers and bit field definitions updates</strong>:\r
+<ul>\r
+<li>Update SYSCFG_TypeDef structure to add\r
+<ul>\r
+<li>Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs</li>\r
+<li>Add definitions of SYSCFG_CFGR register bit fields</li>\r
+<li>PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero</li>\r
+<li>Add SYSCFG_PWRCR register bit fields</li>\r
+</ul></li>\r
+<li>Update RCC_TypeDef structure according to STM32H7xx <strong>Rev.V</strong> devices:\r
+<ul>\r
+<li>ICSCR: renamed to HSICFGR, HSI Clock Calibration Register</li>\r
+<li>Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR</li>\r
+<li>CSICFGR: New registers (on <strong>Rev.V</strong> devices), CSI Clock Calibration Register</li>\r
+<li>Add dedicated RCC_CSICFGR_XXX bit definitions</li>\r
+</ul></li>\r
+<li>Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)\r
+<ul>\r
+<li>RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines</li>\r
+</ul></li>\r
+<li>Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 <strong>Rev.V</strong> devices</li>\r
+<li>Update ADC_CR_BOOST bot field definition for STM32H7 <strong>Rev.V</strong> devices: 2 bits instead of 1</li>\r
+<li>Remove useless I2C_CR1_SWRST definition: alignment with the reference manual</li>\r
+<li>Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 <strong>Rev.V</strong> devices</li>\r
+<li>Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual</li>\r
+<li>Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6</li>\r
+<li>Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK</li>\r
+<li>Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency</li>\r
+</ul></li>\r
+</ul>\r
+</div>\r
+</div>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>\r
+<div>\r
+<h2 id="main-changes-1">Main Changes</h2>\r
+<ul>\r
+<li><strong>Patch Release on top of V1.3.0</strong></li>\r
+<li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:\r
+<ul>\r
+<li>stm32h743xx.h, stm32h750xx.h and stm32h753xx.h</li>\r
+</ul></li>\r
+</ul>\r
+</div>\r
+</div>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>\r
+<div>\r
+<h2 id="main-changes-2">Main Changes</h2>\r
+<ul>\r
+<li>STM32H7xx include files:\r
+<ul>\r
+<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>\r
+<li>Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance</li>\r
+<li>Add definition of <strong>RAMECC_MonitorTypeDef</strong> and <strong>RAMECC_TypeDef</strong> structure</li>\r
+<li>Add definition of <strong>RAMECC</strong> peripheral base addresses</li>\r
+<li>Add <strong>RAMECC</strong> peripheral registers bit definitions</li>\r
+<li>Add IS_RAMECC_MONITOR_ALL_INSTANCE macro</li>\r
+<li>Add <strong>EXTI</strong> SWIER3 bit definitions</li>\r
+<li>Update <strong>FLASH</strong> sector number to 8 instead of 16 (8 sectors for each bank)</li>\r
+<li>Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7</li>\r
+<li>Update <strong>FLASH</strong> user option bytes bit definition</li>\r
+<li>Fix FLASH_BANK_SIZE definition: add parenthesis</li>\r
+<li>Remove <strong>PWR</strong> extra bit definition PWR_CR1_RLPSN</li>\r
+<li>Add <strong>PWR</strong> bit definition PWR_WKUPEPR_WKUPEN</li>\r
+<li>Fix typo in <strong>SDMMC</strong> bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE</li>\r
+<li>Add <strong>SDMMC</strong> instance check macro: IS_SDMMC_ALL_INSTANCE</li>\r
+<li>Fix typo in <strong>SYSCFG</strong> bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2</li>\r
+<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3</li>\r
+<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3</li>\r
+<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3</li>\r
+<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3</li>\r
+<li>Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis</li>\r
+<li>Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis</li>\r
+<li>Update <strong>USART</strong> and <strong>SMARTCARD</strong> bits definition</li>\r
+<li>Update <strong>GPIO</strong> registers and bit definition (BSRR register)</li>\r
+<li>Add IS_GPIO_AF_INSTANCE macro</li>\r
+<li>Update <strong>DAC</strong> bits definition</li>\r
+<li>Update <strong>FDCAN</strong> bits definition</li>\r
+<li>Update <strong>USB</strong> bits definition (OTEPSPRM register)</li>\r
+<li>Fix <strong>CEC</strong> bit definition (RXDR register)</li>\r
+<li>Update <strong>TIM</strong> registers and bits definition naming</li>\r
+<li>Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6</li>\r
+<li>Update <strong>SPI</strong> and <strong>I2S</strong> bits definition</li>\r
+<li>Update <strong>BDMA</strong> bits definition</li>\r
+<li>Update <strong>FMC</strong> bits definition</li>\r
+</ul></li>\r
+</ul>\r
+</div>\r
+</div>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>\r
+<div>\r
+<h2 id="main-changes-3">Main Changes</h2>\r
+<ul>\r
+<li>Add support for stm32h750xx value line devices:\r
+<ul>\r
+<li>Add “stm32h750xx.h” file</li>\r
+<li>Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32</li>\r
+</ul></li>\r
+</ul>\r
+</div>\r
+</div>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>\r
+<div>\r
+<h2 id="main-changes-4">Main Changes</h2>\r
+<ul>\r
+<li>Update FDCAN bit definition</li>\r
+<li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>\r
+</ul>\r
+</div>\r
+</div>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>\r
+<div>\r
+<h2 id="main-changes-5">Main Changes</h2>\r
+<ul>\r
+<li>Update USB OTG bit definition</li>\r
+<li>Adjust PLL fractional computation</li>\r
+</ul>\r
+</div>\r
+</div>\r
+<div class="collapse">\r
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>\r
+<div>\r
+<h2 id="main-changes-6">Main Changes</h2>\r
+<ul>\r
+<li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>\r
+</ul>\r
+</div>\r
+</div>\r
+</div>\r
+</div>\r
+<footer class="sticky">\r
+For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>\r
+</footer>\r
+</body>\r
+</html>\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_compiler.h\r
+ * @brief CMSIS compiler generic header file\r
+ * @version V5.0.1\r
+ * @date 30. January 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_COMPILER_H\r
+#define __CMSIS_COMPILER_H\r
+\r
+#include <stdint.h>\r
+\r
+/*\r
+ * ARM Compiler 4/5\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+\r
+/*\r
+ * ARM Compiler 6 (armclang)\r
+ */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armclang.h"\r
+\r
+\r
+/*\r
+ * GNU Compiler\r
+ */\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+\r
+/*\r
+ * IAR Compiler\r
+ */\r
+#elif defined ( __ICCARM__ )\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+\r
+ #include <cmsis_iar.h>\r
+\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __noreturn\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __root\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __weak\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32\r
+ __packed struct T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __packed\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT __packed struct\r
+ #endif\r
+\r
+\r
+/*\r
+ * TI ARM Compiler\r
+ */\r
+#elif defined ( __TI_ARM__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed))\r
+ #endif\r
+\r
+\r
+/*\r
+ * TASKING Compiler\r
+ */\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32\r
+ struct __packed__ T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __align(x)\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __packed__\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __packed__\r
+ #endif\r
+\r
+\r
+/*\r
+ * COSMIC Compiler\r
+ */\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM _asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ // NO RETURN is automatically detected hence no warning here\r
+ #define __NO_RETURN\r
+ #endif\r
+ #ifndef __USED\r
+ #warning No compiler specific solution for __USED. __USED is ignored.\r
+ #define __USED\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __weak\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32\r
+ @packed struct T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED @packed\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT @packed struct\r
+ #endif\r
+\r
+\r
+#else\r
+ #error Unknown compiler.\r
+#endif\r
+\r
+\r
+#endif /* __CMSIS_COMPILER_H */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V5.0.1\r
+ * @date 30. January 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (4U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000U\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V5.0.1\r
+ * @date 25. November 2016\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (7U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000U\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0U\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0U\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DTCM_PRESENT\r
+ #define __DTCM_PRESENT 0U\r
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifndef CMSIS_NVIC_VIRTUAL\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifndef CMSIS_VECTAB_VIRTUAL\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = SCB->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+\r
+\r
+/**\r
+ \brief Enable I-Cache\r
+ \details Turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable I-Cache\r
+ \details Turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate I-Cache\r
+ \details Invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable D-Cache\r
+ \details Turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+ __DSB();\r
+\r
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable D-Cache\r
+ \details Turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ register uint32_t ccsidr;\r
+ register uint32_t sets;\r
+ register uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate D-Cache\r
+ \details Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean D-Cache\r
+ \details Cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean & Invalidate D-Cache\r
+ \details Cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Invalidate by address\r
+ \details Invalidates D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t)addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean by address\r
+ \details Cleans D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean and Invalidate by address\r
+ \details Cleans and invalidates D_Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
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+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
--- /dev/null
+# CMSIS Version 5\r
+\r
+CMSIS Version 5.0.1 release is now available.\r
+\r
+This GitHub repository development branch reflects our current state of development and is constantly updated.\r
+\r
+The [pre-built documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) for the 5.0.1 release \r
+is available under http://arm-software.github.io/CMSIS_5/General/html/index.html\r
+\r
+Use *Issues* to provide feedback and report problems for CMSIS Version 5. Note that this repository gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions.\r
+\r
+## Implemented Enhancements\r
+ - Support for ARMv8-M Architecture (Mainline and Baseline) as well as devices Cortex-M23 and Cortex-M33\r
+\r
+ - CMSIS-RTOS Version 2 API and RTX reference implementation with several enhancements:\r
+ - Dynamic object creation, Flag events, C API, additional thread and timer functions\r
+\r
+ - CMSIS-RTOS API Secure and Non-Secure support, multi-processor support\r
+\r
+## Futher Planned Enhancements\r
+ - Improvements for Cortex-A / M hybrid devices (focus on Cortex-M interaction)\r
+\r
+ - CMSIS-Pack \r
+ - Additions for generic example, project templates, multiple download portals\r
+ - Adoption of IAR Flash Loader technology\r
+\r
+For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/master/CMSIS_EW2016.pdf).\r
+\r
+## Directory Structure\r
+\r
+| Directory | Content | \r
+| --------------- | ---------------------------------------------- |\r
+| CMSIS/Core | CMSIS-Core related files (for release) |\r
+| CMSIS/DAP | CMSIS-DAP related files and examples |\r
+| CMSIS/Driver | CMSIS-Driver API headers and template files |\r
+| CMSIS/DSP | CMSIS-DSP related files |\r
+| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) |\r
+| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & ARMv8-M) |\r
+| CMSIS/Pack | CMSIS-Pack examples and tutorials |\r
+| CMSIS/DoxyGen | Source of the documentation |\r
+| CMSIS/Utilities | Utility programs |\r
+\r
+## Generate CMSIS Pack for Release\r
+\r
+This GitHub development repository contains already pre-build libraries of various libraries (DSP, RTOS, RTOS2).\r
+These libraries are validated for release.\r
+\r
+To build a complete CMSIS pack for installation the following additional tools are required:\r
+ - **doxygen.exe** Version: 1.8.6 (Documentation Generator)\r
+ - **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter)\r
+ - **7z.exe (7-Zip)** Version: 16.02 (File Archiver)\r
+ \r
+Using these tools, you can generate on a Windows PC:\r
+ - **CMSIS Software Pack** using the batch file **gen_pack.bat** (located in ./CMSIS/Utilities). This batch file also generates the documentation.\r
+ \r
+ - **CMSIS Documentation** using the batch file **genDoc.bat** (located in ./CMSIS/Doxygen). \r
+\r
+The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation.\r
+\r
+## License\r
+\r
+ARM CMSIS is licensed under Apache-2.0.\r
+\r
+## Contributions and Pull Requests\r
+\r
+Contributions are accepted under Apache-2.0. Only submit contributions where you have authored all of the code.\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains all the functions prototypes for the HAL\r
+ * module driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_H\r
+#define STM32H7xx_HAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_conf.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup HAL_TICK_FREQ Tick Frequency\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TICK_FREQ_10HZ = 100U,\r
+ HAL_TICK_FREQ_100HZ = 10U,\r
+ HAL_TICK_FREQ_1KHZ = 1U,\r
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ\r
+} HAL_TickFreqTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup REV_ID device revision ID\r
+ * @{\r
+ */\r
+#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */\r
+#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */\r
+#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */\r
+#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale\r
+ * @{\r
+ */\r
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */\r
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */\r
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */\r
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */\r
+\r
+\r
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \\r
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \\r
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \\r
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance\r
+ * @{\r
+ */\r
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */\r
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */\r
+\r
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \\r
+ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))\r
+\r
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Ethernet_Config Ethernet Config\r
+ * @{\r
+ */\r
+#define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */\r
+#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */\r
+\r
+#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \\r
+ ((CONFIG) == SYSCFG_ETH_RMII))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config\r
+ * @{\r
+ */\r
+#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */\r
+#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */\r
+#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */\r
+#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */\r
+\r
+\r
+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \\r
+ (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \\r
+ (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \\r
+ (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))\r
+\r
+\r
+#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */\r
+#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */\r
+#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */\r
+#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/\r
+#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */\r
+#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */\r
+#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */\r
+#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */\r
+\r
+#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \\r
+ (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \\r
+ (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \\r
+ (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \\r
+ (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \\r
+ (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \\r
+ (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \\r
+ (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Boot_Config Boot Config\r
+ * @{\r
+ */\r
+#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */\r
+#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */\r
+\r
+#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \\r
+ ((REGISTER) == SYSCFG_BOOT_ADDR1))\r
+\r
+#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config\r
+ * @{\r
+ */\r
+#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */\r
+#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */\r
+\r
+#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \\r
+ ((SELECT) == SYSCFG_REGISTER_CODE))\r
+\r
+#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+\r
+/** @defgroup EXTI_Event_Input_Config Event Input Config\r
+ * @{\r
+ */\r
+\r
+#define EXTI_MODE_IT ((uint32_t)0x00010000)\r
+#define EXTI_MODE_EVT ((uint32_t)0x00020000)\r
+#define EXTI_RISING_EDGE ((uint32_t)0x00100000)\r
+#define EXTI_FALLING_EDGE ((uint32_t)0x00200000)\r
+\r
+#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))\r
+#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))\r
+\r
+#define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */\r
+#define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */\r
+#define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */\r
+#define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */\r
+#define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */\r
+#define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */\r
+#define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */\r
+#define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */\r
+#define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */\r
+#define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */\r
+#define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */\r
+#define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */\r
+#define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */\r
+#define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */\r
+#define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */\r
+#define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */\r
+#define EXTI_LINE16 ((uint32_t)0x10)\r
+#define EXTI_LINE17 ((uint32_t)0x11)\r
+#define EXTI_LINE18 ((uint32_t)0x12)\r
+#define EXTI_LINE19 ((uint32_t)0x13)\r
+#define EXTI_LINE20 ((uint32_t)0x14)\r
+#define EXTI_LINE21 ((uint32_t)0x15)\r
+#define EXTI_LINE22 ((uint32_t)0x16)\r
+#define EXTI_LINE23 ((uint32_t)0x17)\r
+#define EXTI_LINE24 ((uint32_t)0x18)\r
+#define EXTI_LINE25 ((uint32_t)0x19)\r
+#define EXTI_LINE26 ((uint32_t)0x1A)\r
+#define EXTI_LINE27 ((uint32_t)0x1B)\r
+#define EXTI_LINE28 ((uint32_t)0x1C)\r
+#define EXTI_LINE29 ((uint32_t)0x1D)\r
+#define EXTI_LINE30 ((uint32_t)0x1E)\r
+#define EXTI_LINE31 ((uint32_t)0x1F)\r
+#define EXTI_LINE32 ((uint32_t)0x20)\r
+#define EXTI_LINE33 ((uint32_t)0x21)\r
+#define EXTI_LINE34 ((uint32_t)0x22)\r
+#define EXTI_LINE35 ((uint32_t)0x23)\r
+#define EXTI_LINE36 ((uint32_t)0x24)\r
+#define EXTI_LINE37 ((uint32_t)0x25)\r
+#define EXTI_LINE38 ((uint32_t)0x26)\r
+#define EXTI_LINE39 ((uint32_t)0x27)\r
+\r
+#define EXTI_LINE40 ((uint32_t)0x28)\r
+#define EXTI_LINE41 ((uint32_t)0x29)\r
+#define EXTI_LINE42 ((uint32_t)0x2A)\r
+#define EXTI_LINE43 ((uint32_t)0x2B)\r
+#define EXTI_LINE44 ((uint32_t)0x2C)\r
+/* EXTI_LINE45 Reserved */\r
+#if defined(DUAL_CORE)\r
+#define EXTI_LINE46 ((uint32_t)0x2E)\r
+#else\r
+/* EXTI_LINE46 Reserved */\r
+#endif\r
+#define EXTI_LINE47 ((uint32_t)0x2F)\r
+#define EXTI_LINE48 ((uint32_t)0x30)\r
+#define EXTI_LINE49 ((uint32_t)0x31)\r
+\r
+#define EXTI_LINE50 ((uint32_t)0x32)\r
+#define EXTI_LINE51 ((uint32_t)0x33)\r
+#define EXTI_LINE52 ((uint32_t)0x34)\r
+#define EXTI_LINE53 ((uint32_t)0x35)\r
+#define EXTI_LINE54 ((uint32_t)0x36)\r
+#define EXTI_LINE55 ((uint32_t)0x37)\r
+#define EXTI_LINE56 ((uint32_t)0x38)\r
+#define EXTI_LINE57 ((uint32_t)0x39)\r
+#define EXTI_LINE58 ((uint32_t)0x3A)\r
+#define EXTI_LINE59 ((uint32_t)0x3B)\r
+\r
+#define EXTI_LINE60 ((uint32_t)0x3C)\r
+#define EXTI_LINE61 ((uint32_t)0x3D)\r
+#define EXTI_LINE62 ((uint32_t)0x3E)\r
+#define EXTI_LINE63 ((uint32_t)0x3F)\r
+#define EXTI_LINE64 ((uint32_t)0x40)\r
+#define EXTI_LINE65 ((uint32_t)0x41)\r
+#define EXTI_LINE66 ((uint32_t)0x42)\r
+#define EXTI_LINE67 ((uint32_t)0x43)\r
+#define EXTI_LINE68 ((uint32_t)0x44)\r
+#define EXTI_LINE69 ((uint32_t)0x45)\r
+\r
+#define EXTI_LINE70 ((uint32_t)0x46)\r
+#define EXTI_LINE71 ((uint32_t)0x47)\r
+#define EXTI_LINE72 ((uint32_t)0x48)\r
+#define EXTI_LINE73 ((uint32_t)0x49)\r
+#define EXTI_LINE74 ((uint32_t)0x4A)\r
+#define EXTI_LINE75 ((uint32_t)0x4B)\r
+#define EXTI_LINE76 ((uint32_t)0x4C)\r
+\r
+#if defined(DUAL_CORE)\r
+#define EXTI_LINE77 ((uint32_t)0x4D)\r
+#define EXTI_LINE78 ((uint32_t)0x4E)\r
+#define EXTI_LINE79 ((uint32_t)0x4F)\r
+\r
+#define EXTI_LINE80 ((uint32_t)0x50)\r
+/* EXTI_LINE81 Reserved */\r
+#define EXTI_LINE82 ((uint32_t)0x52)\r
+/* EXTI_LINE83 Reserved */\r
+#define EXTI_LINE84 ((uint32_t)0x54)\r
+#define EXTI_LINE85 ((uint32_t)0x55)\r
+#define EXTI_LINE86 ((uint32_t)0x56)\r
+#define EXTI_LINE87 ((uint32_t)0x57)\r
+/* EXTI_LINE88 Reserved */\r
+#else\r
+/* EXTI_LINE77 Reserved */\r
+/* EXTI_LINE78 Reserved */\r
+/* EXTI_LINE79 Reserved */\r
+/* EXTI_LINE80 Reserved */\r
+/* EXTI_LINE81 Reserved */\r
+/* EXTI_LINE82 Reserved */\r
+/* EXTI_LINE83 Reserved */\r
+/* EXTI_LINE84 Reserved */\r
+\r
+#define EXTI_LINE85 ((uint32_t)0x55)\r
+#define EXTI_LINE86 ((uint32_t)0x56)\r
+#define EXTI_LINE87 ((uint32_t)0x57)\r
+\r
+/* EXTI_LINE88 Reserved */\r
+#endif\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \\r
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \\r
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \\r
+ ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84) || \\r
+ ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))\r
+#else\r
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \\r
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \\r
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \\r
+ ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))\r
+#endif\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \\r
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \\r
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \\r
+ ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \\r
+ ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \\r
+ ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \\r
+ ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \\r
+ ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \\r
+ ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \\r
+ ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \\r
+ ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \\r
+ ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \\r
+ ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \\r
+ ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \\r
+ ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \\r
+ ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \\r
+ ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \\r
+ ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \\r
+ ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \\r
+ ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \\r
+ ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \\r
+ ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \\r
+ ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \\r
+ ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \\r
+ ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \\r
+ ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \\r
+ ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \\r
+ ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \\r
+ ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \\r
+ ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \\r
+ ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \\r
+ ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \\r
+ ((LINE) == EXTI_LINE78) || \\r
+ ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))\r
+#else\r
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \\r
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \\r
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \\r
+ ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \\r
+ ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \\r
+ ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \\r
+ ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \\r
+ ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \\r
+ ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \\r
+ ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \\r
+ ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \\r
+ ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \\r
+ ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \\r
+ ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \\r
+ ((LINE) == EXTI_LINE44) || \\r
+ ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \\r
+ ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \\r
+ ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \\r
+ ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \\r
+ ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \\r
+ ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \\r
+ ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \\r
+ ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \\r
+ ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \\r
+ ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \\r
+ ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \\r
+ ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \\r
+ ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \\r
+ ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \\r
+ ((LINE) == EXTI_LINE85) || \\r
+ ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \\r
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \\r
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \\r
+ ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \\r
+ ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \\r
+ ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \\r
+ ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \\r
+ ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \\r
+ ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \\r
+ ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \\r
+ ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \\r
+ ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \\r
+ ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \\r
+ ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \\r
+ ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \\r
+ ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \\r
+ ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \\r
+ ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \\r
+ ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \\r
+ ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \\r
+ ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \\r
+ ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \\r
+ ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \\r
+ ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \\r
+ ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \\r
+ ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \\r
+ ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \\r
+ ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \\r
+ ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \\r
+ ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \\r
+ ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \\r
+ ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))\r
+#else\r
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \\r
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \\r
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \\r
+ ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \\r
+ ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \\r
+ ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \\r
+ ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \\r
+ ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \\r
+ ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \\r
+ ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \\r
+ ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \\r
+ ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \\r
+ ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \\r
+ ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \\r
+ ((LINE) == EXTI_LINE44) || \\r
+ ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \\r
+ ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \\r
+ ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \\r
+ ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \\r
+ ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \\r
+ ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \\r
+ ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \\r
+ ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \\r
+ ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \\r
+ ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \\r
+ ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \\r
+ ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \\r
+ ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \\r
+ ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \\r
+ ((LINE) == EXTI_LINE85) || \\r
+ ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \\r
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \\r
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \\r
+ ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \\r
+ ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \\r
+ ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \\r
+ ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \\r
+ ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \\r
+ ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \\r
+ ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \\r
+ ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \\r
+ ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \\r
+ ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \\r
+ ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \\r
+ ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \\r
+ ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \\r
+ ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \\r
+ ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \\r
+ ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \\r
+ ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \\r
+ ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \\r
+ ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \\r
+ ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \\r
+ ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \\r
+ ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \\r
+ ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \\r
+ ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \\r
+ ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \\r
+ ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \\r
+ ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \\r
+ ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \\r
+ ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \\r
+ ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \\r
+ ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \\r
+ ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \\r
+ ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \\r
+ ((LINE) == EXTI_LINE53))\r
+#else\r
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \\r
+ ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \\r
+ ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \\r
+ ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \\r
+ ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \\r
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \\r
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \\r
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \\r
+ ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \\r
+ ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \\r
+ ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \\r
+ ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \\r
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \\r
+ ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \\r
+ ((LINE) == EXTI_LINE53))\r
+#endif\r
+\r
+\r
+#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/\r
+#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/\r
+#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/\r
+#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/\r
+\r
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \\r
+ ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config\r
+ * @{\r
+ */\r
+#define FMC_SWAPBMAP_DISABLE (0x00000000U)\r
+#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0\r
+#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1\r
+\r
+#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \\r
+ ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \\r
+ ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief SYSCFG Break AXIRAM double ECC lock.\r
+ * Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)\r
+\r
+/** @brief SYSCFG Break ITCM double ECC lock.\r
+ * Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)\r
+\r
+/** @brief SYSCFG Break DTCM double ECC lock.\r
+ * Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)\r
+\r
+/** @brief SYSCFG Break SRAM1 double ECC lock.\r
+ * Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)\r
+\r
+/** @brief SYSCFG Break SRAM2 double ECC lock.\r
+ * Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)\r
+\r
+/** @brief SYSCFG Break SRAM3 double ECC lock.\r
+ * Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)\r
+\r
+/** @brief SYSCFG Break SRAM4 double ECC lock.\r
+ * Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)\r
+\r
+/** @brief SYSCFG Break Backup SRAM double ECC lock.\r
+ * Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)\r
+\r
+/** @brief SYSCFG Break Cortex-M7 Lockup lock.\r
+ * Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)\r
+\r
+/** @brief SYSCFG Break FLASH double ECC lock.\r
+ * Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)\r
+\r
+/** @brief SYSCFG Break PVD lock.\r
+ * Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)\r
+\r
+#if defined(DUAL_CORE)\r
+/** @brief SYSCFG Break Cortex-M4 Lockup lock.\r
+ * Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ This feature is available on STM32H7 rev.B and above.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)\r
+#endif /* DUAL_CORE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @brief Freeze/Unfreeze Peripherals in Debug mode\r
+ */\r
+#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))\r
+\r
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))\r
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))\r
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))\r
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))\r
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))\r
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))\r
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))\r
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))\r
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))\r
+#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))\r
+#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))\r
+#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))\r
+#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))\r
+\r
+\r
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))\r
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))\r
+#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))\r
+#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))\r
+#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))\r
+#define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))\r
+\r
+#define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))\r
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))\r
+#define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))\r
+\r
+\r
+#define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))\r
+\r
+#define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))\r
+#define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))\r
+#define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))\r
+#define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))\r
+#define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))\r
+#define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))\r
+#define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))\r
+#define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))\r
+#define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))\r
+#define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))\r
+#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))\r
+#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))\r
+#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))\r
+#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))\r
+\r
+\r
+#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))\r
+#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))\r
+#define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))\r
+#define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))\r
+#define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))\r
+#define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))\r
+\r
+#define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))\r
+#define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))\r
+#define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))\r
+#define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))\r
+#define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))\r
+#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))\r
+#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))\r
+\r
+\r
+#if defined(DUAL_CORE)\r
+#define __HAL_DBGMCU_FREEZE2_IWDG2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG2))\r
+#define __HAL_DBGMCU_FREEZE2_WWDG2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))\r
+\r
+#define __HAL_DBGMCU_UnFreeze2_IWDG2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))\r
+#define __HAL_DBGMCU_UnFreeze2_WWDG2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))\r
+\r
+\r
+#define __HAL_DBGMCU_FREEZE2_WWDG1() (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))\r
+\r
+#define __HAL_DBGMCU_FREEZE2_TIM2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))\r
+#define __HAL_DBGMCU_FREEZE2_TIM3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))\r
+#define __HAL_DBGMCU_FREEZE2_TIM4() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))\r
+#define __HAL_DBGMCU_FREEZE2_TIM5() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))\r
+#define __HAL_DBGMCU_FREEZE2_TIM6() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))\r
+#define __HAL_DBGMCU_FREEZE2_TIM7() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))\r
+#define __HAL_DBGMCU_FREEZE2_TIM12() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))\r
+#define __HAL_DBGMCU_FREEZE2_TIM13() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))\r
+#define __HAL_DBGMCU_FREEZE2_TIM14() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))\r
+#define __HAL_DBGMCU_FREEZE2_LPTIM1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))\r
+#define __HAL_DBGMCU_FREEZE2_I2C1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))\r
+#define __HAL_DBGMCU_FREEZE2_I2C2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))\r
+#define __HAL_DBGMCU_FREEZE2_I2C3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))\r
+#define __HAL_DBGMCU_FREEZE2_FDCAN() (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))\r
+\r
+\r
+#define __HAL_DBGMCU_FREEZE2_TIM1() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))\r
+#define __HAL_DBGMCU_FREEZE2_TIM8() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))\r
+#define __HAL_DBGMCU_FREEZE2_TIM15() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))\r
+#define __HAL_DBGMCU_FREEZE2_TIM16() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))\r
+#define __HAL_DBGMCU_FREEZE2_TIM17() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))\r
+#define __HAL_DBGMCU_FREEZE2_HRTIM() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))\r
+\r
+#define __HAL_DBGMCU_FREEZE2_I2C4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))\r
+#define __HAL_DBGMCU_FREEZE2_LPTIM2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))\r
+#define __HAL_DBGMCU_FREEZE2_LPTIM3() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))\r
+#define __HAL_DBGMCU_FREEZE2_LPTIM4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))\r
+#define __HAL_DBGMCU_FREEZE2_LPTIM5() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))\r
+#define __HAL_DBGMCU_FREEZE2_RTC() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))\r
+#define __HAL_DBGMCU_FREEZE2_IWDG1() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))\r
+\r
+#define __HAL_DBGMCU_UnFreeze2_WWDG1() (DBGMCU->APB3FZ2 &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))\r
+\r
+#define __HAL_DBGMCU_UnFreeze2_TIM2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM4() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM5() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM6() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM7() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM12() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM13() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM14() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))\r
+#define __HAL_DBGMCU_UnFreeze2_LPTIM1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))\r
+#define __HAL_DBGMCU_UnFreeze2_I2C1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))\r
+#define __HAL_DBGMCU_UnFreeze2_I2C2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))\r
+#define __HAL_DBGMCU_UnFreeze2_I2C3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))\r
+#define __HAL_DBGMCU_UnFreeze2_FDCAN() (DBGMCU->APB1HFZ2 &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))\r
+\r
+\r
+#define __HAL_DBGMCU_UnFreeze2_TIM1() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM8() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM15() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM16() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))\r
+#define __HAL_DBGMCU_UnFreeze2_TIM17() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))\r
+#define __HAL_DBGMCU_UnFreeze2_HRTIM() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))\r
+\r
+#define __HAL_DBGMCU_UnFreeze2_I2C4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))\r
+#define __HAL_DBGMCU_UnFreeze2_LPTIM2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))\r
+#define __HAL_DBGMCU_UnFreeze2_LPTIM3() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))\r
+#define __HAL_DBGMCU_UnFreeze2_LPTIM4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))\r
+#define __HAL_DBGMCU_UnFreeze2_LPTIM5() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))\r
+#define __HAL_DBGMCU_UnFreeze2_RTC() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_RTC))\r
+#define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+/** @defgroup HAL_Private_Macros HAL Private Macros\r
+ * @{\r
+ */\r
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \\r
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \\r
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_Init(void);\r
+HAL_StatusTypeDef HAL_DeInit(void);\r
+void HAL_MspInit(void);\r
+void HAL_MspDeInit(void);\r
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\r
+\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_IncTick(void);\r
+void HAL_Delay(uint32_t Delay);\r
+uint32_t HAL_GetTick(void);\r
+uint32_t HAL_GetTickPrio(void);\r
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);\r
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);\r
+void HAL_SuspendTick(void);\r
+void HAL_ResumeTick(void);\r
+uint32_t HAL_GetHalVersion(void);\r
+uint32_t HAL_GetREVID(void);\r
+uint32_t HAL_GetDEVID(void);\r
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);\r
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );\r
+void HAL_SYSCFG_EnableBOOST(void);\r
+void HAL_SYSCFG_DisableBOOST(void);\r
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);\r
+#if defined(DUAL_CORE)\r
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);\r
+void HAL_SYSCFG_EnableCM7BOOT(void);\r
+void HAL_SYSCFG_DisableCM7BOOT(void);\r
+void HAL_SYSCFG_EnableCM4BOOT(void);\r
+void HAL_SYSCFG_DisableCM4BOOT(void);\r
+#endif /*DUAL_CORE*/\r
+void HAL_EnableCompensationCell(void);\r
+void HAL_DisableCompensationCell(void);\r
+void HAL_SYSCFG_EnableIOSpeedOptimize(void);\r
+void HAL_SYSCFG_DisableIOSpeedOptimize(void);\r
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);\r
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);\r
+void HAL_EnableDBGSleepMode(void);\r
+void HAL_DisableDBGSleepMode(void);\r
+void HAL_EnableDBGStopMode(void);\r
+void HAL_DisableDBGStopMode(void);\r
+void HAL_EnableDBGStandbyMode(void);\r
+void HAL_DisableDBGStandbyMode(void);\r
+#if defined(DUAL_CORE)\r
+void HAL_EnableDomain2DBGSleepMode(void);\r
+void HAL_DisableDomain2DBGSleepMode(void);\r
+void HAL_EnableDomain2DBGStopMode(void);\r
+void HAL_DisableDomain2DBGStopMode(void);\r
+void HAL_EnableDomain2DBGStandbyMode(void);\r
+void HAL_DisableDomain2DBGStandbyMode(void);\r
+#endif /*DUAL_CORE*/\r
+void HAL_EnableDomain3DBGStopMode(void);\r
+void HAL_DisableDomain3DBGStopMode(void);\r
+void HAL_EnableDomain3DBGStandbyMode(void);\r
+void HAL_DisableDomain3DBGStandbyMode(void);\r
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );\r
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+#if defined(DUAL_CORE)\r
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);\r
+#endif /*DUAL_CORE*/\r
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);\r
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);\r
+#if defined(DUAL_CORE)\r
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);\r
+#endif /*DUAL_CORE*/\r
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);\r
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);\r
+uint32_t HAL_GetFMCMemorySwappingConfig(void);\r
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);\r
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);\r
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);\r
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);\r
+void HAL_SYSCFG_DisableVREFBUF(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_adc.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of ADC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_ADC_H\r
+#define STM32H7xx_HAL_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/* Include low level driver */\r
+#include "stm32h7xx_ll_adc.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup ADC_Exported_Types ADC Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief ADC group regular oversampling structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Ratio; /*!< Configures the oversampling ratio.\r
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */\r
+\r
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.\r
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */\r
+\r
+ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.\r
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */\r
+\r
+ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.\r
+ The oversampling is either temporary stopped or reset upon an injected\r
+ sequence interruption.\r
+ If oversampling is enabled on both regular and injected groups, this parameter\r
+ is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"\r
+ (the oversampling buffer is zeroed during injection sequence).\r
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */\r
+\r
+}ADC_OversamplingTypeDef;\r
+\r
+/**\r
+ * @brief Structure definition of ADC instance and ADC group regular.\r
+ * @note Parameters of this structure are shared within 2 scopes:\r
+ * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,\r
+ * ScanConvMode, EOCSelection, LowPowerAutoWait.\r
+ * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,\r
+ * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.\r
+ * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.\r
+ * ADC state can be either:\r
+ * - For all parameters: ADC disabled\r
+ * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.\r
+ * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.\r
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed\r
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter\r
+ * (which fulfills the ADC state condition) on the fly).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.\r
+ This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.\r
+ Note: The ADC clock configuration is common to all ADC instances.\r
+ Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, \r
+ AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.\r
+ Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only\r
+ if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC \r
+ must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.\r
+ Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.\r
+ Note: This parameter can be modified only if all ADC instances are disabled. */\r
+\r
+ uint32_t Resolution; /*!< Configure the ADC resolution. \r
+ This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */\r
+\r
+ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.\r
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.\r
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).\r
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).\r
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).\r
+ Scan direction is upward: from rank 1 to rank 'n'.\r
+ This parameter can be a value of @ref ADC_Scan_mode */\r
+\r
+ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.\r
+ This parameter can be a value of @ref ADC_EOCSelection. */\r
+\r
+ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous\r
+ conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,\r
+ using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().\r
+ This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun\r
+ for low frequency applications.\r
+ This parameter can be set to ENABLE or DISABLE.\r
+ Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag\r
+ to free the IRQ vector sequencer.\r
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:\r
+ use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.\r
+ (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */\r
+\r
+ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,\r
+ after the first ADC conversion start trigger occurred (software start or external trigger).\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.\r
+ To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16.\r
+ Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without \r
+ continuous mode or external trigger that could launch a conversion). */\r
+\r
+ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence\r
+ (main sequence subdivided in successive parts).\r
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\r
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.\r
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */\r
+\r
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.\r
+ If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.\r
+ This parameter can be a value of @ref ADC_regular_external_trigger_source.\r
+ Caution: external trigger source is common to all ADC instances. */\r
+ \r
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.\r
+ If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.\r
+ This parameter can be a value of @ref ADC_regular_external_trigger_edge */\r
+\r
+ uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.\r
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.\r
+ This parameter can be a value of @ref ADC_ConversionDataManagement.\r
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups\r
+ (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */\r
+\r
+ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).\r
+ This parameter applies to ADC group regular only.\r
+ This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.\r
+ Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear \r
+ end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function \r
+ HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).\r
+ Note: Error reporting with respect to the conversion mode:\r
+ - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data \r
+ overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.\r
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */\r
+\r
+ uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.\r
+ This parameter can be a value of @ref ADCEx_Left_Bit_Shift */\r
+ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.\r
+ This parameter can be set to ENABLE or DISABLE.\r
+ Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */\r
+\r
+ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.\r
+ Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */\r
+\r
+}ADC_InitTypeDef;\r
+\r
+/**\r
+ * @brief Structure definition of ADC channel for regular group\r
+ * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.\r
+ * ADC state can be either:\r
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')\r
+ * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.\r
+ * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.\r
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed\r
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)\r
+ * on the fly).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.\r
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL\r
+ Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */\r
+\r
+ uint32_t Rank; /*!< Specify the rank in the regular group sequencer.\r
+ This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS\r
+ Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by\r
+ the new channel setting (or parameter number of conversions adjusted) */\r
+\r
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.\r
+ Unit: ADC clock cycles\r
+ Conversion time is the addition of sampling time and processing time\r
+ (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).\r
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME\r
+ Caution: This parameter applies to a channel that can be used into regular and/or injected group.\r
+ It overwrites the last setting.\r
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\r
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\r
+ Refer to device datasheet for timings values. */\r
+\r
+ uint32_t SingleDiff; /*!< Select single-ended or differential input.\r
+ In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).\r
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.\r
+ This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING\r
+ Caution: This parameter applies to a channel that can be used in a regular and/or injected group.\r
+ It overwrites the last setting.\r
+ Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.\r
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.\r
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).\r
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case\r
+ of another parameter update on the fly) */\r
+\r
+ uint32_t OffsetNumber; /*!< Select the offset number\r
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB\r
+ Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */\r
+\r
+ uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.\r
+ Offset value must be a positive number.\r
+ Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,\r
+ 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.\r
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled \r
+ without continuous mode or external trigger that could launch a conversion). */\r
+\r
+ FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.\r
+ This parameter is applied only for 16-bit or 8-bit resolution.\r
+ This parameter can be set to ENABLE or DISABLE.*/\r
+\r
+ FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.\r
+ This parameter is applied only for 16-bit or 8-bit resolution.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+}ADC_ChannelConfTypeDef;\r
+\r
+/**\r
+ * @brief Structure definition of ADC analog watchdog\r
+ * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.\r
+ * ADC state can be either:\r
+ * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.\r
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')\r
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)\r
+ This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */\r
+\r
+ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.\r
+ For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.\r
+ For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.\r
+ This parameter can be a value of @ref ADC_analog_watchdog_mode. */\r
+\r
+ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.\r
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).\r
+ For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').\r
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */\r
+\r
+ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+\r
+ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.\r
+ Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number\r
+ between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.\r
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits \r
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.\r
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are\r
+ impacted: the comparison of analog watchdog thresholds is done \r
+ on oversampling intermediate computation (after ratio, before shift\r
+ application): intermediate register bitfield [32:7] (26 most significant bits). */\r
+\r
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.\r
+ Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number\r
+ between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.\r
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits\r
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.\r
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are\r
+ impacted: the comparison of analog watchdog thresholds is done \r
+ on oversampling intermediate computation (after ratio, before shift\r
+ application): intermediate register bitfield [32:7] (26 most significant bits). */\r
+}ADC_AnalogWDGConfTypeDef;\r
+\r
+/**\r
+ * @brief ADC group injected contexts queue configuration\r
+ * @note Structure intended to be used only through structure "ADC_HandleTypeDef"\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each \r
+ HAL_ADCEx_InjectedConfigChannel() call to finally initialize\r
+ JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */\r
+ \r
+ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */\r
+}ADC_InjectionConfigTypeDef; \r
+\r
+/** @defgroup ADC_States ADC States\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HAL ADC state machine: ADC states definition (bitfields)\r
+ * @note ADC state machine is managed by bitfields, state must be compared\r
+ * with bit by bit.\r
+ * For example: \r
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "\r
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "\r
+ */\r
+/* States of ADC global scope */\r
+#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */\r
+#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */\r
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */\r
+#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */\r
+\r
+/* States of ADC errors */\r
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */\r
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */\r
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */\r
+\r
+/* States of ADC group regular */\r
+#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,\r
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\r
+#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */\r
+#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */\r
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */\r
+\r
+/* States of ADC group injected */\r
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,\r
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\r
+#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */\r
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */\r
+\r
+/* States of ADC analog watchdogs */\r
+#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */\r
+#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */\r
+#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */\r
+\r
+/* States of ADC multi-mode */\r
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief ADC handle Structure definition\r
+ */\r
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\r
+typedef struct __ADC_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif\r
+{\r
+ ADC_TypeDef *Instance; /*!< Register base address */\r
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */\r
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */\r
+ HAL_LockTypeDef Lock; /*!< ADC locking object */\r
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */\r
+ __IO uint32_t ErrorCode; /*!< ADC Error code */\r
+ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */\r
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\r
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */\r
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */\r
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */\r
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */\r
+ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */\r
+ void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */\r
+ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */\r
+ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */\r
+ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */\r
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */\r
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */\r
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\r
+}ADC_HandleTypeDef;\r
+\r
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL ADC Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */\r
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */\r
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */\r
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */\r
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */\r
+ HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */\r
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */\r
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */\r
+ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */\r
+ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */\r
+ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */\r
+} HAL_ADC_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL ADC Callback pointer definition\r
+ */\r
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */\r
+\r
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants ADC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Error_Code ADC Error Code\r
+ * @{\r
+ */\r
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */\r
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,\r
+ enable/disable, erroneous state, ...) */\r
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */\r
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */\r
+#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */\r
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\r
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */\r
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source\r
+ * @{\r
+ */\r
+#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */\r
+#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */\r
+#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */\r
+\r
+#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */\r
+#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */\r
+#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */\r
+#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */\r
+#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */\r
+#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */\r
+#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */\r
+#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */\r
+#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */\r
+#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */\r
+#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */\r
+#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution\r
+ * @{\r
+ */\r
+#define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits */\r
+#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */\r
+#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */\r
+#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */\r
+#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode\r
+ * @{\r
+ */\r
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */\r
+#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source\r
+ * @{\r
+ */\r
+/* ADC group regular trigger sources for all ADC instances */\r
+#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */\r
+#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)\r
+ * @{\r
+ */\r
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */\r
+#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */\r
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */\r
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions\r
+ * @{\r
+ */\r
+#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */\r
+#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data\r
+ * @{\r
+ */\r
+#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */\r
+#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks\r
+ * @{\r
+ */\r
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */\r
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */\r
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */\r
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */\r
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */\r
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */\r
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */\r
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */\r
+#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */\r
+#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */\r
+#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */\r
+#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */\r
+#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */\r
+#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */\r
+#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */\r
+#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time\r
+ * @{\r
+ */\r
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles */\r
+#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */\r
+#define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles */\r
+#define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles */\r
+#define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles */\r
+#define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles */\r
+#define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles */\r
+#define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode\r
+ * @{\r
+ */\r
+#define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)\r
+#define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number\r
+ * @{\r
+ */\r
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */\r
+/* all ADC instances (refer to Reference Manual). */\r
+#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */\r
+#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */\r
+#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */\r
+#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */\r
+#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */\r
+#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */\r
+#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */\r
+#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */\r
+#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */\r
+#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */\r
+#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */\r
+#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */\r
+#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */\r
+#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */\r
+#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */\r
+#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */\r
+#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */\r
+#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */\r
+#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */\r
+#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */\r
+#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3. */\r
+#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC3. */\r
+#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */\r
+#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */\r
+#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management\r
+ * @{\r
+ */\r
+#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */\r
+#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */\r
+#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */\r
+#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number\r
+ * @{\r
+ */\r
+#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */\r
+#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */\r
+#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode\r
+ * @{\r
+ */\r
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */\r
+#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */\r
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */\r
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */\r
+#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */\r
+#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */\r
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio\r
+ * @{\r
+ */\r
+#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_512 (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+#define ADC_OVERSAMPLING_RATIO_1024 (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift\r
+ * @{\r
+ */\r
+#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */\r
+#define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift\r
+ * @{\r
+ */\r
+#define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */\r
+#define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */\r
+#define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */\r
+#define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */\r
+#define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */\r
+#define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */\r
+#define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */\r
+#define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */\r
+#define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */\r
+#define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */\r
+#define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */\r
+#define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */\r
+#define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */\r
+#define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */\r
+#define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */\r
+#define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode\r
+ * @{\r
+ */\r
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */\r
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular\r
+ * @{\r
+ */\r
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */\r
+#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup ADC_Event_type ADC Event type\r
+ * @{\r
+ */\r
+#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */\r
+#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */\r
+#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */\r
+#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */\r
+#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */\r
+#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */\r
+/**\r
+ * @}\r
+ */\r
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */\r
+\r
+/** @defgroup ADC_interrupts_definition ADC interrupts definition\r
+ * @{\r
+ */\r
+#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */\r
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */\r
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */\r
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */\r
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */\r
+#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */\r
+#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */\r
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */\r
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */\r
+#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */\r
+#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */\r
+\r
+#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_flags_definition ADC flags definition\r
+ * @{\r
+ */\r
+#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */\r
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */\r
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */\r
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */\r
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */\r
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */\r
+#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */\r
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */\r
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */\r
+#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */\r
+#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Macros ADC Private Macros\r
+ * @{\r
+ */\r
+/* Macro reserved for internal HAL driver usage, not intended to be used in */\r
+/* code of final user. */\r
+\r
+/**\r
+ * @brief Verify the ADC data conversion setting.\r
+ * @param DATA : programmed DATA conversion mode.\r
+ * @retval SET (DATA is a valid value) or RESET (DATA is invalid)\r
+ */\r
+#define IS_ADC_CONVERSIONDATAMGT(DATA) \\r
+ ((((DATA) == ADC_CONVERSIONDATA_DR)) || \\r
+ (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \\r
+ (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \\r
+ (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))\r
+\r
+/**\r
+ * @brief Return resolution bits in CFGR register RES[1:0] field.\r
+ * @param __HANDLE__ ADC handle\r
+ * @retval Value of bitfield RES in CFGR register.\r
+ */\r
+#define ADC_GET_RESOLUTION(__HANDLE__) \\r
+ (LL_ADC_GetResolution((__HANDLE__)->Instance))\r
+\r
+/**\r
+ * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").\r
+ * @param __HANDLE__ ADC handle\r
+ * @retval None\r
+ */\r
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) \r
+\r
+/**\r
+ * @brief Verification of ADC state: enabled or disabled.\r
+ * @param __HANDLE__ ADC handle\r
+ * @retval SET (ADC enabled) or RESET (ADC disabled)\r
+ */\r
+#define ADC_IS_ENABLE(__HANDLE__) \\r
+ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \\r
+ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \\r
+ ) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Check if conversion is on going on regular group.\r
+ * @param __HANDLE__ ADC handle\r
+ * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)\r
+ */\r
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \\r
+ (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))\r
+\r
+/**\r
+ * @brief Check if ADC clock mode is synchronous\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous)\r
+ */\r
+#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \\r
+ (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL) \\r
+ :((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL))\r
+\r
+/**\r
+ * @brief Simultaneously clear and set specific bits of the handle State.\r
+ * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),\r
+ * the first parameter is the ADC handle State, the second parameter is the\r
+ * bit field to clear, the third and last parameter is the bit field to set.\r
+ * @retval None\r
+ */\r
+#define ADC_STATE_CLR_SET MODIFY_REG\r
+\r
+/**\r
+ * @brief Verify that a given value is aligned with the ADC resolution range.\r
+ * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits).\r
+ * @param __ADC_VALUE__ value checked against the resolution. \r
+ * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)\r
+ */\r
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \\r
+ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))\r
+\r
+/**\r
+ * @brief Verify the length of the scheduled regular conversions group.\r
+ * @param __LENGTH__ number of programmed conversions. \r
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)\r
+ */\r
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))\r
+\r
+\r
+/**\r
+ * @brief Verify the number of scheduled regular conversions in discontinuous mode.\r
+ * @param NUMBER number of scheduled regular conversions in discontinuous mode. \r
+ * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)\r
+ */\r
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))\r
+\r
+\r
+/**\r
+ * @brief Verify the ADC clock setting.\r
+ * @param __ADC_CLOCK__ programmed ADC clock.\r
+ * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)\r
+ */\r
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) \r
+\r
+/**\r
+ * @brief Verify the ADC resolution setting.\r
+ * @param __RESOLUTION__ programmed ADC resolution.\r
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)\r
+ */\r
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \\r
+ ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \\r
+ ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \\r
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \\r
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) )\r
+/**\r
+ * @brief Verify the ADC resolution setting when limited to 8 bits.\r
+ * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits.\r
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)\r
+ */\r
+#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))\r
+\r
+/**\r
+ * @brief Verify the ADC scan mode.\r
+ * @param __SCAN_MODE__ programmed ADC scan mode.\r
+ * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)\r
+ */\r
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \\r
+ ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )\r
+\r
+/**\r
+ * @brief Verify the ADC edge trigger setting for regular group.\r
+ * @param __EDGE__ programmed ADC edge trigger setting.\r
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)\r
+ */\r
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )\r
+\r
+/**\r
+ * @brief Verify the ADC regular conversions external trigger.\r
+ * @param __REGTRIG__ programmed ADC regular conversions external trigger.\r
+ * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)\r
+ */\r
+#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \\r
+ ((__REGTRIG__) == ADC_SOFTWARE_START) )\r
+\r
+/**\r
+ * @brief Verify the ADC regular conversions check for converted data availability.\r
+ * @param __EOC_SELECTION__ converted data availability check.\r
+ * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)\r
+ */\r
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \\r
+ ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )\r
+\r
+/**\r
+ * @brief Verify the ADC regular conversions overrun handling.\r
+ * @param __OVR__ ADC regular conversions overrun handling.\r
+ * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)\r
+ */\r
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \\r
+ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )\r
+\r
+/**\r
+ * @brief Verify the ADC conversions sampling time.\r
+ * @param __TIME__ ADC conversions sampling time.\r
+ * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)\r
+ */\r
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) )\r
+\r
+/**\r
+ * @brief Verify the ADC regular channel setting.\r
+ * @param __CHANNEL__ programmed ADC regular channel.\r
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)\r
+ */\r
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \\r
+ ((__CHANNEL__) == ADC_REGULAR_RANK_16) )\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Constants ADC Private Constants\r
+ * @{\r
+ */\r
+\r
+/* Fixed timeout values for ADC conversion (including sampling time) */\r
+/* Maximum sampling time is 810.5 ADC clock cycle */\r
+/* Maximum conversion time is 16.5 + Maximum sampling time */\r
+/* or 16.5 + 810.5 = 827 ADC clock cycles */\r
+/* Minimum ADC Clock frequency is 0.35 MHz */\r
+/* Maximum conversion time is */\r
+/* 827 / 0.35 MHz = 2.36 ms */\r
+\r
+#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ \r
+\r
+/* Delay for temperature sensor stabilization time. */\r
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */\r
+/* Unit: us */\r
+#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)\r
+\r
+/* Delay for ADC voltage regulator startup time */\r
+/* Maximum delay is 10 microseconds */\r
+/* (refer device RM, parameter Tadcvreg_stup). */\r
+#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Macros ADC Exported Macros\r
+ * @{\r
+ */\r
+/* Macro for internal HAL driver usage, and possibly can be used into code of */\r
+/* final user. */\r
+\r
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset ADC handle state.\r
+ * @param __HANDLE__ ADC handle\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\r
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \\r
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)\r
+#endif\r
+\r
+/**\r
+ * @brief Enable ADC interrupt.\r
+ * @param __HANDLE__ ADC handle\r
+ * @param __INTERRUPT__ ADC Interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source\r
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source\r
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source\r
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source\r
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source\r
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source\r
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source\r
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)\r
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)\r
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)\r
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. \r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \\r
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable ADC interrupt.\r
+ * @param __HANDLE__ ADC handle\r
+ * @param __INTERRUPT__ ADC Interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source\r
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source\r
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source\r
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source\r
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source\r
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source\r
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source\r
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)\r
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)\r
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)\r
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. \r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \\r
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))\r
+\r
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.\r
+ * @param __HANDLE__ ADC handle\r
+ * @param __INTERRUPT__ ADC interrupt source to check\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source\r
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source\r
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source\r
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source\r
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source\r
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source\r
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source\r
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)\r
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)\r
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)\r
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. \r
+ * @retval State of interruption (SET or RESET)\r
+ */\r
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \\r
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))\r
+ \r
+/**\r
+ * @brief Check whether the specified ADC flag is set or not.\r
+ * @param __HANDLE__ ADC handle\r
+ * @param __FLAG__ ADC flag\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag \r
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag \r
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag \r
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag \r
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag \r
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag \r
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag \r
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)\r
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)\r
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)\r
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. \r
+ * @retval State of flag (TRUE or FALSE).\r
+ */\r
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \\r
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear the specified ADC flag.\r
+ * @param __HANDLE__ ADC handle\r
+ * @param __FLAG__ ADC flag\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag \r
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag \r
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag \r
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag \r
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag \r
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag \r
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag \r
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)\r
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)\r
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)\r
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. \r
+ * @retval None\r
+ */\r
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */\r
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Helper macro to get ADC channel number in decimal format\r
+ * from literals ADC_CHANNEL_x.\r
+ * @note Example:\r
+ * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)\r
+ * will return decimal number "4".\r
+ * @note The input can be a value from functions where a channel\r
+ * number is returned, either defined with number\r
+ * or with bitfield (only one bit must be set).\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref ADC_CHANNEL_0 (3)\r
+ * @arg @ref ADC_CHANNEL_1 (3)\r
+ * @arg @ref ADC_CHANNEL_2 (3)\r
+ * @arg @ref ADC_CHANNEL_3 (3)\r
+ * @arg @ref ADC_CHANNEL_4 (3)\r
+ * @arg @ref ADC_CHANNEL_5 (3)\r
+ * @arg @ref ADC_CHANNEL_6\r
+ * @arg @ref ADC_CHANNEL_7\r
+ * @arg @ref ADC_CHANNEL_8\r
+ * @arg @ref ADC_CHANNEL_9\r
+ * @arg @ref ADC_CHANNEL_10\r
+ * @arg @ref ADC_CHANNEL_11\r
+ * @arg @ref ADC_CHANNEL_12\r
+ * @arg @ref ADC_CHANNEL_13\r
+ * @arg @ref ADC_CHANNEL_14\r
+ * @arg @ref ADC_CHANNEL_15\r
+ * @arg @ref ADC_CHANNEL_16\r
+ * @arg @ref ADC_CHANNEL_17\r
+ * @arg @ref ADC_CHANNEL_18\r
+ * @arg @ref ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval Value between Min_Data=0 and Max_Data=18\r
+ */\r
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \\r
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))\r
+\r
+/**\r
+ * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x\r
+ * from number in decimal format.\r
+ * @note Example:\r
+ * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)\r
+ * will return a data equivalent to "ADC_CHANNEL_4".\r
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref ADC_CHANNEL_0 (3)\r
+ * @arg @ref ADC_CHANNEL_1 (3)\r
+ * @arg @ref ADC_CHANNEL_2 (3)\r
+ * @arg @ref ADC_CHANNEL_3 (3)\r
+ * @arg @ref ADC_CHANNEL_4 (3)\r
+ * @arg @ref ADC_CHANNEL_5 (3)\r
+ * @arg @ref ADC_CHANNEL_6\r
+ * @arg @ref ADC_CHANNEL_7\r
+ * @arg @ref ADC_CHANNEL_8\r
+ * @arg @ref ADC_CHANNEL_9\r
+ * @arg @ref ADC_CHANNEL_10\r
+ * @arg @ref ADC_CHANNEL_11\r
+ * @arg @ref ADC_CHANNEL_12\r
+ * @arg @ref ADC_CHANNEL_13\r
+ * @arg @ref ADC_CHANNEL_14\r
+ * @arg @ref ADC_CHANNEL_15\r
+ * @arg @ref ADC_CHANNEL_16\r
+ * @arg @ref ADC_CHANNEL_17\r
+ * @arg @ref ADC_CHANNEL_18\r
+ * @arg @ref ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n\r
+ * (1, 2) For ADC channel read back from ADC register,\r
+ * comparison with internal channel parameter to be done\r
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\r
+ */\r
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \\r
+ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))\r
+\r
+/**\r
+ * @brief Helper macro to determine whether the selected channel\r
+ * corresponds to literal definitions of driver.\r
+ * @note The different literal definitions of ADC channels are:\r
+ * - ADC internal channel:\r
+ * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...\r
+ * - ADC external channel (channel connected to a GPIO pin):\r
+ * ADC_CHANNEL_1, ADC_CHANNEL_2, ...\r
+ * @note The channel parameter must be a value defined from literal\r
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,\r
+ * ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),\r
+ * must not be a value from functions where a channel number is\r
+ * returned from ADC registers,\r
+ * because internal and external channels share the same channel\r
+ * number in ADC registers. The differentiation is made only with\r
+ * parameters definitions of driver.\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref ADC_CHANNEL_0 (3)\r
+ * @arg @ref ADC_CHANNEL_1 (3)\r
+ * @arg @ref ADC_CHANNEL_2 (3)\r
+ * @arg @ref ADC_CHANNEL_3 (3)\r
+ * @arg @ref ADC_CHANNEL_4 (3)\r
+ * @arg @ref ADC_CHANNEL_5 (3)\r
+ * @arg @ref ADC_CHANNEL_6\r
+ * @arg @ref ADC_CHANNEL_7\r
+ * @arg @ref ADC_CHANNEL_8\r
+ * @arg @ref ADC_CHANNEL_9\r
+ * @arg @ref ADC_CHANNEL_10\r
+ * @arg @ref ADC_CHANNEL_11\r
+ * @arg @ref ADC_CHANNEL_12\r
+ * @arg @ref ADC_CHANNEL_13\r
+ * @arg @ref ADC_CHANNEL_14\r
+ * @arg @ref ADC_CHANNEL_15\r
+ * @arg @ref ADC_CHANNEL_16\r
+ * @arg @ref ADC_CHANNEL_17\r
+ * @arg @ref ADC_CHANNEL_18\r
+ * @arg @ref ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).\r
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.\r
+ */\r
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \\r
+ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))\r
+\r
+/**\r
+ * @brief Helper macro to convert a channel defined from parameter\r
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,\r
+ * ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * to its equivalent parameter definition of a ADC external channel\r
+ * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).\r
+ * @note The channel parameter can be, additionally to a value\r
+ * defined from parameter definition of a ADC internal channel\r
+ * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * a value defined from parameter definition of\r
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)\r
+ * or a value from functions where a channel number is returned\r
+ * from ADC registers.\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref ADC_CHANNEL_0 (3)\r
+ * @arg @ref ADC_CHANNEL_1 (3)\r
+ * @arg @ref ADC_CHANNEL_2 (3)\r
+ * @arg @ref ADC_CHANNEL_3 (3)\r
+ * @arg @ref ADC_CHANNEL_4 (3)\r
+ * @arg @ref ADC_CHANNEL_5 (3)\r
+ * @arg @ref ADC_CHANNEL_6\r
+ * @arg @ref ADC_CHANNEL_7\r
+ * @arg @ref ADC_CHANNEL_8\r
+ * @arg @ref ADC_CHANNEL_9\r
+ * @arg @ref ADC_CHANNEL_10\r
+ * @arg @ref ADC_CHANNEL_11\r
+ * @arg @ref ADC_CHANNEL_12\r
+ * @arg @ref ADC_CHANNEL_13\r
+ * @arg @ref ADC_CHANNEL_14\r
+ * @arg @ref ADC_CHANNEL_15\r
+ * @arg @ref ADC_CHANNEL_16\r
+ * @arg @ref ADC_CHANNEL_17\r
+ * @arg @ref ADC_CHANNEL_18\r
+ * @arg @ref ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref ADC_CHANNEL_0\r
+ * @arg @ref ADC_CHANNEL_1\r
+ * @arg @ref ADC_CHANNEL_2\r
+ * @arg @ref ADC_CHANNEL_3\r
+ * @arg @ref ADC_CHANNEL_4\r
+ * @arg @ref ADC_CHANNEL_5\r
+ * @arg @ref ADC_CHANNEL_6\r
+ * @arg @ref ADC_CHANNEL_7\r
+ * @arg @ref ADC_CHANNEL_8\r
+ * @arg @ref ADC_CHANNEL_9\r
+ * @arg @ref ADC_CHANNEL_10\r
+ * @arg @ref ADC_CHANNEL_11\r
+ * @arg @ref ADC_CHANNEL_12\r
+ * @arg @ref ADC_CHANNEL_13\r
+ * @arg @ref ADC_CHANNEL_14\r
+ * @arg @ref ADC_CHANNEL_15\r
+ * @arg @ref ADC_CHANNEL_16\r
+ * @arg @ref ADC_CHANNEL_17\r
+ * @arg @ref ADC_CHANNEL_18\r
+ */\r
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \\r
+ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))\r
+\r
+/**\r
+ * @brief Helper macro to determine whether the internal channel\r
+ * selected is available on the ADC instance selected.\r
+ * @note The channel parameter must be a value defined from parameter\r
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,\r
+ * ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * must not be a value defined from parameter definition of\r
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)\r
+ * or a value from functions where a channel number is\r
+ * returned from ADC registers,\r
+ * because internal and external channels share the same channel\r
+ * number in ADC registers. The differentiation is made only with\r
+ * parameters definitions of driver.\r
+ * @param __ADC_INSTANCE__ ADC instance\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\r
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.\r
+ * Value "1" if the internal channel selected is available on the ADC instance selected.\r
+ */\r
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \\r
+ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))\r
+\r
+/**\r
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master\r
+ * or ADC slave from raw value with both ADC conversion data concatenated.\r
+ * @note This macro is intended to be used when multimode transfer by DMA\r
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().\r
+ * In this case the transferred data need to processed with this macro\r
+ * to separate the conversion data of ADC master and ADC slave.\r
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_MASTER\r
+ * @arg @ref LL_ADC_MULTI_SLAVE\r
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\r
+ */\r
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \\r
+ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))\r
+\r
+/**\r
+ * @brief Helper macro to select the ADC common instance\r
+ * to which is belonging the selected ADC instance.\r
+ * @note ADC common register instance can be used for:\r
+ * - Set parameters common to several ADC instances\r
+ * - Multimode (for devices with several ADC instances)\r
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.\r
+ * @param __ADCx__ ADC instance\r
+ * @retval ADC common register instance\r
+ */\r
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \\r
+ __LL_ADC_COMMON_INSTANCE((__ADCx__))\r
+\r
+/**\r
+ * @brief Helper macro to check if all ADC instances sharing the same\r
+ * ADC common instance are disabled.\r
+ * @note This check is required by functions with setting conditioned to\r
+ * ADC state:\r
+ * All ADC instances of the ADC common group must be disabled.\r
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.\r
+ * @note On devices with only 1 ADC common instance, parameter of this macro\r
+ * is useless and can be ignored (parameter kept for compatibility\r
+ * with devices featuring several ADC common instances).\r
+ * @param __ADCXY_COMMON__ ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance\r
+ * are disabled.\r
+ * Value "1" if at least one ADC instance sharing the same ADC common instance\r
+ * is enabled.\r
+ */\r
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \\r
+ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))\r
+\r
+/**\r
+ * @brief Helper macro to define the ADC conversion data full-scale digital\r
+ * value corresponding to the selected ADC resolution.\r
+ * @note ADC conversion data full-scale corresponds to voltage range\r
+ * determined by analog voltage references Vref+ and Vref-\r
+ * (refer to reference manual).\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref ADC_RESOLUTION_16B\r
+ * @arg @ref ADC_RESOLUTION_14B\r
+ * @arg @ref ADC_RESOLUTION_12B\r
+ * @arg @ref ADC_RESOLUTION_10B\r
+ * @arg @ref ADC_RESOLUTION_8B\r
+ * @retval ADC conversion data full-scale digital value\r
+ */\r
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \\r
+ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))\r
+\r
+/**\r
+ * @brief Helper macro to convert the ADC conversion data from\r
+ * a resolution to another resolution.\r
+ * @param __DATA__ ADC conversion data to be converted \r
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_RESOLUTION_16B\r
+ * @arg @ref ADC_RESOLUTION_14B\r
+ * @arg @ref ADC_RESOLUTION_12B\r
+ * @arg @ref ADC_RESOLUTION_10B\r
+ * @arg @ref ADC_RESOLUTION_8B\r
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_RESOLUTION_16B\r
+ * @arg @ref ADC_RESOLUTION_14B\r
+ * @arg @ref ADC_RESOLUTION_12B\r
+ * @arg @ref ADC_RESOLUTION_10B\r
+ * @arg @ref ADC_RESOLUTION_8B\r
+ * @retval ADC conversion data to the requested resolution\r
+ */\r
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\\r
+ __ADC_RESOLUTION_CURRENT__,\\r
+ __ADC_RESOLUTION_TARGET__) \\r
+ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\\r
+ (__ADC_RESOLUTION_CURRENT__),\\r
+ (__ADC_RESOLUTION_TARGET__))\r
+\r
+/**\r
+ * @brief Helper macro to calculate the voltage (unit: mVolt)\r
+ * corresponding to a ADC conversion data (unit: digital value).\r
+ * @note Analog reference voltage (Vref+) must be either known from\r
+ * user board environment or can be calculated using ADC measurement\r
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\r
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)\r
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)\r
+ * (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref ADC_RESOLUTION_16B\r
+ * @arg @ref ADC_RESOLUTION_14B\r
+ * @arg @ref ADC_RESOLUTION_12B\r
+ * @arg @ref ADC_RESOLUTION_10B\r
+ * @arg @ref ADC_RESOLUTION_8B\r
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)\r
+ */\r
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\\r
+ __ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\\r
+ (__ADC_DATA__),\\r
+ (__ADC_RESOLUTION__))\r
+\r
+/**\r
+ * @brief Helper macro to calculate analog reference voltage (Vref+)\r
+ * (unit: mVolt) from ADC conversion data of internal voltage\r
+ * reference VrefInt.\r
+ * @note Computation is using VrefInt calibration value\r
+ * stored in system memory for each device during production.\r
+ * @note This voltage depends on user board environment: voltage level\r
+ * connected to pin Vref+.\r
+ * On devices with small package, the pin Vref+ is not present\r
+ * and internally bonded to pin Vdda.\r
+ * @note On this STM32 serie, calibration data of internal voltage reference\r
+ * VrefInt corresponds to a resolution of 12 bits,\r
+ * this is the recommended ADC resolution to convert voltage of\r
+ * internal voltage reference VrefInt.\r
+ * Otherwise, this macro performs the processing to scale\r
+ * ADC conversion data to 12 bits.\r
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)\r
+ * of internal voltage reference VrefInt (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref ADC_RESOLUTION_16B\r
+ * @arg @ref ADC_RESOLUTION_14B\r
+ * @arg @ref ADC_RESOLUTION_12B\r
+ * @arg @ref ADC_RESOLUTION_10B\r
+ * @arg @ref ADC_RESOLUTION_8B\r
+ * @retval Analog reference voltage (unit: mV)\r
+ */\r
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\\r
+ (__ADC_RESOLUTION__))\r
+\r
+/**\r
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)\r
+ * from ADC conversion data of internal temperature sensor.\r
+ * @note Computation is using temperature sensor calibration values\r
+ * stored in system memory for each device during production.\r
+ * @note Calculation formula:\r
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)\r
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))\r
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP\r
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC\r
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)\r
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)\r
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature\r
+ * TEMP_DEGC_CAL1 (calibrated in factory)\r
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature\r
+ * TEMP_DEGC_CAL2 (calibrated in factory)\r
+ * Caution: Calculation relevancy under reserve that calibration\r
+ * parameters are correct (address and data).\r
+ * To calculate temperature using temperature sensor\r
+ * datasheet typical values (generic values less, therefore\r
+ * less accurate than calibrated values),\r
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().\r
+ * @note As calculation input, the analog reference voltage (Vref+) must be\r
+ * defined as it impacts the ADC LSB equivalent voltage.\r
+ * @note Analog reference voltage (Vref+) must be either known from\r
+ * user board environment or can be calculated using ADC measurement\r
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\r
+ * @note On this STM32 serie, calibration data of temperature sensor\r
+ * corresponds to a resolution of 12 bits,\r
+ * this is the recommended ADC resolution to convert voltage of\r
+ * temperature sensor.\r
+ * Otherwise, this macro performs the processing to scale\r
+ * ADC conversion data to 12 bits.\r
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)\r
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal\r
+ * temperature sensor (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature\r
+ * sensor voltage has been measured.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_RESOLUTION_16B\r
+ * @arg @ref ADC_RESOLUTION_14B\r
+ * @arg @ref ADC_RESOLUTION_12B\r
+ * @arg @ref ADC_RESOLUTION_10B\r
+ * @arg @ref ADC_RESOLUTION_8B\r
+ * @retval Temperature (unit: degree Celsius)\r
+ */\r
+#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\\r
+ __TEMPSENSOR_ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\\r
+ (__TEMPSENSOR_ADC_DATA__),\\r
+ (__ADC_RESOLUTION__))\r
+\r
+/**\r
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)\r
+ * from ADC conversion data of internal temperature sensor.\r
+ * @note Computation is using temperature sensor typical values\r
+ * (refer to device datasheet).\r
+ * @note Calculation formula:\r
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)\r
+ * / Avg_Slope + CALx_TEMP\r
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC\r
+ * (unit: digital value)\r
+ * Avg_Slope = temperature sensor slope\r
+ * (unit: uV/Degree Celsius)\r
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at\r
+ * temperature CALx_TEMP (unit: mV)\r
+ * Caution: Calculation relevancy under reserve the temperature sensor\r
+ * of the current device has characteristics in line with\r
+ * datasheet typical values.\r
+ * If temperature sensor calibration values are available on\r
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),\r
+ * temperature calculation will be more accurate using\r
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().\r
+ * @note As calculation input, the analog reference voltage (Vref+) must be\r
+ * defined as it impacts the ADC LSB equivalent voltage.\r
+ * @note Analog reference voltage (Vref+) must be either known from\r
+ * user board environment or can be calculated using ADC measurement\r
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\r
+ * @note ADC measurement data must correspond to a resolution of 12bits\r
+ * (full scale digital value 4095). If not the case, the data must be\r
+ * preliminarily rescaled to an equivalent resolution of 12 bits.\r
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).\r
+ * On STM32H7, refer to device datasheet parameter "Avg_Slope".\r
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).\r
+ * On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).\r
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)\r
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)\r
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref ADC_RESOLUTION_16B\r
+ * @arg @ref ADC_RESOLUTION_14B\r
+ * @arg @ref ADC_RESOLUTION_12B\r
+ * @arg @ref ADC_RESOLUTION_10B\r
+ * @arg @ref ADC_RESOLUTION_8B\r
+ * @retval Temperature (unit: degree Celsius)\r
+ */\r
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\\r
+ __TEMPSENSOR_TYP_CALX_V__,\\r
+ __TEMPSENSOR_CALX_TEMP__,\\r
+ __VREFANALOG_VOLTAGE__,\\r
+ __TEMPSENSOR_ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\\r
+ (__TEMPSENSOR_TYP_CALX_V__),\\r
+ (__TEMPSENSOR_CALX_TEMP__),\\r
+ (__VREFANALOG_VOLTAGE__),\\r
+ (__TEMPSENSOR_ADC_DATA__),\\r
+ (__ADC_RESOLUTION__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include ADC HAL Extended module */\r
+#include "stm32h7xx_hal_adc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup ADC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC_Exported_Functions_Group1\r
+ * @brief Initialization and Configuration functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);\r
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);\r
+\r
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC_Exported_Functions_Group2\r
+ * @brief IO operation functions\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);\r
+\r
+/* Non-blocking mode: Interruption */\r
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);\r
+\r
+/* Non-blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);\r
+\r
+/* ADC retrieve conversion value intended to be used with polling or interruption */\r
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);\r
+\r
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */\r
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);\r
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral State functions *************************************************/\r
+/** @addtogroup ADC_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);\r
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions -----------------------------------------------------------*/\r
+/** @addtogroup ADC_Private_Functions ADC Private Functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);\r
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);\r
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);\r
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+void ADC_DMAError(DMA_HandleTypeDef *hdma);\r
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32H7xx_HAL_ADC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_adc_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of ADC HAL extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_ADC_EX_H\r
+#define STM32H7xx_HAL_ADC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADCEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief ADC Injected Conversion Oversampling structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Ratio; /*!< Configures the oversampling ratio.\r
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */\r
+ \r
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.\r
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */\r
+}ADC_InjOversamplingTypeDef; \r
+\r
+/** \r
+ * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected\r
+ * @note Parameters of this structure are shared within 2 scopes:\r
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset\r
+ * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,\r
+ * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.\r
+ * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.\r
+ * ADC state can be either:\r
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')\r
+ * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.\r
+ * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.\r
+ * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going \r
+ * on ADC groups regular and injected.\r
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed\r
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.\r
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL\r
+ Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */\r
+\r
+ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.\r
+ This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.\r
+ Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by \r
+ the new channel setting (or parameter number of conversions adjusted) */\r
+\r
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.\r
+ Unit: ADC clock cycles.\r
+ Conversion time is the addition of sampling time and processing time\r
+ (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).\r
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.\r
+ Caution: This parameter applies to a channel that can be used in a regular and/or injected group.\r
+ It overwrites the last setting.\r
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\r
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\r
+ Refer to device datasheet for timings values. */\r
+\r
+ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.\r
+ In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).\r
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.\r
+ This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.\r
+ Caution: This parameter applies to a channel that can be used in a regular and/or injected group.\r
+ It overwrites the last setting.\r
+ Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.\r
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.\r
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).\r
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case \r
+ of another parameter update on the fly) */\r
+\r
+ uint32_t InjectedOffsetNumber; /*!< Selects the offset number.\r
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.\r
+ Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */\r
+\r
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.\r
+ Offset value must be a positive number.\r
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number\r
+ between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.\r
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled \r
+ without continuous mode or external trigger that could launch a conversion). */\r
+\r
+ uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not.\r
+ This parameter is applied only for 16-bit or 8-bit resolution.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.\r
+ This parameter is applied only for 16-bit or 8-bit resolution.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.\r
+ This parameter can be a value of @ref ADCEx_Left_Bit_Shift */\r
+\r
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.\r
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.\r
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r
+ configure a channel on injected group can impact the configuration of other channels previously set. */\r
+\r
+ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence\r
+ (main sequence subdivided in successive parts).\r
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\r
+ Discontinuous mode can be enabled only if continuous mode is disabled. \r
+ This parameter can be set to ENABLE or DISABLE.\r
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).\r
+ Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).\r
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r
+ configure a channel on injected group can impact the configuration of other channels previously set. */\r
+\r
+ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one\r
+ This parameter can be set to ENABLE or DISABLE. \r
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)\r
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)\r
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.\r
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.\r
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\r
+ configure a channel on injected group can impact the configuration of other channels previously set. */\r
+\r
+ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.\r
+ This parameter can be set to ENABLE or DISABLE.\r
+ If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a\r
+ new injected context is set when queue is full, error is triggered by interruption and through function \r
+ 'HAL_ADCEx_InjectedQueueOverflowCallback'.\r
+ Caution: This feature request that the sequence is fully configured before injected conversion start.\r
+ Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.\r
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r
+ configure a channel on injected group can impact the configuration of other channels previously set.\r
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */\r
+\r
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.\r
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.\r
+ This parameter can be a value of @ref ADC_injected_external_trigger_source.\r
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\r
+ configure a channel on injected group can impact the configuration of other channels previously set. */\r
+\r
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.\r
+ This parameter can be a value of @ref ADC_injected_external_trigger_edge.\r
+ If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.\r
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r
+ configure a channel on injected group can impact the configuration of other channels previously set. */\r
+\r
+ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.\r
+ This parameter can be set to ENABLE or DISABLE.\r
+ Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */\r
+\r
+ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.\r
+ Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. \r
+ Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */\r
+}ADC_InjectionConfTypeDef;\r
+\r
+/** \r
+ * @brief Structure definition of ADC multimode\r
+ * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).\r
+ * Both Master and Slave ADCs must be disabled.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. \r
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */\r
+\r
+ uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format:\r
+ This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */\r
+\r
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.\r
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.\r
+ Delay range depends on selected resolution: \r
+ from 1 to 9 clock cycles for 16 bits,\r
+ from 1 to 9 clock cycles for 14 bits\r
+ from 1 to 8 clock cycles for 12 bits\r
+ from 1 to 6 clock cycles for 10 bits\r
+ from 1 to 6 clock cycles for 8 bits */\r
+}ADC_MultiModeTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source\r
+ * @{\r
+ */\r
+/* ADC group regular trigger sources for all ADC instances */\r
+#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */\r
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)\r
+ * @{\r
+ */\r
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ \r
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ \r
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ \r
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending\r
+ * @{\r
+ */\r
+#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */\r
+#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number\r
+ * @{\r
+ */\r
+#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */\r
+#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks\r
+ * @{\r
+ */\r
+#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */\r
+#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */\r
+#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */\r
+#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode\r
+ * @{\r
+ */\r
+#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */\r
+#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */\r
+#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */\r
+#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */\r
+#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */\r
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */\r
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */\r
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */\r
+\r
+/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting\r
+ * @{\r
+ */\r
+#define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */\r
+#define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */\r
+#define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases\r
+ * @{\r
+ */\r
+#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */\r
+#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */\r
+#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */\r
+#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */\r
+#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */\r
+#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */\r
+#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */\r
+#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */\r
+#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups\r
+ * @{\r
+ */\r
+#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */\r
+#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/\r
+#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_CFGR_fields ADCx CFGR fields\r
+ * @{\r
+ */\r
+#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\\r
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\\r
+ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\\r
+ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\\r
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\\r
+ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields\r
+ * @{\r
+ */\r
+#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\\r
+ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\\r
+ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\\r
+ ADC_SMPR1_SMP0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields \r
+ * @{\r
+ */\r
+/* ADC_CFGR fields of parameters that can be updated when no conversion\r
+ (neither regular nor injected) is on-going */\r
+#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(DFSDM1_Channel0)\r
+/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data\r
+ * @{\r
+ */\r
+#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */\r
+#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Force ADC instance in multimode mode independent (multimode disable).\r
+ * @note This macro must be used only in case of transition from multimode\r
+ * to mode independent and in case of unknown previous state,\r
+ * to ensure ADC configuration is in mode independent.\r
+ * @note Standard way of multimode configuration change is done from\r
+ * HAL ADC handle of ADC master using function\r
+ * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".\r
+ * Usage of this macro is not the Standard way of multimode \r
+ * configuration and can lead to have HAL ADC handles status \r
+ * misaligned. Usage of this macro must be limited to cases \r
+ * mentionned above.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval None\r
+ */\r
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \\r
+ LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros\r
+ * @{\r
+ */\r
+/* Macro reserved for internal HAL driver usage, not intended to be used in */\r
+/* code of final user. */\r
+\r
+/**\r
+ * @brief Test if conversion trigger of injected group is software start\r
+ * or external trigger.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval SET (software start) or RESET (external trigger).\r
+ */\r
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \\r
+ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)\r
+\r
+/**\r
+ * @brief Check if conversion is on going on regular or injected groups.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval SET (conversion is on going) or RESET (no conversion is on going).\r
+ */\r
+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \\r
+ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \\r
+ ) ? RESET : SET)\r
+\r
+/**\r
+ * @brief Check if conversion is on going on injected group.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)\r
+ */\r
+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \\r
+ (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))\r
+\r
+/**\r
+ * @brief Check whether or not ADC is independent.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @note When multimode feature is not available, the macro always returns SET. \r
+ * @retval SET (ADC is independent) or RESET (ADC is not).\r
+ */\r
+#define ADC_IS_INDEPENDENT(__HANDLE__) \\r
+ ( ( ( ((__HANDLE__)->Instance) == ADC3) \\r
+ )? \\r
+ SET \\r
+ : \\r
+ RESET \\r
+ )\r
+\r
+/**\r
+ * @brief Set the selected injected Channel rank.\r
+ * @param __CHANNELNB__ Channel number.\r
+ * @param __RANKNB__ Rank number.\r
+ * @retval None\r
+ */\r
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))\r
+\r
+/**\r
+ * @brief Configure ADC injected context queue\r
+ * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)\r
+\r
+/**\r
+ * @brief Configure ADC discontinuous conversion mode for injected group\r
+ * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)\r
+\r
+/**\r
+ * @brief Configure ADC discontinuous conversion mode for regular group\r
+ * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)\r
+\r
+/**\r
+ * @brief Configure the number of discontinuous conversions for regular group.\r
+ * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.\r
+ * @retval None\r
+ */\r
+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)\r
+\r
+/**\r
+ * @brief Configure the ADC auto delay mode.\r
+ * @param __AUTOWAIT__ Auto delay bit enable or disable.\r
+ * @retval None\r
+ */\r
+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)\r
+\r
+/**\r
+ * @brief Configure ADC continuous conversion mode.\r
+ * @param __CONTINUOUS_MODE__ Continuous mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)\r
+\r
+/**\r
+ * @brief Enable the ADC DMA continuous request.\r
+ * @param __DMACONTREQ_MODE__: DMA continuous request mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))\r
+\r
+/**\r
+ * @brief Configure the channel number into offset OFRx register.\r
+ * @param __CHANNEL__ ADC Channel.\r
+ * @retval None\r
+ */\r
+#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)\r
+\r
+/**\r
+ * @brief Configure the channel number into differential mode selection register.\r
+ * @param __CHANNEL__ ADC Channel.\r
+ * @retval None\r
+ */\r
+#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) \r
+\r
+/**\r
+ * @brief Configure calibration factor in differential mode to be set into calibration register.\r
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.\r
+ * @retval None\r
+ */\r
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)\r
+\r
+/**\r
+ * @brief Calibration factor in differential mode to be retrieved from calibration register.\r
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.\r
+ * @retval None\r
+ */\r
+#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)\r
+\r
+/**\r
+ * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.\r
+ * @param __THRESHOLD__ Threshold value.\r
+ * @retval None\r
+ */\r
+#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)\r
+\r
+/**\r
+ * @brief Configure the ADC DMA continuous request for ADC multimode.\r
+ * @param __DMACONTREQ_MODE__ DMA continuous request mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)\r
+\r
+/**\r
+ * @brief Shift the offset in function of the selected ADC resolution.\r
+ * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0\r
+ * If resolution 16 bits, no shift.\r
+ * If resolution 14 bits, shift of 2 ranks on the left.\r
+ * If resolution 12 bits, shift of 4 ranks on the left.\r
+ * If resolution 10 bits, shift of 6 ranks on the left.\r
+ * If resolution 8 bits, shift of 8 ranks on the left.\r
+ * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))\r
+ * @param __HANDLE__: ADC handle\r
+ * @param __OFFSET__: Value to be shifted\r
+ * @retval None\r
+ */\r
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \\r
+ (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \\r
+ ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \\r
+ : \\r
+ ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \\r
+ ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \\r
+ : \\r
+ ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \\r
+ )\r
+\r
+/**\r
+ * @brief Shift the AWD1 threshold in function of the selected ADC resolution.\r
+ * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.\r
+ * If resolution 16 bits, no shift.\r
+ * If resolution 14 bits, shift of 2 ranks on the left.\r
+ * If resolution 12 bits, shift of 4 ranks on the left.\r
+ * If resolution 10 bits, shift of 6 ranks on the left.\r
+ * If resolution 8 bits, shift of 8 ranks on the left.\r
+ * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))\r
+ * @param __HANDLE__: ADC handle\r
+ * @param __THRESHOLD__: Value to be shifted\r
+ * @retval None\r
+ */\r
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \\r
+ (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \\r
+ ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \\r
+ : \\r
+ ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \\r
+ ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \\r
+ : \\r
+ ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \\r
+ ) \r
+\r
+/**\r
+ * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.\r
+ * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.\r
+ * If resolution 16 bits, no shift.\r
+ * If resolution 14 bits, shift of 2 ranks on the left.\r
+ * If resolution 12 bits, shift of 4 ranks on the left.\r
+ * If resolution 10 bits, shift of 6 ranks on the left.\r
+ * If resolution 8 bits, shift of 8 ranks on the left.\r
+ * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))\r
+ * @param __HANDLE__: ADC handle\r
+ * @param __THRESHOLD__: Value to be shifted\r
+ * @retval None\r
+ */\r
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \\r
+ (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \\r
+ ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \\r
+ : \\r
+ ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \\r
+ ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \\r
+ : \\r
+ ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \\r
+ )\r
+/**\r
+ * @brief Clear Common Control Register.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval None\r
+ */\r
+/**\r
+ * @brief Report common register to ADC1 and ADC2\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval Common control register\r
+ */\r
+#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)\r
+/**\r
+ * @brief Report common register to ADC3\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval Common control register\r
+ */\r
+#define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)\r
+/**\r
+ * @brief Report Master Instance\r
+ * @param __HANDLE__: ADC handle\r
+ * @note return same instance if ADC of input handle is independent ADC\r
+ * @retval Master Instance\r
+ */\r
+#define ADC_MASTER_REGISTER(__HANDLE__) \\r
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \\r
+ )? \\r
+ ((__HANDLE__)->Instance) \\r
+ : \\r
+ (ADC1) \\r
+ )\r
+\r
+/**\r
+ * @brief Check whether or not dual regular conversions are enabled\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)\r
+ */\r
+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \\r
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \\r
+ )? \\r
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \\r
+ : \\r
+ RESET \\r
+ )\r
+\r
+/**\r
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)\r
+ */\r
+#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \\r
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \\r
+ )? \\r
+ SET \\r
+ : \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \\r
+ )\r
+\r
+/**\r
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)\r
+ */\r
+#define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \\r
+ ( ( ((__HANDLE__)->Instance == ADC3) \\r
+ )? \\r
+ SET \\r
+ : \\r
+ ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \\r
+ )\r
+\r
+/**\r
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)\r
+ */\r
+\r
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \\r
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \\r
+ )? \\r
+ SET \\r
+ : \\r
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))\r
+\r
+/**\r
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)\r
+ */\r
+\r
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \\r
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \\r
+ )? \\r
+ SET \\r
+ : \\r
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \\r
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))\r
+\r
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \\r
+ ADC_CCR_PRESC | \\r
+ ADC_CCR_VBATEN | \\r
+ ADC_CCR_TSEN | \\r
+ ADC_CCR_VREFEN | \\r
+ ADC_CCR_DAMDF | \\r
+ ADC_CCR_DELAY | \\r
+ ADC_CCR_DUAL )\r
+\r
+/**\r
+ * @brief Set handle instance of the ADC slave associated to the ADC master.\r
+ * @param __HANDLE_MASTER__ ADC master handle.\r
+ * @param __HANDLE_SLAVE__ ADC slave handle.\r
+ * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.\r
+ * @retval None\r
+ */ \r
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \\r
+ ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )\r
+ \r
+\r
+/**\r
+ * @brief Verify the ADC instance connected to the temperature sensor.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)\r
+ */\r
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)\r
+\r
+/**\r
+ * @brief Verify the ADC instance connected to the battery voltage VBAT.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)\r
+ */\r
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)\r
+\r
+/**\r
+ * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.\r
+ * @param __HANDLE__ ADC handle.\r
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)\r
+ */\r
+#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)\r
+\r
+/**\r
+ * @brief Verify the length of scheduled injected conversions group.\r
+ * @param __LENGTH__ number of programmed conversions. \r
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)\r
+ */\r
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))\r
+\r
+/**\r
+ * @brief Calibration factor size verification (7 bits maximum).\r
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.\r
+ * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)\r
+ */\r
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))\r
+\r
+\r
+/**\r
+ * @brief Verify the ADC channel setting.\r
+ * @param __CHANNEL__ programmed ADC channel. \r
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)\r
+ */\r
+#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_1) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_15) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_18) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_19) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \\r
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \\r
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) )\r
+\r
+/**\r
+ * @brief Verify the ADC channel setting in differential mode for ADC1.\r
+ * @param __CHANNEL__: programmed ADC channel.\r
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)\r
+ */\r
+#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_2) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_3) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_4) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_5) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_10) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_11) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_12) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_16) ||\\r
+ ((__CHANNEL__) == ADC_CHANNEL_18) )\r
+\r
+/**\r
+ * @brief Verify the ADC channel setting in differential mode for ADC2.\r
+ * @param __CHANNEL__: programmed ADC channel.\r
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)\r
+ */\r
+#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_18) )\r
+\r
+/**\r
+ * @brief Verify the ADC channel setting in differential mode for ADC3.\r
+ * @param __CHANNEL__: programmed ADC channel.\r
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)\r
+ */\r
+#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_15) )\r
+\r
+/**\r
+ * @brief Verify the ADC single-ended input or differential mode setting.\r
+ * @param __SING_DIFF__ programmed channel setting. \r
+ * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)\r
+ */\r
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \\r
+ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )\r
+\r
+/**\r
+ * @brief Verify the ADC offset management setting.\r
+ * @param __OFFSET_NUMBER__ ADC offset management. \r
+ * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)\r
+ */\r
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \\r
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \\r
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \\r
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \\r
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) \r
+\r
+/**\r
+ * @brief Verify the ADC injected channel setting.\r
+ * @param __CHANNEL__ programmed ADC injected channel. \r
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)\r
+ */\r
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \\r
+ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \\r
+ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \\r
+ ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) \r
+\r
+/**\r
+ * @brief Verify the ADC injected conversions external trigger.\r
+ * @param __INJTRIG__ programmed ADC injected conversions external trigger.\r
+ * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)\r
+ */\r
+#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \\r
+ \\r
+ ((__INJTRIG__) == ADC_SOFTWARE_START) )\r
+\r
+/**\r
+ * @brief Verify the ADC edge trigger setting for injected group.\r
+ * @param __EDGE__ programmed ADC edge trigger setting.\r
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)\r
+ */ \r
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) \r
+\r
+/**\r
+ * @brief Verify the ADC multimode setting.\r
+ * @param __MODE__ programmed ADC multimode setting.\r
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+ */ \r
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \\r
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \\r
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \\r
+ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \\r
+ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \\r
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \\r
+ ((__MODE__) == ADC_DUALMODE_INTERL) || \\r
+ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )\r
+\r
+/**\r
+ * @brief Verify the ADC dual data mode setting.\r
+ * @param MODE: programmed ADC dual mode setting.\r
+ * @retval SET (MODE is valid) or RESET (MODE is invalid)\r
+ */\r
+#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \\r
+ ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \\r
+ ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) )\r
+\r
+/**\r
+ * @brief Verify the ADC multimode delay setting.\r
+ * @param __DELAY__ programmed ADC multimode delay setting.\r
+ * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)\r
+ */\r
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) )\r
+\r
+/**\r
+ * @brief Verify the ADC analog watchdog setting.\r
+ * @param __WATCHDOG__ programmed ADC analog watchdog setting.\r
+ * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)\r
+ */\r
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) \r
+\r
+/**\r
+ * @brief Verify the ADC analog watchdog mode setting.\r
+ * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.\r
+ * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)\r
+ */\r
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \\r
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \\r
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \\r
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \\r
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \\r
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \\r
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) \r
+\r
+/**\r
+ * @brief Verify the ADC conversion (regular or injected or both).\r
+ * @param __CONVERSION__ ADC conversion group.\r
+ * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)\r
+ */\r
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \\r
+ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \\r
+ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )\r
+\r
+/**\r
+ * @brief Verify the ADC event type.\r
+ * @param __EVENT__ ADC event.\r
+ * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)\r
+ */\r
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \\r
+ ((__EVENT__) == ADC_AWD_EVENT) || \\r
+ ((__EVENT__) == ADC_AWD2_EVENT) || \\r
+ ((__EVENT__) == ADC_AWD3_EVENT) || \\r
+ ((__EVENT__) == ADC_OVR_EVENT) || \\r
+ ((__EVENT__) == ADC_JQOVF_EVENT) ) \r
+\r
+/**\r
+ * @brief Verify the ADC oversampling ratio. \r
+ * @param RATIO: programmed ADC oversampling ratio.\r
+ * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)\r
+ */\r
+#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024UL)\r
+\r
+/**\r
+ * @brief Verify the ADC oversampling shift. \r
+ * @param __SHIFT__ programmed ADC oversampling shift.\r
+ * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)\r
+ */\r
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \\r
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))\r
+\r
+/**\r
+ * @brief Verify the ADC oversampling triggered mode. \r
+ * @param __MODE__ programmed ADC oversampling triggered mode. \r
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+ */\r
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \\r
+ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) \r
+\r
+/**\r
+ * @brief Verify the ADC oversampling regular conversion resumed or continued mode. \r
+ * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. \r
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+ */\r
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \\r
+ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) \r
+\r
+/**\r
+ * @brief Verify the DFSDM mode configuration. \r
+ * @param __HANDLE__ ADC handle. \r
+ * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For\r
+ * this reason, the input parameter is the ADC handle and not the configuration parameter\r
+ * directly. \r
+ * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)\r
+ */\r
+#if defined(DFSDM1_Channel0)\r
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \\r
+ ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )\r
+#else\r
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)\r
+#endif\r
+\r
+/**\r
+ * @brief Return the DFSDM configuration mode.\r
+ * @param __HANDLE__ ADC handle. \r
+ * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). \r
+ * For this reason, the input parameter is the ADC handle and not the configuration parameter\r
+ * directly. \r
+ * @retval DFSDM configuration mode\r
+ */\r
+#if defined(DFSDM1_Channel0)\r
+#define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)\r
+#else \r
+#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup ADCEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+\r
+/* ADC calibration */\r
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff);\r
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);\r
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer);\r
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);\r
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);\r
+\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r
+\r
+/* Non-blocking mode: Interruption */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);\r
+\r
+/* ADC multimode */\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);\r
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);\r
+\r
+/* ADC retrieve conversion value intended to be used with polling or interruption */\r
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);\r
+\r
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */\r
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);\r
+\r
+/* ADC group regular conversions stop */\r
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADCEx_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);\r
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_ADC_EX_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_cortex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of CORTEX HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_CORTEX_H\r
+#define STM32H7xx_HAL_CORTEX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CORTEX\r
+ * @{\r
+ */\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
+ * @brief MPU Region initialization structure\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t Enable; /*!< Specifies the status of the region.\r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */\r
+ uint8_t Number; /*!< Specifies the number of the region to protect.\r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */\r
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */\r
+ uint8_t Size; /*!< Specifies the size of the region to protect.\r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */\r
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.\r
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */\r
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.\r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */\r
+ uint8_t DisableExec; /*!< Specifies the instruction access status.\r
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */\r
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.\r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */\r
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.\r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */\r
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.\r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */\r
+}MPU_Region_InitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r
+ * @{\r
+ */\r
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source\r
+ * @{\r
+ */\r
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)\r
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r
+ * @{\r
+ */\r
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)\r
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)\r
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)\r
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
+ * @{\r
+ */\r
+#define MPU_REGION_ENABLE ((uint8_t)0x01)\r
+#define MPU_REGION_DISABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
+ * @{\r
+ */\r
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)\r
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r
+ * @{\r
+ */\r
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)\r
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)\r
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
+ * @{\r
+ */\r
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)\r
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)\r
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)\r
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)\r
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)\r
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)\r
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)\r
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)\r
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)\r
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)\r
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)\r
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)\r
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)\r
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)\r
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)\r
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)\r
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)\r
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)\r
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)\r
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)\r
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)\r
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)\r
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)\r
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)\r
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)\r
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)\r
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)\r
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes\r
+ * @{\r
+ */\r
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)\r
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)\r
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)\r
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)\r
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)\r
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
+ * @{\r
+ */\r
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)\r
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)\r
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)\r
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)\r
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)\r
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)\r
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)\r
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)\r
+#if !defined(CORE_CM4)\r
+#define MPU_REGION_NUMBER8 ((uint8_t)0x08)\r
+#define MPU_REGION_NUMBER9 ((uint8_t)0x09)\r
+#define MPU_REGION_NUMBER10 ((uint8_t)0x0A)\r
+#define MPU_REGION_NUMBER11 ((uint8_t)0x0B)\r
+#define MPU_REGION_NUMBER12 ((uint8_t)0x0C)\r
+#define MPU_REGION_NUMBER13 ((uint8_t)0x0D)\r
+#define MPU_REGION_NUMBER14 ((uint8_t)0x0E)\r
+#define MPU_REGION_NUMBER15 ((uint8_t)0x0F)\r
+#endif /* !defined(CORE_CM4) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported Macros -----------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier\r
+ * @{\r
+ */\r
+#define CM7_CPUID ((uint32_t)0x00000003)\r
+\r
+#if defined(DUAL_CORE)\r
+#define CM4_CPUID ((uint32_t)0x00000001)\r
+#endif /*DUAL_CORE*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CORTEX_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SystemReset(void);\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+#if (__MPU_PRESENT == 1)\r
+void HAL_MPU_Enable(uint32_t MPU_Control);\r
+void HAL_MPU_Disable(void);\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
+#endif /* __MPU_PRESENT */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
+void HAL_SYSTICK_IRQHandler(void);\r
+void HAL_SYSTICK_Callback(void);\r
+uint32_t HAL_GetCurrentCPUID(void);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
+ * @{\r
+ */\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)\r
+\r
+#define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00)\r
+\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
+\r
+#if (__MPU_PRESENT == 1)\r
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
+ ((STATE) == MPU_REGION_DISABLE))\r
+\r
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
+\r
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
+\r
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
+\r
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
+\r
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \\r
+ ((TYPE) == MPU_TEX_LEVEL1) || \\r
+ ((TYPE) == MPU_TEX_LEVEL2))\r
+\r
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
+\r
+#if !defined(CORE_CM4)\r
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER1) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER2) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER3) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER4) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER5) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER6) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER7) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER8) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER9) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER10) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER11) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER12) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER13) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER14) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER15))\r
+#else\r
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER1) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER2) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER3) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER4) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER5) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER6) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER7))\r
+#endif /* !defined(CORE_CM4) */\r
+\r
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4GB))\r
+\r
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_CORTEX_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_def.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains HAL common defines, enumeration, macros and\r
+ * structures definitions.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_DEF\r
+#define STM32H7xx_HAL_DEF\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx.h"\r
+//#include "Legacy/stm32_hal_legacy.h"\r
+#include <stddef.h>\r
+#include <math.h>\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief HAL Status structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_OK = 0x00,\r
+ HAL_ERROR = 0x01,\r
+ HAL_BUSY = 0x02,\r
+ HAL_TIMEOUT = 0x03\r
+} HAL_StatusTypeDef;\r
+\r
+/**\r
+ * @brief HAL Lock structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_UNLOCKED = 0x00,\r
+ HAL_LOCKED = 0x01\r
+} HAL_LockTypeDef;\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+#define HAL_MAX_DELAY 0xFFFFFFFFU\r
+\r
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))\r
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)\r
+\r
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\r
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \\r
+ } while(0)\r
+\r
+#define UNUSED(x) ((void)(x))\r
+\r
+/** @brief Reset the Handle's State field.\r
+ * @param __HANDLE__: specifies the Peripheral Handle.\r
+ * @note This macro can be used for the following purpose:\r
+ * - When the Handle is declared as local variable; before passing it as parameter\r
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro\r
+ * to set to 0 the Handle's "State" field.\r
+ * Otherwise, "State" field may have any random value and the first time the function\r
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
+ * (i.e. HAL_PPP_MspInit() will not be executed).\r
+ * - When there is a need to reconfigure the low level hardware: instead of calling\r
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
+ * @retval None\r
+ */\r
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)\r
+\r
+#if (USE_RTOS == 1)\r
+ #error " USE_RTOS should be 0 in the current HAL release "\r
+#else\r
+ #define __HAL_LOCK(__HANDLE__) \\r
+ do{ \\r
+ if((__HANDLE__)->Lock == HAL_LOCKED) \\r
+ { \\r
+ return HAL_BUSY; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Lock = HAL_LOCKED; \\r
+ } \\r
+ }while (0)\r
+\r
+ #define __HAL_UNLOCK(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \\r
+ }while (0)\r
+#endif /* USE_RTOS */\r
+\r
+#if defined ( __GNUC__ )\r
+ #ifndef __weak\r
+ #define __weak __attribute__((weak))\r
+ #endif /* __weak */\r
+ #ifndef __packed\r
+ #define __packed __attribute__((__packed__))\r
+ #endif /* __packed */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
+#if defined (__GNUC__) /* GNU Compiler */\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END __attribute__ ((aligned (4)))\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN\r
+ #define __ALIGN_BEGIN\r
+ #endif /* __ALIGN_BEGIN */\r
+#else\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN\r
+ #if defined (__CC_ARM) /* ARM Compiler */\r
+ #define __ALIGN_BEGIN __align(4)\r
+ #elif defined (__ICCARM__) /* IAR Compiler */\r
+ #define __ALIGN_BEGIN\r
+ #endif /* __CC_ARM */\r
+ #endif /* __ALIGN_BEGIN */\r
+#endif /* __GNUC__ */\r
+\r
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */\r
+#if defined (__GNUC__) /* GNU Compiler */\r
+ #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))\r
+#elif defined (__ICCARM__) /* IAR Compiler */\r
+ #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf\r
+#elif defined (__CC_ARM) /* ARM Compiler */\r
+ #define ALIGN_32BYTES(buf) __align(32) buf\r
+#endif\r
+\r
+/**\r
+ * @brief __RAM_FUNC definition\r
+ */\r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options.\r
+ Functions that are executed in RAM should reside in a separate source module.\r
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'\r
+ area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
+ dialog.\r
+*/\r
+#define __RAM_FUNC\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
+*/\r
+#define __RAM_FUNC __ramfunc\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute\r
+ "__attribute__((section(".RamFunc")))".\r
+*/\r
+#define __RAM_FUNC __attribute__((section(".RamFunc")))\r
+\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_DEF */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_dma.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of DMA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_DMA_H\r
+#define STM32H7xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+ * @brief DMA Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Request; /*!< Specifies the request selected for the specified stream.\r
+ This parameter can be a value of @ref DMA_Request_selection */\r
+\r
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,\r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Stream */\r
+\r
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_Priority_level */\r
+\r
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\r
+ This parameter can be a value of @ref DMA_FIFO_direct_mode\r
+ @note The Direct mode (FIFO mode disabled) cannot be used if the\r
+ memory-to-memory data transfer is configured on the selected stream */\r
+\r
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.\r
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */\r
+\r
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.\r
+ It specifies the amount of data to be transferred in a single non interruptible\r
+ transaction.\r
+ This parameter can be a value of @ref DMA_Memory_burst\r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+\r
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.\r
+ It specifies the amount of data to be transferred in a single non interruptible\r
+ transaction.\r
+ This parameter can be a value of @ref DMA_Peripheral_burst\r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+}DMA_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMA State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */\r
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */\r
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */\r
+ HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */\r
+ HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMA Transfer complete level structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMA Callbacks IDs structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */\r
+ HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */\r
+ HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */\r
+ HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */\r
+ HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */\r
+ HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */\r
+}HAL_DMA_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief DMA handle Structure definition\r
+ */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+ void *Instance; /*!< Register base address */\r
+\r
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA locking object */\r
+\r
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
+\r
+ void *Parent; /*!< Parent object state */\r
+\r
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
+\r
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
+\r
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */\r
+\r
+ void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */\r
+\r
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
+\r
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA Error code */\r
+\r
+ uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */\r
+\r
+ uint32_t StreamIndex; /*!< DMA Stream Index */\r
+\r
+ DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */\r
+\r
+ DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */\r
+\r
+ uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */\r
+\r
+\r
+ DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */\r
+\r
+ DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */\r
+\r
+ uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */\r
+\r
+}DMA_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @brief DMA Exported constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+ * @brief DMA Error Code\r
+ * @{\r
+ */\r
+#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */\r
+#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */\r
+#define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */\r
+#define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */\r
+#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */\r
+#define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */\r
+#define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */\r
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */\r
+#define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */\r
+#define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */\r
+#define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Request_selection DMA Request selection\r
+ * @brief DMA Request selection\r
+ * @{\r
+ */\r
+/* DMAMUX1 requests */\r
+#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */\r
+\r
+#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */\r
+#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */\r
+#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */\r
+#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */\r
+#define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */\r
+#define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */\r
+#define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */\r
+#define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */\r
+\r
+#define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */\r
+#define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */\r
+\r
+#define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */\r
+#define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */\r
+#define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */\r
+#define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */\r
+#define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */\r
+#define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */\r
+#define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */\r
+\r
+#define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */\r
+#define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */\r
+#define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */\r
+#define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */\r
+#define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */\r
+\r
+#define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */\r
+#define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */\r
+#define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */\r
+#define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */\r
+#define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */\r
+#define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */\r
+\r
+#define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */\r
+#define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */\r
+#define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */\r
+#define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */\r
+\r
+#define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */\r
+#define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */\r
+#define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */\r
+#define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */\r
+\r
+#define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */\r
+#define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */\r
+#define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */\r
+#define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */\r
+\r
+#define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */\r
+#define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */\r
+#define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */\r
+#define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */\r
+#define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */\r
+#define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */\r
+\r
+#define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */\r
+#define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */\r
+#define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */\r
+#define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */\r
+#define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */\r
+#define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */\r
+#define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */\r
+\r
+#define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */\r
+#define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */\r
+#define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */\r
+#define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */\r
+#define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */\r
+#define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */\r
+\r
+#define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */\r
+#define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */\r
+\r
+#define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */\r
+#define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */\r
+#define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */\r
+#define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */\r
+\r
+#define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */\r
+#define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */\r
+\r
+#define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */\r
+#define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */\r
+\r
+#define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */\r
+#define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */\r
+\r
+#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */\r
+#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */\r
+\r
+#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */\r
+\r
+#define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */\r
+#define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */\r
+\r
+#define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */\r
+\r
+#define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */\r
+#define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */\r
+#define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */\r
+#define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */\r
+\r
+#define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */\r
+#define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */\r
+#define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */\r
+#define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */\r
+\r
+#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */\r
+#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */\r
+#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */\r
+#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */\r
+\r
+#define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */\r
+#define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */\r
+\r
+#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/\r
+#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/\r
+\r
+#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */\r
+#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */\r
+#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */\r
+#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */\r
+#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */\r
+#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */\r
+\r
+#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */\r
+#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */\r
+#define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */\r
+#define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */\r
+\r
+#define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */\r
+#define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */\r
+#define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */\r
+#define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */\r
+\r
+#define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */\r
+#define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */\r
+\r
+#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */\r
+#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */\r
+\r
+#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */\r
+#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */\r
+\r
+#define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */\r
+\r
+\r
+/* DMAMUX2 requests */\r
+#define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */\r
+#define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */\r
+#define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */\r
+#define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */\r
+#define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */\r
+#define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */\r
+#define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */\r
+#define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */\r
+#define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */\r
+#define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */\r
+#define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */\r
+#define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */\r
+#define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */\r
+#define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */\r
+#define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */\r
+#define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */\r
+#define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */\r
+#define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+ * @brief DMA data transfer direction\r
+ * @{\r
+ */\r
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+ * @brief DMA peripheral incremented mode\r
+ * @{\r
+ */\r
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */\r
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+ * @brief DMA memory incremented mode\r
+ * @{\r
+ */\r
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */\r
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+ * @brief DMA peripheral data size\r
+ * @{\r
+ */\r
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */\r
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */\r
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+ * @brief DMA memory data size\r
+ * @{\r
+ */\r
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */\r
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */\r
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+ * @brief DMA mode\r
+ * @{\r
+ */\r
+#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */\r
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */\r
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */\r
+#define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) /*!< Double buffer mode with first target memory M0 */\r
+#define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+ * @brief DMA priority levels\r
+ * @{\r
+ */\r
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */\r
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */\r
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */\r
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\r
+ * @brief DMA FIFO direct mode\r
+ * @{\r
+ */\r
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */\r
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\r
+ * @brief DMA FIFO level\r
+ * @{\r
+ */\r
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */\r
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */\r
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */\r
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Memory_burst DMA Memory burst\r
+ * @brief DMA memory burst\r
+ * @{\r
+ */\r
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)\r
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)\r
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)\r
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\r
+ * @brief DMA peripheral burst\r
+ * @{\r
+ */\r
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)\r
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)\r
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)\r
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+ * @brief DMA interrupts definition\r
+ * @{\r
+ */\r
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)\r
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)\r
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)\r
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)\r
+#define DMA_IT_FE ((uint32_t)0x00000080U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+ * @brief DMA flag definitions\r
+ * @{\r
+ */\r
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)\r
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)\r
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)\r
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)\r
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)\r
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)\r
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)\r
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)\r
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)\r
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)\r
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)\r
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)\r
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)\r
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)\r
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)\r
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)\r
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)\r
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)\r
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)\r
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BDMA_flag_definitions BDMA flag definitions\r
+ * @brief BDMA flag definitions\r
+ * @{\r
+ */\r
+#define BDMA_FLAG_GL0 ((uint32_t)0x00000001)\r
+#define BDMA_FLAG_TC0 ((uint32_t)0x00000002)\r
+#define BDMA_FLAG_HT0 ((uint32_t)0x00000004)\r
+#define BDMA_FLAG_TE0 ((uint32_t)0x00000008)\r
+#define BDMA_FLAG_GL1 ((uint32_t)0x00000010)\r
+#define BDMA_FLAG_TC1 ((uint32_t)0x00000020)\r
+#define BDMA_FLAG_HT1 ((uint32_t)0x00000040)\r
+#define BDMA_FLAG_TE1 ((uint32_t)0x00000080)\r
+#define BDMA_FLAG_GL2 ((uint32_t)0x00000100)\r
+#define BDMA_FLAG_TC2 ((uint32_t)0x00000200)\r
+#define BDMA_FLAG_HT2 ((uint32_t)0x00000400)\r
+#define BDMA_FLAG_TE2 ((uint32_t)0x00000800)\r
+#define BDMA_FLAG_GL3 ((uint32_t)0x00001000)\r
+#define BDMA_FLAG_TC3 ((uint32_t)0x00002000)\r
+#define BDMA_FLAG_HT3 ((uint32_t)0x00004000)\r
+#define BDMA_FLAG_TE3 ((uint32_t)0x00008000)\r
+#define BDMA_FLAG_GL4 ((uint32_t)0x00010000)\r
+#define BDMA_FLAG_TC4 ((uint32_t)0x00020000)\r
+#define BDMA_FLAG_HT4 ((uint32_t)0x00040000)\r
+#define BDMA_FLAG_TE4 ((uint32_t)0x00080000)\r
+#define BDMA_FLAG_GL5 ((uint32_t)0x00100000)\r
+#define BDMA_FLAG_TC5 ((uint32_t)0x00200000)\r
+#define BDMA_FLAG_HT5 ((uint32_t)0x00400000)\r
+#define BDMA_FLAG_TE5 ((uint32_t)0x00800000)\r
+#define BDMA_FLAG_GL6 ((uint32_t)0x01000000)\r
+#define BDMA_FLAG_TC6 ((uint32_t)0x02000000)\r
+#define BDMA_FLAG_HT6 ((uint32_t)0x04000000)\r
+#define BDMA_FLAG_TE6 ((uint32_t)0x08000000)\r
+#define BDMA_FLAG_GL7 ((uint32_t)0x10000000)\r
+#define BDMA_FLAG_TC7 ((uint32_t)0x20000000)\r
+#define BDMA_FLAG_HT7 ((uint32_t)0x40000000)\r
+#define BDMA_FLAG_TE7 ((uint32_t)0x80000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup DMA_Exported_Macros DMA Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset DMA handle state\r
+ * @param __HANDLE__: specifies the DMA handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO filled level.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The FIFO filling state.\r
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full\r
+ * and not empty.\r
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r
+ * - DMA_FIFOStatus_Empty: when FIFO is empty\r
+ * - DMA_FIFOStatus_Full: when FIFO is full\r
+ */\r
+#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE(__HANDLE__) \\r
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \\r
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE(__HANDLE__) \\r
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \\r
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))\r
+\r
+/* Interrupt & Flag management */\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\\r
+ (uint32_t)0x00000000)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream half transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\\r
+ (uint32_t)0x00000000)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\\r
+ (uint32_t)0x00000000)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified FIFO error flag index.\r
+ */\r
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\\r
+ (uint32_t)0x00000000)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream direct mode error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified direct mode error flag index.\r
+ */\r
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\\r
+ (uint32_t)0x00000000)\r
+\r
+/**\r
+ * @brief Returns the current BDMA Channel Global interrupt flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\\r
+ (uint32_t)0x00000000)\r
+\r
+/**\r
+ * @brief Get the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.\r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\r
+\r
+#define DMA_TO_BDMA_IT(__DMA_IT__) \\r
+((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\\r
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\\r
+ (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\\r
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\\r
+ ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\\r
+ ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\\r
+ ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\\r
+ (uint32_t)0x00000000)\r
+\r
+\r
+#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \\r
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))\r
+\r
+#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\\r
+ (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\\r
+ (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))\r
+\r
+\r
+#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))\r
+\r
+#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\\r
+ (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\\r
+ (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))\r
+\r
+\r
+#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))\r
+\r
+#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+ (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \\r
+ (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Check whether the specified DMA Stream interrupt is enabled or not.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval The state of DMA_IT.\r
+ */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \\r
+ (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\\r
+ (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))\r
+\r
+/**\r
+ * @brief Writes the number of data units to be transferred on the DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)\r
+ * Number of data items depends only on the Peripheral data format.\r
+ *\r
+ * @note If Peripheral data format is Bytes: number of data units is equal\r
+ * to total number of bytes to be transferred.\r
+ *\r
+ * @note If Peripheral data format is Half-Word: number of data units is\r
+ * equal to total number of bytes to be transferred / 2.\r
+ *\r
+ * @note If Peripheral data format is Word: number of data units is equal\r
+ * to total number of bytes to be transferred / 4.\r
+ *\r
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.\r
+ */\r
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \\r
+ (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\\r
+ (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.\r
+ * @param __HANDLE__: DMA handle\r
+ *\r
+ * @retval The number of remaining data units in the current DMA Stream transfer.\r
+ */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \\r
+ (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\\r
+ (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include DMA HAL Extension module */\r
+#include "stm32h7xx_hal_dma_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
+ * @brief DMA Exported functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\r
+ * @brief I/O operation functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ * @{\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private Constants -------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Constants DMA Private Constants\r
+ * @brief DMA private defines and constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+ * @brief DMA private macros\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))\r
+\r
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))\r
+\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+ ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
+ ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
+ ((MODE) == DMA_CIRCULAR) || \\r
+ ((MODE) == DMA_PFCTRL) || \\r
+ ((MODE) == DMA_DOUBLE_BUFFER_M0) || \\r
+ ((MODE) == DMA_DOUBLE_BUFFER_M1))\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))\r
+\r
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\r
+ ((STATE) == DMA_FIFOMODE_ENABLE))\r
+\r
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\r
+\r
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\r
+ ((BURST) == DMA_MBURST_INC4) || \\r
+ ((BURST) == DMA_MBURST_INC8) || \\r
+ ((BURST) == DMA_MBURST_INC16))\r
+\r
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\r
+ ((BURST) == DMA_PBURST_INC4) || \\r
+ ((BURST) == DMA_PBURST_INC8) || \\r
+ ((BURST) == DMA_PBURST_INC16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Functions DMA Private Functions\r
+ * @brief DMA private functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_dma_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of DMA HAL extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_DMA_EX_H\r
+#define STM32H7xx_HAL_DMA_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMAEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r
+ * @brief DMAEx Exported types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HAL DMA Memory definition\r
+ */\r
+typedef enum\r
+{\r
+ MEMORY0 = 0x00U, /*!< Memory 0 */\r
+ MEMORY1 = 0x01U, /*!< Memory 1 */\r
+\r
+}HAL_DMA_MemoryTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMAMUX Synchronization configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.\r
+ This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */\r
+\r
+ uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.\r
+ This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */\r
+\r
+ FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled\r
+ This parameter can take the value ENABLE or DISABLE*/\r
+\r
+\r
+ FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.\r
+ This parameter can take the value ENABLE or DISABLE */\r
+\r
+ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.\r
+ This parameters can be in the range 1 to 32 */\r
+\r
+}HAL_DMA_MuxSyncConfigTypeDef;\r
+\r
+\r
+/**\r
+ * @brief HAL DMAMUX request generator parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator\r
+ This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */\r
+\r
+ uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.\r
+ This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */\r
+\r
+ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event.\r
+ This parameters can be in the range 1 to 32 */\r
+\r
+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMAEx_Exported_Constants DMA Exported Constants\r
+ * @brief DMAEx Exported constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection\r
+ * @brief DMAEx MUX SyncSignalID selection\r
+ * @{\r
+ */\r
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */\r
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */\r
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */\r
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */\r
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */\r
+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */\r
+#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */\r
+#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */\r
+\r
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */\r
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */\r
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */\r
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */\r
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */\r
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */\r
+#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */\r
+#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */\r
+#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */\r
+#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */\r
+#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */\r
+#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */\r
+#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */\r
+#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */\r
+#define HAL_DMAMUX2_SYNC_EXTI0 14U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */\r
+#define HAL_DMAMUX2_SYNC_EXTI2 15U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection\r
+ * @brief DMAEx MUX SyncPolarity selection\r
+ * @{\r
+ */\r
+#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */\r
+#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */\r
+#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */\r
+#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection\r
+ * @brief DMAEx MUX SignalGeneratorID selection\r
+ * @{\r
+ */\r
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */\r
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */\r
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */\r
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */\r
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */\r
+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */\r
+#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */\r
+#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */\r
+\r
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */\r
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */\r
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */\r
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */\r
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */\r
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */\r
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */\r
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */\r
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */\r
+#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */\r
+#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */\r
+#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */\r
+#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */\r
+#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */\r
+#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */\r
+#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */\r
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */\r
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */\r
+#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */\r
+#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */\r
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */\r
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection\r
+ * @brief DMAEx MUX RequestGeneneratorPolarity selection\r
+ * @{\r
+ */\r
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */\r
+#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */\r
+#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */\r
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r
+ * @brief DMAEx Exported functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);\r
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);\r
+\r
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Macros DMA Private Macros\r
+ * @brief DMAEx private macros\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)\r
+#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)\r
+\r
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))\r
+\r
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \\r
+ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \\r
+ ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \\r
+ ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))\r
+\r
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))\r
+\r
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \\r
+ ((EVENT) == ENABLE))\r
+\r
+#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)\r
+#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)\r
+\r
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))\r
+\r
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \\r
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \\r
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \\r
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions\r
+ * @brief DMAEx Private functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_flash.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of FLASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_FLASH_H\r
+#define STM32H7xx_HAL_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief FLASH Procedure structure definition\r
+ */\r
+typedef enum\r
+{\r
+ FLASH_PROC_NONE = 0U,\r
+ FLASH_PROC_SECTERASE_BANK1,\r
+ FLASH_PROC_MASSERASE_BANK1,\r
+ FLASH_PROC_PROGRAM_BANK1,\r
+ FLASH_PROC_SECTERASE_BANK2,\r
+ FLASH_PROC_MASSERASE_BANK2,\r
+ FLASH_PROC_PROGRAM_BANK2,\r
+ FLASH_PROC_ALLBANK_MASSERASE\r
+} FLASH_ProcedureTypeDef;\r
+\r
+\r
+/**\r
+ * @brief FLASH handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */\r
+\r
+ __IO uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in IT context */\r
+\r
+ __IO uint32_t VoltageForErase; /*!< Internal variable to provide voltage range selected by user in IT context */\r
+\r
+ __IO uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */\r
+\r
+ __IO uint32_t Address; /*!< Internal variable to save address selected for program */\r
+\r
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */\r
+\r
+ __IO uint32_t ErrorCode; /*!< FLASH error code */\r
+\r
+}FLASH_ProcessTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_Error_Code FLASH Error Code\r
+ * @brief FLASH Error Code\r
+ * @{\r
+ */\r
+#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */\r
+\r
+#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */\r
+#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */\r
+#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */\r
+#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */\r
+#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */\r
+#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */\r
+#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */\r
+#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */\r
+#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */\r
+#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */\r
+\r
+#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1 */\r
+#define HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1 */\r
+\r
+#define HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2 /*!< Write Protection Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2 /*!< ECC Double Detection Error on Bank 2 */\r
+#define HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2 /*!< CRC Read Error on Bank2 */\r
+\r
+#define HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR /*!< Option Byte Change Error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Type_Program FLASH Type Program\r
+ * @{\r
+ */\r
+#define FLASH_TYPEPROGRAM_FLASHWORD 0x03U /*!< Program a flash word (256-bit) at a specified address */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Flag_definition FLASH Flag definition\r
+ * @brief Flag definition\r
+ * @{\r
+ */\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_WDW FLASH_SR_WDW /*!< Waiting for Data to Write on flag */\r
+#define FLASH_FLAG_QW FLASH_SR_QW /*!< Write Waiting in Operation Queue on flag */\r
+#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC module is working on flag */\r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */\r
+#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */\r
+#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< strobe Error on flag */\r
+#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */\r
+#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */\r
+#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */\r
+#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */\r
+#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */\r
+#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */\r
+#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC module completes on bank flag */\r
+#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */\r
+\r
+#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */\r
+#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Waiting for Data to Write on Bank 1 flag */\r
+#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Write Waiting in Operation Queue on Bank 1 flag */\r
+#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC module is working on Bank 1 flag */\r
+#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */\r
+#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */\r
+#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */\r
+#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< strobe Error on Bank 1 flag */\r
+#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */\r
+#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */\r
+#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */\r
+#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */\r
+#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */\r
+#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */\r
+#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC module completes on bank Bank 1 flag */\r
+#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */\r
+\r
+#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \\r
+ FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \\r
+ FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \\r
+ FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \\r
+ FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1)\r
+\r
+#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \\r
+ FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \\r
+ FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \\r
+ FLASH_FLAG_ALL_ERRORS_BANK1)\r
+\r
+#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */\r
+#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Waiting for Data to Write on Bank 2 flag */\r
+#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Write Waiting in Operation Queue on Bank 2 flag */\r
+#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC module is working on Bank 2 flag */\r
+#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */\r
+#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */\r
+#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */\r
+#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */\r
+#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */\r
+#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */\r
+#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */\r
+#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */\r
+#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */\r
+#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */\r
+#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC module completes on bank Bank 2 flag */\r
+#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */\r
+\r
+#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \\r
+ FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \\r
+ FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \\r
+ FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \\r
+ FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2)\r
+\r
+#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \\r
+ FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \\r
+ FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \\r
+ FLASH_FLAG_ALL_ERRORS_BANK2)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition\r
+ * @brief FLASH Interrupt definition\r
+ * @{\r
+ */\r
+#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Bank 1 Operation Interrupt source */\r
+#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE /*!< Write Protection Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */\r
+#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE /*!< Double Detection ECC Error on Bank 1 Interrupt source */\r
+#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */\r
+#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */\r
+\r
+#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \\r
+ FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \\r
+ FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \\r
+ FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \\r
+ FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \\r
+ FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1)\r
+\r
+#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */\r
+#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */\r
+#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 Interrupt source */\r
+#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */\r
+#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */\r
+\r
+#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \\r
+ FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \\r
+ FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \\r
+ FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \\r
+ FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \\r
+ FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism\r
+ * @{\r
+ */\r
+#define FLASH_PSIZE_BYTE 0x00000000U /*!< Flash program/erase by 8 bits */\r
+#define FLASH_PSIZE_HALF_WORD FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */\r
+#define FLASH_PSIZE_WORD FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */\r
+#define FLASH_PSIZE_DOUBLE_WORD FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup FLASH_Keys FLASH Keys\r
+ * @{\r
+ */\r
+#define FLASH_KEY1 0x45670123U\r
+#define FLASH_KEY2 0xCDEF89ABU\r
+#define FLASH_OPT_KEY1 0x08192A3BU\r
+#define FLASH_OPT_KEY2 0x4C5D6E7FU\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Sectors FLASH Sectors\r
+ * @{\r
+ */\r
+#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */\r
+#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */\r
+#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */\r
+#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */\r
+#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */\r
+#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */\r
+#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */\r
+#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Set the FLASH Latency.\r
+ * @param __LATENCY__: FLASH Latency\r
+ * The value of this parameter depend on device used within the same series\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \\r
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))\r
+\r
+/**\r
+ * @brief Get the FLASH Latency.\r
+ * @retval FLASH Latency\r
+ * The value of this parameter depend on device used within the same series\r
+ */\r
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\r
+\r
+/**\r
+ * @brief Enable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ : FLASH interrupt\r
+ * In case of Bank 1 This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source\r
+ * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source\r
+\r
+ * In case of Bank 2, this parameter can be any combination of the following values: *\r
+ * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source\r
+ * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source\r
+ * @retval none\r
+ */\r
+\r
+#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))\r
+\r
+#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))\r
+\r
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \\r
+ __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \\r
+ __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))\r
+\r
+\r
+/**\r
+ * @brief Disable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ : FLASH interrupt\r
+ * In case of Bank 1 This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source\r
+ * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source\r
+ * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source\r
+\r
+ * In case of Bank 2, this parameter can be any combination of the following values: *\r
+ * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source\r
+ * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source\r
+ * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source\r
+ * @retval none\r
+ */\r
+\r
+#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))\r
+\r
+#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))\r
+\r
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \\r
+ __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \\r
+ __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))\r
+\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @param __FLAG__: specifies the FLASH flag to check.\r
+ * In case of Bank 1 This parameter can be any combination of the following values :\r
+ * @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag\r
+ * @arg FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag\r
+ * @arg FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag\r
+ * @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag\r
+ * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag\r
+ * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag\r
+ * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag\r
+ * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag\r
+ *\r
+ * In case of Bank 2 This parameter can be any combination of the following values :\r
+ * @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag\r
+ * @arg FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag\r
+ * @arg FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag\r
+ * @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag\r
+ * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag\r
+ * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag\r
+ * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag\r
+ * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag\r
+ * @retval The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))\r
+\r
+#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))\r
+\r
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \\r
+ __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))\r
+\r
+\r
+/**\r
+ * @brief Clear the specified FLASH flag.\r
+ * @param __FLAG__: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag\r
+ * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag\r
+ * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag\r
+ * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag\r
+ * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag\r
+ *\r
+ * In case of Bank 2 This parameter can be any combination of the following values :\r
+ * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag\r
+ * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag\r
+ * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag\r
+ * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag\r
+ * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag\r
+ * @retval none\r
+ */\r
+\r
+#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))\r
+\r
+#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))\r
+\r
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \\r
+ __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include FLASH HAL Extension module */\r
+#include "stm32h7xx_hal_flash_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+/** @addtogroup FLASH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Program operation functions ***********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);\r
+/* FLASH IRQ handler method */\r
+void HAL_FLASH_IRQHandler(void);\r
+/* Callbacks in non blocking modes */\r
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r
+/* Option bytes control */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+uint32_t HAL_FLASH_GetError(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
+ * @{\r
+ */\r
+extern FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions\r
+ * @{\r
+ */\r
+#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))\r
+\r
+#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))\r
+\r
+#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))\r
+\r
+/** @defgroup FLASH_Address FLASH Address\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))\r
+#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))\r
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))\r
+\r
+#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))\r
+\r
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \\r
+ ((BANK) == FLASH_BANK_2) || \\r
+ ((BANK) == FLASH_BANK_BOTH))\r
+\r
+#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \\r
+ ((BANK) == FLASH_BANK_2))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Functions FLASH Private functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);\r
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);\r
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_FLASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32H7xx_hal_flash_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of FLASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_FLASH_EX_H\r
+#define STM32H7xx_HAL_FLASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief FLASH Erase structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.\r
+ This parameter can be a value of @ref FLASHEx_Type_Erase */\r
+\r
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.\r
+ This parameter must be a value of @ref FLASHEx_Banks */\r
+\r
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled\r
+ This parameter must be a value of @ref FLASH_Sectors */\r
+\r
+ uint32_t NbSectors; /*!< Number of sectors to be erased.\r
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\r
+\r
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism\r
+ This parameter must be a value of @ref FLASHEx_Voltage_Range */\r
+\r
+} FLASH_EraseInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief FLASH Option Bytes Program structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OptionType; /*!< Option byte to be configured.\r
+ This parameter can be a value of @ref FLASHEx_Option_Type */\r
+\r
+ uint32_t WRPState; /*!< Write protection activation or deactivation.\r
+ This parameter can be a value of @ref FLASHEx_WRP_State */\r
+\r
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.\r
+ The value of this parameter depend on device used within the same series */\r
+\r
+ uint32_t RDPLevel; /*!< Set the read protection level.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\r
+\r
+ uint32_t BORLevel; /*!< Set the BOR Level.\r
+ This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */\r
+\r
+ uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).\r
+ This parameter can be a combination of @ref FLASHEx_OB_USER_Type */\r
+\r
+ uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /\r
+ IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */\r
+\r
+ uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config .\r
+ This parameter must be a value of @ref FLASHEx_Banks */\r
+\r
+ uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not\r
+ when RDP level decreased from Level 1 to Level 0 or during a mass erase.\r
+ This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */\r
+\r
+ uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).\r
+ This parameter must be a value between begin and end of a bank */\r
+\r
+ uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).\r
+ This parameter must be a value between PCROP Start address and end of a bank */\r
+\r
+ uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1\r
+ or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */\r
+\r
+ uint32_t BootAddr0; /*!< Boot Address 0.\r
+ This parameter must be a value between begin and end of a bank */\r
+\r
+ uint32_t BootAddr1; /*!< Boot Address 1.\r
+ This parameter must be a value between begin and end of a bank */\r
+#if defined(DUAL_CORE)\r
+ uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1\r
+ or both.\r
+ This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */\r
+\r
+ uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0.\r
+ This parameter must be a value between begin and end of a bank */\r
+\r
+ uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1.\r
+ This parameter must be a value between begin and end of a bank */\r
+#endif /*DUAL_CORE*/\r
+\r
+ uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not\r
+ when RDP level decreased from Level 1 to Level 0 or during a mass erase.\r
+ This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */\r
+\r
+ uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.\r
+ This parameter must be a value between begin address and end address of bank1 */\r
+\r
+ uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address .\r
+ This parameter must be a value between Secure Area Start address and end address of a bank1 */\r
+\r
+} FLASH_OBProgramInitTypeDef;\r
+\r
+/**\r
+ * @brief FLASH Erase structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TypeCRC; /*!< CRC Selection Type.\r
+ This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */\r
+\r
+ uint32_t BurstSize; /*!< CRC Burst Size.\r
+ This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */\r
+\r
+ uint32_t Bank; /*!< Select bank where CRC computation is enabled.\r
+ This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */\r
+\r
+ uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation\r
+ This parameter must be a value of @ref FLASH_Sectors */\r
+\r
+ uint32_t NbSectors; /*!< Number of sectors to be computed.\r
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\r
+\r
+ uint32_t CRCStartAddr; /*!< CRC Start address.\r
+ This parameter must be a value between begin address and end address of a bank */\r
+\r
+ uint32_t CRCEndAddr; /*!< CRC End address.\r
+ This parameter must be a value between CRC Start address and end address of a bank */\r
+\r
+} FLASH_CRCInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase\r
+ * @{\r
+ */\r
+#define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */\r
+#define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range\r
+ * @{\r
+ */\r
+#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */\r
+#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */\r
+#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */\r
+#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_WRP_State FLASH WRP State\r
+ * @{\r
+ */\r
+#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */\r
+#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Type FLASH Option Type\r
+ * @{\r
+ */\r
+#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */\r
+#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */\r
+#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */\r
+#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */\r
+#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */\r
+#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */\r
+#if defined(DUAL_CORE)\r
+#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */\r
+#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */\r
+#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */\r
+#else /* Single core*/\r
+#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */\r
+#endif /*DUAL_CORE*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection\r
+ * @{\r
+ */\r
+#define OB_RDP_LEVEL_0 0xAA00U\r
+#define OB_RDP_LEVEL_1 0x5500U\r
+#define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2\r
+ it s no more possible to go back to level 1 or 0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog\r
+ * @{\r
+ */\r
+#define OB_WWDG_SW 0x10U /*!< Software WWDG selected */\r
+#define OB_WWDG_HW 0x00U /*!< Hardware WWDG selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog\r
+ * @{\r
+ */\r
+#define OB_IWDG_SW 0x20U /*!< Software IWDG selected */\r
+#define OB_IWDG_HW 0x00U /*!< Hardware IWDG selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP\r
+ * @{\r
+ */\r
+#define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY\r
+ * @{\r
+ */\r
+#define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP\r
+ * @{\r
+ */\r
+#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */\r
+#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY\r
+ * @{\r
+ */\r
+#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */\r
+#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level\r
+ * @{\r
+ */\r
+#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */\r
+#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */\r
+#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */\r
+#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address\r
+ * @{\r
+ */\r
+#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */\r
+#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */\r
+#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */\r
+#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */\r
+#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */\r
+#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */\r
+#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Latency FLASH Latency\r
+ * @{\r
+ */\r
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */\r
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */\r
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */\r
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */\r
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */\r
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */\r
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */\r
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */\r
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */\r
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */\r
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */\r
+#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */\r
+#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */\r
+#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */\r
+#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */\r
+#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Banks FLASH Banks\r
+ * @{\r
+ */\r
+#define FLASH_BANK_1 0x01U /*!< Bank 1 */\r
+#define FLASH_BANK_2 0x02U /*!< Bank 2 */\r
+#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP\r
+ * @{\r
+ */\r
+#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level\r
+ is decreased from Level 1 to Level 0 or during a mass erase */\r
+#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is\r
+ decreased from Level 1 to Level 0 (full mass erase) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @{\r
+ */\r
+#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */\r
+#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */\r
+#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */\r
+#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */\r
+#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */\r
+#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */\r
+#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */\r
+#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */\r
+#define OB_WRP_SECTOR_All 0x000000FFU /*!< Write protection of all Sectors */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY\r
+ * @{\r
+ */\r
+#define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */\r
+#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE\r
+ * @{\r
+ */\r
+#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */\r
+#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */\r
+#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */\r
+#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(DUAL_CORE)\r
+/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7\r
+ * @{\r
+ */\r
+#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */\r
+#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4\r
+ * @{\r
+ */\r
+#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */\r
+#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */\r
+/**\r
+ * @}\r
+ */\r
+#endif /*DUAL_CORE*/\r
+\r
+/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW\r
+ * @{\r
+ */\r
+#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */\r
+#define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(DUAL_CORE)\r
+/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW\r
+ * @{\r
+ */\r
+#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/\r
+#define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1\r
+ * @{\r
+ */\r
+#define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */\r
+#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1\r
+ * @{\r
+ */\r
+#define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */\r
+#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(DUAL_CORE)\r
+/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2\r
+ * @{\r
+ */\r
+#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */\r
+#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2\r
+ * @{\r
+ */\r
+#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */\r
+#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK\r
+ * @{\r
+ */\r
+#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */\r
+#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV\r
+ * @{\r
+ */\r
+#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */\r
+#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION\r
+ * @{\r
+ */\r
+#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */\r
+#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */\r
+#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type\r
+ * @{\r
+ */\r
+#define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */\r
+#define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/\r
+#define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/\r
+#define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */\r
+#define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */\r
+#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */\r
+#define OB_USER_SECURITY 0x0040U /*!< security selection */\r
+#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */\r
+#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */\r
+#if defined(DUAL_CORE)\r
+#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */\r
+#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */\r
+#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */\r
+#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection*/\r
+#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection*/\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP\r
+ * @{\r
+ */\r
+#define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level\r
+ is decreased from Level 1 to Level 0 or during a mass erase */\r
+#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is\r
+ decreased from Level 1 to Level 0 (full mass erase) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type\r
+ * @{\r
+ */\r
+#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */\r
+#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */\r
+#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size\r
+ * @{\r
+ */\r
+#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */\r
+#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */\r
+#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */\r
+#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay\r
+ * @{\r
+ */\r
+#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */\r
+#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */\r
+#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */\r
+#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)\r
+ * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].\r
+ * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)\r
+ * @retval The FLASH Boot Base Adress\r
+ */\r
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Set the FLASH Program/Erase parallelism.\r
+ * @param __PSIZE__ FLASH Program/Erase parallelism\r
+ * This parameter can be a value of @ref FLASH_Program_Parallelism\r
+ * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \\r
+ MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \\r
+ MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))\r
+\r
+/**\r
+ * @brief Get the FLASH Program/Erase parallelism.\r
+ * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)\r
+ * @retval FLASH Program/Erase parallelism\r
+ * This return value can be a value of @ref FLASH_Program_Parallelism\r
+ */\r
+#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \\r
+ READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \\r
+ READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))\r
+\r
+/**\r
+ * @brief Set the FLASH Programming Delay.\r
+ * @param __DELAY__ FLASH Programming Delay\r
+ * This parameter can be a value of @ref FLASHEx_Programming_Delay\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))\r
+\r
+/**\r
+ * @brief Get the FLASH Programming Delay.\r
+ * @retval FLASH Programming Delay\r
+ * This return value can be a value of @ref FLASHEx_Programming_Delay\r
+ */\r
+#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Extension Program operation functions *************************************/\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);\r
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);\r
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);\r
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);\r
+\r
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \\r
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))\r
+\r
+#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_4))\r
+\r
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \\r
+ ((VALUE) == OB_WRPSTATE_ENABLE))\r
+#if defined(DUAL_CORE)\r
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))\r
+#else\r
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))\r
+#endif /*DUAL_CORE*/\r
+\r
+#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)\r
+\r
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\\r
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\\r
+ ((LEVEL) == OB_RDP_LEVEL_2))\r
+\r
+#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))\r
+\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))\r
+\r
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))\r
+\r
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \\r
+ ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \\r
+ ((LATENCY) == FLASH_LATENCY_1) || \\r
+ ((LATENCY) == FLASH_LATENCY_2) || \\r
+ ((LATENCY) == FLASH_LATENCY_3) || \\r
+ ((LATENCY) == FLASH_LATENCY_4) || \\r
+ ((LATENCY) == FLASH_LATENCY_5) || \\r
+ ((LATENCY) == FLASH_LATENCY_6) || \\r
+ ((LATENCY) == FLASH_LATENCY_7) || \\r
+ ((LATENCY) == FLASH_LATENCY_8) || \\r
+ ((LATENCY) == FLASH_LATENCY_9) || \\r
+ ((LATENCY) == FLASH_LATENCY_10) || \\r
+ ((LATENCY) == FLASH_LATENCY_11) || \\r
+ ((LATENCY) == FLASH_LATENCY_12) || \\r
+ ((LATENCY) == FLASH_LATENCY_13) || \\r
+ ((LATENCY) == FLASH_LATENCY_14) || \\r
+ ((LATENCY) == FLASH_LATENCY_15))\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \\r
+ (((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \\r
+ (((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END)))\r
+\r
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))\r
+\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\\r
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\\r
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\\r
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r
+\r
+#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \\r
+ ((CONFIG) == OB_PCROP_RDP_ERASE))\r
+\r
+#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \\r
+ ((CONFIG) == OB_SECURE_RDP_ERASE))\r
+\r
+#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))\r
+\r
+#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))\r
+\r
+#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))\r
+#if defined(DUAL_CORE)\r
+#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))\r
+#endif /*DUAL_CORE*/\r
+#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))\r
+\r
+#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))\r
+\r
+#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))\r
+\r
+#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))\r
+\r
+#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \\r
+ ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))\r
+\r
+#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))\r
+\r
+#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))\r
+\r
+#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))\r
+\r
+#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))\r
+#endif /*DUAL_CORE*/\r
+#if defined(DUAL_CORE)\r
+#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))\r
+#else\r
+#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))\r
+#endif\r
+\r
+#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \\r
+ ((VALUE) == OB_BOOT_ADD1) || \\r
+ ((VALUE) == OB_BOOT_ADD_BOTH))\r
+\r
+#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \\r
+ ((VALUE) == FLASH_CRC_SECTORS) || \\r
+ ((VALUE) == FLASH_CRC_BANK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions\r
+ * @{\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_FLASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_gpio.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of GPIO HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_GPIO_H\r
+#define STM32H7xx_HAL_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIO_mode_define */\r
+\r
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
+ This parameter can be a value of @ref GPIO_pull_define */\r
+\r
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIO_speed_define */\r
+\r
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.\r
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */\r
+} GPIO_InitTypeDef;\r
+\r
+/**\r
+ * @brief GPIO Bit SET and Bit RESET enumeration\r
+ */\r
+typedef enum\r
+{\r
+ GPIO_PIN_RESET = 0U,\r
+ GPIO_PIN_SET\r
+} GPIO_PinState;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_pins_define GPIO pins define\r
+ * @{\r
+ */\r
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */\r
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */\r
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */\r
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */\r
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */\r
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */\r
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */\r
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */\r
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */\r
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */\r
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */\r
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */\r
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */\r
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */\r
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */\r
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */\r
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */\r
+\r
+#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_mode_define GPIO mode define\r
+ * @brief GPIO Configuration Mode\r
+ * Elements values convention: 0xX0yz00YZ\r
+ * - X : GPIO mode or EXTI Mode\r
+ * - y : External IT or Event trigger detection\r
+ * - z : IO configuration on External IT or Event\r
+ * - Y : Output type (Push Pull or Open Drain)\r
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)\r
+ * @{\r
+ */\r
+#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */\r
+#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */\r
+#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */\r
+#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */\r
+#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */\r
+\r
+#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */\r
+\r
+#define GPIO_MODE_IT_RISING (0x11110000U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_IT_FALLING (0x11210000U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_IT_RISING_FALLING (0x11310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+\r
+#define GPIO_MODE_EVT_RISING (0x11120000U) /*!< External Event Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_EVT_FALLING (0x11220000U) /*!< External Event Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_EVT_RISING_FALLING (0x11320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_speed_define GPIO speed define\r
+ * @brief GPIO Output Maximum frequency\r
+ * @{\r
+ */\r
+#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */\r
+#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */\r
+#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< Fast speed */\r
+#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< High speed */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_pull_define GPIO pull define\r
+ * @brief GPIO Pull-Up or Pull-Down Activation\r
+ * @{\r
+ */\r
+#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */\r
+#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */\r
+#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))\r
+\r
+#endif\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param __EXTI_LINE__: specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include GPIO HAL Extension module */\r
+#include "stm32h7xx_hal_gpio_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
+#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\\r
+ (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\\r
+ ((MODE) == GPIO_MODE_AF_PP) ||\\r
+ ((MODE) == GPIO_MODE_AF_OD) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_ANALOG))\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \\r
+ ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))\r
+\r
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\r
+ ((PULL) == GPIO_PULLDOWN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Functions GPIO Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_GPIO_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_gpio_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of GPIO HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_GPIO_EX_H\r
+#define STM32H7xx_HAL_GPIO_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIOEx GPIOEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\r
+ * @{\r
+ */\r
+/**\r
+ * @brief AF 0 selection\r
+ */\r
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */\r
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */\r
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */\r
+#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */\r
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */\r
+#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */\r
+#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */\r
+#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */\r
+#define GPIO_AF0_D2PWREN ((uint8_t)0x00) /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */\r
+#if defined(DUAL_CORE)\r
+#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */\r
+#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */\r
+#endif /* DUAL_CORE */\r
+\r
+/**\r
+ * @brief AF 1 selection\r
+ */\r
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */\r
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */\r
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */\r
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 2 selection\r
+ */\r
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */\r
+#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */\r
+#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */\r
+#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 3 selection\r
+ */\r
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */\r
+#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */\r
+#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */\r
+#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 4 selection\r
+ */\r
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */\r
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */\r
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */\r
+#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */\r
+#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */\r
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */\r
+#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */\r
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */\r
+#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 5 selection\r
+ */\r
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */\r
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */\r
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */\r
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */\r
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */\r
+#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */\r
+\r
+\r
+/**\r
+ * @brief AF 6 selection\r
+ */\r
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */\r
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */\r
+#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */\r
+#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */\r
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */\r
+#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 7 selection\r
+ */\r
+#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */\r
+#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */\r
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */\r
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */\r
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */\r
+#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */\r
+#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */\r
+#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */\r
+#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 8 selection\r
+ */\r
+#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */\r
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */\r
+#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */\r
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */\r
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */\r
+#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */\r
+#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */\r
+#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 9 selection\r
+ */\r
+#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */\r
+#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */\r
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */\r
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */\r
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */\r
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */\r
+#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */\r
+#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */\r
+#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 10 selection\r
+ */\r
+#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */\r
+#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */\r
+#define GPIO_AF10_SDMMC2 ((uint8_t)0xA) /* SDMMC2 Alternate Function mapping */\r
+#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */\r
+#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */\r
+#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */\r
+#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */\r
+#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */\r
+#define GPIO_AF10_CRS_SYNC ((uint8_t)0xA) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */\r
+\r
+\r
+/**\r
+ * @brief AF 11 selection\r
+ */\r
+#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */\r
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */\r
+#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */\r
+#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */\r
+#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */\r
+#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */\r
+#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */\r
+#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */\r
+#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */\r
+#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 12 selection\r
+ */\r
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */\r
+#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */\r
+#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */\r
+#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */\r
+#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */\r
+#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */\r
+#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 13 selection\r
+ */\r
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */\r
+#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */\r
+#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */\r
+#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */\r
+#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 14 selection\r
+ */\r
+#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */\r
+#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */\r
+\r
+/**\r
+ * @brief AF 15 selection\r
+ */\r
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO pin available on the platform\r
+ */\r
+/* Defines the available pins per GPIOs */\r
+#define GPIOA_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOB_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOC_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOD_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOE_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOF_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOG_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOI_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOH_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \\r
+ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\r
+ * @{\r
+ */\r
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\\r
+ ((__GPIOx__) == (GPIOB))? 1UL :\\r
+ ((__GPIOx__) == (GPIOC))? 2UL :\\r
+ ((__GPIOx__) == (GPIOD))? 3UL :\\r
+ ((__GPIOx__) == (GPIOE))? 4UL :\\r
+ ((__GPIOx__) == (GPIOF))? 5UL :\\r
+ ((__GPIOx__) == (GPIOG))? 6UL :\\r
+ ((__GPIOx__) == (GPIOH))? 7UL :\\r
+ ((__GPIOx__) == (GPIOI))? 8UL :\\r
+ ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_GPIO_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_hash.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of HASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_HASH_H\r
+#define STM32H7xx_HAL_HASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+#if defined (HASH)\r
+/** @addtogroup HASH\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup HASH_Exported_Types HASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HASH Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.\r
+ This parameter can be a value of @ref HASH_Data_Type. */\r
+\r
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation. */\r
+\r
+ uint8_t* pKey; /*!< The key is used only in HMAC operation. */\r
+\r
+} HASH_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */\r
+ HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */\r
+ HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */\r
+ HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */\r
+ HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */\r
+}HAL_HASH_StateTypeDef;\r
+\r
+/**\r
+ * @brief HAL phase structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */\r
+ HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */\r
+ HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase\r
+ (step 1 consists in entering the inner hash function key) */\r
+ HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase\r
+ (step 2 consists in entering the message text) */\r
+ HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase\r
+ (step 3 consists in entering the outer hash function key) */\r
+}HAL_HASH_PhaseTypeDef;\r
+\r
+/**\r
+ * @brief HAL HASH mode suspend definitions\r
+ */\r
+typedef enum\r
+{\r
+ HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */\r
+ HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */\r
+}HAL_HASH_SuspendTypeDef;\r
+\r
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)\r
+/**\r
+ * @brief HAL HASH common Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */\r
+ HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */\r
+ HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */\r
+ HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */\r
+ HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */\r
+}HAL_HASH_CallbackIDTypeDef;\r
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */\r
+\r
+\r
+/**\r
+ * @brief HASH Handle Structure definition\r
+ */\r
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)\r
+typedef struct __HASH_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */\r
+{\r
+ HASH_InitTypeDef Init; /*!< HASH required parameters */\r
+\r
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */\r
+\r
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */\r
+\r
+ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */\r
+\r
+ uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */\r
+\r
+ uint32_t HashBuffSize; /*!< Size of buffer to be processed */\r
+\r
+ __IO uint32_t HashInCount; /*!< Counter of inputted data */\r
+\r
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */\r
+\r
+ __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */\r
+\r
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */\r
+\r
+ HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */\r
+\r
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+\r
+ __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */\r
+\r
+ HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */\r
+\r
+ FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */\r
+\r
+ __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */\r
+\r
+ __IO uint32_t ErrorCode; /*!< HASH Error code */\r
+\r
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)\r
+ void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */\r
+\r
+ void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */\r
+\r
+ void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */\r
+\r
+ void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */\r
+\r
+ void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */\r
+\r
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */\r
+} HASH_HandleTypeDef;\r
+\r
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)\r
+/**\r
+ * @brief HAL HASH Callback pointer definition\r
+ */\r
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */\r
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HASH_Exported_Constants HASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HASH_Algo_Selection HASH algorithm selection\r
+ * @{\r
+ */\r
+#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */\r
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */\r
+#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */\r
+#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Algorithm_Mode HASH algorithm mode\r
+ * @{\r
+ */\r
+#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */\r
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Data_Type HASH input data type\r
+ * @{\r
+ */\r
+#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */\r
+#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */\r
+#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */\r
+#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type\r
+ * @{\r
+ */\r
+#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */\r
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_flags_definition HASH flags definitions\r
+ * @{\r
+ */\r
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */\r
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */\r
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */\r
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */\r
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_interrupts_definition HASH interrupts definitions\r
+ * @{\r
+ */\r
+#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */\r
+#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup HASH_alias HASH API alias\r
+ * @{\r
+ */\r
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Error_Definition HASH Error Definition\r
+ * @{\r
+ */\r
+#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */\r
+#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */\r
+#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */\r
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)\r
+#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */\r
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup HASH_Exported_Macros HASH Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Check whether or not the specified HASH flag is set.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.\r
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete.\r
+ * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.\r
+ * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.\r
+ * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \\r
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\\r
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )\r
+\r
+\r
+/** @brief Clear the specified HASH flag.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.\r
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))\r
+\r
+\r
+/** @brief Enable the specified HASH interrupt.\r
+ * @param __INTERRUPT__: specifies the HASH interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)\r
+ * @arg @ref HASH_IT_DCI Digest calculation complete\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified HASH interrupt.\r
+ * @param __INTERRUPT__: specifies the HASH interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)\r
+ * @arg @ref HASH_IT_DCI Digest calculation complete\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))\r
+\r
+/** @brief Reset HASH handle state.\r
+ * @param __HANDLE__: HASH handle.\r
+ * @retval None\r
+ */\r
+\r
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)\r
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\\r
+ (__HANDLE__)->State = HAL_HASH_STATE_RESET;\\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ }while(0)\r
+#else\r
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)\r
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */\r
+\r
+\r
+/** @brief Reset HASH handle status.\r
+ * @param __HANDLE__: HASH handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)\r
+\r
+/**\r
+ * @brief Enable the multi-buffer DMA transfer mode.\r
+ * @note This bit is set when hashing large files when multiple DMA transfers are needed.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)\r
+\r
+/**\r
+ * @brief Disable the multi-buffer DMA transfer mode.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)\r
+\r
+\r
+/**\r
+ * @brief Start the digest computation.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)\r
+\r
+/**\r
+ * @brief Set the number of valid bits in the last word written in data register DIN.\r
+ * @param __SIZE__: size in bytes of last data written in Data register.\r
+ * @retval None\r
+*/\r
+#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))\r
+\r
+/**\r
+ * @brief Reset the HASH core.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup HASH_Private_Macros HASH Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Return digest length in bytes.\r
+ * @retval Digest length\r
+ */\r
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \\r
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \\r
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )\r
+/**\r
+ * @brief Return number of words already pushed in the FIFO.\r
+ * @retval Number of words already pushed in the FIFO\r
+ */\r
+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)\r
+\r
+/**\r
+ * @brief Ensure that HASH input data type is valid.\r
+ * @param __DATATYPE__: HASH input data type.\r
+ * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)\r
+ */\r
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \\r
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \\r
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \\r
+ ((__DATATYPE__) == HASH_DATATYPE_1B))\r
+\r
+\r
+\r
+/**\r
+ * @brief Ensure that input data buffer size is valid for multi-buffer HASH\r
+ * processing in polling mode.\r
+ * @note This check is valid only for multi-buffer HASH processing in polling mode.\r
+ * @param __SIZE__: input data buffer size.\r
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)\r
+ */\r
+#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)\r
+/**\r
+ * @brief Ensure that input data buffer size is valid for multi-buffer HASH\r
+ * processing in DMA mode.\r
+ * @note This check is valid only for multi-buffer HASH processing in DMA mode.\r
+ * @param __SIZE__: input data buffer size.\r
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)\r
+ */\r
+#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))\r
+\r
+/**\r
+ * @brief Ensure that input data buffer size is valid for multi-buffer HMAC\r
+ * processing in DMA mode.\r
+ * @note This check is valid only for multi-buffer HMAC processing in DMA mode.\r
+ * @param __HANDLE__: HASH handle.\r
+ * @param __SIZE__: input data buffer size.\r
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)\r
+ */\r
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))\r
+/**\r
+ * @brief Ensure that handle phase is set to HASH processing.\r
+ * @param __HANDLE__: HASH handle.\r
+ * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)\r
+ */\r
+#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)\r
+\r
+/**\r
+ * @brief Ensure that handle phase is set to HMAC processing.\r
+ * @param __HANDLE__: HASH handle.\r
+ * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)\r
+ */\r
+#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \\r
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \\r
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include HASH HAL Extended module */\r
+#include "stm32h7xx_hal_hash_ex.h"\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization methods **********************************/\r
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);\r
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode\r
+ * @{\r
+ */\r
+\r
+\r
+/* HASH processing using polling *********************************************/\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode\r
+ * @{\r
+ */\r
+\r
+/* HASH processing using IT **************************************************/\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode\r
+ * @{\r
+ */\r
+\r
+/* HASH processing using DMA *************************************************/\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode\r
+ * @{\r
+ */\r
+\r
+/* HASH-MAC processing using polling *****************************************/\r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode\r
+ * @{\r
+ */\r
+\r
+/* HASH-HMAC processing using DMA ********************************************/\r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions\r
+ * @{\r
+ */\r
+\r
+\r
+/* Peripheral State methods **************************************************/\r
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);\r
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);\r
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);\r
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);\r
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);\r
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions -----------------------------------------------------------*/\r
+\r
+/** @addtogroup HASH_Private_Functions HASH Private Functions\r
+ * @{\r
+ */\r
+\r
+/* Private functions */\r
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);\r
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);\r
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);\r
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);\r
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);\r
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);\r
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HASH*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32H7xx_HAL_HASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_hash_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of HASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_HASH_EX_H\r
+#define STM32H7xx_HAL_HASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+#if defined (HASH)\r
+/** @addtogroup HASHEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+\r
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HASH*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32H7xx_HAL_HASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_hsem.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of HSEM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_HSEM_H\r
+#define STM32H7xx_HAL_HSEM_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HSEM\r
+ * @{\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup HSEM_Exported_Macros HSEM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SemID to mask helper Macro.\r
+ * @param __SEMID__: semaphore ID from 0 to 31\r
+ * @retval Semaphore Mask.\r
+ */\r
+#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))\r
+\r
+/**\r
+ * @brief Enables the specified HSEM interrupts.\r
+ * @param __SEM_MASK__: semaphores Mask\r
+ * @retval None.\r
+ */\r
+#if defined(DUAL_CORE)\r
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \\r
+ (HSEM->C1IER |= (__SEM_MASK__)) : \\r
+ (HSEM->C2IER |= (__SEM_MASK__)))\r
+#else\r
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))\r
+#endif /* DUAL_CORE */\r
+/**\r
+ * @brief Disables the specified HSEM interrupts.\r
+ * @param __SEM_MASK__: semaphores Mask\r
+ * @retval None.\r
+ */\r
+#if defined(DUAL_CORE)\r
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \\r
+ (HSEM->C1IER &= ~(__SEM_MASK__)) : \\r
+ (HSEM->C2IER &= ~(__SEM_MASK__)))\r
+#else\r
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))\r
+#endif /* DUAL_CORE */\r
+\r
+/**\r
+ * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.\r
+ * @param __SEM_MASK__: semaphores Mask\r
+ * @retval semaphores Mask : Semaphores where an interrupt occurred.\r
+ */\r
+#if defined(DUAL_CORE)\r
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \\r
+ ((__SEM_MASK__) & HSEM->C1MISR) : \\r
+ ((__SEM_MASK__) & HSEM->C2MISR1))\r
+#else\r
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)\r
+#endif /* DUAL_CORE */\r
+\r
+/**\r
+ * @brief Get the semaphores release status flags.\r
+ * @param __SEM_MASK__: semaphores Mask\r
+ * @retval semaphores Mask : Semaphores where Release flags rise.\r
+ */\r
+#if defined(DUAL_CORE)\r
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \\r
+ (__SEM_MASK__) & HSEM->C1ISR : \\r
+ (__SEM_MASK__) & HSEM->C2ISR)\r
+#else\r
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)\r
+#endif /* DUAL_CORE */\r
+\r
+/**\r
+ * @brief Clears the HSEM Interrupt flags.\r
+ * @param __SEM_MASK__: semaphores Mask\r
+ * @retval None.\r
+ */\r
+#if defined(DUAL_CORE)\r
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \\r
+ (HSEM->C1ICR |= (__SEM_MASK__)) : \\r
+ (HSEM->C2ICR |= (__SEM_MASK__)))\r
+#else\r
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))\r
+#endif /* DUAL_CORE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions\r
+ * @brief HSEM Take and Release functions\r
+ * @{\r
+ */\r
+\r
+/* HSEM semaphore take (lock) using 2-Step method ****************************/\r
+HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);\r
+/* HSEM semaphore fast take (lock) using 1-Step method ***********************/\r
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);\r
+/* HSEM Check semaphore state Taken or not **********************************/\r
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);\r
+/* HSEM Release **************************************************************/\r
+void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);\r
+/* HSEM Release All************************************************************/\r
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions\r
+ * @brief HSEM Set and Get Key functions.\r
+ * @{\r
+ */\r
+/* HSEM Set Clear Key *********************************************************/\r
+void HAL_HSEM_SetClearKey(uint32_t Key);\r
+/* HSEM Get Clear Key *********************************************************/\r
+uint32_t HAL_HSEM_GetClearKey(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HSEM_Exported_Functions_Group3\r
+ * @brief HSEM Notification functions\r
+ * @{\r
+ */\r
+/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/\r
+void HAL_HSEM_ActivateNotification(uint32_t SemMask);\r
+/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/\r
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask);\r
+/* HSEM Free Callback (When a semaphore is released) *******************************/\r
+void HAL_HSEM_FreeCallback(uint32_t SemMask);\r
+/* HSEM IRQ Handler **********************************************************/\r
+void HAL_HSEM_IRQHandler(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup HSEM_Private_Macros HSEM Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )\r
+\r
+#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )\r
+\r
+#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \\r
+ ((__COREID__) == HSEM_CPU2_COREID))\r
+#else\r
+#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)\r
+#endif\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_HSEM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_i2c.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of I2C HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_I2C_H\r
+#define STM32H7xx_HAL_I2C_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup I2C_Exported_Types I2C Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r
+ * @brief I2C Configuration Structure definition\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.\r
+ This parameter calculated by referring to I2C initialization\r
+ section in Reference manual */\r
+\r
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_ADDRESSING_MODE */\r
+\r
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */\r
+\r
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected\r
+ This parameter can be a 7-bit address. */\r
+\r
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected\r
+ This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */\r
+\r
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.\r
+ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */\r
+\r
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.\r
+ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */\r
+\r
+} I2C_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_state_structure_definition HAL state structure definition\r
+ * @brief HAL State structure definition\r
+ * @note HAL I2C State value coding follow below described bitmap :\n\r
+ * b7-b6 Error information\n\r
+ * 00 : No Error\n\r
+ * 01 : Abort (Abort user request on going)\n\r
+ * 10 : Timeout\n\r
+ * 11 : Error\n\r
+ * b5 Peripheral initialization status\n\r
+ * 0 : Reset (peripheral not initialized)\n\r
+ * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n\r
+ * b4 (not used)\n\r
+ * x : Should be set to 0\n\r
+ * b3\n\r
+ * 0 : Ready or Busy (No Listen mode ongoing)\n\r
+ * 1 : Listen (peripheral in Address Listen Mode)\n\r
+ * b2 Intrinsic process state\n\r
+ * 0 : Ready\n\r
+ * 1 : Busy (peripheral busy with some configuration or internal operations)\n\r
+ * b1 Rx state\n\r
+ * 0 : Ready (no Rx operation ongoing)\n\r
+ * 1 : Busy (Rx operation ongoing)\n\r
+ * b0 Tx state\n\r
+ * 0 : Ready (no Tx operation ongoing)\n\r
+ * 1 : Busy (Tx operation ongoing)\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */\r
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */\r
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */\r
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */\r
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */\r
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission\r
+ process is ongoing */\r
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception\r
+ process is ongoing */\r
+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */\r
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */\r
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */\r
+\r
+} HAL_I2C_StateTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition\r
+ * @brief HAL Mode structure definition\r
+ * @note HAL I2C Mode value coding follow below described bitmap :\n\r
+ * b7 (not used)\n\r
+ * x : Should be set to 0\n\r
+ * b6\n\r
+ * 0 : None\n\r
+ * 1 : Memory (HAL I2C communication is in Memory Mode)\n\r
+ * b5\n\r
+ * 0 : None\n\r
+ * 1 : Slave (HAL I2C communication is in Slave Mode)\n\r
+ * b4\n\r
+ * 0 : None\n\r
+ * 1 : Master (HAL I2C communication is in Master Mode)\n\r
+ * b3-b2-b1-b0 (not used)\n\r
+ * xxxx : Should be set to 0000\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */\r
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */\r
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */\r
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */\r
+\r
+} HAL_I2C_ModeTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r
+ * @brief I2C Error Code definition\r
+ * @{\r
+ */\r
+#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */\r
+#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */\r
+#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */\r
+#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */\r
+#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */\r
+#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */\r
+#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */\r
+#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */\r
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\r
+ * @brief I2C handle Structure definition\r
+ * @{\r
+ */\r
+typedef struct __I2C_HandleTypeDef\r
+{\r
+ I2C_TypeDef *Instance; /*!< I2C registers base address */\r
+\r
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */\r
+\r
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */\r
+\r
+ uint16_t XferSize; /*!< I2C transfer size */\r
+\r
+ __IO uint16_t XferCount; /*!< I2C transfer counter */\r
+\r
+ __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can\r
+ be a value of @ref I2C_XFEROPTIONS */\r
+\r
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state */\r
+\r
+ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< I2C locking object */\r
+\r
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */\r
+\r
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */\r
+\r
+ __IO uint32_t ErrorCode; /*!< I2C Error code */\r
+\r
+ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */\r
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */\r
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */\r
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */\r
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */\r
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */\r
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */\r
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */\r
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */\r
+\r
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */\r
+\r
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */\r
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */\r
+\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+} I2C_HandleTypeDef;\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL I2C Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */\r
+ HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */\r
+ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */\r
+ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */\r
+ HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */\r
+ HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */\r
+ HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */\r
+ HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */\r
+ HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */\r
+\r
+ HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */\r
+ HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */\r
+\r
+} HAL_I2C_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL I2C Callback pointer definition\r
+ */\r
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */\r
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */\r
+\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Constants I2C Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options\r
+ * @{\r
+ */\r
+#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)\r
+#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
+#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
+#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)\r
+#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)\r
+#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)\r
+\r
+/* List of XferOptions in usage of :\r
+ * 1- Restart condition in all use cases (direction change or not)\r
+ */\r
+#define I2C_OTHER_FRAME (0x000000AAU)\r
+#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)\r
+#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLE (0x00000000U)\r
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks\r
+ * @{\r
+ */\r
+#define I2C_OA2_NOMASK ((uint8_t)0x00U)\r
+#define I2C_OA2_MASK01 ((uint8_t)0x01U)\r
+#define I2C_OA2_MASK02 ((uint8_t)0x02U)\r
+#define I2C_OA2_MASK03 ((uint8_t)0x03U)\r
+#define I2C_OA2_MASK04 ((uint8_t)0x04U)\r
+#define I2C_OA2_MASK05 ((uint8_t)0x05U)\r
+#define I2C_OA2_MASK06 ((uint8_t)0x06U)\r
+#define I2C_OA2_MASK07 ((uint8_t)0x07U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_GENERALCALL_DISABLE (0x00000000U)\r
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode\r
+ * @{\r
+ */\r
+#define I2C_NOSTRETCH_DISABLE (0x00000000U)\r
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size\r
+ * @{\r
+ */\r
+#define I2C_MEMADD_SIZE_8BIT (0x00000001U)\r
+#define I2C_MEMADD_SIZE_16BIT (0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View\r
+ * @{\r
+ */\r
+#define I2C_DIRECTION_TRANSMIT (0x00000000U)\r
+#define I2C_DIRECTION_RECEIVE (0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode\r
+ * @{\r
+ */\r
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD\r
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND\r
+#define I2C_SOFTEND_MODE (0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode\r
+ * @{\r
+ */\r
+#define I2C_NO_STARTSTOP (0x00000000U)\r
+#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)\r
+#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)\r
+#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r
+ * @brief I2C Interrupt definition\r
+ * Elements values convention: 0xXXXXXXXX\r
+ * - XXXXXXXX : Interrupt control mask\r
+ * @{\r
+ */\r
+#define I2C_IT_ERRI I2C_CR1_ERRIE\r
+#define I2C_IT_TCI I2C_CR1_TCIE\r
+#define I2C_IT_STOPI I2C_CR1_STOPIE\r
+#define I2C_IT_NACKI I2C_CR1_NACKIE\r
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE\r
+#define I2C_IT_RXI I2C_CR1_RXIE\r
+#define I2C_IT_TXI I2C_CR1_TXIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Flag_definition I2C Flag definition\r
+ * @{\r
+ */\r
+#define I2C_FLAG_TXE I2C_ISR_TXE\r
+#define I2C_FLAG_TXIS I2C_ISR_TXIS\r
+#define I2C_FLAG_RXNE I2C_ISR_RXNE\r
+#define I2C_FLAG_ADDR I2C_ISR_ADDR\r
+#define I2C_FLAG_AF I2C_ISR_NACKF\r
+#define I2C_FLAG_STOPF I2C_ISR_STOPF\r
+#define I2C_FLAG_TC I2C_ISR_TC\r
+#define I2C_FLAG_TCR I2C_ISR_TCR\r
+#define I2C_FLAG_BERR I2C_ISR_BERR\r
+#define I2C_FLAG_ARLO I2C_ISR_ARLO\r
+#define I2C_FLAG_OVR I2C_ISR_OVR\r
+#define I2C_FLAG_PECERR I2C_ISR_PECERR\r
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT\r
+#define I2C_FLAG_ALERT I2C_ISR_ALERT\r
+#define I2C_FLAG_BUSY I2C_ISR_BUSY\r
+#define I2C_FLAG_DIR I2C_ISR_DIR\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Macros I2C Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset I2C handle state.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r
+#endif\r
+\r
+/** @brief Enable the specified I2C interrupt.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified I2C interrupt.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r
+\r
+/** @brief Check whether the specified I2C interrupt source is enabled or not.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the I2C interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Check whether the specified I2C flag is set or not.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty\r
+ * @arg @ref I2C_FLAG_TXIS Transmit interrupt status\r
+ * @arg @ref I2C_FLAG_RXNE Receive data register not empty\r
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)\r
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag\r
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag\r
+ * @arg @ref I2C_FLAG_TC Transfer complete (master mode)\r
+ * @arg @ref I2C_FLAG_TCR Transfer complete reload\r
+ * @arg @ref I2C_FLAG_BERR Bus error\r
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost\r
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun\r
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception\r
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
+ * @arg @ref I2C_FLAG_ALERT SMBus alert\r
+ * @arg @ref I2C_FLAG_BUSY Bus busy\r
+ * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)\r
+ *\r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define I2C_FLAG_MASK (0x0001FFFFU)\r
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)\r
+\r
+/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty\r
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)\r
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag\r
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag\r
+ * @arg @ref I2C_FLAG_BERR Bus error\r
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost\r
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun\r
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception\r
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
+ * @arg @ref I2C_FLAG_ALERT SMBus alert\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \\r
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))\r
+\r
+/** @brief Enable the specified I2C peripheral.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief Disable the specified I2C peripheral.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include I2C HAL Extended module */\r
+#include "stm32h7xx_hal_i2c_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup I2C_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions******************************/\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);\r
+\r
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ * @{\r
+ */\r
+/* IO operation functions ****************************************************/\r
+/******* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r
+\r
+/******* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\r
+\r
+/******* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */\r
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\r
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
+ * @{\r
+ */\r
+/* Peripheral State, Mode and Error functions *********************************/\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Constants I2C Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Macro I2C Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\r
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r
+\r
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\r
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r
+\r
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \\r
+ ((MASK) == I2C_OA2_MASK01) || \\r
+ ((MASK) == I2C_OA2_MASK02) || \\r
+ ((MASK) == I2C_OA2_MASK03) || \\r
+ ((MASK) == I2C_OA2_MASK04) || \\r
+ ((MASK) == I2C_OA2_MASK05) || \\r
+ ((MASK) == I2C_OA2_MASK06) || \\r
+ ((MASK) == I2C_OA2_MASK07))\r
+\r
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \\r
+ ((CALL) == I2C_GENERALCALL_ENABLE))\r
+\r
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\r
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r
+\r
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\r
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r
+\r
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \\r
+ ((MODE) == I2C_AUTOEND_MODE) || \\r
+ ((MODE) == I2C_SOFTEND_MODE))\r
+\r
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \\r
+ ((REQUEST) == I2C_GENERATE_START_READ) || \\r
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \\r
+ ((REQUEST) == I2C_NO_STARTSTOP))\r
+\r
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \\r
+ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \\r
+ ((REQUEST) == I2C_NEXT_FRAME) || \\r
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \\r
+ ((REQUEST) == I2C_LAST_FRAME) || \\r
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \\r
+ IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))\r
+\r
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \\r
+ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))\r
+\r
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r
+\r
+#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))\r
+#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))\r
+#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)\r
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))\r
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)\r
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)\r
+\r
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))\r
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))\r
+\r
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\r
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r
+\r
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)\r
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32h7xx_hal_i2c.c file */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32H7xx_HAL_I2C_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_i2c_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of I2C HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_I2C_EX_H\r
+#define STM32H7xx_HAL_I2C_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2CEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter\r
+ * @{\r
+ */\r
+#define I2C_ANALOGFILTER_ENABLE 0x00000000U\r
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus\r
+ * @{\r
+ */\r
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */\r
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */\r
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */\r
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */\r
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */\r
+#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */\r
+#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */\r
+#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);\r
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros\r
+ * @{\r
+ */\r
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\r
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r
+\r
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)\r
+\r
+#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))\r
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))\r
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))\r
+#elif defined(SYSCFG_PMCR_I2C1_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))\r
+#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_I2C_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_pwr.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of PWR HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_PWR_H\r
+#define STM32H7xx_HAL_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Types PWR Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief PWR PVD configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.\r
+ This parameter can be a value of @ref PWR_PVD_detection_level */\r
+\r
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref PWR_PVD_Mode */\r
+}PWR_PVDTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r
+ * @{\r
+ */\r
+#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector level 0 selection : 1V95 */\r
+#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector level 1 selection : 2V1 */\r
+#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector level 2 selection : 2V25 */\r
+#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector level 3 selection : 2V4 */\r
+#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector level 4 selection : 2V55 */\r
+#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector level 5 selection : 2V7 */\r
+#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector level 6 selection : 2V85 */\r
+#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage (Compare internally to VREFINT) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_PVD_Mode PWR PVD Mode\r
+ * @{\r
+ */\r
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */\r
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)\r
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r
+ * @{\r
+ */\r
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)\r
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r
+ * @{\r
+ */\r
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)\r
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale\r
+ * @{\r
+ */\r
+#define PWR_REGULATOR_VOLTAGE_SCALE0 ((uint32_t)0x00000000)\r
+#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)\r
+#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)\r
+#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag PWR Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_STOP ((uint8_t)0x01U)\r
+#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)\r
+#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)\r
+#define PWR_FLAG_SB ((uint8_t)0x04U)\r
+#if defined(DUAL_CORE)\r
+#define PWR_FLAG_CPU_HOLD ((uint8_t)0x05U)\r
+#define PWR_FLAG_CPU2_HOLD ((uint8_t)0x06U)\r
+#define PWR_FLAG2_STOP ((uint8_t)0x07U)\r
+#define PWR_FLAG2_SB_D1 ((uint8_t)0x08U)\r
+#define PWR_FLAG2_SB_D2 ((uint8_t)0x09U)\r
+#define PWR_FLAG2_SB ((uint8_t)0x0AU)\r
+#endif /*DUAL_CORE*/\r
+#define PWR_FLAG_PVDO ((uint8_t)0x0BU)\r
+#define PWR_FLAG_AVDO ((uint8_t)0x0CU)\r
+#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x0DU)\r
+#define PWR_FLAG_ACTVOS ((uint8_t)0x0EU)\r
+#define PWR_FLAG_BRR ((uint8_t)0x0FU)\r
+#define PWR_FLAG_VOSRDY ((uint8_t)0x10U)\r
+#if defined(SMPS)\r
+#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x11U)\r
+#else\r
+#define PWR_FLAG_SCUEN ((uint8_t)0x11U)\r
+#endif /* SMPS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask\r
+ * @{\r
+ */\r
+#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Macro PWR Exported Macro\r
+ * @{\r
+ */\r
+\r
+/** @brief macros configure the main internal regulator output voltage.\r
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption when the device does\r
+ * not operate at the maximum frequency (refer to the datasheets for more details).\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE0: Regulator voltage output Scale 0 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\r
+ * @note PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when Vcore is supplied from LDO.\r
+ * the SYSCFG Clock must be enabled before selecting PWR_REGULATOR_VOLTAGE_SCALE0\r
+ * using macro __HAL_RCC_SYSCFG_CLK_ENABLE().\r
+ * Transition to PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when the system is already in\r
+ * PWR_REGULATOR_VOLTAGE_SCALE1.\r
+ * transition from PWR_REGULATOR_VOLTAGE_SCALE0 is only possible to PWR_REGULATOR_VOLTAGE_SCALE1\r
+ * then once in PWR_REGULATOR_VOLTAGE_SCALE1 it is possible to switch to another voltage scale.\r
+ * After each regulator voltage setting, wait on PWR_FLAG_VOSRDY to be set using macro __HAL_PWR_GET_FLAG\r
+ * To enter low power mode , and if current regulator voltage is PWR_REGULATOR_VOLTAGE_SCALE0 then first\r
+ * switch to PWR_REGULATOR_VOLTAGE_SCALE1 before entering low power mode.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \\r
+do { \\r
+ __IO uint32_t tmpreg = 0x00; \\r
+ if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \\r
+ { \\r
+ MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \\r
+ /* Delay after setting the voltage scaling */ \\r
+ tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \\r
+ MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \\r
+ /* Delay after setting the syscfg boost setting */ \\r
+ tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \\r
+ /* Delay after setting the syscfg boost setting */ \\r
+ tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \\r
+ MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \\r
+ tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \\r
+ } \\r
+ UNUSED(tmpreg); \\r
+} while(0)\r
+\r
+#if defined(DUAL_CORE)\r
+/** @brief Check PWR PVD/AVD and VOSflags are set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled\r
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.\r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the PVDE bit is set.\r
+ * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled\r
+ * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.\r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the AVDE bit is set.\r
+ * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage\r
+ * scaling output selection is ready.\r
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage\r
+ * scaling output selection is ready.\r
+ * @arg PWR_FLAG_SMPSEXTRDY: SMPS External supply ready flag.\r
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset\r
+ * when the device wakes up from Standby mode or by a system reset\r
+ * or power reset.\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @arg PWR_FLAG_STOP: STOP flag\r
+ * @arg PWR_FLAG_SB_D1: StandBy D1 flag\r
+ * @arg PWR_FLAG_SB_D2: StandBy D2 flag\r
+ * @arg PWR_FLAG_CPU1_HOLD: CPU1 system wake up with hold\r
+ * @arg PWR_FLAG_CPU2_HOLD: CPU2 system wake up with hold\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_FLAG(__FLAG__) ( \\r
+((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \\r
+((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \\r
+((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \\r
+((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \\r
+((__FLAG__) == PWR_FLAG_SMPSEXTRDY)?((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) : \\r
+((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \\r
+((__FLAG__) == PWR_FLAG_CPU_HOLD)?((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) : \\r
+((__FLAG__) == PWR_FLAG_CPU2_HOLD)?((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) : \\r
+((__FLAG__) == PWR_FLAG_SB)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \\r
+((__FLAG__) == PWR_FLAG2_SB)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) : \\r
+((__FLAG__) == PWR_FLAG_STOP)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \\r
+((__FLAG__) == PWR_FLAG2_STOP)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) : \\r
+((__FLAG__) == PWR_FLAG_SB_D1)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \\r
+((__FLAG__) == PWR_FLAG2_SB_D1)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) : \\r
+((__FLAG__) == PWR_FLAG_SB_D2)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : \\r
+(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2))\r
+#else\r
+/** @brief Check PWR PVD/AVD and VOSflags are set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled\r
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.\r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the PVDE bit is set.\r
+ * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled\r
+ * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.\r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the AVDE bit is set.\r
+ * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage\r
+ * scaling output selection is ready.\r
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage\r
+ * scaling output selection is ready.\r
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset\r
+ * when the device wakes up from Standby mode or by a system reset\r
+ * or power reset.\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @arg PWR_FLAG_STOP: STOP flag\r
+ * @arg PWR_FLAG_SB_D1: StandBy D1 flag\r
+ * @arg PWR_FLAG_SB_D2: StandBy D2 flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_FLAG(__FLAG__) ( \\r
+((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \\r
+((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \\r
+((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \\r
+((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \\r
+((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \\r
+((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \\r
+((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \\r
+((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \\r
+((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \\r
+((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))\r
+#endif /*DUAL_CORE*/\r
+\r
+\r
+#if defined(DUAL_CORE)\r
+/** @brief Clear PWR flags.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_SB: Standby flag.\r
+ * @arg PWR_CPU_FLAGS: Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \\r
+do { \\r
+ SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \\r
+ SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \\r
+} while(0)\r
+#else\r
+/** @brief Clear PWR flags.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_SB: Standby flag.\r
+ * @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Enable the PVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Enable the PVD EXTI D2 Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Disable the PVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Disable the PVD EXTI D2 Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Enable event on PVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Enable event on PVD EXTI D2 Line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Disable event on PVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Disable event on PVD EXTI D2 Line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \\r
+do { \\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \\r
+} while(0);\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \\r
+do { \\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \\r
+} while(0);\r
+\r
+/**\r
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.\r
+ * @retval EXTI PVD Line Status.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)\r
+\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief checks whether the specified PVD Exti interrupt flag is set or not.\r
+ * @retval EXTI D2 PVD Line Status.\r
+ */\r
+#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Clear the PVD EXTI flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Clear the PVD EXTI D2 flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on PVD EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Include PWR HAL Extension module */\r
+#include "stm32h7xx_hal_pwr_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_PWR_DeInit(void);\r
+void HAL_PWR_EnableBkUpAccess(void);\r
+void HAL_PWR_DisableBkUpAccess(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+/* PVD configuration */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
+void HAL_PWR_EnablePVD(void);\r
+void HAL_PWR_DisablePVD(void);\r
+\r
+/* WakeUp pins configuration */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
+\r
+/* Low Power modes entry */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
+void HAL_PWR_EnterSTANDBYMode(void);\r
+\r
+/* Power PVD IRQ Handler */\r
+void HAL_PWR_PVD_IRQHandler(void);\r
+void HAL_PWR_PVDCallback(void);\r
+\r
+/* Cortex System Control functions *******************************************/\r
+void HAL_PWR_EnableSleepOnExit(void);\r
+void HAL_PWR_DisableSleepOnExit(void);\r
+void HAL_PWR_EnableSEVOnPend(void);\r
+void HAL_PWR_DisableSEVOnPend(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Constants PWR Private Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\r
+ * @{\r
+ */\r
+/*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Macros PWR Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
+\r
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\r
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_NORMAL))\r
+\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
+\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
+\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\r
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32H7xx_HAL_PWR_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_pwr_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of PWR HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_PWR_EX_H\r
+#define STM32H7xx_HAL_PWR_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWREx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Types PWREx Exported Types\r
+ * @{\r
+ */\r
+/**\r
+ * @brief PWREx AVD configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level.\r
+ This parameter can be a value of @ref PWREx_AVD_detection_level */\r
+\r
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref PWREx_AVD_Mode */\r
+}PWREx_AVDTypeDef;\r
+\r
+/**\r
+ * @brief PWREx Wakeup pin configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.\r
+ This parameter can be a value of @ref PWREx_WakeUp_Pins */\r
+\r
+ uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.\r
+ This parameter can be a value of @ref PWREx_PIN_Polarity */\r
+\r
+ uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull.\r
+ This parameter can be a value of @ref PWREx_PIN_Pull */\r
+}PWREx_WakeupPinTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6\r
+#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5\r
+#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4\r
+#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3\r
+#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2\r
+#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1\r
+/* High level and No pull */\r
+#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6\r
+#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5\r
+#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4\r
+#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3\r
+#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2\r
+#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1\r
+/* Low level and No pull */\r
+#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)\r
+#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)\r
+#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)\r
+#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)\r
+#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)\r
+#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration\r
+ * @{\r
+ */\r
+#define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)\r
+#define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration\r
+ * @{\r
+ */\r
+#define PWR_PIN_NO_PULL ((uint32_t)0x00000000U)\r
+#define PWR_PIN_PULL_UP ((uint32_t)0x00000001U)\r
+#define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */\r
+#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */\r
+#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */\r
+#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */\r
+#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */\r
+#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(DUAL_CORE)\r
+/** @defgroup PWREx_Core_Select PWREx Core definition\r
+ * @{\r
+ */\r
+#define PWR_CORE_CPU1 ((uint32_t)0x00000000U)\r
+#define PWR_CORE_CPU2 ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+#endif /*DUAL_CORE*/\r
+\r
+/** @defgroup PWREx_Domains PWREx Domains definition\r
+ * @{\r
+ */\r
+#define PWR_D1_DOMAIN ((uint32_t)0x00000000U)\r
+#define PWR_D2_DOMAIN ((uint32_t)0x00000001U)\r
+#define PWR_D3_DOMAIN ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition\r
+ * @{\r
+ */\r
+#if defined(DUAL_CORE)\r
+#define PWR_D1_DOMAIN_FLAGS ((uint32_t)0x00000000U)\r
+#define PWR_D2_DOMAIN_FLAGS ((uint32_t)0x00000001U)\r
+#else\r
+#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)\r
+#endif /*DUAL_CORE*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_D3_State PWREx D3 Domain State\r
+ * @{\r
+ */\r
+#define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)\r
+#define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_Supply_configuration PWREx Supply configuration\r
+ * @{\r
+ */\r
+#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */\r
+#if defined(SMPS)\r
+#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS only */\r
+#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */\r
+#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */\r
+#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */\r
+#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */\r
+#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */\r
+#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */\r
+#endif /* SMPS */\r
+#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */\r
+\r
+#if defined(SMPS)\r
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \\r
+ PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)\r
+#else\r
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)\r
+#endif /* SMPS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level\r
+ * @{\r
+ */\r
+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0\r
+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1\r
+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2\r
+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_AVD_Mode PWREx AVD Mode\r
+ * @{\r
+ */\r
+#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */\r
+#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale\r
+ * @{\r
+ */\r
+#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)\r
+#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)\r
+#define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection\r
+ * @{\r
+ */\r
+#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */\r
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds\r
+ * @{\r
+ */\r
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)\r
+#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL\r
+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds\r
+ * @{\r
+ */\r
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)\r
+#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL\r
+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16\r
+ * @{\r
+ */\r
+#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the AVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Enable the AVD EXTI D2 Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Disable the AVD EXTI Line 16\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Disable the AVD EXTI D2 Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Enable event on AVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Enable event on AVD EXTI D2 Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Disable event on AVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Disable event on AVD EXTI D2 Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Enable the AVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)\r
+\r
+/**\r
+ * @brief Disable the AVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)\r
+\r
+/**\r
+ * @brief Enable the AVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)\r
+\r
+\r
+/**\r
+ * @brief Disable the AVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)\r
+\r
+\r
+/**\r
+ * @brief AVD EXTI line configuration: set rising & falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { \\r
+ __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \\r
+ __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \\r
+} while(0);\r
+\r
+/**\r
+ * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \\r
+do { \\r
+ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \\r
+ __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \\r
+} while(0);\r
+\r
+/**\r
+ * @brief Check whether the specified AVD EXTI interrupt flag is set or not.\r
+ * @retval EXTI AVD Line Status.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.\r
+ * @retval EXTI D2 AVD Line Status.\r
+ */\r
+#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Clear the AVD EXTI flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Clear the AVD EXTI D2 flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions\r
+ * @{\r
+ */\r
+/* Power supply control functions */\r
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);\r
+uint32_t HAL_PWREx_GetSupplyConfig(void);\r
+/* Power volatge scaling functions */\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r
+uint32_t HAL_PWREx_GetVoltageRange(void);\r
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);\r
+uint32_t HAL_PWREx_GetStopModeVoltageRange(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions\r
+ * @{\r
+ */\r
+/* System low power control functions */\r
+void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);\r
+void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);\r
+void HAL_PWREx_ConfigD3Domain(uint32_t D3State);\r
+\r
+#if defined(DUAL_CORE)\r
+void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);\r
+\r
+/* Power core holding functions */\r
+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);\r
+void HAL_PWREx_ReleaseCore(uint32_t CPU);\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+/* Clear pending event function */\r
+void HAL_PWREx_ClearPendingEvent(void);\r
+\r
+/* Flash low power control functions */\r
+void HAL_PWREx_EnableFlashPowerDown(void);\r
+void HAL_PWREx_DisableFlashPowerDown(void);\r
+/* Wakeup Pins control functions */\r
+void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);\r
+void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);\r
+uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);\r
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);\r
+\r
+/* Power Wakeup PIN IRQ Handler */\r
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);\r
+void HAL_PWREx_WKUP1_Callback(void);\r
+void HAL_PWREx_WKUP2_Callback(void);\r
+void HAL_PWREx_WKUP3_Callback(void);\r
+void HAL_PWREx_WKUP4_Callback(void);\r
+void HAL_PWREx_WKUP5_Callback(void);\r
+void HAL_PWREx_WKUP6_Callback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions\r
+ * @{\r
+ */\r
+/* Backup regulator control functions */\r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);\r
+\r
+/* USB regulator control functions */\r
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);\r
+void HAL_PWREx_EnableUSBVoltageDetector(void);\r
+void HAL_PWREx_DisableUSBVoltageDetector(void);\r
+\r
+/* Battery control functions */\r
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);\r
+void HAL_PWREx_DisableBatteryCharging(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions\r
+ * @{\r
+ */\r
+/* Power VBAT/Temperature monitoring functions */\r
+void HAL_PWREx_EnableMonitoring(void);\r
+void HAL_PWREx_DisableMonitoring(void);\r
+uint32_t HAL_PWREx_GetTemperatureLevel(void);\r
+uint32_t HAL_PWREx_GetVBATLevel(void);\r
+\r
+/* Power AVD configuration functions */\r
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);\r
+void HAL_PWREx_EnableAVD(void);\r
+void HAL_PWREx_DisableAVD(void);\r
+\r
+/* Power PVD/AVD IRQ Handler */\r
+void HAL_PWREx_PVD_AVD_IRQHandler(void);\r
+void HAL_PWREx_AVDCallback(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Private_Macros PWREx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters\r
+ * @{\r
+ */\r
+#if defined(SMPS)\r
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \\r
+ ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) || \\r
+ ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) || \\r
+ ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) || \\r
+ ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \\r
+ ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \\r
+ ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) || \\r
+ ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) || \\r
+ ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))\r
+\r
+#else\r
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \\r
+ ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))\r
+#endif /*SMPS*/\r
+\r
+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))\r
+\r
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || \\r
+ ((DOMAIN) == PWR_D2_DOMAIN) || \\r
+ ((DOMAIN) == PWR_D3_DOMAIN))\r
+\r
+#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))\r
+\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \\r
+ ((PIN) == PWR_WAKEUP_PIN2) || \\r
+ ((PIN) == PWR_WAKEUP_PIN3) || \\r
+ ((PIN) == PWR_WAKEUP_PIN4) || \\r
+ ((PIN) == PWR_WAKEUP_PIN5) || \\r
+ ((PIN) == PWR_WAKEUP_PIN6) || \\r
+ ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \\r
+ ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \\r
+ ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \\r
+ ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \\r
+ ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \\r
+ ((PIN) == PWR_WAKEUP_PIN6_HIGH) || \\r
+ ((PIN) == PWR_WAKEUP_PIN1_LOW) || \\r
+ ((PIN) == PWR_WAKEUP_PIN2_LOW) || \\r
+ ((PIN) == PWR_WAKEUP_PIN3_LOW) || \\r
+ ((PIN) == PWR_WAKEUP_PIN4_LOW) || \\r
+ ((PIN) == PWR_WAKEUP_PIN5_LOW) || \\r
+ ((PIN) == PWR_WAKEUP_PIN6_LOW))\r
+\r
+#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \\r
+ ((POLARITY) == PWR_PIN_POLARITY_LOW))\r
+\r
+#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || \\r
+ ((PULL) == PWR_PIN_PULL_UP) || \\r
+ ((PULL) == PWR_PIN_PULL_DOWN))\r
+\r
+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || \\r
+ ((FLAG) == PWR_WAKEUP_FLAG2) || \\r
+ ((FLAG) == PWR_WAKEUP_FLAG3) || \\r
+ ((FLAG) == PWR_WAKEUP_FLAG4) || \\r
+ ((FLAG) == PWR_WAKEUP_FLAG5) || \\r
+ ((FLAG) == PWR_WAKEUP_FLAG6))\r
+\r
+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \\r
+ ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))\r
+\r
+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \\r
+ ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \\r
+ ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \\r
+ ((MODE) == PWR_AVD_MODE_NORMAL))\r
+\r
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\\r
+ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))\r
+\r
+#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))\r
+\r
+#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)\r
+\r
+#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \\r
+ ((FLAG) == PWR_D2_DOMAIN_FLAGS))\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32H7xx_HAL_PWR_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_rcc.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of RCC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_RCC_H\r
+#define STM32H7xx_HAL_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Types RCC Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief RCC PLL configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLState; /*!< The new state of the PLL.\r
+ This parameter can be a value of @ref RCC_PLL_Config */\r
+\r
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.\r
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
+\r
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 63 */\r
+\r
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.\r
+ This parameter must be a number between Min_Data = 4 and Max_Data = 512 */\r
+\r
+ uint32_t PLLP; /*!< PLLP: Division factor for system clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 128\r
+ odd division factors are not allowed */\r
+\r
+ uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r
+\r
+ uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r
+ uint32_t PLLRGE; /*!<PLLRGE: PLL1 clock Input range\r
+ This parameter must be a value of @ref RCC_PLL1_VCI_Range */\r
+ uint32_t PLLVCOSEL; /*!<PLLVCOSEL: PLL1 clock Output range\r
+ This parameter must be a value of @ref RCC_PLL1_VCO_Range */\r
+\r
+ uint32_t PLLFRACN; /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for\r
+ PLL1 VCO It should be a value between 0 and 8191 */\r
+\r
+}RCC_PLLInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OscillatorType; /*!< The oscillators to be configured.\r
+ This parameter can be a value of @ref RCC_Oscillator_Type */\r
+\r
+ uint32_t HSEState; /*!< The new state of the HSE.\r
+ This parameter can be a value of @ref RCC_HSE_Config */\r
+\r
+ uint32_t LSEState; /*!< The new state of the LSE.\r
+ This parameter can be a value of @ref RCC_LSE_Config */\r
+\r
+ uint32_t HSIState; /*!< The new state of the HSI.\r
+ This parameter can be a value of @ref RCC_HSI_Config */\r
+\r
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */\r
+\r
+ uint32_t LSIState; /*!< The new state of the LSI.\r
+ This parameter can be a value of @ref RCC_LSI_Config */\r
+\r
+ uint32_t HSI48State; /*!< The new state of the HSI48.\r
+ This parameter can be a value of @ref RCC_HSI48_Config */\r
+\r
+ uint32_t CSIState; /*!< The new state of the CSI.\r
+ This parameter can be a value of @ref RCC_CSI_Config */\r
+\r
+ uint32_t CSICalibrationValue; /*!< The calibration trimming value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */\r
+\r
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */\r
+\r
+}RCC_OscInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC System, AHB and APB busses clock configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockType; /*!< The clock to be configured.\r
+ This parameter can be a value of @ref RCC_System_Clock_Type */\r
+\r
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.\r
+ This parameter can be a value of @ref RCC_System_Clock_Source */\r
+\r
+ uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be\r
+ a value of @ref RCC_SYS_Clock_Source */\r
+\r
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
+ This parameter can be a value of @ref RCC_HCLK_Clock_Source */\r
+\r
+ uint32_t APB3CLKDivider; /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB3_Clock_Source */\r
+\r
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_Clock_Source */\r
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB2_Clock_Source */\r
+ uint32_t APB4CLKDivider; /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB4_Clock_Source */\r
+}RCC_ClkInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Oscillator_Type RCC Oscillator Type\r
+ * @{\r
+ */\r
+#define RCC_OSCILLATORTYPE_NONE (0x00000000U)\r
+#define RCC_OSCILLATORTYPE_HSE (0x00000001U)\r
+#define RCC_OSCILLATORTYPE_HSI (0x00000002U)\r
+#define RCC_OSCILLATORTYPE_LSE (0x00000004U)\r
+#define RCC_OSCILLATORTYPE_LSI (0x00000008U)\r
+#define RCC_OSCILLATORTYPE_CSI (0x00000010U)\r
+#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Config RCC HSE Config\r
+ * @{\r
+ */\r
+#define RCC_HSE_OFF (0x00000000U)\r
+#define RCC_HSE_ON RCC_CR_HSEON\r
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Config RCC LSE Config\r
+ * @{\r
+ */\r
+#define RCC_LSE_OFF (0x00000000U)\r
+#define RCC_LSE_ON RCC_BDCR_LSEON\r
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSI_Config RCC HSI Config\r
+ * @{\r
+ */\r
+#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */\r
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */\r
+\r
+#define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */\r
+#define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */\r
+#define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */\r
+#define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */\r
+\r
+\r
+\r
+#define RCC_HSICALIBRATION_DEFAULT (0x20U) /* Default HSI calibration trimming value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSI48_Config RCC HSI48 Config\r
+ * @{\r
+ */\r
+#define RCC_HSI48_OFF ((uint8_t)0x00)\r
+#define RCC_HSI48_ON ((uint8_t)0x01)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Config RCC LSI Config\r
+ * @{\r
+ */\r
+#define RCC_LSI_OFF (0x00000000U)\r
+#define RCC_LSI_ON RCC_CSR_LSION\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_CSI_Config RCC CSI Config\r
+ * @{\r
+ */\r
+#define RCC_CSI_OFF (0x00000000U)\r
+#define RCC_CSI_ON RCC_CR_CSION\r
+\r
+#define RCC_CSICALIBRATION_DEFAULT (0x10U) /* Default CSI calibration trimming value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Config RCC PLL Config\r
+ * @{\r
+ */\r
+#define RCC_PLL_NONE (0x00000000U)\r
+#define RCC_PLL_OFF (0x00000001U)\r
+#define RCC_PLL_ON (0x00000002U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source\r
+ * @{\r
+ */\r
+#define RCC_PLLSOURCE_HSI (0x00000000U)\r
+#define RCC_PLLSOURCE_CSI (0x00000001U)\r
+#define RCC_PLLSOURCE_HSE (0x00000002U)\r
+#define RCC_PLLSOURCE_NONE (0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output\r
+ * @{\r
+ */\r
+#define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN\r
+#define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN\r
+#define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range\r
+ * @{\r
+ */\r
+#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0\r
+#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1\r
+#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2\r
+#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range\r
+ * @{\r
+ */\r
+#define RCC_PLL1VCOWIDE (0x00000000U)\r
+#define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_System_Clock_Type RCC System Clock Type\r
+ * @{\r
+ */\r
+#define RCC_CLOCKTYPE_SYSCLK (0x00000001U)\r
+#define RCC_CLOCKTYPE_HCLK (0x00000002U)\r
+#define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)\r
+#define RCC_CLOCKTYPE_PCLK1 (0x00000008U)\r
+#define RCC_CLOCKTYPE_PCLK2 (0x00000010U)\r
+#define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Source RCC System Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI\r
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1\r
+#define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2\r
+#define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4\r
+#define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8\r
+#define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16\r
+#define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64\r
+#define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128\r
+#define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256\r
+#define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source\r
+ * @{\r
+ */\r
+#define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1\r
+#define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2\r
+#define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4\r
+#define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8\r
+#define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16\r
+#define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64\r
+#define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128\r
+#define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256\r
+#define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB3_Clock_Source RCC APB3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1\r
+#define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2\r
+#define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4\r
+#define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8\r
+#define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1\r
+#define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2\r
+#define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4\r
+#define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8\r
+#define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Source RCC APB2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1\r
+#define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2\r
+#define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4\r
+#define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8\r
+#define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB4_Clock_Source RCC APB4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1\r
+#define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2\r
+#define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4\r
+#define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8\r
+#define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_RTCCLKSOURCE_LSE (0x00000100U)\r
+#define RCC_RTCCLKSOURCE_LSI (0x00000200U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_MCO_Index RCC MCO Index\r
+ * @{\r
+ */\r
+#define RCC_MCO1 (0x00000000U)\r
+#define RCC_MCO2 (0x00000001U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO1SOURCE_HSI (0x00000000U)\r
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0\r
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1\r
+#define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)\r
+#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO2SOURCE_SYSCLK (0x00000000U)\r
+#define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0\r
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1\r
+#define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)\r
+#define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2\r
+#define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCOx Clock Prescaler\r
+ * @{\r
+ */\r
+#define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0\r
+#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1\r
+#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)\r
+#define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2\r
+#define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3\r
+#define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)\r
+#define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)\r
+#define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)\r
+#define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)\r
+#define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)\r
+#define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)\r
+#define RCC_MCODIV_15 RCC_CFGR_MCO1PRE\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Interrupt RCC Interrupt\r
+ * @{\r
+ */\r
+#define RCC_IT_LSIRDY (0x00000001U)\r
+#define RCC_IT_LSERDY (0x00000002U)\r
+#define RCC_IT_HSIRDY (0x00000004U)\r
+#define RCC_IT_HSERDY (0x00000008U)\r
+#define RCC_IT_CSIRDY (0x00000010U)\r
+#define RCC_IT_HSI48RDY (0x00000020U)\r
+#define RCC_IT_PLLRDY (0x00000040U)\r
+#define RCC_IT_PLL2RDY (0x00000080U)\r
+#define RCC_IT_PLL3RDY (0x00000100U)\r
+#define RCC_IT_LSECSS (0x00000200U)\r
+#define RCC_IT_CSS (0x00000400U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Flag RCC Flag\r
+ * Elements values convention: XXXYYYYYb\r
+ * - YYYYY : Flag position in the register\r
+ * - XXX : Register index\r
+ * - 001: CR register\r
+ * - 010: BDCR register\r
+ * - 011: CSR register\r
+ * - 100: RSR register\r
+ * @{\r
+ */\r
+/* Flags in the CR register */\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x22)\r
+#define RCC_FLAG_HSIDIV ((uint8_t)0x25)\r
+#define RCC_FLAG_CSIRDY ((uint8_t)0x28)\r
+#define RCC_FLAG_HSI48RDY ((uint8_t)0x2D)\r
+#define RCC_FLAG_D1CKRDY ((uint8_t)0x2E)\r
+#define RCC_FLAG_D2CKRDY ((uint8_t)0x2F)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)\r
+#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)\r
+/* Flags in the BDCR register */\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)\r
+\r
+/* Flags in the CSR register */\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)\r
+\r
+/* Flags in the RSR register */\r
+#define RCC_FLAG_CPURST ((uint8_t)0x91)\r
+\r
+#define RCC_FLAG_D1RST ((uint8_t)0x93)\r
+#define RCC_FLAG_D2RST ((uint8_t)0x94)\r
+#define RCC_FLAG_BORRST ((uint8_t)0x95)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x96)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x97)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x98)\r
+#define RCC_FLAG_IWDG1RST ((uint8_t)0x9A)\r
+#define RCC_FLAG_WWDG1RST ((uint8_t)0x9C)\r
+#define RCC_FLAG_LPWR1RST ((uint8_t)0x9E)\r
+#define RCC_FLAG_LPWR2RST ((uint8_t)0x9F)\r
+\r
+#if defined(DUAL_CORE)\r
+#define RCC_FLAG_C1RST (RCC_FLAG_CPURST)\r
+#define RCC_FLAG_C2RST ((uint8_t)0x92)\r
+#define RCC_FLAG_SFTR1ST (RCC_FLAG_SFTRST)\r
+#define RCC_FLAG_SFTR2ST ((uint8_t)0x99)\r
+#define RCC_FLAG_WWDG2RST ((uint8_t)0x9D)\r
+#define RCC_FLAG_IWDG2RST ((uint8_t)0x9B)\r
+#endif /*DUAL_CORE*/\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config\r
+ * @{\r
+ */\r
+#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */\r
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */\r
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */\r
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Stop_WakeUpClock RCC Stop WakeUpClock\r
+ * @{\r
+ */\r
+#define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)\r
+#define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock\r
+ * @{\r
+ */\r
+#define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)\r
+#define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Enable or disable the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_MDMA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* JPEG */\r
+\r
+\r
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))\r
+#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))\r
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)\r
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)\r
+\r
+#define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)\r
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)\r
+\r
+\r
+/** @brief Enable or disable the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /*DUAL_CORE*/\r
+\r
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))\r
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))\r
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))\r
+#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))\r
+#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))\r
+#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))\r
+#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)\r
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)\r
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U)\r
+#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U)\r
+#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)\r
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)\r
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U)\r
+#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U)\r
+#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)\r
+\r
+/** @brief Enable or disable the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))\r
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))\r
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))\r
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))\r
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))\r
+#define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))\r
+#define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))\r
+#define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)\r
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)\r
+#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)\r
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)\r
+#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)\r
+#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)\r
+#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)\r
+\r
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)\r
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)\r
+#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)\r
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)\r
+#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)\r
+#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)\r
+#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)\r
+\r
+/** @brief Enable or disable the AHB4 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_BDMA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_HSEM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)\r
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)\r
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)\r
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)\r
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)\r
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)\r
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)\r
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)\r
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)\r
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)\r
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)\r
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)\r
+#define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)\r
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)\r
+#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)\r
+#define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB4 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)\r
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)\r
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)\r
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)\r
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U)\r
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U)\r
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U)\r
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U)\r
+#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)\r
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)\r
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)\r
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)\r
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U)\r
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U)\r
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U)\r
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U)\r
+#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)\r
+\r
+\r
+/** @brief Enable or disable the APB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /*DSI*/\r
+\r
+#define __HAL_RCC_WWDG1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)\r
+#endif /*DSI*/\r
+#define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)\r
+\r
+\r
+/** @brief Get the enable or disable status of the APB3 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U)\r
+#endif /*DSI*/\r
+#define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U)\r
+#endif /*DSI*/\r
+#define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)\r
+\r
+\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /*DUAL_CORE*/\r
+\r
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DAC12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CRS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_MDIOS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)\r
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)\r
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)\r
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)\r
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)\r
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)\r
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)\r
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)\r
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)\r
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)\r
+\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)\r
+#endif /*DUAL_CORE*/\r
+\r
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)\r
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)\r
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)\r
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)\r
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)\r
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)\r
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)\r
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)\r
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)\r
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)\r
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)\r
+#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)\r
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)\r
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)\r
+#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)\r
+#define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)\r
+#define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)\r
+#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)\r
+#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)\r
+\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)\r
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)\r
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)\r
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)\r
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)\r
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)\r
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)\r
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)\r
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)\r
+#define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)\r
+#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)\r
+#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)\r
+#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)\r
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)\r
+#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)\r
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)\r
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)\r
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)\r
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)\r
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)\r
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)\r
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)\r
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)\r
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)\r
+#define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)\r
+#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)\r
+#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)\r
+#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)\r
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)\r
+#define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)\r
+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)\r
+\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)\r
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)\r
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)\r
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)\r
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)\r
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)\r
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)\r
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)\r
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)\r
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)\r
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)\r
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)\r
+#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)\r
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)\r
+#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)\r
+\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)\r
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)\r
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)\r
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)\r
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)\r
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)\r
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)\r
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)\r
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)\r
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)\r
+#define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)\r
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U)\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)\r
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)\r
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)\r
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)\r
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)\r
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)\r
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)\r
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)\r
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)\r
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)\r
+#define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)\r
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U)\r
+\r
+\r
+/** @brief Enable or disable the APB4 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_COMP12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_VREF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_RTC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)\r
+#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)\r
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)\r
+#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)\r
+#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)\r
+#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)\r
+#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)\r
+#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)\r
+#define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)\r
+#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)\r
+#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)\r
+#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)\r
+\r
+/** @brief Get the enable or disable status of the APB4 peripheral clock\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)\r
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)\r
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)\r
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)\r
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)\r
+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)\r
+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U)\r
+#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U)\r
+#define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)\r
+#define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)\r
+#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)\r
+#define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U)\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)\r
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)\r
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)\r
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)\r
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)\r
+#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)\r
+#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U)\r
+#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U)\r
+#define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)\r
+#define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)\r
+#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)\r
+#define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U)\r
+\r
+\r
+#if defined(DUAL_CORE)\r
+\r
+/* Exported macros for RCC_C1 -------------------------------------------------*/\r
+\r
+/** @brief Enable or disable the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+\r
+\r
+#define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))\r
+#define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))\r
+#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))\r
+#define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))\r
+#define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))\r
+#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))\r
+\r
+\r
+\r
+\r
+/** @brief Enable or disable the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_ART_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))\r
+#define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))\r
+#define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))\r
+#define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))\r
+#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))\r
+#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))\r
+#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))\r
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))\r
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))\r
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))\r
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))\r
+\r
+/** @brief Enable or disable the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))\r
+#define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))\r
+#define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))\r
+#define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))\r
+#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))\r
+#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))\r
+#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))\r
+#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))\r
+\r
+/** @brief Enable or disable the AHB4 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)\r
+#define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)\r
+#define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)\r
+#define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)\r
+#define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)\r
+#define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)\r
+#define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)\r
+#define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)\r
+#define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)\r
+#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)\r
+#define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)\r
+#define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)\r
+#define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)\r
+#define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)\r
+#define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)\r
+#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)\r
+\r
+\r
+/** @brief Enable or disable the APB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)\r
+#define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)\r
+#define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)\r
+#define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)\r
+#define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)\r
+#define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)\r
+#define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)\r
+#define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)\r
+#define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)\r
+#define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)\r
+#define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)\r
+#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)\r
+#define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)\r
+#define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)\r
+#define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)\r
+#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)\r
+#define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)\r
+#define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)\r
+#define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)\r
+#define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)\r
+#define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)\r
+#define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)\r
+#define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)\r
+#define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)\r
+#define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)\r
+#define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)\r
+#define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)\r
+#define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)\r
+#define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)\r
+#define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)\r
+#define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)\r
+#define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)\r
+#define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)\r
+#define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)\r
+#define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)\r
+#define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)\r
+#define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)\r
+#define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)\r
+#define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)\r
+#define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)\r
+#define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)\r
+#define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)\r
+#define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)\r
+#define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)\r
+#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)\r
+#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)\r
+\r
+/** @brief Enable or disable the APB4 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)\r
+#define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)\r
+#define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)\r
+#define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)\r
+#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)\r
+#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)\r
+#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)\r
+#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)\r
+#define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)\r
+#define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)\r
+#define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)\r
+#define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)\r
+\r
+/* Exported macros for RCC_C2 -------------------------------------------------*/\r
+\r
+/** @brief Enable or disable the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+\r
+#define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_FLASH_C2_ALLOCATE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ITCM_C2_ALLOCATE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+\r
+\r
+#define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))\r
+#define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))\r
+#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))\r
+#define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))\r
+#define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))\r
+#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))\r
+#define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))\r
+#define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))\r
+#define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))\r
+#define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))\r
+#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))\r
+\r
+/** @brief Enable or disable the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_ART_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))\r
+#define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))\r
+#define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))\r
+#define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))\r
+#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))\r
+#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))\r
+#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))\r
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))\r
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))\r
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))\r
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))\r
+\r
+/** @brief Enable or disable the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))\r
+#define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))\r
+#define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))\r
+#define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))\r
+#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))\r
+#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))\r
+#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))\r
+#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))\r
+\r
+/** @brief Enable or disable the AHB4 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)\r
+#define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)\r
+#define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)\r
+#define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)\r
+#define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)\r
+#define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)\r
+#define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)\r
+#define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)\r
+#define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)\r
+#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)\r
+#define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)\r
+#define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)\r
+#define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)\r
+#define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)\r
+#define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)\r
+#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)\r
+\r
+\r
+/** @brief Enable or disable the APB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)\r
+#define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)\r
+#define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+#define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)\r
+#define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)\r
+#define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)\r
+#define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)\r
+#define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)\r
+#define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)\r
+#define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)\r
+#define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)\r
+#define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)\r
+#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)\r
+#define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)\r
+#define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)\r
+#define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)\r
+#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)\r
+#define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)\r
+#define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)\r
+#define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)\r
+#define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)\r
+#define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)\r
+#define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)\r
+#define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)\r
+#define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)\r
+#define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)\r
+#define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)\r
+#define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)\r
+#define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)\r
+#define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)\r
+#define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)\r
+#define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)\r
+#define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)\r
+#define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)\r
+#define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)\r
+#define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)\r
+#define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)\r
+#define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)\r
+#define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)\r
+#define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)\r
+#define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)\r
+#define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)\r
+#define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)\r
+#define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)\r
+#define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)\r
+#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)\r
+#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)\r
+\r
+/** @brief Enable or disable the APB4 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+\r
+#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+\r
+\r
+#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)\r
+#define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)\r
+#define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)\r
+#define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)\r
+#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)\r
+#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)\r
+#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)\r
+#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)\r
+#define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)\r
+#define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)\r
+#define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)\r
+#define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+/** @brief Enable or disable the AHB3 peripheral reset.\r
+ */\r
+\r
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))\r
+#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))\r
+\r
+\r
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)\r
+#define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))\r
+#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))\r
+\r
+\r
+\r
+/** @brief Force or release the AHB1 peripheral reset.\r
+ */\r
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))\r
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))\r
+#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))\r
+#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))\r
+\r
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)\r
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))\r
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))\r
+#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))\r
+#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))\r
+\r
+\r
+/** @brief Force or release the AHB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\r
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\r
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))\r
+\r
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)\r
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))\r
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))\r
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))\r
+\r
+\r
+/** @brief Force or release the AHB4 peripheral reset.\r
+ */\r
+\r
+#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)\r
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)\r
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)\r
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)\r
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)\r
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)\r
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)\r
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)\r
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)\r
+#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)\r
+#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)\r
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)\r
+#define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)\r
+#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)\r
+#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)\r
+\r
+#define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)\r
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)\r
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)\r
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)\r
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)\r
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)\r
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)\r
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)\r
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)\r
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)\r
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)\r
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)\r
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)\r
+#define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)\r
+#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)\r
+#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)\r
+\r
+\r
+/** @brief Force or release the APB3 peripheral reset.\r
+ */\r
+#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFFU)\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)\r
+#endif /*DSI*/\r
+\r
+#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)\r
+#endif /*DSI*/\r
+\r
+/** @brief Force or release the APB1 peripheral reset.\r
+ */\r
+#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)\r
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)\r
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)\r
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)\r
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)\r
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)\r
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)\r
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)\r
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)\r
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)\r
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)\r
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)\r
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)\r
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)\r
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)\r
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)\r
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)\r
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)\r
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)\r
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)\r
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)\r
+#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)\r
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)\r
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)\r
+#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)\r
+#define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)\r
+#define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)\r
+#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)\r
+#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)\r
+\r
+#define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)\r
+#define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)\r
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)\r
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)\r
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)\r
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)\r
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)\r
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)\r
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)\r
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)\r
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)\r
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)\r
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)\r
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)\r
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)\r
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)\r
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)\r
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)\r
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)\r
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)\r
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)\r
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)\r
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)\r
+#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)\r
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)\r
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)\r
+#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)\r
+#define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)\r
+#define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)\r
+#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)\r
+#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)\r
+\r
+/** @brief Force or release the APB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)\r
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)\r
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)\r
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)\r
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)\r
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)\r
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)\r
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)\r
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)\r
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)\r
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)\r
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)\r
+#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)\r
+#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)\r
+#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)\r
+\r
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)\r
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)\r
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)\r
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)\r
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)\r
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)\r
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)\r
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)\r
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)\r
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)\r
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)\r
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)\r
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)\r
+#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)\r
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)\r
+#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)\r
+\r
+/** @brief Force or release the APB4 peripheral reset.\r
+ */\r
+\r
+#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)\r
+#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)\r
+#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)\r
+#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)\r
+#define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)\r
+#define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)\r
+#define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)\r
+#define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)\r
+#define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)\r
+#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)\r
+#define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)\r
+\r
+#define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)\r
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)\r
+#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)\r
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)\r
+#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)\r
+#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)\r
+#define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)\r
+#define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)\r
+#define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)\r
+#define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)\r
+#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)\r
+#define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)\r
+\r
+/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+\r
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))\r
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))\r
+#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))\r
+#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))\r
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))\r
+\r
+\r
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))\r
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))\r
+#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))\r
+#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))\r
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U)\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)\r
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)\r
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)\r
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)\r
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)\r
+\r
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)\r
+\r
+#if defined(JPEG)\r
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U)\r
+#endif /* JPEG */\r
+\r
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)\r
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)\r
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)\r
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)\r
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)\r
+\r
+\r
+/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))\r
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))\r
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))\r
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))\r
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))\r
+\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))\r
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))\r
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))\r
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))\r
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)\r
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)\r
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U)\r
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)\r
+\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)\r
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)\r
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U)\r
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)\r
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U)\r
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)\r
+\r
+\r
+/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))\r
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))\r
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))\r
+\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))\r
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))\r
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))\r
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)\r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)\r
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)\r
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)\r
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)\r
+\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)\r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)\r
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)\r
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)\r
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)\r
+\r
+\r
+/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)\r
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)\r
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)\r
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)\r
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))\r
+\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)\r
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)\r
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)\r
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)\r
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))\r
+\r
+\r
+/** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U)\r
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U)\r
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)\r
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)\r
+\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U)\r
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U)\r
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)\r
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)\r
+\r
+\r
+/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)\r
+#endif /*DSI*/\r
+#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)\r
+#endif /*DSI*/\r
+#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)\r
+\r
+\r
+/** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U)\r
+#endif /*DSI*/\r
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)\r
+\r
+#if defined(LTDC)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U)\r
+#endif /* LTDC */\r
+\r
+#if defined(DSI)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U)\r
+#endif /*DSI*/\r
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)\r
+\r
+\r
+/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)\r
+\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)\r
+#endif /*DUAL_CORE*/\r
+\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)\r
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)\r
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)\r
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)\r
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)\r
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)\r
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)\r
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)\r
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)\r
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)\r
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)\r
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)\r
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)\r
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)\r
+\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)\r
+\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)\r
+#endif /*DUAL_CORE*/\r
+\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)\r
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)\r
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)\r
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)\r
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)\r
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)\r
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)\r
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)\r
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)\r
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)\r
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)\r
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)\r
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)\r
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)\r
+\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)\r
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)\r
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)\r
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)\r
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)\r
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U)\r
+#endif /*DUAL_CORE*/\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)\r
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)\r
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)\r
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)\r
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)\r
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)\r
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)\r
+\r
+\r
+/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)\r
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)\r
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)\r
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)\r
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)\r
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)\r
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)\r
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)\r
+\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)\r
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)\r
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)\r
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)\r
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)\r
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)\r
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)\r
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)\r
+\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)\r
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)\r
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)\r
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)\r
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)\r
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U)\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)\r
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)\r
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)\r
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)\r
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)\r
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U)\r
+\r
+\r
+/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)\r
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)\r
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)\r
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)\r
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)\r
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)\r
+#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)\r
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)\r
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)\r
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)\r
+\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)\r
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)\r
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)\r
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)\r
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)\r
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)\r
+#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)\r
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)\r
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)\r
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)\r
+\r
+\r
+\r
+/** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)\r
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)\r
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)\r
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)\r
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U)\r
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U)\r
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)\r
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)\r
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)\r
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U)\r
+\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)\r
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)\r
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)\r
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)\r
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U)\r
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U)\r
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)\r
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)\r
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)\r
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U)\r
+\r
+\r
+#if defined(DUAL_CORE)\r
+\r
+/** @brief Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))\r
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))\r
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))\r
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))\r
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))\r
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))\r
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))\r
+\r
+\r
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))\r
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))\r
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))\r
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))\r
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))\r
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))\r
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))\r
+\r
+\r
+\r
+/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))\r
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))\r
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))\r
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))\r
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))\r
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))\r
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))\r
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))\r
+\r
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))\r
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))\r
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))\r
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))\r
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))\r
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))\r
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))\r
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))\r
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))\r
+\r
+/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))\r
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))\r
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))\r
+\r
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))\r
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))\r
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))\r
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))\r
+\r
+/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)\r
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)\r
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)\r
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)\r
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)\r
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)\r
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)\r
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)\r
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)\r
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)\r
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)\r
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)\r
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)\r
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)\r
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)\r
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))\r
+\r
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)\r
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)\r
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)\r
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)\r
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)\r
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)\r
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)\r
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)\r
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)\r
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)\r
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)\r
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)\r
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)\r
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)\r
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)\r
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))\r
+\r
+/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)\r
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)\r
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)\r
+\r
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)\r
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)\r
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)\r
+\r
+/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)\r
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)\r
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)\r
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)\r
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)\r
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)\r
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)\r
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)\r
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)\r
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)\r
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)\r
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)\r
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)\r
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)\r
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)\r
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)\r
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)\r
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)\r
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)\r
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)\r
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)\r
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)\r
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)\r
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)\r
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)\r
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)\r
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)\r
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)\r
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)\r
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)\r
+\r
+\r
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)\r
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)\r
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)\r
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)\r
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)\r
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)\r
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)\r
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)\r
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)\r
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)\r
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)\r
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)\r
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)\r
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)\r
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)\r
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)\r
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)\r
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)\r
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)\r
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)\r
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)\r
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)\r
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)\r
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)\r
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)\r
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)\r
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)\r
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)\r
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)\r
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)\r
+\r
+/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)\r
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)\r
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)\r
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)\r
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)\r
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)\r
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)\r
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)\r
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)\r
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)\r
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)\r
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)\r
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)\r
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)\r
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)\r
+\r
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)\r
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)\r
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)\r
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)\r
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)\r
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)\r
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)\r
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)\r
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)\r
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)\r
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)\r
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)\r
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)\r
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)\r
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)\r
+\r
+/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)\r
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)\r
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)\r
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)\r
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)\r
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)\r
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)\r
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)\r
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)\r
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)\r
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)\r
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)\r
+\r
+\r
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)\r
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)\r
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)\r
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)\r
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)\r
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)\r
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)\r
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)\r
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)\r
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)\r
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)\r
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)\r
+\r
+/** @brief Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+\r
+\r
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))\r
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))\r
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))\r
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))\r
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))\r
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))\r
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))\r
+\r
+\r
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))\r
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))\r
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))\r
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))\r
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))\r
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))\r
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))\r
+\r
+\r
+\r
+/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))\r
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))\r
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))\r
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))\r
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))\r
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))\r
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))\r
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))\r
+\r
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))\r
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))\r
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))\r
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))\r
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))\r
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))\r
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))\r
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))\r
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))\r
+\r
+/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))\r
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))\r
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))\r
+\r
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))\r
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))\r
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))\r
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))\r
+\r
+/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)\r
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)\r
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)\r
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)\r
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)\r
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)\r
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)\r
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)\r
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)\r
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)\r
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)\r
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)\r
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)\r
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)\r
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)\r
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))\r
+\r
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)\r
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)\r
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)\r
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)\r
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)\r
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)\r
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)\r
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)\r
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)\r
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)\r
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)\r
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)\r
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)\r
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)\r
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)\r
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))\r
+\r
+/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)\r
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)\r
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)\r
+\r
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)\r
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)\r
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)\r
+\r
+/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)\r
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)\r
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)\r
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)\r
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)\r
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)\r
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)\r
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)\r
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)\r
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)\r
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)\r
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)\r
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)\r
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)\r
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)\r
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)\r
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)\r
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)\r
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)\r
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)\r
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)\r
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)\r
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)\r
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)\r
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)\r
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)\r
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)\r
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)\r
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)\r
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)\r
+\r
+\r
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)\r
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)\r
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)\r
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)\r
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)\r
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)\r
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)\r
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)\r
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)\r
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)\r
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)\r
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)\r
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)\r
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)\r
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)\r
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)\r
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)\r
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)\r
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)\r
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)\r
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)\r
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)\r
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)\r
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)\r
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)\r
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)\r
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)\r
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)\r
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)\r
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)\r
+\r
+/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)\r
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)\r
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)\r
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)\r
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)\r
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)\r
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)\r
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)\r
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)\r
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)\r
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)\r
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)\r
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)\r
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)\r
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)\r
+\r
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)\r
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)\r
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)\r
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)\r
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)\r
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)\r
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)\r
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)\r
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)\r
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)\r
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)\r
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)\r
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)\r
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)\r
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)\r
+\r
+/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.\r
+ * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.\r
+ */\r
+\r
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)\r
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)\r
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)\r
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)\r
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)\r
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)\r
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)\r
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)\r
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)\r
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)\r
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)\r
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)\r
+\r
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)\r
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)\r
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)\r
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)\r
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)\r
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)\r
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)\r
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)\r
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)\r
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)\r
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)\r
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN\r
+ * @note After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP\r
+ */\r
+#else\r
+/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN\r
+ * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP\r
+ */\r
+#endif /*DUAL_CORE*/\r
+\r
+#define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)\r
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)\r
+#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)\r
+#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)\r
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)\r
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)\r
+#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)\r
+#define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)\r
+#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)\r
+#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)\r
+#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)\r
+#define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)\r
+#define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)\r
+#define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)\r
+\r
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)\r
+#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)\r
+\r
+#define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)\r
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)\r
+#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)\r
+#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)\r
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)\r
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)\r
+#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)\r
+#define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)\r
+#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)\r
+#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)\r
+#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN)\r
+#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN)\r
+#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN)\r
+#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN)\r
+\r
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)\r
+#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)\r
+\r
+\r
+/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).\r
+ * @note After enabling the HSI, the application software should wait on\r
+ * HSIRDY flag to be set indicating that HSI clock is stable and can\r
+ * be used to clock the PLL and/or system clock.\r
+ * @note HSI can not be stopped if it is used directly or through the PLL\r
+ * as system clock. In this case, you have to select another source\r
+ * of the system clock then stop the HSI.\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @param __STATE__ specifies the new state of the HSI.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSI_OFF turn OFF the HSI oscillator\r
+ * @arg RCC_HSI_ON turn ON the HSI oscillator\r
+ * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)\r
+ * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2\r
+ * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4\r
+ * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles.\r
+ */\r
+#define __HAL_RCC_HSI_CONFIG(__STATE__) \\r
+ MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))\r
+\r
+\r
+/** @brief Macro to get the HSI divider.\r
+ * @retval The HSI divider. The returned value can be one\r
+ * of the following:\r
+ * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset)\r
+ * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2\r
+ * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4\r
+ * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8\r
+ */\r
+#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))\r
+\r
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after start-up\r
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
+ * of the HSE used directly or indirectly as system clock (if the Clock\r
+ * Security System CSS is enabled).\r
+ * @note HSI can not be stopped if it is used as system clock source. In this case,\r
+ * you have to select another source of the system clock then stop the HSI.\r
+ * @note After enabling the HSI, the application software should wait on HSIRDY\r
+ * flag to be set indicating that HSI clock is stable and can be used as\r
+ * system clock source.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles.\r
+ */\r
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)\r
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)\r
+\r
+\r
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * @param __HSICalibrationValue__: specifies the calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x7F (3F for Rev Y device).\r
+ */\r
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \\r
+ do { \\r
+ if(HAL_GetREVID() <= REV_ID_Y) \\r
+ { \\r
+ MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);\\r
+ } \\r
+ else \\r
+ { \\r
+ MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \\r
+ } \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)\r
+ * in STOP mode to be quickly available as kernel clock for some peripherals.\r
+ * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication\r
+ * speed because of the HSI start-up time.\r
+ * @note The enable of this function has not effect on the HSION bit.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)\r
+#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)\r
+\r
+\r
+/**\r
+ * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).\r
+ * @note After enabling the HSI48, the application software should wait on\r
+ * HSI48RDY flag to be set indicating that HSI48 clock is stable and can\r
+ * be used to clock the USB.\r
+ * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);\r
+\r
+#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);\r
+\r
+/**\r
+ * @brief Macros to enable or disable the Internal oscillator (CSI).\r
+ * @note The CSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after\r
+ * start-up from Reset, wakeup from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * @note CSI can not be stopped if it is used as system clock source.\r
+ * In this case, you have to select another source of the system\r
+ * clock then stop the CSI.\r
+ * @note After enabling the CSI, the application software should wait on\r
+ * CSIRDY flag to be set indicating that CSI clock is stable and can\r
+ * be used as system clock source.\r
+ * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator\r
+ * clock cycles.\r
+ */\r
+#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)\r
+#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)\r
+\r
+/** @brief Macro Adjusts the Internal oscillator (CSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal CSI RC.\r
+ * @param __CSICalibrationValue__: specifies the calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ */\r
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \\r
+ do { \\r
+ if(HAL_GetREVID() <= REV_ID_Y) \\r
+ { \\r
+ MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \\r
+ } \\r
+ else \\r
+ { \\r
+ MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \\r
+ } \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI)\r
+ * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.\r
+ * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication\r
+ * speed because of the CSI start-up time.\r
+ * @note The enable of this function has not effect on the CSION bit.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)\r
+#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)\r
+\r
+\r
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on\r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles.\r
+ */\r
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)\r
+#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)\r
+\r
+/**\r
+ * @brief Macro to configure the External High Speed oscillator (__HSE__).\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param __STATE__: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator.\r
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \\r
+ do { \\r
+ if ((__STATE__) == RCC_HSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ } while(0)\r
+\r
+/** @defgroup RCC_LSE_Configuration LSE Configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the External Low Speed oscillator (LSE).\r
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.\r
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass.\r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using\r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset).\r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param __STATE__: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.\r
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \\r
+ do { \\r
+ if((__STATE__) == RCC_LSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else if((__STATE__) == RCC_LSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ } \\r
+ else if((__STATE__) == RCC_LSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @brief Macros to enable or disable the the RTC clock.\r
+ * @note These macros must be used only after the RTC clock source was selected.\r
+ */\r
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
+\r
+/** @brief Macros to configure the RTC clock (RTCCLK).\r
+ * @note As the RTC clock configuration bits are in the Backup domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using the Power Backup Access macro before to configure\r
+ * the RTC clock source (to be done once after reset).\r
+ * @note Once the RTC clock is configured it can't be changed unless the\r
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by\r
+ * a Power On Reset (POR).\r
+ * @param __RTCCLKSource__: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.\r
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.\r
+ * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected\r
+ * as RTC clock, where x:[2,31]\r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes.\r
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ */\r
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)\r
+\r
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \\r
+ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \\r
+ } while (0)\r
+\r
+#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))\r
+\r
+\r
+/** @brief Macros to force or release the Backup domain reset.\r
+ * @note This function resets the RTC peripheral (including the backup registers)\r
+ * and the RTC clock source selection in RCC_CSR register.\r
+ * @note The BKPSRAM is not affected by this reset.\r
+ */\r
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
+\r
+/** @brief Macros to enable or disable the main PLL.\r
+ * @note After enabling the main PLL, the application software should wait on\r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * @note The main PLL can not be disabled if it is used as system clock source\r
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)\r
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)\r
+\r
+/**\r
+ * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)\r
+ * @note Enabling/disabling those Clocks can be done only when the PLL is disabled.\r
+ * This is mainly used to save Power.\r
+ * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).\r
+ * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL1_DIVP: This clock is used to generate system clock (up to 400MHZ)\r
+ * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)\r
+ * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))\r
+\r
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))\r
+\r
+\r
+/**\r
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO\r
+ * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)\r
+\r
+#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)\r
+\r
+\r
+/**\r
+ * @brief Macro to configures the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ *\r
+ * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .\r
+ *\r
+ * @param __PLLM1__: specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between 1 and 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 16 MHz.\r
+ *\r
+ * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter must be a number between 4 and 512.\r
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
+ * output frequency is between 150 and 420 MHz (when in medium VCO range) or\r
+ * between 192 and 836 MHZ (when in wide VCO range)\r
+ *\r
+ * @param __PLLP1__: specifies the division factor for system clock.\r
+ * This parameter must be a number between 2 and 128 (where odd numbers not allowed)\r
+ *\r
+ * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 1 and 128\r
+ *\r
+ * @param __PLLR1__: specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 1 and 128\r
+ *\r
+ * @retval None\r
+ */\r
+\r
+\r
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \\r
+ do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \\r
+ WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \\r
+ ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \\r
+ } while(0)\r
+\r
+\r
+/** @brief Macro to configure the PLLs clock source.\r
+ * @note This function must be used only when all PLLs are disabled.\r
+ * @param __PLLSOURCE__: specifies the PLLs entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ *\r
+ */\r
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))\r
+\r
+\r
+/**\r
+ * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor\r
+ *\r
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO\r
+ *\r
+ * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO\r
+ * It should be a value between 0 and 8191\r
+ * @note Warning: The software has to set correctly these bits to insure that the VCO\r
+ * output frequency is between its valid frequency range, which is:\r
+ * 192 to 836 MHz if PLL1VCOSEL = 0\r
+ * 150 to 420 MHz if PLL1VCOSEL = 1.\r
+ *\r
+ *\r
+ * @retval None\r
+ */\r
+ #define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)\r
+\r
+\r
+/** @brief Macro to select the PLL1 reference frequency range.\r
+ * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz\r
+ * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz\r
+ * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz\r
+ * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \\r
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))\r
+\r
+\r
+/** @brief Macro to select the PLL1 reference frequency range.\r
+ * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz\r
+ * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \\r
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))\r
+\r
+\r
+\r
+/** @brief Macro to get the clock source used as system clock.\r
+ * @retval The clock source used as system clock. The returned value can be one\r
+ * of the following:\r
+ * - RCC_CFGR_SWS_CSI: CSI used as system clock.\r
+ * - RCC_CFGR_SWS_HSI: HSI used as system clock.\r
+ * - RCC_CFGR_SWS_HSE: HSE used as system clock.\r
+ * - RCC_CFGR_SWS_PLL: PLL used as system clock.\r
+ */\r
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))\r
+\r
+\r
+/**\r
+ * @brief Macro to configure the system clock source.\r
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.\r
+ * This parameter can be one of the following values:\r
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r
+ */\r
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))\r
+\r
+/** @brief Macro to get the oscillator used as PLL clock source.\r
+ * @retval The oscillator used as PLL clock source. The returned value can be one\r
+ * of the following:\r
+ * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.\r
+ * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.\r
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r
+ */\r
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))\r
+\r
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\r
+ * @{\r
+ */\r
+\r
+/** @brief Macro to configure the MCO1 clock.\r
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source\r
+ * @param __MCODIV__ specifies the MCO clock prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock\r
+ */\r
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r
+\r
+/** @brief Macro to configure the MCO2 clock.\r
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source\r
+ * @param __MCODIV__ specifies the MCO clock prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock\r
+ */\r
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.\r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using\r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset).\r
+ * @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.\r
+ * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.\r
+ * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \\r
+ do{ \\r
+ if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \\r
+ { \\r
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \\r
+ } \\r
+ else \\r
+ { \\r
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @brief Macro to configure the wake up from stop clock.\r
+ * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source\r
+ * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))\r
+\r
+/**\r
+ * @brief Macro to configure the Kernel wake up from stop clock.\r
+ * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source\r
+ * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))\r
+\r
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
+ * @brief macros to manage the specified RCC Flags and interrupts.\r
+ * @{\r
+ */\r
+/** @brief Enable RCC interrupt.\r
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_CSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt\r
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
+ * @arg RCC_IT_LSECSS: Clock security system interrupt\r
+ */\r
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))\r
+\r
+/** @brief Disable RCC interrupt\r
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_CSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt\r
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
+ * @arg RCC_IT_LSECSS: Clock security system interrupt\r
+ */\r
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))\r
+\r
+/** @brief Clear the RCC's interrupt pending bits\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_CSIRDY: CSI ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt\r
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
+ * @arg RCC_IT_HSECSS: HSE Clock Security interrupt\r
+ * @arg RCC_IT_LSECSS: Clock security system interrupt\r
+ */\r
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))\r
+\r
+/** @brief Check the RCC's interrupt has occurred or not.\r
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_CSIRDY: CSI ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt\r
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
+ * @arg RCC_IT_HSECSS: HSE Clock Security interrupt\r
+ * @arg RCC_IT_LSECSS: Clock security system interrupt\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/** @brief Set RMVF bit to clear the reset flags.\r
+ */\r
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)\r
+\r
+#if defined(DUAL_CORE)\r
+#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)\r
+\r
+#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+/** @brief Check RCC flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSIDIV: HSI divider flag\r
+ * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready\r
+ * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL1 clock ready\r
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready\r
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_C1RST: CPU reset flag\r
+ * @arg RCC_FLAG_C2RST: CPU2 reset flag\r
+ * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag\r
+ * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag\r
+ * @arg RCC_FLAG_BORRST: BOR reset flag\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag\r
+ * @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag\r
+ * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag\r
+ * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset\r
+ * @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset\r
+ * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset\r
+ * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag\r
+ * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define RCC_FLAG_MASK ((uint8_t)0x1F)\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \\r
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)\r
+\r
+#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \\r
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)\r
+\r
+#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \\r
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)\r
+\r
+#else\r
+\r
+/** @brief Check RCC flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSIDIV: HSI divider flag\r
+ * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready\r
+ * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL1 clock ready\r
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready\r
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_CPURST: CPU reset flag\r
+ * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag\r
+ * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag\r
+ * @arg RCC_FLAG_BORRST: BOR reset flag\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag\r
+ * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag\r
+ * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset\r
+ * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag\r
+ * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define RCC_FLAG_MASK ((uint8_t)0x1F)\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \\r
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include RCC HAL Extension module */\r
+#include "stm32h7xx_hal_rcc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+ /** @addtogroup RCC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void);\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
+void HAL_RCC_EnableCSS(void);\r
+void HAL_RCC_DisableCSS(void);\r
+uint32_t HAL_RCC_GetSysClockFreq(void);\r
+uint32_t HAL_RCC_GetHCLKFreq(void);\r
+uint32_t HAL_RCC_GetPCLK1Freq(void);\r
+uint32_t HAL_RCC_GetPCLK2Freq(void);\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
+/* CSS NMI IRQ handler */\r
+void HAL_RCC_NMI_IRQHandler(void);\r
+/* User Callbacks in non blocking mode (IT mode) */\r
+void HAL_RCC_CCSCallback(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Constants RCC Private Constants\r
+ * @{\r
+ */\r
+\r
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT\r
+#define HSI_TIMEOUT_VALUE (2U) /* 2 ms */\r
+#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */\r
+#define CSI_TIMEOUT_VALUE (2U) /* 2 ms */\r
+#define LSI_TIMEOUT_VALUE (2U) /* 2 ms */\r
+#define PLL_TIMEOUT_VALUE (2U) /* 2 ms */\r
+#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */\r
+#define RCC_DBP_TIMEOUT_VALUE (100U)\r
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */\r
+\r
+#define HAL_RCC_REV_Y_HSITRIM_Pos (12U)\r
+#define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U)\r
+#define HAL_RCC_REV_Y_CSITRIM_Pos (26U)\r
+#define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U)\r
+\r
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \\r
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \\r
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \\r
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \\r
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \\r
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \\r
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))\r
+\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_BYPASS))\r
+\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_BYPASS))\r
+\r
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \\r
+ ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \\r
+ ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))\r
+\r
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))\r
+\r
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))\r
+\r
+#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))\r
+\r
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \\r
+ ((PLL) == RCC_PLL_ON))\r
+\r
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_PLLSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_PLLSOURCE_NONE) || \\r
+ ((SOURCE) == RCC_PLLSOURCE_HSE))\r
+#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))\r
+#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))\r
+#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+\r
+#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \\r
+ ((VALUE) == RCC_PLL1_DIVQ) || \\r
+ ((VALUE) == RCC_PLL1_DIVR))\r
+\r
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))\r
+\r
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))\r
+\r
+#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \\r
+ ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \\r
+ ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \\r
+ ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \\r
+ ((SYSCLK) == RCC_SYSCLK_DIV512))\r
+\r
+\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \\r
+ ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \\r
+ ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \\r
+ ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \\r
+ ((HCLK) == RCC_HCLK_DIV512))\r
+\r
+#define IS_RCC_D1PCLK1(D1PCLK1) (((D1PCLK1) == RCC_APB3_DIV1) || ((D1PCLK1) == RCC_APB3_DIV2) || \\r
+ ((D1PCLK1) == RCC_APB3_DIV4) || ((D1PCLK1) == RCC_APB3_DIV8) || \\r
+ ((D1PCLK1) == RCC_APB3_DIV16))\r
+\r
+#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \\r
+ ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \\r
+ ((PCLK1) == RCC_APB1_DIV16))\r
+\r
+#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \\r
+ ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \\r
+ ((PCLK2) == RCC_APB2_DIV16))\r
+\r
+#define IS_RCC_D3PCLK1(D3PCLK1) (((D3PCLK1) == RCC_APB4_DIV1) || ((D3PCLK1) == RCC_APB4_DIV2) || \\r
+ ((D3PCLK1) == RCC_APB4_DIV4) || ((D3PCLK1) == RCC_APB4_DIV8) || \\r
+ ((D3PCLK1) == RCC_APB4_DIV16))\r
+\r
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))\r
+\r
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))\r
+\r
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \\r
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \\r
+ ((SOURCE) == RCC_MCO1SOURCE_HSI48))\r
+\r
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \\r
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \\r
+ ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))\r
+\r
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \\r
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \\r
+ ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \\r
+ ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \\r
+ ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \\r
+ ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \\r
+ ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \\r
+ ((DIV) == RCC_MCODIV_15))\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \\r
+ ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \\r
+ ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \\r
+ ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \\r
+ ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \\r
+ ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV))\r
+\r
+#else\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \\r
+ ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \\r
+ ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \\r
+ ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)\r
+#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)\r
+\r
+#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \\r
+ ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))\r
+\r
+#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \\r
+ ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_RCC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_rcc_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of RCC HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_RCC_EX_H\r
+#define STM32H7xx_HAL_RCC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCCEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief PLL2 Clock structure definition\r
+ */\r
+typedef struct\r
+{\r
+\r
+ uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 63 */\r
+\r
+ uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.\r
+ This parameter must be a number between Min_Data = 4 and Max_Data = 512 */\r
+\r
+ uint32_t PLL2P; /*!< PLL2P: Division factor for system clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 128\r
+ odd division factors are not allowed */\r
+\r
+ uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r
+\r
+ uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r
+ uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range\r
+ This parameter must be a value of @ref RCC_PLL2_VCI_Range */\r
+ uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range\r
+ This parameter must be a value of @ref RCC_PLL2_VCO_Range */\r
+\r
+ uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for\r
+ PLL2 VCO It should be a value between 0 and 8191 */\r
+}RCC_PLL2InitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief PLL3 Clock structure definition\r
+ */\r
+typedef struct\r
+{\r
+\r
+ uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 63 */\r
+\r
+ uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.\r
+ This parameter must be a number between Min_Data = 4 and Max_Data = 512 */\r
+\r
+ uint32_t PLL3P; /*!< PLL3P: Division factor for system clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 128\r
+ odd division factors are not allowed */\r
+\r
+ uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r
+\r
+ uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r
+ uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range\r
+ This parameter must be a value of @ref RCC_PLL3_VCI_Range */\r
+ uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range\r
+ This parameter must be a value of @ref RCC_PLL3_VCO_Range */\r
+\r
+ uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for\r
+ PLL3 VCO It should be a value between 0 and 8191 */\r
+}RCC_PLL3InitTypeDef;\r
+\r
+/**\r
+ * @brief RCC PLL1 Clocks structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLL1_P_Frequency;\r
+ uint32_t PLL1_Q_Frequency;\r
+ uint32_t PLL1_R_Frequency;\r
+}PLL1_ClocksTypeDef;\r
+\r
+/**\r
+ * @brief RCC PLL2 Clocks structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLL2_P_Frequency;\r
+ uint32_t PLL2_Q_Frequency;\r
+ uint32_t PLL2_R_Frequency;\r
+}PLL2_ClocksTypeDef;\r
+\r
+/**\r
+ * @brief RCC PLL3 Clocks structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLL3_P_Frequency;\r
+ uint32_t PLL3_Q_Frequency;\r
+ uint32_t PLL3_R_Frequency;\r
+}PLL3_ClocksTypeDef;\r
+\r
+\r
+/**\r
+ * @brief RCC extended clocks structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
+\r
+ RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters.\r
+ This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */\r
+\r
+ RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters.\r
+ This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */\r
+\r
+ uint32_t FmcClockSelection; /*!< Specifies FMC clock source\r
+ This parameter can be a value of @ref RCCEx_FMC_Clock_Source */\r
+\r
+ uint32_t QspiClockSelection; /*!< Specifies QSPI clock source\r
+ This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */\r
+#if defined(DSI)\r
+ uint32_t DsiClockSelection; /*!< Specifies DSI clock source\r
+ This parameter can be a value of @ref RCCEx_DSI_Clock_Source */\r
+#endif /*DSI*/\r
+\r
+ uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source\r
+ This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */\r
+\r
+ uint32_t CkperClockSelection; /*!< Specifies CKPER clock source\r
+ This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */\r
+\r
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source\r
+ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r
+\r
+ uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source\r
+ This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */\r
+\r
+ uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source\r
+ This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */\r
+\r
+ uint32_t Spi45ClockSelection; /*!< Specifies SPI4/5 clock source\r
+ This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */\r
+\r
+ uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source\r
+ This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */\r
+\r
+ uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source\r
+ This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */\r
+#if defined(FDCAN1) || defined(FDCAN2)\r
+ uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source\r
+ This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */\r
+#endif /*FDCAN1 || FDCAN2*/\r
+\r
+ uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 Clock clock source\r
+ This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */\r
+\r
+ uint32_t Usart234578ClockSelection; /*!< Specifies USART2/3/4/5/7/8 clock source\r
+ This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */\r
+\r
+ uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source\r
+ This parameter can be a value of @ref RCCEx_USART16_Clock_Source */\r
+\r
+ uint32_t RngClockSelection; /*!< Specifies RNG clock source\r
+ This parameter can be a value of @ref RCCEx_RNG_Clock_Source */\r
+\r
+ uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source\r
+ This parameter can be a value of @ref RCCEx_I2C123_Clock_Source */\r
+\r
+ uint32_t UsbClockSelection; /*!< Specifies USB clock source\r
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */\r
+\r
+ uint32_t CecClockSelection; /*!< Specifies CEC clock source\r
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */\r
+\r
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source\r
+ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r
+\r
+ uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source\r
+ This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */\r
+\r
+ uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source\r
+ This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r
+\r
+ uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source\r
+ This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */\r
+\r
+ uint32_t Lptim345ClockSelection; /*!< Specifies LPTIM3/4/5 clock source\r
+ This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source */\r
+\r
+ uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source\r
+ This parameter can be a value of @ref RCCEx_ADC_Clock_Source */\r
+\r
+ uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source\r
+ This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */\r
+\r
+ uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source\r
+ This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */\r
+\r
+ uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source\r
+ This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */\r
+\r
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source\r
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */\r
+\r
+ uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source\r
+ This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */\r
+ uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.\r
+ This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */\r
+}RCC_PeriphCLKInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief RCC_CRS Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.\r
+ This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */\r
+\r
+ uint32_t Source; /*!< Specifies the SYNC signal source.\r
+ This parameter can be a value of @ref RCCEx_CRS_SynchroSource */\r
+\r
+ uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.\r
+ This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */\r
+\r
+ uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.\r
+ It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)\r
+ This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/\r
+\r
+ uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.\r
+ This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */\r
+\r
+ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.\r
+ This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */\r
+\r
+}RCC_CRSInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC_CRS Synchronization structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.\r
+ This parameter must be a number between 0 and 0xFFFF */\r
+\r
+ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.\r
+ This parameter must be a number between 0 and 0x3F */\r
+\r
+ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter\r
+ value latched in the time of the last SYNC event.\r
+ This parameter must be a number between 0 and 0xFFFF */\r
+\r
+ uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the\r
+ frequency error counter latched in the time of the last SYNC event.\r
+ It shows whether the actual frequency is below or above the target.\r
+ This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/\r
+\r
+}RCC_CRSSynchroInfoTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection\r
+ * @{\r
+ */\r
+\r
+#define RCC_PERIPHCLK_USART16 (0x00000001U)\r
+#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16\r
+#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16\r
+#define RCC_PERIPHCLK_USART234578 (0x00000002U)\r
+#define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578\r
+#define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578\r
+#define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578\r
+#define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578\r
+#define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578\r
+#define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578\r
+#define RCC_PERIPHCLK_LPUART1 (0x00000004U)\r
+#define RCC_PERIPHCLK_I2C123 (0x00000008U)\r
+#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123\r
+#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123\r
+#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123\r
+#define RCC_PERIPHCLK_I2C4 (0x00000010U)\r
+#define RCC_PERIPHCLK_LPTIM1 (0x00000020U)\r
+#define RCC_PERIPHCLK_LPTIM2 (0x00000040U)\r
+#define RCC_PERIPHCLK_LPTIM345 (0x00000080U)\r
+#define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345\r
+#define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345\r
+#define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345\r
+#define RCC_PERIPHCLK_SAI1 (0x00000100U)\r
+#define RCC_PERIPHCLK_SAI23 (0x00000200U)\r
+#define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23\r
+#define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23\r
+#define RCC_PERIPHCLK_SAI4A (0x00000400U)\r
+#define RCC_PERIPHCLK_SAI4B (0x00000800U)\r
+#define RCC_PERIPHCLK_SPI123 (0x00001000U)\r
+#define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123\r
+#define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123\r
+#define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123\r
+#define RCC_PERIPHCLK_SPI45 (0x00002000U)\r
+#define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45\r
+#define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45\r
+#define RCC_PERIPHCLK_SPI6 (0x00004000U)\r
+#define RCC_PERIPHCLK_FDCAN (0x00008000U)\r
+#define RCC_PERIPHCLK_SDMMC (0x00010000U)\r
+#define RCC_PERIPHCLK_RNG (0x00020000U)\r
+#define RCC_PERIPHCLK_USB (0x00040000U)\r
+#define RCC_PERIPHCLK_ADC (0x00080000U)\r
+#define RCC_PERIPHCLK_SWPMI1 (0x00100000U)\r
+#define RCC_PERIPHCLK_DFSDM1 (0x00200000U)\r
+#define RCC_PERIPHCLK_RTC (0x00400000U)\r
+#define RCC_PERIPHCLK_CEC (0x00800000U)\r
+#define RCC_PERIPHCLK_FMC (0x01000000U)\r
+#define RCC_PERIPHCLK_QSPI (0x02000000U)\r
+#define RCC_PERIPHCLK_DSI (0x04000000U)\r
+#define RCC_PERIPHCLK_SPDIFRX (0x08000000U)\r
+#define RCC_PERIPHCLK_HRTIM1 (0x10000000U)\r
+\r
+#if defined(LTDC)\r
+#define RCC_PERIPHCLK_LTDC (0x20000000U)\r
+#endif /* LTDC */\r
+\r
+#define RCC_PERIPHCLK_TIM (0x40000000U)\r
+#define RCC_PERIPHCLK_CKPER (0x80000000U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output\r
+ * @{\r
+ */\r
+#define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN\r
+#define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN\r
+#define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output\r
+ * @{\r
+ */\r
+#define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN\r
+#define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN\r
+#define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range\r
+ * @{\r
+ */\r
+#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0\r
+#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1\r
+#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2\r
+#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range\r
+ * @{\r
+ */\r
+#define RCC_PLL2VCOWIDE (0x00000000U)\r
+#define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range\r
+ * @{\r
+ */\r
+#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0\r
+#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1\r
+#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2\r
+#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range\r
+ * @{\r
+ */\r
+#define RCC_PLL3VCOWIDE (0x00000000U)\r
+#define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U)\r
+#define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0\r
+#define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1\r
+#define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)\r
+#define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2\r
+#define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2\r
+#define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2\r
+#define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3\r
+#define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI\r
+#define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI\r
+#define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2\r
+#define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2\r
+#define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3\r
+#define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI\r
+#define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI\r
+#define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U)\r
+#define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0\r
+#define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1\r
+#define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)\r
+#define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2\r
+#define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1\r
+#define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2\r
+#define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3\r
+#define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI\r
+#define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI\r
+#define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1\r
+#define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2\r
+#define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3\r
+#define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI\r
+#define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI\r
+#define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1\r
+#define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2\r
+#define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3\r
+#define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI\r
+#define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI\r
+#define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1\r
+#define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2\r
+#define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3\r
+#define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI\r
+#define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI\r
+#define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1\r
+#define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2\r
+#define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3\r
+#define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI\r
+#define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI\r
+#define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1\r
+#define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2\r
+#define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3\r
+#define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI\r
+#define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI\r
+#define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U)\r
+#define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0\r
+#define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1\r
+#define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)\r
+#define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2\r
+#define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C123_Clock_Source RCCEx I2C1/2/3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U)\r
+#define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0\r
+#define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1\r
+#define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1\r
+#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3\r
+#define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI\r
+#define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1\r
+#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3\r
+#define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI\r
+#define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1\r
+#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3\r
+#define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI\r
+#define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U)\r
+#define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0\r
+#define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1\r
+#define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source\r
+ * @{\r
+ */\r
+#define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)\r
+#define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0\r
+#define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1\r
+#define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_HRTIM1CLK_TIMCLK (0x00000000U)\r
+#define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0\r
+#define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1\r
+#define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI1CLKSOURCE_PLL (0x00000000U)\r
+#define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0\r
+#define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1\r
+#define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)\r
+#define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI23CLKSOURCE_PLL (0x00000000U)\r
+#define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0\r
+#define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1\r
+#define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)\r
+#define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL\r
+#define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2\r
+#define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3\r
+#define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN\r
+#define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL\r
+#define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2\r
+#define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3\r
+#define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN\r
+#define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI123CLKSOURCE_PLL (0x00000000U)\r
+#define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0\r
+#define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1\r
+#define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)\r
+#define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL\r
+#define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2\r
+#define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3\r
+#define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN\r
+#define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL\r
+#define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2\r
+#define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3\r
+#define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN\r
+#define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL\r
+#define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2\r
+#define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3\r
+#define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN\r
+#define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U)\r
+#define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0\r
+#define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1\r
+#define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)\r
+#define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2\r
+#define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1\r
+#define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2\r
+#define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3\r
+#define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI\r
+#define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI\r
+#define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1\r
+#define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2\r
+#define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3\r
+#define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI\r
+#define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI\r
+#define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U)\r
+#define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0\r
+#define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1\r
+#define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)\r
+#define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2\r
+#define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI4ACLKSOURCE_PLL (0x00000000U)\r
+#define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0\r
+#define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1\r
+#define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)\r
+#define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI4BCLKSOURCE_PLL (0x00000000U)\r
+#define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0\r
+#define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1\r
+#define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)\r
+#define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U)\r
+#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0\r
+#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1\r
+#define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)\r
+#define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2\r
+#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U)\r
+#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0\r
+#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1\r
+#define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)\r
+#define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2\r
+#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U)\r
+#define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0\r
+#define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1\r
+#define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)\r
+#define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2\r
+#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPTIM3_Clock_Source RCCEx LPTIM3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1\r
+#define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2\r
+#define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3\r
+#define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE\r
+#define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI\r
+#define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1\r
+#define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2\r
+#define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3\r
+#define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE\r
+#define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI\r
+#define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1\r
+#define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2\r
+#define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3\r
+#define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE\r
+#define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI\r
+#define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source\r
+ * @{\r
+ */\r
+#define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U)\r
+#define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0\r
+#define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1\r
+#define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+#if defined(DSI)\r
+/** @defgroup RCCEx_DSI_Clock_Source RCCEx DSI Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DSICLKSOURCE_PHY (0x00000000U)\r
+#define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /*DSI*/\r
+\r
+/** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U)\r
+#define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0\r
+#define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1\r
+#define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(FDCAN1) || defined(FDCAN2)\r
+/** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_FDCANCLKSOURCE_HSE (0x00000000U)\r
+#define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0\r
+#define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /*FDCAN1 || FDCAN2*/\r
+\r
+\r
+/** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)\r
+#define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)\r
+#define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0\r
+#define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+/** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U)\r
+#define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U)\r
+#define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)\r
+#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0\r
+#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1\r
+#define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CECCLKSOURCE_LSE (0x00000000U)\r
+#define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0\r
+#define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CLKPSOURCE_HSI (0x00000000U)\r
+#define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0\r
+#define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection\r
+ * @{\r
+ */\r
+#define RCC_TIMPRES_DESACTIVATED (0x00000000U)\r
+#define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(DUAL_CORE)\r
+\r
+/** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx\r
+ * @{\r
+ */\r
+#define RCC_BOOT_C1 RCC_GCR_BOOT_C1\r
+#define RCC_BOOT_C2 RCC_GCR_BOOT_C2\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+/** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx\r
+ * @{\r
+ */\r
+#define RCC_WWDG1 RCC_GCR_WW1RSC\r
+#define RCC_WWDG2 RCC_GCR_WW2RSC\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#else\r
+\r
+/** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx\r
+ * @{\r
+ */\r
+#define RCC_WWDG1 RCC_GCR_WW1RSC\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status\r
+ * @{\r
+ */\r
+#define RCC_CRS_NONE (0x00000000U)\r
+#define RCC_CRS_TIMEOUT (0x00000001U)\r
+#define RCC_CRS_SYNCOK (0x00000002U)\r
+#define RCC_CRS_SYNCWARN (0x00000004U)\r
+#define RCC_CRS_SYNCERR (0x00000008U)\r
+#define RCC_CRS_SYNCMISS (0x00000010U)\r
+#define RCC_CRS_TRIMOVF (0x00000020U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource\r
+ * @{\r
+ */\r
+#define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and abobe devices only */\r
+#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */\r
+#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */\r
+#define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB2 SOF */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider\r
+ * @{\r
+ */\r
+#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */\r
+#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */\r
+#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */\r
+#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */\r
+#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */\r
+#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */\r
+#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */\r
+#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity\r
+ * @{\r
+ */\r
+#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */\r
+#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault\r
+ * @{\r
+ */\r
+#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds\r
+ to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault\r
+ * @{\r
+ */\r
+#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault\r
+ * @{\r
+ */\r
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.\r
+ The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value\r
+ corresponds to a higher output frequency */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection\r
+ * @{\r
+ */\r
+#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */\r
+#define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources\r
+ * @{\r
+ */\r
+#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */\r
+#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */\r
+#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */\r
+#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */\r
+#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */\r
+#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */\r
+#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags\r
+ * @{\r
+ */\r
+#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */\r
+#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */\r
+#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */\r
+#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */\r
+#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */\r
+#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/\r
+#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Macros to enable or disable PLL2.\r
+ * @note After enabling PLL2, the application software should wait on\r
+ * PLL2RDY flag to be set indicating that PLL2 clock is stable and can\r
+ * be used as kernel clock source.\r
+ * @note PLL2 is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)\r
+#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)\r
+\r
+/**\r
+ * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)\r
+ * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled,\r
+ * This is mainly used to save Power.\r
+ * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ)\r
+ * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)\r
+ * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))\r
+\r
+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))\r
+\r
+/**\r
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO\r
+ * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)\r
+\r
+#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)\r
+\r
+/**\r
+ * @brief Macro to configures the PLL2 multiplication and division factors.\r
+ * @note This function must be used only when PLL2 is disabled.\r
+ *\r
+ * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock\r
+ * This parameter must be a number between 1 and 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 16 MHz.\r
+ *\r
+ * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock\r
+ * This parameter must be a number between 4 and 512.\r
+ * @note You have to set the PLL2N parameter correctly to ensure that the VCO\r
+ * output frequency is between 150 and 420 MHz (when in medium VCO range) or\r
+ * between 192 and 836 MHZ (when in wide VCO range)\r
+ *\r
+ * @param __PLL2P__ specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 2 and 128 (where odd numbers not allowed)\r
+ *\r
+ * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 1 and 128\r
+ *\r
+ * @param __PLL2R__ specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 1 and 128\r
+ *\r
+ * @retval None\r
+ */\r
+\r
+\r
+#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \\r
+ do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \\r
+ WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \\r
+ ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \\r
+ } while(0)\r
+/**\r
+ * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor\r
+ *\r
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO\r
+ *\r
+ * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO\r
+ * It should be a value between 0 and 8191\r
+ * @note Warning: the software has to set correctly these bits to insure that the VCO\r
+ * output frequency is between its valid frequency range, which is:\r
+ * 192 to 836 MHz if PLL2VCOSEL = 0\r
+ * 150 to 420 MHz if PLL2VCOSEL = 1.\r
+ *\r
+ *\r
+ * @retval None\r
+ */\r
+ #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)\r
+\r
+/** @brief Macro to select the PLL2 reference frequency range.\r
+ * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz\r
+ * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz\r
+ * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz\r
+ * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \\r
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))\r
+\r
+\r
+/** @brief Macro to select the PLL2 reference frequency range.\r
+ * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz\r
+ * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \\r
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))\r
+\r
+/** @brief Macros to enable or disable the main PLL3.\r
+ * @note After enabling PLL3, the application software should wait on\r
+ * PLL3RDY flag to be set indicating that PLL3 clock is stable and can\r
+ * be used as kernel clock source.\r
+ * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)\r
+#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)\r
+\r
+/**\r
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO\r
+ * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)\r
+\r
+#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)\r
+\r
+/**\r
+ * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)\r
+ * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled,\r
+ * This is mainly used to save Power.\r
+ * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ)\r
+ * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)\r
+ * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))\r
+\r
+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))\r
+\r
+/**\r
+ * @brief Macro to configures the PLL3 multiplication and division factors.\r
+ * @note This function must be used only when PLL3 is disabled.\r
+ *\r
+ * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock\r
+ * This parameter must be a number between 1 and 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 16 MHz.\r
+ *\r
+ * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock\r
+ * This parameter must be a number between 4 and 512.\r
+ * @note You have to set the PLL3N parameter correctly to ensure that the VCO\r
+ * output frequency is between 150 and 420 MHz (when in medium VCO range) or\r
+ * between 192 and 836 MHZ (when in wide VCO range)\r
+ *\r
+ * @param __PLL3P__ specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 2 and 128 (where odd numbers not allowed)\r
+ *\r
+ * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 1 and 128\r
+ *\r
+ * @param __PLL3R__ specifies the division factor for peripheral kernel clocks\r
+ * This parameter must be a number between 1 and 128\r
+ *\r
+ * @retval None\r
+ */\r
+\r
+#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \\r
+ do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \\r
+ WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \\r
+ ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \\r
+ } while(0)\r
+\r
+\r
+\r
+/**\r
+ * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor\r
+ *\r
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO\r
+ *\r
+ * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO\r
+ * It should be a value between 0 and 8191\r
+ * @note Warning: the software has to set correctly these bits to insure that the VCO\r
+ * output frequency is between its valid frequency range, which is:\r
+ * 192 to 836 MHz if PLL3VCOSEL = 0\r
+ * 150 to 420 MHz if PLL3VCOSEL = 1.\r
+ *\r
+ *\r
+ * @retval None\r
+ */\r
+ #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)\r
+\r
+/** @brief Macro to select the PLL3 reference frequency range.\r
+ * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz\r
+ * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz\r
+ * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz\r
+ * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \\r
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))\r
+\r
+\r
+/** @brief Macro to select the PLL3 reference frequency range.\r
+ * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz\r
+ * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \\r
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))\r
+/**\r
+ * @brief Macro to Configure the SAI1 clock source.\r
+ * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL\r
+ * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2\r
+ * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3\r
+ * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))\r
+\r
+/** @brief Macro to get the SAI1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL\r
+ * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2\r
+ * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3\r
+ * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPDIFRX clock source.\r
+ * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, or internal OSC clock\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL\r
+ * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2\r
+ * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3\r
+ * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))\r
+/**\r
+ * @brief Macro to get the SPDIFRX clock source.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SAI2/3 clock source.\r
+ * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL\r
+ * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2\r
+ * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3\r
+ * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP\r
+ * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))\r
+\r
+/** @brief Macro to get the SAI2/3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL\r
+ * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2\r
+ * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3\r
+ * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP\r
+ * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SAI2 clock source.\r
+ * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL\r
+ * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2\r
+ * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3\r
+ * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP\r
+ * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))\r
+\r
+/** @brief Macro to get the SAI2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL\r
+ * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2\r
+ * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3\r
+ * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP\r
+ * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SAI3 clock source.\r
+ * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL\r
+ * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2\r
+ * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3\r
+ * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP\r
+ * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))\r
+\r
+/** @brief Macro to get the SAI3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL\r
+ * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2\r
+ * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3\r
+ * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP\r
+ * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SAI4A clock source.\r
+ * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL\r
+ * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2\r
+ * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3\r
+ * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP\r
+ * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))\r
+\r
+/** @brief Macro to get the SAI4A clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL\r
+ * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2\r
+ * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3\r
+ * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP\r
+ * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SAI4B clock source.\r
+ * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL\r
+ * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2\r
+ * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3\r
+ * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP\r
+ * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))\r
+\r
+/** @brief Macro to get the SAI4B clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL\r
+ * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2\r
+ * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3\r
+ * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP\r
+ * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))\r
+\r
+/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).\r
+ *\r
+ * @param __I2C123CLKSource__ specifies the I2C1/2/3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock\r
+ * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock\r
+ * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock\r
+ * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock\r
+ */\r
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))\r
+\r
+/** @brief macro to get the I2C1/2/3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock\r
+ * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock\r
+ * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock\r
+ * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))\r
+\r
+/** @brief macro to configure the I2C1 clock (I2C1CLK).\r
+ *\r
+ * @param __I2C1CLKSource__ specifies the I2C1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))\r
+\r
+/** @brief macro to get the I2C1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+* @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))\r
+\r
+/** @brief macro to configure the I2C2 clock (I2C2CLK).\r
+ *\r
+ * @param __I2C2CLKSource__ specifies the I2C2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))\r
+\r
+/** @brief macro to get the I2C2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))\r
+\r
+/** @brief macro to configure the I2C3 clock (I2C3CLK).\r
+ *\r
+ * @param __I2C3CLKSource__ specifies the I2C3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))\r
+\r
+/** @brief macro to get the I2C3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))\r
+\r
+/** @brief macro to configure the I2C4 clock (I2C4CLK).\r
+ *\r
+ * @param __I2C4CLKSource__ specifies the I2C4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))\r
+\r
+/** @brief macro to get the I2C4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))\r
+\r
+/** @brief macro to configure the USART1/6 clock (USART16CLK).\r
+ *\r
+ * @param __USART16CLKSource__ specifies the USART1/6 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock\r
+ */\r
+#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))\r
+\r
+/** @brief macro to get the USART1/6 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock\r
+ * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock\r
+ */\r
+#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))\r
+\r
+/** @brief macro to configure the USART234578 clock (USART234578CLK).\r
+ *\r
+ * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock\r
+ */\r
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))\r
+\r
+/** @brief macro to get the USART2/3/4/5/7/8 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock\r
+ * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock\r
+ */\r
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))\r
+\r
+/** @brief macro to configure the USART1 clock (USART1CLK).\r
+ *\r
+ * @param __USART1CLKSource__ specifies the USART1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))\r
+\r
+/** @brief macro to get the USART1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))\r
+\r
+/** @brief macro to configure the USART2 clock (USART2CLK).\r
+ *\r
+ * @param __USART2CLKSource__ specifies the USART2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))\r
+\r
+/** @brief macro to get the USART2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))\r
+\r
+/** @brief macro to configure the USART3 clock (USART3CLK).\r
+ *\r
+ * @param __USART3CLKSource__ specifies the USART3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))\r
+\r
+/** @brief macro to get the USART3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))\r
+\r
+/** @brief macro to configure the UART4 clock (UART4CLK).\r
+ *\r
+ * @param __UART4CLKSource__ specifies the UART4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))\r
+\r
+/** @brief macro to get the UART4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))\r
+\r
+/** @brief macro to configure the UART5 clock (UART5CLK).\r
+ *\r
+ * @param __UART5CLKSource__ specifies the UART5 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))\r
+\r
+/** @brief macro to get the UART5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))\r
+\r
+/** @brief macro to configure the USART6 clock (USART6CLK).\r
+ *\r
+ * @param __USART6CLKSource__ specifies the USART6 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))\r
+\r
+/** @brief macro to get the USART6 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))\r
+\r
+/** @brief macro to configure the UART5 clock (UART7CLK).\r
+ *\r
+ * @param __UART7CLKSource__ specifies the UART7 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))\r
+\r
+/** @brief macro to get the UART7 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))\r
+\r
+/** @brief macro to configure the UART8 clock (UART8CLK).\r
+ *\r
+ * @param __UART8CLKSource__ specifies the UART8 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))\r
+\r
+/** @brief macro to get the UART8 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))\r
+\r
+/** @brief macro to configure the LPUART1 clock (LPUART1CLK).\r
+ *\r
+ * @param __LPUART1CLKSource__ specifies the LPUART1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock\r
+ */\r
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))\r
+\r
+/** @brief macro to get the LPUART1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock\r
+ * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock\r
+ */\r
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))\r
+\r
+/** @brief macro to configure the LPTIM1 clock source.\r
+ *\r
+ * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))\r
+\r
+\r
+/** @brief macro to get the LPTIM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))\r
+\r
+/** @brief macro to configure the LPTIM2 clock source.\r
+ *\r
+ * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock\r
+ */\r
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))\r
+\r
+\r
+/** @brief macro to get the LPTIM2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock\r
+ * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))\r
+\r
+/** @brief macro to configure the LPTIM3/4/5 clock source.\r
+ *\r
+ * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.\r
+ * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock\r
+ */\r
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))\r
+\r
+\r
+/** @brief macro to get the LPTIM3/4/5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock\r
+ * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))\r
+\r
+/** @brief macro to configure the LPTIM3 clock source.\r
+ *\r
+ * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source.\r
+ * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock\r
+ */\r
+#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))\r
+\r
+\r
+/** @brief macro to get the LPTIM3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock\r
+ * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))\r
+\r
+/** @brief macro to configure the LPTIM4 clock source.\r
+ *\r
+ * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source.\r
+ * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock\r
+ */\r
+#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))\r
+\r
+\r
+/** @brief macro to get the LPTIM4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock\r
+ * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))\r
+\r
+/** @brief macro to configure the LPTIM5 clock source.\r
+ *\r
+ * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source.\r
+ * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock\r
+ */\r
+#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))\r
+\r
+\r
+/** @brief macro to get the LPTIM5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock\r
+ * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))\r
+\r
+/** @brief macro to configure the QSPI clock source.\r
+ *\r
+ * @param __QSPICLKSource__ specifies the QSPI clock source.\r
+ * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock\r
+ * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock\r
+ * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock\r
+ * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock\r
+ */\r
+#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \\r
+ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))\r
+\r
+\r
+/** @brief macro to get the QSPI clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock\r
+ * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock\r
+ * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock\r
+ * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock\r
+ */\r
+#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))\r
+\r
+#if defined(DSI)\r
+/** @brief macro to configure the DSI clock source.\r
+ *\r
+ * @param __DSICLKSource__ specifies the DSI clock source.\r
+ * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock\r
+ * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock\r
+ */\r
+#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \\r
+ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))\r
+\r
+\r
+/** @brief macro to get the DSI clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock\r
+ * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock\r
+ */\r
+#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))\r
+#endif /*DSI*/\r
+\r
+/** @brief macro to configure the FMC clock source.\r
+ *\r
+ * @param __FMCCLKSource__ specifies the FMC clock source.\r
+ * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock\r
+ * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock\r
+ * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock\r
+ * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock\r
+ */\r
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \\r
+ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))\r
+\r
+\r
+/** @brief macro to get the FMC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock\r
+ * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock\r
+ * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock\r
+ * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock\r
+ */\r
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))\r
+\r
+/** @brief Macro to configure the USB clock (USBCLK).\r
+ * @param __USBCLKSource__ specifies the USB clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock\r
+ * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock\r
+ * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock\r
+ */\r
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))\r
+\r
+/** @brief Macro to get the USB clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock\r
+ * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock\r
+ * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock\r
+ */\r
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))\r
+\r
+\r
+/** @brief Macro to configure the ADC clock\r
+ * @param __ADCCLKSource__ specifies the ADC digital interface clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock\r
+ * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock\r
+ * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock\r
+ */\r
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))\r
+\r
+/** @brief Macro to get the ADC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock\r
+ * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock\r
+ * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock\r
+ */\r
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))\r
+\r
+ /** @brief Macro to configure the SWPMI1 clock\r
+ * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock\r
+ * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock\r
+ */\r
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))\r
+\r
+/** @brief Macro to get the SWPMI1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock\r
+ * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock\r
+ */\r
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))\r
+\r
+ /** @brief Macro to configure the DFSDM1 clock\r
+ * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock\r
+ * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock\r
+ */\r
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))\r
+\r
+/** @brief Macro to get the DFSDM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock\r
+ * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock\r
+ */\r
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))\r
+\r
+/** @brief macro to configure the CEC clock (CECCLK).\r
+ *\r
+ * @param __CECCLKSource__ specifies the CEC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock\r
+ */\r
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))\r
+\r
+/** @brief macro to get the CEC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock\r
+ */\r
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))\r
+\r
+\r
+/** @brief Macro to configure the CLKP : Oscillator clock for peripheral\r
+ * @param __CLKPSource__ specifies Oscillator clock for peripheral\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral\r
+ * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral\r
+ * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral\r
+ */\r
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \\r
+ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))\r
+\r
+/** @brief Macro to get the Oscillator clock for peripheral source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral\r
+ * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral\r
+ * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral\r
+ */\r
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))\r
+\r
+#if defined(FDCAN1) || defined(FDCAN2)\r
+/** @brief Macro to configure the FDCAN clock\r
+ * @param __FDCANCLKSource__ specifies clock source for FDCAN\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock\r
+ * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock\r
+ * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock\r
+ */\r
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))\r
+\r
+/** @brief Macro to get the FDCAN clock\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock\r
+ * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock\r
+ * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock\r
+ */\r
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))\r
+#endif /*FDCAN1 || FDCAN2*/\r
+/**\r
+ * @brief Macro to Configure the SPI1/2/3 clock source.\r
+ * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL\r
+ * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2\r
+ * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3\r
+ * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP\r
+ * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))\r
+\r
+/** @brief Macro to get the SPI1/2/3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL\r
+ * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2\r
+ * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3\r
+ * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP\r
+ * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPI1 clock source.\r
+ * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL\r
+ * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2\r
+ * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3\r
+ * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP\r
+ * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))\r
+\r
+/** @brief Macro to get the SPI1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL\r
+ * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2\r
+ * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3\r
+ * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP\r
+ * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPI2 clock source.\r
+ * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL\r
+ * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2\r
+ * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3\r
+ * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP\r
+ * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))\r
+\r
+/** @brief Macro to get the SPI2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL\r
+ * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2\r
+ * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3\r
+ * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP\r
+ * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPI3 clock source.\r
+ * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived\r
+ * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL\r
+ * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2\r
+ * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3\r
+ * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP\r
+ * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))\r
+\r
+/** @brief Macro to get the SPI3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL\r
+ * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2\r
+ * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3\r
+ * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP\r
+ * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock\r
+ */\r
+#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPI4/5 clock source.\r
+ * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived\r
+ * from system PCLK, PLL2, PLL3, OSC\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1\r
+ * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2\r
+ * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3\r
+ * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI\r
+ * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI\r
+ * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))\r
+\r
+/** @brief Macro to get the SPI4/5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1\r
+ * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2\r
+ * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3\r
+ * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI\r
+ * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI\r
+ * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE\r
+*/\r
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPI4 clock source.\r
+ * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived\r
+ * from system PCLK, PLL2, PLL3, OSC\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1\r
+ * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2\r
+ * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3\r
+ * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI\r
+ * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI\r
+ * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))\r
+\r
+/** @brief Macro to get the SPI4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1\r
+ * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2\r
+ * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3\r
+ * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI\r
+ * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI\r
+ * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE\r
+*/\r
+#define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPI5 clock source.\r
+ * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived\r
+ * from system PCLK, PLL2, PLL3, OSC\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1\r
+ * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2\r
+ * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3\r
+ * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI\r
+ * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI\r
+ * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__ )\\r
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))\r
+\r
+/** @brief Macro to get the SPI5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1\r
+ * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2\r
+ * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3\r
+ * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI\r
+ * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI\r
+ * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE\r
+*/\r
+#define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))\r
+\r
+/**\r
+ * @brief Macro to Configure the SPI6 clock source.\r
+ * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived\r
+ * from system PCLK, PLL2, PLL3, OSC\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1\r
+ * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2\r
+ * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3\r
+ * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI\r
+ * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI\r
+ * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\\r
+ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))\r
+\r
+/** @brief Macro to get the SPI6 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1\r
+ * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2\r
+ * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3\r
+ * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI\r
+ * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI\r
+ * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE\r
+*/\r
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))\r
+\r
+/** @brief Macro to configure the SDMMC clock\r
+ * @param __SDMMCCLKSource__ specifies clock source for SDMMC\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock\r
+ * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock\r
+ */\r
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \\r
+ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))\r
+\r
+/** @brief Macro to get the SDMMC clock\r
+ */\r
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))\r
+\r
+/** @brief macro to configure the RNG clock (RNGCLK).\r
+ *\r
+ * @param __RNGCLKSource__ specifies the RNG clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock\r
+ * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock\r
+ * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock\r
+ * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock\r
+ */\r
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \\r
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))\r
+\r
+/** @brief macro to get the RNG clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock\r
+ * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock\r
+ * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock\r
+ * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock\r
+ */\r
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))\r
+\r
+\r
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config\r
+ * @{\r
+ */\r
+/** @brief Macro to configure the HRTIM1 prescaler clock source.\r
+ * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock\r
+ * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock\r
+ */\r
+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))\r
+\r
+/** @brief Macro to get the HRTIM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock\r
+ * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock\r
+ */\r
+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))\r
+\r
+/** @brief Macro to configure the Timers clocks prescalers\r
+ * @param __PRESC__ specifies the Timers clocks prescalers selection\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is\r
+ * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,\r
+ * else it is equal to 2 x Frcc_pclkx_d2 (default after reset)\r
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is\r
+ * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,\r
+ * else it is equal to 4 x Frcc_pclkx_d2\r
+ */\r
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\\r
+ RCC->CFGR |= (__PRESC__); \\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @brief Enable the specified CRS interrupts.\r
+ * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt\r
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt\r
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt\r
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified CRS interrupts.\r
+ * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt\r
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt\r
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt\r
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))\r
+\r
+/** @brief Check whether the CRS interrupt has occurred or not.\r
+ * @param __INTERRUPT__ specifies the CRS interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt\r
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt\r
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt\r
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)\r
+\r
+/** @brief Clear the CRS interrupt pending bits\r
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt\r
+ * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt\r
+ * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt\r
+ * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt\r
+ * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt\r
+ * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt\r
+ * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt\r
+ */\r
+/* CRS IT Error Mask */\r
+#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))\r
+\r
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \\r
+ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \\r
+ { \\r
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \\r
+ } \\r
+ else \\r
+ { \\r
+ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \\r
+ } \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Check whether the specified CRS flag is set or not.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK\r
+ * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning\r
+ * @arg @ref RCC_CRS_FLAG_ERR Error\r
+ * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC\r
+ * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow\r
+ * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error\r
+ * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed\r
+ * @retval The new state of _FLAG_ (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear the CRS specified FLAG.\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK\r
+ * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning\r
+ * @arg @ref RCC_CRS_FLAG_ERR Error\r
+ * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC\r
+ * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow\r
+ * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error\r
+ * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed\r
+ * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR\r
+ * @retval None\r
+ */\r
+\r
+/* CRS Flag Error Mask */\r
+#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))\r
+\r
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \\r
+ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \\r
+ { \\r
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \\r
+ } \\r
+ else \\r
+ { \\r
+ WRITE_REG(CRS->ICR, (__FLAG__)); \\r
+ } \\r
+ } while(0)\r
+\r
+ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Enable the oscillator clock for frequency error counter.\r
+ * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)\r
+\r
+/**\r
+ * @brief Disable the oscillator clock for frequency error counter.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)\r
+\r
+/**\r
+ * @brief Enable the automatic hardware adjustment of TRIM bits.\r
+ * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)\r
+\r
+/**\r
+ * @brief Enable or disable the automatic hardware adjustment of TRIM bits.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)\r
+\r
+/**\r
+ * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies\r
+ * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency\r
+ * of the synchronization source after pre-scaling. It is then decreased by one in order to\r
+ * reach the expected synchronization on the zero value. The formula is the following:\r
+ * RELOAD = (fTARGET / fSYNC) -1\r
+ * @param __FTARGET__ Target frequency (value in Hz)\r
+ * @param __FSYNC__ Synchronization signal frequency (value in Hz)\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);\r
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);\r
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void);\r
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);\r
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);\r
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCCEx_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);\r
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);\r
+void HAL_RCCEx_EnableLSECSS(void);\r
+void HAL_RCCEx_DisableLSECSS(void);\r
+#if defined(DUAL_CORE)\r
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);\r
+#endif /*DUAL_CORE*/\r
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup RCCEx_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);\r
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);\r
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);\r
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);\r
+void HAL_RCCEx_CRS_IRQHandler(void);\r
+void HAL_RCCEx_CRS_SyncOkCallback(void);\r
+void HAL_RCCEx_CRS_SyncWarnCallback(void);\r
+void HAL_RCCEx_CRS_ExpectedSyncCallback(void);\r
+void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */\r
+\r
+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \\r
+ ((VALUE) == RCC_PLL2_DIVQ) || \\r
+ ((VALUE) == RCC_PLL2_DIVR))\r
+\r
+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \\r
+ ((VALUE) == RCC_PLL3_DIVQ) || \\r
+ ((VALUE) == RCC_PLL3_DIVR))\r
+\r
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \\r
+ ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART16CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \\r
+ ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))\r
+\r
+#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))\r
+\r
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))\r
+\r
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))\r
+\r
+#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))\r
+\r
+#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \\r
+ ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \\r
+ ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_RNGCLKSOURCE_LSI))\r
+\r
+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \\r
+ ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))\r
+\r
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \\r
+ ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_USBCLKSOURCE_HSI48))\r
+\r
+#define IS_RCC_SAI1CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SAI23CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SAI2CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SAI3CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SPI123CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SPI1CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SPI2CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SPI3CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SPI45CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \\r
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \\r
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \\r
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))\r
+\r
+#define IS_RCC_SPI4CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \\r
+ ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \\r
+ ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \\r
+ ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))\r
+\r
+#define IS_RCC_SPI5CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \\r
+ ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \\r
+ ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \\r
+ ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))\r
+\r
+#define IS_RCC_SPI6CLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \\r
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \\r
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \\r
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))\r
+\r
+#define IS_RCC_SAI4ACLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SAI4BCLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \\r
+ ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \\r
+ ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))\r
+\r
+#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))\r
+#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))\r
+#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+\r
+#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))\r
+#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))\r
+#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))\r
+\r
+#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \\r
+ ((VALUE) == RCC_PLL2VCIRANGE_1) || \\r
+ ((VALUE) == RCC_PLL2VCIRANGE_2) || \\r
+ ((VALUE) == RCC_PLL2VCIRANGE_3))\r
+\r
+#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \\r
+ ((VALUE) == RCC_PLL3VCIRANGE_1) || \\r
+ ((VALUE) == RCC_PLL3VCIRANGE_2) || \\r
+ ((VALUE) == RCC_PLL3VCIRANGE_3))\r
+\r
+#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \\r
+ ((VALUE) == RCC_PLL2VCOMEDIUM))\r
+\r
+#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \\r
+ ((VALUE) == RCC_PLL3VCOMEDIUM))\r
+\r
+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)\r
+\r
+#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))\r
+\r
+#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \\r
+ ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))\r
+\r
+#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \\r
+ ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))\r
+\r
+#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)|| \\r
+ ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))\r
+\r
+#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \\r
+ ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))\r
+\r
+#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \\r
+ ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))\r
+\r
+#define IS_RCC_QSPICLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \\r
+ ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))\r
+\r
+#if defined(DSI)\r
+#define IS_RCC_DSICLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \\r
+ ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))\r
+#endif /*DSI*/\r
+\r
+#define IS_RCC_FMCCLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \\r
+ ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \\r
+ ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))\r
+\r
+#if defined(FDCAN1) || defined(FDCAN2)\r
+#define IS_RCC_FDCANCLK(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \\r
+ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))\r
+#endif /*FDCAN1 || FDCAN2*/\r
+\r
+#define IS_RCC_SDMMC(__SOURCE__) \\r
+ (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \\r
+ ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))\r
+\r
+#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))\r
+\r
+#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \\r
+ ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \\r
+ ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))\r
+\r
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \\r
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \\r
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \\r
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))\r
+\r
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_CECCLKSOURCE_CSI))\r
+\r
+#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_CLKPSOURCE_CSI) || \\r
+ ((SOURCE) == RCC_CLKPSOURCE_HSE))\r
+#define IS_RCC_TIMPRES(VALUE) \\r
+ (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \\r
+ ((VALUE) == RCC_TIMPRES_ACTIVATED))\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \\r
+ ((CORE) == RCC_BOOT_C2))\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+#define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \\r
+ ((WWDG) == RCC_WWDG2))\r
+#else\r
+#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \\r
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \\r
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \\r
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))\r
+\r
+#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \\r
+ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \\r
+ ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \\r
+ ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))\r
+\r
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \\r
+ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))\r
+\r
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))\r
+\r
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))\r
+\r
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))\r
+\r
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \\r
+ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_RCC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_tim.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of TIM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_TIM_H\r
+#define STM32H7xx_HAL_TIM_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Types TIM Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM Time base Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+ uint32_t ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_ClockDivision */\r
+\r
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.\r
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.\r
+ This parameter can be a value of @ref TIM_AutoReloadPreload */\r
+} TIM_Base_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Output Compare Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.\r
+ This parameter can be a value of @ref TIM_Output_Fast_State\r
+ @note This parameter is valid only in PWM1 and PWM2 mode. */\r
+\r
+\r
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+} TIM_OC_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM One Pulse Mode Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_OnePulse_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Input Capture Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_IC_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Encoder Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Encoder_Mode */\r
+\r
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC1Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC2Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_Encoder_InitTypeDef;\r
+\r
+/**\r
+ * @brief Clock Configuration Handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockSource; /*!< TIM clock sources\r
+ This parameter can be a value of @ref TIM_Clock_Source */\r
+ uint32_t ClockPolarity; /*!< TIM clock polarity\r
+ This parameter can be a value of @ref TIM_Clock_Polarity */\r
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler\r
+ This parameter can be a value of @ref TIM_Clock_Prescaler */\r
+ uint32_t ClockFilter; /*!< TIM clock filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClockConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Clear Input Configuration Handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClearInputState; /*!< TIM clear Input state\r
+ This parameter can be ENABLE or DISABLE */\r
+ uint32_t ClearInputSource; /*!< TIM clear Input sources\r
+ This parameter can be a value of @ref TIM_ClearInput_Source */\r
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity\r
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */\r
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler\r
+ This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClearInputConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Master configuration Structure definition\r
+ * @note Advanced timers provide TRGO2 internal line which is redirected\r
+ * to the ADC\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection\r
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */\r
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection\r
+ This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */\r
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection\r
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
+} TIM_MasterConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Slave configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t SlaveMode; /*!< Slave mode selection\r
+ This parameter can be a value of @ref TIM_Slave_Mode */\r
+ uint32_t InputTrigger; /*!< Input Trigger source\r
+ This parameter can be a value of @ref TIM_Trigger_Selection */\r
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity\r
+ This parameter can be a value of @ref TIM_Trigger_Polarity */\r
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler\r
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */\r
+ uint32_t TriggerFilter; /*!< Input trigger filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+} TIM_SlaveConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Break input(s) and Dead time configuration Structure definition\r
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable\r
+ * filter and polarity.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode\r
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode\r
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
+ uint32_t LockLevel; /*!< TIM Lock level\r
+ This parameter can be a value of @ref TIM_Lock_level */\r
+ uint32_t DeadTime; /*!< TIM dead Time\r
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
+ uint32_t BreakState; /*!< TIM Break State\r
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
+ uint32_t BreakPolarity; /*!< TIM Break input polarity\r
+ This parameter can be a value of @ref TIM_Break_Polarity */\r
+ uint32_t BreakFilter; /*!< Specifies the break input filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+ uint32_t Break2State; /*!< TIM Break2 State\r
+ This parameter can be a value of @ref TIM_Break2_Input_enable_disable */\r
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity\r
+ This parameter can be a value of @ref TIM_Break2_Polarity */\r
+ uint32_t Break2Filter; /*!< TIM break2 input filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state\r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BreakDeadTimeConfigTypeDef;\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */\r
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */\r
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */\r
+} HAL_TIM_StateTypeDef;\r
+\r
+/**\r
+ * @brief HAL Active channel structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */\r
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */\r
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */\r
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */\r
+ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */\r
+ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */\r
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */\r
+} HAL_TIM_ActiveChannel;\r
+\r
+/**\r
+ * @brief TIM Time Base Handle Structure definition\r
+ */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+typedef struct __TIM_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+{\r
+ TIM_TypeDef *Instance; /*!< Register base address */\r
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */\r
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */\r
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array\r
+ This array is accessed by a @ref DMA_Handle_index */\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */\r
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */\r
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */\r
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */\r
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */\r
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */\r
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */\r
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */\r
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */\r
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */\r
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */\r
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */\r
+ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */\r
+ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */\r
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */\r
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */\r
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */\r
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */\r
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */\r
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */\r
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */\r
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */\r
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */\r
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */\r
+ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */\r
+ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */\r
+ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */\r
+ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+} TIM_HandleTypeDef;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL TIM Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */\r
+ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */\r
+ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */\r
+ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */\r
+ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */\r
+ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */\r
+ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */\r
+ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */\r
+ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */\r
+ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */\r
+ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */\r
+ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */\r
+ ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */\r
+ ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */\r
+ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */\r
+ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */\r
+ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */\r
+ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */\r
+\r
+ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */\r
+ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */\r
+ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */\r
+ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */\r
+ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */\r
+ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */\r
+ ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */\r
+ ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */\r
+ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */\r
+ ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */\r
+} HAL_TIM_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL TIM Callback pointer definition\r
+ */\r
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */\r
+\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Constants TIM Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */\r
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address\r
+ * @{\r
+ */\r
+#define TIM_DMABASE_CR1 0x00000000U\r
+#define TIM_DMABASE_CR2 0x00000001U\r
+#define TIM_DMABASE_SMCR 0x00000002U\r
+#define TIM_DMABASE_DIER 0x00000003U\r
+#define TIM_DMABASE_SR 0x00000004U\r
+#define TIM_DMABASE_EGR 0x00000005U\r
+#define TIM_DMABASE_CCMR1 0x00000006U\r
+#define TIM_DMABASE_CCMR2 0x00000007U\r
+#define TIM_DMABASE_CCER 0x00000008U\r
+#define TIM_DMABASE_CNT 0x00000009U\r
+#define TIM_DMABASE_PSC 0x0000000AU\r
+#define TIM_DMABASE_ARR 0x0000000BU\r
+#define TIM_DMABASE_RCR 0x0000000CU\r
+#define TIM_DMABASE_CCR1 0x0000000DU\r
+#define TIM_DMABASE_CCR2 0x0000000EU\r
+#define TIM_DMABASE_CCR3 0x0000000FU\r
+#define TIM_DMABASE_CCR4 0x00000010U\r
+#define TIM_DMABASE_BDTR 0x00000011U\r
+#define TIM_DMABASE_DCR 0x00000012U\r
+#define TIM_DMABASE_DMAR 0x00000013U\r
+#define TIM_DMABASE_CCMR3 0x00000015U\r
+#define TIM_DMABASE_CCR5 0x00000016U\r
+#define TIM_DMABASE_CCR6 0x00000017U\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+#define TIM_DMABASE_AF1 0x00000018U\r
+#define TIM_DMABASE_AF2 0x00000019U\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+#define TIM_DMABASE_TISEL 0x00000020U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Event_Source TIM Event Source\r
+ * @{\r
+ */\r
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */\r
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */\r
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */\r
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */\r
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */\r
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */\r
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */\r
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */\r
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity\r
+ * @{\r
+ */\r
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\r
+ * @{\r
+ */\r
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */\r
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */\r
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */\r
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */\r
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode TIM Counter Mode\r
+ * @{\r
+ */\r
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */\r
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */\r
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */\r
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */\r
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClockDivision TIM Clock Division\r
+ * @{\r
+ */\r
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */\r
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */\r
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */\r
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\r
+ * @{\r
+ */\r
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */\r
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State\r
+ * @{\r
+ */\r
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */\r
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */\r
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity\r
+ * @{\r
+ */\r
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */\r
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r
+ * @{\r
+ */\r
+#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */\r
+#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State\r
+ * @{\r
+ */\r
+#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */\r
+#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State\r
+ * @{\r
+ */\r
+#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */\r
+#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity\r
+ * @{\r
+ */\r
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */\r
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */\r
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\r
+ * @{\r
+ */\r
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively */\r
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */\r
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */\r
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */\r
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r
+ * @{\r
+ */\r
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */\r
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r
+ * @{\r
+ */\r
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */\r
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */\r
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition\r
+ * @{\r
+ */\r
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */\r
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */\r
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */\r
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */\r
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */\r
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */\r
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */\r
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Commutation_Source TIM Commutation Source\r
+ * @{\r
+ */\r
+#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */\r
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_sources TIM DMA Sources\r
+ * @{\r
+ */\r
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */\r
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */\r
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */\r
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */\r
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */\r
+#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */\r
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Flag_definition TIM Flag Definition\r
+ * @{\r
+ */\r
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */\r
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */\r
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */\r
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */\r
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */\r
+#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */\r
+#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */\r
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */\r
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */\r
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */\r
+#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */\r
+#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */\r
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */\r
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */\r
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */\r
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Channel TIM Channel\r
+ * @{\r
+ */\r
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */\r
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */\r
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */\r
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */\r
+#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */\r
+#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */\r
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Source TIM Clock Source\r
+ * @{\r
+ */\r
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */\r
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */\r
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */\r
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */\r
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */\r
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */\r
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */\r
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */\r
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */\r
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */\r
+#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */\r
+#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */\r
+#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */\r
+#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */\r
+#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */\r
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\r
+ * @{\r
+ */\r
+#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */\r
+#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\r
+ * @{\r
+ */\r
+#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */\r
+#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Lock_level TIM Lock level\r
+ * @{\r
+ */\r
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */\r
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */\r
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */\r
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable\r
+ * @{\r
+ */\r
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */\r
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity\r
+ * @{\r
+ */\r
+#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */\r
+#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable\r
+ * @{\r
+ */\r
+#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */\r
+#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity\r
+ * @{\r
+ */\r
+#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */\r
+#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable\r
+ * @{\r
+ */\r
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */\r
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event \r
+ (if none of the break inputs BRK and BRK2 is active) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3\r
+ * @{\r
+ */\r
+#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r
+#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */\r
+#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */\r
+#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r
+ * @{\r
+ */\r
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */\r
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */\r
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */\r
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */\r
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)\r
+ * @{\r
+ */\r
+#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode\r
+ * @{\r
+ */\r
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */\r
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Slave_Mode TIM Slave mode\r
+ * @{\r
+ */\r
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */\r
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */\r
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */\r
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */\r
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */\r
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes\r
+ * @{\r
+ */\r
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */\r
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */\r
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */\r
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */\r
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */\r
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */\r
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */\r
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */\r
+#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */\r
+#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */\r
+#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */\r
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\r
+ * @{\r
+ */\r
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */\r
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */\r
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */\r
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */\r
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */\r
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */\r
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */\r
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */\r
+#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */\r
+#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */\r
+#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */\r
+#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */\r
+#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */\r
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */\r
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */\r
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection\r
+ * @{\r
+ */\r
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */\r
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length\r
+ * @{\r
+ */\r
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Handle_index TIM DMA Handle Index\r
+ * @{\r
+ */\r
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */\r
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */\r
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State\r
+ * @{\r
+ */\r
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */\r
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */\r
+#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */\r
+#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break_System TIM Break System\r
+ * @{\r
+ */\r
+#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */\r
+#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */\r
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */\r
+#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Macros TIM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset TIM handle state.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \\r
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \\r
+ (__HANDLE__)->Base_MspInitCallback = NULL; \\r
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->IC_MspInitCallback = NULL; \\r
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->OC_MspInitCallback = NULL; \\r
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \\r
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \\r
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \\r
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \\r
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @brief Enable the TIM peripheral.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r
+\r
+/**\r
+ * @brief Enable the TIM main Output.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r
+\r
+/**\r
+ * @brief Disable the TIM peripheral.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE(__HANDLE__) \\r
+ do { \\r
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
+ { \\r
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
+ { \\r
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Disable the TIM main Output.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled\r
+ */\r
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\r
+ do { \\r
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
+ { \\r
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
+ { \\r
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Disable the TIM main Output.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ * @note The Main Output Enable of a timer instance is disabled unconditionally\r
+ */\r
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)\r
+\r
+/** @brief Enable the specified TIM interrupt.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified TIM interrupt.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r
+\r
+/** @brief Enable the specified DMA request.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __DMA__ specifies the TIM DMA request to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: Update DMA request\r
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
+ * @arg TIM_DMA_COM: Commutation DMA request\r
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))\r
+\r
+/** @brief Disable the specified DMA request.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __DMA__ specifies the TIM DMA request to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: Update DMA request\r
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
+ * @arg TIM_DMA_COM: Commutation DMA request\r
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r
+\r
+/** @brief Check whether the specified TIM interrupt flag is set or not.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __FLAG__ specifies the TIM interrupt flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
+ * @arg TIM_FLAG_COM: Commutation interrupt flag\r
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+ * @arg TIM_FLAG_BREAK: Break interrupt flag\r
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the specified TIM interrupt flag.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
+ * @arg TIM_FLAG_COM: Commutation interrupt flag\r
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+ * @arg TIM_FLAG_BREAK: Break interrupt flag\r
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
+\r
+/**\r
+ * @brief Check whether the specified TIM interrupt source is enabled or not.\r
+ * @param __HANDLE__ TIM handle\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval The state of TIM_IT (SET or RESET).\r
+ */\r
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \\r
+ == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Clear the TIM interrupt pending bits.\r
+ * @param __HANDLE__ TIM handle\r
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\r
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder\r
+mode.\r
+ */\r
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r
+\r
+/**\r
+ * @brief Set the TIM Prescaler on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __PRESC__ specifies the Prescaler new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))\r
+\r
+/**\r
+ * @brief Set the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __COUNTER__ specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r
+\r
+/**\r
+ * @brief Get the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)\r
+ */\r
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)\r
+\r
+/**\r
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __AUTORELOAD__ specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \\r
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Autoreload Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)\r
+ */\r
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)\r
+\r
+/**\r
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CKD__ specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \\r
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \\r
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Clock Division value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval The clock division can be one of the following values:\r
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+ */\r
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r
+\r
+/**\r
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+ do{ \\r
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Input Capture prescaler on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r
+ * @retval The input capture prescaler can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ */\r
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\r
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)\r
+\r
+/**\r
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @param __COMPARE__ specifies the Capture Compare register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\r
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))\r
+\r
+/**\r
+ * @brief Get the TIM Capture Compare Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value\r
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value\r
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)\r
+ */\r
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\r
+ ((__HANDLE__)->Instance->CCR6))\r
+\r
+/**\r
+ * @brief Set the TIM Output compare preload.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\\r
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))\r
+\r
+/**\r
+ * @brief Reset the TIM Output compare preload.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\\r
+ ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))\r
+\r
+/**\r
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter\r
+ * overflow/underflow generates an update interrupt or DMA request (if\r
+ * enabled)\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)\r
+\r
+/**\r
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the\r
+ * following events generate an update interrupt or DMA request (if\r
+ * enabled):\r
+ * _ Counter overflow underflow\r
+ * _ Setting the UG bit\r
+ * _ Update generation through the slave mode controller\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)\r
+\r
+/**\r
+ * @brief Set the TIM Capture x input polarity on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __POLARITY__ Polarity for TIx source\r
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+ do{ \\r
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported macros ----------------------------------------------------*/\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Constants TIM Private Constants\r
+ * @{\r
+ */\r
+/* The counter of a timer instance is disabled only if all the CCx and CCxN\r
+ channels have been disabled */\r
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r
+/**\r
+ * @}\r
+ */\r
+/* End of private constants --------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Macros TIM Private Macros\r
+ * @{\r
+ */\r
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \\r
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))\r
+\r
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CR2) || \\r
+ ((__BASE__) == TIM_DMABASE_SMCR) || \\r
+ ((__BASE__) == TIM_DMABASE_DIER) || \\r
+ ((__BASE__) == TIM_DMABASE_SR) || \\r
+ ((__BASE__) == TIM_DMABASE_EGR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCER) || \\r
+ ((__BASE__) == TIM_DMABASE_CNT) || \\r
+ ((__BASE__) == TIM_DMABASE_PSC) || \\r
+ ((__BASE__) == TIM_DMABASE_ARR) || \\r
+ ((__BASE__) == TIM_DMABASE_RCR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR4) || \\r
+ ((__BASE__) == TIM_DMABASE_BDTR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR5) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR6) || \\r
+ ((__BASE__) == TIM_DMABASE_AF1) || \\r
+ ((__BASE__) == TIM_DMABASE_AF2) || \\r
+ ((__BASE__) == TIM_DMABASE_TISEL))\r
+\r
+\r
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r
+\r
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r
+\r
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\r
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\r
+\r
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \\r
+ ((__STATE__) == TIM_OCFAST_ENABLE))\r
+\r
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\r
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\r
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \\r
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))\r
+\r
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\r
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))\r
+\r
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))\r
+\r
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))\r
+\r
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \\r
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))\r
+\r
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI12))\r
+\r
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_6) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))\r
+\r
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))\r
+\r
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))\r
+\r
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r
+\r
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r
+\r
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \\r
+ ((__STATE__) == TIM_OSSR_DISABLE))\r
+\r
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \\r
+ ((__STATE__) == TIM_OSSI_DISABLE))\r
+\r
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_3))\r
+\r
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)\r
+\r
+\r
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \\r
+ ((__STATE__) == TIM_BREAK_DISABLE))\r
+\r
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\r
+\r
+#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \\r
+ ((__STATE__) == TIM_BREAK2_DISABLE))\r
+\r
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r
+\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\r
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\r
+\r
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))\r
+\r
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \\r
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \\r
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC4REF))\r
+\r
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \\r
+ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \\r
+ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC1) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r
+\r
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\r
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r
+\r
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
+\r
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \\r
+ ((__MODE__) == TIM_OCMODE_PWM2) || \\r
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \\r
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \\r
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \\r
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))\r
+\r
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \\r
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \\r
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\r
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r
+\r
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \\r
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \\r
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \\r
+ ((__SELECTION__) == TIM_TS_ETRF) || \\r
+ ((__SELECTION__) == TIM_TS_ITR4) || \\r
+ ((__SELECTION__) == TIM_TS_ITR5) || \\r
+ ((__SELECTION__) == TIM_TS_ITR6) || \\r
+ ((__SELECTION__) == TIM_TS_ITR7) || \\r
+ ((__SELECTION__) == TIM_TS_ITR8))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_ITR4) || \\r
+ ((__SELECTION__) == TIM_TS_ITR5) || \\r
+ ((__SELECTION__) == TIM_TS_ITR6) || \\r
+ ((__SELECTION__) == TIM_TS_ITR7) || \\r
+ ((__SELECTION__) == TIM_TS_ITR8) || \\r
+ ((__SELECTION__) == TIM_TS_NONE))\r
+\r
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))\r
+\r
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))\r
+\r
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\r
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r
+\r
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r
+\r
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))\r
+\r
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)\r
+\r
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \\r
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \\r
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \\r
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))\r
+\r
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \\r
+ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
+\r
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\r
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))\r
+\r
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\r
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r
+\r
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\\r
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))\r
+\r
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\r
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/* Include TIM HAL Extended module */\r
+#include "stm32h7xx_hal_tim_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+ * @brief Time Base functions\r
+ * @{\r
+ */\r
+/* Time Base functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+ * @brief TIM Output Compare functions\r
+ * @{\r
+ */\r
+/* Timer Output Compare functions *********************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+ * @brief TIM PWM functions\r
+ * @{\r
+ */\r
+/* Timer PWM functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+ * @brief TIM Input Capture functions\r
+ * @{\r
+ */\r
+/* Timer Input Capture functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+ * @brief TIM One Pulse functions\r
+ * @{\r
+ */\r
+/* Timer One Pulse functions **************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+ * @brief TIM Encoder functions\r
+ * @{\r
+ */\r
+/* Timer Encoder functions ****************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\r
+ uint32_t *pData2, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+ * @brief IRQ handler management\r
+ * @{\r
+ */\r
+/* Interrupt Handler functions ***********************************************/\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Control functions *********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,\r
+ uint32_t OutputChannel, uint32_t InputChannel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+ uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,\r
+ uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,\r
+ uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions\r
+ * @{\r
+ */\r
+/* Callback in non blocking modes (Interrupt and DMA) *************************/\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\r
+ pTIM_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions----------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+ * @{\r
+ */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r
+\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_TIM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_tim_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of TIM HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_TIM_EX_H\r
+#define STM32H7xx_HAL_TIM_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM Hall sensor Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+} TIM_HallSensor_InitTypeDef;\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+\r
+/**\r
+ * @brief TIM Break/Break2 input configuration\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Source; /*!< Specifies the source of the timer break input.\r
+ This parameter can be a value of @ref TIMEx_Break_Input_Source */\r
+ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.\r
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */\r
+ uint32_t Polarity; /*!< Specifies the break input source polarity.\r
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity\r
+ Not relevant when analog watchdog output of the DFSDM1 used as break input source */\r
+}\r
+TIMEx_BreakInputConfigTypeDef;\r
+\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx_Remap TIM Extended Remapping\r
+ * @{\r
+ */\r
+#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */\r
+#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */\r
+#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */\r
+#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */\r
+#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */\r
+#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */\r
+#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */\r
+#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */\r
+#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */\r
+\r
+#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */\r
+#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */\r
+#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */\r
+#define TIM_TIM8_ETR_ADC1_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD1 */\r
+#define TIM_TIM8_ETR_ADC1_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC1 AWD2 */\r
+#define TIM_TIM8_ETR_ADC1_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD3 */\r
+#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */\r
+#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */\r
+#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */\r
+\r
+#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */\r
+#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */\r
+#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */\r
+#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */\r
+#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */\r
+#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */\r
+\r
+#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */\r
+#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */\r
+\r
+#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */\r
+#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */\r
+#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */\r
+/**\r
+ * @}\r
+ */\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+\r
+/** @defgroup TIMEx_Break_Input TIM Extended Break input\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */\r
+#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */\r
+#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */\r
+#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */\r
+#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */\r
+#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */\r
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+\r
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection\r
+ * @{\r
+ */\r
+#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */\r
+#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */\r
+\r
+#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */\r
+#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */\r
+\r
+#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */\r
+#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */\r
+#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */\r
+#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */\r
+\r
+#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */\r
+#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */\r
+#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */\r
+#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */\r
+\r
+#define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */\r
+#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */\r
+#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */\r
+\r
+#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */\r
+#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */\r
+#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */\r
+#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */\r
+#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_3) /* !< TIM15_TI1 is connected to RCC LSE */\r
+#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */\r
+#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */\r
+\r
+#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */\r
+#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */\r
+#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */\r
+#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */\r
+\r
+#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */\r
+#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */\r
+#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */\r
+#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */\r
+\r
+#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */\r
+#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to RCC LSI */\r
+#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC LSE */\r
+#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported macro -----------------------------------------------------*/\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros\r
+ * @{\r
+ */\r
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \\r
+ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \\r
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \\r
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \\r
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \\r
+ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))\r
+\r
+#define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\\r
+ ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\\r
+ ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\\r
+ ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\\r
+ ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\\r
+ ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\\r
+ ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\\r
+ ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\\r
+ ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\\r
+ ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\\r
+ ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\\r
+ ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\\r
+ ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\\r
+ ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\\r
+ ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\\r
+ ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\\r
+ ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\\r
+ ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1))\r
+\r
+#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\\r
+ ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD1) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD2) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD3) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\\r
+ ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\\r
+ ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\\r
+ ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\\r
+ ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\\r
+ ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\\r
+ ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\\r
+ ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\\r
+ ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\\r
+ ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\\r
+ ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\\r
+ ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\\r
+ ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private macro ------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+ * @brief Timer Hall Sensor functions\r
+ * @{\r
+ */\r
+/* Timer Hall Sensor functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);\r
+\r
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);\r
+\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+ * @brief Timer Complementary Output Compare functions\r
+ * @{\r
+ */\r
+/* Timer Complementary Output Compare functions *****************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+ * @brief Timer Complementary PWM functions\r
+ * @{\r
+ */\r
+/* Timer Complementary PWM functions ****************************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+ * @brief Timer Complementary One Pulse functions\r
+ * @{\r
+ */\r
+/* Timer Complementary One Pulse functions **********************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Extended Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,\r
+ uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,\r
+ uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,\r
+ uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
+ TIM_MasterConfigTypeDef *sMasterConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,\r
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);\r
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
+ * @brief Extended Callbacks functions\r
+ * @{\r
+ */\r
+/* Extended Callback **********************************************************/\r
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
+ * @brief Extended Peripheral State functions\r
+ * @{\r
+ */\r
+/* Extended Peripheral State functions ***************************************/\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions----------------------------------------------------------*/\r
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions\r
+ * @{\r
+ */\r
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32H7xx_HAL_TIM_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_uart.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of UART HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_UART_H\r
+#define STM32H7xx_HAL_UART_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Types UART Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART Init Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.\r
+ The baud rate register is computed using the following formula:\r
+ LPUART:\r
+ =======\r
+ Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))\r
+ where lpuart_ker_ck_pres is the UART input clock divided by a prescaler\r
+ UART:\r
+ =====\r
+ - If oversampling is 16 or in LIN mode,\r
+ Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))\r
+ - If oversampling is 8,\r
+ Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]\r
+ Baud Rate Register[3] = 0\r
+ Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1\r
+ where uart_ker_ck_pres is the UART input clock divided by a prescaler */\r
+\r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref UARTEx_Word_Length. */\r
+\r
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref UART_Stop_Bits. */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref UART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+\r
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref UART_Mode. */\r
+\r
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */\r
+\r
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).\r
+ This parameter can be a value of @ref UART_Over_Sampling. */\r
+\r
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.\r
+ Selecting the single sample method increases the receiver tolerance to clock\r
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */\r
+\r
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.\r
+ This parameter can be a value of @ref UART_ClockPrescaler. */\r
+\r
+} UART_InitTypeDef;\r
+\r
+/**\r
+ * @brief UART Advanced Features initialization structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several\r
+ Advanced Features may be initialized at the same time .\r
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */\r
+\r
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.\r
+ This parameter can be a value of @ref UART_Tx_Inv. */\r
+\r
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.\r
+ This parameter can be a value of @ref UART_Rx_Inv. */\r
+\r
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic\r
+ vs negative/inverted logic).\r
+ This parameter can be a value of @ref UART_Data_Inv. */\r
+\r
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.\r
+ This parameter can be a value of @ref UART_Rx_Tx_Swap. */\r
+\r
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.\r
+ This parameter can be a value of @ref UART_Overrun_Disable. */\r
+\r
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.\r
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */\r
+\r
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.\r
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable. */\r
+\r
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate\r
+ detection is carried out.\r
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */\r
+\r
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.\r
+ This parameter can be a value of @ref UART_MSB_First. */\r
+} UART_AdvFeatureInitTypeDef;\r
+\r
+\r
+\r
+/**\r
+ * @brief HAL UART State definition\r
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).\r
+ * - gState contains UART state information related to global Handle management\r
+ * and also information related to Tx operations.\r
+ * gState value coding follow below described bitmap :\r
+ * b7-b6 Error information\r
+ * 00 : No Error\r
+ * 01 : (Not Used)\r
+ * 10 : Timeout\r
+ * 11 : Error\r
+ * b5 Peripheral initialization status\r
+ * 0 : Reset (Peripheral not initialized)\r
+ * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)\r
+ * b4-b3 (not used)\r
+ * xx : Should be set to 00\r
+ * b2 Intrinsic process state\r
+ * 0 : Ready\r
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)\r
+ * b1 (not used)\r
+ * x : Should be set to 0\r
+ * b0 Tx state\r
+ * 0 : Ready (no Tx operation ongoing)\r
+ * 1 : Busy (Tx operation ongoing)\r
+ * - RxState contains information related to Rx operations.\r
+ * RxState value coding follow below described bitmap :\r
+ * b7-b6 (not used)\r
+ * xx : Should be set to 00\r
+ * b5 Peripheral initialization status\r
+ * 0 : Reset (Peripheral not initialized)\r
+ * 1 : Init done (Peripheral not initialized)\r
+ * b4-b2 (not used)\r
+ * xxx : Should be set to 000\r
+ * b1 Rx state\r
+ * 0 : Ready (no Rx operation ongoing)\r
+ * 1 : Busy (Rx operation ongoing)\r
+ * b0 (not used)\r
+ * x : Should be set to 0.\r
+ */\r
+typedef uint32_t HAL_UART_StateTypeDef;\r
+\r
+/**\r
+ * @brief UART clock sources definition\r
+ */\r
+typedef enum\r
+{\r
+ UART_CLOCKSOURCE_D2PCLK1 = 0x00U, /*!< Domain2 PCLK1 clock source */\r
+ UART_CLOCKSOURCE_D2PCLK2 = 0x01U, /*!< Domain2 PCLK2 clock source */\r
+ UART_CLOCKSOURCE_D3PCLK1 = 0x02U, /*!< Domain3 PCLK1 clock source */\r
+ UART_CLOCKSOURCE_PLL2 = 0x04U, /*!< PLL2Q clock source */\r
+ UART_CLOCKSOURCE_PLL3 = 0x08U, /*!< PLL3Q clock source */\r
+ UART_CLOCKSOURCE_HSI = 0x10U, /*!< HSI clock source */\r
+ UART_CLOCKSOURCE_CSI = 0x20U, /*!< CSI clock source */\r
+ UART_CLOCKSOURCE_LSE = 0x40U, /*!< LSE clock source */\r
+ UART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */\r
+\r
+} UART_ClockSourceTypeDef;\r
+\r
+/**\r
+ * @brief UART handle Structure definition\r
+ */\r
+typedef struct __UART_HandleTypeDef\r
+{\r
+ USART_TypeDef *Instance; /*!< UART registers base address */\r
+\r
+ UART_InitTypeDef Init; /*!< UART communication parameters */\r
+\r
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */\r
+\r
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */\r
+\r
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */\r
+\r
+ uint16_t Mask; /*!< UART Rx RDR register mask */\r
+\r
+ uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used.\r
+ This parameter can be a value of @ref UARTEx_FIFO_mode. */\r
+\r
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */\r
+\r
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */\r
+\r
+ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */\r
+\r
+ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+\r
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management\r
+ and also related to Tx operations.\r
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.\r
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */\r
+\r
+ __IO uint32_t ErrorCode; /*!< UART Error code */\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */\r
+ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */\r
+ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */\r
+ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */\r
+ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */\r
+ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */\r
+ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */\r
+ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */\r
+ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */\r
+ void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */\r
+ void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */\r
+\r
+ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */\r
+ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+} UART_HandleTypeDef;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL UART Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */\r
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */\r
+ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */\r
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */\r
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */\r
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */\r
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */\r
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */\r
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */\r
+ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */\r
+ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */\r
+\r
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */\r
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */\r
+\r
+} HAL_UART_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL UART Callback pointer definition\r
+ */\r
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */\r
+\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Constants UART Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART_State_Definition UART State Code Definition\r
+ * @{\r
+ */\r
+#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized\r
+ Value is allowed for gState and RxState */\r
+#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use\r
+ Value is allowed for gState and RxState */\r
+#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing\r
+ Value is allowed for gState only */\r
+#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing\r
+ Value is allowed for gState only */\r
+#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing\r
+ Value is allowed for RxState only */\r
+#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing\r
+ Not to be used for neither gState nor RxState.\r
+ Value is result of combination (Or) between gState and RxState values */\r
+#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state\r
+ Value is allowed for gState only */\r
+#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error\r
+ Value is allowed for gState only */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Error_Definition UART Error Definition\r
+ * @{\r
+ */\r
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */\r
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */\r
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */\r
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */\r
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */\r
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits\r
+ * @{\r
+ */\r
+#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */\r
+#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */\r
+#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */\r
+#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Parity UART Parity\r
+ * @{\r
+ */\r
+#define UART_PARITY_NONE 0x00000000U /*!< No parity */\r
+#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */\r
+#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r
+ * @{\r
+ */\r
+#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */\r
+#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */\r
+#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */\r
+#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Mode UART Transfer Mode\r
+ * @{\r
+ */\r
+#define UART_MODE_RX USART_CR1_RE /*!< RX mode */\r
+#define UART_MODE_TX USART_CR1_TE /*!< TX mode */\r
+#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_State UART State\r
+ * @{\r
+ */\r
+#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */\r
+#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Over_Sampling UART Over Sampling\r
+ * @{\r
+ */\r
+#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */\r
+#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method\r
+ * @{\r
+ */\r
+#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */\r
+#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_ClockPrescaler UART Clock Prescaler\r
+ * @{\r
+ */\r
+#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */\r
+#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */\r
+#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */\r
+#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */\r
+#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */\r
+#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */\r
+#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */\r
+#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */\r
+#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */\r
+#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */\r
+#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */\r
+#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut\r
+ * @{\r
+ */\r
+#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */\r
+#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_LIN UART Local Interconnection Network mode\r
+ * @{\r
+ */\r
+#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */\r
+#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection\r
+ * @{\r
+ */\r
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */\r
+#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Tx UART DMA Tx\r
+ * @{\r
+ */\r
+#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */\r
+#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Rx UART DMA Rx\r
+ * @{\r
+ */\r
+#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */\r
+#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection\r
+ * @{\r
+ */\r
+#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */\r
+#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods\r
+ * @{\r
+ */\r
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */\r
+#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Request_Parameters UART Request Parameters\r
+ * @{\r
+ */\r
+#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */\r
+#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */\r
+#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */\r
+#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */\r
+#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */\r
+#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */\r
+#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */\r
+#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */\r
+#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */\r
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */\r
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */\r
+#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */\r
+#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */\r
+#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */\r
+#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */\r
+#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */\r
+#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */\r
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */\r
+#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */\r
+#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */\r
+#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register\r
+ * @{\r
+ */\r
+#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection\r
+ * @{\r
+ */\r
+#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */\r
+#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */\r
+#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity\r
+ * @{\r
+ */\r
+#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */\r
+#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register\r
+ * @{\r
+ */\r
+#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register\r
+ * @{\r
+ */\r
+#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask\r
+ * @{\r
+ */\r
+#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value\r
+ * @{\r
+ */\r
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Flags UART Status Flags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the ISR register\r
+ * @{\r
+ */\r
+#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */\r
+#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */\r
+#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */\r
+#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */\r
+#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */\r
+#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */\r
+#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */\r
+#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */\r
+#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */\r
+#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */\r
+#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */\r
+#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */\r
+#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */\r
+#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */\r
+#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */\r
+#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */\r
+#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */\r
+#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */\r
+#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */\r
+#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */\r
+#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */\r
+#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */\r
+#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */\r
+#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */\r
+#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */\r
+#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition\r
+ * Elements values convention: 000ZZZZZ0XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * - ZZZZZ : Flag position in the ISR register(5bits)\r
+ * Elements values convention: 000000000XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * Elements values convention: 0000ZZZZ00000000b\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ * @{\r
+ */\r
+#define UART_IT_PE 0x0028U /*!< UART parity error interruption */\r
+#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */\r
+#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */\r
+#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */\r
+#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */\r
+#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */\r
+#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */\r
+#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */\r
+#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */\r
+#define UART_IT_CM 0x112EU /*!< UART character match interruption */\r
+#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */\r
+#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */\r
+#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */\r
+#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */\r
+#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */\r
+\r
+#define UART_IT_ERR 0x0060U /*!< UART error interruption */\r
+\r
+#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */\r
+#define UART_IT_NE 0x0200U /*!< UART noise error interruption */\r
+#define UART_IT_FE 0x0100U /*!< UART frame error interruption */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags\r
+ * @{\r
+ */\r
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */\r
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */\r
+#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */\r
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */\r
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */\r
+#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */\r
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */\r
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */\r
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */\r
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */\r
+#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Macros UART Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset UART handle states.\r
+ * @param __HANDLE__ UART handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \\r
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0U)\r
+#else\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \\r
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \\r
+ } while(0U)\r
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/** @brief Flush the UART Data registers.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \\r
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \\r
+ } while(0U)\r
+\r
+/** @brief Clear the specified UART pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag\r
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag\r
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag\r
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag\r
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag\r
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag\r
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag\r
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag\r
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag\r
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag\r
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r
+\r
+/** @brief Clear the UART PE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)\r
+\r
+/** @brief Clear the UART FE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)\r
+\r
+/** @brief Clear the UART NE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)\r
+\r
+/** @brief Clear the UART ORE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)\r
+\r
+/** @brief Clear the UART IDLE pending flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)\r
+\r
+/** @brief Clear the UART TX FIFO empty clear flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)\r
+\r
+/** @brief Check whether the specified UART flag is set or not.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag\r
+ * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag\r
+ * @arg @ref UART_FLAG_RXFF RXFIFO Full flag\r
+ * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag\r
+ * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag\r
+ * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag\r
+ * @arg @ref UART_FLAG_WUF Wake up from stop mode flag\r
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)\r
+ * @arg @ref UART_FLAG_SBKF Send Break flag\r
+ * @arg @ref UART_FLAG_CMF Character match flag\r
+ * @arg @ref UART_FLAG_BUSY Busy flag\r
+ * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag\r
+ * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag\r
+ * @arg @ref UART_FLAG_CTS CTS Change flag\r
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag\r
+ * @arg @ref UART_FLAG_TXE Transmit data register empty flag\r
+ * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag\r
+ * @arg @ref UART_FLAG_TC Transmission Complete flag\r
+ * @arg @ref UART_FLAG_RXNE Receive data register not empty flag\r
+ * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag\r
+ * @arg @ref UART_FLAG_IDLE Idle Line detection flag\r
+ * @arg @ref UART_FLAG_ORE Overrun Error flag\r
+ * @arg @ref UART_FLAG_NE Noise Error flag\r
+ * @arg @ref UART_FLAG_FE Framing Error flag\r
+ * @arg @ref UART_FLAG_PE Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Enable the specified UART interrupt.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt\r
+ * @arg @ref UART_IT_CM Character match interrupt\r
+ * @arg @ref UART_IT_CTS CTS change interrupt\r
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt\r
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref UART_IT_TC Transmission complete interrupt\r
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref UART_IT_PE Parity Error interrupt\r
+ * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+\r
+/** @brief Disable the specified UART interrupt.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt\r
+ * @arg @ref UART_IT_CM Character match interrupt\r
+ * @arg @ref UART_IT_CTS CTS change interrupt\r
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt\r
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref UART_IT_TC Transmission complete interrupt\r
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref UART_IT_PE Parity Error interrupt\r
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+/** @brief Check whether the specified UART interrupt has occurred or not.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __INTERRUPT__ specifies the UART interrupt to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt\r
+ * @arg @ref UART_IT_CM Character match interrupt\r
+ * @arg @ref UART_IT_CTS CTS change interrupt\r
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt\r
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref UART_IT_TC Transmission complete interrupt\r
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref UART_IT_PE Parity Error interrupt\r
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)\r
+\r
+/** @brief Check whether the specified UART interrupt source is enabled or not.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __INTERRUPT__ specifies the UART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt\r
+ * @arg @ref UART_IT_CM Character match interrupt\r
+ * @arg @ref UART_IT_CTS CTS change interrupt\r
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt\r
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref UART_IT_TC Transmission complete interrupt\r
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref UART_IT_PE Parity Error interrupt\r
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \\r
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \\r
+ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)\r
+\r
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag\r
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag\r
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag\r
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag\r
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag\r
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag\r
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag\r
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag\r
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag\r
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag\r
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))\r
+\r
+/** @brief Set a specific UART request flag.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __REQ__ specifies the request flag to set\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request\r
+ * @arg @ref UART_SENDBREAK_REQUEST Send Break Request\r
+ * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request\r
+ * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request\r
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))\r
+\r
+/** @brief Enable the UART one bit sample method.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r
+\r
+/** @brief Disable the UART one bit sample method.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)\r
+\r
+/** @brief Enable UART.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable UART.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/** @brief Enable CTS flow control.\r
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \\r
+ } while(0U)\r
+\r
+/** @brief Disable CTS flow control.\r
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \\r
+ } while(0U)\r
+\r
+/** @brief Enable RTS flow control.\r
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \\r
+ } while(0U)\r
+\r
+/** @brief Disable RTS flow control.\r
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,\r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \\r
+ } while(0U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup UART_Private_Macros UART Private Macros\r
+ * @{\r
+ */\r
+/** @brief Get UART clok division factor from clock prescaler value.\r
+ * @param __CLOCKPRESCALER__ UART prescaler value.\r
+ * @retval UART clock division factor\r
+ */\r
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \\r
+ (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)\r
+\r
+/** @brief BRR division operation to set BRR register with LPUART.\r
+ * @param __PCLK__ LPUART clock.\r
+ * @param __BAUD__ Baud rate set by the user.\r
+ * @param __CLOCKPRESCALER__ UART prescaler value.\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))\r
+\r
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.\r
+ * @param __PCLK__ UART clock.\r
+ * @param __BAUD__ Baud rate set by the user.\r
+ * @param __CLOCKPRESCALER__ UART prescaler value.\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__))\r
+\r
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.\r
+ * @param __PCLK__ UART clock.\r
+ * @param __BAUD__ Baud rate set by the user.\r
+ * @param __CLOCKPRESCALER__ UART prescaler value.\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__))\r
+\r
+/** @brief Check whether or not UART instance is Low Power UART.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)\r
+ */\r
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))\r
+\r
+/** @brief Check UART Baud rate.\r
+ * @param __BAUDRATE__ Baudrate specified by the user.\r
+ * The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)\r
+ * divided by the smallest oversampling used on the USART (i.e. 8)\r
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)\r
+ */\r
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)\r
+\r
+/** @brief Check UART assertion time.\r
+ * @param __TIME__ 5-bit value assertion time.\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)\r
+\r
+/** @brief Check UART deassertion time.\r
+ * @param __TIME__ 5-bit value deassertion time.\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)\r
+\r
+/**\r
+ * @brief Ensure that UART frame number of stop bits is valid.\r
+ * @param __STOPBITS__ UART frame number of stop bits.\r
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)\r
+ */\r
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \\r
+ ((__STOPBITS__) == UART_STOPBITS_1) || \\r
+ ((__STOPBITS__) == UART_STOPBITS_1_5) || \\r
+ ((__STOPBITS__) == UART_STOPBITS_2))\r
+\r
+/**\r
+ * @brief Ensure that LPUART frame number of stop bits is valid.\r
+ * @param __STOPBITS__ LPUART frame number of stop bits.\r
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)\r
+ */\r
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \\r
+ ((__STOPBITS__) == UART_STOPBITS_2))\r
+\r
+/**\r
+ * @brief Ensure that UART frame parity is valid.\r
+ * @param __PARITY__ UART frame parity.\r
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)\r
+ */\r
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \\r
+ ((__PARITY__) == UART_PARITY_EVEN) || \\r
+ ((__PARITY__) == UART_PARITY_ODD))\r
+\r
+/**\r
+ * @brief Ensure that UART hardware flow control is valid.\r
+ * @param __CONTROL__ UART hardware flow control.\r
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)\r
+ */\r
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\\r
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \\r
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \\r
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \\r
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))\r
+\r
+/**\r
+ * @brief Ensure that UART communication mode is valid.\r
+ * @param __MODE__ UART communication mode.\r
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+ */\r
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))\r
+\r
+/**\r
+ * @brief Ensure that UART state is valid.\r
+ * @param __STATE__ UART state.\r
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)\r
+ */\r
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \\r
+ ((__STATE__) == UART_STATE_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART oversampling is valid.\r
+ * @param __SAMPLING__ UART oversampling.\r
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)\r
+ */\r
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \\r
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))\r
+\r
+/**\r
+ * @brief Ensure that UART frame sampling is valid.\r
+ * @param __ONEBIT__ UART frame sampling.\r
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)\r
+ */\r
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \\r
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART auto Baud rate detection mode is valid.\r
+ * @param __MODE__ UART auto Baud rate detection mode.\r
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \\r
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \\r
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \\r
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))\r
+\r
+/**\r
+ * @brief Ensure that UART receiver timeout setting is valid.\r
+ * @param __TIMEOUT__ UART receiver timeout setting.\r
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)\r
+ */\r
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \\r
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART LIN state is valid.\r
+ * @param __LIN__ UART LIN state.\r
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)\r
+ */\r
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \\r
+ ((__LIN__) == UART_LIN_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART LIN break detection length is valid.\r
+ * @param __LENGTH__ UART LIN break detection length.\r
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)\r
+ */\r
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \\r
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))\r
+\r
+/**\r
+ * @brief Ensure that UART DMA TX state is valid.\r
+ * @param __DMATX__ UART DMA TX state.\r
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)\r
+ */\r
+#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \\r
+ ((__DMATX__) == UART_DMA_TX_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART DMA RX state is valid.\r
+ * @param __DMARX__ UART DMA RX state.\r
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)\r
+ */\r
+#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \\r
+ ((__DMARX__) == UART_DMA_RX_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART half-duplex state is valid.\r
+ * @param __HDSEL__ UART half-duplex state.\r
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)\r
+ */\r
+#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \\r
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART wake-up method is valid.\r
+ * @param __WAKEUP__ UART wake-up method .\r
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)\r
+ */\r
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \\r
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))\r
+\r
+/**\r
+ * @brief Ensure that UART request parameter is valid.\r
+ * @param __PARAM__ UART request parameter.\r
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)\r
+ */\r
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \\r
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \\r
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \\r
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \\r
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))\r
+\r
+/**\r
+ * @brief Ensure that UART advanced features initialization is valid.\r
+ * @param __INIT__ UART advanced features initialization.\r
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \\r
+ UART_ADVFEATURE_TXINVERT_INIT | \\r
+ UART_ADVFEATURE_RXINVERT_INIT | \\r
+ UART_ADVFEATURE_DATAINVERT_INIT | \\r
+ UART_ADVFEATURE_SWAP_INIT | \\r
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\r
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \\r
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \\r
+ UART_ADVFEATURE_MSBFIRST_INIT))\r
+\r
+/**\r
+ * @brief Ensure that UART frame TX inversion setting is valid.\r
+ * @param __TXINV__ UART frame TX inversion setting.\r
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \\r
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART frame RX inversion setting is valid.\r
+ * @param __RXINV__ UART frame RX inversion setting.\r
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \\r
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART frame data inversion setting is valid.\r
+ * @param __DATAINV__ UART frame data inversion setting.\r
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \\r
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.\r
+ * @param __SWAP__ UART frame RX/TX pins swap setting.\r
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \\r
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART frame overrun setting is valid.\r
+ * @param __OVERRUN__ UART frame overrun setting.\r
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)\r
+ */\r
+#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \\r
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART auto Baud rate state is valid.\r
+ * @param __AUTOBAUDRATE__ UART auto Baud rate state.\r
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \\r
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.\r
+ * @param __DMA__ UART DMA enabling or disabling on error setting.\r
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \\r
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))\r
+\r
+/**\r
+ * @brief Ensure that UART frame MSB first setting is valid.\r
+ * @param __MSBFIRST__ UART frame MSB first setting.\r
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \\r
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART stop mode state is valid.\r
+ * @param __STOPMODE__ UART stop mode state.\r
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)\r
+ */\r
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \\r
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART mute mode state is valid.\r
+ * @param __MUTE__ UART mute mode state.\r
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)\r
+ */\r
+#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \\r
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that UART wake-up selection is valid.\r
+ * @param __WAKE__ UART wake-up selection.\r
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)\r
+ */\r
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \\r
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \\r
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))\r
+\r
+/**\r
+ * @brief Ensure that UART driver enable polarity is valid.\r
+ * @param __POLARITY__ UART driver enable polarity.\r
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)\r
+ */\r
+#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \\r
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))\r
+\r
+/**\r
+ * @brief Ensure that UART Prescaler is valid.\r
+ * @param __CLOCKPRESCALER__ UART Prescaler value.\r
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)\r
+ */\r
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \\r
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include UART HAL Extended module */\r
+#include "stm32h7xx_hal_uart_ex.h"\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup UART_Exported_Functions UART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r
+/* Transfer Abort functions */\r
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);\r
+\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral State and Errors functions **************************************************/\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions -----------------------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions UART Private Functions\r
+ * @{\r
+ */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_UART_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_uart_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of UART HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_UART_EX_H\r
+#define STM32H7xx_HAL_UART_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UARTEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART wake up from stop mode parameters\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).\r
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.\r
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must\r
+ be filled up. */\r
+\r
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.\r
+ This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */\r
+\r
+ uint8_t Address; /*!< UART/USART node address (7-bit long max). */\r
+} UART_WakeUpTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UARTEx_Word_Length UARTEx Word Length\r
+ * @{\r
+ */\r
+#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */\r
+#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */\r
+#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length\r
+ * @{\r
+ */\r
+#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */\r
+#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode\r
+ * @brief UART FIFO mode\r
+ * @{\r
+ */\r
+#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */\r
+#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level\r
+ * @brief UART TXFIFO threshold level\r
+ * @{\r
+ */\r
+#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */\r
+#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level\r
+ * @brief UART RXFIFO threshold level\r
+ * @{\r
+ */\r
+#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */\r
+#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup UARTEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+\r
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);\r
+\r
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);\r
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UARTEx_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);\r
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);\r
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Report the UART clock source.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @param __CLOCKSOURCE__ output variable.\r
+ * @retval UART clocking source, written in __CLOCKSOURCE__.\r
+ */\r
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\r
+ do { \\r
+ if((__HANDLE__)->Instance == USART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \\r
+ { \\r
+ case RCC_USART1CLKSOURCE_D2PCLK2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART2) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \\r
+ { \\r
+ case RCC_USART2CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART3) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \\r
+ { \\r
+ case RCC_USART3CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == UART4) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \\r
+ { \\r
+ case RCC_UART4CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Instance == UART5) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \\r
+ { \\r
+ case RCC_UART5CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART6) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \\r
+ { \\r
+ case RCC_USART6CLKSOURCE_D2PCLK2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == UART7) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART7_SOURCE()) \\r
+ { \\r
+ case RCC_UART7CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == UART8) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART8_SOURCE()) \\r
+ { \\r
+ case RCC_UART8CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == LPUART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \\r
+ { \\r
+ case RCC_LPUART1CLKSOURCE_D3PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \\r
+ break; \\r
+ case RCC_LPUART1CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_LPUART1CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_LPUART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_LPUART1CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_LPUART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else \\r
+ { \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \\r
+ } \\r
+ } while(0U)\r
+\r
+/** @brief Report the UART mask to apply to retrieve the received data\r
+ * according to the word length and to the parity bits activation.\r
+ * @note If PCE = 1, the parity bit is not included in the data extracted\r
+ * by the reception API().\r
+ * This masking operation is not carried out in the case of\r
+ * DMA transfers.\r
+ * @param __HANDLE__ specifies the UART Handle.\r
+ * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.\r
+ */\r
+#define UART_MASK_COMPUTATION(__HANDLE__) \\r
+ do { \\r
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x01FFU ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FFU ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FFU ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007FU ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007FU ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x003FU ; \\r
+ } \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x0000U; \\r
+ } \\r
+} while(0U)\r
+\r
+/**\r
+ * @brief Ensure that UART frame length is valid.\r
+ * @param __LENGTH__ UART frame length.\r
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)\r
+ */\r
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \\r
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \\r
+ ((__LENGTH__) == UART_WORDLENGTH_9B))\r
+\r
+/**\r
+ * @brief Ensure that UART wake-up address length is valid.\r
+ * @param __ADDRESS__ UART wake-up address length.\r
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)\r
+ */\r
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \\r
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))\r
+\r
+/**\r
+ * @brief Ensure that UART TXFIFO threshold level is valid.\r
+ * @param __THRESHOLD__ UART TXFIFO threshold level.\r
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
+ */\r
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \\r
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \\r
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \\r
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \\r
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \\r
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))\r
+\r
+/**\r
+ * @brief Ensure that UART RXFIFO threshold level is valid.\r
+ * @param __THRESHOLD__ UART RXFIFO threshold level.\r
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
+ */\r
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \\r
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \\r
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \\r
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \\r
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \\r
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_UART_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_usart.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of USART HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_USART_H\r
+#define STM32H7xx_HAL_USART_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup USART_Exported_Types USART Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief USART Init Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]\r
+ Baud Rate Register[3] = 0\r
+ Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1\r
+ where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.\r
+ @note Oversampling by 8 is systematically applied to achieve high baud rates. */\r
+\r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USARTEx_Word_Length. */\r
+\r
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits. */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+\r
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode. */\r
+\r
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity. */\r
+\r
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase. */\r
+\r
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit. */\r
+\r
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.\r
+ This parameter can be a value of @ref USART_ClockPrescaler. */\r
+} USART_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL USART State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */\r
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */\r
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */\r
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */\r
+ HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */\r
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */\r
+} HAL_USART_StateTypeDef;\r
+\r
+/**\r
+ * @brief USART clock sources definitions\r
+ */\r
+typedef enum\r
+{\r
+ USART_CLOCKSOURCE_D2PCLK1 = 0x00U, /*!< Domain2 PCLK1 clock source */\r
+ USART_CLOCKSOURCE_D2PCLK2 = 0x01U, /*!< Domain2 PCLK2 clock source */\r
+ USART_CLOCKSOURCE_PLL2 = 0x02U, /*!< PLL2Q clock source */\r
+ USART_CLOCKSOURCE_PLL3 = 0x04U, /*!< PLL3Q clock source */\r
+ USART_CLOCKSOURCE_HSI = 0x08U, /*!< HSI clock source */\r
+ USART_CLOCKSOURCE_CSI = 0x10U, /*!< CSI clock source */\r
+ USART_CLOCKSOURCE_LSE = 0x20U, /*!< LSE clock source */\r
+ USART_CLOCKSOURCE_UNDEFINED = 0x40U /*!< Undefined clock source */\r
+} USART_ClockSourceTypeDef;\r
+\r
+/**\r
+ * @brief USART handle Structure definition\r
+ */\r
+typedef struct __USART_HandleTypeDef\r
+{\r
+ USART_TypeDef *Instance; /*!< USART registers base address */\r
+\r
+ USART_InitTypeDef Init; /*!< USART communication parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */\r
+\r
+ __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */\r
+\r
+ __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */\r
+\r
+ uint16_t Mask; /*!< USART Rx RDR register mask */\r
+\r
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */\r
+\r
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */\r
+\r
+ uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value\r
+ of @ref USARTEx_Slave_Mode */\r
+\r
+ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value\r
+ of @ref USARTEx_FIFO_mode. */\r
+\r
+ void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */\r
+\r
+ void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+\r
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< USART Error code */\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */\r
+ void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */\r
+ void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */\r
+ void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */\r
+ void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */\r
+ void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */\r
+ void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */\r
+ void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */\r
+ void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */\r
+\r
+ void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */\r
+ void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+} USART_HandleTypeDef;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL USART Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */\r
+ HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */\r
+ HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */\r
+ HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */\r
+ HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */\r
+ HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */\r
+ HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */\r
+ HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */\r
+ HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */\r
+\r
+ HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */\r
+ HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */\r
+\r
+} HAL_USART_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL USART Callback pointer definition\r
+ */\r
+typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */\r
+\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup USART_Exported_Constants USART Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Error_Definition USART Error Definition\r
+ * @{\r
+ */\r
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */\r
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */\r
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */\r
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */\r
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */\r
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */\r
+#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits\r
+ * @{\r
+ */\r
+#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */\r
+#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */\r
+#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */\r
+#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Parity USART Parity\r
+ * @{\r
+ */\r
+#define USART_PARITY_NONE 0x00000000U /*!< No parity */\r
+#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */\r
+#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Mode USART Mode\r
+ * @{\r
+ */\r
+#define USART_MODE_RX USART_CR1_RE /*!< RX mode */\r
+#define USART_MODE_TX USART_CR1_TE /*!< TX mode */\r
+#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Over_Sampling USART Over Sampling\r
+ * @{\r
+ */\r
+#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */\r
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Clock USART Clock\r
+ * @{\r
+ */\r
+#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */\r
+#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Clock_Polarity USART Clock Polarity\r
+ * @{\r
+ */\r
+#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */\r
+#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Clock_Phase USART Clock Phase\r
+ * @{\r
+ */\r
+#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */\r
+#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit USART Last Bit\r
+ * @{\r
+ */\r
+#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */\r
+#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_ClockPrescaler USART Clock Prescaler\r
+ * @{\r
+ */\r
+#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */\r
+#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */\r
+#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */\r
+#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */\r
+#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */\r
+#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */\r
+#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */\r
+#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */\r
+#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */\r
+#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */\r
+#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */\r
+#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Request_Parameters USART Request Parameters\r
+ * @{\r
+ */\r
+#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */\r
+#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Flags USART Flags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the ISR register\r
+ * @{\r
+ */\r
+#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */\r
+#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */\r
+#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */\r
+#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */\r
+#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */\r
+#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */\r
+#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */\r
+#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */\r
+#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */\r
+#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */\r
+#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */\r
+#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */\r
+#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */\r
+#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */\r
+#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */\r
+#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */\r
+#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */\r
+#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition\r
+ * Elements values convention: 0000ZZZZ0XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ * @{\r
+ */\r
+\r
+#define USART_IT_PE 0x0028U /*!< USART parity error interruption */\r
+#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */\r
+#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */\r
+#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */\r
+#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */\r
+#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */\r
+#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */\r
+#define USART_IT_ERR 0x0060U /*!< USART error interruption */\r
+#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */\r
+#define USART_IT_NE 0x0200U /*!< USART noise error interruption */\r
+#define USART_IT_FE 0x0100U /*!< USART frame error interruption */\r
+#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */\r
+#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */\r
+#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */\r
+#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags\r
+ * @{\r
+ */\r
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */\r
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */\r
+#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */\r
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */\r
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */\r
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */\r
+#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */\r
+#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask\r
+ * @{\r
+ */\r
+#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */\r
+#define USART_CR_MASK 0x00E0U /*!< USART control register mask */\r
+#define USART_CR_POS 5U /*!< USART control register position */\r
+#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */\r
+#define USART_ISR_POS 8U /*!< USART ISR register position */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup USART_Exported_Macros USART Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset USART handle state.\r
+ * @param __HANDLE__ USART handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->State = HAL_USART_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0U)\r
+#else\r
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+/** @brief Check whether the specified USART flag is set or not.\r
+ * @param __HANDLE__ specifies the USART Handle\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag\r
+ * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag\r
+ * @arg @ref USART_FLAG_RXFF RXFIFO Full flag\r
+ * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag\r
+ * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag\r
+ * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag\r
+ * @arg @ref USART_FLAG_BUSY Busy flag\r
+ * @arg @ref USART_FLAG_UDR SPI slave underrun error flag\r
+ * @arg @ref USART_FLAG_TXE Transmit data register empty flag\r
+ * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag\r
+ * @arg @ref USART_FLAG_TC Transmission Complete flag\r
+ * @arg @ref USART_FLAG_RXNE Receive data register not empty flag\r
+ * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag\r
+ * @arg @ref USART_FLAG_IDLE Idle Line detection flag\r
+ * @arg @ref USART_FLAG_ORE OverRun Error flag\r
+ * @arg @ref USART_FLAG_NE Noise Error flag\r
+ * @arg @ref USART_FLAG_FE Framing Error flag\r
+ * @arg @ref USART_FLAG_PE Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the specified USART pending flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag\r
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag\r
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag\r
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag\r
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag\r
+ * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag\r
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag\r
+ * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r
+\r
+/** @brief Clear the USART PE pending flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)\r
+\r
+/** @brief Clear the USART FE pending flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)\r
+\r
+/** @brief Clear the USART NE pending flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)\r
+\r
+/** @brief Clear the USART ORE pending flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)\r
+\r
+/** @brief Clear the USART IDLE pending flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)\r
+\r
+/** @brief Clear the USART TX FIFO empty clear flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)\r
+\r
+/** @brief Clear SPI slave underrun error flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)\r
+\r
+/** @brief Enable the specified USART interrupt.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __INTERRUPT__ specifies the USART interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref USART_IT_TC Transmission complete interrupt\r
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref USART_IT_PE Parity Error interrupt\r
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))\r
+\r
+/** @brief Disable the specified USART interrupt.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __INTERRUPT__ specifies the USART interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref USART_IT_TC Transmission complete interrupt\r
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref USART_IT_PE Parity Error interrupt\r
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))\r
+\r
+\r
+/** @brief Check whether the specified USART interrupt has occurred or not.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref USART_IT_TC Transmission complete interrupt\r
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref USART_IT_ORE OverRun Error interrupt\r
+ * @arg @ref USART_IT_NE Noise Error interrupt\r
+ * @arg @ref USART_IT_FE Framing Error interrupt\r
+ * @arg @ref USART_IT_PE Parity Error interrupt\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)\r
+\r
+/** @brief Check whether the specified USART interrupt source is enabled or not.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_IT_RXFF RXFIFO Full interrupt\r
+ * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt\r
+ * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt\r
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt\r
+ * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt\r
+ * @arg @ref USART_IT_TC Transmission complete interrupt\r
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt\r
+ * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt\r
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt\r
+ * @arg @ref USART_IT_ORE OverRun Error interrupt\r
+ * @arg @ref USART_IT_NE Noise Error interrupt\r
+ * @arg @ref USART_IT_FE Framing Error interrupt\r
+ * @arg @ref USART_IT_PE Parity Error interrupt\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \\r
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \\r
+ (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)\r
+\r
+\r
+/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag\r
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag\r
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag\r
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag\r
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag\r
+ * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag\r
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))\r
+\r
+/** @brief Set a specific USART request flag.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __REQ__ specifies the request flag to set.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request\r
+ * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))\r
+\r
+/** @brief Enable the USART one bit sample method.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r
+\r
+/** @brief Disable the USART one bit sample method.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)\r
+\r
+/** @brief Enable USART.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable USART.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup USART_Private_Macros USART Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Get USART clock division factor from clock prescaler value.\r
+ * @param __CLOCKPRESCALER__ USART prescaler value.\r
+ * @retval USART clock division factor\r
+ */\r
+#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \\r
+ (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)\r
+\r
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.\r
+ * @param __PCLK__ USART clock.\r
+ * @param __BAUD__ Baud rate set by the user.\r
+ * @param __CLOCKPRESCALER__ UART prescaler value.\r
+ * @retval Division result\r
+ */\r
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))\r
+\r
+/** @brief Report the USART clock source.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @param __CLOCKSOURCE__ output variable.\r
+ * @retval the USART clocking source, written in __CLOCKSOURCE__.\r
+ */\r
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\r
+ do { \\r
+ if((__HANDLE__)->Instance == USART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \\r
+ { \\r
+ case RCC_USART1CLKSOURCE_D2PCLK2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART2) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \\r
+ { \\r
+ case RCC_USART2CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART3) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \\r
+ { \\r
+ case RCC_USART3CLKSOURCE_D2PCLK1: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART6) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \\r
+ { \\r
+ case RCC_USART6CLKSOURCE_D2PCLK2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_PLL2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_PLL3: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_CSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \\r
+ break; \\r
+ } \\r
+ } \\r
+ else \\r
+ { \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \\r
+ } \\r
+ } while(0U)\r
+\r
+/** @brief Check USART Baud rate.\r
+ * @param __BAUDRATE__ Baudrate specified by the user.\r
+ * The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)\r
+ * divided by the smallest oversampling used on the USART (i.e. 8)\r
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */\r
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)\r
+\r
+/**\r
+ * @brief Ensure that USART frame number of stop bits is valid.\r
+ * @param __STOPBITS__ USART frame number of stop bits.\r
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)\r
+ */\r
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \\r
+ ((__STOPBITS__) == USART_STOPBITS_1) || \\r
+ ((__STOPBITS__) == USART_STOPBITS_1_5) || \\r
+ ((__STOPBITS__) == USART_STOPBITS_2))\r
+\r
+/**\r
+ * @brief Ensure that USART frame parity is valid.\r
+ * @param __PARITY__ USART frame parity.\r
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)\r
+ */\r
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \\r
+ ((__PARITY__) == USART_PARITY_EVEN) || \\r
+ ((__PARITY__) == USART_PARITY_ODD))\r
+\r
+/**\r
+ * @brief Ensure that USART communication mode is valid.\r
+ * @param __MODE__ USART communication mode.\r
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r
+ */\r
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))\r
+\r
+/**\r
+ * @brief Ensure that USART oversampling is valid.\r
+ * @param __SAMPLING__ USART oversampling.\r
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)\r
+ */\r
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \\r
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))\r
+\r
+/**\r
+ * @brief Ensure that USART clock state is valid.\r
+ * @param __CLOCK__ USART clock state.\r
+ * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)\r
+ */\r
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \\r
+ ((__CLOCK__) == USART_CLOCK_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that USART frame polarity is valid.\r
+ * @param __CPOL__ USART frame polarity.\r
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)\r
+ */\r
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))\r
+\r
+/**\r
+ * @brief Ensure that USART frame phase is valid.\r
+ * @param __CPHA__ USART frame phase.\r
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)\r
+ */\r
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))\r
+\r
+/**\r
+ * @brief Ensure that USART frame last bit clock pulse setting is valid.\r
+ * @param __LASTBIT__ USART frame last bit clock pulse setting.\r
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)\r
+ */\r
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \\r
+ ((__LASTBIT__) == USART_LASTBIT_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that USART request parameter is valid.\r
+ * @param __PARAM__ USART request parameter.\r
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)\r
+ */\r
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \\r
+ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))\r
+\r
+/**\r
+ * @brief Ensure that USART Prescaler is valid.\r
+ * @param __CLOCKPRESCALER__ USART Prescaler value.\r
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)\r
+ */\r
+#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \\r
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include USART HAL Extended module */\r
+#include "stm32h7xx_hal_usart_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup USART_Exported_Functions USART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);\r
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);\r
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);\r
+/* Transfer Abort functions */\r
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);\r
+\r
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);\r
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);\r
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_USART_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_usart_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of USART HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_HAL_USART_EX_H\r
+#define STM32H7xx_HAL_USART_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USARTEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USARTEx_Word_Length USARTEx Word Length\r
+ * @{\r
+ */\r
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */\r
+#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */\r
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management\r
+ * @{\r
+ */\r
+#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */\r
+#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable\r
+ * @brief USART SLAVE mode\r
+ * @{\r
+ */\r
+#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */\r
+#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode\r
+ * @brief USART FIFO mode\r
+ * @{\r
+ */\r
+#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */\r
+#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level\r
+ * @brief USART TXFIFO level\r
+ * @{\r
+ */\r
+#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */\r
+#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */\r
+#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */\r
+#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */\r
+#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */\r
+#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level\r
+ * @brief USART RXFIFO level\r
+ * @{\r
+ */\r
+#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */\r
+#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */\r
+#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */\r
+#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */\r
+#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */\r
+#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Compute the USART mask to apply to retrieve the received data\r
+ * according to the word length and to the parity bits activation.\r
+ * @note If PCE = 1, the parity bit is not included in the data extracted\r
+ * by the reception API().\r
+ * This masking operation is not carried out in the case of\r
+ * DMA transfers.\r
+ * @param __HANDLE__ specifies the USART Handle.\r
+ * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.\r
+ */\r
+#define USART_MASK_COMPUTATION(__HANDLE__) \\r
+ do { \\r
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x01FFU; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FFU; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FFU; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007FU; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007FU; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x003FU; \\r
+ } \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x0000U; \\r
+ } \\r
+} while(0U)\r
+\r
+\r
+/**\r
+ * @brief Ensure that USART frame length is valid.\r
+ * @param __LENGTH__ USART frame length.\r
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)\r
+ */\r
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \\r
+ ((__LENGTH__) == USART_WORDLENGTH_8B) || \\r
+ ((__LENGTH__) == USART_WORDLENGTH_9B))\r
+\r
+/**\r
+ * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.\r
+ * @param __NSS__ USART Negative Slave Select pin management.\r
+ * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)\r
+ */\r
+#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \\r
+ ((__NSS__) == USART_NSS_SOFT))\r
+\r
+/**\r
+ * @brief Ensure that USART Slave Mode is valid.\r
+ * @param __STATE__ USART Slave Mode.\r
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)\r
+ */\r
+#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \\r
+ ((__STATE__) == USART_SLAVEMODE_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that USART FIFO mode is valid.\r
+ * @param __STATE__ USART FIFO mode.\r
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)\r
+ */\r
+#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \\r
+ ((__STATE__) == USART_FIFOMODE_ENABLE))\r
+\r
+/**\r
+ * @brief Ensure that USART TXFIFO threshold level is valid.\r
+ * @param __THRESHOLD__ USART TXFIFO threshold level.\r
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
+ */\r
+#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \\r
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \\r
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \\r
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \\r
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \\r
+ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))\r
+\r
+/**\r
+ * @brief Ensure that USART RXFIFO threshold level is valid.\r
+ * @param __THRESHOLD__ USART RXFIFO threshold level.\r
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)\r
+ */\r
+#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \\r
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \\r
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \\r
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \\r
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \\r
+ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup USARTEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USARTEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);\r
+void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup USARTEx_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);\r
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);\r
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_HAL_USART_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_ll_adc.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of ADC LL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32H7xx_LL_ADC_H\r
+#define STM32H7xx_LL_ADC_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx.h"\r
+\r
+/** @addtogroup STM32H7xx_LL_Driver\r
+ * @{\r
+ */\r
+\r
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)\r
+\r
+/** @defgroup ADC_LL ADC\r
+ * @{\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants\r
+ * @{\r
+ */\r
+\r
+/* Internal mask for ADC calibration: */\r
+/* Internal register offset for ADC calibration factors configuration */\r
+\r
+/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */\r
+/* the relevant bits for: */\r
+/* (concatenation of multiple bits used in different registers) */\r
+/* - ADC calibration configuration: configuration before calibration start */\r
+/* - ADC calibration factors: register offset */\r
+#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */\r
+#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */\r
+#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)\r
+#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)\r
+#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */\r
+\r
+\r
+/* Internal mask for ADC group regular sequencer: */\r
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */\r
+/* - sequencer register offset */\r
+/* - sequencer rank bits position into the selected register */\r
+\r
+/* Internal register offset for ADC group regular sequencer configuration */\r
+/* (offset placed into a spare area of literal definition) */\r
+#define ADC_SQR1_REGOFFSET (0x00000000UL)\r
+#define ADC_SQR2_REGOFFSET (0x00000100UL)\r
+#define ADC_SQR3_REGOFFSET (0x00000200UL)\r
+#define ADC_SQR4_REGOFFSET (0x00000300UL)\r
+\r
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)\r
+#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */\r
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)\r
+\r
+/* Definition of ADC group regular sequencer bits information to be inserted */\r
+/* into ADC group regular sequencer ranks literals definition. */\r
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */\r
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */\r
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */\r
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */\r
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */\r
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */\r
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */\r
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */\r
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */\r
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */\r
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */\r
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */\r
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */\r
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */\r
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */\r
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */\r
+\r
+\r
+\r
+/* Internal mask for ADC group injected sequencer: */\r
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */\r
+/* - data register offset */\r
+/* - sequencer rank bits position into the selected register */\r
+\r
+/* Internal register offset for ADC group injected data register */\r
+/* (offset placed into a spare area of literal definition) */\r
+#define ADC_JDR1_REGOFFSET (0x00000000UL)\r
+#define ADC_JDR2_REGOFFSET (0x00000100UL)\r
+#define ADC_JDR3_REGOFFSET (0x00000200UL)\r
+#define ADC_JDR4_REGOFFSET (0x00000300UL)\r
+\r
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)\r
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)\r
+#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */\r
+\r
+/* Definition of ADC group injected sequencer bits information to be inserted */\r
+/* into ADC group injected sequencer ranks literals definition. */\r
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)\r
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)\r
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)\r
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)\r
+\r
+\r
+\r
+/* Internal mask for ADC group regular trigger: */\r
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */\r
+/* - regular trigger source */\r
+/* - regular trigger edge */\r
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */\r
+\r
+/* Mask containing trigger source masks for each of possible */\r
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */\r
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */\r
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \\r
+ ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \\r
+ ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \\r
+ ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )\r
+\r
+/* Mask containing trigger edge masks for each of possible */\r
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */\r
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */\r
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \\r
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \\r
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \\r
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )\r
+\r
+/* Definition of ADC group regular trigger bits information. */\r
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */\r
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */\r
+\r
+\r
+\r
+/* Internal mask for ADC group injected trigger: */\r
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */\r
+/* - injected trigger source */\r
+/* - injected trigger edge */\r
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */\r
+\r
+/* Mask containing trigger source masks for each of possible */\r
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */\r
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */\r
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \\r
+ ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \\r
+ ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \\r
+ ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )\r
+\r
+/* Mask containing trigger edge masks for each of possible */\r
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */\r
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */\r
+#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \\r
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \\r
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \\r
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )\r
+\r
+/* Definition of ADC group injected trigger bits information. */\r
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */\r
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */\r
+\r
+\r
+\r
+\r
+\r
+\r
+/* Internal mask for ADC channel: */\r
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */\r
+/* - channel identifier defined by number */\r
+/* - channel identifier defined by bitfield */\r
+/* - channel differentiation between external channels (connected to */\r
+/* GPIO pins) and internal channels (connected to internal paths) */\r
+/* - channel sampling time defined by SMPRx register offset */\r
+/* and SMPx bits positions into SMPRx register */\r
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)\r
+#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)\r
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */\r
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)\r
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */\r
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */\r
+\r
+/* Channel differentiation between external and internal channels */\r
+#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */\r
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)\r
+\r
+/* Internal register offset for ADC channel sampling time configuration */\r
+/* (offset placed into a spare area of literal definition) */\r
+#define ADC_SMPR1_REGOFFSET (0x00000000UL)\r
+#define ADC_SMPR2_REGOFFSET (0x02000000UL)\r
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)\r
+#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */\r
+\r
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)\r
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */\r
+\r
+/* Definition of channels ID number information to be inserted into */\r
+/* channels literals definition. */\r
+#define ADC_CHANNEL_0_NUMBER (0x00000000UL)\r
+#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )\r
+#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )\r
+#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )\r
+#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )\r
+#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )\r
+#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )\r
+#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )\r
+#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )\r
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)\r
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )\r
+#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\r
+\r
+/* Definition of channels ID bitfield information to be inserted into */\r
+/* channels literals definition. */\r
+#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)\r
+#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)\r
+#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)\r
+#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)\r
+#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)\r
+#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)\r
+#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)\r
+#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)\r
+#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)\r
+#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)\r
+#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)\r
+#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)\r
+#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)\r
+#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)\r
+#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)\r
+#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)\r
+#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)\r
+#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)\r
+#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)\r
+#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)\r
+\r
+/* Definition of channels sampling time information to be inserted into */\r
+/* channels literals definition. */\r
+#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */\r
+#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */\r
+#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */\r
+#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */\r
+#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */\r
+#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */\r
+#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */\r
+#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */\r
+#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */\r
+#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */\r
+#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */\r
+#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */\r
+#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */\r
+#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */\r
+#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */\r
+#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */\r
+#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */\r
+#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */\r
+#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */\r
+#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */\r
+\r
+\r
+/* Internal mask for ADC mode single or differential ended: */\r
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */\r
+/* the relevant bits for: */\r
+/* (concatenation of multiple bits used in different registers) */\r
+/* - ADC calibration: calibration start, calibration factor get or set */\r
+/* - ADC channels: set each ADC channel ending mode */\r
+#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)\r
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)\r
+#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */\r
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */\r
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */\r
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */\r
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */\r
+\r
+/* Internal mask for ADC analog watchdog: */\r
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */\r
+/* (concatenation of multiple bits used in different analog watchdogs, */\r
+/* (feature of several watchdogs not available on all STM32 families)). */\r
+/* - analog watchdog 1: monitored channel defined by number, */\r
+/* selection of ADC group (ADC groups regular and-or injected). */\r
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */\r
+/* selection on groups. */\r
+\r
+/* Internal register offset for ADC analog watchdog channel configuration */\r
+#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)\r
+#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)\r
+#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)\r
+\r
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */\r
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */\r
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)\r
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)\r
+\r
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)\r
+\r
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)\r
+#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)\r
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)\r
+\r
+#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */\r
+\r
+/* Internal register offset for ADC analog watchdog threshold configuration */\r
+#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)\r
+#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)\r
+#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)\r
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)\r
+#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */\r
+\r
+/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */\r
+/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */\r
+#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)\r
+#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)\r
+\r
+/* Legacy literals */\r
+#define LL_ADC_AWD1_TR LL_ADC_AWD1\r
+#define LL_ADC_AWD2_TR LL_ADC_AWD2\r
+#define LL_ADC_AWD3_TR LL_ADC_AWD3\r
+\r
+/* Internal mask for ADC offset: */\r
+/* Internal register offset for ADC offset number configuration */\r
+#define ADC_OFR1_REGOFFSET (0x00000000UL)\r
+#define ADC_OFR2_REGOFFSET (0x00000001UL)\r
+#define ADC_OFR3_REGOFFSET (0x00000002UL)\r
+#define ADC_OFR4_REGOFFSET (0x00000003UL)\r
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)\r
+\r
+\r
+/* ADC registers bits positions */\r
+#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)\r
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)\r
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)\r
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)\r
+\r
+\r
+/* ADC registers bits groups */\r
+#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */\r
+\r
+\r
+/* ADC internal channels related definitions */\r
+/* Internal voltage reference VrefInt */\r
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\r
+#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */\r
+/* Temperature sensor */\r
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\r
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\r
+#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */\r
+#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */\r
+#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Driver macro reserved for internal use: set a pointer to\r
+ * a register from a register basis from which an offset\r
+ * is applied.\r
+ * @param __REG__ Register basis from which the offset is applied.\r
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).\r
+ * @retval Pointer to register address\r
+ */\r
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \\r
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+#if defined(USE_FULL_LL_DRIVER)\r
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Structure definition of some features of ADC common parameters\r
+ * and multimode\r
+ * (all ADC instances belonging to the same ADC common instance).\r
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()\r
+ * is conditioned to ADC instances state (all ADC instances\r
+ * sharing the same ADC common instance):\r
+ * All ADC instances sharing the same ADC common instance must be\r
+ * disabled.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.\r
+ This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE\r
+ @note On this STM32 serie, if ADC group injected is used, some\r
+ clock ratio constraints between ADC clock and AHB clock\r
+ must be respected. Refer to reference manual.\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */\r
+\r
+ uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).\r
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */\r
+\r
+ uint32_t MultiDMATransfer; /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.\r
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */\r
+\r
+ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.\r
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */\r
+\r
+} LL_ADC_CommonInitTypeDef;\r
+\r
+/**\r
+ * @brief Structure definition of some features of ADC instance.\r
+ * @note These parameters have an impact on ADC scope: ADC instance.\r
+ * Affects both group regular and group injected (availability\r
+ * of ADC group injected depends on STM32 families).\r
+ * Refer to corresponding unitary functions into\r
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .\r
+ * @note The setting of these parameters by function @ref LL_ADC_Init()\r
+ * is conditioned to ADC state:\r
+ * ADC instance must be disabled.\r
+ * This condition is applied to all ADC features, for efficiency\r
+ * and compatibility over all STM32 families. However, the different\r
+ * features can be set under different ADC state conditions\r
+ * (setting possible with ADC enabled without conversion on going,\r
+ * ADC enabled with conversion on going, ...)\r
+ * Each feature can be updated afterwards with a unitary function\r
+ * and potentially with ADC in a different state than disabled,\r
+ * refer to description of each function for setting\r
+ * conditioned to ADC state.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Resolution; /*!< Set ADC resolution.\r
+ This parameter can be a value of @ref ADC_LL_EC_RESOLUTION\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */\r
+\r
+ uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.\r
+ This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */\r
+\r
+ uint32_t LowPowerMode; /*!< Set ADC low power mode.\r
+ This parameter can be a value of @ref ADC_LL_EC_LP_MODE\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */\r
+\r
+} LL_ADC_InitTypeDef;\r
+\r
+/**\r
+ * @brief Structure definition of some features of ADC group regular.\r
+ * @note These parameters have an impact on ADC scope: ADC group regular.\r
+ * Refer to corresponding unitary functions into\r
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular\r
+ * (functions with prefix "REG").\r
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()\r
+ * is conditioned to ADC state:\r
+ * ADC instance must be disabled.\r
+ * This condition is applied to all ADC features, for efficiency\r
+ * and compatibility over all STM32 families. However, the different\r
+ * features can be set under different ADC state conditions\r
+ * (setting possible with ADC enabled without conversion on going,\r
+ * ADC enabled with conversion on going, ...)\r
+ * Each feature can be updated afterwards with a unitary function\r
+ * and potentially with ADC in a different state than disabled,\r
+ * refer to description of each function for setting\r
+ * conditioned to ADC state.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).\r
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE\r
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge\r
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).\r
+ In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */\r
+\r
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.\r
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */\r
+\r
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.\r
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE\r
+ @note This parameter has an effect only if group regular sequencer is enabled\r
+ (scan length of 2 ranks or more).\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */\r
+\r
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).\r
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE\r
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */\r
+\r
+ uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.\r
+ This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */\r
+\r
+ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:\r
+ data preserved or overwritten.\r
+ This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */\r
+\r
+} LL_ADC_REG_InitTypeDef;\r
+\r
+/**\r
+ * @brief Structure definition of some features of ADC group injected.\r
+ * @note These parameters have an impact on ADC scope: ADC group injected.\r
+ * Refer to corresponding unitary functions into\r
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular\r
+ * (functions with prefix "INJ").\r
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()\r
+ * is conditioned to ADC state:\r
+ * ADC instance must be disabled.\r
+ * This condition is applied to all ADC features, for efficiency\r
+ * and compatibility over all STM32 families. However, the different\r
+ * features can be set under different ADC state conditions\r
+ * (setting possible with ADC enabled without conversion on going,\r
+ * ADC enabled with conversion on going, ...)\r
+ * Each feature can be updated afterwards with a unitary function\r
+ * and potentially with ADC in a different state than disabled,\r
+ * refer to description of each function for setting\r
+ * conditioned to ADC state.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).\r
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE\r
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge\r
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).\r
+ In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */\r
+\r
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.\r
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */\r
+\r
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.\r
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE\r
+ @note This parameter has an effect only if group injected sequencer is enabled\r
+ (scan length of 2 ranks or more).\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */\r
+\r
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.\r
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO\r
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.\r
+\r
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */\r
+\r
+} LL_ADC_INJ_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* USE_FULL_LL_DRIVER */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_FLAG ADC flags\r
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function\r
+ * @{\r
+ */\r
+#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */\r
+#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */\r
+#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */\r
+#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */\r
+#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */\r
+#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */\r
+#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */\r
+#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */\r
+#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */\r
+#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */\r
+#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */\r
+#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */\r
+#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */\r
+#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */\r
+#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */\r
+#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */\r
+#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */\r
+#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */\r
+#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */\r
+#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */\r
+#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */\r
+#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */\r
+#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */\r
+#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */\r
+#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */\r
+#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */\r
+#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */\r
+#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */\r
+#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */\r
+#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */\r
+#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */\r
+#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */\r
+#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)\r
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions\r
+ * @{\r
+ */\r
+#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */\r
+#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */\r
+#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */\r
+#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */\r
+#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */\r
+#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */\r
+#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */\r
+#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */\r
+#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */\r
+#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */\r
+#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose\r
+ * @{\r
+ */\r
+/* List of ADC registers intended to be used (most commonly) with */\r
+/* DMA transfer. */\r
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */\r
+#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */\r
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source\r
+ * @{\r
+ */\r
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */\r
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */\r
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */\r
+#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */\r
+#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels\r
+ * @{\r
+ */\r
+/* Note: Other measurement paths to internal channels may be available */\r
+/* (connections to other peripherals). */\r
+/* If they are not listed below, they do not require any specific */\r
+/* path enable. In this case, Access to measurement path is done */\r
+/* only by selecting the corresponding ADC internal channel. */\r
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */\r
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */\r
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */\r
+#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode\r
+ * @{\r
+ */\r
+#define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL) /*!< Boost mode is configured for frequency <= 6.25Mhz */\r
+#define LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0) /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */\r
+#define LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz */\r
+#define LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 20Mhz < frequency <= 25Mhz */\r
+#define LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0) /*!< Boost mode is configured for frequency > 25Mhz */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity\r
+ * @{\r
+ */\r
+#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */\r
+#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET) /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */\r
+#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD ADC instance - Calibration linearity words\r
+ * @{\r
+ */\r
+#define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1) /*!< ADC calibration linearity word 1 */\r
+#define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2) /*!< ADC calibration linearity word 2 */\r
+#define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3) /*!< ADC calibration linearity word 3 */\r
+#define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4) /*!< ADC calibration linearity word 4 */\r
+#define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5) /*!< ADC calibration linearity word 5 */\r
+#define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6) /*!< ADC calibration linearity word 6 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution\r
+ * @{\r
+ */\r
+#define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */\r
+#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */\r
+#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits */\r
+#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */\r
+#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift\r
+ * @{\r
+ */\r
+#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC convesion data */\r
+#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC convesion data */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode\r
+ * @{\r
+ */\r
+#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */\r
+#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number\r
+ * @{\r
+ */\r
+#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode\r
+ * @{\r
+ */\r
+#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */\r
+#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift\r
+ * @{\r
+ */\r
+#define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */\r
+#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups\r
+ * @{\r
+ */\r
+#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */\r
+#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/\r
+#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number\r
+ * @{\r
+ */\r
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */\r
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */\r
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */\r
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */\r
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */\r
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */\r
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */\r
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */\r
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */\r
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */\r
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */\r
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */\r
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */\r
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */\r
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */\r
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */\r
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */\r
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */\r
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */\r
+#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */\r
+/*!< ADC3 is defined only in the case of STM32H7XX */\r
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */\r
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */\r
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */\r
+#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */\r
+#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source\r
+ * @{\r
+ */\r
+#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */\r
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge\r
+ * @{\r
+ */\r
+#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */\r
+#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */\r
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode\r
+* @{\r
+*/\r
+#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */\r
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data\r
+ * @{\r
+ */\r
+#define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */\r
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */\r
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */\r
+#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data\r
+* @{\r
+*/\r
+#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */\r
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length\r
+ * @{\r
+ */\r
+#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */\r
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode\r
+ * @{\r
+ */\r
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */\r
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */\r
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */\r
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */\r
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */\r
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */\r
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */\r
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */\r
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks\r
+ * @{\r
+ */\r
+#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */\r
+#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */\r
+#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */\r
+#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */\r
+#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */\r
+#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */\r
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */\r
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */\r
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */\r
+#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */\r
+#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */\r
+#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */\r
+#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */\r
+#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */\r
+#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */\r
+#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source\r
+ * @{\r
+ */\r
+#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */\r
+#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge\r
+ * @{\r
+ */\r
+#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */\r
+#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */\r
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode\r
+* @{\r
+*/\r
+#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */\r
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode\r
+ * @{\r
+ */\r
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */\r
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */\r
+#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length\r
+ * @{\r
+ */\r
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */\r
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */\r
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */\r
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode\r
+ * @{\r
+ */\r
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */\r
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks\r
+ * @{\r
+ */\r
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */\r
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */\r
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */\r
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time\r
+ * @{\r
+ */\r
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycles */\r
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */\r
+#define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 8.5 ADC clock cycles */\r
+#define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */\r
+#define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 32.5 ADC clock cycles */\r
+#define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */\r
+#define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 387.5 ADC clock cycles */\r
+#define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending\r
+ * @{\r
+ */\r
+#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */\r
+#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */\r
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number\r
+ * @{\r
+ */\r
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */\r
+#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */\r
+#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels\r
+ * @{\r
+ */\r
+#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */\r
+#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */\r
+#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */\r
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */\r
+#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */\r
+#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */\r
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */\r
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */\r
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */\r
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */\r
+#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */\r
+#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */\r
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */\r
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */\r
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */\r
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */\r
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */\r
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds\r
+ * @{\r
+ */\r
+#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */\r
+#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope\r
+ * @{\r
+ */\r
+#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */\r
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */\r
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */\r
+#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */\r
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode\r
+ * @{\r
+ */\r
+#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */\r
+#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift\r
+ * @{\r
+ */\r
+#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */\r
+#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode\r
+ * @{\r
+ */\r
+#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */\r
+#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */\r
+#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */\r
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */\r
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */\r
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */\r
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */\r
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer\r
+ * @{\r
+ */\r
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */\r
+#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */\r
+#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases\r
+ * @{\r
+ */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution */\r
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave\r
+ * @{\r
+ */\r
+#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */\r
+#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */\r
+#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays\r
+ * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,\r
+ * not timeout values.\r
+ * For details on delays values, refer to descriptions in source code\r
+ * above each literal definition.\r
+ * @{\r
+ */\r
+\r
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */\r
+/* not timeout values. */\r
+/* Timeout values for ADC operations are dependent to device clock */\r
+/* configuration (system clock versus ADC clock), */\r
+/* and therefore must be defined in user application. */\r
+/* Indications for estimation of ADC timeout delays, for this */\r
+/* STM32 serie: */\r
+/* - ADC calibration time: maximum delay is 16384/fADC. */\r
+/* (refer to device datasheet, parameter "tCAL") */\r
+/* - ADC enable time: maximum delay is 1 conversion cycle. */\r
+/* (refer to device datasheet, parameter "tSTAB") */\r
+/* - ADC disable time: maximum delay should be a few ADC clock cycles */\r
+/* - ADC stop conversion time: maximum delay should be a few ADC clock */\r
+/* cycles */\r
+/* - ADC conversion time: duration depending on ADC clock and ADC */\r
+/* configuration. */\r
+/* (refer to device reference manual, section "Timing") */\r
+\r
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */\r
+/* Delay set to maximum value (refer to device datasheet, */\r
+/* parameter "tADCVREG_STUP"). */\r
+/* Unit: us */\r
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */\r
+\r
+/* Delay for internal voltage reference stabilization time. */\r
+/* Delay set to maximum value (refer to device datasheet, */\r
+/* parameter "ts_vrefint"). */\r
+/* Unit: us */\r
+#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */\r
+\r
+/* Delay for temperature sensor stabilization time. */\r
+/* Literal set to maximum value (refer to device datasheet, */\r
+/* parameter "tSTART_RUN"). */\r
+/* Unit: us */\r
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */\r
+\r
+/* Delay required between ADC end of calibration and ADC enable. */\r
+/* Note: On this STM32 serie, a minimum number of ADC clock cycles */\r
+/* are required between ADC end of calibration and ADC enable. */\r
+/* Wait time can be computed in user application by waiting for the */\r
+/* equivalent number of CPU cycles, by taking into account */\r
+/* ratio of CPU clock versus ADC clock prescalers. */\r
+/* Unit: ADC clock cycles. */\r
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */\r
+\r
+/* Fixed timeout value for ADC linearity word bit set/clear delay. */\r
+/* Values defined to be higher than worst cases: low clock frequency, */\r
+/* maximum prescalers. */\r
+/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */\r
+/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */\r
+/* 6 / 4577 = 1,311ms */\r
+/* At maximum CPU speed (400 MHz), this means */\r
+/* 3.58 * 400 MHz = 524400 CPU cycles */\r
+#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Write a value in ADC register\r
+ * @param __INSTANCE__ ADC Instance\r
+ * @param __REG__ Register to be written\r
+ * @param __VALUE__ Value to be written in the register\r
+ * @retval None\r
+ */\r
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\r
+\r
+/**\r
+ * @brief Read a value in ADC register\r
+ * @param __INSTANCE__ ADC Instance\r
+ * @param __REG__ Register to be read\r
+ * @retval Register value\r
+ */\r
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Helper macro to get ADC channel number in decimal format\r
+ * from literals LL_ADC_CHANNEL_x.\r
+ * @note Example:\r
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)\r
+ * will return decimal number "4".\r
+ * @note The input can be a value from functions where a channel\r
+ * number is returned, either defined with number\r
+ * or with bitfield (only one bit must be set).\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval Value between Min_Data=0 and Max_Data=18\r
+ */\r
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \\r
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \\r
+ ? ( \\r
+ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \\r
+ ) \\r
+ : \\r
+ ( \\r
+ (uint32_t)POSITION_VAL((__CHANNEL__)) \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x\r
+ * from number in decimal format.\r
+ * @note Example:\r
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)\r
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".\r
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n\r
+ * (1, 2) For ADC channel read back from ADC register,\r
+ * comparison with internal channel parameter to be done\r
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\r
+ */\r
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \\r
+ (((__DECIMAL_NB__) <= 9UL) \\r
+ ? ( \\r
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \\r
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \\r
+ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \\r
+ ) \\r
+ : \\r
+ ( \\r
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \\r
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \\r
+ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to determine whether the selected channel\r
+ * corresponds to literal definitions of driver.\r
+ * @note The different literal definitions of ADC channels are:\r
+ * - ADC internal channel:\r
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...\r
+ * - ADC external channel (channel connected to a GPIO pin):\r
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...\r
+ * @note The channel parameter must be a value defined from literal\r
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\r
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),\r
+ * must not be a value from functions where a channel number is\r
+ * returned from ADC registers,\r
+ * because internal and external channels share the same channel\r
+ * number in ADC registers. The differentiation is made only with\r
+ * parameters definitions of driver.\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).\r
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.\r
+ */\r
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \\r
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)\r
+\r
+/**\r
+ * @brief Helper macro to convert a channel defined from parameter\r
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\r
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * to its equivalent parameter definition of a ADC external channel\r
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).\r
+ * @note The channel parameter can be, additionally to a value\r
+ * defined from parameter definition of a ADC internal channel\r
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * a value defined from parameter definition of\r
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)\r
+ * or a value from functions where a channel number is returned\r
+ * from ADC registers.\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0\r
+ * @arg @ref LL_ADC_CHANNEL_1\r
+ * @arg @ref LL_ADC_CHANNEL_2\r
+ * @arg @ref LL_ADC_CHANNEL_3\r
+ * @arg @ref LL_ADC_CHANNEL_4\r
+ * @arg @ref LL_ADC_CHANNEL_5\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ */\r
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \\r
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)\r
+\r
+/**\r
+ * @brief Helper macro to determine whether the internal channel\r
+ * selected is available on the ADC instance selected.\r
+ * @note The channel parameter must be a value defined from parameter\r
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\r
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),\r
+ * must not be a value defined from parameter definition of\r
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)\r
+ * or a value from functions where a channel number is\r
+ * returned from ADC registers,\r
+ * because internal and external channels share the same channel\r
+ * number in ADC registers. The differentiation is made only with\r
+ * parameters definitions of driver.\r
+ * @param __ADC_INSTANCE__ ADC instance\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\r
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.\r
+ * Value "1" if the internal channel selected is available on the ADC instance selected.\r
+ */\r
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \\r
+ ((((__ADC_INSTANCE__) == ADC2) \\r
+ &&( \\r
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \\r
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \\r
+ ) \\r
+ ) \\r
+ || \\r
+ (((__ADC_INSTANCE__) == ADC3) \\r
+ &&( \\r
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \\r
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \\r
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \\r
+ ) \\r
+ ) \\r
+ )\r
+/**\r
+ * @brief Helper macro to define ADC analog watchdog parameter:\r
+ * define a single channel to monitor with analog watchdog\r
+ * from sequencer channel and groups definition.\r
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().\r
+ * Example:\r
+ * LL_ADC_SetAnalogWDMonitChannels(\r
+ * ADC1, LL_ADC_AWD1,\r
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))\r
+ * @param __CHANNEL__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n\r
+ * (1, 2) For ADC channel read back from ADC register,\r
+ * comparison with internal channel parameter to be done\r
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\r
+ * @param __GROUP__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_GROUP_REGULAR\r
+ * @arg @ref LL_ADC_GROUP_INJECTED\r
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD_DISABLE\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)\r
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)\r
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)\r
+ * \r
+ * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n\r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\r
+ */\r
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \\r
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \\r
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \\r
+ : \\r
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \\r
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \\r
+ : \\r
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high\r
+ * or low in function of ADC resolution, when ADC resolution is\r
+ * different of 16 bits.\r
+ * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().\r
+ * Example, with a ADC resolution of 8 bits, to set the value of\r
+ * analog watchdog threshold high (on 18 bits):\r
+ * LL_ADC_SetAnalogWDThresholds\r
+ * (< ADCx param >,\r
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)\r
+ * );\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF\r
+ * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF\r
+ */\r
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \\r
+ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))\r
+\r
+/**\r
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high\r
+ * or low in function of ADC resolution, when ADC resolution is\r
+ * different of 16 bits.\r
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().\r
+ * Example, with a ADC resolution of 8 bits, to get the value of\r
+ * analog watchdog threshold high (on 18 bits):\r
+ * < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION\r
+ * (LL_ADC_RESOLUTION_8B,\r
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)\r
+ * );\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @param __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF\r
+ * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF\r
+ */\r
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \\r
+ ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))\r
+\r
+/**\r
+ * @brief Helper macro to set the ADC calibration value with both single ended\r
+ * and differential modes calibration factors concatenated.\r
+ * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().\r
+ * Example, to set calibration factors single ended to 0x55\r
+ * and differential ended to 0x2A:\r
+ * LL_ADC_SetCalibrationOffsetFactor(\r
+ * ADC1,\r
+ * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))\r
+ * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F\r
+ * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F\r
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\r
+ */\r
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \\r
+ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))\r
+\r
+/**\r
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master\r
+ * or ADC slave from raw value with both ADC conversion data concatenated.\r
+ * @note This macro is intended to be used when multimode transfer by DMA\r
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().\r
+ * In this case the transferred data need to processed with this macro\r
+ * to separate the conversion data of ADC master and ADC slave.\r
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_MASTER\r
+ * @arg @ref LL_ADC_MULTI_SLAVE\r
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\r
+ */\r
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \\r
+ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)\r
+\r
+/**\r
+ * @brief Helper macro to select, from a ADC instance, to which ADC instance\r
+ * it has a dependence in multimode (ADC master of the corresponding\r
+ * ADC common instance).\r
+ * @note In case of device with multimode available and a mix of\r
+ * ADC instances compliant and not compliant with multimode feature,\r
+ * ADC instances not compliant with multimode feature are\r
+ * considered as master instances (do not depend to\r
+ * any other ADC instance).\r
+ * @param __ADCx__ ADC instance\r
+ * @retval __ADCx__ ADC instance master of the corresponding ADC common instance\r
+ */\r
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \\r
+ ( ( ((__ADCx__) == ADC2) \\r
+ )? \\r
+ (ADC1) \\r
+ : \\r
+ (__ADCx__) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to select the ADC common instance\r
+ * to which is belonging the selected ADC instance.\r
+ * @note ADC common register instance can be used for:\r
+ * - Set parameters common to several ADC instances\r
+ * - Multimode (for devices with several ADC instances)\r
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.\r
+ * @param __ADCx__ ADC instance\r
+ * @retval ADC common register instance\r
+ */\r
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \\r
+ ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \\r
+ ? ( \\r
+ (ADC12_COMMON) \\r
+ ) \\r
+ : \\r
+ ( \\r
+ (ADC3_COMMON) \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to check if all ADC instances sharing the same\r
+ * ADC common instance are disabled.\r
+ * @note This check is required by functions with setting conditioned to\r
+ * ADC state:\r
+ * All ADC instances of the ADC common group must be disabled.\r
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.\r
+ * @note On devices with only 1 ADC common instance, parameter of this macro\r
+ * is useless and can be ignored (parameter kept for compatibility\r
+ * with devices featuring several ADC common instances).\r
+ * @param __ADCXY_COMMON__ ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance\r
+ * are disabled.\r
+ * Value "1" if at least one ADC instance sharing the same ADC common instance\r
+ * is enabled.\r
+ */\r
+#if defined(ADC3_COMMON)\r
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \\r
+ (((__ADCXY_COMMON__) == ADC12_COMMON) \\r
+ ? ( \\r
+ (LL_ADC_IsEnabled(ADC1) | \\r
+ LL_ADC_IsEnabled(ADC2) ) \\r
+ ) \\r
+ : \\r
+ ( \\r
+ (LL_ADC_IsEnabled(ADC3)) \\r
+ ) \\r
+ )\r
+#else\r
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \\r
+ (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))\r
+#endif\r
+\r
+/**\r
+ * @brief Helper macro to define the ADC conversion data full-scale digital\r
+ * value corresponding to the selected ADC resolution.\r
+ * @note ADC conversion data full-scale corresponds to voltage range\r
+ * determined by analog voltage references Vref+ and Vref-\r
+ * (refer to reference manual).\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)\r
+ */\r
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \\r
+ (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))\r
+\r
+/**\r
+ * @brief Helper macro to convert the ADC conversion data from\r
+ * a resolution to another resolution.\r
+ * @param __DATA__ ADC conversion data to be converted\r
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @retval ADC conversion data to the requested resolution\r
+ */\r
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\\r
+ __ADC_RESOLUTION_CURRENT__,\\r
+ __ADC_RESOLUTION_TARGET__) \\r
+ (((__DATA__) \\r
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \\r
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to calculate the voltage (unit: mVolt)\r
+ * corresponding to a ADC conversion data (unit: digital value).\r
+ * @note Analog reference voltage (Vref+) must be either known from\r
+ * user board environment or can be calculated using ADC measurement\r
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\r
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)\r
+ * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)\r
+ * (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)\r
+ */\r
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\\r
+ __ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \\r
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to calculate analog reference voltage (Vref+)\r
+ * (unit: mVolt) from ADC conversion data of internal voltage\r
+ * reference VrefInt.\r
+ * @note Computation is using VrefInt calibration value\r
+ * stored in system memory for each device during production.\r
+ * @note This voltage depends on user board environment: voltage level\r
+ * connected to pin Vref+.\r
+ * On devices with small package, the pin Vref+ is not present\r
+ * and internally bonded to pin Vdda.\r
+ * @note On this STM32 serie, calibration data of internal voltage reference\r
+ * VrefInt corresponds to a resolution of 16 bits,\r
+ * this is the recommended ADC resolution to convert voltage of\r
+ * internal voltage reference VrefInt.\r
+ * Otherwise, this macro performs the processing to scale\r
+ * ADC conversion data to 16 bits.\r
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)\r
+ * of internal voltage reference VrefInt (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @retval Analog reference voltage (unit: mV)\r
+ */\r
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \\r
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \\r
+ (__ADC_RESOLUTION__), \\r
+ LL_ADC_RESOLUTION_16B) \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)\r
+ * from ADC conversion data of internal temperature sensor.\r
+ * @note Computation is using temperature sensor calibration values\r
+ * stored in system memory for each device during production.\r
+ * @note Calculation formula:\r
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)\r
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))\r
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP\r
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC\r
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)\r
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)\r
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature\r
+ * TEMP_DEGC_CAL1 (calibrated in factory)\r
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature\r
+ * TEMP_DEGC_CAL2 (calibrated in factory)\r
+ * Caution: Calculation relevancy under reserve that calibration\r
+ * parameters are correct (address and data).\r
+ * To calculate temperature using temperature sensor\r
+ * datasheet typical values (generic values less, therefore\r
+ * less accurate than calibrated values),\r
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().\r
+ * @note As calculation input, the analog reference voltage (Vref+) must be\r
+ * defined as it impacts the ADC LSB equivalent voltage.\r
+ * @note Analog reference voltage (Vref+) must be either known from\r
+ * user board environment or can be calculated using ADC measurement\r
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\r
+ * @note On this STM32 serie, calibration data of temperature sensor\r
+ * corresponds to a resolution of 16 bits,\r
+ * this is the recommended ADC resolution to convert voltage of\r
+ * temperature sensor.\r
+ * Otherwise, this macro performs the processing to scale\r
+ * ADC conversion data to 16 bits.\r
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)\r
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal\r
+ * temperature sensor (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature\r
+ * sensor voltage has been measured.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @retval Temperature (unit: degree Celsius)\r
+ */\r
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\\r
+ __TEMPSENSOR_ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \\r
+ (__ADC_RESOLUTION__), \\r
+ LL_ADC_RESOLUTION_16B) \\r
+ * (__VREFANALOG_VOLTAGE__)) \\r
+ / TEMPSENSOR_CAL_VREFANALOG) \\r
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \\r
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \\r
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \\r
+ ) + TEMPSENSOR_CAL1_TEMP \\r
+ )\r
+\r
+/**\r
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)\r
+ * from ADC conversion data of internal temperature sensor.\r
+ * @note Computation is using temperature sensor typical values\r
+ * (refer to device datasheet).\r
+ * @note Calculation formula:\r
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)\r
+ * / Avg_Slope + CALx_TEMP\r
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC\r
+ * (unit: digital value)\r
+ * Avg_Slope = temperature sensor slope\r
+ * (unit: uV/Degree Celsius)\r
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at\r
+ * temperature CALx_TEMP (unit: mV)\r
+ * Caution: Calculation relevancy under reserve the temperature sensor\r
+ * of the current device has characteristics in line with\r
+ * datasheet typical values.\r
+ * If temperature sensor calibration values are available on\r
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),\r
+ * temperature calculation will be more accurate using\r
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().\r
+ * @note As calculation input, the analog reference voltage (Vref+) must be\r
+ * defined as it impacts the ADC LSB equivalent voltage.\r
+ * @note Analog reference voltage (Vref+) must be either known from\r
+ * user board environment or can be calculated using ADC measurement\r
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\r
+ * @note ADC measurement data must correspond to a resolution of 16 bits\r
+ * (full scale digital value 4095). If not the case, the data must be\r
+ * preliminarily rescaled to an equivalent resolution of 16 bits.\r
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).\r
+ * On STM32H7, refer to device datasheet parameter "Avg_Slope".\r
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).\r
+ * On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).\r
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)\r
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)\r
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).\r
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @retval Temperature (unit: degree Celsius)\r
+ */\r
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\\r
+ __TEMPSENSOR_TYP_CALX_V__,\\r
+ __TEMPSENSOR_CALX_TEMP__,\\r
+ __VREFANALOG_VOLTAGE__,\\r
+ __TEMPSENSOR_ADC_DATA__,\\r
+ __ADC_RESOLUTION__) \\r
+ ((( ( \\r
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \\r
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \\r
+ * 1000UL) \\r
+ - \\r
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \\r
+ * 1000UL) \\r
+ ) \\r
+ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \\r
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \\r
+ )\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the\r
+ * ADC register address from ADC instance and a list of ADC registers\r
+ * intended to be used (most commonly) with DMA transfer.\r
+ * @note These ADC registers are data registers:\r
+ * when ADC conversion data is available in ADC data registers,\r
+ * ADC generates a DMA transfer request.\r
+ * @note This macro is intended to be used with LL DMA driver, refer to\r
+ * function "LL_DMA_ConfigAddresses()".\r
+ * Example:\r
+ * LL_DMA_ConfigAddresses(DMA1,\r
+ * LL_DMA_CHANNEL_1,\r
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),\r
+ * (uint32_t)&< array or variable >,\r
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);\r
+ * @note For devices with several ADC: in multimode, some devices\r
+ * use a different data register outside of ADC instance scope\r
+ * (common data register). This macro manages this register difference,\r
+ * only ADC instance has to be set as parameter.\r
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n\r
+ * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n\r
+ * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr\r
+ * @param ADCx ADC instance\r
+ * @param Register This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA\r
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)\r
+ *\r
+ * (1) Available on devices with several ADC instances.\r
+ * @retval ADC register address\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)\r
+{\r
+ register uint32_t data_reg_addr;\r
+\r
+ if (Register == LL_ADC_DMA_REG_REGULAR_DATA)\r
+ {\r
+ /* Retrieve address of register DR */\r
+ data_reg_addr = (uint32_t)&(ADCx->DR);\r
+ }\r
+ else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */\r
+ {\r
+ /* Retrieve address of register CDR */\r
+ data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);\r
+ }\r
+\r
+ return data_reg_addr;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set parameter common to several ADC: Clock source and prescaler.\r
+ * @note On this STM32 serie, if ADC group injected is used, some\r
+ * clock ratio constraints between ADC clock and AHB clock\r
+ * must be respected.\r
+ * Refer to reference manual.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * All ADC instances of the ADC common group must be disabled.\r
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each\r
+ * ADC instance or by using helper macro helper macro\r
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\r
+ * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n\r
+ * CCR PRESC LL_ADC_SetCommonClock\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @param CommonClock This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1\r
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2\r
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)\r
+{\r
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);\r
+}\r
+\r
+/**\r
+ * @brief Get parameter common to several ADC: Clock source and prescaler.\r
+ * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n\r
+ * CCR PRESC LL_ADC_GetCommonClock\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1\r
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2\r
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128\r
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));\r
+}\r
+\r
+/**\r
+ * @brief Set parameter common to several ADC: measurement path to internal\r
+ * channels (VrefInt, temperature sensor, ...).\r
+ * @note One or several values can be selected.\r
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |\r
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)\r
+ * @note Stabilization time of measurement path to internal channel:\r
+ * After enabling internal paths, before starting ADC conversion,\r
+ * a delay is required for internal voltage reference and\r
+ * temperature sensor stabilization time.\r
+ * Refer to device datasheet.\r
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.\r
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.\r
+ * @note ADC internal channel sampling time constraint:\r
+ * For ADC conversion of internal channels,\r
+ * a sampling time minimum value is required.\r
+ * Refer to device datasheet.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * All ADC instances of the ADC common group must be disabled.\r
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each\r
+ * ADC instance or by using helper macro helper macro\r
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\r
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n\r
+ * CCR TSEN LL_ADC_SetCommonPathInternalCh\n\r
+ * CCR VBATEN LL_ADC_SetCommonPathInternalCh\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @param PathInternal This parameter can be a combination of the following values:\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)\r
+{\r
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);\r
+}\r
+\r
+/**\r
+ * @brief Get parameter common to several ADC: measurement path to internal\r
+ * channels (VrefInt, temperature sensor, ...).\r
+ * @note One or several values can be selected.\r
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |\r
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)\r
+ * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n\r
+ * CCR TSEN LL_ADC_GetCommonPathInternalCh\n\r
+ * CCR VBATEN LL_ADC_GetCommonPathInternalCh\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval Returned value can be a combination of the following values:\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR\r
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set ADC calibration factor in the mode single-ended\r
+ * or differential (for devices with differential mode available).\r
+ * @note This function is intended to set calibration parameters\r
+ * without having to perform a new calibration using\r
+ * @ref LL_ADC_StartCalibration().\r
+ * @note For devices with differential mode available:\r
+ * Calibration of offset is specific to each of\r
+ * single-ended and differential modes\r
+ * (calibration factor must be specified for each of these\r
+ * differential modes, if used afterwards and if the application\r
+ * requires their calibration).\r
+ * Calibration of linearity is common to both\r
+ * single-ended and differential modes\r
+ * (calibration factor can be specified only once).\r
+ * @note In case of setting calibration factors of both modes single ended\r
+ * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):\r
+ * both calibration factors must be concatenated.\r
+ * To perform this processing, use helper macro\r
+ * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be enabled, without calibration on going, without conversion\r
+ * on going on group regular.\r
+ * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor\n\r
+ * CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor\r
+ * @param ADCx ADC instance\r
+ * @param SingleDiff This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_SINGLE_ENDED\r
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED\r
+ * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED\r
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)\r
+{\r
+ MODIFY_REG(ADCx->CALFACT,\r
+ SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,\r
+ CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC calibration factor in the mode single-ended\r
+ * or differential (for devices with differential mode available).\r
+ * @note Calibration factors are set by hardware after performing\r
+ * a calibration run using function @ref LL_ADC_StartCalibration().\r
+ * @note For devices with differential mode available:\r
+ * Calibration of offset is specific to each of\r
+ * single-ended and differential modes\r
+ * Calibration of linearity is common to both\r
+ * single-ended and differential modes\r
+ * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor\n\r
+ * CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor\r
+ * @param ADCx ADC instance\r
+ * @param SingleDiff This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_SINGLE_ENDED\r
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED\r
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7F\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)\r
+{\r
+ /* Retrieve bits with position in register depending on parameter */\r
+ /* "SingleDiff". */\r
+ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */\r
+ /* containing other bits reserved for other purpose. */\r
+ return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC Linear calibration factor in the mode single-ended.\r
+ * @note This function is intended to set linear calibration parameters\r
+ * without having to perform a new calibration using\r
+ * @ref LL_ADC_StartCalibration().\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be enabled, without calibration on going, without conversion\r
+ * on going on group regular.\r
+ * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n\r
+ * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\r
+ * @param ADCx ADC instance\r
+ * @param LinearityWord This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6\r
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)\r
+{\r
+ register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;\r
+ MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);\r
+ MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);\r
+ while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))\r
+ {\r
+ timeout_cpu_cycles--;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get ADC Linear calibration factor in the mode single-ended.\r
+ * @note Calibration factors are set by hardware after performing\r
+ * a calibration run using function @ref LL_ADC_StartCalibration().\r
+ * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n\r
+ * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\r
+ * @param ADCx ADC instance\r
+ * @param LinearityWord This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5\r
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6\r
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)\r
+{\r
+ register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;\r
+ CLEAR_BIT(ADCx->CR, LinearityWord);\r
+ while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))\r
+ {\r
+ timeout_cpu_cycles--;\r
+ }\r
+ return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));\r
+}\r
+/**\r
+ * @brief Set ADC resolution.\r
+ * Refer to reference manual for alignments formats\r
+ * dependencies to ADC resolutions.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR RES LL_ADC_SetResolution\r
+ * @param ADCx ADC instance\r
+ * @param Resolution This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)\r
+{\r
+ if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */\r
+ {\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);\r
+ }\r
+ else /* rev.V */\r
+ {\r
+ if(LL_ADC_RESOLUTION_8B == Resolution)\r
+ {\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);\r
+ }\r
+ else\r
+ {\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get ADC resolution.\r
+ * Refer to reference manual for alignments formats\r
+ * dependencies to ADC resolutions.\r
+ * @rmtoll CFGR RES LL_ADC_GetResolution\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_RESOLUTION_16B\r
+ * @arg @ref LL_ADC_RESOLUTION_14B\r
+ * @arg @ref LL_ADC_RESOLUTION_12B\r
+ * @arg @ref LL_ADC_RESOLUTION_10B\r
+ * @arg @ref LL_ADC_RESOLUTION_8B\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)\r
+{\r
+ if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */\r
+ {\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));\r
+ }\r
+ else\r
+ {\r
+ if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)\r
+ {\r
+ return (LL_ADC_RESOLUTION_8B);\r
+ }\r
+ else\r
+ {\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set ADC low power mode.\r
+ * @note Description of ADC low power modes:\r
+ * - ADC low power mode "auto wait": Dynamic low power mode,\r
+ * ADC conversions occurrences are limited to the minimum necessary\r
+ * in order to reduce power consumption.\r
+ * New ADC conversion starts only when the previous\r
+ * unitary conversion data (for ADC group regular)\r
+ * or previous sequence conversions data (for ADC group injected)\r
+ * has been retrieved by user software.\r
+ * In the meantime, ADC remains idle: does not performs any\r
+ * other conversion.\r
+ * This mode allows to automatically adapt the ADC conversions\r
+ * triggers to the speed of the software that reads the data.\r
+ * Moreover, this avoids risk of overrun for low frequency\r
+ * applications.\r
+ * How to use this low power mode:\r
+ * - Do not use with interruption or DMA since these modes\r
+ * have to clear immediately the EOC flag to free the\r
+ * IRQ vector sequencer.\r
+ * - Do use with polling: 1. Start conversion,\r
+ * 2. Later on, when conversion data is needed: poll for end of\r
+ * conversion to ensure that conversion is completed and\r
+ * retrieve ADC conversion data. This will trig another\r
+ * ADC conversion start.\r
+ * - ADC low power mode "auto power-off" (feature available on\r
+ * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):\r
+ * the ADC automatically powers-off after a conversion and\r
+ * automatically wakes up when a new conversion is triggered\r
+ * (with startup time between trigger and start of sampling).\r
+ * This feature can be combined with low power mode "auto wait".\r
+ * @note With ADC low power mode "auto wait", the ADC conversion data read\r
+ * is corresponding to previous ADC conversion start, independently\r
+ * of delay during which ADC was idle.\r
+ * Therefore, the ADC conversion data may be outdated: does not\r
+ * correspond to the current voltage level on the selected\r
+ * ADC channel.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode\r
+ * @param ADCx ADC instance\r
+ * @param LowPowerMode This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_LP_MODE_NONE\r
+ * @arg @ref LL_ADC_LP_AUTOWAIT\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC low power mode:\r
+ * @note Description of ADC low power modes:\r
+ * - ADC low power mode "auto wait": Dynamic low power mode,\r
+ * ADC conversions occurrences are limited to the minimum necessary\r
+ * in order to reduce power consumption.\r
+ * New ADC conversion starts only when the previous\r
+ * unitary conversion data (for ADC group regular)\r
+ * or previous sequence conversions data (for ADC group injected)\r
+ * has been retrieved by user software.\r
+ * In the meantime, ADC remains idle: does not performs any\r
+ * other conversion.\r
+ * This mode allows to automatically adapt the ADC conversions\r
+ * triggers to the speed of the software that reads the data.\r
+ * Moreover, this avoids risk of overrun for low frequency\r
+ * applications.\r
+ * How to use this low power mode:\r
+ * - Do not use with interruption or DMA since these modes\r
+ * have to clear immediately the EOC flag to free the\r
+ * IRQ vector sequencer.\r
+ * - Do use with polling: 1. Start conversion,\r
+ * 2. Later on, when conversion data is needed: poll for end of\r
+ * conversion to ensure that conversion is completed and\r
+ * retrieve ADC conversion data. This will trig another\r
+ * ADC conversion start.\r
+ * - ADC low power mode "auto power-off" (feature available on\r
+ * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):\r
+ * the ADC automatically powers-off after a conversion and\r
+ * automatically wakes up when a new conversion is triggered\r
+ * (with startup time between trigger and start of sampling).\r
+ * This feature can be combined with low power mode "auto wait".\r
+ * @note With ADC low power mode "auto wait", the ADC conversion data read\r
+ * is corresponding to previous ADC conversion start, independently\r
+ * of delay during which ADC was idle.\r
+ * Therefore, the ADC conversion data may be outdated: does not\r
+ * correspond to the current voltage level on the selected\r
+ * ADC channel.\r
+ * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_LP_MODE_NONE\r
+ * @arg @ref LL_ADC_LP_AUTOWAIT\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC selected offset number 1, 2, 3 or 4.\r
+ * @note This function set the 2 items of offset configuration:\r
+ * - ADC channel to which the offset programmed will be applied\r
+ * (independently of channel mapped on ADC group regular\r
+ * or group injected)\r
+ * - Offset level (offset to be subtracted from the raw\r
+ * converted data).\r
+ * @note Caution: Offset format is dependent to ADC resolution:\r
+ * offset has to be left-aligned on bit 11, the LSB (right bits)\r
+ * are set to 0.\r
+ * @note This function enables the offset, by default. It can be forced\r
+ * to disable state using function LL_ADC_SetOffsetState().\r
+ * @note If a channel is mapped on several offsets numbers, only the offset\r
+ * with the lowest value is considered for the subtraction.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @note On STM32H7, some fast channels are available: fast analog inputs\r
+ * coming from GPIO pads (ADC_IN0..5).\r
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n\r
+ * OFR1 OFFSET1 LL_ADC_SetOffset\n\r
+ * OFR1 OFFSET1_EN LL_ADC_SetOffset\n\r
+ * OFR2 OFFSET2_CH LL_ADC_SetOffset\n\r
+ * OFR2 OFFSET2 LL_ADC_SetOffset\n\r
+ * OFR2 OFFSET2_EN LL_ADC_SetOffset\n\r
+ * OFR3 OFFSET3_CH LL_ADC_SetOffset\n\r
+ * OFR3 OFFSET3 LL_ADC_SetOffset\n\r
+ * OFR3 OFFSET3_EN LL_ADC_SetOffset\n\r
+ * OFR4 OFFSET4_CH LL_ADC_SetOffset\n\r
+ * OFR4 OFFSET4 LL_ADC_SetOffset\n\r
+ * OFR4 OFFSET4_EN LL_ADC_SetOffset\r
+ * @param ADCx ADC instance\r
+ * @param Offsety This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_1\r
+ * @arg @ref LL_ADC_OFFSET_2\r
+ * @arg @ref LL_ADC_OFFSET_3\r
+ * @arg @ref LL_ADC_OFFSET_4\r
+ * @param Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)\r
+{\r
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\r
+\r
+ MODIFY_REG(*preg,\r
+ ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,\r
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);\r
+}\r
+\r
+/**\r
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:\r
+ * Channel to which the offset programmed will be applied\r
+ * (independently of channel mapped on ADC group regular\r
+ * or group injected)\r
+ * @note Usage of the returned channel number:\r
+ * - To reinject this channel into another function LL_ADC_xxx:\r
+ * the returned channel number is only partly formatted on definition\r
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\r
+ * with parts of literals LL_ADC_CHANNEL_x or using\r
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * Then the selected literal LL_ADC_CHANNEL_x can be used\r
+ * as parameter for another function.\r
+ * - To get the channel number in decimal format:\r
+ * process the returned value with the helper macro\r
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * @note On STM32H7, some fast channels are available: fast analog inputs\r
+ * coming from GPIO pads (ADC_IN0..5).\r
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n\r
+ * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n\r
+ * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n\r
+ * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel\r
+ * @param ADCx ADC instance\r
+ * @param Offsety This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_1\r
+ * @arg @ref LL_ADC_OFFSET_2\r
+ * @arg @ref LL_ADC_OFFSET_3\r
+ * @arg @ref LL_ADC_OFFSET_4\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n\r
+ * (1, 2) For ADC channel read back from ADC register,\r
+ * comparison with internal channel parameter to be done\r
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\r
+\r
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);\r
+}\r
+\r
+/**\r
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:\r
+ * Offset level (offset to be subtracted from the raw\r
+ * converted data).\r
+ * @note Caution: Offset format is dependent to ADC resolution:\r
+ * offset has to be left-aligned on bit 11, the LSB (right bits)\r
+ * are set to 0.\r
+ * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n\r
+ * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n\r
+ * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n\r
+ * OFR4 OFFSET4 LL_ADC_GetOffsetLevel\r
+ * @param ADCx ADC instance\r
+ * @param Offsety This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_1\r
+ * @arg @ref LL_ADC_OFFSET_2\r
+ * @arg @ref LL_ADC_OFFSET_3\r
+ * @arg @ref LL_ADC_OFFSET_4\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\r
+\r
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set data right shift for the ADC selected offset number 1, 2, 3 or 4:\r
+ * signed offset saturation if enabled or disabled.\r
+ * @rmtoll CFGR2 RSHIFT LL_ADC_SetDataRightShift\n\r
+ * @param ADCx ADC instance\r
+ * @param Offsety This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_1\r
+ * @arg @ref LL_ADC_OFFSET_2\r
+ * @arg @ref LL_ADC_OFFSET_3\r
+ * @arg @ref LL_ADC_OFFSET_4\r
+ * @param RigthShift This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE\r
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE\r
+ * @retval Returned None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)\r
+{\r
+ MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));\r
+}\r
+\r
+/**\r
+ * @brief Get data right shift for the ADC selected offset number 1, 2, 3 or 4:\r
+ * signed offset saturation if enabled or disabled.\r
+ * @rmtoll CFGR2 RSHIFT LL_ADC_GetDataRightShift\n\r
+ * @param ADCx ADC instance\r
+ * @param Offsety This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_1\r
+ * @arg @ref LL_ADC_OFFSET_2\r
+ * @arg @ref LL_ADC_OFFSET_3\r
+ * @arg @ref LL_ADC_OFFSET_4\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE\r
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)\r
+{\r
+ return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));\r
+}\r
+\r
+/**\r
+ * @brief Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:\r
+ * signed offset saturation if enabled or disabled.\r
+ * @rmtoll OFR1 SSATE LL_ADC_SetOffsetSignedSaturation\n\r
+ * OFR2 SSATE LL_ADC_SetOffsetSignedSaturation\n\r
+ * OFR3 SSATE LL_ADC_SetOffsetSignedSaturation\n\r
+ * OFR4 SSATE LL_ADC_SetOffsetSignedSaturation\r
+ * @param ADCx ADC instance\r
+ * @param Offsety This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_1\r
+ * @arg @ref LL_ADC_OFFSET_2\r
+ * @arg @ref LL_ADC_OFFSET_3\r
+ * @arg @ref LL_ADC_OFFSET_4\r
+ * @param OffsetSignedSaturation This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE\r
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE\r
+ * @retval Returned None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)\r
+{\r
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\r
+ MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);\r
+}\r
+\r
+/**\r
+ * @brief Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:\r
+ * signed offset saturation if enabled or disabled.\r
+ * @rmtoll OFR1 SSATE LL_ADC_GetOffsetSignedSaturation\n\r
+ * OFR2 SSATE LL_ADC_GetOffsetSignedSaturation\n\r
+ * OFR3 SSATE LL_ADC_GetOffsetSignedSaturation\n\r
+ * OFR4 SSATE LL_ADC_GetOffsetSignedSaturation\r
+ * @param ADCx ADC instance\r
+ * @param Offsety This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_1\r
+ * @arg @ref LL_ADC_OFFSET_2\r
+ * @arg @ref LL_ADC_OFFSET_3\r
+ * @arg @ref LL_ADC_OFFSET_4\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE\r
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\r
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set ADC group regular conversion trigger source:\r
+ * internal (SW start) or from external peripheral (timer event,\r
+ * external interrupt line).\r
+ * @note On this STM32 serie, setting trigger source to external trigger\r
+ * also set trigger polarity to rising edge\r
+ * (default setting for compatibility with some ADC on other\r
+ * STM32 families having this setting set by HW default value).\r
+ * In case of need to modify trigger edge, use\r
+ * function @ref LL_ADC_REG_SetTriggerEdge().\r
+ * @note Availability of parameters of trigger sources from timer\r
+ * depends on timers availability on the selected device.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n\r
+ * CFGR EXTEN LL_ADC_REG_SetTriggerSource\r
+ * @param ADCx ADC instance\r
+ * @param TriggerSource This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion trigger source:\r
+ * internal (SW start) or from external peripheral (timer event,\r
+ * external interrupt line).\r
+ * @note To determine whether group regular trigger source is\r
+ * internal (SW start) or external, without detail\r
+ * of which peripheral is selected as external trigger,\r
+ * (equivalent to\r
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")\r
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.\r
+ * @note Availability of parameters of trigger sources from timer\r
+ * depends on timers availability on the selected device.\r
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n\r
+ * CFGR EXTEN LL_ADC_REG_GetTriggerSource\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)\r
+{\r
+ register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);\r
+\r
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */\r
+ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */\r
+ register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));\r
+\r
+ /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */\r
+ /* to match with triggers literals definition. */\r
+ return ((TriggerSource\r
+ & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)\r
+ | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion trigger source internal (SW start)\r
+ * or external.\r
+ * @note In case of group regular trigger source set to external trigger,\r
+ * to determine which peripheral is selected as external trigger,\r
+ * use function @ref LL_ADC_REG_GetTriggerSource().\r
+ * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart\r
+ * @param ADCx ADC instance\r
+ * @retval Value "0" if trigger source external trigger\r
+ * Value "1" if trigger source SW start.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group regular conversion trigger polarity.\r
+ * @note Applicable only for trigger source set to external trigger.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge\r
+ * @param ADCx ADC instance\r
+ * @param ExternalTriggerEdge This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion trigger polarity.\r
+ * @note Applicable only for trigger source set to external trigger.\r
+ * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING\r
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group regular sequencer length and scan direction.\r
+ * @note Description of ADC group regular sequencer features:\r
+ * - For devices with sequencer fully configurable\r
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):\r
+ * sequencer length and each rank affectation to a channel\r
+ * are configurable.\r
+ * This function performs configuration of:\r
+ * - Sequence length: Number of ranks in the scan sequence.\r
+ * - Sequence direction: Unless specified in parameters, sequencer\r
+ * scan direction is forward (from rank 1 to rank n).\r
+ * Sequencer ranks are selected using\r
+ * function "LL_ADC_REG_SetSequencerRanks()".\r
+ * - For devices with sequencer not fully configurable\r
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):\r
+ * sequencer length and each rank affectation to a channel\r
+ * are defined by channel number.\r
+ * This function performs configuration of:\r
+ * - Sequence length: Number of ranks in the scan sequence is\r
+ * defined by number of channels set in the sequence,\r
+ * rank of each channel is fixed by channel HW number.\r
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).\r
+ * - Sequence direction: Unless specified in parameters, sequencer\r
+ * scan direction is forward (from lowest channel number to\r
+ * highest channel number).\r
+ * Sequencer ranks are selected using\r
+ * function "LL_ADC_REG_SetSequencerChannels()".\r
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:\r
+ * ADC conversion on only 1 channel.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength\r
+ * @param ADCx ADC instance\r
+ * @param SequencerNbRanks This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)\r
+{\r
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular sequencer length and scan direction.\r
+ * @note Description of ADC group regular sequencer features:\r
+ * - For devices with sequencer fully configurable\r
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):\r
+ * sequencer length and each rank affectation to a channel\r
+ * are configurable.\r
+ * This function retrieves:\r
+ * - Sequence length: Number of ranks in the scan sequence.\r
+ * - Sequence direction: Unless specified in parameters, sequencer\r
+ * scan direction is forward (from rank 1 to rank n).\r
+ * Sequencer ranks are selected using\r
+ * function "LL_ADC_REG_SetSequencerRanks()".\r
+ * - For devices with sequencer not fully configurable\r
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):\r
+ * sequencer length and each rank affectation to a channel\r
+ * are defined by channel number.\r
+ * This function retrieves:\r
+ * - Sequence length: Number of ranks in the scan sequence is\r
+ * defined by number of channels set in the sequence,\r
+ * rank of each channel is fixed by channel HW number.\r
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).\r
+ * - Sequence direction: Unless specified in parameters, sequencer\r
+ * scan direction is forward (from lowest channel number to\r
+ * highest channel number).\r
+ * Sequencer ranks are selected using\r
+ * function "LL_ADC_REG_SetSequencerChannels()".\r
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:\r
+ * ADC conversion on only 1 channel.\r
+ * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group regular sequencer discontinuous mode:\r
+ * sequence subdivided and scan conversions interrupted every selected\r
+ * number of ranks.\r
+ * @note It is not possible to enable both ADC group regular\r
+ * continuous mode and sequencer discontinuous mode.\r
+ * @note It is not possible to enable both ADC auto-injected mode\r
+ * and ADC group regular sequencer discontinuous mode.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n\r
+ * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont\r
+ * @param ADCx ADC instance\r
+ * @param SeqDiscont This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular sequencer discontinuous mode:\r
+ * sequence subdivided and scan conversions interrupted every selected\r
+ * number of ranks.\r
+ * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n\r
+ * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS\r
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group regular sequence: channel on the selected\r
+ * scan sequence rank.\r
+ * @note This function performs configuration of:\r
+ * - Channels ordering into each rank of scan sequence:\r
+ * whatever channel can be placed into whatever rank.\r
+ * @note On this STM32 serie, ADC group regular sequencer is\r
+ * fully configurable: sequencer length and each rank\r
+ * affectation to a channel are configurable.\r
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().\r
+ * @note Depending on devices and packages, some channels may not be available.\r
+ * Refer to device datasheet for channels availability.\r
+ * @note On this STM32 serie, to measure internal channels (VrefInt,\r
+ * TempSensor, ...), measurement paths to internal channels must be\r
+ * enabled separately.\r
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n\r
+ * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_RANK_1\r
+ * @arg @ref LL_ADC_REG_RANK_2\r
+ * @arg @ref LL_ADC_REG_RANK_3\r
+ * @arg @ref LL_ADC_REG_RANK_4\r
+ * @arg @ref LL_ADC_REG_RANK_5\r
+ * @arg @ref LL_ADC_REG_RANK_6\r
+ * @arg @ref LL_ADC_REG_RANK_7\r
+ * @arg @ref LL_ADC_REG_RANK_8\r
+ * @arg @ref LL_ADC_REG_RANK_9\r
+ * @arg @ref LL_ADC_REG_RANK_10\r
+ * @arg @ref LL_ADC_REG_RANK_11\r
+ * @arg @ref LL_ADC_REG_RANK_12\r
+ * @arg @ref LL_ADC_REG_RANK_13\r
+ * @arg @ref LL_ADC_REG_RANK_14\r
+ * @arg @ref LL_ADC_REG_RANK_15\r
+ * @arg @ref LL_ADC_REG_RANK_16\r
+ * @param Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)\r
+{\r
+ /* Set bits with content of parameter "Channel" with bits position */\r
+ /* in register and register position depending on parameter "Rank". */\r
+ /* Parameters "Rank" and "Channel" are used with masks because containing */\r
+ /* other bits reserved for other purpose. */\r
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));\r
+\r
+ MODIFY_REG(*preg,\r
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),\r
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular sequence: channel on the selected\r
+ * scan sequence rank.\r
+ * @note On this STM32 serie, ADC group regular sequencer is\r
+ * fully configurable: sequencer length and each rank\r
+ * affectation to a channel are configurable.\r
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().\r
+ * @note Depending on devices and packages, some channels may not be available.\r
+ * Refer to device datasheet for channels availability.\r
+ * @note Usage of the returned channel number:\r
+ * - To reinject this channel into another function LL_ADC_xxx:\r
+ * the returned channel number is only partly formatted on definition\r
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\r
+ * with parts of literals LL_ADC_CHANNEL_x or using\r
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * Then the selected literal LL_ADC_CHANNEL_x can be used\r
+ * as parameter for another function.\r
+ * - To get the channel number in decimal format:\r
+ * process the returned value with the helper macro\r
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n\r
+ * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_RANK_1\r
+ * @arg @ref LL_ADC_REG_RANK_2\r
+ * @arg @ref LL_ADC_REG_RANK_3\r
+ * @arg @ref LL_ADC_REG_RANK_4\r
+ * @arg @ref LL_ADC_REG_RANK_5\r
+ * @arg @ref LL_ADC_REG_RANK_6\r
+ * @arg @ref LL_ADC_REG_RANK_7\r
+ * @arg @ref LL_ADC_REG_RANK_8\r
+ * @arg @ref LL_ADC_REG_RANK_9\r
+ * @arg @ref LL_ADC_REG_RANK_10\r
+ * @arg @ref LL_ADC_REG_RANK_11\r
+ * @arg @ref LL_ADC_REG_RANK_12\r
+ * @arg @ref LL_ADC_REG_RANK_13\r
+ * @arg @ref LL_ADC_REG_RANK_14\r
+ * @arg @ref LL_ADC_REG_RANK_15\r
+ * @arg @ref LL_ADC_REG_RANK_16\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n\r
+ * (1, 2) For ADC channel read back from ADC register,\r
+ * comparison with internal channel parameter to be done\r
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));\r
+\r
+ return (uint32_t) ((READ_BIT(*preg,\r
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))\r
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Set ADC continuous conversion mode on ADC group regular.\r
+ * @note Description of ADC continuous conversion mode:\r
+ * - single mode: one conversion per trigger\r
+ * - continuous mode: after the first trigger, following\r
+ * conversions launched successively automatically.\r
+ * @note It is not possible to enable both ADC group regular\r
+ * continuous mode and sequencer discontinuous mode.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode\r
+ * @param ADCx ADC instance\r
+ * @param Continuous This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_CONV_SINGLE\r
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC continuous conversion mode on ADC group regular.\r
+ * @note Description of ADC continuous conversion mode:\r
+ * - single mode: one conversion per trigger\r
+ * - continuous mode: after the first trigger, following\r
+ * conversions launched successively automatically.\r
+ * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_CONV_SINGLE\r
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));\r
+}\r
+/**\r
+ * @brief Set ADC data transfer mode\r
+ * @note Conversion data can be either:\r
+ * - Available in Data Register\r
+ * - Transfered by DMA in one shot mode\r
+ * - Transfered by DMA in circular mode\r
+ * - Transfered to DFSDM data register\r
+ * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode\r
+ * @param ADCx ADC instance\r
+ * @param DataTransferMode Select Data Management configuration\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Get ADC data transfer mode\r
+ * @note Conversion data can be either:\r
+ * - Available in Data Register\r
+ * - Transfered by DMA in one shot mode\r
+ * - Transfered by DMA in circular mode\r
+ * - Transfered to DFSDM data register\r
+ * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_DR_TRANSFER\r
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED\r
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED\r
+ * @arg @ref LL_ADC_REG_DFSDM_TRANSFER\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set ADC group regular behavior in case of overrun:\r
+ * data preserved or overwritten.\r
+ * @note Compatibility with devices without feature overrun:\r
+ * other devices without this feature have a behavior\r
+ * equivalent to data overwritten.\r
+ * The default setting of overrun is data preserved.\r
+ * Therefore, for compatibility with all devices, parameter\r
+ * overrun should be set to data overwritten.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun\r
+ * @param ADCx ADC instance\r
+ * @param Overrun This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED\r
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular behavior in case of overrun:\r
+ * data preserved or overwritten.\r
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED\r
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set ADC group injected conversion trigger source:\r
+ * internal (SW start) or from external peripheral (timer event,\r
+ * external interrupt line).\r
+ * @note On this STM32 serie, setting trigger source to external trigger\r
+ * also set trigger polarity to rising edge\r
+ * (default setting for compatibility with some ADC on other\r
+ * STM32 families having this setting set by HW default value).\r
+ * In case of need to modify trigger edge, use\r
+ * function @ref LL_ADC_INJ_SetTriggerEdge().\r
+ * @note Availability of parameters of trigger sources from timer\r
+ * depends on timers availability on the selected device.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must not be disabled. Can be enabled with or without conversion\r
+ * on going on either groups regular or injected.\r
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n\r
+ * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource\r
+ * @param ADCx ADC instance\r
+ * @param TriggerSource This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\r
+{\r
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion trigger source:\r
+ * internal (SW start) or from external peripheral (timer event,\r
+ * external interrupt line).\r
+ * @note To determine whether group injected trigger source is\r
+ * internal (SW start) or external, without detail\r
+ * of which peripheral is selected as external trigger,\r
+ * (equivalent to\r
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")\r
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.\r
+ * @note Availability of parameters of trigger sources from timer\r
+ * depends on timers availability on the selected device.\r
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n\r
+ * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)\r
+{\r
+ register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);\r
+\r
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */\r
+ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */\r
+ register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));\r
+\r
+ /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */\r
+ /* to match with triggers literals definition. */\r
+ return ((TriggerSource\r
+ & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)\r
+ | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion trigger source internal (SW start)\r
+ or external\r
+ * @note In case of group injected trigger source set to external trigger,\r
+ * to determine which peripheral is selected as external trigger,\r
+ * use function @ref LL_ADC_INJ_GetTriggerSource.\r
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart\r
+ * @param ADCx ADC instance\r
+ * @retval Value "0" if trigger source external trigger\r
+ * Value "1" if trigger source SW start.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group injected conversion trigger polarity.\r
+ * Applicable only for trigger source set to external trigger.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must not be disabled. Can be enabled with or without conversion\r
+ * on going on either groups regular or injected.\r
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge\r
+ * @param ADCx ADC instance\r
+ * @param ExternalTriggerEdge This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)\r
+{\r
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion trigger polarity.\r
+ * Applicable only for trigger source set to external trigger.\r
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group injected sequencer length and scan direction.\r
+ * @note This function performs configuration of:\r
+ * - Sequence length: Number of ranks in the scan sequence.\r
+ * - Sequence direction: Unless specified in parameters, sequencer\r
+ * scan direction is forward (from rank 1 to rank n).\r
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:\r
+ * ADC conversion on only 1 channel.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must not be disabled. Can be enabled with or without conversion\r
+ * on going on either groups regular or injected.\r
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength\r
+ * @param ADCx ADC instance\r
+ * @param SequencerNbRanks This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)\r
+{\r
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected sequencer length and scan direction.\r
+ * @note This function retrieves:\r
+ * - Sequence length: Number of ranks in the scan sequence.\r
+ * - Sequence direction: Unless specified in parameters, sequencer\r
+ * scan direction is forward (from rank 1 to rank n).\r
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:\r
+ * ADC conversion on only 1 channel.\r
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group injected sequencer discontinuous mode:\r
+ * sequence subdivided and scan conversions interrupted every selected\r
+ * number of ranks.\r
+ * @note It is not possible to enable both ADC group injected\r
+ * auto-injected mode and sequencer discontinuous mode.\r
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont\r
+ * @param ADCx ADC instance\r
+ * @param SeqDiscont This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE\r
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected sequencer discontinuous mode:\r
+ * sequence subdivided and scan conversions interrupted every selected\r
+ * number of ranks.\r
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE\r
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group injected sequence: channel on the selected\r
+ * sequence rank.\r
+ * @note Depending on devices and packages, some channels may not be available.\r
+ * Refer to device datasheet for channels availability.\r
+ * @note On this STM32 serie, to measure internal channels (VrefInt,\r
+ * TempSensor, ...), measurement paths to internal channels must be\r
+ * enabled separately.\r
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\r
+ * @note On STM32H7, some fast channels are available: fast analog inputs\r
+ * coming from GPIO pads (ADC_IN0..5).\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must not be disabled. Can be enabled with or without conversion\r
+ * on going on either groups regular or injected.\r
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n\r
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n\r
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n\r
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @param Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)\r
+{\r
+ /* Set bits with content of parameter "Channel" with bits position */\r
+ /* in register depending on parameter "Rank". */\r
+ /* Parameters "Rank" and "Channel" are used with masks because containing */\r
+ /* other bits reserved for other purpose. */\r
+ MODIFY_REG(ADCx->JSQR,\r
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),\r
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected sequence: channel on the selected\r
+ * sequence rank.\r
+ * @note Depending on devices and packages, some channels may not be available.\r
+ * Refer to device datasheet for channels availability.\r
+ * @note Usage of the returned channel number:\r
+ * - To reinject this channel into another function LL_ADC_xxx:\r
+ * the returned channel number is only partly formatted on definition\r
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\r
+ * with parts of literals LL_ADC_CHANNEL_x or using\r
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * Then the selected literal LL_ADC_CHANNEL_x can be used\r
+ * as parameter for another function.\r
+ * - To get the channel number in decimal format:\r
+ * process the returned value with the helper macro\r
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n\r
+ * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n\r
+ * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n\r
+ * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n\r
+ * (1, 2) For ADC channel read back from ADC register,\r
+ * comparison with internal channel parameter to be done\r
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ return (uint32_t)((READ_BIT(ADCx->JSQR,\r
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))\r
+ >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group injected conversion trigger:\r
+ * independent or from ADC group regular.\r
+ * @note This mode can be used to extend number of data registers\r
+ * updated after one ADC conversion trigger and with data\r
+ * permanently kept (not erased by successive conversions of scan of\r
+ * ADC sequencer ranks), up to 5 data registers:\r
+ * 1 data register on ADC group regular, 4 data registers\r
+ * on ADC group injected.\r
+ * @note If ADC group injected injected trigger source is set to an\r
+ * external trigger, this feature must be must be set to\r
+ * independent trigger.\r
+ * ADC group injected automatic trigger is compliant only with\r
+ * group injected trigger source set to SW start, without any\r
+ * further action on ADC group injected conversion start or stop:\r
+ * in this case, ADC group injected is controlled only\r
+ * from ADC group regular.\r
+ * @note It is not possible to enable both ADC group injected\r
+ * auto-injected mode and sequencer discontinuous mode.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto\r
+ * @param ADCx ADC instance\r
+ * @param TrigAuto This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT\r
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion trigger:\r
+ * independent or from ADC group regular.\r
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT\r
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC group injected contexts queue mode.\r
+ * @note A context is a setting of group injected sequencer:\r
+ * - group injected trigger\r
+ * - sequencer length\r
+ * - sequencer ranks\r
+ * If contexts queue is disabled:\r
+ * - only 1 sequence can be configured\r
+ * and is active perpetually.\r
+ * If contexts queue is enabled:\r
+ * - up to 2 contexts can be queued\r
+ * and are checked in and out as a FIFO stack (first-in, first-out).\r
+ * - If a new context is set when queues is full, error is triggered\r
+ * by interruption "Injected Queue Overflow".\r
+ * - Two behaviors are possible when all contexts have been processed:\r
+ * the contexts queue can maintain the last context active perpetually\r
+ * or can be empty and injected group triggers are disabled.\r
+ * - Triggers can be only external (not internal SW start)\r
+ * - Caution: The sequence must be fully configured in one time\r
+ * (one write of register JSQR makes a check-in of a new context\r
+ * into the queue).\r
+ * Therefore functions to set separately injected trigger and\r
+ * sequencer channels cannot be used, register JSQR must be set\r
+ * using function @ref LL_ADC_INJ_ConfigQueueContext().\r
+ * @note This parameter can be modified only when no conversion is on going\r
+ * on either groups regular or injected.\r
+ * @note A modification of the context mode (bit JQDIS) causes the contexts\r
+ * queue to be flushed and the register JSQR is cleared.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n\r
+ * CFGR JQDIS LL_ADC_INJ_SetQueueMode\r
+ * @param ADCx ADC instance\r
+ * @param QueueMode This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_QUEUE_DISABLE\r
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE\r
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)\r
+{\r
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected context queue mode.\r
+ * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n\r
+ * CFGR JQDIS LL_ADC_INJ_GetQueueMode\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_QUEUE_DISABLE\r
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE\r
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));\r
+}\r
+\r
+/**\r
+ * @brief Set one context on ADC group injected that will be checked in\r
+ * contexts queue.\r
+ * @note A context is a setting of group injected sequencer:\r
+ * - group injected trigger\r
+ * - sequencer length\r
+ * - sequencer ranks\r
+ * This function is intended to be used when contexts queue is enabled,\r
+ * because the sequence must be fully configured in one time\r
+ * (functions to set separately injected trigger and sequencer channels\r
+ * cannot be used):\r
+ * Refer to function @ref LL_ADC_INJ_SetQueueMode().\r
+ * @note In the contexts queue, only the active context can be read.\r
+ * The parameters of this function can be read using functions:\r
+ * @arg @ref LL_ADC_INJ_GetTriggerSource()\r
+ * @arg @ref LL_ADC_INJ_GetTriggerEdge()\r
+ * @arg @ref LL_ADC_INJ_GetSequencerRanks()\r
+ * @note On this STM32 serie, to measure internal channels (VrefInt,\r
+ * TempSensor, ...), measurement paths to internal channels must be\r
+ * enabled separately.\r
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\r
+ * @note On STM32H7, some fast channels are available: fast analog inputs\r
+ * coming from GPIO pads (ADC_IN0..5).\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must not be disabled. Can be enabled with or without conversion\r
+ * on going on either groups regular or injected.\r
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n\r
+ * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n\r
+ * JSQR JL LL_ADC_INJ_ConfigQueueContext\n\r
+ * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n\r
+ * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n\r
+ * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n\r
+ * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext\r
+ * @param ADCx ADC instance\r
+ * @param TriggerSource This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT\r
+ * @param ExternalTriggerEdge This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\r
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\r
+ *\r
+ * Note: This parameter is discarded in case of SW start:\r
+ * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".\r
+ * @param SequencerNbRanks This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\r
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\r
+ * @param Rank1_Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @param Rank2_Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @param Rank3_Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @param Rank4_Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,\r
+ uint32_t TriggerSource,\r
+ uint32_t ExternalTriggerEdge,\r
+ uint32_t SequencerNbRanks,\r
+ uint32_t Rank1_Channel,\r
+ uint32_t Rank2_Channel,\r
+ uint32_t Rank3_Channel,\r
+ uint32_t Rank4_Channel)\r
+{\r
+ /* Set bits with content of parameter "Rankx_Channel" with bits position */\r
+ /* in register depending on literal "LL_ADC_INJ_RANK_x". */\r
+ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */\r
+ /* because containing other bits reserved for other purpose. */\r
+ /* If parameter "TriggerSource" is set to SW start, then parameter */\r
+ /* "ExternalTriggerEdge" is discarded. */\r
+ register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);\r
+ MODIFY_REG(ADCx->JSQR ,\r
+ ADC_JSQR_JEXTSEL |\r
+ ADC_JSQR_JEXTEN |\r
+ ADC_JSQR_JSQ4 |\r
+ ADC_JSQR_JSQ3 |\r
+ ADC_JSQR_JSQ2 |\r
+ ADC_JSQR_JSQ1 |\r
+ ADC_JSQR_JL ,\r
+ TriggerSource |\r
+ (ExternalTriggerEdge * (is_trigger_not_sw)) |\r
+ (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |\r
+ (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |\r
+ (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |\r
+ (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |\r
+ SequencerNbRanks\r
+ );\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set sampling time of the selected ADC channel\r
+ * Unit: ADC clock cycles.\r
+ * @note On this device, sampling time is on channel scope: independently\r
+ * of channel mapped on ADC group regular or injected.\r
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be\r
+ * converted:\r
+ * sampling time constraints must be respected (sampling time can be\r
+ * adjusted in function of ADC clock frequency and sampling time\r
+ * setting).\r
+ * Refer to device datasheet for timings values (parameters TS_vrefint,\r
+ * TS_temp, ...).\r
+ * @note Conversion time is the addition of sampling time and processing time.\r
+ * On this STM32 serie, ADC processing time is:\r
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits\r
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits\r
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits\r
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits\r
+ * @note In case of ADC conversion of internal channel (VrefInt,\r
+ * temperature sensor, ...), a sampling time minimum value\r
+ * is required.\r
+ * Refer to device datasheet.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n\r
+ * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime\r
+ * @param ADCx ADC instance\r
+ * @param Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @param SamplingTime This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)\r
+{\r
+ /* Set bits with content of parameter "SamplingTime" with bits position */\r
+ /* in register and register position depending on parameter "Channel". */\r
+ /* Parameter "Channel" is used with masks because containing */\r
+ /* other bits reserved for other purpose. */\r
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));\r
+\r
+ MODIFY_REG(*preg,\r
+ ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),\r
+ SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));\r
+}\r
+\r
+/**\r
+ * @brief Get sampling time of the selected ADC channel\r
+ * Unit: ADC clock cycles.\r
+ * @note On this device, sampling time is on channel scope: independently\r
+ * of channel mapped on ADC group regular or injected.\r
+ * @note Conversion time is the addition of sampling time and processing time.\r
+ * On this STM32 serie, ADC processing time is:\r
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits\r
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits\r
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits\r
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits\r
+ * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n\r
+ * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime\r
+ * @param ADCx ADC instance\r
+ * @param Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_0 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_1 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_2 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_3 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_4 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_5 (3)\r
+ * @arg @ref LL_ADC_CHANNEL_6\r
+ * @arg @ref LL_ADC_CHANNEL_7\r
+ * @arg @ref LL_ADC_CHANNEL_8\r
+ * @arg @ref LL_ADC_CHANNEL_9\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)\r
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)\r
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)\r
+ * \r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n\r
+ * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).\r
+ * Other channels are slow channels (conversion rate: refer to reference manual).\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5\r
+ * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));\r
+\r
+ return (uint32_t)(READ_BIT(*preg,\r
+ ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))\r
+ >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Set mode single-ended or differential input of the selected\r
+ * ADC channel.\r
+ * @note Channel ending is on channel scope: independently of channel mapped\r
+ * on ADC group regular or injected.\r
+ * In differential mode: Differential measurement is carried out\r
+ * between the selected channel 'i' (positive input) and\r
+ * channel 'i+1' (negative input). Only channel 'i' has to be\r
+ * configured, channel 'i+1' is configured automatically.\r
+ * @note Refer to Reference Manual to ensure the selected channel is\r
+ * available in differential mode.\r
+ * For example, internal channels (VrefInt, TempSensor, ...) are\r
+ * not available in differential mode.\r
+ * @note When configuring a channel 'i' in differential mode,\r
+ * the channel 'i+1' is not usable separately.\r
+ * @note On STM32H7, some channels are internally fixed to single-ended inputs\r
+ * configuration:\r
+ * - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19\r
+ * - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19\r
+ * - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19\r
+ * @note For ADC channels configured in differential mode, both inputs\r
+ * should be biased at (Vref+)/2 +/-200mV.\r
+ * (Vref+ is the analog voltage reference)\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be ADC disabled.\r
+ * @note One or several values can be selected.\r
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)\r
+ * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff\r
+ * @param ADCx ADC instance\r
+ * @param Channel This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_1\r
+ * @arg @ref LL_ADC_CHANNEL_2\r
+ * @arg @ref LL_ADC_CHANNEL_3\r
+ * @arg @ref LL_ADC_CHANNEL_4\r
+ * @arg @ref LL_ADC_CHANNEL_5\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @param SingleDiff This parameter can be a combination of the following values:\r
+ * @arg @ref LL_ADC_SINGLE_ENDED\r
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)\r
+{\r
+ /* Bits of channels in single or differential mode are set only for */\r
+ /* differential mode (for single mode, mask of bits allowed to be set is */\r
+ /* shifted out of range of bits of channels in single or differential mode. */\r
+ MODIFY_REG(ADCx->DIFSEL,\r
+ Channel & ADC_SINGLEDIFF_CHANNEL_MASK,\r
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));\r
+}\r
+\r
+/**\r
+ * @brief Get mode single-ended or differential input of the selected\r
+ * ADC channel.\r
+ * @note When configuring a channel 'i' in differential mode,\r
+ * the channel 'i+1' is not usable separately.\r
+ * Therefore, to ensure a channel is configured in single-ended mode,\r
+ * the configuration of channel itself and the channel 'i-1' must be\r
+ * read back (to ensure that the selected channel channel has not been\r
+ * configured in differential mode by the previous channel).\r
+ * @note Refer to Reference Manual to ensure the selected channel is\r
+ * available in differential mode.\r
+ * For example, internal channels (VrefInt, TempSensor, ...) are\r
+ * not available in differential mode.\r
+ * @note When configuring a channel 'i' in differential mode,\r
+ * the channel 'i+1' is not usable separately.\r
+ * @note On STM32H7, some channels are internally fixed to single-ended inputs\r
+ * configuration:\r
+ * - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19\r
+ * - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19\r
+ * - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19\r
+ * @note One or several values can be selected. In this case, the value\r
+ * returned is null if all channels are in single ended-mode.\r
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)\r
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff\r
+ * @param ADCx ADC instance\r
+ * @param Channel This parameter can be a combination of the following values:\r
+ * @arg @ref LL_ADC_CHANNEL_1\r
+ * @arg @ref LL_ADC_CHANNEL_2\r
+ * @arg @ref LL_ADC_CHANNEL_3\r
+ * @arg @ref LL_ADC_CHANNEL_4\r
+ * @arg @ref LL_ADC_CHANNEL_5\r
+ * @arg @ref LL_ADC_CHANNEL_10\r
+ * @arg @ref LL_ADC_CHANNEL_11\r
+ * @arg @ref LL_ADC_CHANNEL_12\r
+ * @arg @ref LL_ADC_CHANNEL_13\r
+ * @arg @ref LL_ADC_CHANNEL_14\r
+ * @arg @ref LL_ADC_CHANNEL_15\r
+ * @arg @ref LL_ADC_CHANNEL_16\r
+ * @arg @ref LL_ADC_CHANNEL_17\r
+ * @arg @ref LL_ADC_CHANNEL_18\r
+ * @arg @ref LL_ADC_CHANNEL_19\r
+ * @retval 0: channel in single-ended mode, else: channel in differential mode\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set ADC analog watchdog monitored channels:\r
+ * a single channel, multiple channels or all channels,\r
+ * on ADC groups regular and-or injected.\r
+ * @note Once monitored channels are selected, analog watchdog\r
+ * is enabled.\r
+ * @note In case of need to define a single channel to monitor\r
+ * with analog watchdog from sequencer channel definition,\r
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().\r
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog\r
+ * instance:\r
+ * - AWD standard (instance AWD1):\r
+ * - channels monitored: can monitor 1 channel or all channels.\r
+ * - groups monitored: ADC groups regular and-or injected.\r
+ * - resolution: resolution is not limited (corresponds to\r
+ * ADC resolution configured).\r
+ * - AWD flexible (instances AWD2, AWD3):\r
+ * - channels monitored: flexible on channels monitored, selection is\r
+ * channel wise, from from 1 to all channels.\r
+ * Specificity of this analog watchdog: Multiple channels can\r
+ * be selected. For example:\r
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)\r
+ * - groups monitored: not selection possible (monitoring on both\r
+ * groups regular and injected).\r
+ * Channels selected are monitored on groups regular and injected:\r
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters\r
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)\r
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is\r
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits\r
+ * the 2 LSB are ignored.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n\r
+ * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n\r
+ * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n\r
+ * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n\r
+ * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n\r
+ * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels\r
+ * @param ADCx ADC instance\r
+ * @param AWDy This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD1\r
+ * @arg @ref LL_ADC_AWD2\r
+ * @arg @ref LL_ADC_AWD3\r
+ * @param AWDChannelGroup This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD_DISABLE\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)\r
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)\r
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)\r
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)\r
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)\r
+ * \r
+ * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n\r
+ * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n\r
+ * (2) On STM32H7, parameter available only on ADC instance: ADC2.\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)\r
+{\r
+ /* Set bits with content of parameter "AWDChannelGroup" with bits position */\r
+ /* in register and register position depending on parameter "AWDy". */\r
+ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */\r
+ /* containing other bits reserved for other purpose. */\r
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)\r
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));\r
+\r
+ MODIFY_REG(*preg,\r
+ (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),\r
+ AWDChannelGroup & AWDy);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC analog watchdog monitored channel.\r
+ * @note Usage of the returned channel number:\r
+ * - To reinject this channel into another function LL_ADC_xxx:\r
+ * the returned channel number is only partly formatted on definition\r
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\r
+ * with parts of literals LL_ADC_CHANNEL_x or using\r
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * Then the selected literal LL_ADC_CHANNEL_x can be used\r
+ * as parameter for another function.\r
+ * - To get the channel number in decimal format:\r
+ * process the returned value with the helper macro\r
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\r
+ * Applicable only when the analog watchdog is set to monitor\r
+ * one channel.\r
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog\r
+ * instance:\r
+ * - AWD standard (instance AWD1):\r
+ * - channels monitored: can monitor 1 channel or all channels.\r
+ * - groups monitored: ADC groups regular and-or injected.\r
+ * - resolution: resolution is not limited (corresponds to\r
+ * ADC resolution configured).\r
+ * - AWD flexible (instances AWD2, AWD3):\r
+ * - channels monitored: flexible on channels monitored, selection is\r
+ * channel wise, from from 1 to all channels.\r
+ * Specificity of this analog watchdog: Multiple channels can\r
+ * be selected. For example:\r
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)\r
+ * - groups monitored: not selection possible (monitoring on both\r
+ * groups regular and injected).\r
+ * Channels selected are monitored on groups regular and injected:\r
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters\r
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)\r
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is\r
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits\r
+ * the 2 LSB are ignored.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n\r
+ * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n\r
+ * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n\r
+ * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n\r
+ * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n\r
+ * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels\r
+ * @param ADCx ADC instance\r
+ * @param AWDy This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD1\r
+ * @arg @ref LL_ADC_AWD2 (1)\r
+ * @arg @ref LL_ADC_AWD3 (1)\r
+ *\r
+ * (1) On this AWD number, monitored channel can be retrieved\r
+ * if only 1 channel is programmed (or none or all channels).\r
+ * This function cannot retrieve monitored channel if\r
+ * multiple channels are programmed simultaneously\r
+ * by bitfield.\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD_DISABLE\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)\r
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ\r
+ * \r
+ * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)\r
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));\r
+\r
+ register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);\r
+\r
+ /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */\r
+ /* (parameter value LL_ADC_AWD_DISABLE). */\r
+ /* Else, the selected AWD is enabled and is monitoring a group of channels */\r
+ /* or a single channel. */\r
+ if(AnalogWDMonitChannels != 0UL)\r
+ {\r
+ if(AWDy == LL_ADC_AWD1)\r
+ {\r
+ if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)\r
+ {\r
+ /* AWD monitoring a group of channels */\r
+ AnalogWDMonitChannels = (( AnalogWDMonitChannels\r
+ | (ADC_AWD_CR23_CHANNEL_MASK)\r
+ )\r
+ & (~(ADC_CFGR_AWD1CH))\r
+ );\r
+ }\r
+ else\r
+ {\r
+ /* AWD monitoring a single channel */\r
+ AnalogWDMonitChannels = (AnalogWDMonitChannels\r
+ | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))\r
+ );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)\r
+ {\r
+ /* AWD monitoring a group of channels */\r
+ AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK\r
+ | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))\r
+ );\r
+ }\r
+ else\r
+ {\r
+ /* AWD monitoring a single channel */\r
+ /* AWD monitoring a group of channels */\r
+ AnalogWDMonitChannels = ( AnalogWDMonitChannels\r
+ | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)\r
+ | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)\r
+ );\r
+ }\r
+ }\r
+ }\r
+\r
+ return AnalogWDMonitChannels;\r
+}\r
+\r
+/**\r
+ * @brief Set ADC analog watchdog threshold value of threshold\r
+ * high or low.\r
+ * @note In case of ADC resolution different of 12 bits,\r
+ * analog watchdog thresholds data require a specific shift.\r
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().\r
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog\r
+ * instance:\r
+ * - AWD standard (instance AWD1):\r
+ * - channels monitored: can monitor 1 channel or all channels.\r
+ * - groups monitored: ADC groups regular and-or injected.\r
+ * - resolution: resolution is not limited (corresponds to\r
+ * ADC resolution configured).\r
+ * - AWD flexible (instances AWD2, AWD3):\r
+ * - channels monitored: flexible on channels monitored, selection is\r
+ * channel wise, from from 1 to all channels.\r
+ * Specificity of this analog watchdog: Multiple channels can\r
+ * be selected. For example:\r
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)\r
+ * - groups monitored: not selection possible (monitoring on both\r
+ * groups regular and injected).\r
+ * Channels selected are monitored on groups regular and injected:\r
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters\r
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)\r
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is\r
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits\r
+ * the 2 LSB are ignored.\r
+ * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are\r
+ * impacted: the comparison of analog watchdog thresholds is done\r
+ * on oversampling intermediate computation (after ratio, before shift\r
+ * application): intermediate register bitfield [32:7]\r
+ * (26 most significant bits).\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either ADC groups regular or injected.\r
+ * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n\r
+ * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n\r
+ * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n\r
+ * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n\r
+ * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n\r
+ * TR3 LT3 LL_ADC_SetAnalogWDThresholds\r
+ * @param ADCx ADC instance\r
+ * @param AWDy This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD1\r
+ * @arg @ref LL_ADC_AWD2\r
+ * @arg @ref LL_ADC_AWD3\r
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH\r
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW\r
+ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)\r
+{\r
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */\r
+ /* position in register and register position depending on parameters */\r
+ /* "AWDThresholdsHighLow" and "AWDy". */\r
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */\r
+ /* containing other bits reserved for other purpose. */\r
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)\r
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)\r
+ + (AWDThresholdsHighLow));\r
+\r
+ MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC analog watchdog threshold value of threshold high,\r
+ * threshold low or raw data with ADC thresholds high and low\r
+ * concatenated.\r
+ * @note In case of ADC resolution different of 12 bits,\r
+ * analog watchdog thresholds data require a specific shift.\r
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().\r
+ * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n\r
+ * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n\r
+ * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n\r
+ * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n\r
+ * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n\r
+ * TR3 LT3 LL_ADC_GetAnalogWDThresholds\r
+ * @param ADCx ADC instance\r
+ * @param AWDy This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD1\r
+ * @arg @ref LL_ADC_AWD2\r
+ * @arg @ref LL_ADC_AWD3\r
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH\r
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF\r
+*/\r
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)\r
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)\r
+ + (AWDThresholdsHighLow));\r
+\r
+ return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set ADC oversampling scope: ADC groups regular and-or injected\r
+ * (availability of ADC group injected depends on STM32 families).\r
+ * @note If both groups regular and injected are selected,\r
+ * specify behavior of ADC group injected interrupting\r
+ * group regular: when ADC group injected is triggered,\r
+ * the oversampling on ADC group regular is either\r
+ * temporary stopped and continued, or resumed from start\r
+ * (oversampler buffer reset).\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n\r
+ * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n\r
+ * CFGR2 ROVSM LL_ADC_SetOverSamplingScope\r
+ * @param ADCx ADC instance\r
+ * @param OvsScope This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OVS_DISABLE\r
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED\r
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED\r
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED\r
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)\r
+{\r
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC oversampling scope: ADC groups regular and-or injected\r
+ * (availability of ADC group injected depends on STM32 families).\r
+ * @note If both groups regular and injected are selected,\r
+ * specify behavior of ADC group injected interrupting\r
+ * group regular: when ADC group injected is triggered,\r
+ * the oversampling on ADC group regular is either\r
+ * temporary stopped and continued, or resumed from start\r
+ * (oversampler buffer reset).\r
+ * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n\r
+ * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n\r
+ * CFGR2 ROVSM LL_ADC_GetOverSamplingScope\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_OVS_DISABLE\r
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED\r
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED\r
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED\r
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC oversampling discontinuous mode (triggered mode)\r
+ * on the selected ADC group.\r
+ * @note Number of oversampled conversions are done either in:\r
+ * - continuous mode (all conversions of oversampling ratio\r
+ * are done from 1 trigger)\r
+ * - discontinuous mode (each conversion of oversampling ratio\r
+ * needs a trigger)\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on group regular.\r
+ * @note On this STM32 serie, oversampling discontinuous mode\r
+ * (triggered mode) can be used only when oversampling is\r
+ * set on group regular only and in resumed mode.\r
+ * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont\r
+ * @param ADCx ADC instance\r
+ * @param OverSamplingDiscont This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OVS_REG_CONT\r
+ * @arg @ref LL_ADC_OVS_REG_DISCONT\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)\r
+{\r
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC oversampling discontinuous mode (triggered mode)\r
+ * on the selected ADC group.\r
+ * @note Number of oversampled conversions are done either in:\r
+ * - continuous mode (all conversions of oversampling ratio\r
+ * are done from 1 trigger)\r
+ * - discontinuous mode (each conversion of oversampling ratio\r
+ * needs a trigger)\r
+ * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont\r
+ * @param ADCx ADC instance\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_OVS_REG_CONT\r
+ * @arg @ref LL_ADC_OVS_REG_DISCONT\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC oversampling\r
+ * (impacting both ADC groups regular and injected)\r
+ * @note This function set the 2 items of oversampling configuration:\r
+ * - ratio\r
+ * - shift\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be disabled or enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n\r
+ * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift\r
+ * @param ADCx ADC instance\r
+ * @param Ratio This parameter can be in the range from 1 to 1024.\r
+ * @param Shift This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)\r
+{\r
+ MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC oversampling ratio\r
+ * (impacting both ADC groups regular and injected)\r
+ * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio\r
+ * @param ADCx ADC instance\r
+ * @retval Ratio This parameter can be in the from 1 to 1024.\r
+*/\r
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)\r
+{\r
+ return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC oversampling shift\r
+ * (impacting both ADC groups regular and injected)\r
+ * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift\r
+ * @param ADCx ADC instance\r
+ * @retval Shift This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10\r
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11\r
+*/\r
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Set ADC boost mode.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC boost must be configured, without calibration on going, without conversion\r
+ * on going on group regular.\r
+ * @rmtoll CR BOOST LL_ADC_SetBoostMode\r
+ * @param ADCx ADC instance\r
+ * @param BoostMode This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_BOOST_MODE_6MHZ25\r
+ * @arg @ref LL_ADC_BOOST_MODE_12MHZ5\r
+ * @arg @ref LL_ADC_BOOST_MODE_20MHZ\r
+ * @arg @ref LL_ADC_BOOST_MODE_25MHZ\r
+ * @arg @ref LL_ADC_BOOST_MODE_50MHZ\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)\r
+{\r
+ if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */\r
+ {\r
+ MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));\r
+ }\r
+ else /* Cut 2.x */\r
+ {\r
+ MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get ADC boost mode.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC boost must be configured, without calibration on going, without conversion\r
+ * on going on group regular.\r
+ * @rmtoll CR BOOST LL_ADC_GetBoostMode\r
+ * @param ADCx ADC instance\r
+ * @retval 0: Boost disabled 1: Boost enabled\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)\r
+{\r
+ if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */\r
+ {\r
+ return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);\r
+ }\r
+ else /* Cut 2.x */\r
+ {\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set ADC multimode configuration to operate in independent mode\r
+ * or multimode (for devices with several ADC instances).\r
+ * @note If multimode configuration: the selected ADC instance is\r
+ * either master or slave depending on hardware.\r
+ * Refer to reference manual.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * All ADC instances of the ADC common group must be disabled.\r
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each\r
+ * ADC instance or by using helper macro\r
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\r
+ * @rmtoll CCR DUAL LL_ADC_SetMultimode\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @param Multimode This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL\r
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)\r
+{\r
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC multimode configuration to operate in independent mode\r
+ * or multimode (for devices with several ADC instances).\r
+ * @note If multimode configuration: the selected ADC instance is\r
+ * either master or slave depending on hardware.\r
+ * Refer to reference manual.\r
+ * @rmtoll CCR DUAL LL_ADC_GetMultimode\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL\r
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT\r
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC multimode conversion data transfer: no transfer\r
+ * or transfer by DMA.\r
+ * @note If ADC multimode transfer by DMA is not selected:\r
+ * each ADC uses its own DMA channel, with its individual\r
+ * DMA transfer settings.\r
+ * If ADC multimode transfer by DMA is selected:\r
+ * One DMA channel is used for both ADC (DMA of ADC master)\r
+ * Specifies the DMA requests mode:\r
+ * - Limited mode (One shot mode): DMA transfer requests are stopped\r
+ * when number of DMA data transfers (number of\r
+ * ADC conversions) is reached.\r
+ * This ADC mode is intended to be used with DMA mode non-circular.\r
+ * - Unlimited mode: DMA transfer requests are unlimited,\r
+ * whatever number of DMA data transfers (number of\r
+ * ADC conversions).\r
+ * This ADC mode is intended to be used with DMA mode circular.\r
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to\r
+ * mode non-circular:\r
+ * when DMA transfers size will be reached, DMA will stop transfers of\r
+ * ADC conversions data ADC will raise an overrun error\r
+ * (overrun flag and interruption if enabled).\r
+ * @note How to retrieve multimode conversion data:\r
+ * Whatever multimode transfer by DMA setting: using function\r
+ * @ref LL_ADC_REG_ReadMultiConversionData32().\r
+ * If ADC multimode transfer by DMA is selected: conversion data\r
+ * is a raw data with ADC master and slave concatenated.\r
+ * A macro is available to get the conversion data of\r
+ * ADC master or ADC slave: see helper macro\r
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * All ADC instances of the ADC common group must be disabled\r
+ * or enabled without conversion on going on group regular.\r
+ * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @param MultiDMATransfer This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC\r
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B\r
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)\r
+{\r
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC multimode conversion data transfer: no transfer\r
+ * or transfer by DMA.\r
+ * @note If ADC multimode transfer by DMA is not selected:\r
+ * each ADC uses its own DMA channel, with its individual\r
+ * DMA transfer settings.\r
+ * If ADC multimode transfer by DMA is selected:\r
+ * One DMA channel is used for both ADC (DMA of ADC master)\r
+ * Specifies the DMA requests mode:\r
+ * - Limited mode (One shot mode): DMA transfer requests are stopped\r
+ * when number of DMA data transfers (number of\r
+ * ADC conversions) is reached.\r
+ * This ADC mode is intended to be used with DMA mode non-circular.\r
+ * - Unlimited mode: DMA transfer requests are unlimited,\r
+ * whatever number of DMA data transfers (number of\r
+ * ADC conversions).\r
+ * This ADC mode is intended to be used with DMA mode circular.\r
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to\r
+ * mode non-circular:\r
+ * when DMA transfers size will be reached, DMA will stop transfers of\r
+ * ADC conversions data ADC will raise an overrun error\r
+ * (overrun flag and interruption if enabled).\r
+ * @note How to retrieve multimode conversion data:\r
+ * Whatever multimode transfer by DMA setting: using function\r
+ * @ref LL_ADC_REG_ReadMultiConversionData32().\r
+ * If ADC multimode transfer by DMA is selected: conversion data\r
+ * is a raw data with ADC master and slave concatenated.\r
+ * A macro is available to get the conversion data of\r
+ * ADC master or ADC slave: see helper macro\r
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\r
+ * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC\r
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B\r
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));\r
+}\r
+\r
+/**\r
+ * @brief Set ADC multimode delay between 2 sampling phases.\r
+ * @note The sampling delay range depends on ADC resolution:\r
+ * - ADC resolution 12 bits can have maximum delay of 12 cycles.\r
+ * - ADC resolution 10 bits can have maximum delay of 10 cycles.\r
+ * - ADC resolution 8 bits can have maximum delay of 8 cycles.\r
+ * - ADC resolution 6 bits can have maximum delay of 6 cycles.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * All ADC instances of the ADC common group must be disabled.\r
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each\r
+ * ADC instance or by using helper macro helper macro\r
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\r
+ * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @param MultiTwoSamplingDelay This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)\r
+ *\r
+ * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.\r
+ * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.\r
+ * (3) Parameter available only if ADC resolution is 10 or 8 bits.\r
+ * (4) Parameter available only if ADC resolution is 16 or 14 bits.\r
+ * (5) Parameter available only if ADC resolution is 16 bits.\r
+ * (6) Parameter available only if ADC resolution is 12 bits.\r
+ * (7) Parameter available only if ADC resolution is 16 or 14 bits.\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)\r
+{\r
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC multimode delay between 2 sampling phases.\r
+ * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)\r
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)\r
+ *\r
+ * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.\r
+ * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.\r
+ * (3) Parameter available only if ADC resolution is 10 or 8 bits.\r
+ * (4) Parameter available only if ADC resolution is 16 or 14 bits.\r
+ * (5) Parameter available only if ADC resolution is 16 bits.\r
+ * (6) Parameter available only if ADC resolution is 12 bits.\r
+ * (7) Parameter available only if ADC resolution is 16 or 14 bits.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Put ADC instance in deep power down state.\r
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down\r
+ * state, the internal analog calibration is lost. After exiting from\r
+ * deep power down, calibration must be relaunched or calibration factor\r
+ * (preliminarily saved) must be set back into calibration register.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be ADC disabled.\r
+ * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_DEEPPWD);\r
+}\r
+\r
+/**\r
+ * @brief Disable ADC deep power down mode.\r
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down\r
+ * state, the internal analog calibration is lost. After exiting from\r
+ * deep power down, calibration must be relaunched or calibration factor\r
+ * (preliminarily saved) must be set back into calibration register.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be ADC disabled.\r
+ * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));\r
+}\r
+\r
+/**\r
+ * @brief Get the selected ADC instance deep power down state.\r
+ * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled\r
+ * @param ADCx ADC instance\r
+ * @retval 0: deep power down is disabled, 1: deep power down is enabled.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Enable ADC instance internal voltage regulator.\r
+ * @note On this STM32 serie, after ADC internal voltage regulator enable,\r
+ * a delay for ADC internal voltage regulator stabilization\r
+ * is required before performing a ADC calibration or ADC enable.\r
+ * Refer to device datasheet, parameter tADCVREG_STUP.\r
+ * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be ADC disabled.\r
+ * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_ADVREGEN);\r
+}\r
+\r
+/**\r
+ * @brief Disable ADC internal voltage regulator.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be ADC disabled.\r
+ * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));\r
+}\r
+\r
+/**\r
+ * @brief Get the selected ADC instance internal voltage regulator state.\r
+ * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled\r
+ * @param ADCx ADC instance\r
+ * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Enable the selected ADC instance.\r
+ * @note On this STM32 serie, after ADC enable, a delay for\r
+ * ADC internal analog stabilization is required before performing a\r
+ * ADC conversion start.\r
+ * Refer to device datasheet, parameter tSTAB.\r
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\r
+ * is enabled and when conversion clock is active.\r
+ * (not only core clock: this ADC has a dual clock domain)\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be ADC disabled and ADC internal voltage regulator enabled.\r
+ * @rmtoll CR ADEN LL_ADC_Enable\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_ADEN);\r
+}\r
+\r
+/**\r
+ * @brief Disable the selected ADC instance.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be not disabled. Must be enabled without conversion on going\r
+ * on either groups regular or injected.\r
+ * @rmtoll CR ADDIS LL_ADC_Disable\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_ADDIS);\r
+}\r
+\r
+/**\r
+ * @brief Get the selected ADC instance enable state.\r
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\r
+ * is enabled and when conversion clock is active.\r
+ * (not only core clock: this ADC has a dual clock domain)\r
+ * @rmtoll CR ADEN LL_ADC_IsEnabled\r
+ * @param ADCx ADC instance\r
+ * @retval 0: ADC is disabled, 1: ADC is enabled.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get the selected ADC instance disable state.\r
+ * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing\r
+ * @param ADCx ADC instance\r
+ * @retval 0: no ADC disable command on going.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Start ADC calibration in the mode single-ended\r
+ * or differential (for devices with differential mode available).\r
+ * @note On this STM32 serie, a minimum number of ADC clock cycles\r
+ * are required between ADC end of calibration and ADC enable.\r
+ * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.\r
+ * @note Calibration duration:\r
+ * - Calibration of offset: 520 ADC clock cycles\r
+ * - Calibration of linearity: 131072 ADC clock cycles\r
+ * @note For devices with differential mode available:\r
+ * Calibration of offset is specific to each of\r
+ * single-ended and differential modes\r
+ * (calibration run must be performed for each of these\r
+ * differential modes, if used afterwards and if the application\r
+ * requires their calibration).\r
+ * Calibration of linearity is common to both\r
+ * single-ended and differential modes\r
+ * (calibration run can be performed only once).\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be ADC disabled.\r
+ * @rmtoll CR ADCAL LL_ADC_StartCalibration\n\r
+ * CR ADCALDIF LL_ADC_StartCalibration\n\r
+ * CR ADCALLIN LL_ADC_StartCalibration\r
+ * @param ADCx ADC instance\r
+ * @param CalibrationMode This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_CALIB_OFFSET\r
+ * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY\r
+ * @param SingleDiff This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_SINGLE_ENDED\r
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC calibration state.\r
+ * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing\r
+ * @param ADCx ADC instance\r
+ * @retval 0: calibration complete, 1: calibration in progress.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start ADC group regular conversion.\r
+ * @note On this STM32 serie, this function is relevant for both\r
+ * internal trigger (SW start) and external trigger:\r
+ * - If ADC trigger has been set to software start, ADC conversion\r
+ * starts immediately.\r
+ * - If ADC trigger has been set to external trigger, ADC conversion\r
+ * will start at next trigger event (on the selected trigger edge)\r
+ * following the ADC start conversion command.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be enabled without conversion on going on group regular,\r
+ * without conversion stop command on going on group regular,\r
+ * without ADC disable command on going.\r
+ * @rmtoll CR ADSTART LL_ADC_REG_StartConversion\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_ADSTART);\r
+}\r
+\r
+/**\r
+ * @brief Stop ADC group regular conversion.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be enabled with conversion on going on group regular,\r
+ * without ADC disable command on going.\r
+ * @rmtoll CR ADSTP LL_ADC_REG_StopConversion\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_ADSTP);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion state.\r
+ * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing\r
+ * @param ADCx ADC instance\r
+ * @retval 0: no conversion is on going on ADC group regular.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular command of conversion stop state\r
+ * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing\r
+ * @param ADCx ADC instance\r
+ * @retval 0: no command of conversion stop is on going on ADC group regular.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion data, range fit for\r
+ * all ADC configurations: all ADC resolutions and\r
+ * all oversampling increased data width (for devices\r
+ * with feature oversampling).\r
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32\r
+ * @param ADCx ADC instance\r
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion data, range fit for\r
+ * ADC resolution 16 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.\r
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16\r
+ * @param ADCx ADC instance\r
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion data, range fit for\r
+ * ADC resolution 14 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.\r
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14\r
+ * @param ADCx ADC instance\r
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3FF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion data, range fit for\r
+ * ADC resolution 12 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.\r
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12\r
+ * @param ADCx ADC instance\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion data, range fit for\r
+ * ADC resolution 10 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.\r
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10\r
+ * @param ADCx ADC instance\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion data, range fit for\r
+ * ADC resolution 8 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.\r
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8\r
+ * @param ADCx ADC instance\r
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF\r
+ */\r
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)\r
+{\r
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\r
+}\r
+/**\r
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave\r
+ * or raw data with ADC master and slave concatenated.\r
+ * @note If raw data with ADC master and slave concatenated is retrieved,\r
+ * a macro is available to get the conversion data of\r
+ * ADC master or ADC slave: see helper macro\r
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\r
+ * (however this macro is mainly intended for multimode\r
+ * transfer by DMA, because this function can do the same\r
+ * by getting multimode conversion data of ADC master or ADC slave\r
+ * separately).\r
+ * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n\r
+ * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @param ConversionData This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_MULTI_MASTER\r
+ * @arg @ref LL_ADC_MULTI_SLAVE\r
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE\r
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)\r
+{\r
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,\r
+ ConversionData)\r
+ >> (POSITION_VAL(ConversionData) & 0x1FUL)\r
+ );\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start ADC group injected conversion.\r
+ * @note On this STM32 serie, this function is relevant for both\r
+ * internal trigger (SW start) and external trigger:\r
+ * - If ADC trigger has been set to software start, ADC conversion\r
+ * starts immediately.\r
+ * - If ADC trigger has been set to external trigger, ADC conversion\r
+ * will start at next trigger event (on the selected trigger edge)\r
+ * following the ADC start conversion command.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be enabled without conversion on going on group injected,\r
+ * without conversion stop command on going on group injected,\r
+ * without ADC disable command on going.\r
+ * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_JADSTART);\r
+}\r
+\r
+/**\r
+ * @brief Stop ADC group injected conversion.\r
+ * @note On this STM32 serie, setting of this feature is conditioned to\r
+ * ADC state:\r
+ * ADC must be enabled with conversion on going on group injected,\r
+ * without ADC disable command on going.\r
+ * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)\r
+{\r
+ /* Note: Write register with some additional bits forced to state reset */\r
+ /* instead of modifying only the selected bit for this function, */\r
+ /* to not interfere with bits with HW property "rs". */\r
+ MODIFY_REG(ADCx->CR,\r
+ ADC_CR_BITS_PROPERTY_RS,\r
+ ADC_CR_JADSTP);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion state.\r
+ * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing\r
+ * @param ADCx ADC instance\r
+ * @retval 0: no conversion is on going on ADC group injected.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected command of conversion stop state\r
+ * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing\r
+ * @param ADCx ADC instance\r
+ * @retval 0: no command of conversion stop is on going on ADC group injected.\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group regular conversion data, range fit for\r
+ * all ADC configurations: all ADC resolutions and\r
+ * all oversampling increased data width (for devices\r
+ * with feature oversampling).\r
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n\r
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n\r
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n\r
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\r
+\r
+ return (uint32_t)(READ_BIT(*preg,\r
+ ADC_JDR1_JDATA)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion data, range fit for\r
+ * ADC resolution 16 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.\r
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n\r
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n\r
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n\r
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData16\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\r
+\r
+ return (uint16_t)(READ_BIT(*preg,\r
+ ADC_JDR1_JDATA)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion data, range fit for\r
+ * ADC resolution 14 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.\r
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n\r
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n\r
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n\r
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData14\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\r
+\r
+ return (uint16_t)(READ_BIT(*preg,\r
+ ADC_JDR1_JDATA)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion data, range fit for\r
+ * ADC resolution 12 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.\r
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n\r
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n\r
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n\r
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\r
+\r
+ return (uint16_t)(READ_BIT(*preg,\r
+ ADC_JDR1_JDATA)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion data, range fit for\r
+ * ADC resolution 10 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.\r
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n\r
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n\r
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n\r
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData10\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF\r
+ */\r
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\r
+\r
+ return (uint16_t)(READ_BIT(*preg,\r
+ ADC_JDR1_JDATA)\r
+ );\r
+}\r
+\r
+/**\r
+ * @brief Get ADC group injected conversion data, range fit for\r
+ * ADC resolution 8 bits.\r
+ * @note For devices with feature oversampling: Oversampling\r
+ * can increase data width, function for extended range\r
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.\r
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n\r
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n\r
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n\r
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData8\r
+ * @param ADCx ADC instance\r
+ * @param Rank This parameter can be one of the following values:\r
+ * @arg @ref LL_ADC_INJ_RANK_1\r
+ * @arg @ref LL_ADC_INJ_RANK_2\r
+ * @arg @ref LL_ADC_INJ_RANK_3\r
+ * @arg @ref LL_ADC_INJ_RANK_4\r
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF\r
+ */\r
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)\r
+{\r
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\r
+\r
+ return (uint8_t)(READ_BIT(*preg,\r
+ ADC_JDR1_JDATA)\r
+ );\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Get flag ADC ready.\r
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\r
+ * is enabled and when conversion clock is active.\r
+ * (not only core clock: this ADC has a dual clock domain)\r
+ * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC group regular end of unitary conversion.\r
+ * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC group regular end of sequence conversions.\r
+ * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC group regular overrun.\r
+ * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC group regular end of sampling phase.\r
+ * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC group injected end of unitary conversion.\r
+ * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC group injected end of sequence conversions.\r
+ * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC group injected contexts queue overflow.\r
+ * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC analog watchdog 1 flag\r
+ * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC analog watchdog 2.\r
+ * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag ADC analog watchdog 3.\r
+ * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC ready.\r
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\r
+ * is enabled and when conversion clock is active.\r
+ * (not only core clock: this ADC has a dual clock domain)\r
+ * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC group regular end of unitary conversion.\r
+ * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC group regular end of sequence conversions.\r
+ * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC group regular overrun.\r
+ * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC group regular end of sampling phase.\r
+ * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC group injected end of unitary conversion.\r
+ * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC group injected end of sequence conversions.\r
+ * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC group injected contexts queue overflow.\r
+ * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC analog watchdog 1.\r
+ * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC analog watchdog 2.\r
+ * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);\r
+}\r
+\r
+/**\r
+ * @brief Clear flag ADC analog watchdog 3.\r
+ * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)\r
+{\r
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC ready of the ADC master.\r
+ * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC ready of the ADC slave.\r
+ * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.\r
+ * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.\r
+ * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.\r
+ * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.\r
+ * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular overrun of the ADC master.\r
+ * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular overrun of the ADC slave.\r
+ * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC master.\r
+ * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.\r
+ * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.\r
+ * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.\r
+ * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.\r
+ * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.\r
+ * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.\r
+ * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.\r
+ * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.\r
+ * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave.\r
+ * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.\r
+ * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.\r
+ * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.\r
+ * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.\r
+ * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3\r
+ * @param ADCxy_COMMON ADC common instance\r
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)\r
+{\r
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable ADC ready.\r
+ * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC group regular end of unitary conversion.\r
+ * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOC);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC group regular end of sequence conversions.\r
+ * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOS);\r
+}\r
+\r
+/**\r
+ * @brief Enable ADC group regular interruption overrun.\r
+ * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_OVR);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC group regular end of sampling.\r
+ * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC group injected end of unitary conversion.\r
+ * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC group injected end of sequence conversions.\r
+ * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC group injected context queue overflow.\r
+ * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC analog watchdog 1.\r
+ * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC analog watchdog 2.\r
+ * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);\r
+}\r
+\r
+/**\r
+ * @brief Enable interruption ADC analog watchdog 3.\r
+ * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)\r
+{\r
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC ready.\r
+ * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC group regular end of unitary conversion.\r
+ * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC group regular end of sequence conversions.\r
+ * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC group regular overrun.\r
+ * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC group regular end of sampling.\r
+ * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC group regular end of unitary conversion.\r
+ * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC group injected end of sequence conversions.\r
+ * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC group injected context queue overflow.\r
+ * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC analog watchdog 1.\r
+ * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC analog watchdog 2.\r
+ * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);\r
+}\r
+\r
+/**\r
+ * @brief Disable interruption ADC analog watchdog 3.\r
+ * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3\r
+ * @param ADCx ADC instance\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)\r
+{\r
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC ready\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC group regular end of unitary conversion\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC group regular end of sequence conversions\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC group regular overrun\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC group regular end of sampling\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC group injected end of unitary conversion\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC group injected end of sequence conversions\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC group injected context queue overflow interrupt state\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption ADC analog watchdog 1\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption Get ADC analog watchdog 2\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Get state of interruption Get ADC analog watchdog 3\r
+ * (0: interrupt disabled, 1: interrupt enabled).\r
+ * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3\r
+ * @param ADCx ADC instance\r
+ * @retval State of bit (1 or 0).\r
+ */\r
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)\r
+{\r
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(USE_FULL_LL_DRIVER)\r
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization of some features of ADC common parameters and multimode */\r
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);\r
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);\r
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);\r
+\r
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */\r
+/* (availability of ADC group injected depends on STM32 families) */\r
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);\r
+\r
+/* Initialization of some features of ADC instance */\r
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);\r
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);\r
+\r
+/* Initialization of some features of ADC instance and ADC group regular */\r
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);\r
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);\r
+\r
+/* Initialization of some features of ADC instance and ADC group injected */\r
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);\r
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* USE_FULL_LL_DRIVER */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* ADC1 || ADC2 || ADC3 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32H7xx_LL_ADC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
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+ol\r
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+ul\r
+{margin-bottom:0in;}\r
+-->\r
+</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif";} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="7170"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->\r
+ <meta content="MCD Application Team" name="author"></head>\r
+<body link="blue" vlink="blue">\r
+ <div class="WordSection1">\r
+ <p class="MsoNormal"><span style="font-family: "Arial","sans-serif";"><o:p> </o:p></span></p>\r
+ <div align="center">\r
+ <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+ <tbody>\r
+ <tr>\r
+ <td style="padding: 0in;" valign="top">\r
+ <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+ <tbody>\r
+ <tr style="">\r
+ <td style="padding: 0in 5.4pt;" valign="top">\r
+ <p class="MsoNormal"><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"><a href="../../Release_Notes.html">Back to Release\r
+ page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+ </td>\r
+ </tr>\r
+ <tr style="">\r
+ <td style="padding: 1.5pt;">\r
+ <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release\r
+Notes\r
+ for STM32H7xx HAL Drivers</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>\r
+ <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright\r
+2017\r
+ STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+ <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"><img style="border: 0px solid ; width: 171px; height: 126px;" alt="" id="_x0000_i1026" src="../../_htmresc/st_logo.png"></span></p>\r
+ <p class="MsoNormal" style="text-align: center;" align="center"><span lang="fr"><font face="Arial">The hardware\r
+abstraction layer (HAL) provides low level drivers and the hardware\r
+interfacing methods to interact with upper layer (application,\r
+libraries and stacks). It includes a complete set of ready-to-use\r
+APIs, that are feature-oriented instead of IP-Oriented to simplify user\r
+application development</font></span></p>\r
+ <p class="MsoNormal" style="text-align: center;" align="center"><span lang="fr"></span><br>\r
+ <span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+\r
+ </td>\r
+ </tr>\r
+ </tbody>\r
+ </table>\r
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p style="margin: 0px 0px 0px 0in; font-size: medium; font-family: Arial,Helvetica,sans-serif; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; padding-top: 3px; padding-bottom: 3px;">This\r
+software component is licensed by ST under BSD 3-Clause\r
+license, the "License"; You may not use this component except in\r
+compliance with the License. You may obtain a copy of the License at:</p><p style="margin: 0px 0px 0px 0in; font-size: medium; font-family: Arial,Helvetica,sans-serif; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; padding-top: 3px; padding-bottom: 3px; text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank" style="color: blue; text-decoration: underline;">https://opensource.org/licenses/BSD-3-Clause</a></p><table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+ <tbody>\r
+ <tr style="">\r
+ <td style="padding: 0in;" valign="top">\r
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update\r
+ History</span></h2>\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 196px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0RC1\r
+ / 12-December-2018</span></h3>\r
+\r
+ \r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+ Changes</span></u></b></p>\r
+\r
+ \r
+ <ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Add support for VOS0 power regulator voltage scaling with 480MHz over clock.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">General\r
+ updates to fix known defects and enhancements\r
+ implementation.</span></li></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Add Dual core API for system peripherals HAL and LL (<span style="font-weight: bold;">COMP, CORTEX, ETH, FLASH, GPIO, HSEM, MDIOS, PWR, RCC, RTC</span>) </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL ADC:</strong> </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update to support STM32H7 Rev.X and above : 8bits resolution settings. (Driver remains compatible for STM32H7 Rev.Y)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP:</span> Update to support STM32H7 devices rev.X and above.</span><span style="font-family: Verdana; font-size: 10pt;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL FLASH:</strong></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update to support STM32H7 devices rev.X and above.</span><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add support for CRC calculation feature</span><span style="font-family: Verdana; font-size: 10pt;">.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL PWR:</strong></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update to support VOS0 </span><span style="font-family: Verdana; font-size: 10pt;">power regulator voltage scaling</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;">Improve </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">implementation</span><span style="font-family: Verdana; font-size: 10pt;"> of HAL_PWREx_ConfigSupply function.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL RAMECC:</strong></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Fix typo in HAL_RAMECC_EnableNotification and HAL_RAMECC_DisableNotification APIs.</span><span style="font-family: Verdana; font-size: 10pt;"></span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL SAI:</strong></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update to support STM32H7 Rev.X and above</span><span style="font-family: Verdana; font-size: 10pt;">.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO:</span>\r
+Add definition for new AF available in STM32H7\r
+Rev.X: GPIO_AF0_C1DSLEEP, GPIO_AF0_C1DSLEEP, GPIO_AF0_C1SLEEP,\r
+GPIO_AF0_D1PWREN, GPIO_AF0_D2PWREN, GPIO_AF0_C2DSLEEP,\r
+GPIO_AF0_C2SLEEP and </span><span lang="fr"><font color="#000000" face="Segoe UI" size="2">GPIO_AF13_CRS_SYNC</font>.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL SYSTEM</span>: Add new APIs to allow timers break source selection (new feature of </span><span style="font-family: Verdana; font-size: 10pt;">STM32H7 devices rev.X and above)</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 0in; font-size: 13.5pt; font-family: "Times New Roman",serif; font-weight: bold; color: rgb(0, 0, 0); font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; width: 196px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0 / 30-November-2018</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman",serif; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">General updates to fix known defects and<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">implementation<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">enhancements.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add LL drivers :</span><span style="font-family: Verdana; font-size: 10pt;"> <span style="font-weight: bold;">LL_ADC, LL_BDMA, LL_BUS,<span> </span></span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_COMP,<span> </span></span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_CORTEX, LL_CRC, </span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_DAC,</span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;"><span> </span>LL_DMA, LL_DMA2D, LL_DMAMUX, <span> </span></span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_EXTI,<span> </span></span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA,<span> </span></span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_OPAMP,</span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_PWR, LL_RCC, LL_RNG, LL_RTC, </span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL_SPI,</span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;"><span> </span>LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</span></span></li><li><span style="font-family: Verdana; font-size: 10pt;">Introduce the<span> </span><span style="font-weight: bold;">register callback</span> </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">mechanism</span><span style="font-family: Verdana; font-size: 10pt;">. It permits the user to configure dynamically the interrupt callbacks.</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">hal_conf_template.h\r
+is updated to embed the required new define to activate the feature :\r
+one define per HAL driver, example: USE_HAL_I2C_REGISTER_CALLBACKS</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add HAL<span> </span><span style="font-weight: bold;">EXTI</span><span> </span>driver</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add HAL<span> </span><span style="font-weight: bold;">RAMECC</span><span> </span>driver</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL</span><span> </span>: stm32h7xx_hal.c and stm32h7xx_hal.h and stm32h7xx_hal_conf_template.h files</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix register bit field "SYSCFG_PMCR_EPIS_SEL" naming in function "HAL_SYSCFG_ETHInterfaceSelect" in<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">stm32h7xx_hal.c</span><span style="font-family: Verdana; font-size: 10pt;">:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Alignment<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">with the cmsis device include files.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rename internal private macro "IS_EXTI_CONFIG_LINE" to IS_HAL_EXTI_CONFIG_LINE in<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">stm32h7xx_hal.h</span><span style="font-family: Verdana; font-size: 10pt;">: to avoid conflict with HAL EXTI driver.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update stm32h7xx_hal_conf_template.h to add HAL EXTI and HAL RAMECC</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update stm32h7xx_hal_conf_template.h to to put<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">the\r
+include of the MDMA HAL header file before the include of the\r
+JPEG and QSPI HAL header files (as JPEG and QSPI HAL drivers are using\r
+the MDMA)</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">File stm32h7xx_hal.c, update HAL_SetFMCMemorySwappingConfig and HAL_GetFMCMemorySwappingConfig to align with<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">Reference Manual regarding registers and bit defintion naming</span><span style="font-family: Verdana; font-size: 10pt;">. </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">stm32h7xx_hal.c with Driver version number set to V1.4.0</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL ADC:</strong> </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Remove BoostMode from Init structure, this settings is </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">automatically</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>handled by HAL_ADC_Init() function depending of the ADC Clock value.</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">Caution : </span></span><b><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">compatibility</span></b><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;"><span> </span>break with previous version regarding ADC init parameters (ADC_InitTypeDef structure)</span> </span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_CRYP</span><span> </span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Improve error detection in function "CRYP_GCMCCM_SetPayloadPhase_IT"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Improve padding management in funcion "CRYP_GCMCCM_SetPayloadPhase_IT"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix data counter issue in function "CRYP_AESCCM_Process"</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_DFSDM</span><span> </span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rename DFSDM_FILTER_EXT_TRIG_LPTIMx with DFSDM_FILTER_EXT_TRIG_LPTIMx_OUT.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL DMA:</strong> </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add double buffering feature support for BDMA.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4 numerical values (no impact on the functional </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">behavior</span><span style="font-family: Verdana; font-size: 10pt;">)</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add a Clean/Reset of callbacks in HAL_DMA_DeInit()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Remove\r
+FIFO error enabling in "HAL_DMA_Start_IT". when FIFO error monitoring\r
+is requested in IT model, the macro __HAL_DMA_ENABLE_IT can be used to\r
+enable the FIFO error IT at the user Msp function.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Remove check on busy state within "HAL_DMA_DeInit" function : to allow forcing a </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">de-initialization</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>even in busy state</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL ETH:</strong><span> </span>Add check for input buffer against NULL in function HAL_ETH_GetRxDataBuffer.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL FDCAN:</strong> </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Fix counter increment in API HAL_FDCAN_ConfigFilter</span><span style="font-family: Verdana; font-size: 10pt;">.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix comment </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">description<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">of parameter "RxFDFflag" in "FDCAN_ProtocolStatusTypeDef" structure</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix comment </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">description<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">of defines FDCAN_FRAME_FD_NO_BRS and FDCAN_FRAME_FD_BRS</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add a reset of FDCAN operation mode in the "HAL_FDCAN_Init" function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add Error Status callback support:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add parameter "ErrorStatusCallback" in FDCAN_HandleTypeDef structure in stm32h7xx_hal_fdcan.h.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add typedef "pFDCAN_ErrorStatusCallbackTypeDef" </span><span style="font-family: Verdana; font-size: 10pt;">in stm32h7xx_hal_fdcan.h.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add APIs "HAL_FDCAN_RegisterErrorStatusCallback" and "HAL_FDCAN_UnRegisterErrorStatusCallback"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add weak callback "HAL_FDCAN_ErrorStatusCallback"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update "HAL_FDCAN_IRQHandler" function to call the<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">ErrorStatusCallback in case of an error status interrupt.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Improve\r
+error management by adding error codes "HAL_FDCAN_ERROR_FIFO_EMPTY" and\r
+"HAL_FDCAN_ERROR_FIFO_FULL" used in case of FIFO full in\r
+"HAL_FDCAN_AddMessageToTxFifoQ" and FIFO empty in\r
+"HAL_FDCAN_GetRxMessage" functions</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix implementation issue in "HAL_FDCAN_ResetTimeoutCounter" function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Improve\r
+behavior of "HAL_FDCAN_GetRxMessage" and "HAL_FDCAN_GetTxEvent"\r
+functions : operation not allowed in HAL_FDCAN_STATE_READY\r
+state. </span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL FLASH:</strong></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Align driver with the Reference Manual regarding registers and bit defintion naming</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_GPIO</span><span> </span>:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"> Add assert check of parameter GPIO_Pin in function "HAL_GPIO_DeInit"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add assert check against alternate function </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">availability<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">for parameter "GPIOx" in function "HAL_GPIO_Init"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Improve "HAL_GPIO_TogglePin" function </span><span style="font-family: Verdana; font-size: 10pt;">against reentrancy.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Move GPIO clearing to default values in "HAL_GPIO_DeInit" </span><span style="font-family: Verdana; font-size: 10pt;">function<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">after EXTI clearing to avoid unexpected pending interrupts issues.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_HRTIM</span><span> </span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix "HAL_HRTIM_FaultConfig" function regarding FLTINR1 and FLTINR2 registers settings</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update\r
+"HAL_HRTIM_SimpleBaseStop_DMA", "HAL_HRTIM_SimpleOCStop_DMA" and\r
+"HAL_HRTIM_SimplePWMStop_DMA" functions to add a check for the DMA\r
+handle against NULL pointer.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">HAL_HRTIM_SimpleOCChannelConfig,,<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">"HAL_HRTIM_SimpleCaptureChannelConfig",\r
+HAL_HRTIM_SimplePWMChannelConfig and \r
+"HAL_HRTIM_SimpleOnePulseChannelConfig" functions : considering\r
+parameters "pSimpleOCChannelCfg->Polarity " ,\r
+"pSimpleOCChannelCfg->IdleLevel" and\r
+"pSimpleCaptureChannelCfg->EventSensitivity"</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL IRDA: compatibilty break, </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">alignment<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">with STM32L4 (</span><span style="font-family: Verdana; font-size: 10pt;">for inter STM32 families portability</span><span style="font-family: Verdana; font-size: 10pt;">)</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add new field "ClockPrescaler" to "IRDA_InitTypeDef" structure"</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL I2C: </span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">ErrorCode is set to HAL_I2C_ERROR_INVALID_PARAM in all APIs when I2C handle is NULL</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add and I2C restart condition for each call of HAL_I2C_Master_Sequential_xxxx_IT</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rename APIs "HAL_I2C_Master_Sequential_Transmit_IT" and "HAL_I2C_Master_Seq_Receive_IT" </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">respectively<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">to "HAL_I2C_Master_Seq_Transmit_IT" and "HAL_I2C_Master_Seq_Receive_IT" for MISRA-C 2012 compliancy.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rename APIs "HAL_I2C_Slave_Sequential_Transmit_IT" and "HAL_I2C_Slave_Sequential_Receive_IT" </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">respectively<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">to "HAL_I2C_Slave_Seq_Transmit_IT" and "HAL_I2C_Slave_Seq_Receive_IT" for MISRA-C 2012 compliancy.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rename APIs "HAL_I2C_Master_Sequential_Transmit_DMA" and "HAL_I2C_Master_Seq_Receive_DMA" </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">respectively<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">to "HAL_I2C_Master_Seq_Transmit_DMA" and "HAL_I2C_Master_Seq_Receive_DMA" for MISRA-C 2012 compliancy.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rename APIs "HAL_I2C_Slave_Sequential_Transmit_DMA" and "HAL_I2C_Slave_Sequential_Receive_DMA" </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">respectively</span><span style="font-family: Verdana; font-size: 10pt;">to "HAL_I2C_Slave_Seq_Transmit_DMA" and "HAL_I2C_Slave_Seq_Receive_DMA" for MISRA-C 2012 compliancy.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S: </span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Align driver with the Reference Manual regarding registers and bit </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">definition</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>naming.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix HAL_I2S_DMAPause and HAL_I2S_DMAResume management</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">HAL_I2S_DMAStop is no more supported (return HAL_I2S_ERROR_NOT_SUPPORTED when called)</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"> Fix FifoThreshold affectation into HAL_I2S_Init</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update several defines into stm32h7xx_hal_i2s.h</span><span style="font-family: Verdana; font-size: 10pt;"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add macro __HAL_I2S_CLEAR_SUSPFLAG</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix compilation issue when SPI driver is not included in the project (Due to the use of some HAL SPI define, use </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">appropriate</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>I2S defines instead)</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix Tx\r
+and RX buffers increment to avoid memory overflow (functions\r
+HAL_I2S_Transmit, HAL_I2S_Receive, I2S_RxISR_16BIT, I2S_RxISR_32BIT,\r
+I2S_TxISR_16BIT and I2S_TxISR_32BIT)<br></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">Known limitations</span><span> </span>:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">Driver not fully tested, some features may not be working as expected</span>. </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black; font-weight: bold;"><span style="font-family: Verdana; font-size: 10pt;">A new version of this driver will be </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">available</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>in next release with full features tested.</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_JPEG</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"> Remove include of MDMA HAL driver as it is already done through the stm32h7xx_hal_conf.h header file</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Note : in the<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">stm32h7xx_hal_conf.h the include of the MDMA HAL header file must be done before the include of the JPEG HAL header file (</span><span style="font-family: Verdana; font-size: 10pt;">stm32h7xx_hal_conf_template.h updated accordingly</span><span style="font-family: Verdana; font-size: 10pt;">)</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_LPTIM</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update "HAL_LPTIM_Init" function to add a clock </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">polarity<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">reset.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update "__HAL_LPTIM_DISABLE" macro </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Replace usage of global variables "tmpclksource", "tmpIER", "tmpCFGR", "tmpCMP", "tmpARR" and "tmpCFGR2" by local ones.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_MDMA</span>:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Remove check on busy state within "HAL_MDMA_DeInit" function : to allow forcing a </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">de-initialization</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>even in busy state</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_MMC</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rename "BLOCKSIZE" define to "MMC_BLOCKSIZE" to avoid conflict with HAL SD definition.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_PWR</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"> Update "HAL_PWR_DisableWakeUpPin" function to disable the Wakeup for the given wakeup pin only.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix\r
+"HAL_PWR_EnterSLEEPMode" and "HAL_PWR_EnterSTOPMode" using one single\r
+__WFE instruction in case low power mode with wait for event.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix "HAL_PWREx_EnterSTOPMode" using one single </span><span style="font-family: Verdana; font-size: 10pt;">using one single __WFE instruction </span><span style="font-family: Verdana; font-size: 10pt;">in case low power mode with wait for event</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add API "HAL_PWREx_ClearPendingEvent" to clear pending events if any.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_QSPI</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;">Remove include of MDMA HAL driver as it is already done through the stm32h7xx_hal_conf.h header file</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Note : in the<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">stm32h7xx_hal_conf.h the include of the MDMA HAL header file must be done before the include of the QSPI HAL header file<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">(</span><span style="font-family: Verdana; font-size: 10pt;">stm32h7xx_hal_conf_template.h updated accordingly</span><span style="font-family: Verdana; font-size: 10pt;">)</span><span style="font-family: Verdana; font-size: 10pt;">.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">description</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>of MDMA required settings in the "How to use this driver" section</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix the "HAL_QSPI_Transmit_DMA" function:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add check for MDMA settings : Data size and increment mode</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Support of BYTE, HALF WORD and WORD modes</span><span style="font-family: Verdana; font-size: 10pt;"></span></li></ul></ul></ul><ul style="margin-bottom: 0in;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Enable the QSPI Transfer complete and errors interrupt before starting the MDMA transfer to avoid race condition</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix the "HAL_QSPI_Receive_DMA"<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">function :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"></span> <span style="font-family: Verdana; font-size: 10pt;">Add check for MDMA settings : Data size and increment mode</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Support of BYTE, HALF WORD and WORD modes</span></li></ul></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC:</span> </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add management for "Frac" parameter in PLL2 and PLL3</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add macros __HAL_RCC_MCO1_CONFIG and __HAL_RCC_MCO2_CONFIG.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rewoek HAL_RCC_DeInit function to reset RCC registers.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Rework HAL_RCC_ClockConfig function to use the correct </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">divider</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>settings order according to the Reference Manual.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix PCLK1 Configuration in HAL_RCC_ClockConfig function : use correct register RCC->D2CFGR instead of RCC->D1CFGR.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add\r
+definitions of "RCC_SYSCLKSOURCE_STATUS_CSI",\r
+"RCC_SYSCLKSOURCE_STATUS_HSI", "RCC_SYSCLKSOURCE_STATUS_HSE" and\r
+"RCC_SYSCLKSOURCE_STATUS_PLLCLK". </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix "HAL_RCC_ClockConfig" implementation:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Null pointer check</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"> use "__HAL_FLASH_GET_LATENCY" macro instead of direct register </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">access</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Optimize the wait for clock source switching.</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC:</span> </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add new macro IS_RTC_TAMPER_FILTER_CONFIG_CORRECT() to check filter is enabled only in case of high or low level.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Align driver with the Reference Manual regarding registers and bit </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">definition</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>naming.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">PDM feature is avilable on SAI1 and SAI4 only</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Improve and fix HAL_SAI_DMAStop and HAL_SAI_Abort APIs</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Expend external synchronization feature to SAI3 and SAI4</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL SD</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix and improve High speed and </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">ultra-high<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">speed </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">behavior</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add APIs "HAL_SD_ConfigSpeedBusOperation" to configure the SD card speed bus mode :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Remove extra function prototype "HAL_SD_SendSDStatus" from stm32h7xx_hal_sd.h</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">multi-buffering feature implementation</span><span style="font-family: Verdana; font-size: 10pt;">.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_SPI</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update HAL_SPI_Transmit_DMA : checking hmdtx instead of hdmrx.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Update to add Reload Feauture and Duplex Packet DXP</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add APIs : "HAL_SPI_Reload_Transmit_IT", "HAL_SPI_Reload_Receive_IT" and "HAL_SPI_Reload_TransmitReceive_IT"</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Align driver with the Reference Manual regarding registers and bit </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">definition</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>naming.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Known limitations :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Circular topology not supported: Daisy Chain topology.<br></span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL SMARTCARD: </span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">compatibilty break, </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">alignment<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">with STM32L4 (for inter STM32 </span><span style="font-family: Verdana; font-size: 10pt;">families</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>portability)</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Remove fields "FIFOMode", "TXFIFOThreshold" and "RXFIFOThreshold" from </span><span style="font-family: Verdana; font-size: 10pt;">"SMARTCARD_InitTypeDef"<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">structure</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add new field "ClockPrescaler" to "</span><span style="font-family: Verdana; font-size: 10pt;">SMARTCARD</span><span style="font-family: Verdana; font-size: 10pt;">_InitTypeDef" structure"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">SMARTCARD RXFIFO and TXFIFO threshold level defines moved to "stm32h7xx_hal_smartcard_ex.h"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Introduce new APIs to manage the Tx and Rx FIFO :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">HAL_SMARTCARDEx_EnableFifoMode, HAL_</span><span style="font-family: Verdana; font-size: 10pt;">SMARTCARDEx</span><span style="font-family: Verdana; font-size: 10pt;">_DisableFifoMode, HAL_</span><span style="font-family: Verdana; font-size: 10pt;">SMARTCARDEx</span><span style="font-family: Verdana; font-size: 10pt;">_SetTxFifoThreshold and HAL_</span><span style="font-family: Verdana; font-size: 10pt;">SMARTCARDEx</span><span style="font-family: Verdana; font-size: 10pt;">_SetRxFifoThreshold</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Introduce "HAL_SMARTCARDEx_RxFifoFullCallback" and "HAL_SMARTCARDEx_TxFifoEmptyCallback" </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix Linux compilation warning in function "HAL_SMARTCARD_Receive".</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL SRAM, HAL SDRAM , HAL NOR<span> </span></span>and<span> </span><span style="font-weight: bold;">HAL NAND</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Align driver with the Reference Manual regarding registers and bit </span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">definition</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>naming</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Fix and improve state and error management.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL_TIM</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add a call to HAL_DMA_Abort_IT from HAL_TIM_XXX_Stop_DMA.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Add APIs "HAL_TIM_DMABurst_MultiWriteStart" and "HAL_TIM_DMABurst_MultiReadStart".</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span>:<span> </span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">compatibilty break, </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">alignment<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">with STM32L4 (for inter STM32 </span><span style="font-family: Verdana; font-size: 10pt;">families</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>portability)</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Field "Prescaler" of structure "UART_InitTypeDef" renamed to ClockPrescaler</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">remove fields "FIFOMode", "TXFIFOThreshold" and "RXFIFOThreshold" from </span><span style="font-family: Verdana; font-size: 10pt;">"UART_InitTypeDef"<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">structure</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">UART RXFIFO and TXFIFO threshold level defines moved to "stm32h7xx_hal_uart_ex.h"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Introduce new APIs to manage the Tx and Rx FIFO :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">HAL_UARTEx_EnableFifoMode, HAL_UARTEx_DisableFifoMode, HAL_UARTEx_SetTxFifoThreshold and HAL_UARTEx_SetRxFifoThreshold<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Introduce "HAL_UARTEx_RxFifoFullCallback" and "HAL_UARTEx_TxFifoEmptyCallback"<span> </span><br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL USART</span>:<span> </span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">compatibilty break, </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">alignment<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">with STM32L4 (</span><span style="font-family: Verdana; font-size: 10pt;">for inter STM32 </span><span style="font-family: Verdana; font-size: 10pt;">families</span><span style="font-family: Verdana; font-size: 10pt;"><span> </span>portability</span><span style="font-family: Verdana; font-size: 10pt;">)</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Introduce "stm32h7xx_hal_usart_ex.c" file with new Tx/Rx FIFO management APIs</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Field "Prescaler" of structure "USART_InitTypeDef" renamed to ClockPrescaler</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">remove fields "NSS", "SlaveMode", "FIFOMode", "TXFIFOThreshold" and "RXFIFOThreshold" from </span><span style="font-family: Verdana; font-size: 10pt;">"USART_InitTypeDef"<span> </span></span><span style="font-family: Verdana; font-size: 10pt;">structure</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">USART RXFIFO and TXFIFO threshold level defines moved to "stm32h7xx_hal_usart_ex.h"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">USART Salve Mode defines moved to "stm32h7xx_hal_usart_ex.h"</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Introduce new APIs to manage the Tx and Rx FIFO :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">HAL_USARTEx_EnableFifoMode, HAL_USARTEx_DisableFifoMode, HAL_USARTEx_SetTxFifoThreshold and HAL_USARTEx_SetRxFifoThreshold</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Introduce new APIs to manage SPI slave mode :</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">HAL_USARTEx_EnableSlaveMode, HAL_USARTEx_DisableSlaveMode and HAL_USARTEx_ConfigNSS</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL USB</span>: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;">Fix condition check for EmptyTX FIFO<span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0\r
+ / 29-June-2018</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman",serif; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;">Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL Cortex:</strong><span> </span>Driver\r
+update to support 16 MPU regions instead of 8. User can now select an\r
+MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><p class="MsoNormal" style="margin: 0in 0in 0.0001pt; font-size: 12pt; font-family: "Times New Roman",serif;"><strong><span style="font-family: Calibri,sans-serif;">HAL RCC :</span></strong><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span> </span>Update\r
+and rework HAL_RCC_PeriphCLKConfig function in order to\r
+support consecutive configurations for several peripherals using\r
+PLL2 and PLL3. To do so first the given PLL is stopped, then the given\r
+divider is updated, the given PLL clock output divider is enabled\r
+and finally the given PLL is enabled.</span></p></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL SDMMC:</strong><span> </span>Fix and </span><span style="font-family: Verdana; font-size: 10pt;">enhancements to support high speed mode</span><span style="font-family: Verdana; font-size: 10pt;">.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0\r
+ / 29-December-2017</span></h3>\r
+\r
+ \r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+ Changes</span></u></b></p>\r
+\r
+ \r
+ <ul style="margin-top: 0cm;" type="square">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">General\r
+ updates to fix known defects and enhancements\r
+ implementation.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL SPI:</strong> Driver reworked to fix critical issues.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL:</strong> Update HAL Tick implementation.</span></li>\r
+ </ul>\r
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0\r
+ / 31-August-2017</span></h3>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+ Changes</span></u></b></p>\r
+ <ul style="margin-top: 0cm;" type="square">\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">General\r
+ updates to fix known defects and enhancements\r
+ implementation.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL\r
+ FLASH:</strong> Add Mass Erase for both banks.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL\r
+ RCC:</strong> <br>\r
+ </span></li>\r
+ <ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Update\r
+ <strong>RCC_PeriphCLKInitTypeDef</strong>\r
+ structure for more IP clock selection\r
+ flexibility.</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">Adjust\r
+ PLL fractional computation.</span></li>\r
+ </ul>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><strong>HAL\r
+ SPDIFRX:</strong> Add symbol clock generation.<br>\r
+ </span></li>\r
+ </ul>\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0\r
+ / 21-April-2017</span></h3>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+ Changes</span></u></b></p>\r
+ <ul style="margin-top: 0cm;" type="square">\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">First\r
+ official release for</span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold;">\r
+ STM32H743xx/753xx</span> devices</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>\r
+ </ul>\r
+ <b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></u></b><div style="text-align: justify;"><span style="font-family: "Verdana","sans-serif";"></span></div>\r
+ <span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span>\r
+ <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+ <hr align="center" size="2" width="100%"></span></div>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For\r
+complete\r
+ documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
+ </td>\r
+ </tr>\r
+ <tr>\r
+ <td style="padding: 0in;" valign="top"><br>\r
+ </td>\r
+ </tr>\r
+ </tbody>\r
+ </table>\r
+ <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+ </td>\r
+ </tr>\r
+ </tbody>\r
+ </table>\r
+ </div>\r
+ <p class="MsoNormal"><o:p> </o:p></p>\r
+ </div>\r
+ </body></html>
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal.c\r
+ * @author MCD Application Team\r
+ * @brief HAL module driver.\r
+ * This is the common part of the HAL initialization\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The common HAL driver contains a set of generic and common APIs that can be\r
+ used by the PPP peripheral drivers and the user to start using the HAL.\r
+ [..]\r
+ The HAL contains two APIs' categories:\r
+ (+) Common HAL APIs\r
+ (+) Services HAL APIs\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL HAL\r
+ * @brief HAL module driver.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/**\r
+ * @brief STM32H7xx HAL Driver version number V1.5.0\r
+ */\r
+#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */\r
+#define __STM32H7xx_HAL_VERSION_SUB1 (0x05UL) /*!< [23:16] sub1 version */\r
+#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */\r
+#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */\r
+#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\\r
+ |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\\r
+ |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\\r
+ |(__STM32H7xx_HAL_VERSION_RC))\r
+\r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+static __IO uint32_t uwTick;\r
+static uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */\r
+static HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Private_Functions HAL Private Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initializes the Flash interface the NVIC allocation and initial clock\r
+ configuration. It initializes the systick also when timeout is needed\r
+ and the backup domain when enabled.\r
+ (+) De-Initializes common part of the HAL.\r
+ (+) Configure The time base source to have 1ms time base with a dedicated\r
+ Tick interrupt priority.\r
+ (++) SysTick timer is used by default as source of time base, but user\r
+ can eventually implement his proper time base source (a general purpose\r
+ timer for example or other time source), keeping in mind that Time base\r
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and\r
+ handled in milliseconds basis.\r
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically\r
+ at the beginning of the program after reset by HAL_Init() or at any time\r
+ when clock is configured, by HAL_RCC_ClockConfig().\r
+ (++) Source of time base is configured to generate interrupts at regular\r
+ time intervals. Care must be taken if HAL_Delay() is called from a\r
+ peripheral ISR process, the Tick interrupt line must have higher priority\r
+ (numerically lower) than the peripheral interrupt. Otherwise the caller\r
+ ISR process will be blocked.\r
+ (++) functions affecting time base configurations are declared as __weak\r
+ to make override possible in case of other implementations in user file.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is used to initialize the HAL Library; it must be the first\r
+ * instruction to be executed in the main program (before to call any other\r
+ * HAL function), it performs the following:\r
+ * Configures the SysTick to generate an interrupt each 1 millisecond,\r
+ * which is clocked by the HSI (at this stage, the clock is not yet\r
+ * configured and thus the system is running from the internal HSI at 16 MHz).\r
+ * Set NVIC Group Priority to 4.\r
+ * Calls the HAL_MspInit() callback function defined in user file\r
+ * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization\r
+ *\r
+ * @note SysTick is used as time base for the HAL_Delay() function, the application\r
+ * need to ensure that the SysTick time base is always set to 1 millisecond\r
+ * to have correct HAL operation.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_Init(void)\r
+{\r
+ /* Set Interrupt Group Priority */\r
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);\r
+\r
+ /* Update the SystemD2Clock global variable */ \r
+ SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));\r
+\r
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\r
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ HAL_MspInit();\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function de-Initializes common part of the HAL and stops the systick.\r
+ * This function is optional.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DeInit(void)\r
+{\r
+ /* Reset of all peripherals */\r
+ __HAL_RCC_AHB3_FORCE_RESET();\r
+ __HAL_RCC_AHB3_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB1_FORCE_RESET();\r
+ __HAL_RCC_AHB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB2_FORCE_RESET();\r
+ __HAL_RCC_AHB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB4_FORCE_RESET();\r
+ __HAL_RCC_AHB4_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB3_FORCE_RESET();\r
+ __HAL_RCC_APB3_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB1L_FORCE_RESET();\r
+ __HAL_RCC_APB1L_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB1H_FORCE_RESET();\r
+ __HAL_RCC_APB1H_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB2_FORCE_RESET();\r
+ __HAL_RCC_APB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB4_FORCE_RESET();\r
+ __HAL_RCC_APB4_RELEASE_RESET();\r
+\r
+ /* De-Init the low level hardware */\r
+ HAL_MspDeInit();\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function configures the source of the time base.\r
+ * The time source is configured to have 1ms time base with a dedicated\r
+ * Tick interrupt priority.\r
+ * @note This function is called automatically at the beginning of program after\r
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().\r
+ * @note In the default implementation, SysTick timer is the source of time base.\r
+ * It is used to generate interrupts at regular time intervals.\r
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,\r
+ * The the SysTick interrupt must have higher priority (numerically lower)\r
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
+ * The function is declared as __weak to be overwritten in case of other\r
+ * implementation in user file.\r
+ * @param TickPriority: Tick interrupt priority.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+ /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/\r
+ if((uint32_t)uwTickFreq == 0UL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+#if defined(DUAL_CORE)\r
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)\r
+ {\r
+ /* Cortex-M7 detected */\r
+ /* Configure the SysTick to have interrupt in 1ms time basis*/\r
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Cortex-M4 detected */\r
+ /* Configure the SysTick to have interrupt in 1ms time basis*/\r
+ if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+#else\r
+ /* Configure the SysTick to have interrupt in 1ms time basis*/\r
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+#endif\r
+\r
+ /* Configure the SysTick IRQ priority */\r
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))\r
+ {\r
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\r
+ uwTickPrio = TickPriority;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Group2 HAL Control functions\r
+ * @brief HAL Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### HAL Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Provide a tick value in millisecond\r
+ (+) Provide a blocking delay in millisecond\r
+ (+) Suspend the time base source interrupt\r
+ (+) Resume the time base source interrupt\r
+ (+) Get the HAL API driver version\r
+ (+) Get the device identifier\r
+ (+) Get the device revision identifier\r
+ (+) Enable/Disable Debug module during SLEEP mode\r
+ (+) Enable/Disable Debug module during STOP mode\r
+ (+) Enable/Disable Debug module during STANDBY mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is called to increment a global variable "uwTick"\r
+ * used as application time base.\r
+ * @note In the default implementation, this variable is incremented each 1ms\r
+ * in Systick ISR.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IncTick(void)\r
+{\r
+ uwTick += (uint32_t)uwTickFreq;\r
+}\r
+\r
+/**\r
+ * @brief Provides a tick value in millisecond.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval tick value\r
+ */\r
+__weak uint32_t HAL_GetTick(void)\r
+{\r
+ return uwTick;\r
+}\r
+\r
+/**\r
+ * @brief This function returns a tick priority.\r
+ * @retval tick priority\r
+ */\r
+uint32_t HAL_GetTickPrio(void)\r
+{\r
+ return uwTickPrio;\r
+}\r
+\r
+/**\r
+ * @brief Set new tick Freq.\r
+ * @retval Status\r
+ */\r
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ assert_param(IS_TICKFREQ(Freq));\r
+\r
+ if (uwTickFreq != Freq)\r
+ {\r
+ uwTickFreq = Freq;\r
+\r
+ /* Apply the new tick Freq */\r
+ status = HAL_InitTick(uwTickPrio);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Return tick frequency.\r
+ * @retval tick period in Hz\r
+ */\r
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)\r
+{\r
+ return uwTickFreq;\r
+}\r
+\r
+/**\r
+ * @brief This function provides minimum delay (in milliseconds) based\r
+ * on variable incremented.\r
+ * @note In the default implementation , SysTick timer is the source of time base.\r
+ * It is used to generate interrupts at regular time intervals where uwTick\r
+ * is incremented.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @param Delay specifies the delay time length, in milliseconds.\r
+ * @retval None\r
+ */\r
+__weak void HAL_Delay(uint32_t Delay)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+ uint32_t wait = Delay;\r
+\r
+ /* Add a freq to guarantee minimum wait */\r
+ if (wait < HAL_MAX_DELAY)\r
+ {\r
+ wait += (uint32_t)(uwTickFreq);\r
+ }\r
+\r
+ while ((HAL_GetTick() - tickstart) < wait)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Suspend Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
+ * is called, the the SysTick interrupt will be disabled and so Tick increment\r
+ * is suspended.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SuspendTick(void)\r
+{\r
+ /* Disable SysTick Interrupt */\r
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Resume Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
+ * is called, the the SysTick interrupt will be enabled and so Tick increment\r
+ * is resumed.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ResumeTick(void)\r
+{\r
+ /* Enable SysTick Interrupt */\r
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HAL revision\r
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r
+ */\r
+uint32_t HAL_GetHalVersion(void)\r
+{\r
+ return __STM32H7xx_HAL_VERSION;\r
+}\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t HAL_GetREVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetDEVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Configure the internal voltage reference buffer voltage scale.\r
+ * @param VoltageScaling specifies the output voltage to achieve\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.\r
+ * This requires VDDA equal to or higher than 2.4 V.\r
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.\r
+ * This requires VDDA equal to or higher than 2.8 V.\r
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.\r
+ * This requires VDDA equal to or higher than 1.8 V.\r
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.\r
+ * This requires VDDA equal to or higher than 2.1 V.\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));\r
+\r
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);\r
+}\r
+\r
+/**\r
+ * @brief Configure the internal voltage reference buffer high impedance mode.\r
+ * @param Mode specifies the high impedance mode\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.\r
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));\r
+\r
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);\r
+}\r
+\r
+/**\r
+ * @brief Tune the Internal Voltage Reference buffer (VREFBUF).\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));\r
+\r
+ MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Internal Voltage Reference buffer (VREFBUF).\r
+ * @retval HAL_OK/HAL_TIMEOUT\r
+ */\r
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for VRR bit */\r
+ while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the Internal Voltage Reference buffer (VREFBUF).\r
+ *\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_DisableVREFBUF(void)\r
+{\r
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\r
+}\r
+\r
+/**\r
+ * @brief Ethernet PHY Interface Selection either MII or RMII\r
+ * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_ETH_MII : Select the Media Independent Interface\r
+ * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));\r
+\r
+ MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Analog Switch control for dual analog pads.\r
+ * @param SYSCFG_AnalogSwitch: Selects the analog pad\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch\r
+ * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch\r
+ * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch\r
+ * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch\r
+ * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SYSCFG_SWITCH_PA0_OPEN\r
+ * @arg SYSCFG_SWITCH_PA0_CLOSE\r
+ * @arg SYSCFG_SWITCH_PA1_OPEN\r
+ * @arg SYSCFG_SWITCH_PA1_CLOSE\r
+ * @arg SYSCFG_SWITCH_PC2_OPEN\r
+ * @arg SYSCFG_SWITCH_PC2_CLOSE\r
+ * @arg SYSCFG_SWITCH_PC3_OPEN\r
+ * @arg SYSCFG_SWITCH_PC3_CLOSE\r
+ * @retval None\r
+ */\r
+\r
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));\r
+ assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));\r
+\r
+ MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables the booster to reduce the total harmonic distortion of the analog\r
+ * switch when the supply voltage is lower than 2.7 V.\r
+ * @note Activating the booster allows to guaranty the analog switch AC performance\r
+ * when the supply voltage is below 2.7 V: in this case, the analog switch\r
+ * performance is the same on the full voltage range\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_EnableBOOST(void)\r
+{\r
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;\r
+}\r
+\r
+/**\r
+ * @brief Disables the booster\r
+ * @note Activating the booster allows to guaranty the analog switch AC performance\r
+ * when the supply voltage is below 2.7 V: in this case, the analog switch\r
+ * performance is the same on the full voltage range\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_DisableBOOST(void)\r
+{\r
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;\r
+}\r
+\r
+\r
+/**\r
+ * @brief BootCM7 address 0 configuration\r
+ * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0\r
+ * @arg SYSCFG_BOOT_ADDR1: Select the boot address1\r
+ * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));\r
+ assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));\r
+ if ( BootRegister == SYSCFG_BOOT_ADDR0 )\r
+ {\r
+ /* Configure CM7 BOOT ADD0 */\r
+#if defined(DUAL_CORE)\r
+ MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));\r
+#else\r
+ MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));\r
+#endif /*DUAL_CORE*/\r
+ }\r
+ else\r
+ {\r
+ /* Configure CM7 BOOT ADD1 */\r
+#if defined(DUAL_CORE)\r
+ MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));\r
+#else\r
+ MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));\r
+#endif /*DUAL_CORE*/\r
+ }\r
+\r
+}\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief BootCM4 address 0 configuration\r
+ * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0\r
+ * @arg SYSCFG_BOOT_ADDR1: Select the boot address1\r
+ * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));\r
+ assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));\r
+\r
+ if ( BootRegister == SYSCFG_BOOT_ADDR0 )\r
+ {\r
+ /* Configure CM4 BOOT ADD0 */\r
+ MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));\r
+ }\r
+\r
+ else\r
+ {\r
+ /* Configure CM4 BOOT ADD1 */\r
+ MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Cortex-M7 boot\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_EnableCM7BOOT(void)\r
+{\r
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Cortex-M7 boot\r
+ * @note Disabling the boot will gate the CPU clock\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_DisableCM7BOOT(void)\r
+{\r
+ CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Cortex-M4 boot\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_EnableCM4BOOT(void)\r
+{\r
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Cortex-M4 boot\r
+ * @note Disabling the boot will gate the CPU clock\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_DisableCM4BOOT(void)\r
+{\r
+ CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);\r
+}\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Enables the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V.\r
+ * @retval None\r
+ */\r
+void HAL_EnableCompensationCell(void)\r
+{\r
+ SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;\r
+}\r
+\r
+/**\r
+ * @brief Power-down the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V.\r
+ * @retval None\r
+ */\r
+void HAL_DisableCompensationCell(void)\r
+{\r
+ CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);\r
+}\r
+\r
+\r
+/**\r
+ * @brief To Enable optimize the I/O speed when the product voltage is low.\r
+ * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be\r
+ * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is\r
+ * higher than 2.5 V might be destructive.\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_EnableIOSpeedOptimize(void)\r
+{\r
+ SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);\r
+}\r
+\r
+/**\r
+ * @brief To Disable optimize the I/O speed when the product voltage is low.\r
+ * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be\r
+ * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is\r
+ * higher than 2.5 V might be destructive.\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_DisableIOSpeedOptimize(void)\r
+{\r
+ CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);\r
+}\r
+\r
+/**\r
+ * @brief Code selection for the I/O Compensation cell\r
+ * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)\r
+ * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));\r
+ MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));\r
+}\r
+\r
+/**\r
+ * @brief Code selection for the I/O Compensation cell\r
+ * @param SYSCFG_PMOSCode: PMOS compensation code\r
+ * This code is applied to the I/O compensation cell when the CS bit of the\r
+ * SYSCFG_CMPCR is set\r
+ * @param SYSCFG_NMOSCode: NMOS compensation code\r
+ * This code is applied to the I/O compensation cell when the CS bit of the\r
+ * SYSCFG_CMPCR is set\r
+ * @retval None\r
+ */\r
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));\r
+ assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));\r
+ MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable the Debug Module during Domain1 SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDBGSleepMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain1 SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDBGSleepMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during Domain1 STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDBGStopMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain1 STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDBGStopMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during Domain1 STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDBGStandbyMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain1 STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDBGStandbyMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);\r
+}\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Enable the Debug Module during Domain1 SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDomain2DBGSleepMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain2 SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDomain2DBGSleepMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during Domain2 STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDomain2DBGStopMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain2 STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDomain2DBGStopMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during Domain2 STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDomain2DBGStandbyMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain2 STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDomain2DBGStandbyMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);\r
+}\r
+#endif /*DUAL_CORE*/\r
+\r
+\r
+/**\r
+ * @brief Enable the Debug Module during Domain3 STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDomain3DBGStopMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain3 STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDomain3DBGStopMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during Domain3 STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDomain3DBGStandbyMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during Domain3 STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDomain3DBGStandbyMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);\r
+}\r
+\r
+/**\r
+ * @brief Set the FMC Memory Mapping Swapping config.\r
+ * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be\r
+ FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2\r
+ * @retval HAL state\r
+ */\r
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));\r
+ MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);\r
+}\r
+\r
+/**\r
+ * @brief Get FMC Bank mapping mode.\r
+ * @retval The FMC Bank mapping mode. This parameter can be\r
+ FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2\r
+*/\r
+uint32_t HAL_GetFMCMemorySwappingConfig(void)\r
+{\r
+ return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);\r
+}\r
+\r
+/**\r
+ * @brief Configure the EXTI input event line edge\r
+ * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),\r
+ * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.\r
+ * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,\r
+ * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved\r
+ * @param EXTI_Edge: Specifies EXTI line Edge used.\r
+ * This parameter can be one of the following values :\r
+ * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection\r
+ * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection\r
+ * @retval None\r
+ */\r
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));\r
+ assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+\r
+ if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)\r
+ {\r
+ SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+ if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)\r
+ {\r
+ SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,\r
+ * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.\r
+ * @retval None\r
+ */\r
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));\r
+\r
+ SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags for Domain D1\r
+ * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,\r
+ * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved\r
+ * @retval None\r
+ */\r
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_D1_LINE(EXTI_Line));\r
+ SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+\r
+}\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Clears the EXTI's line pending flags for Domain D2\r
+ * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,\r
+ * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved\r
+ * @retval None\r
+ */\r
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_D2_LINE(EXTI_Line));\r
+ SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+}\r
+\r
+#endif /*DUAL_CORE*/\r
+/**\r
+ * @brief Configure the EXTI input event line for Domain D1\r
+ * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,\r
+ * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved\r
+ * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.\r
+ * This parameter can be one or a combination of the following values :\r
+ * @arg EXTI_MODE_IT : Interrupt Mode selected\r
+ * @arg EXTI_MODE_EVT : Event Mode selected\r
+ * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.\r
+\r
+ * @retval None\r
+ */\r
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_EXTI_D1_LINE(EXTI_Line));\r
+ assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));\r
+\r
+ if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)\r
+ {\r
+ if( EXTI_LineCmd == 0UL)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+ }\r
+\r
+ if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)\r
+ {\r
+ if( EXTI_LineCmd == 0UL)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+ else\r
+ {\r
+ SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+ }\r
+}\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Configure the EXTI input event line for Domain D2\r
+ * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,\r
+ * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved\r
+ * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.\r
+ * This parameter can be one or a combination of the following values :\r
+ * @arg EXTI_MODE_IT : Interrupt Mode selected\r
+ * @arg EXTI_MODE_EVT : Event Mode selected\r
+ * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.\r
+\r
+ * @retval None\r
+ */\r
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_EXTI_D2_LINE(EXTI_Line));\r
+ assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));\r
+\r
+ if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)\r
+ {\r
+ if( EXTI_LineCmd == 0UL)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+ }\r
+\r
+ if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)\r
+ {\r
+ if( EXTI_LineCmd == 0UL)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+ else\r
+ {\r
+ SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+ }\r
+}\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Configure the EXTI input event line for Domain D3\r
+ * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,\r
+ * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,\r
+ * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)\r
+ * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.\r
+ * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event.\r
+ * This parameter can be one of the following values :\r
+ * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source\r
+ * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source\r
+ * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source\r
+ * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source\r
+ * @retval None\r
+ */\r
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc )\r
+{\r
+ __IO uint32_t *pRegv;\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_EXTI_D3_LINE(EXTI_Line));\r
+ assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));\r
+\r
+ if( EXTI_LineCmd == 0UL)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));\r
+ }\r
+\r
+ if(((EXTI_Line>>4)%2UL) == 0UL)\r
+ {\r
+ pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));\r
+ }\r
+ else\r
+ {\r
+ pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));\r
+ }\r
+ MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));\r
+\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_cortex.c\r
+ * @author MCD Application Team\r
+ * @brief CORTEX HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the CORTEX:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+\r
+ [..]\r
+ *** How to configure Interrupts using CORTEX HAL driver ***\r
+ ===========================================================\r
+ [..]\r
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).\r
+ The Cortex-M exceptions are managed by CMSIS functions.\r
+\r
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\r
+ function according to the following table.\r
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().\r
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r
+ (#) please refer to programming manual for details in how to configure priority.\r
+\r
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.\r
+ The pending IRQ priority will be managed only by the sub priority.\r
+\r
+ -@- IRQ priority order (sorted by highest to lowest priority):\r
+ (+@) Lowest preemption priority\r
+ (+@) Lowest sub priority\r
+ (+@) Lowest hardware priority (IRQ number)\r
+\r
+ [..]\r
+ *** How to configure Systick using CORTEX HAL driver ***\r
+ ========================================================\r
+ [..]\r
+ Setup SysTick Timer for time base.\r
+\r
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r
+ is a CMSIS function that:\r
+ (++) Configures the SysTick Reload register with value passed as function parameter.\r
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r
+ (++) Resets the SysTick Counter register.\r
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
+ (++) Enables the SysTick Interrupt.\r
+ (++) Starts the SysTick Counter.\r
+\r
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
+ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
+ HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined\r
+ inside the stm32h7xx_hal_cortex.h file.\r
+\r
+ (+) You can change the SysTick IRQ priority by calling the\r
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function\r
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
+\r
+ (+) To adjust the SysTick time base, use the following formula:\r
+\r
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)\r
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
+ (++) Reload Value should not exceed 0xFFFFFF\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX CORTEX\r
+ * @brief CORTEX HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r
+ Systick functionalities\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Sets the priority grouping field (preemption priority and subpriority)\r
+ * using the required unlock sequence.\r
+ * @param PriorityGroup The priority grouping bits length.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.\r
+ * The pending IRQ priority will be managed only by the subpriority.\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+\r
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
+ NVIC_SetPriorityGrouping(PriorityGroup);\r
+}\r
+\r
+/**\r
+ * @brief Sets the priority of an interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @param PreemptPriority The preemption priority for the IRQn channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority\r
+ * @param SubPriority the subpriority level for the IRQ channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority.\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t prioritygroup;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
+\r
+ prioritygroup = NVIC_GetPriorityGrouping();\r
+\r
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
+}\r
+\r
+/**\r
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+ /* Enable interrupt */\r
+ NVIC_EnableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+ /* Disable interrupt */\r
+ NVIC_DisableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Initiates a system reset request to reset the MCU.\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SystemReset(void)\r
+{\r
+ /* System Reset */\r
+ NVIC_SystemReset();\r
+}\r
+\r
+/**\r
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ * Counter is in free running mode to generate periodic interrupts.\r
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.\r
+ * @retval status - 0 Function succeeded.\r
+ * - 1 Function failed.\r
+ */\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
+{\r
+ return SysTick_Config(TicksNumb);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Cortex control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the CORTEX\r
+ (NVIC, SYSTICK, MPU) functionalities.\r
+\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+ * @brief Disables the MPU\r
+ * @retval None\r
+ */\r
+void HAL_MPU_Disable(void)\r
+{\r
+ /* Make sure outstanding transfers are done */\r
+ __DMB();\r
+\r
+ /* Disable fault exceptions */\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+\r
+ /* Disable the MPU and clear the control register*/\r
+ MPU->CTRL = 0;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MPU\r
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault,\r
+ * NMI, FAULTMASK and privileged access to the default memory\r
+ * This parameter can be one of the following values:\r
+ * @arg MPU_HFNMI_PRIVDEF_NONE\r
+ * @arg MPU_HARDFAULT_NMI\r
+ * @arg MPU_PRIVILEGED_DEFAULT\r
+ * @arg MPU_HFNMI_PRIVDEF\r
+ * @retval None\r
+ */\r
+void HAL_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ /* Enable the MPU */\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+\r
+ /* Enable fault exceptions */\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+\r
+ /* Ensure MPU setting take effects */\r
+ __DSB();\r
+ __ISB();\r
+}\r
+/**\r
+ * @brief Initializes and configures the Region and the memory to be protected.\r
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains\r
+ * the initialization and configuration information.\r
+ * @retval None\r
+ */\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
+\r
+ /* Set the Region number */\r
+ MPU->RNR = MPU_Init->Number;\r
+\r
+ if ((MPU_Init->Enable) != 0UL)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
+\r
+ MPU->RBAR = MPU_Init->BaseAddress;\r
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |\r
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |\r
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |\r
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |\r
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |\r
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |\r
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |\r
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |\r
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);\r
+ }\r
+ else\r
+ {\r
+ MPU->RBAR = 0x00;\r
+ MPU->RASR = 0x00;\r
+ }\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.\r
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
+ */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
+{\r
+ /* Get the PRIGROUP[10:8] field value */\r
+ return NVIC_GetPriorityGrouping();\r
+}\r
+\r
+/**\r
+ * @brief Gets the priority of an interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @param PriorityGroup the priority grouping bits length.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).\r
+ * @param pSubPriority Pointer on the Subpriority value (starting from 0).\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ /* Get priority for Cortex-M system or device specific interrupts */\r
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
+}\r
+\r
+/**\r
+ * @brief Sets Pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+ /* Set interrupt pending */\r
+ NVIC_SetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC\r
+ * and returns the pending bit for the specified interrupt).\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @retval status - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+ /* Return 1 if pending else 0 */\r
+ return NVIC_GetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Clears the pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+ /* Clear pending interrupt */\r
+ NVIC_ClearPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))\r
+ * @retval status - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+\r
+ /* Return 1 if active else 0 */\r
+ return NVIC_GetActive(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param CLKSource specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
+ {\r
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SYSTICK interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_IRQHandler(void)\r
+{\r
+ HAL_SYSTICK_Callback();\r
+}\r
+\r
+/**\r
+ * @brief SYSTICK callback.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SYSTICK_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SYSTICK_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+#if defined(DUAL_CORE)\r
+\r
+/**\r
+ * @brief Returns the current CPU ID.\r
+ * @retval CPU identifier\r
+ */\r
+uint32_t HAL_GetCurrentCPUID(void)\r
+{\r
+ if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)\r
+ {\r
+ return CM7_CPUID;\r
+ }\r
+ else\r
+ {\r
+ return CM4_CPUID;\r
+ }\r
+}\r
+\r
+#else\r
+\r
+/**\r
+* @brief Returns the current CPU ID.\r
+* @retval CPU identifier\r
+*/\r
+uint32_t HAL_GetCurrentCPUID(void)\r
+{\r
+ return CM7_CPUID;\r
+}\r
+\r
+#endif /*DUAL_CORE*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_dma.c\r
+ * @author MCD Application Team\r
+ * @brief DMA HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Direct Memory Access (DMA) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and errors functions\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable and configure the peripheral to be connected to the DMA Stream\r
+ (except for internal SRAM/FLASH memories: no initialization is\r
+ necessary) please refer to Reference manual for connection between peripherals\r
+ and DMA requests .\r
+\r
+ (#) For a given Stream, program the required configuration through the following parameters:\r
+ Transfer Direction, Source and Destination data formats,\r
+ Circular, Normal or peripheral flow control mode, Stream Priority level,\r
+ Source and Destination Increment mode, FIFO mode and its Threshold (if needed),\r
+ Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source\r
+ address and destination address and the Length of data to be transferred\r
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this\r
+ case a fixed Timeout can be configured by User depending from his application.\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of\r
+ Source address and destination address and the Length of data to be transferred. In this\r
+ case the DMA interrupt is configured\r
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can\r
+ add his own function by customization of function pointer XferCpltCallback and\r
+ XferErrorCallback (i.e a member of DMA handle structure).\r
+ [..]\r
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error\r
+ detection.\r
+\r
+ (#) Use HAL_DMA_Abort() function to abort the current transfer\r
+\r
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
+\r
+ -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\r
+ possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\r
+ Half-Word data size for the peripheral to access its data register and set Word data size\r
+ for the Memory to gain in access time. Each two half words will be packed and written in\r
+ a single access to a Word in the Memory).\r
+\r
+ -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\r
+ and Destination. In this case the Peripheral Data Size will be applied to both Source\r
+ and Destination.\r
+\r
+ *** DMA HAL driver macros list ***\r
+ =============================================\r
+ [..]\r
+ Below the list of most used macros in DMA HAL driver.\r
+\r
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.\r
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.\r
+ (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.\r
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.\r
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.\r
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.\r
+\r
+ [..]\r
+ (@) You can refer to the DMA HAL driver header file for more useful macros.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA DMA\r
+ * @brief DMA HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< DMA interrupt status register */\r
+ __IO uint32_t Reserved0;\r
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */\r
+} DMA_Base_Registers;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< BDMA interrupt status register */\r
+ __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */\r
+} BDMA_Base_Registers;\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Constants\r
+ * @{\r
+ */\r
+#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */\r
+\r
+#define BDMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */\r
+#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR) /*!< Memory to peripheral direction */\r
+#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction */\r
+\r
+/* DMA to BDMA conversion */\r
+#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \\r
+ ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \\r
+ BDMA_PERIPH_TO_MEMORY)\r
+\r
+#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)\r
+#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)\r
+\r
+#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)\r
+#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)\r
+\r
+#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)\r
+\r
+#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);\r
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);\r
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group1\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to initialize the DMA Stream source\r
+ and destination incrementation and data sizes, transfer direction,\r
+ circular/normal mode selection, memory-to-memory mode selection and Stream priority value.\r
+ [..]\r
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
+ reference manual.\r
+ The HAL_DMA_DeInit function allows to deinitialize the DMA stream.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the DMA according to the specified\r
+ * parameters in the DMA_InitTypeDef and create the associated handle.\r
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t registerValue;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ DMA_Base_Registers *regs_dma;\r
+ BDMA_Base_Registers *regs_bdma;\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ assert_param(IS_DMA_REQUEST(hdma->Init.Request));\r
+ assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));\r
+ /* Check the memory burst, peripheral burst and FIFO threshold parameters only\r
+ when FIFO mode is enabled */\r
+ if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)\r
+ {\r
+ assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));\r
+ assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));\r
+ assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));\r
+ }\r
+\r
+ /* Allocate lock resource */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Check if the DMA Stream is effectively disabled */\r
+ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_ERROR;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Get the CR register value */\r
+ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR;\r
+\r
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */\r
+ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\r
+ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \\r
+ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \\r
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));\r
+\r
+ /* Prepare the DMA Stream configuration */\r
+ registerValue |= hdma->Init.Direction |\r
+ hdma->Init.PeriphInc | hdma->Init.MemInc |\r
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
+ hdma->Init.Mode | hdma->Init.Priority;\r
+\r
+ /* the Memory burst and peripheral burst are not used when the FIFO is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get memory burst and peripheral burst */\r
+ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;\r
+ }\r
+\r
+ /* Write to DMA Stream CR register */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;\r
+\r
+ /* Get the FCR register value */\r
+ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR;\r
+\r
+ /* Clear Direct mode and FIFO threshold bits */\r
+ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\r
+\r
+ /* Prepare the DMA Stream FIFO configuration */\r
+ registerValue |= hdma->Init.FIFOMode;\r
+\r
+ /* the FIFO threshold is not used when the FIFO mode is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get the FIFO threshold */\r
+ registerValue |= hdma->Init.FIFOThreshold;\r
+\r
+ /* Check compatibility between FIFO threshold level and size of the memory burst */\r
+ /* for INCR4, INCR8, INCR16 */\r
+ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)\r
+ {\r
+ if (DMA_CheckFifoParam(hdma) != HAL_OK)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Write to DMA Stream FCR */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue;\r
+\r
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate\r
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */\r
+ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+\r
+ /* Clear all interrupt flags */\r
+ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */\r
+ {\r
+ /* Check the request parameter */\r
+ assert_param(IS_BDMA_REQUEST(hdma->Init.Request));\r
+\r
+ /* Allocate lock resource */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Get the CR register value */\r
+ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;\r
+\r
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */\r
+ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \\r
+ BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \\r
+ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \\r
+ BDMA_CCR_CT));\r
+\r
+ /* Prepare the DMA Channel configuration */\r
+ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | \\r
+ DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | \\r
+ DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | \\r
+ DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | \\r
+ DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | \\r
+ DMA_TO_BDMA_MODE(hdma->Init.Mode) | \\r
+ DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);\r
+\r
+ /* Write to DMA Channel CR register */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;\r
+\r
+ /* calculation of the channel index */\r
+ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;\r
+\r
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate\r
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */\r
+ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+\r
+ /* Clear all interrupt flags */\r
+ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));\r
+ }\r
+ else\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r
+ hdma->State = HAL_DMA_STATE_ERROR;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Initialize parameters for DMAMUX channel :\r
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask\r
+ */\r
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);\r
+\r
+ if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ /* if memory to memory force the request to 0*/\r
+ hdma->Init.Request = DMA_REQUEST_MEM2MEM;\r
+ }\r
+\r
+ /* Set peripheral request to DMAMUX channel */\r
+ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ /* Initialize parameters for DMAMUX request generator :\r
+ if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7\r
+ */\r
+ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))\r
+ {\r
+ /* Initialize parameters for DMAMUX request generator :\r
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */\r
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);\r
+\r
+ /* Reset the DMAMUX request generator register */\r
+ hdma->DMAmuxRequestGen->RGCR = 0U;\r
+\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+ else\r
+ {\r
+ hdma->DMAmuxRequestGen = 0U;\r
+ hdma->DMAmuxRequestGenStatus = 0U;\r
+ hdma->DMAmuxRequestGenStatusMask = 0U;\r
+ }\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DMA peripheral\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
+{\r
+ DMA_Base_Registers *regs_dma;\r
+ BDMA_Base_Registers *regs_bdma;\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable the selected DMA Streamx */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Reset DMA Streamx control register */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U;\r
+\r
+ /* Reset DMA Streamx number of data to transfer register */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U;\r
+\r
+ /* Reset DMA Streamx peripheral address register */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U;\r
+\r
+ /* Reset DMA Streamx memory 0 address register */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U;\r
+\r
+ /* Reset DMA Streamx memory 1 address register */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U;\r
+\r
+ /* Reset DMA Streamx FIFO control register */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U;\r
+\r
+ /* Get DMA steam Base Address */\r
+ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+\r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */\r
+ {\r
+ /* Reset DMA Channel control register */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U;\r
+\r
+ /* Reset DMA Channel Number of Data to Transfer register */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;\r
+\r
+ /* Reset DMA Channel peripheral address register */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U;\r
+\r
+ /* Reset DMA Channel memory 0 address register */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U;\r
+\r
+ /* Reset DMA Channel memory 1 address register */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U;\r
+\r
+ /* Get DMA steam Base Address */\r
+ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+\r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Initialize parameters for DMAMUX channel :\r
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */\r
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);\r
+\r
+ if(hdma->DMAmuxChannel != 0U)\r
+ {\r
+ /* Resett he DMAMUX channel that corresponds to the DMA stream */\r
+ hdma->DMAmuxChannel->CCR = 0U;\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+ }\r
+\r
+ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))\r
+ {\r
+ /* Initialize parameters for DMAMUX request generator :\r
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */\r
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);\r
+\r
+ /* Reset the DMAMUX request generator register */\r
+ hdma->DMAmuxRequestGen->RGCR = 0U;\r
+\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ hdma->DMAmuxRequestGen = 0U;\r
+ hdma->DMAmuxRequestGenStatus = 0U;\r
+ hdma->DMAmuxRequestGenStatusMask = 0U;\r
+\r
+ /* Clean callbacks */\r
+ hdma->XferCpltCallback = NULL;\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ hdma->XferM1CpltCallback = NULL;\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ hdma->XferErrorCallback = NULL;\r
+ hdma->XferAbortCallback = NULL;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group2\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and Start DMA transfer\r
+ (+) Configure the source, destination address and data length and\r
+ Start DMA transfer with interrupt\r
+ (+) Register and Unregister DMA callbacks\r
+ (+) Abort DMA transfer\r
+ (+) Poll for transfer complete\r
+ (+) Handle DMA interrupt request\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Start the DMA Transfer with interrupt enabled.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Enable Common interrupts*/\r
+ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));\r
+\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Enable Half Transfer IT if corresponding Callback is set */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;\r
+ }\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ /* Enable Common interrupts */\r
+ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));\r
+\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /*Enable Half Transfer IT if corresponding Callback is set */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;\r
+ }\r
+ }\r
+\r
+ /* Check if DMAMUX Synchronization is enabled */\r
+ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)\r
+ {\r
+ /* Enable DMAMUX sync overrun IT*/\r
+ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;\r
+ }\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/\r
+ /* enable the request gen overrun IT */\r
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ *\r
+ * @note After disabling a DMA Stream, a check for wait until the DMA Stream is\r
+ * effectively disabled is added. If a Stream is disabled\r
+ * while a data transfer is ongoing, the current data will be transferred\r
+ * and the Stream will be effectively disabled only after the transfer of\r
+ * this single data is finished.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs_dma;\r
+ BDMA_Base_Registers *regs_bdma;\r
+ const __IO uint32_t *enableRegister;\r
+\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the DMA peripheral state */\r
+ if(hdma->State != HAL_DMA_STATE_BUSY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable all the transfer interrupts */\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Disable DMA All Interrupts */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);\r
+\r
+ enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR));\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ /* Disable DMA All Interrupts */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);\r
+\r
+ enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR));\r
+ }\r
+\r
+ /* disable the DMAMUX sync overrun IT */\r
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
+\r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Check if the DMA Stream is effectively disabled */\r
+ while(((*enableRegister) & DMA_SxCR_EN) != 0U)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_ERROR;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));\r
+ }\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */\r
+ /* disable the request gen overrun IT */\r
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
+\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer in Interrupt mode.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r
+{\r
+ BDMA_Base_Registers *regs_bdma;\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hdma->State != HAL_DMA_STATE_BUSY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Set Abort State */\r
+ hdma->State = HAL_DMA_STATE_ABORT;\r
+\r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ /* Disable DMA All Interrupts */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);\r
+\r
+ /* Disable the channel */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* disable the DMAMUX sync overrun IT */\r
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
+\r
+ /* Clear all flags */\r
+ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/\r
+ /* disable the request gen overrun IT */\r
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
+\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Call User Abort callback */\r
+ if(hdma->XferAbortCallback != NULL)\r
+ {\r
+ hdma->XferAbortCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Polling for transfer complete.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CompleteLevel: Specifies the DMA level complete.\r
+ * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.\r
+ * This model could be used for debug purpose.\r
+ * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).\r
+ * @param Timeout: Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t cpltlevel_mask;\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ /* IT status register */\r
+ __IO uint32_t *isr_reg;\r
+ /* IT clear flag register */\r
+ __IO uint32_t *ifcr_reg;\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(HAL_DMA_STATE_BUSY != hdma->State)\r
+ {\r
+ /* No transfer ongoing */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Polling mode not supported in circular mode and double buffering mode */\r
+ if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Transfer Complete flag */\r
+ cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else\r
+ {\r
+ /* Half Transfer Complete flag */\r
+ cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);\r
+ ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ /* Polling mode not supported in circular mode */\r
+ if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Transfer Complete flag */\r
+ cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else\r
+ {\r
+ /* Half Transfer Complete flag */\r
+ cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ isr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);\r
+ ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);\r
+ }\r
+\r
+ while(((*isr_reg) & cpltlevel_mask) == 0U)\r
+ {\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+\r
+ /* Clear the FIFO error flag */\r
+ (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+\r
+ /* Clear the Direct Mode error flag */\r
+ (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+\r
+ /* Clear the transfer error flag */\r
+ (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ /* When a DMA transfer error occurs */\r
+ /* A hardware clear of its EN bits is performed */\r
+ /* Clear all flags */\r
+ (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU));\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Check for the Timeout (Not applicable in circular mode)*/\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+\r
+ /* if timeout then abort the current transfer */\r
+ /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */\r
+ (void) HAL_DMA_Abort(hdma);\r
+ /*\r
+ Note that the Abort function will\r
+ - Clear the transfer error flags\r
+ - Unlock\r
+ - Set the State\r
+ */\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Check for DMAMUX Request generator (if used) overrun status */\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* if using DMAMUX request generator Check for DMAMUX request generator overrun */\r
+ if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)\r
+ {\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;\r
+ }\r
+ }\r
+\r
+ /* Check for DMAMUX Synchronization overrun */\r
+ if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)\r
+ {\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;\r
+ }\r
+ }\r
+\r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Clear the half transfer and transfer complete flags */\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/\r
+ {\r
+ /* Clear the half transfer and transfer complete flags */\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else /* BDMA channel */\r
+ {\r
+ (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU));\r
+ }\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Handles DMA interrupt request.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval None\r
+ */\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmpisr_dma, tmpisr_bdma;\r
+ uint32_t ccr_reg;\r
+ __IO uint32_t count = 0U;\r
+ uint32_t timeout = SystemCoreClock / 9600U;\r
+\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;\r
+\r
+ tmpisr_dma = regs_dma->ISR;\r
+ tmpisr_bdma = regs_bdma->ISR;\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)\r
+ {\r
+ /* Disable the transfer error interrupt */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE);\r
+\r
+ /* Clear the transfer error flag */\r
+ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+ }\r
+ }\r
+ /* FIFO Error Interrupt management ******************************************/\r
+ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)\r
+ {\r
+ /* Clear the FIFO error flag */\r
+ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+ }\r
+ }\r
+ /* Direct Mode Error Interrupt management ***********************************/\r
+ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)\r
+ {\r
+ /* Clear the direct mode error flag */\r
+ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+ }\r
+ }\r
+ /* Half Transfer Complete Interrupt management ******************************/\r
+ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Multi_Buffering mode enabled */\r
+ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)\r
+ {\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferM1HalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferM1HalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
+ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)\r
+ {\r
+ /* Disable the half transfer interrupt */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);\r
+ }\r
+\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Transfer Complete Interrupt management ***********************************/\r
+ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)\r
+ {\r
+ /* Clear the transfer complete flag */\r
+ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);\r
+\r
+ if(HAL_DMA_STATE_ABORT == hdma->State)\r
+ {\r
+ /* Disable all the transfer interrupts */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);\r
+\r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);\r
+ }\r
+\r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ if(hdma->XferAbortCallback != NULL)\r
+ {\r
+ hdma->XferAbortCallback(hdma);\r
+ }\r
+ return;\r
+ }\r
+\r
+ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)\r
+ {\r
+ if(hdma->XferM1CpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory1 */\r
+ hdma->XferM1CpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory0 */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r
+ else\r
+ {\r
+ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)\r
+ {\r
+ /* Disable the transfer complete interrupt */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete callback */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* manage error case */\r
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r
+ {\r
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)\r
+ {\r
+ hdma->State = HAL_DMA_STATE_ABORT;\r
+\r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ do\r
+ {\r
+ if (++count > timeout)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)\r
+ {\r
+ /* Change the DMA state to error if DMA disable fails */\r
+ hdma->State = HAL_DMA_STATE_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Change the DMA state to Ready if DMA disable success */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ }\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */\r
+ {\r
+ ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR);\r
+\r
+ /* Half Transfer Complete Interrupt management ******************************/\r
+ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));\r
+\r
+ /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */\r
+ if((ccr_reg & BDMA_CCR_DBM) != 0U)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((ccr_reg & BDMA_CCR_CT) == 0U)\r
+ {\r
+ if(hdma->XferM1HalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer Callback for Memory 1 */\r
+ hdma->XferM1HalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer Callback for Memory 0 */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((ccr_reg & BDMA_CCR_CIRC) == 0U)\r
+ {\r
+ /* Disable the half transfer interrupt */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
+ }\r
+\r
+ /* DMA peripheral state is not updated in Half Transfer */\r
+ /* but in Transfer Complete case */\r
+\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Transfer Complete Interrupt management ***********************************/\r
+ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))\r
+ {\r
+ /* Clear the transfer complete flag */\r
+ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */\r
+ if((ccr_reg & BDMA_CCR_DBM) != 0U)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((ccr_reg & BDMA_CCR_CT) == 0U)\r
+ {\r
+ if(hdma->XferM1CpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for Memory 1 */\r
+ hdma->XferM1CpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for Memory 0 */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((ccr_reg & BDMA_CCR_CIRC) == 0U)\r
+ {\r
+ /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete callback */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Transfer Error Interrupt management **************************************/\r
+ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))\r
+ {\r
+ /* When a DMA transfer error occurs */\r
+ /* A hardware clear of its EN bits is performed */\r
+ /* Disable ALL DMA IT */\r
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));\r
+\r
+ /* Clear all flags */\r
+ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ if (hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing To Do */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing To Do */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Register callbacks\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CallbackID: User Callback identifier\r
+ * a DMA_HandleTypeDef structure as parameter.\r
+ * @param pCallback: pointer to private callback function which has pointer to\r
+ * a DMA_HandleTypeDef structure as parameter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))\r
+{\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_M1CPLT_CB_ID:\r
+ hdma->XferM1CpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r
+ hdma->XferM1HalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = pCallback;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief UnRegister callbacks\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CallbackID: User Callback identifier\r
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the DMA peripheral handle */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_M1CPLT_CB_ID:\r
+ hdma->XferM1CpltCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = NULL;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ALL_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ hdma->XferM1CpltCallback = NULL;\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ hdma->XferErrorCallback = NULL;\r
+ hdma->XferAbortCallback = NULL;\r
+ break;\r
+\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group3\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DMA state\r
+ (+) Get error code\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the DMA state.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL state\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the DMA error code\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval DMA Error Code\r
+ */\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the DMA Transfer parameter.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval None\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Clear DBM bit */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);\r
+\r
+ /* Configure DMA Stream data length */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;\r
+ }\r
+ }\r
+ else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */\r
+ {\r
+ /* Clear all flags */\r
+ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);\r
+\r
+ /* Configure DMA Channel data length */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Channel destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;\r
+\r
+ /* Configure DMA Channel source address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Channel source address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;\r
+\r
+ /* Configure DMA Channel destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing To Do */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the DMA Stream base address depending on stream number\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval Stream base address\r
+ */\r
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)\r
+{\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;\r
+\r
+ /* lookup table for necessary bitshift of flags within status registers */\r
+ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};\r
+ hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];\r
+\r
+ if (stream_number > 3U)\r
+ {\r
+ /* return pointer to HISR and HIFCR */\r
+ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);\r
+ }\r
+ else\r
+ {\r
+ /* return pointer to LISR and LIFCR */\r
+ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));\r
+ }\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* return pointer to ISR and IFCR */\r
+ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));\r
+ }\r
+\r
+ return hdma->StreamBaseAddress;\r
+}\r
+\r
+/**\r
+ * @brief Check compatibility between FIFO threshold level and size of the memory burst\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Memory Data size equal to Byte */\r
+ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)\r
+ {\r
+ switch (hdma->Init.FIFOThreshold)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Memory Data size equal to Half-Word */\r
+ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+ {\r
+ switch (hdma->Init.FIFOThreshold)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ status = HAL_ERROR;\r
+ break;\r
+\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Memory Data size equal to Word */\r
+ else\r
+ {\r
+ switch (hdma->Init.FIFOThreshold)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ status = HAL_ERROR;\r
+ break;\r
+\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t stream_number;\r
+ uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);\r
+\r
+ if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)\r
+ {\r
+ /* BDMA Channels are connected to DMAMUX2 channels */\r
+ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;\r
+ hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));\r
+ hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;\r
+ hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);\r
+ }\r
+ else\r
+ {\r
+ /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */\r
+ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;\r
+\r
+ if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \\r
+ (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))\r
+ {\r
+ stream_number += 8U;\r
+ }\r
+ hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));\r
+ hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;\r
+ hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Updates the DMA handle with the DMAMUX request generator params\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;\r
+\r
+ if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))\r
+ {\r
+ if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)\r
+ {\r
+ /* BDMA Channels are connected to DMAMUX2 request generator blocks */\r
+ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));\r
+\r
+ hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;\r
+ }\r
+ else\r
+ {\r
+ /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */\r
+ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));\r
+\r
+ hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;\r
+ }\r
+\r
+ hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_dma_ex.c\r
+ * @author MCD Application Team\r
+ * @brief DMA Extension HAL module driver\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the DMA Extension peripheral:\r
+ * + Extended features functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The DMA Extension HAL driver can be used as follows:\r
+ (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\r
+ for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\r
+\r
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
+ Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
+ to respectively enable/disable the request generator.\r
+\r
+ (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from\r
+ the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .\r
+ As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be\r
+ called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project\r
+ (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)\r
+\r
+ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r
+ -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r
+ -@- In Multi (Double) buffer mode, it is possible to update the base address for\r
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.\r
+ -@- Multi (Double) buffer mode is possible with DMA and BDMA instances.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx DMAEx\r
+ * @brief DMA Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup DMAEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @addtogroup DMAEx_Exported_Functions_Group1\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and\r
+ Start MultiBuffer DMA transfer\r
+ (+) Configure the source, destination address and data length and\r
+ Start MultiBuffer DMA transfer with interrupt\r
+ (+) Change on the fly the memory0 or memory1 address.\r
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
+ (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
+ to respectively enable/disable the request generator.\r
+ (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from\r
+ the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Enable Common interrupts*/\r
+ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;\r
+\r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ /*Enable Half Transfer IT if corresponding Callback is set*/\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;\r
+ }\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Enable Common interrupts*/\r
+ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));\r
+\r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ /*Enable Half Transfer IT if corresponding Callback is set*/\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;\r
+ }\r
+ }\r
+\r
+ /* Check if DMAMUX Synchronization is enabled*/\r
+ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)\r
+ {\r
+ /* Enable DMAMUX sync overrun IT*/\r
+ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;\r
+ }\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/\r
+ /* enable the request gen overrun IT*/\r
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;\r
+ }\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Change the memory0 or memory1 address on the fly.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param Address: The new address\r
+ * @param memory: the memory to be changed, This parameter can be one of\r
+ * the following values:\r
+ * MEMORY0 /\r
+ * MEMORY1\r
+ * @note The MEMORY0 address can be changed only when the current transfer use\r
+ * MEMORY1 and the MEMORY1 address can be changed only when the current\r
+ * transfer use MEMORY0.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\r
+{\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ if(memory == MEMORY0)\r
+ {\r
+ /* change the memory0 address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;\r
+ }\r
+ else\r
+ {\r
+ /* change the memory1 address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;\r
+ }\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ if(memory == MEMORY0)\r
+ {\r
+ /* change the memory0 address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address;\r
+ }\r
+ else\r
+ {\r
+ /* change the memory1 address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)\r
+{\r
+ uint32_t syncSignalID = 0;\r
+ uint32_t syncPolarity = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+ assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));\r
+ assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));\r
+ assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));\r
+\r
+ if(pSyncConfig->SyncEnable == ENABLE)\r
+ {\r
+ assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));\r
+ }\r
+ syncSignalID = pSyncConfig->SyncSignalID;\r
+ syncPolarity = pSyncConfig->SyncPolarity;\r
+ }\r
+\r
+ /*Check if the DMA state is ready */\r
+ if(hdma->State == HAL_DMA_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Disable the synchronization and event generation before applying a new config */\r
+ CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));\r
+\r
+ /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/\r
+ MODIFY_REG( hdma->DMAmuxChannel->CCR, \\r
+ (~DMAMUX_CxCR_DMAREQ_ID) , \\r
+ (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \\r
+ ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \\r
+ syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \\r
+ ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));\r
+\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :\r
+ * contains the request generator parameters.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)\r
+{\r
+ HAL_StatusTypeDef status;\r
+ HAL_DMA_StateTypeDef temp_state = hdma->State;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));\r
+ }\r
+\r
+\r
+ assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));\r
+ assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));\r
+\r
+ /* check if the DMA state is ready\r
+ and DMA is using a DMAMUX request generator block\r
+ */\r
+ if(hdma->DMAmuxRequestGen == 0U)\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r
+\r
+ /* error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))\r
+ {\r
+ /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Set the request generator new parameters */\r
+ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \\r
+ ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \\r
+ pRequestGeneratorConfig->Polarity;\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* check if the DMA state is ready\r
+ and DMA is using a DMAMUX request generator block */\r
+ if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))\r
+ {\r
+ /* Enable the request generator*/\r
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* check if the DMA state is ready\r
+ and DMA is using a DMAMUX request generator block */\r
+ if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))\r
+ {\r
+ /* Disable the request generator*/\r
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handles DMAMUX interrupt request.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval None\r
+ */\r
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Check for DMAMUX Synchronization overrun */\r
+ if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)\r
+ {\r
+ /* Disable the synchro overrun interrupt */\r
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+\r
+ if(hdma->DMAmuxRequestGen != 0)\r
+ {\r
+ /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */\r
+ if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)\r
+ {\r
+ /* Disable the request gen overrun interrupt */\r
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
+\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the DMA Transfer parameter.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Configure DMA Stream data length */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;\r
+ }\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Configure DMA Stream data length */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_gpio.c\r
+ * @author MCD Application Team\r
+ * @brief GPIO HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### GPIO Peripheral features #####\r
+ ==============================================================================\r
+ [..]\r
+ (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually\r
+ configured by software in several modes:\r
+ (++) Input mode\r
+ (++) Analog mode\r
+ (++) Output mode\r
+ (++) Alternate function mode\r
+ (++) External interrupt/event lines\r
+\r
+ (+) During and just after reset, the alternate functions and external interrupt\r
+ lines are not active and the I/O ports are configured in input floating mode.\r
+\r
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be\r
+ activated or not.\r
+\r
+ (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
+ type and the IO speed can be selected depending on the VDD value.\r
+\r
+ (+) The microcontroller IO pins are connected to onboard peripherals/modules through a\r
+ multiplexer that allows only one peripheral alternate function (AF) connected\r
+ to an IO pin at a time. In this way, there can be no conflict between peripherals\r
+ sharing the same IO pin.\r
+\r
+ (+) All ports have external interrupt/event capability. To use external interrupt\r
+ lines, the port must be configured in input mode. All available GPIO pins are\r
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
+\r
+ The external interrupt/event controller consists of up to 23 edge detectors\r
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each\r
+ input line can be independently configured to select the type (interrupt or event)\r
+ and the corresponding trigger event (rising or falling or both). Each line can\r
+ also be masked independently.\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().\r
+\r
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef\r
+ structure.\r
+ (++) In case of Output or alternate function mode selection: the speed is\r
+ configured through "Speed" member from GPIO_InitTypeDef structure.\r
+ (++) In alternate mode is selection, the alternate function connected to the IO\r
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.\r
+ (++) Analog mode is required when a pin is to be used as ADC channel\r
+ or DAC output.\r
+ (++) In case of external interrupt/event selection the "Mode" member from\r
+ GPIO_InitTypeDef structure select the type (interrupt or event) and\r
+ the corresponding trigger event (rising or falling or both).\r
+\r
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority\r
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
+ HAL_NVIC_EnableIRQ().\r
+\r
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
+\r
+ (#) To set/reset the level of a pin configured in output mode use\r
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
+\r
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
+\r
+\r
+ (#) During and just after reset, the alternate functions are not\r
+ active and the GPIO pins are configured in input floating mode (except JTAG\r
+ pins).\r
+\r
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose\r
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has\r
+ priority over the GPIO function.\r
+\r
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as\r
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off.\r
+ The HSE has priority over the GPIO function.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO GPIO\r
+ * @brief GPIO HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+#define GPIO_MODE (0x00000003U)\r
+#define ANALOG_MODE (0x00000008U)\r
+#define EXTI_MODE (0x10000000U)\r
+#define GPIO_MODE_IT (0x00010000U)\r
+#define GPIO_MODE_EVT (0x00020000U)\r
+#define RISING_EDGE (0x00100000U)\r
+#define FALLING_EDGE (0x00200000U)\r
+#define GPIO_OUTPUT_TYPE (0x00000010U)\r
+\r
+#if defined(DUAL_CORE)\r
+#define EXTI_CPU1 (0x01000000U)\r
+#define EXTI_CPU2 (0x02000000U)\r
+#endif /*DUAL_CORE*/\r
+#define GPIO_NUMBER (16U)\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to initialize and de-initialize the GPIOs\r
+ to be ready for use.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains\r
+ * the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
+{\r
+ uint32_t position = 0x00U;\r
+ uint32_t iocurrent;\r
+ uint32_t temp;\r
+ EXTI_Core_TypeDef *EXTI_CurrentCPU;\r
+\r
+#if defined(DUAL_CORE) && defined(CORE_CM4)\r
+ EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */\r
+#else\r
+ EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */\r
+#endif\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r
+\r
+ /* Configure the port pins */\r
+ while (((GPIO_Init->Pin) >> position) != 0x00U)\r
+ {\r
+ /* Get current io position */\r
+ iocurrent = (GPIO_Init->Pin) & (1UL << position);\r
+\r
+ if (iocurrent != 0x00U)\r
+ {\r
+ /*--------------------- GPIO Mode Configuration ------------------------*/\r
+ /* In case of Alternate function mode selection */\r
+ if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Alternate function parameters */\r
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r
+\r
+ /* Configure Alternate function mapped with the current IO */\r
+ temp = GPIOx->AFR[position >> 3U];\r
+ temp &= ~(0xFU << ((position & 0x07U) * 4U));\r
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));\r
+ GPIOx->AFR[position >> 3U] = temp;\r
+ }\r
+\r
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r
+ temp = GPIOx->MODER;\r
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2U));\r
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));\r
+ GPIOx->MODER = temp;\r
+\r
+ /* In case of Output or Alternate function mode selection */\r
+ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Speed parameter */\r
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
+ /* Configure the IO Speed */\r
+ temp = GPIOx->OSPEEDR;\r
+ temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));\r
+ temp |= (GPIO_Init->Speed << (position * 2U));\r
+ GPIOx->OSPEEDR = temp;\r
+\r
+ /* Configure the IO Output Type */\r
+ temp = GPIOx->OTYPER;\r
+ temp &= ~(GPIO_OTYPER_OT0 << position) ;\r
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);\r
+ GPIOx->OTYPER = temp;\r
+ }\r
+\r
+ /* Activate the Pull-up or Pull down resistor for the current IO */\r
+ temp = GPIOx->PUPDR;\r
+ temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));\r
+ temp |= ((GPIO_Init->Pull) << (position * 2U));\r
+ GPIOx->PUPDR = temp;\r
+\r
+ /*--------------------- EXTI Mode Configuration ------------------------*/\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r
+ {\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ temp = SYSCFG->EXTICR[position >> 2U];\r
+ temp &= ~(0x0FUL << (4U * (position & 0x03U)));\r
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));\r
+ SYSCFG->EXTICR[position >> 2U] = temp;\r
+\r
+ /* Clear EXTI line configuration */\r
+ temp = EXTI_CurrentCPU->IMR1;\r
+ temp &= ~(iocurrent);\r
+ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI_CurrentCPU->IMR1 = temp;\r
+\r
+ temp = EXTI_CurrentCPU->EMR1;\r
+ temp &= ~(iocurrent);\r
+ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI_CurrentCPU->EMR1 = temp;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ temp = EXTI->RTSR1;\r
+ temp &= ~(iocurrent);\r
+ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->RTSR1 = temp;\r
+\r
+ temp = EXTI->FTSR1;\r
+ temp &= ~(iocurrent);\r
+ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->FTSR1 = temp;\r
+ }\r
+ }\r
+\r
+ position++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)\r
+{\r
+ uint32_t position = 0x00U;\r
+ uint32_t iocurrent;\r
+ uint32_t tmp;\r
+ EXTI_Core_TypeDef *EXTI_CurrentCPU;\r
+\r
+#if defined(DUAL_CORE) && defined(CORE_CM4)\r
+ EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */\r
+#else\r
+ EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */\r
+#endif\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ /* Configure the port pins */\r
+ while ((GPIO_Pin >> position) != 0x00U)\r
+ {\r
+ /* Get current io position */\r
+ iocurrent = GPIO_Pin & (1UL << position) ;\r
+\r
+ if (iocurrent != 0x00U)\r
+ {\r
+ /*------------------------- EXTI Mode Configuration --------------------*/\r
+ /* Clear the External Interrupt or Event for the current IO */\r
+ tmp = SYSCFG->EXTICR[position >> 2U];\r
+ tmp &= (0x0FUL << (8U * (position & 0x03U)));\r
+ if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))))\r
+ {\r
+ tmp = 0x0FUL << (8U * (position & 0x03U));\r
+ SYSCFG->EXTICR[position >> 2U] &= ~tmp;\r
+\r
+ /* Clear EXTI line configuration for Current CPU */\r
+ EXTI_CurrentCPU->IMR1 &= ~(iocurrent);\r
+ EXTI_CurrentCPU->EMR1 &= ~(iocurrent);\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR1 &= ~(iocurrent);\r
+ EXTI->FTSR1 &= ~(iocurrent);\r
+ }\r
+\r
+ /*------------------------- GPIO Mode Configuration --------------------*/\r
+ /* Configure IO in Analog Mode */\r
+ GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));\r
+\r
+ /* Configure the default Alternate Function in current IO */\r
+ GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;\r
+\r
+ /* Configure the default value for IO Speed */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));\r
+\r
+ /* Configure the default value IO Output Type */\r
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;\r
+\r
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));\r
+ }\r
+\r
+ position++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions\r
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_PIN_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ GPIO_PinState bitstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->IDR & GPIO_Pin) != 0x00U)\r
+ {\r
+ bitstatus = GPIO_PIN_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = GPIO_PIN_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ *\r
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify\r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ *\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @param PinState: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the GPIO_PinState enum values:\r
+ * @arg GPIO_PIN_RESET: to clear the port pin\r
+ * @arg GPIO_PIN_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_PIN_ACTION(PinState));\r
+\r
+ if (PinState != GPIO_PIN_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Toggles the specified GPIO pins.\r
+ * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the pins to be toggled.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * @note The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family\r
+ * @param GPIO_Pin: specifies the port bit to be locked.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ /* Apply lock key write sequence */\r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+\r
+ if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)\r
+ {\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle EXTI interrupt request.\r
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
+{\r
+#if defined(DUAL_CORE) && defined(CORE_CM4)\r
+ if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)\r
+ {\r
+ __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);\r
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
+ }\r
+#else\r
+ /* EXTI line interrupt detected */\r
+ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)\r
+ {\r
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief EXTI line detection callback.\r
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.\r
+ * @retval None\r
+ */\r
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(GPIO_Pin);\r
+\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_hsem.c\r
+ * @author MCD Application Team\r
+ * @brief HSEM HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the semaphore peripheral:\r
+ * + Semaphore Take function (2-Step Procedure) , non blocking\r
+ * + Semaphore FastTake function (1-Step Procedure) , non blocking\r
+ * + Semaphore Status check\r
+ * + Semaphore Clear Key Set and Get\r
+ * + Release and release all functions\r
+ * + Semaphore notification enabling and disabling and callnack functions\r
+ * + IRQ handler management\r
+ *\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :\r
+ (++) the semaphore ID from 0 to 31\r
+ (++) the process ID from 0 to 255\r
+ (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :\r
+ (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero\r
+ (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :\r
+ (++) the semaphore ID from 0_ID to 31\r
+ (++) It returns 1 if the given semaphore is taken otherwise (Free) zero\r
+ (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :\r
+ (++) the semaphore ID from 0 to 31\r
+ (++) the process ID from 0 to 255:\r
+ (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt\r
+ may be generated when enabled (notification activated). If ProcessID or MasterID does not match,\r
+ semaphore remains taken (locked)\r
+\r
+ (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All\r
+ This function takes as parameters :\r
+ (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by\r
+ HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions\r
+ (++) the Master ID:\r
+ (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds\r
+ to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the\r
+ Key or the MasterID doesn't match, semaphores remains taken (locked)\r
+\r
+ (#)Semaphores Release all key functions:\r
+ (++) HAL_HSEM_SetClearKey() to set semaphore release all Key\r
+ (++) HAL_HSEM_GetClearKey() to get release all Key\r
+ (#)Semaphores notification functions :\r
+ (++) HAL_HSEM_ActivateNotification to activate a notification callback on\r
+ a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released\r
+ the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released\r
+ semaphores (bitfield).\r
+\r
+ (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).\r
+ (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask\r
+ Used by the notification functions\r
+ *** HSEM HAL driver macros list ***\r
+ =============================================\r
+ [..] Below the list of most used macros in HSEM HAL driver.\r
+\r
+ (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.\r
+ [..] Example of use :\r
+ [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).\r
+ [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.\r
+ (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.\r
+ (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.\r
+ (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.\r
+ (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.\r
+ (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HSEM HSEM\r
+ * @brief HSEM HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_HSEM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#if defined(DUAL_CORE)\r
+#ifndef HSEM_R_MASTERID\r
+#define HSEM_R_MASTERID HSEM_R_COREID\r
+#endif\r
+\r
+#ifndef HSEM_RLR_MASTERID\r
+#define HSEM_RLR_MASTERID HSEM_RLR_COREID\r
+#endif\r
+\r
+#ifndef HSEM_CR_MASTERID\r
+#define HSEM_CR_MASTERID HSEM_CR_COREID\r
+#endif\r
+#endif /* DUAL_CORE */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions\r
+ * @brief HSEM Take and Release functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### HSEM Take and Release functions #####\r
+ ==============================================================================\r
+[..] This section provides functions allowing to:\r
+ (+) Take a semaphore with 2 Step method\r
+ (+) Fast Take a semaphore with 1 Step method\r
+ (+) Check semaphore state Taken or not\r
+ (+) Release a semaphore\r
+ (+) Release all semaphore at once\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Take a semaphore in 2 Step mode.\r
+ * @param SemID: semaphore ID from 0 to 31\r
+ * @param ProcessID: Process ID from 0 to 255\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_HSEM_SEMID(SemID));\r
+ assert_param(IS_HSEM_PROCESSID(ProcessID));\r
+\r
+#if USE_MULTI_CORE_SHARED_CODE != 0U\r
+ /* First step write R register with MasterID, processID and take bit=1*/\r
+ HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);\r
+\r
+ /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */\r
+ if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))\r
+ {\r
+ /*take success when MasterID and ProcessID match and take bit set*/\r
+ return HAL_OK;\r
+ }\r
+#else\r
+ /* First step write R register with MasterID, processID and take bit=1*/\r
+ HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);\r
+\r
+ /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */\r
+ if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))\r
+ {\r
+ /*take success when MasterID and ProcessID match and take bit set*/\r
+ return HAL_OK;\r
+ }\r
+#endif\r
+\r
+ /* Semaphore take fails*/\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Fast Take a semaphore with 1 Step mode.\r
+ * @param SemID: semaphore ID from 0 to 31\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_HSEM_SEMID(SemID));\r
+\r
+#if USE_MULTI_CORE_SHARED_CODE != 0U\r
+ /* Read the RLR register to take the semaphore */\r
+ if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))\r
+ {\r
+ /*take success when MasterID match and take bit set*/\r
+ return HAL_OK;\r
+ }\r
+#else\r
+ /* Read the RLR register to take the semaphore */\r
+ if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))\r
+ {\r
+ /*take success when MasterID match and take bit set*/\r
+ return HAL_OK;\r
+ }\r
+#endif\r
+\r
+ /* Semaphore take fails */\r
+ return HAL_ERROR;\r
+}\r
+/**\r
+ * @brief Check semaphore state Taken or not.\r
+ * @param SemID: semaphore ID\r
+ * @retval HAL HSEM state\r
+ */\r
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)\r
+{\r
+ return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Release a semaphore.\r
+ * @param SemID: semaphore ID from 0 to 31\r
+ * @param ProcessID: Process ID from 0 to 255\r
+ * @retval None\r
+ */\r
+void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_HSEM_SEMID(SemID));\r
+ assert_param(IS_HSEM_PROCESSID(ProcessID));\r
+\r
+ /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */\r
+ HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Release All semaphore used by a given Master .\r
+ * @param Key: Semaphore Key , value from 0 to 0xFFFF\r
+ * @param CoreID: CoreID of the CPU that is using semaphores to be released\r
+ * @retval None\r
+ */\r
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)\r
+{\r
+ assert_param(IS_HSEM_KEY(Key));\r
+ assert_param(IS_HSEM_COREID(CoreID));\r
+\r
+ HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions\r
+ * @brief HSEM Set and Get Key functions.\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### HSEM Set and Get Key functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Set semaphore Key\r
+ (+) Get semaphore Key\r
+@endverbatim\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set semaphore Key .\r
+ * @param Key: Semaphore Key , value from 0 to 0xFFFF\r
+ * @retval None\r
+ */\r
+void HAL_HSEM_SetClearKey(uint32_t Key)\r
+{\r
+ assert_param(IS_HSEM_KEY(Key));\r
+\r
+ MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));\r
+\r
+}\r
+\r
+/**\r
+ * @brief Get semaphore Key .\r
+ * @retval Semaphore Key , value from 0 to 0xFFFF\r
+ */\r
+uint32_t HAL_HSEM_GetClearKey(void)\r
+{\r
+ return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management\r
+ * @brief HSEM Notification functions.\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### HSEM IRQ handler management and Notification functions #####\r
+ ==============================================================================\r
+[..] This section provides HSEM IRQ handler and Notification function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Activate Semaphore release Notification for a given Semaphores Mask .\r
+ * @param SemMask: Mask of Released semaphores\r
+ * @retval Semaphore Key\r
+ */\r
+void HAL_HSEM_ActivateNotification(uint32_t SemMask)\r
+{\r
+#if USE_MULTI_CORE_SHARED_CODE != 0U\r
+ /*enable the semaphore mask interrupts */\r
+ if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)\r
+ {\r
+ /*Use interrupt line 0 for CPU1 Master */\r
+ HSEM->C1IER |= SemMask;\r
+ }\r
+ else /* HSEM_CPU2_COREID */\r
+ {\r
+ /*Use interrupt line 1 for CPU2 Master*/\r
+ HSEM->C2IER |= SemMask;\r
+ }\r
+#else\r
+ HSEM_COMMON->IER |= SemMask;\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Deactivate Semaphore release Notification for a given Semaphores Mask .\r
+ * @param SemMask: Mask of Released semaphores\r
+ * @retval Semaphore Key\r
+ */\r
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask)\r
+{\r
+#if USE_MULTI_CORE_SHARED_CODE != 0U\r
+ /*enable the semaphore mask interrupts */\r
+ if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)\r
+ {\r
+ /*Use interrupt line 0 for CPU1 Master */\r
+ HSEM->C1IER &= ~SemMask;\r
+ }\r
+ else /* HSEM_CPU2_COREID */\r
+ {\r
+ /*Use interrupt line 1 for CPU2 Master*/\r
+ HSEM->C2IER &= ~SemMask;\r
+ }\r
+#else\r
+ HSEM_COMMON->IER &= ~SemMask;\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief This function handles HSEM interrupt request\r
+ * @retval None\r
+ */\r
+void HAL_HSEM_IRQHandler(void)\r
+{\r
+ uint32_t statusreg;\r
+#if USE_MULTI_CORE_SHARED_CODE != 0U\r
+ if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)\r
+ {\r
+ /* Get the list of masked freed semaphores*/\r
+ statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/\r
+\r
+ /*Disable Interrupts*/\r
+ HSEM->C1IER &= ~((uint32_t)statusreg);\r
+\r
+ /*Clear Flags*/\r
+ HSEM->C1ICR = ((uint32_t)statusreg);\r
+ }\r
+ else /* HSEM_CPU2_COREID */\r
+ {\r
+ /* Get the list of masked freed semaphores*/\r
+ statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/\r
+\r
+ /*Disable Interrupts*/\r
+ HSEM->C2IER &= ~((uint32_t)statusreg);\r
+\r
+ /*Clear Flags*/\r
+ HSEM->C2ICR = ((uint32_t)statusreg);\r
+ }\r
+#else\r
+ /* Get the list of masked freed semaphores*/\r
+ statusreg = HSEM_COMMON->MISR;\r
+\r
+ /*Disable Interrupts*/\r
+ HSEM_COMMON->IER &= ~((uint32_t)statusreg);\r
+\r
+ /*Clear Flags*/\r
+ HSEM_COMMON->ICR = ((uint32_t)statusreg);\r
+\r
+#endif\r
+ /* Call FreeCallback */\r
+ HAL_HSEM_FreeCallback(statusreg);\r
+}\r
+\r
+/**\r
+ * @brief Semaphore Released Callback.\r
+ * @param SemMask: Mask of Released semaphores\r
+ * @retval None\r
+ */\r
+__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(SemMask);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_HSEM_FreeCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_HSEM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_pwr.c\r
+ * @author MCD Application Team\r
+ * @brief PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR PWR\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWR_Private_Constants PWR Private Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
+ * @{\r
+ */\r
+#if !defined (DUAL_CORE)\r
+#define PVD_MODE_IT ((uint32_t)0x00010000U)\r
+#define PVD_MODE_EVT ((uint32_t)0x00020000U)\r
+#endif /* DUAL_CORE */\r
+#define PVD_RISING_EDGE ((uint32_t)0x00000001U)\r
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)\r
+#define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions\r
+ * @brief Initialization and De-Initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and De-Initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ After reset, the backup domain (RTC registers, RTC backup data\r
+ registers and backup SRAM) is protected against possible unwanted\r
+ write accesses.\r
+ To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __HAL_RCC_PWR_CLK_ENABLE() macro.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.\r
+ * @note This functionality is not available in this product.\r
+ * The prototype is kept just to maintain compatibility with other products.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief Enable access to the backup domain (RTC registers, RTC\r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the\r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+ /* Enable access to RTC and backup registers */\r
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @brief Disable access to the backup domain (RTC registers, RTC\r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the\r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+ /* Disable access to RTC and backup registers */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Low Power modes configuration functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+\r
+ *** PVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a\r
+ threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 register).\r
+ (+) A PVDO flag is available to indicate if VDD is higher or lower\r
+ than the PVD threshold. This event is internally connected to the EXTI\r
+ line 16 to generate an interrupt if enabled.\r
+ It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+ *** Wake-up pin configuration ***\r
+ ================================\r
+ [..]\r
+ (+) Wake-up pin is used to wake up the system from Standby mode.\r
+ The pin pull is configurable through the WKUPEPR register to be in No pull-up, Pull-up and Pull-down.\r
+ The pin polarity is configurable through the WKUPEPR register to be active on rising or falling edges.\r
+ (+) There are up to six Wake-up pin in the STM32H7 devices family.\r
+\r
+ *** Low Power modes configuration ***\r
+ =====================================\r
+ [..]\r
+ The device present 3 principles low-power modes features:\r
+ (+) SLEEP mode: Cortex-M7 core stopped and D1, D2 and D3 peripherals kept running.\r
+ (+) STOP mode: all clocks are stopped and the regulator is running in main or low power mode.\r
+ (+) STANDBY mode: D1, D2 and D3 domains enter DSTANDBY mode and the VCORE supply\r
+ regulator is powered off.\r
+\r
+ *** SLEEP mode ***\r
+ ==================\r
+ [..]\r
+ (+) Entry:\r
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)\r
+ function.\r
+\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+\r
+ -@@- The Regulator parameter is not used for the STM32H7 family\r
+ and is kept as parameter just to maintain compatibility with the\r
+ lower power families (STM32L).\r
+ (+) Exit:\r
+ Any peripheral interrupt acknowledged by the nested vectored interrupt\r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** STOP mode ***\r
+ =================\r
+ [..]\r
+ In system Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents\r
+ are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, FLASH can be powered off before\r
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\r
+ It can be switched on again by software after exiting the Stop mode using\r
+ the HAL_PWREx_DisableFlashPowerDown() function.\r
+\r
+ (+) Entry:\r
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)\r
+ function with:\r
+ (++) Regulator:\r
+ (+++) PWR_MAINREGULATOR_ON: Main regulator ON.\r
+ (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.\r
+ (++) STOPEntry:\r
+ (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction\r
+ (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction\r
+ (+) Exit:\r
+ Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+\r
+ *** STANDBY mode ***\r
+ ====================\r
+ [..]\r
+ (+)\r
+ The system Standby mode allows to achieve the lowest power consumption. It is based\r
+ on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.\r
+ The system is consequently powered off. The PLL, the HSI oscillator and\r
+ the HSE oscillator are also switched off. SRAM and register contents are lost\r
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby\r
+ circuitry.\r
+ [..]\r
+ The voltage regulator is OFF.\r
+ (++) Entry:\r
+ (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r
+ (++) Exit:\r
+ (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r
+ wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode ***\r
+ =============================================\r
+ [..]\r
+ (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC\r
+ Wakeup event, a tamper event or a time-stamp event, without depending on\r
+ an external interrupt (Auto-wakeup mode).\r
+ (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes\r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to\r
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it\r
+ is necessary to configure the RTC to detect the tamper or time stamp event using the\r
+ HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration\r
+ * information for the PVD.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage threshold corresponding to each\r
+ * detection level.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+\r
+ /* Set PLS[7:5] bits according to PVDLevel value */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);\r
+\r
+ /* Clear any previous config */\r
+#if !defined (DUAL_CORE)\r
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+#endif /* DUAL_CORE */\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+#if !defined (DUAL_CORE)\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure event mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+ }\r
+#endif /* DUAL_CORE */\r
+\r
+ /* Configure the edge */\r
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+ /* Enable the power voltage detector */\r
+ SET_BIT(PWR->CR1, PWR_CR1_PVDEN);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+ /* Disable the power voltage detector */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);\r
+}\r
+\r
+/**\r
+ * @brief Enable the WakeUp PINx functionality.\r
+ * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r
+ * This parameter can be one of the following legacy values, which sets the default:\r
+ * polarity detection on high level (rising edge):\r
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4,\r
+ * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following values where\r
+ * the user can explicitly states the enabled pin and the chosen polarity.\r
+ * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW\r
+ * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW\r
+ * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW\r
+ * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
+ * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW\r
+ * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW\r
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
+\r
+ /* Enable and Specify the Wake-Up pin polarity and the pull configuration\r
+ for the event detection (rising or falling edge) */\r
+ MODIFY_REG(PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);\r
+}\r
+\r
+/**\r
+ * @brief Disable the WakeUp PINx functionality.\r
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1\r
+ * @arg PWR_WAKEUP_PIN2\r
+ * @arg PWR_WAKEUP_PIN3\r
+ * @arg PWR_WAKEUP_PIN4\r
+ * @arg PWR_WAKEUP_PIN5\r
+ * @arg PWR_WAKEUP_PIN6\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+\r
+ CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));\r
+}\r
+\r
+/**\r
+ * @brief Enter the current core to Sleep mode.\r
+ * @param Regulator: Specifies the regulator state in SLEEP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r
+ * @note This parameter is not used for the STM32H7 family and is kept as parameter\r
+ * just to maintain compatibility with the lower power families.\r
+ * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select SLEEP mode entry */\r
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enter the system to STOP mode.\r
+ * @note This API must be used only for single core devices.\r
+ * @note In System Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting System Stop mode by issuing an interrupt or a wakeup event,\r
+ * the HSI RC oscillator is selected as default system wakeup clock.\r
+ * @note In System STOP mode, when the voltage regulator operates in low power mode,\r
+ * an additional startup delay is incurred when the system is waking up.\r
+ * By keeping the internal regulator ON during Stop mode, the consumption\r
+ * is higher although the startup time is reduced.\r
+ * @param Regulator: Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+ /* Select the regulator state in Stop mode */\r
+ tmpreg = PWR->CR1;\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= (uint32_t)~(PWR_CR1_LPDS);\r
+\r
+ /* Set LPDS bit according to Regulator value */\r
+ tmpreg |= Regulator;\r
+\r
+ /* Store the new value */\r
+ PWR->CR1 = tmpreg;\r
+\r
+#if defined(DUAL_CORE)\r
+ /* Keep DSTOP mode when D1 domain enters Deepsleep */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);\r
+ CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);\r
+#else\r
+ /* Keep DSTOP mode when D1 domain enters Deepsleep */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);\r
+\r
+ /* Keep DSTOP mode when D2 domain enters Deepsleep */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);\r
+\r
+ /* Keep DSTOP mode when D3 domain enters Deepsleep */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);\r
+#endif /*DUAL_CORE*/\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Ensure that all instructions done before entering STOP mode */\r
+ __DSB();\r
+ __ISB();\r
+\r
+ /* Select Stop mode entry */\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Enter the system to STANDBY mode.\r
+ * @note The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.\r
+ * @note When the System exit STANDBY mode by issuing an interrupt or a wakeup event,\r
+ * the HSI RC oscillator is selected as system clock.\r
+ * @retval None.\r
+ */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+#if defined(DUAL_CORE)\r
+ /* Keep DSTANDBY mode when D1 domain enters Deepsleep */\r
+ SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);\r
+ SET_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);\r
+#else\r
+ /* Keep DSTANDBY mode when D1 domain enters Deepsleep */\r
+ SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);\r
+\r
+ /* Keep DSTANDBY mode when D2 domain enters Deepsleep */\r
+ SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);\r
+\r
+ /* Keep DSTANDBY mode when D3 domain enters Deepsleep */\r
+ SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);\r
+#endif /*DUAL_CORE*/\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.\r
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * Setting this bit is useful when the processor is expected to run only on\r
+ * interruptions handling.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.\r
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Enable CORTEX SEVONPEND bit.\r
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes\r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+ /* Set SEVONPEND bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disable CORTEX SEVONPEND bit.\r
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes\r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+ /* Clear SEVONPEND bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD interrupt request.\r
+ * @note This API should be called under the PVD_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWR_PVD_IRQHandler(void)\r
+{\r
+#if defined(DUAL_CORE)\r
+ /* PVD EXTI line interrupt detected */\r
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)\r
+ {\r
+ /* Check PWR EXTI flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PWR EXTI pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check PWR EXTI D2 flag */\r
+ if(__HAL_PWR_PVD_EXTID2_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PWR EXTI D2 pending bit */\r
+ __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();\r
+ }\r
+ }\r
+#else\r
+ /* PVD EXTI line interrupt detected */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PWR EXTI pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+#endif /*DUAL_CORE*/\r
+}\r
+\r
+/**\r
+ * @brief PWR PVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWR_PVDCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_pwr_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of PWR extension peripheral:\r
+ * + Peripheral Extended features functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx PWREx\r
+ * @brief PWR Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWREx_Private_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask\r
+ * @{\r
+ */\r
+#define AVD_MODE_IT ((uint32_t)0x00010000U)\r
+#define AVD_MODE_EVT ((uint32_t)0x00020000U)\r
+#define AVD_RISING_EDGE ((uint32_t)0x00000001U)\r
+#define AVD_FALLING_EDGE ((uint32_t)0x00000002U)\r
+#define AVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value\r
+ * @{\r
+ */\r
+#define PWR_FLAG_SETTING_DELAY_US ((uint32_t)1000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets\r
+ * @{\r
+ */\r
+/* Wake-Up Pins EXTI register mask */\r
+#define PWR_EXTI_WAKEUP_PINS_MASK (uint32_t)(EXTI_IMR2_IM55 | EXTI_IMR2_IM56 | \\r
+ EXTI_IMR2_IM57 | EXTI_IMR2_IM58 | \\r
+ EXTI_IMR2_IM59 | EXTI_IMR2_IM60)\r
+\r
+/* Wake-Up Pins PWR Pin Pull shift offsets */\r
+#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2U\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group1 Power supply control functions\r
+ * @brief Power supply control functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Power supply control functions #####\r
+ ===============================================================================\r
+\r
+ *** Power supply configuration ***\r
+ ==================================\r
+ [..]\r
+ When the system is powered on, the POR monitors VDD supply. Once VDD is above the\r
+ POR threshold level, the voltage regulator is enabled in the default supply\r
+ configuration:\r
+ (+) The Voltage converter output level is set at 1.0 V in accordance with the VOS3\r
+ level configured in PWR D3 domain control register (PWR_D3CR).\r
+ (+) The system is kept in reset mode as long as VCORE is not ok.\r
+ (+) Once VCORE is ok, the system is taken out of reset and the HSI oscillator is enabled.\r
+ (+) Once the oscillator is stable, the system is initialized: Flash memory and option\r
+ bytes are loaded and the CPU starts in Run* mode.\r
+ (+) The software shall then initialize the system including supply configuration\r
+ programming using the HAL_PWREx_ConfigSupply(SupplySource) with:\r
+ (++) SupplySource:\r
+ (+++) PWR_LDO_SUPPLY: VCORE Power Domains are supplied from the LDO according to\r
+ VOS. LDO power mode (Main, LP, Off) will follow system low-power\r
+ modes.\r
+ (+++) PWR_EXTERNAL_SOURCE_SUPPLY: VCORE supplied from external source and LDO bypassed,\r
+ voltage monitoring still active.\r
+ (+) Once the supply configuration has been configured, the HAL_PWREx_ConfigSupply\r
+ function checks the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)\r
+ to guarantee a valid voltage levels:\r
+ (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in\r
+ limited Run* mode, write accesses to the RAMs are not permitted and VOS shall\r
+ not be changed.\r
+ (++) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal\r
+ Run mode, write accesses to RAMs are allowed and VOS can be changed.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+#if defined(SMPS)\r
+/**\r
+ * @brief Configure the system Power Supply.\r
+ * @param SupplySource: Specifies the Power Supply source to set after a system startup.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_LDO_SUPPLY The LDO regulator supplies the Vcore Power Domains.\r
+ * The SMPS regulator is Bypassed.\r
+ *\r
+ * @arg PWR_DIRECT_SMPS_SUPPLY The SMPS supplies the Vcore Power Domains.\r
+ * The LDO is Bypassed.\r
+ *\r
+ * @arg PWR_SMPS_1V8_SUPPLIES_LDO The SMPS 1.8V output supplies the LDO.\r
+ * The Vcore Power Domains are supplied from the LDO.\r
+ *\r
+ * @arg PWR_SMPS_2V5_SUPPLIES_LDO The SMPS 2.5V output supplies the LDO.\r
+ * The Vcore Power Domains are supplied from the LDO.\r
+ *\r
+ * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO The SMPS 1.8V output supplies external circuits and the LDO.\r
+ * The Vcore Power Domains are supplied from the LDO.\r
+ *\r
+ * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO The SMPS 2.5V output supplies external circuits and the LDO.\r
+ * The Vcore Power Domains are supplied from the LDO.\r
+ *\r
+ * @arg PWR_SMPS_1V8_SUPPLIES_EXT The SMPS 1.8V output supplies external circuits.\r
+ * The LDO is Bypassed.\r
+ * The Vcore Power Domains are supplied from external source.\r
+ *\r
+ * @arg PWR_SMPS_2V5_SUPPLIES_EXT The SMPS 2.5V output supplies external circuits.\r
+ * The LDO is Bypassed.\r
+ * The Vcore Power Domains are supplied from external source.\r
+ *\r
+ * @arg PWR_EXTERNAL_SOURCE_SUPPLY The SMPS and the LDO are Bypassed.\r
+ * The Vcore Power Domains are supplied from external source.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_SUPPLY(SupplySource));\r
+\r
+ if((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))\r
+ {\r
+ if((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)\r
+ {\r
+ /* Supply configuration update locked, can't apply a new regulator config */\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Set the power supply configuration */\r
+ MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till voltage level flag is set */\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */\r
+ if((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\r
+ (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\r
+ (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) ||\r
+ (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till SMPS external supply ready flag is set */\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_SMPSEXTRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+#else\r
+/**\r
+ * @brief Configure the system Power Supply.\r
+ * @param SupplySource: Specifies the Power Supply source to set after a system startup.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_LDO_SUPPLY The LDO regulator supplies the Vcore Power Domains.\r
+ *\r
+ * @arg PWR_EXTERNAL_SOURCE_SUPPLY The LDO regulator is Bypassed.\r
+ * The Vcore Power Domains are supplied from external source.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_SUPPLY(SupplySource));\r
+\r
+ if(!__HAL_PWR_GET_FLAG(PWR_FLAG_SCUEN))\r
+ {\r
+ if((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)\r
+ {\r
+ /* Supply configuration update locked, can't apply a new regulator config */\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Set the power supply configuration */\r
+ MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till voltage level flag is set */\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+#endif /*SMPS*/\r
+\r
+\r
+/**\r
+ * @brief Get the power supply configuration.\r
+ * @retval The supply configuration.\r
+ */\r
+uint32_t HAL_PWREx_GetSupplyConfig(void)\r
+{\r
+ return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Configure the main internal regulator output voltage.\r
+ * @param VoltageScaling: Specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode.\r
+ * @note When moving from Range 1 to Range 2, the system frequency must be decreased\r
+ * before calling HAL_PWREx_ControlVoltageScaling() API.\r
+ * When moving from Range 2 to Range 1, the system frequency can be increased\r
+ * after calling HAL_PWREx_ControlVoltageScaling() API.\r
+ * @note When moving from a Range to an other one, the API waits for VOSRDY flag to be\r
+ * set before returning the status. If the flag is not set within 1000 microseconds,\r
+ * HAL_TIMEOUT status is reported.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));\r
+\r
+ /* Set the voltage range */\r
+ MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until the VOSRDY flag is set */\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get the main internal regulator output voltage.\r
+ * Reflecting the last VOS value applied to the PMU.\r
+ * @retval The actual applied VOS for VDD11 Voltage Scaling selection.\r
+ */\r
+uint32_t HAL_PWREx_GetVoltageRange(void)\r
+{\r
+ return (PWR->CSR1 & PWR_CSR1_ACTVOS);\r
+}\r
+\r
+/**\r
+ * @brief Configure the main internal regulator output voltage in STOP mode.\r
+ * @param VoltageScaling: Specifies the regulator output voltage when the system enters\r
+ * Stop mode to achieve a tradeoff between performance and power consumption.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_SVOS_SCALE3: Regulator voltage output range 3 mode.\r
+ * @arg PWR_REGULATOR_SVOS_SCALE4: Regulator voltage output range 4 mode.\r
+ * @arg PWR_REGULATOR_SVOS_SCALE5: Regulator voltage output range 5 mode.\r
+ * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage regulator\r
+ * in Low-power (LP) mode to further reduce power consumption.\r
+ * When preselecting SVOS3, the use of the voltage regulator low-power mode (LP)\r
+ * can be selected by LPDS register bit.\r
+ * @note The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting\r
+ * from system Stop mode.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)\r
+{\r
+ assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling));\r
+\r
+ /* Set the stop mode voltage range */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get the main internal regulator output voltage in STOP mode.\r
+ * @retval The actual applied VOS for VDD11 Voltage Scaling selection.\r
+ */\r
+uint32_t HAL_PWREx_GetStopModeVoltageRange(void)\r
+{\r
+ return (PWR->CR1 & PWR_CR1_SVOS);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group2 Low power control functions\r
+ * @brief Low power control functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Low power control functions #####\r
+ ===============================================================================\r
+\r
+ *** Domains Low Power modes configuration ***\r
+ =============================================\r
+ [..]\r
+ The system present 3 principles domains (D1, D2 and D3) that can be operated\r
+ in low-power modes (DSTOP or DSTANDBY mode):\r
+\r
+ (+) DSTOP mode to enters a domain to STOP mode:\r
+ (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU\r
+ subsystem is in CSTOP mode and has allocated peripheral in the domain.\r
+ In DSTOP mode the domain bus matrix clock is stopped.\r
+ (++) The system enters STOP mode using one of the following scenarios:\r
+ (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains enter DSTOP mode.\r
+ (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains enter DSTOP mode.\r
+ (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains enter DSTOP mode.\r
+ (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain enters DSTOP mode.\r
+ (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain enters DSTOP mode.\r
+ (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain enters DSTOP mode.\r
+ (+++) D1, D2 and D3 domains enter DSTOP mode.\r
+ (++) When the system enters STOP mode, the clocks are stopped and the regulator is running\r
+ in main or low power mode.\r
+ (++) D3 domain can be kept in Run mode regardless of the CPU status when enter\r
+ STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.\r
+\r
+ (+) DSTANDBY mode to enters a domain to STANDBY mode:\r
+ (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control register\r
+ (PWR_CPUCR) for the Dn domain selects Standby mode.\r
+ (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter DSTANDBY mode.\r
+ Consequently the VCORE supply regulator is powered off.\r
+\r
+ *** DSTOP mode ***\r
+ ==================\r
+ [..]\r
+ In DStop mode the domain bus matrix clock is stopped.\r
+ The Flash memory can enter low-power Stop mode when it is enabled through FLPS in\r
+ PWR_CR1 register. This allows a trade-off between domain DStop restart time and low\r
+ power consumption.\r
+ [..]\r
+ In DStop mode domain peripherals using the LSI or LSE clock and peripherals having a\r
+ kernel clock request are still able to operate.\r
+ [..]\r
+ Before entering DSTOP mode it is recommended to call SCB_CleanDCache function\r
+ in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.\r
+\r
+ (+) Entry:\r
+ The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, STOPEntry, Domain)\r
+ function with:\r
+ (++) Regulator:\r
+ (+++) PWR_MAINREGULATOR_ON: Main regulator ON.\r
+ (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.\r
+ (++) STOPEntry:\r
+ (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction\r
+ (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction\r
+ (++) Domain:\r
+ (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTOP mode.\r
+ (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTOP mode.\r
+ (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTOP mode.\r
+\r
+ (+) Exit:\r
+ Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+\r
+ *** DSTANDBY mode ***\r
+ ====================\r
+ [..]\r
+ In DStandby mode:\r
+ (+) The domain bus matrix clock is stopped.\r
+ (+) The domain is powered down and the domain RAM and register contents are lost.\r
+ [..]\r
+ Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function\r
+ in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.\r
+\r
+ (+) Entry:\r
+ The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode(Domain) function with:\r
+ (++) Domain:\r
+ (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTANDBY mode.\r
+ (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTANDBY mode.\r
+ (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTANDBY mode.\r
+\r
+ (+) Exit:\r
+ WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r
+ wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Keep D3 in RUN mode ***\r
+ ===========================\r
+ [..]\r
+ D3 domain can be kept in Run mode regardless of the CPU status when enter\r
+ STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function with:\r
+ (+) D3State:\r
+ (++) PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.\r
+ (++) PWR_D3_DOMAIN_RUN: D3 domain remains in Run mode regardless of CPU subsystem mode.\r
+\r
+ *** FLASH Power Down configuration ****\r
+ =======================================\r
+ [..]\r
+ By setting the FLPS bit in the PWR_CR1 register using the HAL_PWREx_EnableFlashPowerDown()\r
+ function, the Flash memory also enters power down mode when the device enters Stop mode.\r
+ When the Flash memory is in power down mode, an additional startup delay is incurred when\r
+ waking up from Stop mode.\r
+\r
+ *** Wakeup Pins configuration ****\r
+ ===================================\r
+ [..]\r
+ Wakeup pins allow the system to exit from Standby mode. The configuration of\r
+ wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) function with:\r
+ (+) sPinParams: structure to enable and configure a wakeup pin:\r
+ (++) WakeUpPin: Wakeup pin to be enabled.\r
+ (++) PinPolarity: Wakeup pin polarity (rising or falling edge).\r
+ (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).\r
+ [..]\r
+ The wakeup pins are internally connected to the EXTI lines [55-60] to generate an interrupt\r
+ if enabled. The EXTI lines configuration is done by the HAL_EXTI_Dx_EventInputConfig() functions\r
+ defined in the stm32h7xxhal.c file.\r
+ [..]\r
+ When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is called\r
+ and the appropriate flag is set in the PWR_WKUPFR register. Then in the HAL_PWREx_WAKEUP_PIN_IRQHandler\r
+ function the wakeup pin flag will be cleared and the appropriate user callback will be called.\r
+ The user can add his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enter a Domain to DSTOP mode.\r
+ * @note In DStop mode the domain bus matrix clock is stopped.\r
+ * @note The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode,\r
+ * the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU\r
+ * control register (PWR_CPUCR) for any domain request Stop.\r
+ * @note In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or\r
+ * DStandby mode.\r
+ * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache function\r
+ * in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.\r
+ * @note In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the\r
+ * peripherals that have a kernel clock request to select HSI or CSI as source,\r
+ * are still able to operate.\r
+ * @param Regulator: Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPENTRY_WFI: Enter DStop mode with WFI instruction\r
+ * @arg PWR_STOPENTRY_WFE: Enter DStop mode with WFE instruction\r
+ * @param Domain: Specifies the Domain to enter STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTOP mode.\r
+ * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTOP mode.\r
+ * @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTOP mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+ assert_param(IS_PWR_DOMAIN(Domain));\r
+\r
+ /* Select the regulator state in Stop mode */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, Regulator);\r
+\r
+ /* Select the domain Power Down DeepSleep */\r
+ if (Domain == PWR_D1_DOMAIN)\r
+ {\r
+ /* Check Core */\r
+ assert_param(IS_PWR_D1_CPU(HAL_GetCurrentCPUID()));\r
+\r
+ /* Keep DSTOP mode when D1 domain enters Deepsleep */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);\r
+\r
+#if defined(DUAL_CORE)\r
+ CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);\r
+#endif /*DUAL_CORE*/\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Ensure that all instructions done before entering STOP mode */\r
+ __DSB();\r
+ __ISB();\r
+\r
+ /* Select Stop mode entry */\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r
+ }\r
+ else if (Domain == PWR_D2_DOMAIN)\r
+ {\r
+ /* Keep DSTOP mode when D2 domain enters Deepsleep */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);\r
+\r
+#if defined(DUAL_CORE)\r
+ /* Check Core */\r
+ assert_param(IS_PWR_D2_CPU(HAL_GetCurrentCPUID()));\r
+\r
+ CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Ensure that all instructions done before entering STOP mode */\r
+ __DSB();\r
+ __ISB();\r
+\r
+ /* Select Stop mode entry */\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r
+#endif /*DUAL_CORE*/\r
+ }\r
+ else\r
+ {\r
+ /* Keep DSTOP mode when D3 domain enters Deepsleep */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);\r
+\r
+#if defined(DUAL_CORE)\r
+ CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);\r
+#endif /*DUAL_CORE*/\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clear pending event.\r
+ * @note This API clear the pending event in order to enter a given domain to DSTOP. It should\r
+ * be called just before enter low power mode APIs using Wait For Event request.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_ClearPendingEvent(void)\r
+{\r
+#if defined(DUAL_CORE)\r
+ /* Check Core */\r
+ if(HAL_GetCurrentCPUID() == CM7_CPUID)\r
+ {\r
+ __WFE();\r
+ }\r
+ else\r
+ {\r
+ __SEV();\r
+ __WFE();\r
+ }\r
+#else\r
+ __WFE();\r
+#endif /*DUAL_CORE*/\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enter a Domain to DSTANDBY mode.\r
+ * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain\r
+ * select Standby mode. When the system enters Standby mode, the voltage regulator\r
+ * is disabled.\r
+ * @note When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn\r
+ * bit to select Stop mode, the domain remains in DStandby mode. The domain will only\r
+ * exit DStandby when the CPU allocates a peripheral in the domain.\r
+ * @note The system D3 domain enters Standby mode only when the D1 and D2 domain are in\r
+ * DStandby.\r
+ * @note Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function\r
+ * in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.\r
+ * @param Domain: Specifies the Domain to enter to STANDBY mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTANDBY mode.\r
+ * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.\r
+ * @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTANDBY mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_DOMAIN(Domain));\r
+\r
+ /* Select the domain Power Down DeepSleep */\r
+ if (Domain == PWR_D1_DOMAIN)\r
+ {\r
+ /* Check Core */\r
+ assert_param(IS_PWR_D1_CPU(HAL_GetCurrentCPUID()));\r
+\r
+ /* Allow DSTANDBY mode when D1 domain enters Deepsleep */\r
+ SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D1);\r
+\r
+#if defined(DUAL_CORE)\r
+ SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);\r
+#endif /*DUAL_CORE*/\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else if (Domain == PWR_D2_DOMAIN)\r
+ {\r
+ /* Allow DSTANDBY mode when D2 domain enters Deepsleep */\r
+ SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D2);\r
+\r
+#if defined(DUAL_CORE)\r
+ /* Check Core */\r
+ assert_param(IS_PWR_D2_CPU(HAL_GetCurrentCPUID()));\r
+\r
+ SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+#endif /*DUAL_CORE*/\r
+ }\r
+ else\r
+ {\r
+ /* Allow DSTANDBY mode when D3 domain enters Deepsleep */\r
+ SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D3);\r
+\r
+#if defined(DUAL_CORE)\r
+ SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);\r
+#endif /*DUAL_CORE*/\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the D3 Domain state when the CPU is in low power mode.\r
+ * @param D3State: Specifies the D3 state.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.\r
+ * @arg PWR_D3_DOMAIN_RUN : D3 domain will stay in RUN mode regardless of the\r
+ * CPU sub-system mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_ConfigD3Domain(uint32_t D3State)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_D3_STATE(D3State));\r
+\r
+ /* Keep D3 in run mode */\r
+ MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);\r
+#if defined(DUAL_CORE)\r
+ MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_RUN_D3, D3State);\r
+#endif /*DUAL_CORE*/\r
+}\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a given domain.\r
+ * @param DomainFlags: Specifies the Domain flags to be cleared.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_D1_DOMAIN_FLAGS: Clear D1 Domain flags.\r
+ * @arg PWR_D2_DOMAIN_FLAGS: Clear D2 Domain flags.\r
+ * @retval None.\r
+ */\r
+void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_DOMAIN_FLAG(DomainFlags));\r
+\r
+ if (DomainFlags == PWR_D1_DOMAIN_FLAGS)\r
+ {\r
+ /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */\r
+ SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);\r
+ }\r
+ else\r
+ {\r
+ /* Clear D2 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */\r
+ SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);\r
+ }\r
+}\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Hold the CPU and their allocated peripherals when exiting from STOP mode.\r
+ * @param CPU: Specifies the core to be held.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.\r
+ * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CORE(CPU));\r
+\r
+ if (PWR_CORE_CPU2 == CPU)\r
+ {\r
+ /* If CPU1 is not held */\r
+ if(PWR_CPU2CR_HOLD1 != (PWR->CPU2CR & PWR_CPU2CR_HOLD1))\r
+ {\r
+ /* Set HOLD2 bit */\r
+ SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else if (PWR_CORE_CPU1 == CPU)\r
+ {\r
+ /* If CPU2 is not held */\r
+ if(PWR_CPUCR_HOLD2 != (PWR->CPUCR & PWR_CPUCR_HOLD2))\r
+ {\r
+ /* Set HOLD1 bit */\r
+ SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ return status;\r
+}\r
+#endif /*DUAL_CORE*/\r
+\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Release the CPU and their allocated peripherals after a wake-up from STOP mode.\r
+ * @param CPU: Specifies the core to be released.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_CORE_CPU1: Release the CPU1 and their allocated peripherals from holding.\r
+ * @arg PWR_CORE_CPU2: Release the CPU2 and their allocated peripherals from holding.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_ReleaseCore(uint32_t CPU)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CORE(CPU));\r
+\r
+ if (PWR_CORE_CPU2 == CPU)\r
+ {\r
+ /* Reset HOLD2 bit */\r
+ CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);\r
+ }\r
+ else\r
+ {\r
+ /* Reset HOLD1 bit */\r
+ CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);\r
+ }\r
+}\r
+#endif /*DUAL_CORE*/\r
+\r
+/**\r
+ * @brief Enable the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableFlashPowerDown(void)\r
+{\r
+ /* Enable the Flash Power Down */\r
+ SET_BIT(PWR->CR1, PWR_CR1_FLPS);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableFlashPowerDown(void)\r
+{\r
+ /* Disable the Flash Power Down */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Wake-up PINx functionality.\r
+ * @param sPinParams: pointer to an PWREx_WakeupPinTypeDef structure that contains\r
+ * the configuration informations for the wake-up Pin.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams)\r
+{\r
+ uint32_t pinConfig;\r
+ uint32_t regMask;\r
+ const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin));\r
+ assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity));\r
+ assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull));\r
+\r
+ pinConfig = sPinParams->WakeUpPin | \\r
+ (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \\r
+ (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));\r
+\r
+ regMask = sPinParams->WakeUpPin | \\r
+ (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \\r
+ (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));\r
+\r
+ /* Enable and Specify the Wake-Up pin polarity and the pull configuration\r
+ for the event detection (rising or falling edge) */\r
+ MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig);\r
+#ifndef DUAL_CORE\r
+ /* Configure the Wakeup Pin EXTI Line */\r
+ MODIFY_REG(EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Disable the Wake-up PINx functionality.\r
+ * @param WakeUpPin: Specifies the Wake-Up pin to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1: Disable PA0 wake-up PIN.\r
+ * @arg PWR_WAKEUP_PIN2: Disable PA2 wake-up PIN..\r
+ * @arg PWR_WAKEUP_PIN3: Disable PI8 wake-up PIN..\r
+ * @arg PWR_WAKEUP_PIN4: Disable PC13 wake-up PIN..\r
+ * @arg PWR_WAKEUP_PIN5: Disable PI11 wake-up PIN..\r
+ * @arg PWR_WAKEUP_PIN6: Disable PC1 wake-up PIN..\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));\r
+\r
+ /* Disable the WakeUpPin */\r
+ CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);\r
+}\r
+\r
+/**\r
+ * @brief Get the Wake-Up Pin flag.\r
+ * @param WakeUpFlag: Specifies the Wake-Up PIN flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_FLAG1: A wakeup event was received from PA0.\r
+ * @arg PWR_WAKEUP_FLAG2: A wakeup event was received from PA2.\r
+ * @arg PWR_WAKEUP_FLAG3: A wakeup event was received from PC1.\r
+ * @arg PWR_WAKEUP_FLAG4: A wakeup event was received from PC13.\r
+ * @arg PWR_WAKEUP_FLAG5: A wakeup event was received from PI8.\r
+ * @arg PWR_WAKEUP_FLAG6: A wakeup event was received from PI11.\r
+ * @retval The Wake-Up pin flag.\r
+ */\r
+uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));\r
+\r
+ return (PWR->WKUPFR & WakeUpFlag);\r
+}\r
+\r
+/**\r
+ * @brief Clear the Wake-Up pin flag.\r
+ * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_FLAG1: Clear the wakeup event received from PA0.\r
+ * @arg PWR_WAKEUP_FLAG2: Clear the wakeup event received from PA2.\r
+ * @arg PWR_WAKEUP_FLAG3: Clear the wakeup event received from PC1.\r
+ * @arg PWR_WAKEUP_FLAG4: Clear the wakeup event received from PC13.\r
+ * @arg PWR_WAKEUP_FLAG5: Clear the wakeup event received from PI8.\r
+ * @arg PWR_WAKEUP_FLAG6: Clear the wakeup event received from PI11.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));\r
+\r
+ SET_BIT(PWR->WKUPCR, WakeUpFlag);\r
+\r
+ if((PWR->WKUPFR & WakeUpFlag) != 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles the PWR WAKEUP PIN interrupt request.\r
+ * @note This API should be called under the WAKEUP_PIN_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void)\r
+{\r
+ /* Wakeup pin EXTI line interrupt detected */\r
+ if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)\r
+ {\r
+ /* Clear PWR WKUPF1 flag */\r
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);\r
+\r
+ /* PWR WKUP1 interrupt user callback */\r
+ HAL_PWREx_WKUP1_Callback();\r
+ }\r
+ else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)\r
+ {\r
+ /* Clear PWR WKUPF2 flag */\r
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);\r
+\r
+ /* PWR WKUP2 interrupt user callback */\r
+ HAL_PWREx_WKUP2_Callback();\r
+ }\r
+ else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)\r
+ {\r
+ /* Clear PWR WKUPF3 flag */\r
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);\r
+\r
+ /* PWR WKUP3 interrupt user callback */\r
+ HAL_PWREx_WKUP3_Callback();\r
+ }\r
+ else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)\r
+ {\r
+ /* Clear PWR WKUPF4 flag */\r
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);\r
+\r
+ /* PWR WKUP4 interrupt user callback */\r
+ HAL_PWREx_WKUP4_Callback();\r
+ }\r
+ else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)\r
+ {\r
+ /* Clear PWR WKUPF5 flag */\r
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);\r
+\r
+ /* PWR WKUP5 interrupt user callback */\r
+ HAL_PWREx_WKUP5_Callback();\r
+ }\r
+ else\r
+ {\r
+ /* Clear PWR WKUPF6 flag */\r
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);\r
+\r
+ /* PWR WKUP6 interrupt user callback */\r
+ HAL_PWREx_WKUP6_Callback();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief PWR WKUP1 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_WKUP1_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWREx_WKUP1Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWR WKUP2 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_WKUP2_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWREx_WKUP2Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWR WKUP3 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_WKUP3_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWREx_WKUP3Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWR WKUP4 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_WKUP4_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWREx_WKUP4Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWR WKUP5 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_WKUP5_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWREx_WKUP5Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWR WKUP6 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_WKUP6_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWREx_WKUP6Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions\r
+ * @brief Peripherals control functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripherals control functions #####\r
+ ===============================================================================\r
+\r
+ *** Main and Backup Regulators configuration ***\r
+ ================================================\r
+ [..]\r
+ (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from\r
+ the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is\r
+ retained even in Standby or VBAT mode when the low power backup regulator\r
+ is enabled. It can be considered as an internal EEPROM when VBAT is\r
+ always present. You can use the HAL_PWREx_EnableBkUpReg() function to\r
+ enable the low power backup regulator.\r
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD)\r
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to\r
+ save battery life.\r
+ (+) The backup SRAM is not mass erased by a tamper event. It is read\r
+ protected to prevent confidential data, such as cryptographic private\r
+ key, from being accessed. The backup SRAM can be erased only through\r
+ the Flash interface when a protection level change from level 1 to\r
+ level 0 is requested.\r
+ -@- Refer to the description of Read protection (RDP) in the Flash\r
+ programming manual.\r
+ (+) The main internal regulator can be configured to have a tradeoff between\r
+ performance and power consumption when the device does not operate at\r
+ the maximum frequency. This is done through HAL_PWREx_ControlVoltageScaling(VOS)\r
+ function which configure the VOS bit in PWR_D3CR register.\r
+ (+) The main internal regulator can be configured to operate in Low Power mode\r
+ when the system enter STOP mode to further reduce power consumption.\r
+ This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)\r
+ function which configure the SVOS bit in PWR_CR1 register.\r
+ The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from\r
+ system Stop mode.\r
+ -@- Refer to the product datasheets for more details.\r
+\r
+ *** USB Regulator configuration ***\r
+ ===================================\r
+ [..]\r
+ (+) The USB transceivers are supplied from a dedicated VDD33USB supply that can be\r
+ provided either by the integrated USB regulator, or by an external USB supply.\r
+ (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the VDD33USB\r
+ is then provided from the USB regulator.\r
+ (+) When the USB regulator is enabled, the VDD33USB supply level detector shall\r
+ be enabled through HAL_PWREx_EnableUSBVoltageDetector() function.\r
+ (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() function and VDD33USB\r
+ can be provided from an external supply. In this case VDD33USB and VDD50USB shall\r
+ be connected together\r
+\r
+ *** VBAT battery charging ***\r
+ =============================\r
+ [..]\r
+ (+) When VDD is present, the external battery connected to VBAT can be charged through an\r
+ internal resistance. VBAT charging can be performed either through a 5 KOhm resistor\r
+ or through a 1.5 KOhm resistor.\r
+ (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging(ResistorValue) function\r
+ with:\r
+ (++) ResistorValue:\r
+ (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.\r
+ (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.\r
+ (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Enable the Backup regulator */\r
+ SET_BIT(PWR->CR2, PWR_CR2_BREN);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is set */\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_BRR))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Disable the Backup regulator */\r
+ CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is reset */\r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the USB Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Enable the USB regulator */\r
+ SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till the USB regulator ready flag is set */\r
+ while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the USB Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Disable the USB regulator */\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till the USB regulator ready flag is reset */\r
+ while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the USB voltage level detector.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableUSBVoltageDetector(void)\r
+{\r
+ /* Enable the USB voltage detector */\r
+ SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);\r
+}\r
+\r
+/**\r
+ * @brief Disable the USB voltage level detector.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableUSBVoltageDetector(void)\r
+{\r
+ /* Disable the USB voltage detector */\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable the Battery charging.\r
+ * When VDD is present, charge the external battery through an internal resistor.\r
+ * @param ResistorValue: Specifies the charging resistor.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.\r
+ * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)\r
+{\r
+ assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));\r
+\r
+ /* Specify the charging resistor */\r
+ MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, ResistorValue);\r
+\r
+ /* Enable the Battery charging */\r
+ SET_BIT(PWR->CR3, PWR_CR3_VBE);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable the Battery charging.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableBatteryCharging(void)\r
+{\r
+ /* Disable the Battery charging */\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions\r
+ * @brief Power Monitoring functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Power Monitoring functions #####\r
+ ===============================================================================\r
+\r
+ *** VBAT and Temperature supervision ***\r
+ ========================================\r
+ [..]\r
+ (+) The VBAT battery voltage supply can be monitored by comparing it with two threshold\r
+ levels: VBAThigh and VBATlow. VBATH flag and VBATL flags in the PWR control register 2\r
+ (PWR_CR2), indicate if VBAT is higher or lower than the threshold.\r
+ (+) The temperature can be monitored by comparing it with two threshold levels, TEMPhigh\r
+ and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2 (PWR_CR2),\r
+ indicate whether the device temperature is higher or lower than the threshold.\r
+ (+) The VBAT and the temperature monitoring is enabled by HAL_PWREx_EnableMonitoring()\r
+ function and disabled by HAL_PWREx_DisableMonitoring() function.\r
+ (+) The HAL_PWREx_GetVBATLevel() function return the VBAT level which can be:\r
+ PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or\r
+ PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.\r
+ (+) The HAL_PWREx_GetTemperatureLevel() function return the Temperature level which\r
+ can be: PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or\r
+ PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.\r
+\r
+ *** AVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The AVD is used to monitor the VDDA power supply by comparing it to a\r
+ threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 register).\r
+ (+) A AVDO flag is available to indicate if VDDA is higher or lower\r
+ than the AVD threshold. This event is internally connected to the EXTI\r
+ line 16 to generate an interrupt if enabled.\r
+ It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.\r
+ (+) The AVD is stopped in System Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the VBAT and temperature monitoring.\r
+ * @retval HAL status\r
+ */\r
+void HAL_PWREx_EnableMonitoring(void)\r
+{\r
+ /* Enable the VBAT and Temperature monitoring */\r
+ SET_BIT(PWR->CR2, PWR_CR2_MONEN);\r
+}\r
+\r
+/**\r
+ * @brief Disable the VBAT and temperature monitoring.\r
+ * @retval HAL status\r
+ */\r
+void HAL_PWREx_DisableMonitoring(void)\r
+{\r
+ /* Disable the VBAT and Temperature monitoring */\r
+ CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);\r
+}\r
+\r
+/**\r
+ * @brief Indicate whether the junction temperature is between, above or below the threshold.\r
+ * @retval Temperature level.\r
+ */\r
+uint32_t HAL_PWREx_GetTemperatureLevel(void)\r
+{\r
+ uint32_t tempLevel;\r
+ uint32_t regValue;\r
+\r
+ /* Read the temperature flags */\r
+ regValue = PWR->CR2 & (PWR_CR2_TEMPH | PWR_CR2_TEMPL);\r
+\r
+ /* Compare the read value to the temperature threshold */\r
+ if(regValue == PWR_CR2_TEMPL)\r
+ {\r
+ tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;\r
+ }\r
+ else if(regValue == PWR_CR2_TEMPH)\r
+ {\r
+ tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;\r
+ }\r
+ else\r
+ {\r
+ tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;\r
+ }\r
+\r
+ return tempLevel;\r
+}\r
+\r
+/**\r
+ * @brief Indicate whether the Battery voltage level is between, above or below the threshold.\r
+ * @retval VBAT level.\r
+ */\r
+uint32_t HAL_PWREx_GetVBATLevel(void)\r
+{\r
+ uint32_t VBATLevel;\r
+ uint32_t regValue;\r
+\r
+ /* Read the VBAT flags */\r
+ regValue = PWR->CR2 & (PWR_CR2_VBATH | PWR_CR2_VBATL);\r
+\r
+ /* Compare the read value to the VBAT threshold */\r
+ if(regValue == PWR_CR2_VBATL)\r
+ {\r
+ VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;\r
+ }\r
+ else if(regValue == PWR_CR2_VBATH)\r
+ {\r
+ VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;\r
+ }\r
+ else\r
+ {\r
+ VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;\r
+ }\r
+\r
+ return VBATLevel;\r
+}\r
+\r
+/**\r
+ * @brief Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).\r
+ * @param sConfigAVD: pointer to an PWR_AVDTypeDef structure that contains the configuration\r
+ * information for the AVD.\r
+ * @note Refer to the electrical characteristics of your device datasheet for more details\r
+ * about the voltage threshold corresponding to each detection level.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel));\r
+ assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode));\r
+\r
+ /* Set the ALS[18:17] bits according to AVDLevel value */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);\r
+\r
+ /* Clear any previous config */\r
+#if !defined (DUAL_CORE)\r
+ __HAL_PWR_AVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_AVD_EXTI_DISABLE_IT();\r
+#endif\r
+ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();\r
+ __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+#if !defined (DUAL_CORE)\r
+ /* Configure the interrupt mode */\r
+ if(AVD_MODE_IT == (sConfigAVD->Mode & AVD_MODE_IT))\r
+ {\r
+ __HAL_PWR_AVD_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure the event mode */\r
+ if(AVD_MODE_EVT == (sConfigAVD->Mode & AVD_MODE_EVT))\r
+ {\r
+ __HAL_PWR_AVD_EXTI_ENABLE_EVENT();\r
+ }\r
+#endif\r
+ /* Configure the edge */\r
+ if(AVD_RISING_EDGE == (sConfigAVD->Mode & AVD_RISING_EDGE))\r
+ {\r
+ __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if(AVD_FALLING_EDGE == (sConfigAVD->Mode & AVD_FALLING_EDGE))\r
+ {\r
+ __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the Analog Voltage Detector(AVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableAVD(void)\r
+{\r
+ /* Enable the Analog Voltage Detector */\r
+ SET_BIT(PWR->CR1, PWR_CR1_AVDEN);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Analog Voltage Detector(AVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableAVD(void)\r
+{\r
+ /* Disable the Analog Voltage Detector */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);\r
+}\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD/AVD interrupt request.\r
+ * @note This API should be called under the PVD_AVD_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_PVD_AVD_IRQHandler(void)\r
+{\r
+#if defined(DUAL_CORE)\r
+ /* PVD EXTI line interrupt detected */\r
+ if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != 0U)\r
+ {\r
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)\r
+ {\r
+ /* Check PWR D1 EXTI flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PWR EXTI D1 pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check PWR EXTI D2 flag */\r
+ if(__HAL_PWR_PVD_EXTID2_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PWR EXTI D2 pending bit */\r
+ __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();\r
+ }\r
+ }\r
+ }\r
+\r
+ /* AVD EXTI line interrupt detected */\r
+ if(READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != 0U)\r
+ {\r
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)\r
+ {\r
+ /* Check PWR EXTI D1 flag */\r
+ if(__HAL_PWR_AVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR AVD interrupt user callback */\r
+ HAL_PWREx_AVDCallback();\r
+\r
+ /* Clear PWR EXTI D1 pending bit */\r
+ __HAL_PWR_AVD_EXTI_CLEAR_FLAG();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check PWR EXTI D2 flag */\r
+ if(__HAL_PWR_AVD_EXTID2_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR AVD interrupt user callback */\r
+ HAL_PWREx_AVDCallback();\r
+\r
+ /* Clear PWR EXTI D2 pending bit */\r
+ __HAL_PWR_AVD_EXTID2_CLEAR_FLAG();\r
+ }\r
+ }\r
+ }\r
+#else\r
+ /* PVD EXTI line interrupt detected */\r
+ if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != 0U)\r
+ {\r
+ /* Check PWR EXTI flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PWR EXTI pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+ }\r
+\r
+ /* AVD EXTI line interrupt detected */\r
+ if(READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != 0U)\r
+ {\r
+ /* Check PWR EXTI flag */\r
+ if(__HAL_PWR_AVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR AVD interrupt user callback */\r
+ HAL_PWREx_AVDCallback();\r
+\r
+ /* Clear PWR EXTI pending bit */\r
+ __HAL_PWR_AVD_EXTI_CLEAR_FLAG();\r
+ }\r
+ }\r
+#endif /*DUAL_CORE*/\r
+}\r
+\r
+/**\r
+ * @brief PWR AVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_AVDCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWR_AVDCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_rcc.c\r
+ * @author MCD Application Team\r
+ * @brief RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Reset and Clock Control (RCC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### RCC specific features #####\r
+ ==============================================================================\r
+ [..]\r
+ After reset the device is running from Internal High Speed oscillator\r
+ (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except\r
+ internal SRAM, Flash, JTAG and PWR\r
+ (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;\r
+ all peripherals mapped on these buses are running at HSI speed.\r
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ (+) All GPIOs are in analogue mode , except the JTAG pins which\r
+ are assigned to be used for debug purpose.\r
+\r
+ [..]\r
+ Once the device started from reset, the user application has to:\r
+ (+) Configure the clock source to be used to drive the System clock\r
+ (if the application needs higher frequency/performance)\r
+ (+) Configure the System clock frequency and Flash settings\r
+ (+) Configure the AHB and APB buses pre-scalers\r
+ (+) Enable the clock for the peripheral(s) to be used\r
+ (+) Configure the clock kernel source(s) for peripherals which clocks are not\r
+ derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R\r
+ and RCC_D3CCIPR registers\r
+\r
+ ##### RCC Limitations #####\r
+ ==============================================================================\r
+ [..]\r
+ A delay between an RCC peripheral clock enable and the effective peripheral\r
+ enabling should be taken into account in order to manage the peripheral read/write\r
+ from/to registers.\r
+ (+) This delay depends on the peripheral mapping.\r
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle\r
+ after the clock enable bit is set on the hardware register\r
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle\r
+ after the clock enable bit is set on the hardware register\r
+\r
+ [..]\r
+ Implemented Workaround:\r
+ (+) For AHB & APB peripherals, a dummy read to the peripheral register has been\r
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC RCC\r
+ * @brief RCC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()\r
+#define MCO1_GPIO_PORT GPIOA\r
+#define MCO1_PIN GPIO_PIN_8\r
+\r
+#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()\r
+#define MCO2_GPIO_PORT GPIOC\r
+#define MCO2_PIN GPIO_PIN_9\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Variables RCC Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to configure the internal/external oscillators\r
+ (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1\r
+ AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).\r
+\r
+ [..] Internal/external clock and PLL configuration\r
+ (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+ (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral\r
+ clock, or PLL input.But even with frequency calibration, is less accurate than an\r
+ external crystal oscillator or ceramic resonator.\r
+ (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\r
+\r
+ (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),\r
+ featuring three different output clocks and able to work either in integer or Fractional mode.\r
+ (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU\r
+ and to some peripherals.\r
+ (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.\r
+\r
+\r
+ (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs\r
+ (HSE used directly or through PLL as System clock source), the System clock\r
+ is automatically switched to HSI and an interrupt is generated if enabled.\r
+ The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)\r
+ exception vector.\r
+\r
+ (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)\r
+ or HSI48 clock (through a configurable pre-scaler) on PA8 pin.\r
+\r
+ (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,\r
+ LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.\r
+\r
+ [..] System, AHB and APB buses clocks configuration\r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System core clock through configurable\r
+ pre-scaler and used to clock the CPU, memory and peripherals mapped\r
+ on AHB and APB bus of the 3 Domains (D1, D2, D3) through configurable pre-scalers\r
+ and used to clock the peripherals mapped on these buses. You can use\r
+ "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.\r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those\r
+ with dual clock domain where kernel source clock could be selected through\r
+ RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * - HSI ON and used as system clock source\r
+ * - HSE, PLL1, PLL2 and PLL3 OFF\r
+ * - AHB, APB Bus pre-scaler set to 1.\r
+ * - CSS, MCO1 and MCO2 OFF\r
+ * - All interrupts disabled\r
+ * @note This function doesn't modify the configuration of the\r
+ * - Peripheral clocks\r
+ * - LSI, LSE and RTC clocks\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Set HSION bit */\r
+ SET_BIT(RCC->CR, RCC_CR_HSION);\r
+\r
+ /* Wait till HSI is ready */\r
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Set HSITRIM[6:0] bits to the reset value */\r
+ SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);\r
+\r
+ /* Reset CFGR register */\r
+ CLEAR_REG(RCC->CFGR);\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HSI_VALUE;\r
+\r
+ /* Adapt Systick interrupt period */\r
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till clock switch is ready */\r
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON \\r
+ | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);\r
+\r
+ /* Wait till HSE is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Clear PLLON bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);\r
+\r
+ /* Wait till PLL is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Reset PLL2ON bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);\r
+\r
+ /* Wait till PLL2 is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Reset PLL3 bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);\r
+\r
+ /* Wait till PLL3 is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Reset D1CFGR register */\r
+ CLEAR_REG(RCC->D1CFGR);\r
+\r
+ /* Reset D2CFGR register */\r
+ CLEAR_REG(RCC->D2CFGR);\r
+\r
+ /* Reset D3CFGR register */\r
+ CLEAR_REG(RCC->D3CFGR);\r
+\r
+ /* Reset PLLCKSELR register to default value */\r
+ RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;\r
+\r
+ /* Reset PLLCFGR register to default value */\r
+ WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);\r
+\r
+ /* Reset PLL1DIVR register to default value */\r
+ WRITE_REG(RCC->PLL1DIVR,0x01010280U);\r
+\r
+ /* Reset PLL1FRACR register */\r
+ CLEAR_REG(RCC->PLL1FRACR);\r
+\r
+ /* Reset PLL2DIVR register to default value */\r
+ WRITE_REG(RCC->PLL2DIVR,0x01010280U);\r
+\r
+ /* Reset PLL2FRACR register */\r
+ CLEAR_REG(RCC->PLL2FRACR);\r
+\r
+ /* Reset PLL3DIVR register to default value */\r
+ WRITE_REG(RCC->PLL3DIVR,0x01010280U);\r
+\r
+ /* Reset PLL3FRACR register */\r
+ CLEAR_REG(RCC->PLL3FRACR);\r
+\r
+ /* Reset HSEBYP bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
+\r
+ /* Disable all interrupts */\r
+ CLEAR_REG(RCC->CIER);\r
+\r
+ /* Clear all interrupts flags */\r
+ WRITE_REG(RCC->CICR,0xFFFFFFFFU);\r
+\r
+ /* Reset all RSR flags */\r
+ SET_BIT(RCC->RSR, RCC_RSR_RMVF);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the\r
+ * RCC_OscInitTypeDef.\r
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC Oscillators.\r
+ * @note The PLL is not disabled when used as system clock.\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
+ * supported by this function. User should request a transition to LSE Off\r
+ * first and then LSE On or LSE Bypass.\r
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this function. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check Null pointer */\r
+ if(RCC_OscInitStruct == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
+ /*------------------------------- HSE Configuration ------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
+\r
+ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();\r
+ const uint32_t temp_pllckselr = RCC->PLLCKSELR;\r
+ /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */\r
+ if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))\r
+ {\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the new HSE configuration ---------------------------------------*/\r
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
+\r
+ /* Check the HSE State */\r
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)\r
+ {\r
+ if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSE is bypassed or disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)\r
+ {\r
+ if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- HSI Configuration --------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
+ assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
+\r
+ /* When the HSI is used as system clock it will not disabled */\r
+ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();\r
+ const uint32_t temp_pllckselr = RCC->PLLCKSELR;\r
+ if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))\r
+ {\r
+ /* When HSI is used as system clock it will not disabled */\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration is allowed */\r
+ else\r
+ {\r
+ /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */\r
+ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)\r
+ {\r
+ if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ }\r
+\r
+ else\r
+ {\r
+ /* Check the HSI State */\r
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r
+ {\r
+ /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */\r
+ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- CSI Configuration --------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));\r
+ assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));\r
+\r
+ /* When the CSI is used as system clock it will not disabled */\r
+ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();\r
+ const uint32_t temp_pllckselr = RCC->PLLCKSELR;\r
+ if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))\r
+ {\r
+ /* When CSI is used as system clock it will not disabled */\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration is allowed */\r
+ else\r
+ {\r
+ /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/\r
+ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check the CSI State */\r
+ if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)\r
+ {\r
+ /* Enable the Internal High Speed oscillator (CSI). */\r
+ __HAL_RCC_CSI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till CSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/\r
+ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal High Speed oscillator (CSI). */\r
+ __HAL_RCC_CSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till CSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSI Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
+\r
+ /* Check the LSI State */\r
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r
+ {\r
+ /* Enable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /*------------------------------ HSI48 Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));\r
+\r
+ /* Check the HSI48 State */\r
+ if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)\r
+ {\r
+ /* Enable the Internal Low Speed oscillator (HSI48). */\r
+ __HAL_RCC_HSI48_ENABLE();\r
+\r
+ /* Get time-out */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI48 is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal Low Speed oscillator (HSI48). */\r
+ __HAL_RCC_HSI48_DISABLE();\r
+\r
+ /* Get time-out */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI48 is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSE Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
+\r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+\r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((PWR->CR1 & PWR_CR1_DBP) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Set the new LSE configuration -----------------------------------------*/\r
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
+ /* Check the LSE State */\r
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*-------------------------------- PLL Configuration -----------------------*/\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r
+ {\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)\r
+ {\r
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r
+ assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));\r
+\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Configure the main PLL clock source, multiplication and division factors. */\r
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
+ RCC_OscInitStruct->PLL.PLLM,\r
+ RCC_OscInitStruct->PLL.PLLN,\r
+ RCC_OscInitStruct->PLL.PLLP,\r
+ RCC_OscInitStruct->PLL.PLLQ,\r
+ RCC_OscInitStruct->PLL.PLLR);\r
+\r
+ /* Disable PLLFRACN . */\r
+ __HAL_RCC_PLLFRACN_DISABLE();\r
+\r
+ /* Configure PLL PLL1FRACN */\r
+ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);\r
+\r
+ /* Select PLL1 input reference frequency range: VCI */\r
+ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;\r
+\r
+ /* Select PLL1 output frequency range : VCO */\r
+ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;\r
+\r
+ /* Enable PLL System Clock output. */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);\r
+\r
+ /* Enable PLL1Q Clock output. */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* Enable PLL1R Clock output. */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);\r
+\r
+ /* Enable PLL1FRACN . */\r
+ __HAL_RCC_PLLFRACN_ENABLE();\r
+\r
+ /* Enable the main PLL. */\r
+ __HAL_RCC_PLL_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CPU, AHB and APB buses clocks according to the specified\r
+ * parameters in the RCC_ClkInitStruct.\r
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC peripheral.\r
+ * @param FLatency: FLASH Latency, this parameter depend on device selected\r
+ *\r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
+ * and updated by HAL_InitTick() function called within this function\r
+ *\r
+ * @note The HSI is used (enabled by hardware) as system clock source after\r
+ * start-up from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ *\r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after start-up delay or PLL locked).\r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready.\r
+ * You can use HAL_RCC_GetClockConfig() function to know which clock is\r
+ * currently used as system clock source.\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency\r
+ * (for more details refer to section above "Initialization/de-initialization functions")\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)\r
+{\r
+ HAL_StatusTypeDef halstatus;\r
+ uint32_t tickstart;\r
+\r
+ /* Check Null pointer */\r
+ if(RCC_ClkInitStruct == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
+ assert_param(IS_FLASH_LATENCY(FLatency));\r
+\r
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
+ must be correctly programmed according to the frequency of the CPU clock\r
+ (HCLK) and the supply voltage of the device. */\r
+\r
+ /* Increasing the CPU frequency */\r
+ if(FLatency > __HAL_FLASH_GET_LATENCY())\r
+ {\r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ }\r
+\r
+ /* Increasing the BUS frequency divider */\r
+ /*-------------------------- D1PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)\r
+ {\r
+ if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))\r
+ {\r
+ assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));\r
+ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+ {\r
+ if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))\r
+ {\r
+ assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));\r
+ MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK2 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+ {\r
+ if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))\r
+ {\r
+ assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));\r
+ MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));\r
+ }\r
+ }\r
+\r
+ /*-------------------------- D3PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)\r
+ {\r
+ if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))\r
+ {\r
+ assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));\r
+ MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );\r
+ }\r
+ }\r
+\r
+ /*-------------------------- HCLK Configuration --------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+ {\r
+ if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))\r
+ {\r
+ /* Set the new HCLK clock divider */\r
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+ }\r
+ }\r
+\r
+ /*------------------------- SYSCLK Configuration -------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
+ {\r
+ assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));\r
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
+ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);\r
+ /* HSE is selected as System Clock Source */\r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ /* Check the HSE ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* PLL is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ /* Check the PLL ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* CSI is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)\r
+ {\r
+ /* Check the PLL ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* HSI is selected as System Clock Source */\r
+ else\r
+ {\r
+ /* Check the HSI ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ /* Decreasing the BUS frequency divider */\r
+ /*-------------------------- HCLK Configuration --------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+ {\r
+ if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))\r
+ {\r
+ /* Set the new HCLK clock divider */\r
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+ }\r
+ }\r
+\r
+ /* Decreasing the number of wait states because of lower CPU frequency */\r
+ if(FLatency < __HAL_FLASH_GET_LATENCY())\r
+ {\r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- D1PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)\r
+ {\r
+ if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))\r
+ {\r
+ assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));\r
+ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+ {\r
+ if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))\r
+ {\r
+ assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));\r
+ MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK2 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+ {\r
+ if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))\r
+ {\r
+ assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));\r
+ MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));\r
+ }\r
+ }\r
+\r
+ /*-------------------------- D3PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)\r
+ {\r
+ if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))\r
+ {\r
+ assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));\r
+ MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );\r
+ }\r
+ }\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);\r
+\r
+ /* Configure the source of time base considering new system clocks settings*/\r
+ halstatus = HAL_InitTick (TICK_INT_PRIORITY);\r
+\r
+ return halstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group2 Peripheral Control functions\r
+ * @brief RCC clocks control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks\r
+ frequencies.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).\r
+ * @note PA8/PC9 should be configured in alternate function mode.\r
+ * @param RCC_MCOx: specifies the output direction for the clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).\r
+ * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).\r
+ * @param RCC_MCOSource: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source\r
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source\r
+ * @param RCC_MCODiv: specifies the MCOx pre-scaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock\r
+ * @retval None\r
+ */\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCOx));\r
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
+ /* RCC_MCO1 */\r
+ if(RCC_MCOx == RCC_MCO1)\r
+ {\r
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
+\r
+ /* MCO1 Clock Enable */\r
+ MCO1_CLK_ENABLE();\r
+\r
+ /* Configure the MCO1 pin in alternate function mode */\r
+ GPIO_InitStruct.Pin = MCO1_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+ /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));\r
+\r
+ /* MCO2 Clock Enable */\r
+ MCO2_CLK_ENABLE();\r
+\r
+ /* Configure the MCO2 pin in alternate function mode */\r
+ GPIO_InitStruct.Pin = MCO2_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+ /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to\r
+ * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_EnableCSS(void)\r
+{\r
+ SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Clock Security System.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_DisableCSS(void)\r
+{\r
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);\r
+}\r
+\r
+/**\r
+ * @brief Returns the SYSCLK frequency\r
+ *\r
+ * @note The system frequency computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)\r
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)\r
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)\r
+ * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),\r
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.\r
+ * @note (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value\r
+ * 4 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * @note (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value\r
+ * 64 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * @note (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ *\r
+ * @note The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ *\r
+ * @note This function can be used by the user application to compute the\r
+ * baud rate for the communication peripherals or configure other parameters.\r
+ *\r
+ * @note Each time SYSCLK changes, this function must be called to update the\r
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ *\r
+ *\r
+ * @retval SYSCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetSysClockFreq(void)\r
+{\r
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;\r
+ float_t fracn1, pllvco;\r
+ uint32_t sysclockfreq;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+\r
+ switch (RCC->CFGR & RCC_CFGR_SWS)\r
+ {\r
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */\r
+\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));\r
+ }\r
+ else\r
+ {\r
+ sysclockfreq = (uint32_t) HSI_VALUE;\r
+ }\r
+\r
+ break;\r
+\r
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */\r
+ sysclockfreq = CSI_VALUE;\r
+ break;\r
+\r
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */\r
+ sysclockfreq = HSE_VALUE;\r
+ break;\r
+\r
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN\r
+ SYSCLK = PLL_VCO / PLLR\r
+ */\r
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);\r
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;\r
+ pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);\r
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));\r
+\r
+ if (pllm != 0U)\r
+ {\r
+ switch (pllsource)\r
+ {\r
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */\r
+\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));\r
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ else\r
+ {\r
+ pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ break;\r
+\r
+ case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */\r
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */\r
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ default:\r
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+ }\r
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;\r
+ sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp);\r
+ }\r
+ else\r
+ {\r
+ sysclockfreq = 0U;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ sysclockfreq = CSI_VALUE;\r
+ break;\r
+ }\r
+\r
+ return sysclockfreq;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Returns the HCLK frequency\r
+ * @note Each time HCLK changes, this function must be called to update the\r
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ *\r
+ * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency\r
+ * and updated within this function\r
+ * @retval HCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetHCLKFreq(void)\r
+{\r
+ SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));\r
+ return SystemD2Clock;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Returns the PCLK1 frequency\r
+ * @note Each time PCLK1 changes, this function must be called to update the\r
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK1Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Returns the PCLK2 frequency\r
+ * @note Each time PCLK2 changes, this function must be called to update the\r
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK2Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));\r
+}\r
+\r
+/**\r
+ * @brief Configures the RCC_OscInitStruct according to the internal\r
+ * RCC configuration registers.\r
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * will be configured.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ /* Set all possible values for the Oscillator type parameter ---------------*/\r
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \\r
+ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;\r
+\r
+ /* Get the HSE configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
+ }\r
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
+ }\r
+\r
+ /* Get the CSI configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)\r
+ {\r
+ RCC_OscInitStruct->CSIState = RCC_CSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->CSIState = RCC_CSI_OFF;\r
+ }\r
+\r
+ if(HAL_GetREVID() <= REV_ID_Y)\r
+ {\r
+ RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);\r
+ }\r
+\r
+ /* Get the HSI configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
+ }\r
+\r
+ if(HAL_GetREVID() <= REV_ID_Y)\r
+ {\r
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);\r
+ }\r
+\r
+ /* Get the LSE configuration -----------------------------------------------*/\r
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
+ }\r
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
+ }\r
+\r
+ /* Get the LSI configuration -----------------------------------------------*/\r
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
+ }\r
+\r
+ /* Get the HSI48 configuration ---------------------------------------------*/\r
+ if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)\r
+ {\r
+ RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;\r
+ }\r
+\r
+ /* Get the PLL configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
+ }\r
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);\r
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos);\r
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U;\r
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U;\r
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U;\r
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U;\r
+ RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));\r
+ RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);\r
+ RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));\r
+}\r
+\r
+/**\r
+ * @brief Configures the RCC_ClkInitStruct according to the internal\r
+ * RCC configuration registers.\r
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that\r
+ * will be configured.\r
+ * @param pFLatency: Pointer on the Flash Latency.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)\r
+{\r
+ /* Set all possible values for the Clock type parameter --------------------*/\r
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |\r
+ RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ;\r
+\r
+ /* Get the SYSCLK configuration --------------------------------------------*/\r
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r
+\r
+ /* Get the SYSCLK configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);\r
+\r
+ /* Get the D1HCLK configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);\r
+\r
+ /* Get the APB3 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);\r
+\r
+ /* Get the APB1 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);\r
+\r
+ /* Get the APB2 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);\r
+\r
+ /* Get the APB4 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);\r
+\r
+\r
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/\r
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);\r
+}\r
+\r
+/**\r
+ * @brief This function handles the RCC CSS interrupt request.\r
+ * @note This API should be called under the NMI_Handler().\r
+ * @retval None\r
+ */\r
+void HAL_RCC_NMI_IRQHandler(void)\r
+{\r
+ /* Check RCC CSSF flag */\r
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
+ {\r
+ /* RCC Clock Security System interrupt user callback */\r
+ HAL_RCC_CCSCallback();\r
+\r
+ /* Clear RCC CSS pending bit */\r
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RCC Clock Security System interrupt callback\r
+ * @retval none\r
+ */\r
+__weak void HAL_RCC_CCSCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RCC_CCSCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_rcc_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities RCC extension peripheral:\r
+ * + Extended Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx RCCEx\r
+ * @brief RCC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_defines Private Defines\r
+ * @{\r
+ */\r
+#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */\r
+#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */\r
+\r
+#define DIVIDER_P_UPDATE 0U\r
+#define DIVIDER_Q_UPDATE 1U\r
+#define DIVIDER_R_UPDATE 2U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);\r
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Functions Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions\r
+ * @brief Extended Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks\r
+ frequencies.\r
+ [..]\r
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
+ select the RTC clock source; in this case the Backup domain will be reset in\r
+ order to modify the RTC Clock source, as consequence RTC registers (including\r
+ the backup registers) and RCC_BDCR register are set to their reset values.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the RCC extended peripherals clocks according to the specified\r
+ * parameters in the RCC_PeriphCLKInitTypeDef.\r
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+ * contains the configuration information for the Extended Peripherals\r
+ * clocks(SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,\r
+ * USART234578, USART16, RNG, HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,\r
+ * SAI4A,SAI4B,SPI6,RTC).\r
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\r
+ * the RTC clock source; in this case the Backup domain will be reset in\r
+ * order to modify the RTC Clock source, as consequence RTC registers (including\r
+ * the backup registers) are set to their reset values.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tmpreg;\r
+ uint32_t tickstart;\r
+ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */\r
+ HAL_StatusTypeDef status = HAL_OK; /* Final status */\r
+\r
+ /*---------------------------- SPDIFRX configuration -------------------------------*/\r
+\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r
+ {\r
+\r
+ switch(PeriphClkInit->SpdifrxClockSelection)\r
+ {\r
+ case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/\r
+ /* Enable SAI Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPDIFRXCLKSOURCE_HSI:\r
+ /* Internal OSC clock is used as source of SPDIFRX clock*/\r
+ /* SPDIFRX clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SPDIFRX clock*/\r
+ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- SAI1 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)\r
+ {\r
+ switch(PeriphClkInit->Sai1ClockSelection)\r
+ {\r
+ case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/\r
+ /* Enable SAI Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI1CLKSOURCE_PIN:\r
+ /* External clock is used as source of SAI1 clock*/\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI1CLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SAI1 clock*/\r
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- SAI2/3 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)\r
+ {\r
+ switch(PeriphClkInit->Sai23ClockSelection)\r
+ {\r
+ case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */\r
+ /* Enable SAI Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* SAI2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* SAI2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);\r
+\r
+ /* SAI2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI23CLKSOURCE_PIN:\r
+ /* External clock is used as source of SAI2/3 clock*/\r
+ /* SAI2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI23CLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */\r
+ /* SAI2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SAI2/3 clock*/\r
+ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- SAI4A configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)\r
+ {\r
+ switch(PeriphClkInit->Sai4AClockSelection)\r
+ {\r
+ case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/\r
+ /* Enable SAI Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* SAI2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4ACLKSOURCE_PIN:\r
+ /* External clock is used as source of SAI2 clock*/\r
+ /* SAI2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4ACLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SAI2 clock*/\r
+ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+ /*---------------------------- SAI4B configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)\r
+ {\r
+ switch(PeriphClkInit->Sai4BClockSelection)\r
+ {\r
+ case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/\r
+ /* Enable SAI Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* SAI2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);\r
+\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4BCLKSOURCE_PIN:\r
+ /* External clock is used as source of SAI2 clock*/\r
+ /* SAI2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SAI4BCLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */\r
+ /* SAI1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SAI2 clock*/\r
+ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+ /*---------------------------- QSPI configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)\r
+ {\r
+ switch(PeriphClkInit->QspiClockSelection)\r
+ {\r
+ case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/\r
+ /* Enable QSPI Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* QSPI clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);\r
+\r
+ /* QSPI clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+\r
+ case RCC_QSPICLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */\r
+ /* QSPI clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_QSPICLKSOURCE_D1HCLK:\r
+ /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of QSPI clock*/\r
+ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- SPI1/2/3 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)\r
+ {\r
+ switch(PeriphClkInit->Spi123ClockSelection)\r
+ {\r
+ case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */\r
+ /* Enable SPI Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* SPI1/2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* SPI1/2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);\r
+\r
+ /* SPI1/2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI123CLKSOURCE_PIN:\r
+ /* External clock is used as source of SPI1/2/3 clock*/\r
+ /* SPI1/2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI123CLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */\r
+ /* SPI1/2/3 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SPI1/2/3 clock*/\r
+ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- SPI4/5 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)\r
+ {\r
+ switch(PeriphClkInit->Spi45ClockSelection)\r
+ {\r
+ case RCC_SPI45CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for SPI4/5 */\r
+ /* SPI4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);\r
+\r
+ /* SPI4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+ case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);\r
+ /* SPI4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI45CLKSOURCE_HSI:\r
+ /* HSI oscillator clock is used as source of SPI4/5 clock*/\r
+ /* SPI4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI45CLKSOURCE_CSI:\r
+ /* CSI oscillator clock is used as source of SPI4/5 clock */\r
+ /* SPI4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI45CLKSOURCE_HSE:\r
+ /* HSE, oscillator is used as source of SPI4/5 clock */\r
+ /* SPI4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SPI4/5 clock*/\r
+ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- SPI6 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)\r
+ {\r
+ switch(PeriphClkInit->Spi6ClockSelection)\r
+ {\r
+ case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for SPI6*/\r
+ /* SPI6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);\r
+\r
+ /* SPI6 clock source configuration done later after clock selection check */\r
+ break;\r
+ case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);\r
+ /* SPI6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI6CLKSOURCE_HSI:\r
+ /* HSI oscillator clock is used as source of SPI6 clock*/\r
+ /* SPI6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI6CLKSOURCE_CSI:\r
+ /* CSI oscillator clock is used as source of SPI6 clock */\r
+ /* SPI6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SPI6CLKSOURCE_HSE:\r
+ /* HSE, oscillator is used as source of SPI6 clock */\r
+ /* SPI6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SPI6 clock*/\r
+ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+#if defined(DSI)\r
+ /*---------------------------- DSI configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)\r
+ {\r
+ switch(PeriphClkInit->DsiClockSelection)\r
+ {\r
+\r
+ case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);\r
+\r
+ /* DSI clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_DSICLKSOURCE_PHY:\r
+ /* PHY is used as clock source for DSI*/\r
+ /* DSI clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of DSI clock*/\r
+ __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+#endif /*DSI*/\r
+\r
+#if defined(FDCAN1) || defined(FDCAN2)\r
+ /*---------------------------- FDCAN configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)\r
+ {\r
+ switch(PeriphClkInit->FdcanClockSelection)\r
+ {\r
+ case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/\r
+ /* Enable FDCAN Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* FDCAN clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);\r
+\r
+ /* FDCAN clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_FDCANCLKSOURCE_HSE:\r
+ /* HSE is used as clock source for FDCAN*/\r
+ /* FDCAN clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of FDCAN clock*/\r
+ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+#endif /*FDCAN1 || FDCAN2*/\r
+ /*---------------------------- FMC configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)\r
+ {\r
+ switch(PeriphClkInit->FmcClockSelection)\r
+ {\r
+ case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/\r
+ /* Enable FMC Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* FMC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);\r
+\r
+ /* FMC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+\r
+ case RCC_FMCCLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of FMC clock */\r
+ /* FMC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_FMCCLKSOURCE_D1HCLK:\r
+ /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of FMC clock*/\r
+ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- RTC configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)\r
+ {\r
+ /* check for RTC Parameters used to output RTCCLK */\r
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
+\r
+ /* Enable write access to Backup domain */\r
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+\r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((PWR->CR1 & PWR_CR1_DBP) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ ret = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */\r
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))\r
+ {\r
+ /* Store the content of BDCR register before the reset of Backup Domain */\r
+ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
+ __HAL_RCC_BACKUPRESET_FORCE();\r
+ __HAL_RCC_BACKUPRESET_RELEASE();\r
+ /* Restore the Content of BDCR register */\r
+ RCC->BDCR = tmpreg;\r
+ }\r
+\r
+ /* If LSE is selected as RTC clock source, wait for LSE reactivation */\r
+ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ ret = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+\r
+ /*-------------------------- USART1/6 configuration --------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)\r
+ {\r
+ switch(PeriphClkInit->Usart16ClockSelection)\r
+ {\r
+ case RCC_USART16CLKSOURCE_D2PCLK2: /* D2PCLK2 as clock source for USART1/6 */\r
+ /* USART1/6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);\r
+ /* USART1/6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);\r
+ /* USART1/6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART16CLKSOURCE_HSI:\r
+ /* HSI oscillator clock is used as source of USART1/6 clock */\r
+ /* USART1/6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART16CLKSOURCE_CSI:\r
+ /* CSI oscillator clock is used as source of USART1/6 clock */\r
+ /* USART1/6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART16CLKSOURCE_LSE:\r
+ /* LSE, oscillator is used as source of USART1/6 clock */\r
+ /* USART1/6 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of USART1/6 clock */\r
+ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)\r
+ {\r
+ switch(PeriphClkInit->Usart234578ClockSelection)\r
+ {\r
+ case RCC_USART234578CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for USART2/3/4/5/7/8 */\r
+ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);\r
+ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);\r
+ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART234578CLKSOURCE_HSI:\r
+ /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */\r
+ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART234578CLKSOURCE_CSI:\r
+ /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */\r
+ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USART234578CLKSOURCE_LSE:\r
+ /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */\r
+ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of USART2/3/4/5/7/8 clock */\r
+ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- LPUART1 Configuration -------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)\r
+ {\r
+ switch(PeriphClkInit->Lpuart1ClockSelection)\r
+ {\r
+ case RCC_LPUART1CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPUART1 */\r
+ /* LPUART1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);\r
+ /* LPUART1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);\r
+ /* LPUART1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPUART1CLKSOURCE_HSI:\r
+ /* HSI oscillator clock is used as source of LPUART1 clock */\r
+ /* LPUART1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPUART1CLKSOURCE_CSI:\r
+ /* CSI oscillator clock is used as source of LPUART1 clock */\r
+ /* LPUART1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPUART1CLKSOURCE_LSE:\r
+ /* LSE, oscillator is used as source of LPUART1 clock */\r
+ /* LPUART1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of LPUART1 clock */\r
+ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- LPTIM1 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r
+ {\r
+ switch(PeriphClkInit->Lptim1ClockSelection)\r
+ {\r
+ case RCC_LPTIM1CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for LPTIM1*/\r
+ /* LPTIM1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* LPTIM1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);\r
+\r
+ /* LPTIM1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM1CLKSOURCE_LSE:\r
+ /* External low speed OSC clock is used as source of LPTIM1 clock*/\r
+ /* LPTIM1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM1CLKSOURCE_LSI:\r
+ /* Internal low speed OSC clock is used as source of LPTIM1 clock*/\r
+ /* LPTIM1 clock source configuration done later after clock selection check */\r
+ break;\r
+ case RCC_LPTIM1CLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */\r
+ /* LPTIM1 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of LPTIM1 clock*/\r
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- LPTIM2 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)\r
+ {\r
+ switch(PeriphClkInit->Lptim2ClockSelection)\r
+ {\r
+ case RCC_LPTIM2CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM2*/\r
+ /* LPTIM2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* LPTIM2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);\r
+\r
+ /* LPTIM2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM2CLKSOURCE_LSE:\r
+ /* External low speed OSC clock is used as source of LPTIM2 clock*/\r
+ /* LPTIM2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM2CLKSOURCE_LSI:\r
+ /* Internal low speed OSC clock is used as source of LPTIM2 clock*/\r
+ /* LPTIM2 clock source configuration done later after clock selection check */\r
+ break;\r
+ case RCC_LPTIM2CLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */\r
+ /* LPTIM2 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of LPTIM2 clock*/\r
+ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- LPTIM345 configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)\r
+ {\r
+ switch(PeriphClkInit->Lptim345ClockSelection)\r
+ {\r
+\r
+ case RCC_LPTIM345CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM3/4/5 */\r
+ /* LPTIM3/4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* LPTIM3/4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);\r
+\r
+ /* LPTIM3/4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM345CLKSOURCE_LSE:\r
+ /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */\r
+ /* LPTIM3/4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_LPTIM345CLKSOURCE_LSI:\r
+ /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */\r
+ /* LPTIM3/4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+ case RCC_LPTIM345CLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */\r
+ /* LPTIM3/4/5 clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of LPTIM3/4/5 clock */\r
+ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*------------------------------ I2C1/2/3 Configuration ------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));\r
+\r
+ if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )\r
+ {\r
+ if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ else\r
+ {\r
+ __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);\r
+ }\r
+\r
+ }\r
+\r
+ /*------------------------------ I2C4 Configuration ------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r
+\r
+ if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )\r
+ {\r
+ if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ else\r
+ {\r
+ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r
+ }\r
+ }\r
+\r
+ /*---------------------------- ADC configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)\r
+ {\r
+ switch(PeriphClkInit->AdcClockSelection)\r
+ {\r
+\r
+ case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);\r
+\r
+ /* ADC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);\r
+\r
+ /* ADC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_ADCCLKSOURCE_CLKP:\r
+ /* HSI, HSE, or CSI oscillator is used as source of ADC clock */\r
+ /* ADC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of ADC clock*/\r
+ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+ /*------------------------------ USB Configuration -------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)\r
+ {\r
+\r
+ switch(PeriphClkInit->UsbClockSelection)\r
+ {\r
+ case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/\r
+ /* Enable USB Clock output generated form System USB . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* USB clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/\r
+\r
+ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);\r
+\r
+ /* USB clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_USBCLKSOURCE_HSI48:\r
+ /* HSI48 oscillator is used as source of USB clock */\r
+ /* USB clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of USB clock*/\r
+ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+\r
+ }\r
+\r
+ /*------------------------------------- SDMMC Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));\r
+\r
+ switch(PeriphClkInit->SdmmcClockSelection)\r
+ {\r
+ case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/\r
+ /* Enable SDMMC Clock output generated form System PLL . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* SDMMC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/\r
+\r
+ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);\r
+\r
+ /* SDMMC clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of SDMMC clock*/\r
+ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+ }\r
+\r
+#if defined(LTDC)\r
+ /*-------------------------------------- LTDC Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r
+ {\r
+ if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)\r
+ {\r
+ status=HAL_ERROR;\r
+ }\r
+ }\r
+#endif /* LTDC */\r
+\r
+ /*------------------------------ RNG Configuration -------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)\r
+ {\r
+\r
+ switch(PeriphClkInit->RngClockSelection)\r
+ {\r
+ case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/\r
+ /* Enable RNG Clock output generated form System RNG . */\r
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);\r
+\r
+ /* RNG clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/\r
+\r
+ /* RNG clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/\r
+\r
+ /* RNG clock source configuration done later after clock selection check */\r
+ break;\r
+ case RCC_RNGCLKSOURCE_HSI48:\r
+ /* HSI48 oscillator is used as source of RNG clock */\r
+ /* RNG clock source configuration done later after clock selection check */\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(ret == HAL_OK)\r
+ {\r
+ /* Set the source of RNG clock*/\r
+ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);\r
+ }\r
+ else\r
+ {\r
+ /* set overall return value */\r
+ status = ret;\r
+ }\r
+\r
+ }\r
+\r
+ /*------------------------------ SWPMI1 Configuration ------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));\r
+\r
+ /* Configure the SWPMI1 interface clock source */\r
+ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);\r
+ }\r
+\r
+ /*------------------------------ HRTIM1 clock Configuration ----------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));\r
+\r
+ /* Configure the HRTIM1 clock source */\r
+ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);\r
+ }\r
+\r
+ /*------------------------------ DFSDM1 Configuration ------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\r
+\r
+ /* Configure the DFSDM1 interface clock source */\r
+ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\r
+ }\r
+\r
+ /*------------------------------------ TIM configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r
+\r
+ /* Configure Timer Prescaler */\r
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r
+ }\r
+\r
+ /*------------------------------------ CKPER configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));\r
+\r
+ /* Configure the CKPER clock source */\r
+ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);\r
+ }\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.\r
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+* returns the configuration information for the Extended Peripherals clocks :\r
+ * (SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,\r
+ * USART234578, USART16, RNG,HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,\r
+* SAI4A,SAI4B,SPI6,RTC,TIM).\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ /* Set all possible values for the extended clock type parameter------------*/\r
+ PeriphClkInit->PeriphClockSelection =\r
+ RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C123 |\r
+ RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 |\r
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI23 | RCC_PERIPHCLK_SAI4A | RCC_PERIPHCLK_SAI4B |\r
+ RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_FDCAN |\r
+ RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC |\r
+ RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CEC |\r
+ RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_SPDIFRX |\r
+ RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_CKPER;\r
+\r
+#if defined(LTDC)\r
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;\r
+#endif /* LTDC */\r
+\r
+ /* Get the PLL3 Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);\r
+ PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;\r
+ PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;\r
+ PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;\r
+ PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;\r
+ PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);\r
+ PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);\r
+\r
+ /* Get the PLL2 Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);\r
+ PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;\r
+ PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;\r
+ PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;\r
+ PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;\r
+ PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);\r
+ PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);\r
+\r
+ /* Get the USART1 configuration --------------------------------------------*/\r
+ PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE();\r
+ /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/\r
+ PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE();\r
+ /* Get the LPUART1 clock source --------------------------------------------*/\r
+ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();\r
+ /* Get the I2C1/2/3 clock source -------------------------------------------*/\r
+ PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r
+ /* Get the LPTIM1 clock source ---------------------------------------------*/\r
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r
+ /* Get the LPTIM2 clock source ---------------------------------------------*/\r
+ PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();\r
+ /* Get the LPTIM3/4/5 clock source -----------------------------------------*/\r
+ PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE();\r
+ /* Get the SAI1 clock source -----------------------------------------------*/\r
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r
+ /* Get the SAI2/3 clock source ---------------------------------------------*/\r
+ PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE();\r
+ /* Get the SAI4A clock source ----------------------------------------------*/\r
+ PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE();\r
+ /* Get the SAI4B clock source ----------------------------------------------*/\r
+ PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE();\r
+ /* Get the RTC clock source ------------------------------------------------*/\r
+ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();\r
+ /* Get the USB clock source ------------------------------------------------*/\r
+ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();\r
+ /* Get the SDMMC clock source ----------------------------------------------*/\r
+ PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();\r
+ /* Get the RNG clock source ------------------------------------------------*/\r
+ PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();\r
+ /* Get the HRTIM1 clock source ---------------------------------------------*/\r
+ PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();\r
+ /* Get the ADC clock source ------------------------------------------------*/\r
+ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();\r
+ /* Get the SWPMI1 clock source ---------------------------------------------*/\r
+ PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();\r
+ /* Get the DFSDM1 clock source ---------------------------------------------*/\r
+ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();\r
+ /* Get the SPDIFRX clock source --------------------------------------------*/\r
+ PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();\r
+ /* Get the SPI1/2/3 clock source -------------------------------------------*/\r
+ PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE();\r
+ /* Get the SPI4/5 clock source ---------------------------------------------*/\r
+ PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();\r
+ /* Get the SPI6 clock source -----------------------------------------------*/\r
+ PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();\r
+ /* Get the FDCAN clock source ----------------------------------------------*/\r
+ PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();\r
+ /* Get the CEC clock source ------------------------------------------------*/\r
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();\r
+ /* Get the FMC clock source ------------------------------------------------*/\r
+ PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();\r
+ /* Get the QSPI clock source -----------------------------------------------*/\r
+ PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();\r
+\r
+#if defined(DSI)\r
+ /* Get the DSI clock source ------------------------------------------------*/\r
+ PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();\r
+#endif /*DSI*/\r
+\r
+ /* Get the CKPER clock source ----------------------------------------------*/\r
+ PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();\r
+\r
+ /* Get the TIM Prescaler configuration -------------------------------------*/\r
+ if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r
+ }\r
+ else\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)\r
+ * @note Return 0 if peripheral clock identifier not managed by this API\r
+ * @param PeriphClk: Peripheral clock identifier\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock\r
+ * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock\r
+ * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock\r
+ * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock\r
+ * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock\r
+ * @retval Frequency in KHz\r
+ */\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
+{\r
+ PLL1_ClocksTypeDef pll1_clocks;\r
+ PLL2_ClocksTypeDef pll2_clocks;\r
+ PLL3_ClocksTypeDef pll3_clocks;\r
+\r
+ /* This variable is used to store the SAI clock frequency (value in Hz) */\r
+ uint32_t frequency;\r
+ /* This variable is used to store the SAI and CKP clock source */\r
+ uint32_t saiclocksource;\r
+ uint32_t ckpclocksource;\r
+ uint32_t srcclk;\r
+\r
+ if (PeriphClk == RCC_PERIPHCLK_SAI1)\r
+ {\r
+\r
+ saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();\r
+\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLL1 is the clock source for SAI1 */\r
+ {\r
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);\r
+ frequency = pll1_clocks.PLL1_Q_Frequency;\r
+ break;\r
+ }\r
+ case RCC_D2CCIP1R_SAI1SEL_0: /* PLLI2 is the clock source for SAI1 */\r
+ {\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ frequency = pll2_clocks.PLL2_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D2CCIP1R_SAI1SEL_1: /* PLLI3 is the clock source for SAI1 */\r
+ {\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ frequency = pll3_clocks.PLL3_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D2CCIP1R_SAI1SEL_2: /* CKPER is the clock source for SAI1*/\r
+ {\r
+\r
+ ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();\r
+\r
+ if(ckpclocksource== 0U)\r
+ {\r
+ /* In Case the CKPER Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+\r
+ else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)\r
+ {\r
+ /* In Case the CKPER Source is CSI */\r
+ frequency = CSI_VALUE;\r
+ }\r
+\r
+ else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)\r
+ {\r
+ /* In Case the CKPER Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+\r
+ else\r
+ {\r
+ /* In Case the CKPER is disabled*/\r
+ frequency = 0;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ case (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1 ): /* External clock is the clock source for SAI1 */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+ default :\r
+ {\r
+ frequency = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ else if (PeriphClk == RCC_PERIPHCLK_SAI23)\r
+ {\r
+\r
+ saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();\r
+\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLL1 is the clock source for SAI2/3 */\r
+ {\r
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);\r
+ frequency = pll1_clocks.PLL1_Q_Frequency;\r
+ break;\r
+ }\r
+ case RCC_D2CCIP1R_SAI23SEL_0: /* PLLI2 is the clock source for SAI2/3 */\r
+ {\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ frequency = pll2_clocks.PLL2_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D2CCIP1R_SAI23SEL_1: /* PLLI3 is the clock source for SAI2/3 */\r
+ {\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ frequency = pll3_clocks.PLL3_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D2CCIP1R_SAI23SEL_2: /* CKPER is the clock source for SAI2/3 */\r
+ {\r
+\r
+ ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();\r
+\r
+ if(ckpclocksource== 0U)\r
+ {\r
+ /* In Case the CKPER Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+\r
+ else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)\r
+ {\r
+ /* In Case the CKPER Source is CSI */\r
+ frequency = CSI_VALUE;\r
+ }\r
+\r
+ else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)\r
+ {\r
+ /* In Case the CKPER Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+\r
+ else\r
+ {\r
+ /* In Case the CKPER is disabled*/\r
+ frequency = 0;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ case (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1 ): /* External clock is the clock source for SAI2/3 */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+ default :\r
+ {\r
+ frequency = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ else if (PeriphClk == RCC_PERIPHCLK_SAI4A)\r
+ {\r
+\r
+ saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();\r
+\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLL1 is the clock source for SAI4A */\r
+ {\r
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);\r
+ frequency = pll1_clocks.PLL1_Q_Frequency;\r
+ break;\r
+ }\r
+ case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */\r
+ {\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ frequency = pll2_clocks.PLL2_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */\r
+ {\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ frequency = pll3_clocks.PLL3_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/\r
+ {\r
+\r
+ ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();\r
+\r
+ if(ckpclocksource== 0U)\r
+ {\r
+ /* In Case the CKPER Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+\r
+ else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)\r
+ {\r
+ /* In Case the CKPER Source is CSI */\r
+ frequency = CSI_VALUE;\r
+ }\r
+\r
+ else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)\r
+ {\r
+ /* In Case the CKPER Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+\r
+ else\r
+ {\r
+ /* In Case the CKPER is disabled*/\r
+ frequency = 0;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ frequency = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ else if (PeriphClk == RCC_PERIPHCLK_SAI4B)\r
+ {\r
+\r
+ saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();\r
+\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLL1 is the clock source for SAI4B */\r
+ {\r
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);\r
+ frequency = pll1_clocks.PLL1_Q_Frequency;\r
+ break;\r
+ }\r
+ case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */\r
+ {\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ frequency = pll2_clocks.PLL2_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */\r
+ {\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ frequency = pll3_clocks.PLL3_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/\r
+ {\r
+\r
+ ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();\r
+\r
+ if(ckpclocksource== 0U)\r
+ {\r
+ /* In Case the CKPER Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+\r
+ else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)\r
+ {\r
+ /* In Case the CKPER Source is CSI */\r
+ frequency = CSI_VALUE;\r
+ }\r
+\r
+ else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)\r
+ {\r
+ /* In Case the CKPER Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+\r
+ else\r
+ {\r
+ /* In Case the CKPER is disabled*/\r
+ frequency = 0;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ frequency = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ else if (PeriphClk == RCC_PERIPHCLK_SPI123)\r
+ {\r
+ /* Get SPI1/2/3 clock source */\r
+ srcclk= __HAL_RCC_GET_SPI123_SOURCE();\r
+\r
+ switch (srcclk)\r
+ {\r
+ case 0: /* PLL1 is the clock source for I2S */\r
+ {\r
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);\r
+ frequency = pll1_clocks.PLL1_Q_Frequency;\r
+ break;\r
+ }\r
+ case RCC_D2CCIP1R_SPI123SEL_0: /* PLL2 is the clock source for I2S */\r
+ {\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ frequency = pll2_clocks.PLL2_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D2CCIP1R_SPI123SEL_1: /* PLL3 is the clock source for I2S */\r
+ {\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ frequency = pll3_clocks.PLL3_P_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_D2CCIP1R_SPI123SEL_2: /* CKPER is the clock source for I2S */\r
+ {\r
+\r
+ ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();\r
+\r
+ if(ckpclocksource== RCC_CLKPSOURCE_HSI)\r
+ {\r
+ /* In Case the CKPER Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+\r
+ else if(ckpclocksource== RCC_CLKPSOURCE_CSI)\r
+ {\r
+ /* In Case the CKPER Source is CSI */\r
+ frequency = CSI_VALUE;\r
+ }\r
+\r
+ else if (ckpclocksource== RCC_CLKPSOURCE_HSE)\r
+ {\r
+ /* In Case the CKPER Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+\r
+ else\r
+ {\r
+ /* In Case the CKPER is disabled*/\r
+ frequency = 0;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ case (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1): /* External clock is the clock source for I2S */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+ default :\r
+ {\r
+ frequency = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else if (PeriphClk == RCC_PERIPHCLK_ADC)\r
+ {\r
+ /* Get ADC clock source */\r
+ srcclk= __HAL_RCC_GET_ADC_SOURCE();\r
+\r
+ switch (srcclk)\r
+ {\r
+ case RCC_ADCCLKSOURCE_PLL2:\r
+ {\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ frequency = pll2_clocks.PLL2_P_Frequency;\r
+ break;\r
+ }\r
+ case RCC_ADCCLKSOURCE_PLL3:\r
+ {\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ frequency = pll3_clocks.PLL3_R_Frequency;\r
+ break;\r
+ }\r
+\r
+ case RCC_ADCCLKSOURCE_CLKP:\r
+ {\r
+\r
+ ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();\r
+\r
+ if(ckpclocksource== RCC_CLKPSOURCE_HSI)\r
+ {\r
+ /* In Case the CKPER Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+\r
+ else if(ckpclocksource== RCC_CLKPSOURCE_CSI)\r
+ {\r
+ /* In Case the CKPER Source is CSI */\r
+ frequency = CSI_VALUE;\r
+ }\r
+\r
+ else if (ckpclocksource== RCC_CLKPSOURCE_HSE)\r
+ {\r
+ /* In Case the CKPER Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+\r
+ else\r
+ {\r
+ /* In Case the CKPER is disabled*/\r
+ frequency = 0;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ frequency = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ frequency = 0;\r
+ }\r
+\r
+ return frequency;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Returns the D1PCLK1 frequency\r
+ * @note Each time D1PCLK1 changes, this function must be called to update the\r
+ * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval D1PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)\r
+{\r
+ /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));\r
+}\r
+\r
+/**\r
+ * @brief Returns the D3PCLK1 frequency\r
+ * @note Each time D3PCLK1 changes, this function must be called to update the\r
+ * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval D3PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)\r
+{\r
+ /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));\r
+}\r
+/**\r
+* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency\r
+ * @note The PLL2 clock frequencies computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.\r
+ * @note This function can be used by the user application to compute the\r
+ * baud-rate for the communication peripherals or configure other parameters.\r
+ *\r
+ * @note Each time PLL2CLK changes, this function must be called to update the\r
+ * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @param PLL2_Clocks structure.\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)\r
+{\r
+ uint32_t pllsource, pll2m, pll2fracen, hsivalue;\r
+ float_t fracn2, pll2vco;\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N\r
+ PLL2xCLK = PLL2_VCO / PLL2x\r
+ */\r
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);\r
+ pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12) ;\r
+ pll2fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN;\r
+ fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));\r
+\r
+ if (pll2m != 0U)\r
+ {\r
+ switch (pllsource)\r
+ {\r
+\r
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */\r
+\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));\r
+ pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ else\r
+ {\r
+ pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ break;\r
+\r
+ case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */\r
+ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */\r
+ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ default:\r
+ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+ }\r
+ PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + (float_t)1 )) ;\r
+ PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;\r
+ PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;\r
+ }\r
+ else\r
+ {\r
+ PLL2_Clocks->PLL2_P_Frequency = 0U;\r
+ PLL2_Clocks->PLL2_Q_Frequency = 0U;\r
+ PLL2_Clocks->PLL2_R_Frequency = 0U;\r
+ }\r
+}\r
+\r
+/**\r
+* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency\r
+ * @note The PLL3 clock frequencies computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.\r
+ * @note This function can be used by the user application to compute the\r
+ * baud-rate for the communication peripherals or configure other parameters.\r
+ *\r
+ * @note Each time PLL3CLK changes, this function must be called to update the\r
+ * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @param PLL3_Clocks structure.\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)\r
+{\r
+ uint32_t pllsource, pll3m, pll3fracen, hsivalue;\r
+ float_t fracn3, pll3vco;\r
+\r
+ /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N\r
+ PLL3xCLK = PLL3_VCO / PLLxR\r
+ */\r
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);\r
+ pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ;\r
+ pll3fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN;\r
+ fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));\r
+\r
+ if (pll3m != 0U)\r
+ {\r
+ switch (pllsource)\r
+ {\r
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */\r
+\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));\r
+ pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ else\r
+ {\r
+ pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ break;\r
+ case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */\r
+ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */\r
+ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ default:\r
+ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+ }\r
+ PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + (float_t)1 )) ;\r
+ PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;\r
+ PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;\r
+ }\r
+ else\r
+ {\r
+ PLL3_Clocks->PLL3_P_Frequency = 0U;\r
+ PLL3_Clocks->PLL3_Q_Frequency = 0U;\r
+ PLL3_Clocks->PLL3_R_Frequency = 0U;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency\r
+ * @note The PLL1 clock frequencies computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.\r
+ * @note This function can be used by the user application to compute the\r
+ * baud-rate for the communication peripherals or configure other parameters.\r
+ *\r
+ * @note Each time PLL1CLK changes, this function must be called to update the\r
+ * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @param PLL1_Clocks structure.\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)\r
+{\r
+ uint32_t pllsource, pll1m, pll1fracen, hsivalue;\r
+ float_t fracn1, pll1vco;\r
+\r
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);\r
+ pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);\r
+ pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;\r
+ fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));\r
+\r
+ if (pll1m != 0U)\r
+ {\r
+ switch (pllsource)\r
+ {\r
+\r
+ case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */\r
+\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));\r
+ pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ else\r
+ {\r
+ pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ }\r
+ break;\r
+ case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */\r
+ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */\r
+ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+\r
+ default:\r
+ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+ }\r
+\r
+ PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + (float_t)1 )) ;\r
+ PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;\r
+ PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;\r
+ }\r
+ else\r
+ {\r
+ PLL1_Clocks->PLL1_P_Frequency = 0U;\r
+ PLL1_Clocks->PLL1_Q_Frequency = 0U;\r
+ PLL1_Clocks->PLL1_R_Frequency = 0U;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Returns the main Core frequency\r
+ * @note Each time core clock changes, this function must be called to update the\r
+ * right system core clock value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
+ * and updated within this function\r
+ * @retval HCLK frequency\r
+ */\r
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void)\r
+{\r
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);\r
+ return SystemCoreClock;\r
+}\r
+\r
+/**\r
+ * @brief Enables the LSE Clock Security System.\r
+ * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled\r
+ * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC\r
+ * clock with HAL_RCCEx_PeriphCLKConfig().\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_EnableLSECSS(void)\r
+{\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
+}\r
+\r
+/**\r
+ * @brief Disables the LSE Clock Security System.\r
+ * @note LSE Clock Security System can only be disabled after a LSE failure detection.\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_DisableLSECSS(void)\r
+{\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;\r
+ /* Disable LSE CSS IT if any */\r
+ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);\r
+}\r
+\r
+/**\r
+ * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock\r
+ * @param WakeUpClk: Wakeup clock\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection\r
+ * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection\r
+ * @note This function shall not be called after the Clock Security System on HSE has been\r
+ * enabled.\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)\r
+{\r
+ assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));\r
+\r
+ __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);\r
+}\r
+\r
+/**\r
+ * @brief Configure the oscillator Kernel clock source for wakeup from Stop\r
+ * @param WakeUpClk: Kernel Wakeup clock\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection\r
+ * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)\r
+{\r
+ assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));\r
+\r
+ __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);\r
+}\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Enable COREx boot independently of CMx_B option byte value\r
+ * @param RCC_BootCx: Boot Core to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_BOOT_C1: CM7 core selection\r
+ * @arg RCC_BOOT_C2: CM4 core selection\r
+ * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY\r
+ *\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)\r
+{\r
+ assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));\r
+ SET_BIT(RCC->GCR, RCC_BootCx) ;\r
+}\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+#if defined(DUAL_CORE)\r
+/**\r
+ * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs\r
+ * @param RCC_WWDGx: WWDGx to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_WWDG1: WWDG1 generates system reset\r
+ * @arg RCC_WWDG2: WWDG2 generates system reset\r
+ * @note This bit can be set by software but is cleared by hardware during a system reset\r
+ *\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)\r
+{\r
+ assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));\r
+ SET_BIT(RCC->GCR, RCC_WWDGx) ;\r
+}\r
+\r
+#else\r
+\r
+/**\r
+ * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs\r
+ * @param RCC_WWDGx: WWDGx to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_WWDG1: WWDG1 generates system reset\r
+ * @note This bit can be set by software but is cleared by hardware during a system reset\r
+ *\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)\r
+{\r
+ assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));\r
+ SET_BIT(RCC->GCR, RCC_WWDGx) ;\r
+}\r
+\r
+#endif /*DUAL_CORE*/\r
+\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions\r
+ * @brief Extended Clock Recovery System Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended Clock Recovery System Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:\r
+\r
+ (#) In System clock config, HSI48 needs to be enabled\r
+\r
+ (#) Enable CRS clock in IP MSP init which will use CRS functions\r
+\r
+ (#) Call CRS functions as follows:\r
+ (##) Prepare synchronization configuration necessary for HSI48 calibration\r
+ (+++) Default values can be set for frequency Error Measurement (reload and error limit)\r
+ and also HSI48 oscillator smooth trimming.\r
+ (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate\r
+ directly reload value with target and synchronization frequencies values\r
+ (##) Call function HAL_RCCEx_CRSConfig which\r
+ (+++) Resets CRS registers to their default values.\r
+ (+++) Configures CRS registers with synchronization configuration\r
+ (+++) Enables automatic calibration and frequency error counter feature\r
+ Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the\r
+ periodic USB SOF will not be generated by the host. No SYNC signal will therefore be\r
+ provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock\r
+ precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs\r
+ should be used as SYNC signal.\r
+\r
+ (##) A polling function is provided to wait for complete synchronization\r
+ (+++) Call function HAL_RCCEx_CRSWaitSynchronization()\r
+ (+++) According to CRS status, user can decide to adjust again the calibration or continue\r
+ application if synchronization is OK\r
+\r
+ (#) User can retrieve information related to synchronization in calling function\r
+ HAL_RCCEx_CRSGetSynchronizationInfo()\r
+\r
+ (#) Regarding synchronization status and synchronization information, user can try a new calibration\r
+ in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.\r
+ Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),\r
+ it means that the actual frequency is lower than the target (and so, that the TRIM value should be\r
+ incremented), while when it is detected during the up-counting phase it means that the actual frequency\r
+ is higher (and that the TRIM value should be decremented).\r
+\r
+ (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go\r
+ through CRS Handler (CRS_IRQn/CRS_IRQHandler)\r
+ (++) Call function HAL_RCCEx_CRSConfig()\r
+ (++) Enable CRS_IRQn (thanks to NVIC functions)\r
+ (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)\r
+ (++) Implement CRS status management in the following user callbacks called from\r
+ HAL_RCCEx_CRS_IRQHandler():\r
+ (+++) HAL_RCCEx_CRS_SyncOkCallback()\r
+ (+++) HAL_RCCEx_CRS_SyncWarnCallback()\r
+ (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()\r
+ (+++) HAL_RCCEx_CRS_ErrorCallback()\r
+\r
+ (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().\r
+ This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start automatic synchronization for polling mode\r
+ * @param pInit Pointer on RCC_CRSInitTypeDef structure\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)\r
+{\r
+ uint32_t value;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));\r
+ assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));\r
+ assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));\r
+ assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));\r
+ assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));\r
+ assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));\r
+\r
+ /* CONFIGURATION */\r
+\r
+ /* Before configuration, reset CRS registers to their default values*/\r
+ __HAL_RCC_CRS_FORCE_RESET();\r
+ __HAL_RCC_CRS_RELEASE_RESET();\r
+\r
+ /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */\r
+ /* Set the SYNCSRC[1:0] bits according to Source value */\r
+ /* Set the SYNCSPOL bit according to Polarity value */\r
+ if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))\r
+ {\r
+ /* Use Rev.Y value of USB2 */\r
+ value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);\r
+ }\r
+ else\r
+ {\r
+ value = (pInit->Prescaler | pInit->Source | pInit->Polarity);\r
+ }\r
+ /* Set the RELOAD[15:0] bits according to ReloadValue value */\r
+ value |= pInit->ReloadValue;\r
+ /* Set the FELIM[7:0] bits according to ErrorLimitValue value */\r
+ value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);\r
+ WRITE_REG(CRS->CFGR, value);\r
+\r
+ /* Adjust HSI48 oscillator smooth trimming */\r
+ /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */\r
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));\r
+\r
+ /* START AUTOMATIC SYNCHRONIZATION*/\r
+\r
+ /* Enable Automatic trimming & Frequency error counter */\r
+ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);\r
+}\r
+\r
+/**\r
+ * @brief Generate the software synchronization event\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)\r
+{\r
+ SET_BIT(CRS->CR, CRS_CR_SWSYNC);\r
+}\r
+\r
+/**\r
+ * @brief Return synchronization info\r
+ * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(pSynchroInfo != (void *)NULL);\r
+\r
+ /* Get the reload value */\r
+ pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));\r
+\r
+ /* Get HSI48 oscillator smooth trimming */\r
+ pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);\r
+\r
+ /* Get Frequency error capture */\r
+ pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);\r
+\r
+ /* Get Frequency error direction */\r
+ pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));\r
+}\r
+\r
+/**\r
+* @brief Wait for CRS Synchronization status.\r
+* @param Timeout Duration of the time-out\r
+* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization\r
+* frequency.\r
+* @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.\r
+* @retval Combination of Synchronization status\r
+* This parameter can be a combination of the following values:\r
+* @arg @ref RCC_CRS_TIMEOUT\r
+* @arg @ref RCC_CRS_SYNCOK\r
+* @arg @ref RCC_CRS_SYNCWARN\r
+* @arg @ref RCC_CRS_SYNCERR\r
+* @arg @ref RCC_CRS_SYNCMISS\r
+* @arg @ref RCC_CRS_TRIMOVF\r
+*/\r
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)\r
+{\r
+ uint32_t crsstatus = RCC_CRS_NONE;\r
+ uint32_t tickstart;\r
+\r
+ /* Get time-out */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for CRS flag or time-out detection */\r
+ do\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ crsstatus = RCC_CRS_TIMEOUT;\r
+ }\r
+ }\r
+ /* Check CRS SYNCOK flag */\r
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))\r
+ {\r
+ /* CRS SYNC event OK */\r
+ crsstatus |= RCC_CRS_SYNCOK;\r
+\r
+ /* Clear CRS SYNC event OK bit */\r
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);\r
+ }\r
+\r
+ /* Check CRS SYNCWARN flag */\r
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))\r
+ {\r
+ /* CRS SYNC warning */\r
+ crsstatus |= RCC_CRS_SYNCWARN;\r
+\r
+ /* Clear CRS SYNCWARN bit */\r
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);\r
+ }\r
+\r
+ /* Check CRS TRIM overflow flag */\r
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))\r
+ {\r
+ /* CRS SYNC Error */\r
+ crsstatus |= RCC_CRS_TRIMOVF;\r
+\r
+ /* Clear CRS Error bit */\r
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);\r
+ }\r
+\r
+ /* Check CRS Error flag */\r
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))\r
+ {\r
+ /* CRS SYNC Error */\r
+ crsstatus |= RCC_CRS_SYNCERR;\r
+\r
+ /* Clear CRS Error bit */\r
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);\r
+ }\r
+\r
+ /* Check CRS SYNC Missed flag */\r
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))\r
+ {\r
+ /* CRS SYNC Missed */\r
+ crsstatus |= RCC_CRS_SYNCMISS;\r
+\r
+ /* Clear CRS SYNC Missed bit */\r
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);\r
+ }\r
+\r
+ /* Check CRS Expected SYNC flag */\r
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))\r
+ {\r
+ /* frequency error counter reached a zero value */\r
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);\r
+ }\r
+ } while(RCC_CRS_NONE == crsstatus);\r
+\r
+ return crsstatus;\r
+}\r
+\r
+/**\r
+ * @brief Handle the Clock Recovery System interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_CRS_IRQHandler(void)\r
+{\r
+ uint32_t crserror = RCC_CRS_NONE;\r
+ /* Get current IT flags and IT sources values */\r
+ uint32_t itflags = READ_REG(CRS->ISR);\r
+ uint32_t itsources = READ_REG(CRS->CR);\r
+\r
+ /* Check CRS SYNCOK flag */\r
+ if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))\r
+ {\r
+ /* Clear CRS SYNC event OK flag */\r
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);\r
+\r
+ /* user callback */\r
+ HAL_RCCEx_CRS_SyncOkCallback();\r
+ }\r
+ /* Check CRS SYNCWARN flag */\r
+ else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))\r
+ {\r
+ /* Clear CRS SYNCWARN flag */\r
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);\r
+\r
+ /* user callback */\r
+ HAL_RCCEx_CRS_SyncWarnCallback();\r
+ }\r
+ /* Check CRS Expected SYNC flag */\r
+ else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))\r
+ {\r
+ /* frequency error counter reached a zero value */\r
+ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);\r
+\r
+ /* user callback */\r
+ HAL_RCCEx_CRS_ExpectedSyncCallback();\r
+ }\r
+ /* Check CRS Error flags */\r
+ else\r
+ {\r
+ if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))\r
+ {\r
+ if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)\r
+ {\r
+ crserror |= RCC_CRS_SYNCERR;\r
+ }\r
+ if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)\r
+ {\r
+ crserror |= RCC_CRS_SYNCMISS;\r
+ }\r
+ if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)\r
+ {\r
+ crserror |= RCC_CRS_TRIMOVF;\r
+ }\r
+\r
+ /* Clear CRS Error flags */\r
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC);\r
+\r
+ /* user error callback */\r
+ HAL_RCCEx_CRS_ErrorCallback(crserror);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.\r
+ * @retval none\r
+ */\r
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.\r
+ * @retval none\r
+ */\r
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.\r
+ * @retval none\r
+ */\r
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief RCCEx Clock Recovery System Error interrupt callback.\r
+ * @param Error Combination of Error status.\r
+ * This parameter can be a combination of the following values:\r
+ * @arg @ref RCC_CRS_SYNCERR\r
+ * @arg @ref RCC_CRS_SYNCMISS\r
+ * @arg @ref RCC_CRS_TRIMOVF\r
+ * @retval none\r
+ */\r
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(Error);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Private_functions Private Functions\r
+ * @{\r
+ */\r
+\r
+\r
+\r
+/**\r
+ * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it\r
+ * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that\r
+ * contains the configuration parameters as well as VCI, VCO clock ranges.\r
+ * @param Divider divider parameter to be updated\r
+ * @note PLL2 is temporary disable to apply new parameters\r
+ *\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)\r
+{\r
+\r
+ uint32_t tickstart;\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));\r
+ assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));\r
+ assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));\r
+ assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));\r
+ assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));\r
+ assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));\r
+ assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));\r
+ assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));\r
+\r
+ /* Check that PLL2 OSC clock source is already set */\r
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+\r
+ else\r
+ {\r
+ /* Disable PLL2. */\r
+ __HAL_RCC_PLL2_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)\r
+ {\r
+ if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Configure PLL2 multiplication and division factors. */\r
+ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,\r
+ pll2->PLL2N,\r
+ pll2->PLL2P,\r
+ pll2->PLL2Q,\r
+ pll2->PLL2R);\r
+\r
+ /* Select PLL2 input reference frequency range: VCI */\r
+ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;\r
+\r
+ /* Select PLL2 output frequency range : VCO */\r
+ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;\r
+\r
+ /* Disable PLL2FRACN . */\r
+ __HAL_RCC_PLL2FRACN_DISABLE();\r
+\r
+ /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */\r
+ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);\r
+\r
+ /* Enable PLL2FRACN . */\r
+ __HAL_RCC_PLL2FRACN_ENABLE();\r
+\r
+ /* Enable the PLL2 clock output */\r
+ if(Divider == DIVIDER_P_UPDATE)\r
+ {\r
+ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);\r
+ }\r
+ else if(Divider == DIVIDER_Q_UPDATE)\r
+ {\r
+ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);\r
+ }\r
+ else\r
+ {\r
+ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);\r
+ }\r
+\r
+ /* Enable PLL2. */\r
+ __HAL_RCC_PLL2_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL2 is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)\r
+ {\r
+ if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it\r
+ * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that\r
+ * contains the configuration parameters as well as VCI, VCO clock ranges.\r
+ * @param Divider divider parameter to be updated\r
+ * @note PLL3 is temporary disable to apply new parameters\r
+ *\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)\r
+{\r
+ uint32_t tickstart;\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));\r
+ assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));\r
+ assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));\r
+ assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));\r
+ assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));\r
+ assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));\r
+ assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));\r
+ assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));\r
+\r
+ /* Check that PLL3 OSC clock source is already set */\r
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+\r
+ else\r
+ {\r
+ /* Disable PLL3. */\r
+ __HAL_RCC_PLL3_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ /* Wait till PLL3 is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)\r
+ {\r
+ if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Configure the PLL3 multiplication and division factors. */\r
+ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,\r
+ pll3->PLL3N,\r
+ pll3->PLL3P,\r
+ pll3->PLL3Q,\r
+ pll3->PLL3R);\r
+\r
+ /* Select PLL3 input reference frequency range: VCI */\r
+ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;\r
+\r
+ /* Select PLL3 output frequency range : VCO */\r
+ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;\r
+\r
+ /* Disable PLL3FRACN . */\r
+ __HAL_RCC_PLL3FRACN_DISABLE();\r
+\r
+ /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */\r
+ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);\r
+\r
+ /* Enable PLL3FRACN . */\r
+ __HAL_RCC_PLL3FRACN_ENABLE();\r
+\r
+ /* Enable the PLL3 clock output */\r
+ if(Divider == DIVIDER_P_UPDATE)\r
+ {\r
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);\r
+ }\r
+ else if(Divider == DIVIDER_Q_UPDATE)\r
+ {\r
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);\r
+ }\r
+ else\r
+ {\r
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);\r
+ }\r
+\r
+ /* Enable PLL3. */\r
+ __HAL_RCC_PLL3_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL3 is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)\r
+ {\r
+ if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+\r
+ return status;\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_tim.c\r
+ * @author MCD Application Team\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Timer (TIM) peripheral:\r
+ * + TIM Time Base Initialization\r
+ * + TIM Time Base Start\r
+ * + TIM Time Base Start Interruption\r
+ * + TIM Time Base Start DMA\r
+ * + TIM Output Compare/PWM Initialization\r
+ * + TIM Output Compare/PWM Channel Configuration\r
+ * + TIM Output Compare/PWM Start\r
+ * + TIM Output Compare/PWM Start Interruption\r
+ * + TIM Output Compare/PWM Start DMA\r
+ * + TIM Input Capture Initialization\r
+ * + TIM Input Capture Channel Configuration\r
+ * + TIM Input Capture Start\r
+ * + TIM Input Capture Start Interruption\r
+ * + TIM Input Capture Start DMA\r
+ * + TIM One Pulse Initialization\r
+ * + TIM One Pulse Channel Configuration\r
+ * + TIM One Pulse Start\r
+ * + TIM Encoder Interface Initialization\r
+ * + TIM Encoder Interface Start\r
+ * + TIM Encoder Interface Start Interruption\r
+ * + TIM Encoder Interface Start DMA\r
+ * + Commutation Event configuration with Interruption and DMA\r
+ * + TIM OCRef clear configuration\r
+ * + TIM External Clock configuration\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### TIMER Generic features #####\r
+ ==============================================================================\r
+ [..] The Timer features include:\r
+ (#) 16-bit up, down, up/down auto-reload counter.\r
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the\r
+ counter clock frequency either by any factor between 1 and 65536.\r
+ (#) Up to 4 independent channels for:\r
+ (++) Input Capture\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output\r
+ (#) Synchronization circuit to control the timer with external signals and to interconnect\r
+ several timers together.\r
+ (#) Supports incremental encoder for positioning purposes\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions\r
+ depending on the selected feature:\r
+ (++) Time Base : HAL_TIM_Base_MspInit()\r
+ (++) Input Capture : HAL_TIM_IC_MspInit()\r
+ (++) Output Compare : HAL_TIM_OC_MspInit()\r
+ (++) PWM generation : HAL_TIM_PWM_MspInit()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
+\r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE();\r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the\r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
+ any start function.\r
+\r
+ (#) Configure the TIM in the desired functioning mode using one of the\r
+ Initialization function of this driver:\r
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an\r
+ Output Compare signal.\r
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a\r
+ PWM signal.\r
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an\r
+ external signal.\r
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer\r
+ in One Pulse Mode.\r
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
+\r
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:\r
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
+\r
+ (#) The DMA Burst is managed with the two following functions:\r
+ HAL_TIM_DMABurst_WriteStart()\r
+ HAL_TIM_DMABurst_ReadStart()\r
+\r
+ *** Callback registration ***\r
+ =============================================\r
+\r
+ [..]\r
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1\r
+ allows the user to configure dynamically the driver callbacks.\r
+\r
+ [..]\r
+ Use Function @ref HAL_TIM_RegisterCallback() to register a callback.\r
+ @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,\r
+ the Callback ID and a pointer to the user callback function.\r
+\r
+ [..]\r
+ Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default\r
+ weak function.\r
+ @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
+ and the Callback ID.\r
+\r
+ [..]\r
+ These functions allow to register/unregister following callbacks:\r
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.\r
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.\r
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.\r
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.\r
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.\r
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.\r
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.\r
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.\r
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.\r
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.\r
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.\r
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.\r
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.\r
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.\r
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.\r
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.\r
+ (+) TriggerCallback : TIM Trigger Callback.\r
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.\r
+ (+) IC_CaptureCallback : TIM Input Capture Callback.\r
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.\r
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.\r
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.\r
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.\r
+ (+) ErrorCallback : TIM Error Callback.\r
+ (+) CommutationCallback : TIM Commutation Callback.\r
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.\r
+ (+) BreakCallback : TIM Break Callback.\r
+ (+) Break2Callback : TIM Break2 Callback.\r
+\r
+ [..]\r
+By default, after the Init and when the state is HAL_TIM_STATE_RESET\r
+all interrupt callbacks are set to the corresponding weak functions:\r
+ examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().\r
+\r
+ [..]\r
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\r
+ functionalities in the Init / DeInit only when these callbacks are null\r
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit\r
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)\r
+\r
+ [..]\r
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.\r
+ Exception done MspInit / MspDeInit that can be registered / unregistered\r
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,\r
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.\r
+ In that case first register the MspInit/MspDeInit user callbacks\r
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.\r
+\r
+ [..]\r
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or\r
+ not defined, the callback registration feature is not available and all callbacks\r
+ are set to the corresponding weak functions.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM TIM\r
+ * @brief TIM HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+ * @brief Time Base functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Time Base functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM base.\r
+ (+) De-initialize the TIM base.\r
+ (+) Start the Time Base.\r
+ (+) Stop the Time Base.\r
+ (+) Start the Time Base and enable interrupt.\r
+ (+) Stop the Time Base and disable interrupt.\r
+ (+) Start the Time Base and enable DMA transfer.\r
+ (+) Stop the Time Base and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Time base Unit according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->Base_MspInitCallback == NULL)\r
+ {\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->Base_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the Time Base configuration */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Base peripheral\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->Base_MspDeInitCallback == NULL)\r
+ {\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->Base_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Base MSP.\r
+ * @param htim TIM Base handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Base MSP.\r
+ * @param htim TIM Base handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Change the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in interrupt mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the TIM Update interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in interrupt mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ /* Disable the TIM Update interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in DMA mode.\r
+ * @param htim TIM Base handle\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Update DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in DMA mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+ * @brief TIM Output Compare functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Output Compare functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Output Compare.\r
+ (+) De-initialize the TIM Output Compare.\r
+ (+) Start the TIM Output Compare.\r
+ (+) Stop the TIM Output Compare.\r
+ (+) Start the TIM Output Compare and enable interrupt.\r
+ (+) Stop the TIM Output Compare and disable interrupt.\r
+ (+) Start the TIM Output Compare and enable DMA transfer.\r
+ (+) Stop the TIM Output Compare and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Output Compare according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->OC_MspInitCallback == NULL)\r
+ {\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->OC_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the Output Compare */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->OC_MspDeInitCallback == NULL)\r
+ {\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->OC_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare MSP.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Output Compare MSP.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+ * @brief TIM PWM functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM PWM functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM PWM.\r
+ (+) De-initialize the TIM PWM.\r
+ (+) Start the TIM PWM.\r
+ (+) Stop the TIM PWM.\r
+ (+) Start the TIM PWM and enable interrupt.\r
+ (+) Stop the TIM PWM and disable interrupt.\r
+ (+) Start the TIM PWM and enable DMA transfer.\r
+ (+) Stop the TIM PWM and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM PWM Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()\r
+ * @param htim TIM PWM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->PWM_MspInitCallback == NULL)\r
+ {\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->PWM_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the PWM */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM PWM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->PWM_MspDeInitCallback == NULL)\r
+ {\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->PWM_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM MSP.\r
+ * @param htim TIM PWM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM PWM MSP.\r
+ * @param htim TIM PWM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Capture/Compare 3 request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+ * @brief TIM Input Capture functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Input Capture functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Input Capture.\r
+ (+) De-initialize the TIM Input Capture.\r
+ (+) Start the TIM Input Capture.\r
+ (+) Stop the TIM Input Capture.\r
+ (+) Start the TIM Input Capture and enable interrupt.\r
+ (+) Stop the TIM Input Capture and disable interrupt.\r
+ (+) Start the TIM Input Capture and enable DMA transfer.\r
+ (+) Stop the TIM Input Capture and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Input Capture Time base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()\r
+ * @param htim TIM Input Capture handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->IC_MspInitCallback == NULL)\r
+ {\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->IC_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the input capture */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM Input Capture handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->IC_MspDeInitCallback == NULL)\r
+ {\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->IC_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture MSP.\r
+ * @param htim TIM Input Capture handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Input Capture MSP.\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in DMA mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The destination Buffer address.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in DMA mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+ * @brief TIM One Pulse functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM One Pulse functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM One Pulse.\r
+ (+) De-initialize the TIM One Pulse.\r
+ (+) Start the TIM One Pulse.\r
+ (+) Stop the TIM One Pulse.\r
+ (+) Start the TIM One Pulse and enable interrupt.\r
+ (+) Stop the TIM One Pulse and disable interrupt.\r
+ (+) Start the TIM One Pulse and enable DMA transfer.\r
+ (+) Stop the TIM One Pulse and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM One Pulse Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()\r
+ * @param htim TIM One Pulse handle\r
+ * @param OnePulseMode Select the One pulse mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->OnePulse_MspInitCallback == NULL)\r
+ {\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->OnePulse_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OnePulse_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Configure the Time base in the One Pulse Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Reset the OPM Bit */\r
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
+\r
+ /* Configure the OPM Mode */\r
+ htim->Instance->CR1 |= OnePulseMode;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM One Pulse\r
+ * @param htim TIM One Pulse handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->OnePulse_MspDeInitCallback == NULL)\r
+ {\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->OnePulse_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_OnePulse_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse MSP.\r
+ * @param htim TIM One Pulse handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM One Pulse MSP.\r
+ * @param htim TIM One Pulse handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Enable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+ No need to enable the counter, it's enabled automatically by hardware\r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be disable\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Disable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Enable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+ No need to enable the counter, it's enabled automatically by hardware\r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ /* Disable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+ * @brief TIM Encoder functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Encoder functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Encoder.\r
+ (+) De-initialize the TIM Encoder.\r
+ (+) Start the TIM Encoder.\r
+ (+) Stop the TIM Encoder.\r
+ (+) Start the TIM Encoder and enable interrupt.\r
+ (+) Stop the TIM Encoder and disable interrupt.\r
+ (+) Start the TIM Encoder and enable DMA transfer.\r
+ (+) Stop the TIM Encoder and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()\r
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together\r
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource\r
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param sConfig TIM Encoder Interface configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->Encoder_MspInitCallback == NULL)\r
+ {\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->Encoder_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_Encoder_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Reset the SMS and ECE bits */\r
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);\r
+\r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = htim->Instance->CCER;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr |= sConfig->EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));\r
+\r
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);\r
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+\r
+ /* Write to TIMx CCER */\r
+ htim->Instance->CCER = tmpccer;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Encoder interface\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->Encoder_MspDeInitCallback == NULL)\r
+ {\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->Encoder_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Encoder_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface MSP.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Encoder Interface MSP.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the encoder interface channels */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+ }\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in interrupt mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the encoder interface channels */\r
+ /* Enable the capture compare Interrupts 1 and/or 2 */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in interrupt mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 1 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 1 and 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in DMA mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @param pData1 The destination Buffer address for IC1.\r
+ * @param pData2 The destination Buffer address for IC2.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\r
+ uint32_t *pData2, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_ALL:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in DMA mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 1 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 1 and 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+ * @brief TIM IRQ handler management\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### IRQ handler management #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides Timer IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles TIM interrupts requests.\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Capture compare 1 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)\r
+ {\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ }\r
+ /* Capture compare 2 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 3 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 4 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* TIM Update event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM Break input event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->BreakCallback(htim);\r
+#else\r
+ HAL_TIMEx_BreakCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM Break2 input event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->Break2Callback(htim);\r
+#else\r
+ HAL_TIMEx_Break2Callback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM Trigger detection event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM commutation event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->CommutationCallback(htim);\r
+#else\r
+ HAL_TIMEx_CommutCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+ * @brief TIM Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.\r
+ (+) Configure External Clock source.\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master and the Slave synchronization.\r
+ (+) Configure the DMA Burst Mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare Channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim TIM Output Compare handle\r
+ * @param sConfig TIM Output Compare configuration structure\r
+ * @param Channel TIM Channels to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,\r
+ TIM_OC_InitTypeDef *sConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 1 in Output Compare */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 2 in Output Compare */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 3 in Output Compare */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 4 in Output Compare */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 5 in Output Compare */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 6 in Output Compare */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture Channels according to the specified\r
+ * parameters in the TIM_IC_InitTypeDef.\r
+ * @param htim TIM IC handle\r
+ * @param sConfig TIM Input Capture configuration structure\r
+ * @param Channel TIM Channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TIM_TI1_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI2_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Set the IC2PSC value */\r
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI3_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC3PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
+\r
+ /* Set the IC3PSC value */\r
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI4_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC4PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
+\r
+ /* Set the IC4PSC value */\r
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim TIM PWM handle\r
+ * @param sConfig TIM PWM configuration structure\r
+ * @param Channel TIM Channels to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,\r
+ TIM_OC_InitTypeDef *sConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 1 in PWM mode */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 2 in PWM mode */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 3 in PWM mode */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 4 in PWM mode */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 5 in PWM mode */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel5*/\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 6 in PWM mode */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel6 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse Channels according to the specified\r
+ * parameters in the TIM_OnePulse_InitTypeDef.\r
+ * @param htim TIM One Pulse handle\r
+ * @param sConfig TIM One Pulse configuration structure\r
+ * @param OutputChannel TIM output channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @param InputChannel TIM input Channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,\r
+ uint32_t OutputChannel, uint32_t InputChannel)\r
+{\r
+ TIM_OC_InitTypeDef temp1;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
+\r
+ if (OutputChannel != InputChannel)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Extract the Output compare configuration from sConfig structure */\r
+ temp1.OCMode = sConfig->OCMode;\r
+ temp1.Pulse = sConfig->Pulse;\r
+ temp1.OCPolarity = sConfig->OCPolarity;\r
+ temp1.OCNPolarity = sConfig->OCNPolarity;\r
+ temp1.OCIdleState = sConfig->OCIdleState;\r
+ temp1.OCNIdleState = sConfig->OCNIdleState;\r
+\r
+ switch (OutputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ TIM_OC1_SetConfig(htim->Instance, &temp1);\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_OC2_SetConfig(htim->Instance, &temp1);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (InputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
+\r
+ /* Select the Slave Mode */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
+\r
+ /* Select the Slave Mode */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_CCMR3 \r
+ * @arg TIM_DMABASE_CCR5 \r
+ * @arg TIM_DMABASE_CCR6 \r
+ * @arg TIM_DMABASE_AF1 \r
+ * @arg TIM_DMABASE_AF2 \r
+ * @arg TIM_DMABASE_TISEL\r
+ * \r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,\r
+ ((BurstLength) >> 8U) + 1U);\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_CCMR3 \r
+ * @arg TIM_DMABASE_CCR5 \r
+ * @arg TIM_DMABASE_CCR6 \r
+ * @arg TIM_DMABASE_AF1 \r
+ * @arg TIM_DMABASE_AF2 \r
+ * @arg TIM_DMABASE_TISEL\r
+ * \r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @param DataLength Data length. This parameter can be one value\r
+ * between 1 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,\r
+ uint32_t BurstLength, uint32_t DataLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,\r
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,\r
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,\r
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,\r
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,\r
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ /* Set the DMA commutation callbacks */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,\r
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ /* Set the DMA trigger callbacks */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,\r
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Configure the DMA Burst Mode */\r
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM DMA Burst mode\r
+ * @param htim TIM handle\r
+ * @param BurstRequestSrc TIM DMA Request sources to disable\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+ /* Abort the DMA transfer (at least disable the DMA stream) */\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (HAL_OK == status)\r
+ {\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_CCMR3 \r
+ * @arg TIM_DMABASE_CCR5 \r
+ * @arg TIM_DMABASE_CCR6 \r
+ * @arg TIM_DMABASE_AF1 \r
+ * @arg TIM_DMABASE_AF2 \r
+ * @arg TIM_DMABASE_TISEL\r
+ * \r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,\r
+ ((BurstLength) >> 8U) + 1U);\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_CCMR3 \r
+ * @arg TIM_DMABASE_CCR5 \r
+ * @arg TIM_DMABASE_CCR6 \r
+ * @arg TIM_DMABASE_AF1 \r
+ * @arg TIM_DMABASE_AF2 \r
+ * @arg TIM_DMABASE_TISEL\r
+ * \r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @param DataLength Data length. This parameter can be one value\r
+ * between 1 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\r
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,\r
+ uint32_t BurstLength, uint32_t DataLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\r
+ DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\r
+ DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\r
+ DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\r
+ DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\r
+ DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ /* Set the DMA commutation callbacks */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\r
+ DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ /* Set the DMA trigger callbacks */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\r
+ DataLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Configure the DMA Burst Mode */\r
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+\r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA burst reading\r
+ * @param htim TIM handle\r
+ * @param BurstRequestSrc TIM DMA Request sources to disable.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+ /* Abort the DMA transfer (at least disable the DMA stream) */\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (HAL_OK == status)\r
+ {\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Generate a software event\r
+ * @param htim TIM handle\r
+ * @param EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source\r
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source\r
+ * @note Basic timers can only generate an update event.\r
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.\r
+ * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant\r
+ * only for timer instances supporting break input(s).\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the event sources */\r
+ htim->Instance->EGR = EventSource;\r
+\r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the OCRef clear feature\r
+ * @param htim TIM handle\r
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that\r
+ * contains the OCREF clear feature and parameters for the TIM peripheral.\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (sClearInputConfig->ClearInputSource)\r
+ {\r
+ case TIM_CLEARINPUTSOURCE_NONE:\r
+ {\r
+ /* Clear the OCREF clear selection bit and the the ETR Bits */\r
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));\r
+ break;\r
+ }\r
+\r
+ case TIM_CLEARINPUTSOURCE_ETR:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+\r
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClearInputConfig->ClearInputPrescaler,\r
+ sClearInputConfig->ClearInputPolarity,\r
+ sClearInputConfig->ClearInputFilter);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 1 */\r
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 1 */\r
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 2 */\r
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 2 */\r
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 3 */\r
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 3 */\r
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 4 */\r
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 4 */\r
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_5:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 5 */\r
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 5 */\r
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_6:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 6 */\r
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 6 */\r
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the clock source to be used\r
+ * @param htim TIM handle\r
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that\r
+ * contains the clock source information for the TIM peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
+\r
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ switch (sClockSourceConfig->ClockSource)\r
+ {\r
+ case TIM_CLOCKSOURCE_INTERNAL:\r
+ {\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ETRMODE1:\r
+ {\r
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+\r
+ /* Check ETR input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClockSourceConfig->ClockPrescaler,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+\r
+ /* Select the External clock mode1 and the ETRF trigger */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ETRMODE2:\r
+ {\r
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));\r
+\r
+ /* Check ETR input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClockSourceConfig->ClockPrescaler,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ /* Enable the External clock mode2 */\r
+ htim->Instance->SMCR |= TIM_SMCR_ECE;\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI1:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 */\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI2:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI2 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI1ED:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 */\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ITR0:\r
+ case TIM_CLOCKSOURCE_ITR1:\r
+ case TIM_CLOCKSOURCE_ITR2:\r
+ case TIM_CLOCKSOURCE_ITR3:\r
+ case TIM_CLOCKSOURCE_ITR4:\r
+ case TIM_CLOCKSOURCE_ITR5:\r
+ case TIM_CLOCKSOURCE_ITR6:\r
+ case TIM_CLOCKSOURCE_ITR7:\r
+ case TIM_CLOCKSOURCE_ITR8:\r
+ {\r
+ /* Check whether or not the timer instance supports internal trigger input */\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+\r
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input\r
+ * or a XOR combination between CH1_input, CH2_input & CH3_input\r
+ * @param htim TIM handle.\r
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the\r
+ * output of a XOR gate.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
+ * pins are connected to the TI1 input (XOR combination)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
+{\r
+ uint32_t tmpcr2;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Reset the TI1 selection */\r
+ tmpcr2 &= ~TIM_CR2_TI1S;\r
+\r
+ /* Set the TI1 selection */\r
+ tmpcr2 |= TI1_Selection;\r
+\r
+ /* Write to TIMxCR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode\r
+ * @param htim TIM handle.\r
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the Slave mode\r
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Trigger Interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode in interrupt mode\r
+ * @param htim TIM handle.\r
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the Slave mode\r
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable Trigger Interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read the captured value from Capture Compare unit\r
+ * @param htim TIM handle.\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval Captured value\r
+ */\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpreg = 0U;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 1 value */\r
+ tmpreg = htim->Instance->CCR1;\r
+\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 2 value */\r
+ tmpreg = htim->Instance->CCR2;\r
+\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 3 value */\r
+ tmpreg = htim->Instance->CCR3;\r
+\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 4 value */\r
+ tmpreg = htim->Instance->CCR4;\r
+\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Callbacks functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides TIM callback functions:\r
+ (+) TIM Period elapsed callback\r
+ (+) TIM Output Compare callback\r
+ (+) TIM Input capture callback\r
+ (+) TIM Trigger callback\r
+ (+) TIM Error callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Period elapsed callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Period elapsed half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Output Compare callback in non-blocking mode\r
+ * @param htim TIM OC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input Capture callback in non-blocking mode\r
+ * @param htim TIM IC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input Capture half complete callback in non-blocking mode\r
+ * @param htim TIM IC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Timer error callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback\r
+ * @param htim tim handle\r
+ * @param CallbackID ID of the callback to be registered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
+ * @param pCallback pointer to the callback function\r
+ * @retval status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\r
+ pTIM_CallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ if (htim->State == HAL_TIM_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+ htim->PeriodElapsedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+ htim->PeriodElapsedHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_CB_ID :\r
+ htim->TriggerCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+ htim->TriggerHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_CB_ID :\r
+ htim->IC_CaptureCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+ htim->IC_CaptureHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+ htim->OC_DelayElapsedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+ htim->PWM_PulseFinishedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ERROR_CB_ID :\r
+ htim->ErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_CB_ID :\r
+ htim->CommutationCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
+ htim->CommutationHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BREAK_CB_ID :\r
+ htim->BreakCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BREAK2_CB_ID :\r
+ htim->Break2Callback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Unregister a TIM callback\r
+ * TIM callback is redirected to the weak predefined callback\r
+ * @param htim tim handle\r
+ * @param CallbackID ID of the callback to be unregistered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
+ * @retval status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ if (htim->State == HAL_TIM_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_CB_ID :\r
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_CB_ID :\r
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ERROR_CB_ID :\r
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_CB_ID :\r
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BREAK_CB_ID :\r
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BREAK2_CB_ID :\r
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return status;\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+ * @brief TIM Peripheral State functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Base handle state.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM OC handle state.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM PWM handle state.\r
+ * @param htim TIM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Input Capture handle state.\r
+ * @param htim TIM IC handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM One Pulse Mode handle state.\r
+ * @param htim TIM OPM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Encoder Mode handle state.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA error callback\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->ErrorCallback(htim);\r
+#else\r
+ HAL_TIM_ErrorCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Capture complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Capture half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief Time Base configuration\r
+ * @param TIMx TIM peripheral\r
+ * @param Structure TIM Base configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
+{\r
+ uint32_t tmpcr1;\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))\r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
+ tmpcr1 |= Structure->CounterMode;\r
+ }\r
+\r
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= ~TIM_CR1_CKD;\r
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
+ }\r
+\r
+ /* Set the auto-reload preload */\r
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = (uint32_t)Structure->Period ;\r
+\r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Structure->Prescaler;\r
+\r
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))\r
+ {\r
+ /* Set the Repetition Counter value */\r
+ TIMx->RCR = Structure->RepetitionCounter;\r
+ }\r
+\r
+ /* Generate an update event to reload the Prescaler\r
+ and the repetition counter (only for advanced timer) value immediately */\r
+ TIMx->EGR = TIM_EGR_UG;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 1 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC1M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC1S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= OC_Config->OCPolarity;\r
+\r
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= OC_Config->OCNPolarity;\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC1NE;\r
+ }\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS1;\r
+ tmpcr2 &= ~TIM_CR2_OIS1N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= OC_Config->OCIdleState;\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= OC_Config->OCNIdleState;\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 2 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC2M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC2S;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 4U);\r
+\r
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 4U);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC2NE;\r
+\r
+ }\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS2;\r
+ tmpcr2 &= ~TIM_CR2_OIS2N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 3 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 3: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC3M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC3S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 8U);\r
+\r
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 8U);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC3NE;\r
+ }\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS3;\r
+ tmpcr2 &= ~TIM_CR2_OIS3N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 4 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC4M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC4S;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC4P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 12U);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS4;\r
+\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 5 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,\r
+ TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC5E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC5P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 16U);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS5;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR5 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 6 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,\r
+ TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC6E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 20U);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS6;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR6 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Slave Timer configuration function\r
+ * @param htim TIM handle\r
+ * @param sSlaveConfig Slave timer configuration\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the Trigger Selection Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+ /* Reset the slave mode Bits */\r
+ tmpsmcr &= ~TIM_SMCR_SMS;\r
+ /* Set the slave mode */\r
+ tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Configure the trigger prescaler, filter, and polarity */\r
+ switch (sSlaveConfig->InputTrigger)\r
+ {\r
+ case TIM_TS_ETRF:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ /* Configure the ETR Trigger source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sSlaveConfig->TriggerPrescaler,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI1F_ED:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = htim->Instance->CCER;\r
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+ htim->Instance->CCER = tmpccer;\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI1FP1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI1 Filter and Polarity */\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI2FP2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI2 Filter and Polarity */\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_ITR0:\r
+ case TIM_TS_ITR1:\r
+ case TIM_TS_ITR2:\r
+ case TIM_TS_ITR3:\r
+ case TIM_TS_ITR4:\r
+ case TIM_TS_ITR5:\r
+ case TIM_TS_ITR6:\r
+ case TIM_TS_ITR7:\r
+ case TIM_TS_ITR8:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1\r
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
+ {\r
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
+ tmpccmr1 |= TIM_ICSelection;\r
+ }\r
+ else\r
+ {\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
+ }\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI1.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = TIMx->CCER;\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= (TIM_ICFilter << 4U);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_ICPolarity;\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
+ tmpccmr1 |= (TIM_ICSelection << 8U);\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI2.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= (TIM_ICFilter << 12U);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= (TIM_ICPolarity << 4U);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
+ tmpccmr2 |= TIM_ICSelection;\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);\r
+\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ * @retval None\r
+ */\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
+ tmpccmr2 |= (TIM_ICSelection << 8U);\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param InputTriggerSource The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @arg TIM_TS_ITR4: Internal Trigger 4\r
+ * @arg TIM_TS_ITR5: Internal Trigger 5\r
+ * @arg TIM_TS_ITR6: Internal Trigger 6\r
+ * @arg TIM_TS_ITR7: Internal Trigger 7\r
+ * @arg TIM_TS_ITR8: Internal Trigger 8\r
+ * @retval None\r
+ */\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source and the slave mode*/\r
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.\r
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.\r
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.\r
+ * @param ExtTRGFilter External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));\r
+\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)\r
+{\r
+ uint32_t tmp;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+\r
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxE Bit */\r
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.\r
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Reset the TIM callback to the legacy weak callbacks */\r
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */\r
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */\r
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */\r
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */\r
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */\r
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */\r
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */\r
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */\r
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */\r
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */\r
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */\r
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */\r
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_tim_ex.c\r
+ * @author MCD Application Team\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Timer Extended peripheral:\r
+ * + Time Hall Sensor Interface Initialization\r
+ * + Time Hall Sensor Interface Start\r
+ * + Time Complementary signal break and dead time configuration\r
+ * + Time Master and Slave synchronization configuration\r
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)\r
+ * + Timer remapping capabilities configuration\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### TIMER Extended features #####\r
+ ==============================================================================\r
+ [..]\r
+ The Timer Extended features include:\r
+ (#) Complementary outputs with programmable dead-time for :\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output\r
+ (#) Synchronization circuit to control the timer with external signals and to\r
+ interconnect several timers together.\r
+ (#) Break input to put the timer output signals in reset state or in a known state.\r
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for\r
+ positioning purposes\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions\r
+ depending on the selected feature:\r
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()\r
+\r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE();\r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the\r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
+ any start function.\r
+\r
+ (#) Configure the TIM in the desired functioning mode using one of the\r
+ initialization function of this driver:\r
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the\r
+ Timer Hall Sensor Interface and the commutation event with the corresponding\r
+ Interrupt and DMA request if needed (Note that One Timer is used to interface\r
+ with the Hall sensor Interface and another Timer should be used to use\r
+ the commutation event).\r
+\r
+ (#) Activate the TIM peripheral using one of the start functions:\r
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()\r
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx TIMEx\r
+ * @brief TIM Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+ * @brief Timer Hall Sensor functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Hall Sensor functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure TIM HAL Sensor.\r
+ (+) De-initialize TIM HAL Sensor.\r
+ (+) Start the Hall Sensor Interface.\r
+ (+) Stop the Hall Sensor Interface.\r
+ (+) Start the Hall Sensor Interface and enable interrupts.\r
+ (+) Stop the Hall Sensor Interface and disable interrupts.\r
+ (+) Start the Hall Sensor Interface and enable DMA transfers.\r
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @param sConfig TIM Hall Sensor configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)\r
+{\r
+ TIM_OC_InitTypeDef OC_Config;\r
+\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy week callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->HallSensor_MspInitCallback == NULL)\r
+ {\r
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->HallSensor_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIMEx_HallSensor_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */\r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r
+\r
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */\r
+ htim->Instance->CR2 |= TIM_CR2_TI1S;\r
+\r
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r
+\r
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r
+\r
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
+ OC_Config.OCMode = TIM_OCMODE_PWM2;\r
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
+ OC_Config.Pulse = sConfig->Commutation_Delay;\r
+\r
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r
+\r
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r
+ register to 101 */\r
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Hall Sensor interface\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->HallSensor_MspDeInitCallback == NULL)\r
+ {\r
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->HallSensor_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIMEx_HallSensor_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor MSP.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Hall Sensor MSP.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall sensor Interface.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1, 2 and 3\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Enable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts event */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @param pData The destination Buffer address.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if (((uint32_t)pData == 0U) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ /* Enable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+ /* Set the DMA Input Capture 1 Callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream for Capture 1*/\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the capture compare 1 Interrupt */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+\r
+ /* Disable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+ * @brief Timer Complementary Output Compare functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Complementary Output Compare functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary Output Compare/PWM.\r
+ (+) Stop the Complementary Output Compare/PWM.\r
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.\r
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode\r
+ * on the complementary output.\r
+ * @param htim TIM OC handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode\r
+ * on the complementary output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode\r
+ * on the complementary output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if (((uint32_t)pData == 0U) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode\r
+ * on the complementary output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+ * @brief Timer Complementary PWM functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Complementary PWM functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary PWM.\r
+ (+) Stop the Complementary PWM.\r
+ (+) Start the Complementary PWM and enable interrupts.\r
+ (+) Stop the Complementary PWM and disable interrupts.\r
+ (+) Start the Complementary PWM and enable DMA transfers.\r
+ (+) Stop the Complementary PWM and disable DMA transfers.\r
+ (+) Start the Complementary Input Capture measurement.\r
+ (+) Stop the Complementary Input Capture.\r
+ (+) Start the Complementary Input Capture and enable interrupts.\r
+ (+) Stop the Complementary Input Capture and disable interrupts.\r
+ (+) Start the Complementary Input Capture and enable DMA transfers.\r
+ (+) Stop the Complementary Input Capture and disable DMA transfers.\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation on the complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation on the complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode on the\r
+ * complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode on the\r
+ * complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode on the\r
+ * complementary output\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if (((uint32_t)pData == 0U) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary\r
+ * output\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+ * @brief Timer Complementary One Pulse functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Complementary One Pulse functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Configure the commutation event in case of use of the Hall sensor interface.\r
+ (+) Configure Output channels for OC and PWM mode.\r
+\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master synchronization.\r
+ (+) Configure timer remapping capabilities.\r
+ (+) Select timer input source.\r
+ (+) Enable or disable channel grouping.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence.\r
+ * @note This function is mandatory to use the commutation event in order to\r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer)\r
+ * configured in Hall sensor interface, this interface Timer will generate the\r
+ * commutation at its TRGO output (connected to Timer used in this function) each time\r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim TIM handle\r
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource the Commutation Event source\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,\r
+ uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ {\r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+\r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+\r
+ /* Disable Commutation Interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
+\r
+ /* Disable Commutation DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with interrupt.\r
+ * @note This function is mandatory to use the commutation event in order to\r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer)\r
+ * configured in Hall sensor interface, this interface Timer will generate the\r
+ * commutation at its TRGO output (connected to Timer used in this function) each time\r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim TIM handle\r
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource the Commutation Event source\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,\r
+ uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ {\r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+\r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+\r
+ /* Disable Commutation DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ /* Enable the Commutation Interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with DMA.\r
+ * @note This function is mandatory to use the commutation event in order to\r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer)\r
+ * configured in Hall sensor interface, this interface Timer will generate the\r
+ * commutation at its TRGO output (connected to Timer used in this function) each time\r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set\r
+ * @param htim TIM handle\r
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource the Commutation Event source\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,\r
+ uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ {\r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+\r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+\r
+ /* Enable the Commutation DMA Request */\r
+ /* Set the DMA Commutation Callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;\r
+\r
+ /* Disable Commutation Interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
+\r
+ /* Enable the Commutation DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in master mode.\r
+ * @param htim TIM handle.\r
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that\r
+ * contains the selected trigger output (TRGO) and the Master/Slave\r
+ * mode.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
+ TIM_MasterConfigTypeDef *sMasterConfig)\r
+{\r
+ uint32_t tmpcr2;\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Change the handler state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */\r
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));\r
+\r
+ /* Clear the MMS2 bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS2;\r
+ /* Select the TRGO2 source*/\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;\r
+ }\r
+\r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS;\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;\r
+\r
+ /* Reset the MSM Bit */\r
+ tmpsmcr &= ~TIM_SMCR_MSM;\r
+ /* Set master mode */\r
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;\r
+\r
+ /* Update TIMx CR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ /* Update TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r
+ * and the AOE(automatic output enable).\r
+ * @param htim TIM handle\r
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that\r
+ * contains the BDTR Register configuration information for the TIM peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)\r
+{\r
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */\r
+ uint32_t tmpbdtr = 0U;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));\r
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+\r
+ /* Set the BDTR bits */\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));\r
+\r
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));\r
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));\r
+\r
+ /* Set the BREAK2 input related BDTR bits */\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);\r
+ }\r
+\r
+ /* Set TIMx_BDTR */\r
+ htim->Instance->BDTR = tmpbdtr;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+\r
+/**\r
+ * @brief Configures the break input source.\r
+ * @param htim TIM handle.\r
+ * @param BreakInput Break input to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_BREAKINPUT_BRK: Timer break input\r
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input\r
+ * @param sBreakInputConfig Break input source configuration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,\r
+ uint32_t BreakInput,\r
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)\r
+\r
+{\r
+ uint32_t tmporx;\r
+ uint32_t bkin_enable_mask = 0U;\r
+ uint32_t bkin_polarity_mask = 0U;\r
+ uint32_t bkin_enable_bitpos = 0U;\r
+ uint32_t bkin_polarity_bitpos = 0U;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));\r
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+ {\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));\r
+ }\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ switch (sBreakInputConfig->Source)\r
+ {\r
+ case TIM_BREAKINPUTSOURCE_BKIN:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKINE;\r
+ bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;\r
+ bkin_polarity_mask = TIM1_AF1_BKINP;\r
+ bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;\r
+ break;\r
+ }\r
+ case TIM_BREAKINPUTSOURCE_COMP1:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKCMP1E;\r
+ bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;\r
+ bkin_polarity_mask = TIM1_AF1_BKCMP1P;\r
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;\r
+ break;\r
+ }\r
+ case TIM_BREAKINPUTSOURCE_COMP2:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKCMP2E;\r
+ bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;\r
+ bkin_polarity_mask = TIM1_AF1_BKCMP2P;\r
+ bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;\r
+ break;\r
+ }\r
+ case TIM_BREAKINPUTSOURCE_DFSDM1:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKDF1BK0E;\r
+ bkin_enable_bitpos = 8U;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (BreakInput)\r
+ {\r
+ case TIM_BREAKINPUT_BRK:\r
+ {\r
+ /* Get the TIMx_AF1 register value */\r
+ tmporx = htim->Instance->AF1;\r
+\r
+ /* Enable the break input */\r
+ tmporx &= ~bkin_enable_mask;\r
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+\r
+ /* Set the break input polarity */\r
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+ {\r
+ tmporx &= ~bkin_polarity_mask;\r
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
+ }\r
+\r
+ /* Set TIMx_AF1 */\r
+ htim->Instance->AF1 = tmporx;\r
+ break;\r
+ }\r
+ case TIM_BREAKINPUT_BRK2:\r
+ {\r
+ /* Get the TIMx_AF2 register value */\r
+ tmporx = htim->Instance->AF2;\r
+\r
+ /* Enable the break input */\r
+ tmporx &= ~bkin_enable_mask;\r
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+\r
+ /* Set the break input polarity */\r
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+ {\r
+ tmporx &= ~bkin_polarity_mask;\r
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
+ }\r
+\r
+ /* Set TIMx_AF2 */\r
+ htim->Instance->AF2 = tmporx;\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+#endif /*TIM_BREAK_INPUT_SUPPORT */\r
+\r
+/**\r
+ * @brief Configures the TIMx Remapping input capabilities.\r
+ * @param htim TIM handle.\r
+ * @param Remap specifies the TIM remapping source.\r
+ * For TIM1, the parameter is one of the following values:\r
+ * @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO\r
+ * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output\r
+ * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output\r
+ * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1\r
+ * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2\r
+ * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3\r
+ * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1\r
+ * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2\r
+ * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3\r
+ *\r
+ * For TIM2, the parameter is one of the following values:\r
+ * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO\r
+ * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output\r
+ * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output\r
+ * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE\r
+ * @arg TIM_TIM2_ETR_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A\r
+ * @arg TIM_TIM2_ETR_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B\r
+ *\r
+ * For TIM3, the parameter is one of the following values:\r
+ * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO\r
+ * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output\r
+ *\r
+ * For TIM5, the parameter is one of the following values:\r
+ * @arg TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO\r
+ * @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A\r
+ * @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B\r
+ *\r
+ * For TIM8, the parameter is one of the following values:\r
+ * @arg TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO\r
+ * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output\r
+ * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output\r
+ * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1\r
+ * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2\r
+ * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3\r
+ * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1\r
+ * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2\r
+ * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_REMAP(Remap));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Select the timer input source\r
+ * @param htim TIM handle.\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TI1 input channel\r
+ * @arg TIM_CHANNEL_2: TI2 input channel\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4\r
+ * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:\r
+ * For TIM1, the parameter is one of the following values:\r
+ * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO\r
+ * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output\r
+ *\r
+ * For TIM2, the parameter is one of the following values:\r
+ * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO\r
+ * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output\r
+ * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output\r
+ * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output\r
+ *\r
+ * For TIM3, the parameter is one of the following values:\r
+ * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO\r
+ * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output\r
+ * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output\r
+ * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output\r
+ *\r
+ * For TIM5, the parameter is one of the following values:\r
+ * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO\r
+ * @arg TIM_TIM5_TI1_CAN_TMP: TIM5 TI1 is connected to CAN TMP\r
+ * @arg TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP\r
+ *\r
+ * For TIM8, the parameter is one of the following values:\r
+ * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO\r
+ * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output\r
+ *\r
+ * For TIM15, the parameter is one of the following values:\r
+ * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO\r
+ * @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1\r
+ * @arg TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1\r
+ * @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1\r
+ * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE\r
+ * @arg TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI\r
+ * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2\r
+ * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO\r
+ * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2\r
+ * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2\r
+ * @arg TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2\r
+ *\r
+ * For TIM16, the parameter can have the following values:\r
+ * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO\r
+ * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI\r
+ * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE\r
+ * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt\r
+ *\r
+ * For TIM17, the parameter can have the following values:\r
+ * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO\r
+ * @arg TIM_TIM17_TI1_SPDIFFS: TIM17 TI1 is connected to SPDIF FS\r
+ * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz\r
+ * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TISEL(TISelection));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);\r
+ break;\r
+ case TIM_CHANNEL_2:\r
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);\r
+ break;\r
+ case TIM_CHANNEL_3:\r
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);\r
+ break;\r
+ case TIM_CHANNEL_4:\r
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);\r
+ break;\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Group channel 5 and channel 1, 2 or 3\r
+ * @param htim TIM handle.\r
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.\r
+ * This parameter can be any combination of the following values:\r
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC\r
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF\r
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF\r
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_GROUPCH5(Channels));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Clear GC5Cx bit fields */\r
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);\r
+\r
+ /* Set GC5Cx bit fields */\r
+ htim->Instance->CCR5 |= Channels;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
+ * @brief Extended Callbacks functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Extended Callbacks functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides Extended TIM callback functions:\r
+ (+) Timer Commutation callback\r
+ (+) Timer Break callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Hall commutation changed callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_CommutCallback could be implemented in the user file\r
+ */\r
+}\r
+/**\r
+ * @brief Hall commutation changed half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Break detection callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_BreakCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Break2 detection callback in non blocking mode\r
+ * @param htim: TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_Break2Callback could be implemented in the user file\r
+ */\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
+ * @brief Extended Peripheral State functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Extended Peripheral State functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Hall Sensor interface handle state.\r
+ * @param htim TIM Hall Sensor handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA Commutation callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->CommutationCallback(htim);\r
+#else\r
+ HAL_TIMEx_CommutCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Commutation half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->CommutationHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIMEx_CommutHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel xN.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.\r
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.\r
+ * @retval None\r
+ */\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)\r
+{\r
+ uint32_t tmp;\r
+\r
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
+\r
+ /* Reset the CCxNE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxNE Bit */\r
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_uart.c\r
+ * @author MCD Application Team\r
+ * @brief UART HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ *\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The UART HAL driver can be used as follows:\r
+\r
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).\r
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r
+ (++) Enable the USARTx interface clock.\r
+ (++) UART pins configuration:\r
+ (+++) Enable the clock for the UART GPIOs.\r
+ (+++) Configure these UART pins as alternate function pull-up.\r
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r
+ and HAL_UART_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (++) UART interrupts handling:\r
+ -@@- The specific UART interrupts (Transmission complete interrupt,\r
+ RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)\r
+ are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()\r
+ inside the transmit and receive processes.\r
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r
+ and HAL_UART_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r
+ (+++) Configure the DMA Tx/Rx channel.\r
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.\r
+\r
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware\r
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.\r
+\r
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)\r
+ in the huart handle AdvancedInit structure.\r
+\r
+ (#) For the UART asynchronous mode, initialize the UART registers by calling\r
+ the HAL_UART_Init() API.\r
+\r
+ (#) For the UART Half duplex mode, initialize the UART registers by calling\r
+ the HAL_HalfDuplex_Init() API.\r
+\r
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers\r
+ by calling the HAL_LIN_Init() API.\r
+\r
+ (#) For the UART Multiprocessor mode, initialize the UART registers\r
+ by calling the HAL_MultiProcessor_Init() API.\r
+\r
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers\r
+ by calling the HAL_RS485Ex_Init() API.\r
+\r
+ [..]\r
+ (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),\r
+ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by\r
+ calling the customized HAL_UART_MspInit() API.\r
+\r
+ ##### Callback registration #####\r
+ ==================================\r
+\r
+ [..]\r
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1\r
+ allows the user to configure dynamically the driver callbacks.\r
+\r
+ [..]\r
+ Use Function @ref HAL_UART_RegisterCallback() to register a user callback.\r
+ Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:\r
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.\r
+ (+) TxCpltCallback : Tx Complete Callback.\r
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.\r
+ (+) RxCpltCallback : Rx Complete Callback.\r
+ (+) ErrorCallback : Error Callback.\r
+ (+) AbortCpltCallback : Abort Complete Callback.\r
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.\r
+ (+) WakeupCallback : Wakeup Callback.\r
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.\r
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.\r
+ (+) MspInitCallback : UART MspInit.\r
+ (+) MspDeInitCallback : UART MspDeInit.\r
+ This function takes as parameters the HAL peripheral handle, the Callback ID\r
+ and a pointer to the user callback function.\r
+\r
+ [..]\r
+ Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default\r
+ weak (surcharged) function.\r
+ @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
+ and the Callback ID.\r
+ This function allows to reset following callbacks:\r
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.\r
+ (+) TxCpltCallback : Tx Complete Callback.\r
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.\r
+ (+) RxCpltCallback : Rx Complete Callback.\r
+ (+) ErrorCallback : Error Callback.\r
+ (+) AbortCpltCallback : Abort Complete Callback.\r
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\r
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.\r
+ (+) WakeupCallback : Wakeup Callback.\r
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.\r
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.\r
+ (+) MspInitCallback : UART MspInit.\r
+ (+) MspDeInitCallback : UART MspDeInit.\r
+\r
+ [..]\r
+ By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET\r
+ all callbacks are set to the corresponding weak (surcharged) functions:\r
+ examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().\r
+ Exception done for MspInit and MspDeInit functions that are respectively\r
+ reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()\r
+ and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).\r
+ If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()\r
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).\r
+\r
+ [..]\r
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.\r
+ Exception done MspInit/MspDeInit that can be registered/unregistered\r
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)\r
+ MspInit/DeInit callbacks can be used during the Init/DeInit.\r
+ In that case first register the MspInit/MspDeInit user callbacks\r
+ using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()\r
+ or @ref HAL_UART_Init() function.\r
+\r
+ [..]\r
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or\r
+ not defined, the callback registration feature is not available\r
+ and weak (surcharged) callbacks are used.\r
+\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART UART\r
+ * @brief HAL UART module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup UART_Private_Constants UART Private Constants\r
+ * @{\r
+ */\r
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \\r
+ USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */\r
+\r
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \\r
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */\r
+\r
+#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */\r
+#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */\r
+\r
+#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */\r
+#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions\r
+ * @{\r
+ */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);\r
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);\r
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);\r
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);\r
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup UART_Exported_Functions UART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
+ in asynchronous mode.\r
+ (+) For the asynchronous mode the parameters below can be configured:\r
+ (++) Baud Rate\r
+ (++) Word Length\r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ (++) Hardware flow control\r
+ (++) Receiver/transmitter modes\r
+ (++) Over Sampling Method\r
+ (++) One-Bit Sampling Method\r
+ (+) For the asynchronous mode, the following advanced features can be configured as well:\r
+ (++) TX and/or RX pin level inversion\r
+ (++) data logical level inversion\r
+ (++) RX and TX pins swap\r
+ (++) RX overrun detection disabling\r
+ (++) DMA disabling on RX error\r
+ (++) MSB first on communication line\r
+ (++) auto Baud rate detection\r
+ [..]\r
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API\r
+ follow respectively the UART asynchronous, UART Half duplex, UART LIN mode\r
+ and UART multiprocessor mode configuration procedures (details for the procedures\r
+ are available in reference manual).\r
+\r
+@endverbatim\r
+\r
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
+ 8-bit or 9-bit), the possible UART formats are listed in the\r
+ following table.\r
+\r
+ Table 1. UART frame format.\r
+ +-----------------------------------------------------------------------+\r
+ | M1 bit | M0 bit | PCE bit | UART frame |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |\r
+ +-----------------------------------------------------------------------+\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the UART mode according to the specified\r
+ * parameters in the UART_InitTypeDef and initialize the associated handle.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r
+ }\r
+ else\r
+ {\r
+ /* Check the parameters */\r
+ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));\r
+ }\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In asynchronous mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Initialize the half-duplex mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check UART instance */\r
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In half-duplex mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the LIN mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle.\r
+ * @param huart UART handle.\r
+ * @param BreakDetectLength Specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection\r
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the LIN UART instance */\r
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\r
+ /* Check the Break detection length parameter */\r
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r
+\r
+ /* LIN mode limited to 16-bit oversampling only */\r
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* LIN mode limited to 8-bit data length */\r
+ if (huart->Init.WordLength != UART_WORDLENGTH_8B)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In LIN mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\r
+\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\r
+\r
+ /* Set the USART LIN Break detection length. */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the multiprocessor mode according to the specified\r
+ * parameters in the UART_InitTypeDef and initialize the associated handle.\r
+ * @param huart UART handle.\r
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).\r
+ * @param WakeUpMethod Specifies the UART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection\r
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark\r
+ * @note If the user resorts to idle line detection wake up, the Address parameter\r
+ * is useless and ignored by the initialization function.\r
+ * @note If the user resorts to address mark wake up, the address length detection\r
+ * is configured by default to 4 bits only. For the UART to be able to\r
+ * manage 6-, 7- or 8-bit long addresses detection, the API\r
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after\r
+ * HAL_MultiProcessor_Init().\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the wake up method parameter */\r
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In multiprocessor mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */\r
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)\r
+ {\r
+ /* If address mark wake up method is chosen, set the USART address node */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));\r
+ }\r
+\r
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */\r
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInitialize the UART peripheral.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ huart->Instance->CR1 = 0x0U;\r
+ huart->Instance->CR2 = 0x0U;\r
+ huart->Instance->CR3 = 0x0U;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ if (huart->MspDeInitCallback == NULL)\r
+ {\r
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ huart->MspDeInitCallback(huart);\r
+#else\r
+ /* DeInit the low level hardware */\r
+ HAL_UART_MspDeInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_RESET;\r
+ huart->RxState = HAL_UART_STATE_RESET;\r
+\r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the UART MSP.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the UART MSP.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspDeInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Register a User UART Callback\r
+ * To be used instead of the weak predefined callback\r
+ * @param huart uart handle\r
+ * @param CallbackID ID of the callback to be registered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID\r
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+ * @param pCallback pointer to the Callback function\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
+ huart->TxHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_TX_COMPLETE_CB_ID :\r
+ huart->TxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
+ huart->RxHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_RX_COMPLETE_CB_ID :\r
+ huart->RxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ERROR_CB_ID :\r
+ huart->ErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ABORT_COMPLETE_CB_ID :\r
+ huart->AbortCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
+ huart->AbortTransmitCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
+ huart->AbortReceiveCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_WAKEUP_CB_ID :\r
+ huart->WakeupCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_RX_FIFO_FULL_CB_ID :\r
+ huart->RxFifoFullCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :\r
+ huart->TxFifoEmptyCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Unregister an UART Callback\r
+ * UART callaback is redirected to the weak predefined callback\r
+ * @param huart uart handle\r
+ * @param CallbackID ID of the callback to be unregistered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\r
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\r
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID\r
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\r
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if (HAL_UART_STATE_READY == huart->gState)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :\r
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_TX_COMPLETE_CB_ID :\r
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :\r
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_RX_COMPLETE_CB_ID :\r
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_ERROR_CB_ID :\r
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ break;\r
+\r
+ case HAL_UART_ABORT_COMPLETE_CB_ID :\r
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\r
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\r
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */\r
+ break;\r
+\r
+ case HAL_UART_WAKEUP_CB_ID :\r
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */\r
+ break;\r
+\r
+ case HAL_UART_RX_FIFO_FULL_CB_ID :\r
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */\r
+ break;\r
+\r
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :\r
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */\r
+ break;\r
+\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (HAL_UART_STATE_RESET == huart->gState)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_UART_MSPINIT_CB_ID :\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ break;\r
+\r
+ case HAL_UART_MSPDEINIT_CB_ID :\r
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return status;\r
+}\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions\r
+ * @brief UART Transmit/Receive functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the UART asynchronous\r
+ and Half duplex data transfers.\r
+\r
+ (#) There are two mode of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (+) Non-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_UART_Transmit()\r
+ (+) HAL_UART_Receive()\r
+\r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_UART_Transmit_IT()\r
+ (+) HAL_UART_Receive_IT()\r
+ (+) HAL_UART_IRQHandler()\r
+\r
+ (#) Non-Blocking mode API's with DMA are :\r
+ (+) HAL_UART_Transmit_DMA()\r
+ (+) HAL_UART_Receive_DMA()\r
+ (+) HAL_UART_DMAPause()\r
+ (+) HAL_UART_DMAResume()\r
+ (+) HAL_UART_DMAStop()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r
+ (+) HAL_UART_TxHalfCpltCallback()\r
+ (+) HAL_UART_TxCpltCallback()\r
+ (+) HAL_UART_RxHalfCpltCallback()\r
+ (+) HAL_UART_RxCpltCallback()\r
+ (+) HAL_UART_ErrorCallback()\r
+\r
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :\r
+ (+) HAL_UART_Abort()\r
+ (+) HAL_UART_AbortTransmit()\r
+ (+) HAL_UART_AbortReceive()\r
+ (+) HAL_UART_Abort_IT()\r
+ (+) HAL_UART_AbortTransmit_IT()\r
+ (+) HAL_UART_AbortReceive_IT()\r
+\r
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:\r
+ (+) HAL_UART_AbortCpltCallback()\r
+ (+) HAL_UART_AbortTransmitCpltCallback()\r
+ (+) HAL_UART_AbortReceiveCpltCallback()\r
+\r
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.\r
+ Errors are handled as follows :\r
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is\r
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .\r
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,\r
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.\r
+ If user wants to abort it, Abort services should be called by user.\r
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.\r
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.\r
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.\r
+\r
+ -@- In the Half duplex communication, it is forbidden to run the transmit\r
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Send an amount of data in blocking mode.\r
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one\r
+ * data to the TXFIFO. Write operations to the TDR register are performed\r
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and\r
+ * TXE are mapped on the same bit-field.\r
+ * @param huart UART handle.\r
+ * @param pData Pointer to data buffer.\r
+ * @param Size Amount of data to be sent.\r
+ * @param Timeout Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint8_t *pdata8bits;\r
+ uint16_t *pdata16bits;\r
+ uint32_t tickstart;\r
+\r
+ /* Check that a Tx process is not already ongoing */\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+\r
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ pdata8bits = NULL;\r
+ pdata16bits = (uint16_t *) pData;\r
+ }\r
+ else\r
+ {\r
+ pdata8bits = pData;\r
+ pdata16bits = NULL;\r
+ }\r
+\r
+ while (huart->TxXferCount > 0U)\r
+ {\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if (pdata8bits == NULL)\r
+ {\r
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);\r
+ pdata16bits++;\r
+ }\r
+ else\r
+ {\r
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);\r
+ pdata8bits++;\r
+ }\r
+ huart->TxXferCount--;\r
+ }\r
+\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* At end of Tx process, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode.\r
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO\r
+ * is not empty. Read operations from the RDR register are performed when\r
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and\r
+ * RXNE are mapped on the same bit-field.\r
+ * @param huart UART handle.\r
+ * @param pData Pointer to data buffer.\r
+ * @param Size Amount of data to be received.\r
+ * @param Timeout Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint8_t *pdata8bits;\r
+ uint16_t *pdata16bits;\r
+ uint16_t uhMask;\r
+ uint32_t tickstart;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ huart->RxXferSize = Size;\r
+ huart->RxXferCount = Size;\r
+\r
+ /* Computation of UART mask to apply to RDR register */\r
+ UART_MASK_COMPUTATION(huart);\r
+ uhMask = huart->Mask;\r
+\r
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ pdata8bits = NULL;\r
+ pdata16bits = (uint16_t *) pData;\r
+ }\r
+ else\r
+ {\r
+ pdata8bits = pData;\r
+ pdata16bits = NULL;\r
+ }\r
+\r
+ /* as long as data have to be received */\r
+ while (huart->RxXferCount > 0U)\r
+ {\r
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if (pdata8bits == NULL)\r
+ {\r
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);\r
+ pdata16bits++;\r
+ }\r
+ else\r
+ {\r
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r
+ pdata8bits++;\r
+ }\r
+ huart->RxXferCount--;\r
+ }\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode.\r
+ * @param huart UART handle.\r
+ * @param pData Pointer to data buffer.\r
+ * @param Size Amount of data to be sent.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Tx process is not already ongoing */\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+ huart->TxISR = NULL;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ /* Configure Tx interrupt processing */\r
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+ {\r
+ /* Set the Tx ISR function pointer according to the data word length */\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ huart->TxISR = UART_TxISR_16BIT_FIFOEN;\r
+ }\r
+ else\r
+ {\r
+ huart->TxISR = UART_TxISR_8BIT_FIFOEN;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the TX FIFO threshold interrupt */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+ }\r
+ else\r
+ {\r
+ /* Set the Tx ISR function pointer according to the data word length */\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ huart->TxISR = UART_TxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ huart->TxISR = UART_TxISR_8BIT;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the Transmit Data Register Empty interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode.\r
+ * @param huart UART handle.\r
+ * @param pData Pointer to data buffer.\r
+ * @param Size Amount of data to be received.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Rx process is not already ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+ huart->RxXferCount = Size;\r
+ huart->RxISR = NULL;\r
+\r
+ /* Computation of UART mask to apply to RDR register */\r
+ UART_MASK_COMPUTATION(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Configure Rx interrupt processing*/\r
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))\r
+ {\r
+ /* Set the Rx ISR function pointer according to the data word length */\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;\r
+ }\r
+ else\r
+ {\r
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx ISR function pointer according to the data word length */\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ huart->RxISR = UART_RxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ huart->RxISR = UART_RxISR_8BIT;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode.\r
+ * @param huart UART handle.\r
+ * @param pData Pointer to data buffer.\r
+ * @param Size Amount of data to be sent.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Tx process is not already ongoing */\r
+ if (huart->gState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->gState = HAL_UART_STATE_BUSY_TX;\r
+\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r
+\r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ huart->hdmatx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the UART transmit DMA channel */\r
+ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Restore huart->gState to ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* Clear the TC flag in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode.\r
+ * @note When the UART parity is enabled (PCE = 1), the received data contain\r
+ * the parity bit (MSB position).\r
+ * @param huart UART handle.\r
+ * @param pData Pointer to data buffer.\r
+ * @param Size Amount of data to be received.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check that a Rx process is not already ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->RxState = HAL_UART_STATE_BUSY_RX;\r
+\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r
+\r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ huart->hdmarx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Set the DMA abort callback */\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA channel */\r
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Restore huart->gState to ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Parity Error Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the UART CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pause the DMA Transfer.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r
+{\r
+ const HAL_UART_StateTypeDef gstate = huart->gState;\r
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
+ (gstate == HAL_UART_STATE_BUSY_TX))\r
+ {\r
+ /* Disable the UART DMA Tx request */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
+ (rxstate == HAL_UART_STATE_BUSY_RX))\r
+ {\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the UART DMA Rx request */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the DMA Transfer.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the UART DMA Tx request */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);\r
+\r
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the UART DMA Rx request */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA Transfer.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /\r
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:\r
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r
+ the stream and the corresponding call back is executed. */\r
+\r
+ const HAL_UART_StateTypeDef gstate = huart->gState;\r
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
+\r
+ /* Stop UART DMA Tx request if ongoing */\r
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
+ (gstate == HAL_UART_STATE_BUSY_TX))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ UART_EndTxTransfer(huart);\r
+ }\r
+\r
+ /* Stop UART DMA Rx request if ongoing */\r
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
+ (rxstate == HAL_UART_STATE_BUSY_RX))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ UART_EndRxTransfer(huart);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing transfers (blocking mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx and Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset Tx and Rx transfer counters */\r
+ huart->TxXferCount = 0U;\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Discard the received data */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore huart->gState and huart->RxState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Reset Handle ErrorCode to No Error */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Transmit transfer (blocking mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset Tx transfer counter */\r
+ huart->TxXferCount = 0U;\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Receive transfer (blocking mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ huart->ErrorCode = HAL_UART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset Rx transfer counter */\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Discard the received data */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing transfers (Interrupt mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx and Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * - At abort completion, call user abort complete callback\r
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+ * considered as completed only when user abort complete callback is executed (not when exiting function).\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t abortcplt = 1U;\r
+\r
+ /* Disable interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));\r
+\r
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised\r
+ before any call to DMA Abort functions */\r
+ /* DMA Tx Handle is valid */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r
+ Otherwise, set it to NULL */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;\r
+ }\r
+ else\r
+ {\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+ }\r
+ }\r
+ /* DMA Rx Handle is valid */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r
+ Otherwise, set it to NULL */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;\r
+ }\r
+ else\r
+ {\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+ }\r
+ }\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ /* Disable DMA Tx at UART level */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* UART Tx DMA Abort callback has already been initialised :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
+ {\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+ }\r
+ else\r
+ {\r
+ abortcplt = 0U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* UART Rx DMA Abort callback has already been initialised :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+ {\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+ abortcplt = 1U;\r
+ }\r
+ else\r
+ {\r
+ abortcplt = 0U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */\r
+ if (abortcplt == 1U)\r
+ {\r
+ /* Reset Tx and Rx transfer counters */\r
+ huart->TxXferCount = 0U;\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Clear ISR function pointers */\r
+ huart->RxISR = NULL;\r
+ huart->TxISR = NULL;\r
+\r
+ /* Reset errorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Discard the received data */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore huart->gState and huart->RxState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort complete callback */\r
+ huart->AbortCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort complete callback */\r
+ HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Tx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * - At abort completion, call user abort complete callback\r
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+ * considered as completed only when user abort complete callback is executed (not when exiting function).\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+\r
+ /* Disable the UART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */\r
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Tx transfer counter */\r
+ huart->TxXferCount = 0U;\r
+\r
+ /* Clear TxISR function pointers */\r
+ huart->TxISR = NULL;\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Transmit Complete Callback */\r
+ huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Transmit Complete Callback */\r
+ HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Tx transfer counter */\r
+ huart->TxXferCount = 0U;\r
+\r
+ /* Clear TxISR function pointers */\r
+ huart->TxISR = NULL;\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Transmit Complete Callback */\r
+ huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Transmit Complete Callback */\r
+ HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing Receive transfer (Interrupt mode).\r
+ * @param huart UART handle.\r
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable UART Interrupts (Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * - At abort completion, call user abort complete callback\r
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+ * considered as completed only when user abort complete callback is executed (not when exiting function).\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback :\r
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Rx transfer counter */\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Clear RxISR function pointer */\r
+ huart->pRxBuffPtr = NULL;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Discard the received data */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Receive Complete Callback */\r
+ huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Receive Complete Callback */\r
+ HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset Rx transfer counter */\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Clear RxISR function pointer */\r
+ huart->pRxBuffPtr = NULL;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Receive Complete Callback */\r
+ huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Receive Complete Callback */\r
+ HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle UART interrupt request.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);\r
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);\r
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);\r
+\r
+ uint32_t errorflags;\r
+ uint32_t errorcode;\r
+\r
+ /* If no error occurs */\r
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r
+ if (errorflags == 0U)\r
+ {\r
+ /* UART in mode Receiver ---------------------------------------------------*/\r
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
+ {\r
+ if (huart->RxISR != NULL)\r
+ {\r
+ huart->RxISR(huart);\r
+ }\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* If some errors occur */\r
+ if ((errorflags != 0U)\r
+ && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)\r
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))\r
+ {\r
+ /* UART parity error interrupt occurred -------------------------------------*/\r
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))\r
+ {\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_PE;\r
+ }\r
+\r
+ /* UART frame error interrupt occurred --------------------------------------*/\r
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
+ {\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_FE;\r
+ }\r
+\r
+ /* UART noise error interrupt occurred --------------------------------------*/\r
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
+ {\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_NE;\r
+ }\r
+\r
+ /* UART Over-Run interrupt occurred -----------------------------------------*/\r
+ if (((isrflags & USART_ISR_ORE) != 0U)\r
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||\r
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))\r
+ {\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;\r
+ }\r
+\r
+ /* Call UART Error Call back function if need be --------------------------*/\r
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)\r
+ {\r
+ /* UART in mode Receiver ---------------------------------------------------*/\r
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
+ {\r
+ if (huart->RxISR != NULL)\r
+ {\r
+ huart->RxISR(huart);\r
+ }\r
+ }\r
+\r
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+ consider error as blocking */\r
+ errorcode = huart->ErrorCode;\r
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||\r
+ ((errorcode & HAL_UART_ERROR_ORE) != 0U))\r
+ {\r
+ /* Blocking error : transfer is aborted\r
+ Set the UART state ready to be able to start again the process,\r
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r
+ UART_EndRxTransfer(huart);\r
+\r
+ /* Disable the UART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the UART DMA Rx channel */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ /* Set the UART DMA Abort callback :\r
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\r
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Non Blocking error : transfer could go on.\r
+ Error is notified to user through user error callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ }\r
+ }\r
+ return;\r
+\r
+ } /* End if some error occurs */\r
+\r
+ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/\r
+ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))\r
+ {\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);\r
+\r
+ /* UART Rx state is not reset as a reception process might be ongoing.\r
+ If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Wakeup Callback */\r
+ huart->WakeupCallback(huart);\r
+#else\r
+ /* Call legacy weak Wakeup Callback */\r
+ HAL_UARTEx_WakeupCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ return;\r
+ }\r
+\r
+ /* UART in mode Transmitter ------------------------------------------------*/\r
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)\r
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)\r
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))\r
+ {\r
+ if (huart->TxISR != NULL)\r
+ {\r
+ huart->TxISR(huart);\r
+ }\r
+ return;\r
+ }\r
+\r
+ /* UART in mode Transmitter (transmission end) -----------------------------*/\r
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))\r
+ {\r
+ UART_EndTransmit_IT(huart);\r
+ return;\r
+ }\r
+\r
+ /* UART TX Fifo Empty occurred ----------------------------------------------*/\r
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))\r
+ {\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Fifo Empty Callback */\r
+ huart->TxFifoEmptyCallback(huart);\r
+#else\r
+ /* Call legacy weak Tx Fifo Empty Callback */\r
+ HAL_UARTEx_TxFifoEmptyCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ return;\r
+ }\r
+\r
+ /* UART RX Fifo Full occurred ----------------------------------------------*/\r
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))\r
+ {\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Fifo Full Callback */\r
+ huart->RxFifoFullCallback(huart);\r
+#else\r
+ /* Call legacy weak Rx Fifo Full Callback */\r
+ HAL_UARTEx_RxFifoFullCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART error callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_ErrorCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART Abort Complete callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART Abort Complete callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART Abort Receive Complete callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief UART control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the UART.\r
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode\r
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode\r
+ (+) UART_SetConfig() API configures the UART peripheral\r
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features\r
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization\r
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter\r
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver\r
+ (+) HAL_LIN_SendBreak() API transmits the break characters\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;\r
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_MME);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode\r
+ * as it may not have been in mute mode at this very moment).\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Enter UART mute mode (means UART actually enters mute mode).\r
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r
+{\r
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);\r
+}\r
+\r
+/**\r
+ * @brief Enable the UART transmitter and disable the UART receiver.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Clear TE and RE bits */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+\r
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the UART receiver and disable the UART transmitter.\r
+ * @param huart UART handle.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Clear TE and RE bits */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+\r
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Transmit break characters.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Send break characters */\r
+ __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
+ * @brief UART Peripheral State functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral State and Error functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to :\r
+ (+) Return the UART handle state.\r
+ (+) Return the UART handle error code\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the UART handle state.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART.\r
+ * @retval HAL state\r
+ */\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t temp1, temp2;\r
+ temp1 = huart->gState;\r
+ temp2 = huart->RxState;\r
+\r
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);\r
+}\r
+\r
+/**\r
+ * @brief Return the UART handle error code.\r
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART.\r
+ * @retval UART Error Code\r
+*/\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r
+{\r
+ return huart->ErrorCode;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Private_Functions UART Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the callbacks to their default values.\r
+ * @param huart UART handle.\r
+ * @retval none\r
+ */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)\r
+{\r
+ /* Init the UART Callback settings */\r
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\r
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */\r
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */\r
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */\r
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */\r
+\r
+}\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @brief Configure the UART peripheral.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpreg;\r
+ uint16_t brrtemp;\r
+ UART_ClockSourceTypeDef clocksource;\r
+ uint32_t usartdiv = 0x00000000U;\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ uint32_t lpuart_ker_ck_pres = 0x00000000U;\r
+ PLL2_ClocksTypeDef pll2_clocks;\r
+ PLL3_ClocksTypeDef pll3_clocks;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\r
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
+ if (UART_INSTANCE_LOWPOWER(huart))\r
+ {\r
+ assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));\r
+ }\r
+\r
+ assert_param(IS_UART_PARITY(huart->Init.Parity));\r
+ assert_param(IS_UART_MODE(huart->Init.Mode));\r
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\r
+ assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure\r
+ * the UART Word Length, Parity, Mode and oversampling:\r
+ * set the M bits according to huart->Init.WordLength value\r
+ * set PCE and PS bits according to huart->Init.Parity value\r
+ * set TE and RE bits according to huart->Init.Mode value\r
+ * set OVER8 bit according to huart->Init.OverSampling value */\r
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;\r
+ tmpreg |= (uint32_t)huart->FifoMode;\r
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR2 Configuration -----------------------*/\r
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according\r
+ * to huart->Init.StopBits value */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r
+\r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* Configure\r
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according\r
+ * to huart->Init.HwFlowCtl value\r
+ * - one-bit sampling method versus three samples' majority rule according\r
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */\r
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;\r
+\r
+ if (!(UART_INSTANCE_LOWPOWER(huart)))\r
+ {\r
+ tmpreg |= huart->Init.OneBitSampling;\r
+ }\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART PRESC Configuration -----------------------*/\r
+ /* Configure\r
+ * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */\r
+ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);\r
+\r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ UART_GETCLOCKSOURCE(huart, clocksource);\r
+\r
+ /* Check LPUART instance */\r
+ if (UART_INSTANCE_LOWPOWER(huart))\r
+ {\r
+ /* Retrieve frequency clock */\r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_D3PCLK1:\r
+ lpuart_ker_ck_pres = (HAL_RCCEx_GetD3PCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL2:\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ lpuart_ker_ck_pres = (pll2_clocks.PLL2_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL3:\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ lpuart_ker_ck_pres = (pll3_clocks.PLL3_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI:\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ lpuart_ker_ck_pres = ((uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+ }\r
+ else\r
+ {\r
+ lpuart_ker_ck_pres = ((uint32_t) HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+ }\r
+ break;\r
+ case UART_CLOCKSOURCE_CSI:\r
+ lpuart_ker_ck_pres = ((uint32_t)CSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_LSE:\r
+ lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ /* if proper clock source reported */\r
+ if (lpuart_ker_ck_pres != 0U)\r
+ {\r
+ /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */\r
+ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||\r
+ (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))\r
+ {\r
+ ret = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_D3PCLK1:\r
+ usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCCEx_GetD3PCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL2:\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL3:\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI:\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ usartdiv = (uint32_t)(UART_DIV_LPUART((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ }\r
+ else\r
+ {\r
+ usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ }\r
+ break;\r
+ case UART_CLOCKSOURCE_CSI:\r
+ usartdiv = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */\r
+ if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))\r
+ {\r
+ huart->Instance->BRR = usartdiv;\r
+ }\r
+ else\r
+ {\r
+ ret = HAL_ERROR;\r
+ }\r
+ } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */\r
+ } /* if (lpuart_ker_ck_pres != 0) */\r
+ }\r
+ /* Check UART Over Sampling to set Baud Rate Register */\r
+ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
+ {\r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_D2PCLK1:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_D2PCLK2:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL2:\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL3:\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI:\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ }\r
+ else\r
+ {\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ }\r
+ break;\r
+ case UART_CLOCKSOURCE_CSI:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ /* USARTDIV must be greater than or equal to 0d16 */\r
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))\r
+ {\r
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);\r
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r
+ huart->Instance->BRR = brrtemp;\r
+ }\r
+ else\r
+ {\r
+ ret = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_D2PCLK1:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_D2PCLK2:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL2:\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_PLL3:\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI:\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ }\r
+ else\r
+ {\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ }\r
+ break;\r
+ case UART_CLOCKSOURCE_CSI:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));\r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED:\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ /* USARTDIV must be greater than or equal to 0d16 */\r
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))\r
+ {\r
+ huart->Instance->BRR = usartdiv;\r
+ }\r
+ else\r
+ {\r
+ ret = HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Initialize the number of data to process during RX/TX ISR execution */\r
+ huart->NbTxDataToProcess = 1;\r
+ huart->NbRxDataToProcess = 1;\r
+\r
+ /* Clear ISR function pointers */\r
+ huart->RxISR = NULL;\r
+ huart->TxISR = NULL;\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Configure the UART peripheral advanced features.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check whether the set of advanced features to configure is properly set */\r
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));\r
+\r
+ /* if required, configure TX pin active level inversion */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);\r
+ }\r
+\r
+ /* if required, configure RX pin active level inversion */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);\r
+ }\r
+\r
+ /* if required, configure data inversion */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);\r
+ }\r
+\r
+ /* if required, configure RX/TX pins swap */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);\r
+ }\r
+\r
+ /* if required, configure RX overrun detection disabling */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r
+ {\r
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);\r
+ }\r
+\r
+ /* if required, configure DMA disabling on reception error */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);\r
+ }\r
+\r
+ /* if required, configure auto Baud rate detection scheme */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))\r
+ {\r
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));\r
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);\r
+ /* set auto Baudrate detection parameters if detection is enabled */\r
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);\r
+ }\r
+ }\r
+\r
+ /* if required, configure MSB first on communication line */\r
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Check the UART Idle State.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Initialize the UART ErrorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the Transmitter is enabled */\r
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+ {\r
+ /* Timeout occurred */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check if the Receiver is enabled */\r
+ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+ {\r
+ /* Timeout occurred */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Initialize the UART State */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle UART Communication Timeout.\r
+ * @param huart UART handle.\r
+ * @param Flag Specifies the UART flag to check\r
+ * @param Status Flag status (SET or RESET)\r
+ * @param Tickstart Tick start value\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+ /* Wait until flag is set */\r
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable TXEIE, TCIE, TXFT interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));\r
+\r
+ /* At end of Tx process, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+}\r
+\r
+\r
+/**\r
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Reset RxIsr function pointer */\r
+ huart->RxISR = NULL;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA UART transmit process complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ /* DMA Normal mode */\r
+ if (hdma->Init.Mode != DMA_CIRCULAR)\r
+ {\r
+ huart->TxXferCount = 0U;\r
+\r
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r
+ in the UART CR3 register */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+ }\r
+ /* DMA Circular mode */\r
+ else\r
+ {\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Tx complete callback*/\r
+ huart->TxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Tx complete callback*/\r
+ HAL_UART_TxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA UART transmit process half complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Tx Half complete callback*/\r
+ huart->TxHalfCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Tx Half complete callback*/\r
+ HAL_UART_TxHalfCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ /* DMA Normal mode */\r
+ if (hdma->Init.Mode != DMA_CIRCULAR)\r
+ {\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit\r
+ in the UART CR3 register */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* At end of Rx process, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+ }\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx complete callback*/\r
+ huart->RxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx complete callback*/\r
+ HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process half complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx Half complete callback*/\r
+ huart->RxHalfCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx Half complete callback*/\r
+ HAL_UART_RxHalfCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART communication error callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ const HAL_UART_StateTypeDef gstate = huart->gState;\r
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;\r
+\r
+ /* Stop UART DMA Tx request if ongoing */\r
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&\r
+ (gstate == HAL_UART_STATE_BUSY_TX))\r
+ {\r
+ huart->TxXferCount = 0U;\r
+ UART_EndTxTransfer(huart);\r
+ }\r
+\r
+ /* Stop UART DMA Rx request if ongoing */\r
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&\r
+ (rxstate == HAL_UART_STATE_BUSY_RX))\r
+ {\r
+ huart->RxXferCount = 0U;\r
+ UART_EndRxTransfer(huart);\r
+ }\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error\r
+ * (To be called at end of DMA Abort procedure following error occurrence).\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+ huart->RxXferCount = 0U;\r
+ huart->TxXferCount = 0U;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered error callback*/\r
+ huart->ErrorCallback(huart);\r
+#else\r
+ /*Call legacy weak error callback*/\r
+ HAL_UART_ErrorCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART Tx communication abort callback, when initiated by user\r
+ * (To be called at end of DMA Tx Abort procedure following user abort request).\r
+ * @note When this callback is executed, User Abort complete call back is called only if no\r
+ * Abort still ongoing for Rx DMA Handle.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ huart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Check if an Abort process is still ongoing */\r
+ if (huart->hdmarx != NULL)\r
+ {\r
+ if (huart->hdmarx->XferAbortCallback != NULL)\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+ huart->TxXferCount = 0U;\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Reset errorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Restore huart->gState and huart->RxState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort complete callback */\r
+ huart->AbortCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort complete callback */\r
+ HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA UART Rx communication abort callback, when initiated by user\r
+ * (To be called at end of DMA Rx Abort procedure following user abort request).\r
+ * @note When this callback is executed, User Abort complete call back is called only if no\r
+ * Abort still ongoing for Tx DMA Handle.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ huart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Check if an Abort process is still ongoing */\r
+ if (huart->hdmatx != NULL)\r
+ {\r
+ if (huart->hdmatx->XferAbortCallback != NULL)\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+ huart->TxXferCount = 0U;\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Reset errorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Discard the received data */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore huart->gState and huart->RxState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort complete callback */\r
+ huart->AbortCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort complete callback */\r
+ HAL_UART_AbortCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to\r
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)\r
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,\r
+ * and leads to user Tx Abort Complete callback execution).\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ huart->TxXferCount = 0U;\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Transmit Complete Callback */\r
+ huart->AbortTransmitCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Transmit Complete Callback */\r
+ HAL_UART_AbortTransmitCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to\r
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)\r
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,\r
+ * and leads to user Rx Abort Complete callback execution).\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ huart->RxXferCount = 0U;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);\r
+\r
+ /* Discard the received data */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Receive Complete Callback */\r
+ huart->AbortReceiveCpltCallback(huart);\r
+#else\r
+ /* Call legacy weak Abort Receive Complete Callback */\r
+ HAL_UART_AbortReceiveCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TX interrrupt handler for 7 or 8 bits data word length .\r
+ * @note Function is called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Transmit_IT().\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check that a Tx process is ongoing */\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ if (huart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Transmit Data Register Empty Interrupt */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+ }\r
+ else\r
+ {\r
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);\r
+ huart->pTxBuffPtr++;\r
+ huart->TxXferCount--;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief TX interrrupt handler for 9 bits data word length.\r
+ * @note Function is called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Transmit_IT().\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t *tmp;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ if (huart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Transmit Data Register Empty Interrupt */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint16_t *) huart->pTxBuffPtr;\r
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);\r
+ huart->pTxBuffPtr += 2U;\r
+ huart->TxXferCount--;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.\r
+ * @note Function is called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Transmit_IT().\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t nb_tx_data;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
+ {\r
+ if (huart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the TX FIFO threshold interrupt */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ break; /* force exit loop */\r
+ }\r
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)\r
+ {\r
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);\r
+ huart->pTxBuffPtr++;\r
+ huart->TxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.\r
+ * @note Function is called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Transmit_IT().\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t *tmp;\r
+ uint16_t nb_tx_data;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
+ {\r
+ if (huart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the TX FIFO threshold interrupt */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);\r
+\r
+ /* Enable the UART Transmit Complete Interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ break; /* force exit loop */\r
+ }\r
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)\r
+ {\r
+ tmp = (uint16_t *) huart->pTxBuffPtr;\r
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);\r
+ huart->pTxBuffPtr += 2U;\r
+ huart->TxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Wrap up transmission in non-blocking mode.\r
+ * @param huart pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval None\r
+ */\r
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ /* Disable the UART Transmit Complete Interrupt */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r
+\r
+ /* Tx process is ended, restore huart->gState to Ready */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Cleat TxISR function pointer */\r
+ huart->TxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Tx complete callback*/\r
+ huart->TxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Tx complete callback*/\r
+ HAL_UART_TxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief RX interrrupt handler for 7 or 8 bits data word length .\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t uhMask = huart->Mask;\r
+ uint16_t uhdata;\r
+\r
+ /* Check that a Rx process is ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);\r
+ huart->pRxBuffPtr++;\r
+ huart->RxXferCount--;\r
+\r
+ if (huart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Rx process is completed, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Clear RxISR function pointer */\r
+ huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx complete callback*/\r
+ huart->RxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx complete callback*/\r
+ HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RX interrrupt handler for 9 bits data word length .\r
+ * @note Function is called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Receive_IT()\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t *tmp;\r
+ uint16_t uhMask = huart->Mask;\r
+ uint16_t uhdata;\r
+\r
+ /* Check that a Rx process is ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+ tmp = (uint16_t *) huart->pRxBuffPtr ;\r
+ *tmp = (uint16_t)(uhdata & uhMask);\r
+ huart->pRxBuffPtr += 2U;\r
+ huart->RxXferCount--;\r
+\r
+ if (huart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Rx process is completed, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Clear RxISR function pointer */\r
+ huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx complete callback*/\r
+ huart->RxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx complete callback*/\r
+ HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.\r
+ * @note Function is called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Receive_IT()\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t uhMask = huart->Mask;\r
+ uint16_t uhdata;\r
+ uint16_t nb_rx_data;\r
+ uint16_t rxdatacount;\r
+\r
+ /* Check that a Rx process is ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
+ {\r
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);\r
+ huart->pRxBuffPtr++;\r
+ huart->RxXferCount--;\r
+\r
+ if (huart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+ /* Rx process is completed, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Clear RxISR function pointer */\r
+ huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx complete callback*/\r
+ huart->RxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx complete callback*/\r
+ HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+\r
+ /* When remaining number of bytes to receive is less than the RX FIFO\r
+ threshold, next incoming frames are processed as if FIFO mode was\r
+ disabled (i.e. one interrupt per received frame).\r
+ */\r
+ rxdatacount = huart->RxXferCount;\r
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))\r
+ {\r
+ /* Disable the UART RXFT interrupt*/\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
+\r
+ /* Update the RxISR function pointer */\r
+ huart->RxISR = UART_RxISR_8BIT;\r
+\r
+ /* Enable the UART Data Register Not Empty interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.\r
+ * @note Function is called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Receive_IT()\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t *tmp;\r
+ uint16_t uhMask = huart->Mask;\r
+ uint16_t uhdata;\r
+ uint16_t nb_rx_data;\r
+ uint16_t rxdatacount;\r
+\r
+ /* Check that a Rx process is ongoing */\r
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
+ {\r
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);\r
+ tmp = (uint16_t *) huart->pRxBuffPtr ;\r
+ *tmp = (uint16_t)(uhdata & uhMask);\r
+ huart->pRxBuffPtr += 2U;\r
+ huart->RxXferCount--;\r
+\r
+ if (huart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+ /* Rx process is completed, restore huart->RxState to Ready */\r
+ huart->RxState = HAL_UART_STATE_READY;\r
+\r
+ /* Clear RxISR function pointer */\r
+ huart->RxISR = NULL;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ /*Call registered Rx complete callback*/\r
+ huart->RxCpltCallback(huart);\r
+#else\r
+ /*Call legacy weak Rx complete callback*/\r
+ HAL_UART_RxCpltCallback(huart);\r
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+\r
+ /* When remaining number of bytes to receive is less than the RX FIFO\r
+ threshold, next incoming frames are processed as if FIFO mode was\r
+ disabled (i.e. one interrupt per received frame).\r
+ */\r
+ rxdatacount = huart->RxXferCount;\r
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))\r
+ {\r
+ /* Disable the UART RXFT interrupt*/\r
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);\r
+\r
+ /* Update the RxISR function pointer */\r
+ huart->RxISR = UART_RxISR_16BIT;\r
+\r
+ /* Enable the UART Data Register Not Empty interrupt */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_uart_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended UART HAL module driver.\r
+ * This file provides firmware functions to manage the following extended\r
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### UART peripheral extended features #####\r
+ ==============================================================================\r
+\r
+ (#) Declare a UART_HandleTypeDef handle structure.\r
+\r
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers\r
+ by calling the HAL_RS485Ex_Init() API.\r
+\r
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.\r
+\r
+ -@- When UART operates in FIFO mode, FIFO mode must be enabled prior\r
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be\r
+ configured prior starting RX/TX transfers.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UARTEx UARTEx\r
+ * @brief UART Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants\r
+ * @{\r
+ */\r
+/* UART RX FIFO depth */\r
+#define RX_FIFO_DEPTH 8U\r
+\r
+/* UART TX FIFO depth */\r
+#define TX_FIFO_DEPTH 8U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions\r
+ * @{\r
+ */\r
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);\r
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Extended Initialization and Configuration Functions\r
+ *\r
+@verbatim\r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r
+ in asynchronous mode.\r
+ (+) For the asynchronous mode the parameters below can be configured:\r
+ (++) Baud Rate\r
+ (++) Word Length\r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ (++) Hardware flow control\r
+ (++) Receiver/transmitter modes\r
+ (++) Over Sampling Method\r
+ (++) One-Bit Sampling Method\r
+ (+) For the asynchronous mode, the following advanced features can be configured as well:\r
+ (++) TX and/or RX pin level inversion\r
+ (++) data logical level inversion\r
+ (++) RX and TX pins swap\r
+ (++) RX overrun detection disabling\r
+ (++) DMA disabling on RX error\r
+ (++) MSB first on communication line\r
+ (++) auto Baud rate detection\r
+ [..]\r
+ The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration\r
+ procedures (details for the procedures are available in reference manual).\r
+\r
+@endverbatim\r
+\r
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
+ 8-bit or 9-bit), the possible UART formats are listed in the\r
+ following table.\r
+\r
+ Table 1. UART frame format.\r
+ +-----------------------------------------------------------------------+\r
+ | M1 bit | M0 bit | PCE bit | UART frame |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |\r
+ +-----------------------------------------------------------------------+\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the RS485 Driver enable feature according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle.\r
+ * @param huart UART handle.\r
+ * @param Polarity Select the driver enable polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high\r
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low\r
+ * @param AssertionTime Driver Enable assertion time:\r
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)\r
+ * signal and the beginning of the start bit. It is expressed in sample time\r
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)\r
+ * @param DeassertionTime Driver Enable deassertion time:\r
+ * 5-bit value defining the time between the end of the last stop bit, in a\r
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.\r
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the\r
+ * oversampling rate).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)\r
+{\r
+ uint32_t temp;\r
+\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Check the Driver Enable UART instance */\r
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));\r
+\r
+ /* Check the Driver Enable polarity */\r
+ assert_param(IS_UART_DE_POLARITY(Polarity));\r
+\r
+ /* Check the Driver Enable assertion time */\r
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));\r
+\r
+ /* Check the Driver Enable deassertion time */\r
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));\r
+\r
+ if (huart->gState == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\r
+ UART_InitCallbacksToDefault(huart);\r
+\r
+ if (huart->MspInitCallback == NULL)\r
+ {\r
+ huart->MspInitCallback = HAL_UART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ huart->MspInitCallback(huart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
+ HAL_UART_MspInit(huart);\r
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\r
+ }\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */\r
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);\r
+\r
+ /* Set the Driver Enable polarity */\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);\r
+\r
+ /* Set the Driver Enable assertion and deassertion times */\r
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);\r
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);\r
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions\r
+ * @brief Extended functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of Wakeup and FIFO mode related callback functions.\r
+\r
+ (#) Wakeup from Stop mode Callback:\r
+ (+) HAL_UARTEx_WakeupCallback()\r
+\r
+ (#) TX/RX Fifos Callbacks:\r
+ (+) HAL_UARTEx_RxFifoFullCallback()\r
+ (+) HAL_UARTEx_TxFifoEmptyCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART wakeup from Stop mode callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART RX Fifo full callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART TX Fifo empty callback.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(huart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Extended Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides the following functions:\r
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address\r
+ detection length to more than 4 bits for multiprocessor address mark wake up.\r
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode\r
+ trigger: address match, Start Bit detection or RXNE bit status.\r
+ (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode\r
+ (+) HAL_UARTEx_DisableStopMode() API disables the above functionality\r
+ (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode\r
+ (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode\r
+ (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold\r
+ (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief By default in multiprocessor mode, when the wake up method is set\r
+ * to address mark, the UART handles only 4-bit long addresses detection;\r
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit\r
+ * long).\r
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,\r
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.\r
+ * @param huart UART handle.\r
+ * @param AddressLength This parameter can be one of the following values:\r
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address\r
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if (huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the address length parameter */\r
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the address length */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Set Wakeup from Stop mode interrupt flag selection.\r
+ * @note It is the application responsibility to enable the interrupt used as\r
+ * usart_wkup interrupt source before entering low-power mode.\r
+ * @param huart UART handle.\r
+ * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_WAKEUP_ON_ADDRESS\r
+ * @arg @ref UART_WAKEUP_ON_STARTBIT\r
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tickstart;\r
+\r
+ /* check the wake-up from stop mode UART instance */\r
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));\r
+ /* check the wake-up selection parameter */\r
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the wake-up selection scheme */\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);\r
+\r
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)\r
+ {\r
+ UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until REACK flag is set */\r
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+ {\r
+ status = HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ /* Initialize the UART State */\r
+ huart->gState = HAL_UART_STATE_READY;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enable UART Stop Mode.\r
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ /* Set UESM bit */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_UESM);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable UART Stop Mode.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ /* Clear UESM bit */\r
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the FIFO mode.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Save actual UART configuration */\r
+ tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+ /* Disable UART */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Enable FIFO mode */\r
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);\r
+ huart->FifoMode = UART_FIFOMODE_ENABLE;\r
+\r
+ /* Restore UART configuration */\r
+ WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+ /* Determine the number of data to process during RX/TX ISR execution */\r
+ UARTEx_SetNbDataToProcess(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the FIFO mode.\r
+ * @param huart UART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Save actual UART configuration */\r
+ tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+ /* Disable UART */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Enable FIFO mode */\r
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);\r
+ huart->FifoMode = UART_FIFOMODE_DISABLE;\r
+\r
+ /* Restore UART configuration */\r
+ WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the TXFIFO threshold.\r
+ * @param huart UART handle.\r
+ * @param Threshold TX FIFO threshold value\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_8\r
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_4\r
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_2\r
+ * @arg @ref UART_TXFIFO_THRESHOLD_3_4\r
+ * @arg @ref UART_TXFIFO_THRESHOLD_7_8\r
+ * @arg @ref UART_TXFIFO_THRESHOLD_8_8\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+ assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Save actual UART configuration */\r
+ tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+ /* Disable UART */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Update TX threshold configuration */\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);\r
+\r
+ /* Determine the number of data to process during RX/TX ISR execution */\r
+ UARTEx_SetNbDataToProcess(huart);\r
+\r
+ /* Restore UART configuration */\r
+ WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the RXFIFO threshold.\r
+ * @param huart UART handle.\r
+ * @param Threshold RX FIFO threshold value\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_8\r
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_4\r
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_2\r
+ * @arg @ref UART_RXFIFO_THRESHOLD_3_4\r
+ * @arg @ref UART_RXFIFO_THRESHOLD_7_8\r
+ * @arg @ref UART_RXFIFO_THRESHOLD_8_8\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));\r
+ assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->gState = HAL_UART_STATE_BUSY;\r
+\r
+ /* Save actual UART configuration */\r
+ tmpcr1 = READ_REG(huart->Instance->CR1);\r
+\r
+ /* Disable UART */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Update RX threshold configuration */\r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);\r
+\r
+ /* Determine the number of data to process during RX/TX ISR execution */\r
+ UARTEx_SetNbDataToProcess(huart);\r
+\r
+ /* Restore UART configuration */\r
+ WRITE_REG(huart->Instance->CR1, tmpcr1);\r
+\r
+ huart->gState = HAL_UART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UARTEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.\r
+ * @param huart UART handle.\r
+ * @param WakeUpSelection UART wake up from stop mode parameters.\r
+ * @retval None\r
+ */\r
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)\r
+{\r
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));\r
+\r
+ /* Set the USART address length */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);\r
+\r
+ /* Set the USART address node */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));\r
+}\r
+\r
+/**\r
+ * @brief Calculate the number of data to process in RX/TX ISR.\r
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from\r
+ * the UART configuration registers.\r
+ * @param huart UART handle.\r
+ * @retval None\r
+ */\r
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)\r
+{\r
+ uint8_t rx_fifo_depth;\r
+ uint8_t tx_fifo_depth;\r
+ uint8_t rx_fifo_threshold;\r
+ uint8_t tx_fifo_threshold;\r
+ uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};\r
+ uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};\r
+\r
+ if (huart->FifoMode == UART_FIFOMODE_DISABLE)\r
+ {\r
+ huart->NbTxDataToProcess = 1U;\r
+ huart->NbRxDataToProcess = 1U;\r
+ }\r
+ else\r
+ {\r
+ rx_fifo_depth = RX_FIFO_DEPTH;\r
+ tx_fifo_depth = TX_FIFO_DEPTH;\r
+ rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);\r
+ tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);\r
+ huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];\r
+ huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_usart.c\r
+ * @author MCD Application Team\r
+ * @brief USART HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter\r
+ * Peripheral (USART).\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Error functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The USART HAL driver can be used as follows:\r
+\r
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).\r
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:\r
+ (++) Enable the USARTx interface clock.\r
+ (++) USART pins configuration:\r
+ (+++) Enable the clock for the USART GPIOs.\r
+ (+++) Configure these USART pins as alternate function pull-up.\r
+ (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),\r
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (++) USART interrupts handling:\r
+ -@@- The specific USART interrupts (Transmission complete interrupt,\r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.\r
+ (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()\r
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r
+ (+++) Configure the DMA Tx/Rx channel.\r
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.\r
+\r
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode\r
+ (Receiver/Transmitter) in the husart handle Init structure.\r
+\r
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:\r
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customized HAL_USART_MspInit(&husart) API.\r
+\r
+ [..]\r
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's\r
+ HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and\r
+ HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.\r
+\r
+ ##### Callback registration #####\r
+ ==================================\r
+\r
+ [..]\r
+ The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1\r
+ allows the user to configure dynamically the driver callbacks.\r
+\r
+ [..]\r
+ Use Function @ref HAL_USART_RegisterCallback() to register a user callback.\r
+ Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:\r
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.\r
+ (+) TxCpltCallback : Tx Complete Callback.\r
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.\r
+ (+) RxCpltCallback : Rx Complete Callback.\r
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.\r
+ (+) ErrorCallback : Error Callback.\r
+ (+) AbortCpltCallback : Abort Complete Callback.\r
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.\r
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.\r
+ (+) MspInitCallback : USART MspInit.\r
+ (+) MspDeInitCallback : USART MspDeInit.\r
+ This function takes as parameters the HAL peripheral handle, the Callback ID\r
+ and a pointer to the user callback function.\r
+\r
+ [..]\r
+ Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default\r
+ weak (surcharged) function.\r
+ @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,\r
+ and the Callback ID.\r
+ This function allows to reset following callbacks:\r
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.\r
+ (+) TxCpltCallback : Tx Complete Callback.\r
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.\r
+ (+) RxCpltCallback : Rx Complete Callback.\r
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.\r
+ (+) ErrorCallback : Error Callback.\r
+ (+) AbortCpltCallback : Abort Complete Callback.\r
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.\r
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.\r
+ (+) MspInitCallback : USART MspInit.\r
+ (+) MspDeInitCallback : USART MspDeInit.\r
+\r
+ [..]\r
+ By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET\r
+ all callbacks are set to the corresponding weak (surcharged) functions:\r
+ examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().\r
+ Exception done for MspInit and MspDeInit functions that are respectively\r
+ reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()\r
+ and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).\r
+ If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()\r
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).\r
+\r
+ [..]\r
+ Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.\r
+ Exception done MspInit/MspDeInit that can be registered/unregistered\r
+ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)\r
+ MspInit/DeInit callbacks can be used during the Init/DeInit.\r
+ In that case first register the MspInit/MspDeInit user callbacks\r
+ using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()\r
+ or @ref HAL_USART_Init() function.\r
+\r
+ [..]\r
+ When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or\r
+ not defined, the callback registration feature is not available\r
+ and weak (surcharged) callbacks are used.\r
+\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART USART\r
+ * @brief HAL USART Synchronous module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup USART_Private_Constants USART Private Constants\r
+ * @{\r
+ */\r
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */\r
+#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */\r
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \\r
+ USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */\r
+\r
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \\r
+ USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \\r
+ USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */\r
+\r
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */\r
+\r
+#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */\r
+#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup USART_Private_Functions\r
+ * @{\r
+ */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+static void USART_EndTransfer(USART_HandleTypeDef *husart);\r
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAError(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);\r
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);\r
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);\r
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);\r
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);\r
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);\r
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);\r
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);\r
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);\r
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Functions USART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USART\r
+ in asynchronous and in synchronous modes.\r
+ (+) For the asynchronous mode only these parameters can be configured:\r
+ (++) Baud Rate\r
+ (++) Word Length\r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ (++) USART polarity\r
+ (++) USART phase\r
+ (++) USART LastBit\r
+ (++) Receiver/transmitter modes\r
+\r
+ [..]\r
+ The HAL_USART_Init() function follows the USART synchronous configuration\r
+ procedure (details for the procedure are available in reference manual).\r
+\r
+@endverbatim\r
+\r
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
+ 8-bit or 9-bit), the possible USART formats are listed in the\r
+ following table.\r
+\r
+ Table 1. USART frame format.\r
+ +-----------------------------------------------------------------------+\r
+ | M1 bit | M0 bit | PCE bit | USART frame |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |\r
+ |---------|---------|-----------|---------------------------------------|\r
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |\r
+ +-----------------------------------------------------------------------+\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the USART mode according to the specified\r
+ * parameters in the USART_InitTypeDef and initialize the associated handle.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)\r
+{\r
+ /* Check the USART handle allocation */\r
+ if (husart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_INSTANCE(husart->Instance));\r
+\r
+ if (husart->State == HAL_USART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ husart->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ USART_InitCallbacksToDefault(husart);\r
+\r
+ if (husart->MspInitCallback == NULL)\r
+ {\r
+ husart->MspInitCallback = HAL_USART_MspInit;\r
+ }\r
+\r
+ /* Init the low level hardware */\r
+ husart->MspInitCallback(husart);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_USART_MspInit(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Set the Usart Communication parameters */\r
+ if (USART_SetConfig(husart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* In Synchronous mode, the following bits must be kept cleared:\r
+ - LINEN bit in the USART_CR2 register\r
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/\r
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;\r
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_USART_ENABLE(husart);\r
+\r
+ /* TEACK and/or REACK to check before moving husart->State to Ready */\r
+ return (USART_CheckIdleState(husart));\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the USART peripheral.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* Check the USART handle allocation */\r
+ if (husart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_INSTANCE(husart->Instance));\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ husart->Instance->CR1 = 0x0U;\r
+ husart->Instance->CR2 = 0x0U;\r
+ husart->Instance->CR3 = 0x0U;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ if (husart->MspDeInitCallback == NULL)\r
+ {\r
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ husart->MspDeInitCallback(husart);\r
+#else\r
+ /* DeInit the low level hardware */\r
+ HAL_USART_MspDeInit(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_RESET;\r
+\r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the USART MSP.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_MspInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the USART MSP.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_MspDeInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Register a User USART Callback\r
+ * To be used instead of the weak predefined callback\r
+ * @param husart usart handle\r
+ * @param CallbackID ID of the callback to be registered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+ * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
+ * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID\r
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+ * @param pCallback pointer to the Callback function\r
+ * @retval HAL status\r
++ */\r
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ /* Update the error code */\r
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :\r
+ husart->TxHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_TX_COMPLETE_CB_ID :\r
+ husart->TxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :\r
+ husart->RxHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_RX_COMPLETE_CB_ID :\r
+ husart->RxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :\r
+ husart->TxRxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_ERROR_CB_ID :\r
+ husart->ErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_ABORT_COMPLETE_CB_ID :\r
+ husart->AbortCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_RX_FIFO_FULL_CB_ID :\r
+ husart->RxFifoFullCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_TX_FIFO_EMPTY_CB_ID :\r
+ husart->TxFifoEmptyCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_MSPINIT_CB_ID :\r
+ husart->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_MSPDEINIT_CB_ID :\r
+ husart->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (husart->State == HAL_USART_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_USART_MSPINIT_CB_ID :\r
+ husart->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_USART_MSPDEINIT_CB_ID :\r
+ husart->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Unregister an UART Callback\r
+ * UART callaback is redirected to the weak predefined callback\r
+ * @param husart uart handle\r
+ * @param CallbackID ID of the callback to be unregistered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\r
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID\r
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\r
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID\r
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\r
+ * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID\r
+ * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID\r
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID\r
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if (HAL_USART_STATE_READY == husart->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :\r
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
+ break;\r
+\r
+ case HAL_USART_TX_COMPLETE_CB_ID :\r
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
+ break;\r
+\r
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :\r
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
+ break;\r
+\r
+ case HAL_USART_RX_COMPLETE_CB_ID :\r
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
+ break;\r
+\r
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :\r
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */\r
+ break;\r
+\r
+ case HAL_USART_ERROR_CB_ID :\r
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ break;\r
+\r
+ case HAL_USART_ABORT_COMPLETE_CB_ID :\r
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ break;\r
+\r
+ case HAL_USART_RX_FIFO_FULL_CB_ID :\r
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */\r
+ break;\r
+\r
+ case HAL_USART_TX_FIFO_EMPTY_CB_ID :\r
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */\r
+ break;\r
+\r
+ case HAL_USART_MSPINIT_CB_ID :\r
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */\r
+ break;\r
+\r
+ case HAL_USART_MSPDEINIT_CB_ID :\r
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (HAL_USART_STATE_RESET == husart->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_USART_MSPINIT_CB_ID :\r
+ husart->MspInitCallback = HAL_USART_MspInit;\r
+ break;\r
+\r
+ case HAL_USART_MSPDEINIT_CB_ID :\r
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return status;\r
+}\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions\r
+ * @brief USART Transmit and Receive functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous\r
+ data transfers.\r
+\r
+ [..] The USART supports master mode only: it cannot receive or send data related to an input\r
+ clock (SCLK is always an output).\r
+\r
+ [..]\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (++) No-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (++) HAL_USART_Transmit() in simplex mode\r
+ (++) HAL_USART_Receive() in full duplex receive only\r
+ (++) HAL_USART_TransmitReceive() in full duplex mode\r
+\r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (++) HAL_USART_Transmit_IT() in simplex mode\r
+ (++) HAL_USART_Receive_IT() in full duplex receive only\r
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode\r
+ (++) HAL_USART_IRQHandler()\r
+\r
+ (#) No-Blocking mode API's with DMA are :\r
+ (++) HAL_USART_Transmit_DMA() in simplex mode\r
+ (++) HAL_USART_Receive_DMA() in full duplex receive only\r
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode\r
+ (++) HAL_USART_DMAPause()\r
+ (++) HAL_USART_DMAResume()\r
+ (++) HAL_USART_DMAStop()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r
+ (++) HAL_USART_TxCpltCallback()\r
+ (++) HAL_USART_RxCpltCallback()\r
+ (++) HAL_USART_TxHalfCpltCallback()\r
+ (++) HAL_USART_RxHalfCpltCallback()\r
+ (++) HAL_USART_ErrorCallback()\r
+ (++) HAL_USART_TxRxCpltCallback()\r
+\r
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :\r
+ (++) HAL_USART_Abort()\r
+ (++) HAL_USART_Abort_IT()\r
+\r
+ (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:\r
+ (++) HAL_USART_AbortCpltCallback()\r
+\r
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.\r
+ Errors are handled as follows :\r
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is\r
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .\r
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,\r
+ and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.\r
+ If user wants to abort it, Abort services should be called by user.\r
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.\r
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.\r
+ Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Simplex send an amount of data in blocking mode.\r
+ * @param husart USART handle.\r
+ * @param pTxData Pointer to data buffer.\r
+ * @param Size Amount of data to be sent.\r
+ * @param Timeout Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint8_t *ptxdata8bits;\r
+ uint16_t *ptxdata16bits;\r
+ uint32_t tickstart;\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pTxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ ptxdata8bits = NULL;\r
+ ptxdata16bits = (uint16_t *) pTxData;\r
+ }\r
+ else\r
+ {\r
+ ptxdata8bits = pTxData;\r
+ ptxdata16bits = NULL;\r
+ }\r
+\r
+ /* Check the remaining data to be sent */\r
+ while (husart->TxXferCount > 0U)\r
+ {\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if (ptxdata8bits == NULL)\r
+ {\r
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);\r
+ ptxdata16bits++;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);\r
+ ptxdata8bits++;\r
+ }\r
+\r
+ husart->TxXferCount--;\r
+ }\r
+\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Clear Transmission Complete Flag */\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);\r
+\r
+ /* Clear overrun flag and discard the received data */\r
+ __HAL_USART_CLEAR_OREFLAG(husart);\r
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+\r
+ /* At end of Tx process, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode.\r
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.\r
+ * @param husart USART handle.\r
+ * @param pRxData Pointer to data buffer.\r
+ * @param Size Amount of data to be received.\r
+ * @param Timeout Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint8_t *prxdata8bits;\r
+ uint16_t *prxdata16bits;\r
+ uint16_t uhMask;\r
+ uint32_t tickstart;\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ USART_MASK_COMPUTATION(husart);\r
+ uhMask = husart->Mask;\r
+\r
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ prxdata8bits = NULL;\r
+ prxdata16bits = (uint16_t *) pRxData;\r
+ }\r
+ else\r
+ {\r
+ prxdata8bits = pRxData;\r
+ prxdata16bits = NULL;\r
+ }\r
+\r
+ /* as long as data have to be received */\r
+ while (husart->RxXferCount > 0U)\r
+ {\r
+ if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)\r
+ {\r
+ /* Wait until TXE flag is set to send dummy byte in order to generate the\r
+ * clock for the slave to send data.\r
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value\r
+ * can be written for all the cases. */\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);\r
+ }\r
+\r
+ /* Wait for RXNE Flag */\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ if (prxdata8bits == NULL)\r
+ {\r
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ prxdata16bits++;\r
+ }\r
+ else\r
+ {\r
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));\r
+ prxdata8bits++;\r
+ }\r
+\r
+ husart->RxXferCount--;\r
+\r
+ }\r
+\r
+ /* Clear SPI slave underrun flag and discard transmit data */\r
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)\r
+ {\r
+ __HAL_USART_CLEAR_UDRFLAG(husart);\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* At end of Rx process, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.\r
+ * @param husart USART handle.\r
+ * @param pTxData pointer to TX data buffer.\r
+ * @param pRxData pointer to RX data buffer.\r
+ * @param Size amount of data to be sent (same amount to be received).\r
+ * @param Timeout Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint8_t *prxdata8bits;\r
+ uint16_t *prxdata16bits;\r
+ uint8_t *ptxdata8bits;\r
+ uint16_t *ptxdata16bits;\r
+ uint16_t uhMask;\r
+ uint16_t rxdatacount;\r
+ uint32_t tickstart;\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ husart->RxXferSize = Size;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ USART_MASK_COMPUTATION(husart);\r
+ uhMask = husart->Mask;\r
+\r
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ prxdata8bits = NULL;\r
+ ptxdata8bits = NULL;\r
+ ptxdata16bits = (uint16_t *) pTxData;\r
+ prxdata16bits = (uint16_t *) pRxData;\r
+ }\r
+ else\r
+ {\r
+ prxdata8bits = pRxData;\r
+ ptxdata8bits = pTxData;\r
+ ptxdata16bits = NULL;\r
+ prxdata16bits = NULL;\r
+ }\r
+\r
+ if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))\r
+ {\r
+ /* Wait until TXE flag is set to send data */\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if (ptxdata8bits == NULL)\r
+ {\r
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);\r
+ ptxdata16bits++;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));\r
+ ptxdata8bits++;\r
+ }\r
+\r
+ husart->TxXferCount--;\r
+ }\r
+\r
+ /* Check the remain data to be sent */\r
+ /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */\r
+ rxdatacount = husart->RxXferCount;\r
+ while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))\r
+ {\r
+ if (husart->TxXferCount > 0U)\r
+ {\r
+ /* Wait until TXE flag is set to send data */\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if (ptxdata8bits == NULL)\r
+ {\r
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);\r
+ ptxdata16bits++;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));\r
+ ptxdata8bits++;\r
+ }\r
+\r
+ husart->TxXferCount--;\r
+ }\r
+\r
+ if (husart->RxXferCount > 0U)\r
+ {\r
+ /* Wait for RXNE Flag */\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ if (prxdata8bits == NULL)\r
+ {\r
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ prxdata16bits++;\r
+ }\r
+ else\r
+ {\r
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));\r
+ prxdata8bits++;\r
+ }\r
+\r
+ husart->RxXferCount--;\r
+ }\r
+ rxdatacount = husart->RxXferCount;\r
+ }\r
+\r
+ /* At end of TxRx process, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode.\r
+ * @param husart USART handle.\r
+ * @param pTxData pointer to data buffer.\r
+ * @param Size amount of data to be sent.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r
+{\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pTxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+ husart->TxISR = NULL;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)\r
+ are not managed by the USART Transmit Process to avoid the overrun interrupt\r
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"\r
+ to benefit for the frame error and noise interrupts the usart mode should be\r
+ configured only for transmit "USART_MODE_TX" */\r
+\r
+ /* Configure Tx interrupt processing */\r
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)\r
+ {\r
+ /* Set the Tx ISR function pointer according to the data word length */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ husart->TxISR = USART_TxISR_16BIT_FIFOEN;\r
+ }\r
+ else\r
+ {\r
+ husart->TxISR = USART_TxISR_8BIT_FIFOEN;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the TX FIFO threshold interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);\r
+ }\r
+ else\r
+ {\r
+ /* Set the Tx ISR function pointer according to the data word length */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ husart->TxISR = USART_TxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ husart->TxISR = USART_TxISR_8BIT;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Transmit Data Register Empty Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode.\r
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.\r
+ * @param husart USART handle.\r
+ * @param pRxData pointer to data buffer.\r
+ * @param Size amount of data to be received.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ uint16_t nb_dummy_data;\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+ husart->RxISR = NULL;\r
+\r
+ USART_MASK_COMPUTATION(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Configure Rx interrupt processing */\r
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))\r
+ {\r
+ /* Set the Rx ISR function pointer according to the data word length */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ husart->RxISR = USART_RxISR_16BIT_FIFOEN;\r
+ }\r
+ else\r
+ {\r
+ husart->RxISR = USART_RxISR_8BIT_FIFOEN;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx ISR function pointer according to the data word length */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ husart->RxISR = USART_RxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ husart->RxISR = USART_RxISR_8BIT;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);\r
+ }\r
+\r
+ if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)\r
+ {\r
+ /* Send dummy data in order to generate the clock for the Slave to send the next data.\r
+ When FIFO mode is disabled only one data must be transferred.\r
+ When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.\r
+ */\r
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))\r
+ {\r
+ for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)\r
+ {\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.\r
+ * @param husart USART handle.\r
+ * @param pTxData pointer to TX data buffer.\r
+ * @param pRxData pointer to RX data buffer.\r
+ * @param Size amount of data to be sent (same amount to be received).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ USART_MASK_COMPUTATION(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;\r
+\r
+ /* Configure TxRx interrupt processing */\r
+ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))\r
+ {\r
+ /* Set the Rx ISR function pointer according to the data word length */\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ husart->TxISR = USART_TxISR_16BIT_FIFOEN;\r
+ husart->RxISR = USART_RxISR_16BIT_FIFOEN;\r
+ }\r
+ else\r
+ {\r
+ husart->TxISR = USART_TxISR_8BIT_FIFOEN;\r
+ husart->RxISR = USART_RxISR_8BIT_FIFOEN;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the USART Parity Error interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the TX and RX FIFO Threshold interrupts */\r
+ SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));\r
+ }\r
+ else\r
+ {\r
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ husart->TxISR = USART_TxISR_16BIT;\r
+ husart->RxISR = USART_RxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ husart->TxISR = USART_TxISR_8BIT;\r
+ husart->RxISR = USART_RxISR_8BIT;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the USART Parity Error and USART Data Register not empty Interrupts */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);\r
+\r
+ /* Enable the USART Transmit Data Register Empty Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode.\r
+ * @param husart USART handle.\r
+ * @param pTxData pointer to data buffer.\r
+ * @param Size amount of data to be sent.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t *tmp;\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pTxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ /* Set the USART DMA transfer complete callback */\r
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ husart->hdmatx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART transmit DMA channel */\r
+ tmp = (uint32_t *)&pTxData;\r
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+ }\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ /* Clear the TC flag in the ICR register */\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Set error code to DMA */\r
+ husart->ErrorCode = HAL_USART_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Restore husart->State to ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode.\r
+ * @note When the USART parity is enabled (PCE = 1), the received data contain\r
+ * the parity bit (MSB position).\r
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.\r
+ * @param husart USART handle.\r
+ * @param pRxData pointer to data buffer.\r
+ * @param Size amount of data to be received.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t *tmp = (uint32_t *)&pRxData;\r
+\r
+ /* Check that a Rx process is not already ongoing */\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->pTxBuffPtr = pRxData;\r
+ husart->TxXferSize = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ /* Set the USART DMA Rx transfer complete callback */\r
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r
+\r
+ /* Set the USART DMA Rx transfer error callback */\r
+ husart->hdmarx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART receive DMA channel */\r
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);\r
+ }\r
+\r
+ if ((status == HAL_OK) &&\r
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))\r
+ {\r
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order\r
+ to generate in the non-blocking mode the clock to the slave device,\r
+ this mode isn't a simplex receive mode but a full-duplex receive mode */\r
+\r
+ /* Set the USART DMA Tx Complete and Error callback to Null */\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ husart->hdmatx->XferErrorCallback = NULL;\r
+ husart->hdmatx->XferHalfCpltCallback = NULL;\r
+ husart->hdmatx->XferCpltCallback = NULL;\r
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+ }\r
+ }\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Parity Error Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ status = HAL_DMA_Abort(husart->hdmarx);\r
+ }\r
+\r
+ /* No need to check on error code */\r
+ UNUSED(status);\r
+\r
+ /* Set error code to DMA */\r
+ husart->ErrorCode = HAL_USART_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Restore husart->State to ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.\r
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.\r
+ * @param husart USART handle.\r
+ * @param pTxData pointer to TX data buffer.\r
+ * @param pRxData pointer to RX data buffer.\r
+ * @param Size amount of data to be received/sent.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef status;\r
+ uint32_t *tmp;\r
+\r
+ if (husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;\r
+\r
+ if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))\r
+ {\r
+ /* Set the USART DMA Rx transfer complete callback */\r
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r
+\r
+ /* Set the USART DMA Tx transfer complete callback */\r
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r
+\r
+ /* Set the USART DMA Tx transfer error callback */\r
+ husart->hdmatx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Set the USART DMA Rx transfer error callback */\r
+ husart->hdmarx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART receive DMA channel */\r
+ tmp = (uint32_t *)&pRxData;\r
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);\r
+\r
+ /* Enable the USART transmit DMA channel */\r
+ if (status == HAL_OK)\r
+ {\r
+ tmp = (uint32_t *)&pTxData;\r
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ if (status == HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Parity Error Interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Clear the TC flag in the ICR register */\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ status = HAL_DMA_Abort(husart->hdmarx);\r
+ }\r
+\r
+ /* No need to check on error code */\r
+ UNUSED(status);\r
+\r
+ /* Set error code to DMA */\r
+ husart->ErrorCode = HAL_USART_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Restore husart->State to ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pause the DMA Transfer.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&\r
+ (state == HAL_USART_STATE_BUSY_TX))\r
+ {\r
+ /* Disable the USART DMA Tx request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ /* Disable the USART DMA Tx request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the USART DMA Rx request */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the DMA Transfer.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if (state == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the USART DMA Tx request */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);\r
+\r
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Enable the USART DMA Rx request before the DMA Tx request */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Enable the USART DMA Tx request */\r
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA Transfer.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /\r
+ HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:\r
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r
+ the stream and the corresponding call back is executed. */\r
+\r
+ /* Disable the USART Tx/Rx DMA requests */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the USART DMA tx channel */\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ husart->ErrorCode = HAL_USART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Abort the USART DMA rx channel */\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ husart->ErrorCode = HAL_USART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ USART_EndTransfer(husart);\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing transfers (blocking mode).\r
+ * @param husart USART handle.\r
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable USART Interrupts (Tx and Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)\r
+{\r
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));\r
+\r
+ /* Disable the USART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ /* Set the USART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ husart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ husart->ErrorCode = HAL_USART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Disable the USART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ /* Set the USART DMA Abort callback to Null.\r
+ No call back execution at end of DMA abort procedure */\r
+ husart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)\r
+ {\r
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\r
+ {\r
+ /* Set error code to DMA */\r
+ husart->ErrorCode = HAL_USART_ERROR_DMA;\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Reset Tx and Rx transfer counters */\r
+ husart->TxXferCount = 0U;\r
+ husart->RxXferCount = 0U;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Discard the received data */\r
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Reset Handle ErrorCode to No Error */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort ongoing transfers (Interrupt mode).\r
+ * @param husart USART handle.\r
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\r
+ * This procedure performs following operations :\r
+ * - Disable USART Interrupts (Tx and Rx)\r
+ * - Disable the DMA transfer in the peripheral register (if enabled)\r
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
+ * - Set handle State to READY\r
+ * - At abort completion, call user abort complete callback\r
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
+ * considered as completed only when user abort complete callback is executed (not when exiting function).\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t abortcplt = 1U;\r
+\r
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));\r
+\r
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised\r
+ before any call to DMA Abort functions */\r
+ /* DMA Tx Handle is valid */\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.\r
+ Otherwise, set it to NULL */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;\r
+ }\r
+ else\r
+ {\r
+ husart->hdmatx->XferAbortCallback = NULL;\r
+ }\r
+ }\r
+ /* DMA Rx Handle is valid */\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.\r
+ Otherwise, set it to NULL */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;\r
+ }\r
+ else\r
+ {\r
+ husart->hdmarx->XferAbortCallback = NULL;\r
+ }\r
+ }\r
+\r
+ /* Disable the USART DMA Tx request if enabled */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))\r
+ {\r
+ /* Disable DMA Tx at USART level */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ /* USART Tx DMA Abort callback has already been initialised :\r
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)\r
+ {\r
+ husart->hdmatx->XferAbortCallback = NULL;\r
+ }\r
+ else\r
+ {\r
+ abortcplt = 0U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Disable the USART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+\r
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ /* USART Rx DMA Abort callback has already been initialised :\r
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)\r
+ {\r
+ husart->hdmarx->XferAbortCallback = NULL;\r
+ abortcplt = 1U;\r
+ }\r
+ else\r
+ {\r
+ abortcplt = 0U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */\r
+ if (abortcplt == 1U)\r
+ {\r
+ /* Reset Tx and Rx transfer counters */\r
+ husart->TxXferCount = 0U;\r
+ husart->RxXferCount = 0U;\r
+\r
+ /* Reset errorCode */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);\r
+\r
+ /* Flush the whole TX FIFO (if needed) */\r
+ if (husart->FifoMode == USART_FIFOMODE_ENABLE)\r
+ {\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Discard the received data */\r
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* As no DMA to be aborted, call directly user Abort complete callback */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Complete Callback */\r
+ husart->AbortCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Abort Complete Callback */\r
+ HAL_USART_AbortCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handle USART interrupt request.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t isrflags = READ_REG(husart->Instance->ISR);\r
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);\r
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);\r
+\r
+ uint32_t errorflags;\r
+ uint32_t errorcode;\r
+\r
+ /* If no error occurs */\r
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));\r
+ if (errorflags == 0U)\r
+ {\r
+ /* USART in mode Receiver ---------------------------------------------------*/\r
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
+ {\r
+ if (husart->RxISR != NULL)\r
+ {\r
+ husart->RxISR(husart);\r
+ }\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* If some errors occur */\r
+ if ((errorflags != 0U)\r
+ && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)\r
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))\r
+ {\r
+ /* USART parity error interrupt occurred -------------------------------------*/\r
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);\r
+\r
+ husart->ErrorCode |= HAL_USART_ERROR_PE;\r
+ }\r
+\r
+ /* USART frame error interrupt occurred --------------------------------------*/\r
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);\r
+\r
+ husart->ErrorCode |= HAL_USART_ERROR_FE;\r
+ }\r
+\r
+ /* USART noise error interrupt occurred --------------------------------------*/\r
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);\r
+\r
+ husart->ErrorCode |= HAL_USART_ERROR_NE;\r
+ }\r
+\r
+ /* USART Over-Run interrupt occurred -----------------------------------------*/\r
+ if (((isrflags & USART_ISR_ORE) != 0U)\r
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||\r
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r
+\r
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;\r
+ }\r
+\r
+ /* USART SPI slave underrun error interrupt occurred -------------------------*/\r
+ if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))\r
+ {\r
+ /* Ignore SPI slave underrun errors when reception is going on */\r
+ if (husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ __HAL_USART_CLEAR_UDRFLAG(husart);\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ __HAL_USART_CLEAR_UDRFLAG(husart);\r
+ husart->ErrorCode |= HAL_USART_ERROR_UDR;\r
+ }\r
+ }\r
+\r
+ /* Call USART Error Call back function if need be --------------------------*/\r
+ if (husart->ErrorCode != HAL_USART_ERROR_NONE)\r
+ {\r
+ /* USART in mode Receiver ---------------------------------------------------*/\r
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)\r
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)\r
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))\r
+ {\r
+ if (husart->RxISR != NULL)\r
+ {\r
+ husart->RxISR(husart);\r
+ }\r
+ }\r
+\r
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r
+ consider error as blocking */\r
+ errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;\r
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||\r
+ (errorcode != 0U))\r
+ {\r
+ /* Blocking error : transfer is aborted\r
+ Set the USART state ready to be able to start again the process,\r
+ Disable Interrupts, and disable DMA requests, if ongoing */\r
+ USART_EndTransfer(husart);\r
+\r
+ /* Disable the USART DMA Rx request if enabled */\r
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r
+ {\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);\r
+\r
+ /* Abort the USART DMA Tx channel */\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ /* Set the USART Tx DMA Abort callback to NULL : no callback\r
+ executed at end of DMA abort procedure */\r
+ husart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Abort DMA TX */\r
+ (void)HAL_DMA_Abort_IT(husart->hdmatx);\r
+ }\r
+\r
+ /* Abort the USART DMA Rx channel */\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ /* Set the USART Rx DMA Abort callback :\r
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */\r
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */\r
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Error Callback */\r
+ husart->ErrorCallback(husart);\r
+#else\r
+ /* Call legacy weak Error Callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call user error callback */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Error Callback */\r
+ husart->ErrorCallback(husart);\r
+#else\r
+ /* Call legacy weak Error Callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Non Blocking error : transfer could go on.\r
+ Error is notified to user through user error callback */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Error Callback */\r
+ husart->ErrorCallback(husart);\r
+#else\r
+ /* Call legacy weak Error Callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ }\r
+ }\r
+ return;\r
+\r
+ } /* End if some error occurs */\r
+\r
+\r
+ /* USART in mode Transmitter ------------------------------------------------*/\r
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)\r
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)\r
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))\r
+ {\r
+ if (husart->TxISR != NULL)\r
+ {\r
+ husart->TxISR(husart);\r
+ }\r
+ return;\r
+ }\r
+\r
+ /* USART in mode Transmitter (transmission end) -----------------------------*/\r
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))\r
+ {\r
+ USART_EndTransmit_IT(husart);\r
+ return;\r
+ }\r
+\r
+ /* USART TX Fifo Empty occurred ----------------------------------------------*/\r
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))\r
+ {\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Fifo Empty Callback */\r
+ husart->TxFifoEmptyCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Fifo Empty Callback */\r
+ HAL_USARTEx_TxFifoEmptyCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ return;\r
+ }\r
+\r
+ /* USART RX Fifo Full occurred ----------------------------------------------*/\r
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))\r
+ {\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Fifo Full Callback */\r
+ husart->RxFifoFullCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Fifo Full Callback */\r
+ HAL_USARTEx_RxFifoFullCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_USART_RxCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief USART error callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_ErrorCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief USART Abort Complete callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions\r
+ * @brief USART Peripheral State and Error functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral State and Error functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to :\r
+ (+) Return the USART handle state\r
+ (+) Return the USART handle error code\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Return the USART handle state.\r
+ * @param husart pointer to a USART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART.\r
+ * @retval USART handle state\r
+ */\r
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)\r
+{\r
+ return husart->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the USART error code.\r
+ * @param husart pointer to a USART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART.\r
+ * @retval USART handle Error Code\r
+ */\r
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)\r
+{\r
+ return husart->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Functions USART Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the callbacks to their default values.\r
+ * @param husart USART handle.\r
+ * @retval none\r
+ */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)\r
+{\r
+ /* Init the USART Callback settings */\r
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */\r
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */\r
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */\r
+}\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+static void USART_EndTransfer(USART_HandleTypeDef *husart)\r
+{\r
+ /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));\r
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));\r
+\r
+ /* At end of process, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief DMA USART transmit process complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ /* DMA Normal mode */\r
+ if (hdma->Init.Mode != DMA_CIRCULAR)\r
+ {\r
+ husart->TxXferCount = 0U;\r
+\r
+ if (husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r
+ in the USART CR3 register */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
+ }\r
+ }\r
+ /* DMA Circular mode */\r
+ else\r
+ {\r
+ if (husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Complete Callback */\r
+ husart->TxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Complete Callback */\r
+ HAL_USART_TxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA USART transmit process half complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Half Complete Callback */\r
+ husart->TxHalfCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Half Complete Callback */\r
+ HAL_USART_TxHalfCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA USART receive process complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ /* DMA Normal mode */\r
+ if (hdma->Init.Mode != DMA_CIRCULAR)\r
+ {\r
+ husart->RxXferCount = 0U;\r
+\r
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit\r
+ in USART CR3 register */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r
+ /* similarly, disable the DMA TX transfer that was started to provide the\r
+ clock to the slave device */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r
+\r
+ if (husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Complete Callback */\r
+ husart->RxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Complete Callback */\r
+ HAL_USART_RxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r
+ else\r
+ {\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Rx Complete Callback */\r
+ husart->TxRxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Rx Complete Callback */\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ husart->State = HAL_USART_STATE_READY;\r
+ }\r
+ /* DMA circular mode */\r
+ else\r
+ {\r
+ if (husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Complete Callback */\r
+ husart->RxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Complete Callback */\r
+ HAL_USART_RxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r
+ else\r
+ {\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Rx Complete Callback */\r
+ husart->TxRxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Rx Complete Callback */\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA USART receive process half complete callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Half Complete Callback */\r
+ husart->RxHalfCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Half Complete Callback */\r
+ HAL_USART_RxHalfCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA USART communication error callback.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ husart->RxXferCount = 0U;\r
+ husart->TxXferCount = 0U;\r
+ USART_EndTransfer(husart);\r
+\r
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Error Callback */\r
+ husart->ErrorCallback(husart);\r
+#else\r
+ /* Call legacy weak Error Callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error\r
+ * (To be called at end of DMA Abort procedure following error occurrence).\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+ husart->RxXferCount = 0U;\r
+ husart->TxXferCount = 0U;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Error Callback */\r
+ husart->ErrorCallback(husart);\r
+#else\r
+ /* Call legacy weak Error Callback */\r
+ HAL_USART_ErrorCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief DMA USART Tx communication abort callback, when initiated by user\r
+ * (To be called at end of DMA Tx Abort procedure following user abort request).\r
+ * @note When this callback is executed, User Abort complete call back is called only if no\r
+ * Abort still ongoing for Rx DMA Handle.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ husart->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Check if an Abort process is still ongoing */\r
+ if (husart->hdmarx != NULL)\r
+ {\r
+ if (husart->hdmarx->XferAbortCallback != NULL)\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+ husart->TxXferCount = 0U;\r
+ husart->RxXferCount = 0U;\r
+\r
+ /* Reset errorCode */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);\r
+\r
+ /* Restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Complete Callback */\r
+ husart->AbortCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Abort Complete Callback */\r
+ HAL_USART_AbortCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA USART Rx communication abort callback, when initiated by user\r
+ * (To be called at end of DMA Rx Abort procedure following user abort request).\r
+ * @note When this callback is executed, User Abort complete call back is called only if no\r
+ * Abort still ongoing for Tx DMA Handle.\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);\r
+\r
+ husart->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Check if an Abort process is still ongoing */\r
+ if (husart->hdmatx != NULL)\r
+ {\r
+ if (husart->hdmatx->XferAbortCallback != NULL)\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\r
+ husart->TxXferCount = 0U;\r
+ husart->RxXferCount = 0U;\r
+\r
+ /* Reset errorCode */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+\r
+ /* Clear the Error flags in the ICR register */\r
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);\r
+\r
+ /* Restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Call user Abort complete callback */\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Abort Complete Callback */\r
+ husart->AbortCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Abort Complete Callback */\r
+ HAL_USART_AbortCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Handle USART Communication Timeout.\r
+ * @param husart USART handle.\r
+ * @param Flag Specifies the USART flag to check.\r
+ * @param Status the Flag status (SET or RESET).\r
+ * @param Tickstart Tick start value\r
+ * @param Timeout timeout duration.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r
+{\r
+ /* Wait until flag is set */\r
+ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the USART peripheral.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tmpreg;\r
+ USART_ClockSourceTypeDef clocksource;\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ uint16_t brrtemp;\r
+ uint32_t usartdiv = 0x00000000;\r
+ PLL2_ClocksTypeDef pll2_clocks;\r
+ PLL3_ClocksTypeDef pll3_clocks;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));\r
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));\r
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));\r
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));\r
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));\r
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));\r
+ assert_param(IS_USART_PARITY(husart->Init.Parity));\r
+ assert_param(IS_USART_MODE(husart->Init.Mode));\r
+ assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Clear M, PCE, PS, TE and RE bits and configure\r
+ * the USART Word Length, Parity and Mode:\r
+ * set the M bits according to husart->Init.WordLength value\r
+ * set PCE and PS bits according to husart->Init.Parity value\r
+ * set TE and RE bits according to husart->Init.Mode value\r
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */\r
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;\r
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
+\r
+ /*---------------------------- USART CR2 Configuration ---------------------*/\r
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:\r
+ * set CPOL bit according to husart->Init.CLKPolarity value\r
+ * set CPHA bit according to husart->Init.CLKPhase value\r
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)\r
+ * set STOP[13:12] bits according to husart->Init.StopBits value */\r
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE);\r
+ tmpreg |= (uint32_t)husart->Init.CLKLastBit;\r
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);\r
+ tmpreg |= (uint32_t)husart->Init.StopBits;\r
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART PRESC Configuration -----------------------*/\r
+ /* Configure\r
+ * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */\r
+ MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);\r
+\r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */\r
+ USART_GETCLOCKSOURCE(husart, clocksource);\r
+\r
+ switch (clocksource)\r
+ {\r
+ case USART_CLOCKSOURCE_D2PCLK1:\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ break;\r
+ case USART_CLOCKSOURCE_D2PCLK2:\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ break;\r
+ case USART_CLOCKSOURCE_PLL2:\r
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ break;\r
+ case USART_CLOCKSOURCE_PLL3:\r
+ HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ break;\r
+ case USART_CLOCKSOURCE_HSI:\r
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)\r
+ {\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ }\r
+ else\r
+ {\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ }\r
+ break;\r
+ case USART_CLOCKSOURCE_CSI:\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(CSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ break;\r
+ case USART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));\r
+ break;\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */\r
+ if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))\r
+ {\r
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);\r
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r
+ husart->Instance->BRR = brrtemp;\r
+ }\r
+ else\r
+ {\r
+ ret = HAL_ERROR;\r
+ }\r
+\r
+ /* Initialize the number of data to process during RX/TX ISR execution */\r
+ husart->NbTxDataToProcess = 1U;\r
+ husart->NbRxDataToProcess = 1U;\r
+\r
+ /* Clear ISR function pointers */\r
+ husart->RxISR = NULL;\r
+ husart->TxISR = NULL;\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Check the USART Idle State.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Initialize the USART ErrorCode */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+\r
+ /* Init tickstart for timeout managment*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the Transmitter is enabled */\r
+ if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Timeout occurred */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Timeout occurred */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Initialize the USART state*/\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Simplex send an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Transmit_IT().\r
+ * @note The USART errors are not managed to avoid the overrun error.\r
+ * @note ISR function executed when FIFO mode is disabled and when the\r
+ * data word length is less than 9 bits long.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if ((state == HAL_USART_STATE_BUSY_TX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ if (husart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the USART Transmit data register empty interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);\r
+ husart->pTxBuffPtr++;\r
+ husart->TxXferCount--;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Simplex send an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Transmit_IT().\r
+ * @note The USART errors are not managed to avoid the overrun error.\r
+ * @note ISR function executed when FIFO mode is disabled and when the\r
+ * data word length is 9 bits long.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+ uint16_t *tmp;\r
+\r
+ if ((state == HAL_USART_STATE_BUSY_TX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ if (husart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the USART Transmit data register empty interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint16_t *) husart->pTxBuffPtr;\r
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);\r
+ husart->pTxBuffPtr += 2U;\r
+ husart->TxXferCount--;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Simplex send an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Transmit_IT().\r
+ * @note The USART errors are not managed to avoid the overrun error.\r
+ * @note ISR function executed when FIFO mode is enabled and when the\r
+ * data word length is less than 9 bits long.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+ uint16_t nb_tx_data;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if ((state == HAL_USART_STATE_BUSY_TX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
+ {\r
+ if (husart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the TX FIFO threshold interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
+\r
+ break; /* force exit loop */\r
+ }\r
+ else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);\r
+ husart->pTxBuffPtr++;\r
+ husart->TxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Simplex send an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Transmit_IT().\r
+ * @note The USART errors are not managed to avoid the overrun error.\r
+ * @note ISR function executed when FIFO mode is enabled and when the\r
+ * data word length is 9 bits long.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+ uint16_t *tmp;\r
+ uint16_t nb_tx_data;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if ((state == HAL_USART_STATE_BUSY_TX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)\r
+ {\r
+ if (husart->TxXferCount == 0U)\r
+ {\r
+ /* Disable the TX FIFO threshold interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);\r
+\r
+ /* Enable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r
+\r
+ break; /* force exit loop */\r
+ }\r
+ else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)\r
+ {\r
+ tmp = (uint16_t *) husart->pTxBuffPtr;\r
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);\r
+ husart->pTxBuffPtr += 2U;\r
+ husart->TxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Wraps up transmission in non-blocking mode.\r
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART module.\r
+ * @retval None\r
+ */\r
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)\r
+{\r
+ /* Disable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
+\r
+ /* Clear TxISR function pointer */\r
+ husart->TxISR = NULL;\r
+\r
+ if (husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Clear overrun flag and discard the received data */\r
+ __HAL_USART_CLEAR_OREFLAG(husart);\r
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);\r
+\r
+ /* Tx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Complete Callback */\r
+ husart->TxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Complete Callback */\r
+ HAL_USART_TxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else if (husart->RxXferCount == 0U)\r
+ {\r
+ /* TxRx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Rx Complete Callback */\r
+ husart->TxRxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Rx Complete Callback */\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Simplex receive an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Receive_IT().\r
+ * @note ISR function executed when FIFO mode is disabled and when the\r
+ * data word length is less than 9 bits long.\r
+ * @param husart USART handle\r
+ * @retval None\r
+ */\r
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+ uint16_t txdatacount;\r
+ uint16_t uhMask = husart->Mask;\r
+ uint32_t txftie;\r
+\r
+ if ((state == HAL_USART_STATE_BUSY_RX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ husart->pRxBuffPtr++;\r
+ husart->RxXferCount--;\r
+\r
+ if (husart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Clear RxISR function pointer */\r
+ husart->RxISR = NULL;\r
+\r
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */\r
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);\r
+ txdatacount = husart->TxXferCount;\r
+\r
+ if (state == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear SPI slave underrun flag and discard transmit data */\r
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)\r
+ {\r
+ __HAL_USART_CLEAR_UDRFLAG(husart);\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Rx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Complete Callback */\r
+ husart->RxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Complete Callback */\r
+ HAL_USART_RxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&\r
+ (txftie != USART_CR3_TXFTIE) &&\r
+ (txdatacount == 0U))\r
+ {\r
+ /* TxRx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Rx Complete Callback */\r
+ husart->TxRxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Rx Complete Callback */\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&\r
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))\r
+ {\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Simplex receive an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Receive_IT().\r
+ * @note ISR function executed when FIFO mode is disabled and when the\r
+ * data word length is 9 bits long.\r
+ * @param husart USART handle\r
+ * @retval None\r
+ */\r
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)\r
+{\r
+ const HAL_USART_StateTypeDef state = husart->State;\r
+ uint16_t txdatacount;\r
+ uint16_t *tmp;\r
+ uint16_t uhMask = husart->Mask;\r
+ uint32_t txftie;\r
+\r
+ if ((state == HAL_USART_STATE_BUSY_RX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ tmp = (uint16_t *) husart->pRxBuffPtr;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ husart->pRxBuffPtr += 2U;\r
+ husart->RxXferCount--;\r
+\r
+ if (husart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/\r
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r
+\r
+ /* Clear RxISR function pointer */\r
+ husart->RxISR = NULL;\r
+\r
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */\r
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);\r
+ txdatacount = husart->TxXferCount;\r
+\r
+ if (state == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear SPI slave underrun flag and discard transmit data */\r
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)\r
+ {\r
+ __HAL_USART_CLEAR_UDRFLAG(husart);\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Rx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Complete Callback */\r
+ husart->RxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Complete Callback */\r
+ HAL_USART_RxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&\r
+ (txftie != USART_CR3_TXFTIE) &&\r
+ (txdatacount == 0U))\r
+ {\r
+ /* TxRx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Rx Complete Callback */\r
+ husart->TxRxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Rx Complete Callback */\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&\r
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))\r
+ {\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Simplex receive an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Receive_IT().\r
+ * @note ISR function executed when FIFO mode is enabled and when the\r
+ * data word length is less than 9 bits long.\r
+ * @param husart USART handle\r
+ * @retval None\r
+ */\r
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)\r
+{\r
+ HAL_USART_StateTypeDef state = husart->State;\r
+ uint16_t txdatacount;\r
+ uint16_t rxdatacount;\r
+ uint16_t uhMask = husart->Mask;\r
+ uint16_t nb_rx_data;\r
+ uint32_t txftie;\r
+\r
+ /* Check that a Rx process is ongoing */\r
+ if ((state == HAL_USART_STATE_BUSY_RX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
+ {\r
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)\r
+ {\r
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));\r
+ husart->pRxBuffPtr++;\r
+ husart->RxXferCount--;\r
+\r
+ if (husart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the USART Parity Error Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+ /* Clear RxISR function pointer */\r
+ husart->RxISR = NULL;\r
+\r
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */\r
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);\r
+ txdatacount = husart->TxXferCount;\r
+\r
+ if (state == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear SPI slave underrun flag and discard transmit data */\r
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)\r
+ {\r
+ __HAL_USART_CLEAR_UDRFLAG(husart);\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Rx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ state = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Complete Callback */\r
+ husart->RxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Complete Callback */\r
+ HAL_USART_RxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&\r
+ (txftie != USART_CR3_TXFTIE) &&\r
+ (txdatacount == 0U))\r
+ {\r
+ /* TxRx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ state = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Rx Complete Callback */\r
+ husart->TxRxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Rx Complete Callback */\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&\r
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))\r
+ {\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* When remaining number of bytes to receive is less than the RX FIFO\r
+ threshold, next incoming frames are processed as if FIFO mode was\r
+ disabled (i.e. one interrupt per received frame).\r
+ */\r
+ rxdatacount = husart->RxXferCount;\r
+ if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))\r
+ {\r
+ /* Disable the USART RXFT interrupt*/\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);\r
+\r
+ /* Update the RxISR function pointer */\r
+ husart->RxISR = USART_RxISR_8BIT;\r
+\r
+ /* Enable the USART Data Register Not Empty interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
+\r
+ if ((husart->TxXferCount == 0U) &&\r
+ (state == HAL_USART_STATE_BUSY_TX_RX) &&\r
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))\r
+ {\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Simplex receive an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Receive_IT().\r
+ * @note ISR function executed when FIFO mode is enabled and when the\r
+ * data word length is 9 bits long.\r
+ * @param husart USART handle\r
+ * @retval None\r
+ */\r
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)\r
+{\r
+ HAL_USART_StateTypeDef state = husart->State;\r
+ uint16_t txdatacount;\r
+ uint16_t rxdatacount;\r
+ uint16_t *tmp;\r
+ uint16_t uhMask = husart->Mask;\r
+ uint16_t nb_rx_data;\r
+ uint32_t txftie;\r
+\r
+ /* Check that a Tx process is ongoing */\r
+ if ((state == HAL_USART_STATE_BUSY_RX) ||\r
+ (state == HAL_USART_STATE_BUSY_TX_RX))\r
+ {\r
+ for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)\r
+ {\r
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)\r
+ {\r
+ tmp = (uint16_t *) husart->pRxBuffPtr;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ husart->pRxBuffPtr += 2U;\r
+ husart->RxXferCount--;\r
+\r
+ if (husart->RxXferCount == 0U)\r
+ {\r
+ /* Disable the USART Parity Error Interrupt */\r
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */\r
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));\r
+\r
+ /* Clear RxISR function pointer */\r
+ husart->RxISR = NULL;\r
+\r
+ /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */\r
+ txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);\r
+ txdatacount = husart->TxXferCount;\r
+\r
+ if (state == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Clear SPI slave underrun flag and discard transmit data */\r
+ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)\r
+ {\r
+ __HAL_USART_CLEAR_UDRFLAG(husart);\r
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);\r
+ }\r
+\r
+ /* Rx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ state = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Rx Complete Callback */\r
+ husart->RxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Rx Complete Callback */\r
+ HAL_USART_RxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&\r
+ (txftie != USART_CR3_TXFTIE) &&\r
+ (txdatacount == 0U))\r
+ {\r
+ /* TxRx process is completed, restore husart->State to Ready */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ state = HAL_USART_STATE_READY;\r
+\r
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)\r
+ /* Call registered Tx Rx Complete Callback */\r
+ husart->TxRxCpltCallback(husart);\r
+#else\r
+ /* Call legacy weak Tx Rx Complete Callback */\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ else if ((state == HAL_USART_STATE_BUSY_RX) &&\r
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))\r
+ {\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* When remaining number of bytes to receive is less than the RX FIFO\r
+ threshold, next incoming frames are processed as if FIFO mode was\r
+ disabled (i.e. one interrupt per received frame).\r
+ */\r
+ rxdatacount = husart->RxXferCount;\r
+ if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))\r
+ {\r
+ /* Disable the USART RXFT interrupt*/\r
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);\r
+\r
+ /* Update the RxISR function pointer */\r
+ husart->RxISR = USART_RxISR_16BIT;\r
+\r
+ /* Enable the USART Data Register Not Empty interrupt */\r
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);\r
+\r
+ if ((husart->TxXferCount == 0U) &&\r
+ (state == HAL_USART_STATE_BUSY_TX_RX) &&\r
+ (husart->SlaveMode == USART_SLAVEMODE_DISABLE))\r
+ {\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_usart_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended USART HAL module driver.\r
+ * This file provides firmware functions to manage the following extended\r
+ * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).\r
+ * + Peripheral Control functions\r
+ *\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### USART peripheral extended features #####\r
+ ==============================================================================\r
+\r
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.\r
+\r
+ -@- When USART operates in FIFO mode, FIFO mode must be enabled prior\r
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be\r
+ configured prior starting RX/TX transfers.\r
+\r
+ (#) Slave mode enabling/disabling and NSS pin configuration.\r
+\r
+ -@- When USART operates in Slave mode, Slave mode must be enabled prior\r
+ starting RX/TX transfers.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USARTEx USARTEx\r
+ * @brief USART Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* UART RX FIFO depth */\r
+#define RX_FIFO_DEPTH 8U\r
+\r
+/* UART TX FIFO depth */\r
+#define TX_FIFO_DEPTH 8U\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup USARTEx_Private_Functions USARTEx Private Functions\r
+ * @{\r
+ */\r
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions\r
+ * @brief Extended USART Transmit/Receive functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of FIFO mode related callback functions.\r
+\r
+ (#) TX/RX Fifos Callbacks:\r
+ (+) HAL_USARTEx_RxFifoFullCallback()\r
+ (+) HAL_USARTEx_TxFifoEmptyCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief USART RX Fifo full callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief USART TX Fifo empty callback.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(husart);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Extended Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides the following functions:\r
+ (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode\r
+ (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode\r
+ (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)\r
+ (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode\r
+ (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode\r
+ (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold\r
+ (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold\r
+\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the SPI slave mode.\r
+ * @note When the USART operates in SPI slave mode, it handles data flow using\r
+ * the serial interface clock derived from the external SCLK signal\r
+ * provided by the external master SPI device.\r
+ * @note In SPI slave mode, the USART must be enabled before starting the master\r
+ * communications (or between frames while the clock is stable). Otherwise,\r
+ * if the USART slave is enabled while the master is in the middle of a\r
+ * frame, it will become desynchronized with the master.\r
+ * @note The data register of the slave needs to be ready before the first edge\r
+ * of the communication clock or before the end of the ongoing communication,\r
+ * otherwise the SPI slave will transmit zeros.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Save actual USART configuration */\r
+ tmpcr1 = READ_REG(husart->Instance->CR1);\r
+\r
+ /* Disable USART */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* In SPI slave mode mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bit in the USART_CR2 register\r
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/\r
+ CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r
+\r
+ /* Enable SPI slave mode */\r
+ SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);\r
+\r
+ /* Restore USART configuration */\r
+ WRITE_REG(husart->Instance->CR1, tmpcr1);\r
+\r
+ husart->SlaveMode = USART_SLAVEMODE_ENABLE;\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Enable USART */\r
+ __HAL_USART_ENABLE(husart);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the SPI slave mode.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Save actual USART configuration */\r
+ tmpcr1 = READ_REG(husart->Instance->CR1);\r
+\r
+ /* Disable USART */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Disable SPI slave mode */\r
+ CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);\r
+\r
+ /* Restore USART configuration */\r
+ WRITE_REG(husart->Instance->CR1, tmpcr1);\r
+\r
+ husart->SlaveMode = USART_SLAVEMODE_ENABLE;\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Slave Select input pin (NSS).\r
+ * @note Software NSS management: SPI slave will always be selected and NSS\r
+ * input pin will be ignored.\r
+ * @note Hardware NSS management: the SPI slave selection depends on NSS\r
+ * input pin. The slave is selected when NSS is low and deselected when\r
+ * NSS is high.\r
+ * @param husart USART handle.\r
+ * @param NSSConfig NSS configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_NSS_HARD\r
+ * @arg @ref USART_NSS_SOFT\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));\r
+ assert_param(IS_USART_NSS(NSSConfig));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Save actual USART configuration */\r
+ tmpcr1 = READ_REG(husart->Instance->CR1);\r
+\r
+ /* Disable USART */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Program DIS_NSS bit in the USART_CR2 register */\r
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);\r
+\r
+ /* Restore USART configuration */\r
+ WRITE_REG(husart->Instance->CR1, tmpcr1);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the FIFO mode.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Save actual USART configuration */\r
+ tmpcr1 = READ_REG(husart->Instance->CR1);\r
+\r
+ /* Disable USART */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Enable FIFO mode */\r
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);\r
+ husart->FifoMode = USART_FIFOMODE_ENABLE;\r
+\r
+ /* Restore USART configuration */\r
+ WRITE_REG(husart->Instance->CR1, tmpcr1);\r
+\r
+ /* Determine the number of data to process during RX/TX ISR execution */\r
+ USARTEx_SetNbDataToProcess(husart);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the FIFO mode.\r
+ * @param husart USART handle.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Save actual USART configuration */\r
+ tmpcr1 = READ_REG(husart->Instance->CR1);\r
+\r
+ /* Disable USART */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Enable FIFO mode */\r
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);\r
+ husart->FifoMode = USART_FIFOMODE_DISABLE;\r
+\r
+ /* Restore USART configuration */\r
+ WRITE_REG(husart->Instance->CR1, tmpcr1);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the TXFIFO threshold.\r
+ * @param husart USART handle.\r
+ * @param Threshold TX FIFO threshold value\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_8\r
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_4\r
+ * @arg @ref USART_TXFIFO_THRESHOLD_1_2\r
+ * @arg @ref USART_TXFIFO_THRESHOLD_3_4\r
+ * @arg @ref USART_TXFIFO_THRESHOLD_7_8\r
+ * @arg @ref USART_TXFIFO_THRESHOLD_8_8\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));\r
+ assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Save actual USART configuration */\r
+ tmpcr1 = READ_REG(husart->Instance->CR1);\r
+\r
+ /* Disable USART */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Update TX threshold configuration */\r
+ MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);\r
+\r
+ /* Determine the number of data to process during RX/TX ISR execution */\r
+ USARTEx_SetNbDataToProcess(husart);\r
+\r
+ /* Restore USART configuration */\r
+ WRITE_REG(husart->Instance->CR1, tmpcr1);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the RXFIFO threshold.\r
+ * @param husart USART handle.\r
+ * @param Threshold RX FIFO threshold value\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_8\r
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_4\r
+ * @arg @ref USART_RXFIFO_THRESHOLD_1_2\r
+ * @arg @ref USART_RXFIFO_THRESHOLD_3_4\r
+ * @arg @ref USART_RXFIFO_THRESHOLD_7_8\r
+ * @arg @ref USART_RXFIFO_THRESHOLD_8_8\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)\r
+{\r
+ uint32_t tmpcr1;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));\r
+ assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Save actual USART configuration */\r
+ tmpcr1 = READ_REG(husart->Instance->CR1);\r
+\r
+ /* Disable USART */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Update RX threshold configuration */\r
+ MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);\r
+\r
+ /* Determine the number of data to process during RX/TX ISR execution */\r
+ USARTEx_SetNbDataToProcess(husart);\r
+\r
+ /* Restore USART configuration */\r
+ WRITE_REG(husart->Instance->CR1, tmpcr1);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup USARTEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Calculate the number of data to process in RX/TX ISR.\r
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from\r
+ * the USART configuration registers.\r
+ * @param husart USART handle.\r
+ * @retval None\r
+ */\r
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)\r
+{\r
+ uint8_t rx_fifo_depth;\r
+ uint8_t tx_fifo_depth;\r
+ uint8_t rx_fifo_threshold;\r
+ uint8_t tx_fifo_threshold;\r
+ /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */\r
+ uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};\r
+ uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};\r
+\r
+ if (husart->FifoMode == USART_FIFOMODE_DISABLE)\r
+ {\r
+ husart->NbTxDataToProcess = 1U;\r
+ husart->NbRxDataToProcess = 1U;\r
+ }\r
+ else\r
+ {\r
+ rx_fifo_depth = RX_FIFO_DEPTH;\r
+ tx_fifo_depth = TX_FIFO_DEPTH;\r
+ rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);\r
+ tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);\r
+ husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];\r
+ husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+@echo off \r
+\r
+if not "%~1" == "" goto debugFile \r
+\r
+@echo on \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl" \r
+\r
+@echo off \r
+goto end \r
+\r
+:debugFile \r
+\r
+@echo on \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl" \r
+\r
+@echo off \r
+:end
\ No newline at end of file
--- /dev/null
+param([String]$debugfile = "");\r
+\r
+# This powershell file has been generated by the IAR Embedded Workbench\r
+# C - SPY Debugger, as an aid to preparing a command line for running\r
+# the cspybat command line utility using the appropriate settings.\r
+#\r
+# Note that this file is generated every time a new debug session\r
+# is initialized, so you may want to move or rename the file before\r
+# making changes.\r
+#\r
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed\r
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).\r
+#\r
+# Read about available command line parameters in the C - SPY Debugging\r
+# Guide. Hints about additional command line parameters that may be\r
+# useful in specific cases :\r
+# --download_only Downloads a code image without starting a debug\r
+# session afterwards.\r
+# --silent Omits the sign - on message.\r
+# --timeout Limits the maximum allowed execution time.\r
+#\r
+\r
+\r
+if ($debugfile -eq "")\r
+{\r
+& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl" \r
+}\r
+else\r
+{\r
+& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl" \r
+}\r
--- /dev/null
+"--endian=little" \r
+\r
+"--cpu=Cortex-M4" \r
+\r
+"--fpu=VFPv4_SP" \r
+\r
+"-p" \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\CONFIG\debugger\ST\STM32H7x5_CM4.ddf" \r
+\r
+"--semihosting" \r
+\r
+"--device=STM32H745XI_CM4" \r
+\r
+"--multicore_nr_of_cores=1" \r
+\r
+"--jet_script_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32.ProbeScript" \r
+\r
+"--jet_standard_reset=9,0,0" \r
+\r
+"--reset_style=\"0,-,0,Disabled__no_reset_\"" \r
+\r
+"--reset_style=\"1,-,0,Software\"" \r
+\r
+"--reset_style=\"2,-,0,Hardware\"" \r
+\r
+"--reset_style=\"3,-,0,Core\"" \r
+\r
+"--reset_style=\"4,-,0,System\"" \r
+\r
+"--reset_style=\"9,ConnectUnderReset,1,Connect_during_reset\"" \r
+\r
+"--jet_power_from_probe=leave_on" \r
+\r
+"--drv_interface=SWD" \r
+\r
+"--drv_catch_exceptions=0xff0" \r
+\r
+"--board_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM4.board" \r
+\r
+\r
+\r
+\r
--- /dev/null
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armproc.dll" \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armJET.dll" \r
+\r
+"C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\STM32H745I_Discovery_CM4\Exe\STM32H745I_Discovery_CM4.out" \r
+\r
+--plugin="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armbat.dll" \r
+\r
+--flash_loader="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM4.board" \r
+\r
+\r
+\r
+\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+@echo off \r
+\r
+if not "%~1" == "" goto debugFile \r
+\r
+@echo on \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl" \r
+\r
+@echo off \r
+goto end \r
+\r
+:debugFile \r
+\r
+@echo on \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl" \r
+\r
+@echo off \r
+:end
\ No newline at end of file
--- /dev/null
+param([String]$debugfile = "");\r
+\r
+# This powershell file has been generated by the IAR Embedded Workbench\r
+# C - SPY Debugger, as an aid to preparing a command line for running\r
+# the cspybat command line utility using the appropriate settings.\r
+#\r
+# Note that this file is generated every time a new debug session\r
+# is initialized, so you may want to move or rename the file before\r
+# making changes.\r
+#\r
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed\r
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).\r
+#\r
+# Read about available command line parameters in the C - SPY Debugging\r
+# Guide. Hints about additional command line parameters that may be\r
+# useful in specific cases :\r
+# --download_only Downloads a code image without starting a debug\r
+# session afterwards.\r
+# --silent Omits the sign - on message.\r
+# --timeout Limits the maximum allowed execution time.\r
+#\r
+\r
+\r
+if ($debugfile -eq "")\r
+{\r
+& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl" \r
+}\r
+else\r
+{\r
+& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl" \r
+}\r
--- /dev/null
+"--endian=little" \r
+\r
+"--cpu=Cortex-M7" \r
+\r
+"--fpu=VFPv5_D16" \r
+\r
+"-p" \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\CONFIG\debugger\ST\STM32H7x5_CM7.ddf" \r
+\r
+"--drv_verify_download" \r
+\r
+"--semihosting" \r
+\r
+"--device=STM32H745XI_CM7" \r
+\r
+"--multicore_nr_of_cores=1" \r
+\r
+"--jet_script_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32.ProbeScript" \r
+\r
+"--jet_standard_reset=9,0,0" \r
+\r
+"--reset_style=\"0,-,0,Disabled__no_reset_\"" \r
+\r
+"--reset_style=\"1,-,0,Software\"" \r
+\r
+"--reset_style=\"2,-,0,Hardware\"" \r
+\r
+"--reset_style=\"3,-,0,Core\"" \r
+\r
+"--reset_style=\"4,-,0,System\"" \r
+\r
+"--reset_style=\"9,ConnectUnderReset,1,Connect_during_reset\"" \r
+\r
+"--jet_power_from_probe=leave_on" \r
+\r
+"--drv_interface=SWD" \r
+\r
+"--drv_catch_exceptions=0xff0" \r
+\r
+"--board_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM7.board" \r
+\r
+\r
+\r
+\r
--- /dev/null
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armproc.dll" \r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armJET.dll" \r
+\r
+"C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\STM32H745I_Discovery_CM7\Exe\STM32H745I_Discovery_CM7.out" \r
+\r
+--plugin="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armbat.dll" \r
+\r
+--flash_loader="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM7.board" \r
+\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<crun>\r
+ <version>1</version>\r
+ <filter_entries>\r
+ <filter index="0" type="default">\r
+ <type>*</type>\r
+ <start_file>*</start_file>\r
+ <end_file>*</end_file>\r
+ <action_debugger>0</action_debugger>\r
+ <action_log>1</action_log>\r
+ </filter>\r
+ </filter_entries>\r
+</crun>\r
--- /dev/null
+<?xml version="1.0"?>\r
+<Project>\r
+ <WindowStorage>\r
+ <ChildIdMap>\r
+ <TB_CMSISPACK>34048</TB_CMSISPACK>\r
+ <TB_DEBUG>34049</TB_DEBUG>\r
+ <TB_JET_TRACE>34050</TB_JET_TRACE>\r
+ <TB_MAIN>34051</TB_MAIN>\r
+ <WIN_AUTO>34052</WIN_AUTO>\r
+ <WIN_BREAKPOINTS>34053</WIN_BREAKPOINTS>\r
+ <WIN_BUILD>34054</WIN_BUILD>\r
+ <WIN_CALL_GRAPH>34055</WIN_CALL_GRAPH>\r
+ <WIN_CALL_STACK>34056</WIN_CALL_STACK>\r
+ <WIN_CMSISPACK_AGENT_LOG>34057</WIN_CMSISPACK_AGENT_LOG>\r
+ <WIN_CODE_COVERAGE>34058</WIN_CODE_COVERAGE>\r
+ <WIN_CORES>34059</WIN_CORES>\r
+ <WIN_CUSTOM_SFR>34060</WIN_CUSTOM_SFR>\r
+ <WIN_C_STAT>34061</WIN_C_STAT>\r
+ <WIN_DATA_LOG>34062</WIN_DATA_LOG>\r
+ <WIN_DATA_STAT>34063</WIN_DATA_STAT>\r
+ <WIN_DEBUGGER_MACROS>34064</WIN_DEBUGGER_MACROS>\r
+ <WIN_DEBUG_LOG>34065</WIN_DEBUG_LOG>\r
+ <WIN_DISASSEMBLY>34066</WIN_DISASSEMBLY>\r
+ <WIN_EVENT_LOG>34067</WIN_EVENT_LOG>\r
+ <WIN_EVENT_STAT>34068</WIN_EVENT_STAT>\r
+ <WIN_EXCEPTION_VIEWER>34069</WIN_EXCEPTION_VIEWER>\r
+ <WIN_EXTRA_TRACE>34070</WIN_EXTRA_TRACE>\r
+ <WIN_FIND_ALL_DECLARATIONS>34071</WIN_FIND_ALL_DECLARATIONS>\r
+ <WIN_FIND_ALL_REFERENCES>34072</WIN_FIND_ALL_REFERENCES>\r
+ <WIN_FIND_IN_FILES>34073</WIN_FIND_IN_FILES>\r
+ <WIN_FIND_IN_TRACE_EXTRA>34074</WIN_FIND_IN_TRACE_EXTRA>\r
+ <WIN_IMAGES>34075</WIN_IMAGES>\r
+ <WIN_INTERRUPT_LOG>34076</WIN_INTERRUPT_LOG>\r
+ <WIN_INTERRUPT_STAT>34077</WIN_INTERRUPT_STAT>\r
+ <WIN_LOCALS>34078</WIN_LOCALS>\r
+ <WIN_MACRO_EVAL>34079</WIN_MACRO_EVAL>\r
+ <WIN_MACRO_REGISTRATION>34080</WIN_MACRO_REGISTRATION>\r
+ <WIN_MEMORY_1>34081</WIN_MEMORY_1>\r
+ <WIN_MEMORY_2>34082</WIN_MEMORY_2>\r
+ <WIN_MEMORY_3>34083</WIN_MEMORY_3>\r
+ <WIN_MEMORY_4>34084</WIN_MEMORY_4>\r
+ <WIN_PHYSICAL_BREAKPOINTS>34085</WIN_PHYSICAL_BREAKPOINTS>\r
+ <WIN_PROFILING2>34086</WIN_PROFILING2>\r
+ <WIN_QUICK_WATCH>34087</WIN_QUICK_WATCH>\r
+ <WIN_REGISTER_1>34088</WIN_REGISTER_1>\r
+ <WIN_REGISTER_2>34089</WIN_REGISTER_2>\r
+ <WIN_REGISTER_3>34090</WIN_REGISTER_3>\r
+ <WIN_REGISTER_4>34091</WIN_REGISTER_4>\r
+ <WIN_REGISTER_GROUPS>34092</WIN_REGISTER_GROUPS>\r
+ <WIN_SELECT_AMBIGUOUS_DEFINITIONS>34093</WIN_SELECT_AMBIGUOUS_DEFINITIONS>\r
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+</Project>\r
--- /dev/null
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--- /dev/null
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+ </MDIClientArea-0>\r
+ </MDIWindows>\r
+ </WindowStorage>\r
+</Workspace>\r
--- /dev/null
+;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************\r
+;* File Name : startup_stm32h745xx.s\r
+;* Author : MCD Application Team\r
+;* Description : STM32H745xx devices vector table for EWARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == _iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR \r
+;* address.\r
+;* - Branches to main in the C library (which eventually\r
+;* calls main()).\r
+;* After Reset the Cortex-M processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;******************************************************************************\r
+;* @attention\r
+;*\r
+;* <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+;* All rights reserved.</center></h2>\r
+;*\r
+;* This software component is licensed by ST under BSD 3-Clause license,\r
+;* the "License"; You may not use this file except in compliance with the\r
+;* License. You may obtain a copy of the License at:\r
+;* opensource.org/licenses/BSD-3-Clause\r
+;*\r
+;******************************************************************************\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+ \r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) \r
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection \r
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line \r
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line \r
+ DCD FLASH_IRQHandler ; FLASH \r
+ DCD RCC_IRQHandler ; RCC \r
+ DCD EXTI0_IRQHandler ; EXTI Line0 \r
+ DCD EXTI1_IRQHandler ; EXTI Line1 \r
+ DCD EXTI2_IRQHandler ; EXTI Line2 \r
+ DCD EXTI3_IRQHandler ; EXTI Line3 \r
+ DCD EXTI4_IRQHandler ; EXTI Line4 \r
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 \r
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 \r
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 \r
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 \r
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 \r
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 \r
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 \r
+ DCD ADC_IRQHandler ; ADC1, ADC2 \r
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 \r
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 \r
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 \r
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 \r
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s \r
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt \r
+ DCD TIM1_UP_IRQHandler ; TIM1 Update \r
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare \r
+ DCD TIM2_IRQHandler ; TIM2 \r
+ DCD TIM3_IRQHandler ; TIM3 \r
+ DCD TIM4_IRQHandler ; TIM4 \r
+ DCD I2C1_EV_IRQHandler ; I2C1 Event \r
+ DCD I2C1_ER_IRQHandler ; I2C1 Error \r
+ DCD I2C2_EV_IRQHandler ; I2C2 Event \r
+ DCD I2C2_ER_IRQHandler ; I2C2 Error \r
+ DCD SPI1_IRQHandler ; SPI1 \r
+ DCD SPI2_IRQHandler ; SPI2 \r
+ DCD USART1_IRQHandler ; USART1 \r
+ DCD USART2_IRQHandler ; USART2 \r
+ DCD USART3_IRQHandler ; USART3 \r
+ DCD EXTI15_10_IRQHandler ; External Line[15:10] \r
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line \r
+ DCD 0 ; Reserved \r
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt \r
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt\r
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob\r
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt \r
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 \r
+ DCD FMC_IRQHandler ; FMC \r
+ DCD SDMMC1_IRQHandler ; SDMMC1 \r
+ DCD TIM5_IRQHandler ; TIM5 \r
+ DCD SPI3_IRQHandler ; SPI3 \r
+ DCD UART4_IRQHandler ; UART4 \r
+ DCD UART5_IRQHandler ; UART5 \r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors \r
+ DCD TIM7_IRQHandler ; TIM7 \r
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 \r
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 \r
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 \r
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 \r
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 \r
+ DCD ETH_IRQHandler ; Ethernet \r
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line \r
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt \r
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4\r
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 \r
+ DCD 0 ; Reserved \r
+ DCD 0 ; Reserved \r
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 \r
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 \r
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 \r
+ DCD USART6_IRQHandler ; USART6 \r
+ DCD I2C3_EV_IRQHandler ; I2C3 event \r
+ DCD I2C3_ER_IRQHandler ; I2C3 error \r
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out \r
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In \r
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI \r
+ DCD OTG_HS_IRQHandler ; USB OTG HS \r
+ DCD DCMI_IRQHandler ; DCMI \r
+ DCD 0 ; Reserved \r
+ DCD RNG_IRQHandler ; Rng\r
+ DCD FPU_IRQHandler ; FPU\r
+ DCD UART7_IRQHandler ; UART7\r
+ DCD UART8_IRQHandler ; UART8\r
+ DCD SPI4_IRQHandler ; SPI4\r
+ DCD SPI5_IRQHandler ; SPI5\r
+ DCD SPI6_IRQHandler ; SPI6\r
+ DCD SAI1_IRQHandler ; SAI1\r
+ DCD LTDC_IRQHandler ; LTDC\r
+ DCD LTDC_ER_IRQHandler ; LTDC error\r
+ DCD DMA2D_IRQHandler ; DMA2D\r
+ DCD SAI2_IRQHandler ; SAI2\r
+ DCD QUADSPI_IRQHandler ; QUADSPI\r
+ DCD LPTIM1_IRQHandler ; LPTIM1\r
+ DCD CEC_IRQHandler ; HDMI_CEC\r
+ DCD I2C4_EV_IRQHandler ; I2C4 Event \r
+ DCD I2C4_ER_IRQHandler ; I2C4 Error \r
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX\r
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out \r
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In \r
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI \r
+ DCD OTG_FS_IRQHandler ; USB OTG FS \r
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt \r
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts \r
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt \r
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt \r
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt \r
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt \r
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt \r
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt \r
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt \r
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt \r
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt \r
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt \r
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt \r
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt \r
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt \r
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt \r
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt \r
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt \r
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt \r
+ DCD JPEG_IRQHandler ; JPEG global Interrupt \r
+ DCD MDMA_IRQHandler ; MDMA global Interrupt \r
+ DCD 0 ; Reserved \r
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt \r
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt \r
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt \r
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt \r
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt \r
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt \r
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt \r
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt \r
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt \r
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt \r
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt \r
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt \r
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt \r
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt \r
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt \r
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt \r
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt \r
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt \r
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt \r
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) \r
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt \r
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt\r
+ DCD SAI4_IRQHandler ; SAI4 global interrupt \r
+ DCD 0 ; Reserved \r
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt \r
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins \r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(2)\r
+Reset_Handler\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+\r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+\r
+ PUBWEAK MemManage_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+MemManage_Handler\r
+ B MemManage_Handler\r
+\r
+ PUBWEAK BusFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+BusFault_Handler\r
+ B BusFault_Handler\r
+\r
+ PUBWEAK UsageFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UsageFault_Handler\r
+ B UsageFault_Handler\r
+\r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+\r
+ PUBWEAK DebugMon_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DebugMon_Handler\r
+ B DebugMon_Handler\r
+\r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+\r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+WWDG_IRQHandler \r
+ B WWDG_IRQHandler\r
+\r
+ PUBWEAK PVD_AVD_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PVD_AVD_IRQHandler \r
+ B PVD_AVD_IRQHandler\r
+\r
+ PUBWEAK TAMP_STAMP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TAMP_STAMP_IRQHandler \r
+ B TAMP_STAMP_IRQHandler\r
+\r
+ PUBWEAK RTC_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+RTC_WKUP_IRQHandler \r
+ B RTC_WKUP_IRQHandler\r
+\r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FLASH_IRQHandler \r
+ B FLASH_IRQHandler\r
+\r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RCC_IRQHandler \r
+ B RCC_IRQHandler\r
+\r
+ PUBWEAK EXTI0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI0_IRQHandler \r
+ B EXTI0_IRQHandler\r
+\r
+ PUBWEAK EXTI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI1_IRQHandler \r
+ B EXTI1_IRQHandler\r
+\r
+ PUBWEAK EXTI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI2_IRQHandler \r
+ B EXTI2_IRQHandler\r
+\r
+ PUBWEAK EXTI3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI3_IRQHandler\r
+ B EXTI3_IRQHandler\r
+\r
+ PUBWEAK EXTI4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+EXTI4_IRQHandler \r
+ B EXTI4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream0_IRQHandler \r
+ B DMA1_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream1_IRQHandler \r
+ B DMA1_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream2_IRQHandler \r
+ B DMA1_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream3_IRQHandler \r
+ B DMA1_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream4_IRQHandler \r
+ B DMA1_Stream4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream5_IRQHandler \r
+ B DMA1_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream6_IRQHandler \r
+ B DMA1_Stream6_IRQHandler\r
+\r
+ PUBWEAK ADC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC_IRQHandler \r
+ B ADC_IRQHandler\r
+\r
+ PUBWEAK FDCAN1_IT0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+FDCAN1_IT0_IRQHandler \r
+ B FDCAN1_IT0_IRQHandler\r
+\r
+ PUBWEAK FDCAN2_IT0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+FDCAN2_IT0_IRQHandler \r
+ B FDCAN2_IT0_IRQHandler\r
+\r
+ PUBWEAK FDCAN1_IT1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+FDCAN1_IT1_IRQHandler \r
+ B FDCAN1_IT1_IRQHandler\r
+\r
+ PUBWEAK FDCAN2_IT1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+FDCAN2_IT1_IRQHandler \r
+ B FDCAN2_IT1_IRQHandler\r
+\r
+ PUBWEAK EXTI9_5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+EXTI9_5_IRQHandler \r
+ B EXTI9_5_IRQHandler\r
+\r
+ PUBWEAK TIM1_BRK_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_BRK_IRQHandler \r
+ B TIM1_BRK_IRQHandler\r
+\r
+ PUBWEAK TIM1_UP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_UP_IRQHandler \r
+ B TIM1_UP_IRQHandler\r
+\r
+ PUBWEAK TIM1_TRG_COM_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_TRG_COM_IRQHandler \r
+ B TIM1_TRG_COM_IRQHandler\r
+ \r
+ PUBWEAK TIM1_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_CC_IRQHandler \r
+ B TIM1_CC_IRQHandler\r
+\r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM2_IRQHandler \r
+ B TIM2_IRQHandler\r
+\r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM3_IRQHandler \r
+ B TIM3_IRQHandler\r
+\r
+ PUBWEAK TIM4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM4_IRQHandler \r
+ B TIM4_IRQHandler\r
+\r
+ PUBWEAK I2C1_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C1_EV_IRQHandler \r
+ B I2C1_EV_IRQHandler\r
+\r
+ PUBWEAK I2C1_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C1_ER_IRQHandler \r
+ B I2C1_ER_IRQHandler\r
+\r
+ PUBWEAK I2C2_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C2_EV_IRQHandler \r
+ B I2C2_EV_IRQHandler\r
+\r
+ PUBWEAK I2C2_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C2_ER_IRQHandler \r
+ B I2C2_ER_IRQHandler\r
+\r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI1_IRQHandler \r
+ B SPI1_IRQHandler\r
+\r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI2_IRQHandler \r
+ B SPI2_IRQHandler\r
+\r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART1_IRQHandler \r
+ B USART1_IRQHandler\r
+\r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART2_IRQHandler \r
+ B USART2_IRQHandler\r
+\r
+ PUBWEAK USART3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART3_IRQHandler \r
+ B USART3_IRQHandler\r
+\r
+ PUBWEAK EXTI15_10_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+EXTI15_10_IRQHandler \r
+ B EXTI15_10_IRQHandler\r
+\r
+ PUBWEAK RTC_Alarm_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+RTC_Alarm_IRQHandler \r
+ B RTC_Alarm_IRQHandler\r
+ \r
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_BRK_TIM12_IRQHandler \r
+ B TIM8_BRK_TIM12_IRQHandler\r
+\r
+ PUBWEAK TIM8_UP_TIM13_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_UP_TIM13_IRQHandler \r
+ B TIM8_UP_TIM13_IRQHandler\r
+\r
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_TRG_COM_TIM14_IRQHandler \r
+ B TIM8_TRG_COM_TIM14_IRQHandler\r
+\r
+ PUBWEAK TIM8_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_CC_IRQHandler \r
+ B TIM8_CC_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream7_IRQHandler \r
+ B DMA1_Stream7_IRQHandler\r
+\r
+ PUBWEAK FMC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FMC_IRQHandler \r
+ B FMC_IRQHandler\r
+\r
+ PUBWEAK SDMMC1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SDMMC1_IRQHandler \r
+ B SDMMC1_IRQHandler\r
+\r
+ PUBWEAK TIM5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM5_IRQHandler \r
+ B TIM5_IRQHandler\r
+\r
+ PUBWEAK SPI3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI3_IRQHandler \r
+ B SPI3_IRQHandler\r
+\r
+ PUBWEAK UART4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART4_IRQHandler \r
+ B UART4_IRQHandler\r
+\r
+ PUBWEAK UART5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART5_IRQHandler \r
+ B UART5_IRQHandler\r
+\r
+ PUBWEAK TIM6_DAC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM6_DAC_IRQHandler \r
+ B TIM6_DAC_IRQHandler\r
+\r
+ PUBWEAK TIM7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM7_IRQHandler \r
+ B TIM7_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream0_IRQHandler \r
+ B DMA2_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream1_IRQHandler \r
+ B DMA2_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream2_IRQHandler \r
+ B DMA2_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream3_IRQHandler \r
+ B DMA2_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream4_IRQHandler \r
+ B DMA2_Stream4_IRQHandler\r
+\r
+ PUBWEAK ETH_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ETH_IRQHandler \r
+ B ETH_IRQHandler\r
+\r
+ PUBWEAK ETH_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+ETH_WKUP_IRQHandler \r
+ B ETH_WKUP_IRQHandler\r
+\r
+ PUBWEAK FDCAN_CAL_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+FDCAN_CAL_IRQHandler \r
+ B FDCAN_CAL_IRQHandler\r
+\r
+ PUBWEAK CM7_SEV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CM7_SEV_IRQHandler \r
+ B CM7_SEV_IRQHandler\r
+\r
+ PUBWEAK CM4_SEV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CM4_SEV_IRQHandler \r
+ B CM4_SEV_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream5_IRQHandler \r
+ B DMA2_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream6_IRQHandler \r
+ B DMA2_Stream6_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream7_IRQHandler \r
+ B DMA2_Stream7_IRQHandler\r
+\r
+ PUBWEAK USART6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART6_IRQHandler \r
+ B USART6_IRQHandler\r
+\r
+ PUBWEAK I2C3_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C3_EV_IRQHandler \r
+ B I2C3_EV_IRQHandler\r
+\r
+ PUBWEAK I2C3_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C3_ER_IRQHandler \r
+ B I2C3_ER_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_HS_EP1_OUT_IRQHandler \r
+ B OTG_HS_EP1_OUT_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_HS_EP1_IN_IRQHandler \r
+ B OTG_HS_EP1_IN_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+OTG_HS_WKUP_IRQHandler \r
+ B OTG_HS_WKUP_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_IRQHandler \r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+OTG_HS_IRQHandler \r
+ B OTG_HS_IRQHandler \r
+\r
+ PUBWEAK DCMI_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DCMI_IRQHandler \r
+ B DCMI_IRQHandler\r
+\r
+ PUBWEAK RNG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+RNG_IRQHandler \r
+ B RNG_IRQHandler\r
+\r
+ PUBWEAK FPU_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+FPU_IRQHandler \r
+ B FPU_IRQHandler\r
+\r
+ PUBWEAK UART7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+UART7_IRQHandler \r
+ B UART7_IRQHandler \r
+\r
+ PUBWEAK UART8_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+UART8_IRQHandler \r
+ B UART8_IRQHandler\r
+ \r
+ PUBWEAK SPI4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPI4_IRQHandler\r
+ B SPI4_IRQHandler \r
+\r
+ PUBWEAK SPI5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPI5_IRQHandler \r
+ B SPI5_IRQHandler \r
+\r
+ PUBWEAK SPI6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPI6_IRQHandler \r
+ B SPI6_IRQHandler \r
+\r
+ PUBWEAK SAI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SAI1_IRQHandler \r
+ B SAI1_IRQHandler \r
+\r
+ PUBWEAK LTDC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LTDC_IRQHandler \r
+ B LTDC_IRQHandler \r
+\r
+ PUBWEAK LTDC_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LTDC_ER_IRQHandler \r
+ B LTDC_ER_IRQHandler \r
+\r
+ PUBWEAK DMA2D_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2D_IRQHandler \r
+ B DMA2D_IRQHandler \r
+\r
+ PUBWEAK SAI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SAI2_IRQHandler \r
+ B SAI2_IRQHandler \r
+\r
+ PUBWEAK QUADSPI_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+QUADSPI_IRQHandler \r
+ B QUADSPI_IRQHandler \r
+ \r
+ PUBWEAK LPTIM1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LPTIM1_IRQHandler \r
+ B LPTIM1_IRQHandler \r
+ \r
+ PUBWEAK CEC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CEC_IRQHandler \r
+ B CEC_IRQHandler \r
+\r
+ PUBWEAK I2C4_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C4_EV_IRQHandler \r
+ B I2C4_EV_IRQHandler \r
+ \r
+ PUBWEAK I2C4_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C4_ER_IRQHandler \r
+ B I2C4_ER_IRQHandler \r
+ \r
+ PUBWEAK SPDIF_RX_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPDIF_RX_IRQHandler \r
+ B SPDIF_RX_IRQHandler \r
+\r
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_FS_EP1_OUT_IRQHandler \r
+ B OTG_FS_EP1_OUT_IRQHandler \r
+\r
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_FS_EP1_IN_IRQHandler \r
+ B OTG_FS_EP1_IN_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_FS_WKUP_IRQHandler \r
+ B OTG_FS_WKUP_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_FS_IRQHandler \r
+ B OTG_FS_IRQHandler \r
+\r
+ PUBWEAK DMAMUX1_OVR_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMAMUX1_OVR_IRQHandler \r
+ B DMAMUX1_OVR_IRQHandler \r
+\r
+ PUBWEAK HRTIM1_Master_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HRTIM1_Master_IRQHandler \r
+ B HRTIM1_Master_IRQHandler \r
+\r
+ PUBWEAK HRTIM1_TIMA_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HRTIM1_TIMA_IRQHandler \r
+ B HRTIM1_TIMA_IRQHandler \r
+\r
+ PUBWEAK HRTIM1_TIMB_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HRTIM1_TIMB_IRQHandler \r
+ B HRTIM1_TIMB_IRQHandler \r
+\r
+ PUBWEAK HRTIM1_TIMC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HRTIM1_TIMC_IRQHandler \r
+ B HRTIM1_TIMC_IRQHandler \r
+\r
+ PUBWEAK HRTIM1_TIMD_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HRTIM1_TIMD_IRQHandler \r
+ B HRTIM1_TIMD_IRQHandler\r
+\r
+ PUBWEAK HRTIM1_TIME_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HRTIM1_TIME_IRQHandler \r
+ B HRTIM1_TIME_IRQHandler\r
+\r
+ PUBWEAK HRTIM1_FLT_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HRTIM1_FLT_IRQHandler \r
+ B HRTIM1_FLT_IRQHandler\r
+\r
+ PUBWEAK DFSDM1_FLT0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DFSDM1_FLT0_IRQHandler \r
+ B DFSDM1_FLT0_IRQHandler \r
+\r
+ PUBWEAK DFSDM1_FLT1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DFSDM1_FLT1_IRQHandler \r
+ B DFSDM1_FLT1_IRQHandler\r
+\r
+ PUBWEAK DFSDM1_FLT2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DFSDM1_FLT2_IRQHandler \r
+ B DFSDM1_FLT2_IRQHandler\r
+\r
+ PUBWEAK DFSDM1_FLT3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DFSDM1_FLT3_IRQHandler \r
+ B DFSDM1_FLT3_IRQHandler \r
+\r
+ PUBWEAK SAI3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SAI3_IRQHandler \r
+ B SAI3_IRQHandler\r
+\r
+ PUBWEAK SWPMI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SWPMI1_IRQHandler \r
+ B SWPMI1_IRQHandler\r
+\r
+ PUBWEAK TIM15_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM15_IRQHandler \r
+ B TIM15_IRQHandler\r
+\r
+ PUBWEAK TIM16_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM16_IRQHandler \r
+ B TIM16_IRQHandler\r
+\r
+ PUBWEAK TIM17_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM17_IRQHandler \r
+ B TIM17_IRQHandler\r
+\r
+ PUBWEAK MDIOS_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+MDIOS_WKUP_IRQHandler \r
+ B MDIOS_WKUP_IRQHandler\r
+\r
+ PUBWEAK MDIOS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+MDIOS_IRQHandler \r
+ B MDIOS_IRQHandler\r
+\r
+ PUBWEAK JPEG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+JPEG_IRQHandler \r
+ B JPEG_IRQHandler\r
+\r
+ PUBWEAK MDMA_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+MDMA_IRQHandler \r
+ B MDMA_IRQHandler\r
+\r
+ PUBWEAK SDMMC2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SDMMC2_IRQHandler \r
+ B SDMMC2_IRQHandler\r
+\r
+ PUBWEAK HSEM1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HSEM1_IRQHandler \r
+ B HSEM1_IRQHandler\r
+\r
+ PUBWEAK HSEM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HSEM2_IRQHandler \r
+ B HSEM2_IRQHandler\r
+\r
+ PUBWEAK ADC3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+ADC3_IRQHandler \r
+ B ADC3_IRQHandler\r
+\r
+ PUBWEAK DMAMUX2_OVR_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMAMUX2_OVR_IRQHandler \r
+ B DMAMUX2_OVR_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel0_IRQHandler \r
+ B BDMA_Channel0_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel1_IRQHandler \r
+ B BDMA_Channel1_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel2_IRQHandler \r
+ B BDMA_Channel2_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel3_IRQHandler \r
+ B BDMA_Channel3_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel4_IRQHandler \r
+ B BDMA_Channel4_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel5_IRQHandler \r
+ B BDMA_Channel5_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel6_IRQHandler \r
+ B BDMA_Channel6_IRQHandler\r
+\r
+ PUBWEAK BDMA_Channel7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+BDMA_Channel7_IRQHandler \r
+ B BDMA_Channel7_IRQHandler\r
+\r
+ PUBWEAK COMP1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+COMP1_IRQHandler \r
+ B COMP1_IRQHandler\r
+\r
+ PUBWEAK LPTIM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LPTIM2_IRQHandler \r
+ B LPTIM2_IRQHandler\r
+\r
+ PUBWEAK LPTIM3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LPTIM3_IRQHandler \r
+ B LPTIM3_IRQHandler\r
+\r
+ PUBWEAK LPTIM4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LPTIM4_IRQHandler \r
+ B LPTIM4_IRQHandler\r
+\r
+ PUBWEAK LPTIM5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LPTIM5_IRQHandler \r
+ B LPTIM5_IRQHandler \r
+\r
+ PUBWEAK LPUART1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LPUART1_IRQHandler \r
+ B LPUART1_IRQHandler\r
+\r
+ PUBWEAK WWDG_RST_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+WWDG_RST_IRQHandler \r
+ B WWDG_RST_IRQHandler\r
+\r
+ PUBWEAK CRS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CRS_IRQHandler \r
+ B CRS_IRQHandler\r
+\r
+ PUBWEAK ECC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+ECC_IRQHandler \r
+ B ECC_IRQHandler \r
+\r
+ PUBWEAK SAI4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SAI4_IRQHandler \r
+ B SAI4_IRQHandler\r
+\r
+ PUBWEAK HOLD_CORE_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HOLD_CORE_IRQHandler \r
+ B HOLD_CORE_IRQHandler\r
+\r
+ PUBWEAK WAKEUP_PIN_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+WAKEUP_PIN_IRQHandler \r
+ B WAKEUP_PIN_IRQHandler \r
+ END\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x1003FFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x800;\r
+define symbol __ICFEDIT_size_heap__ = 0x400;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block HEAP };
\ No newline at end of file
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x2401FFFF;\r
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;\r
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block HEAP };
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32h7xx.c\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.\r
+ *\r
+ * This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32h7xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32h7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32H7xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32h7xx.h"\r
+#include <math.h>\r
+\r
+#if !defined (HSE_VALUE)\r
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (CSI_VALUE)\r
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* CSI_VALUE */\r
+\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to use external SDRAM mounted\r
+ on DISCO board as data memory */\r
+/*#define DATA_IN_ExtSDRAM*/\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Private_Variables\r
+ * @{\r
+ */\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+ uint32_t SystemCoreClock = 64000000;\r
+ uint32_t SystemD2Clock = 64000000;\r
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+#if defined (DATA_IN_ExtSDRAM)\r
+ static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSDRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32H7xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the FPU setting, vector table location and External memory \r
+ * configuration.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit (void)\r
+{ \r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+\r
+ /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is\r
+ detectable by the CPU after a WFI/WFE instruction.*/ \r
+ SCB->SCR |= SCB_SCR_SEVONPEND_Pos;\r
+\r
+#ifdef CORE_CM7 \r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= RCC_CR_HSION;\r
+ \r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */\r
+ RCC->CR &= 0xEAF6ED7FU;\r
+\r
+ /* Reset D1CFGR register */\r
+ RCC->D1CFGR = 0x00000000;\r
+\r
+ /* Reset D2CFGR register */\r
+ RCC->D2CFGR = 0x00000000;\r
+ \r
+ /* Reset D3CFGR register */\r
+ RCC->D3CFGR = 0x00000000;\r
+\r
+ /* Reset PLLCKSELR register */\r
+ RCC->PLLCKSELR = 0x00000000;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x00000000;\r
+ /* Reset PLL1DIVR register */\r
+ RCC->PLL1DIVR = 0x00000000;\r
+ /* Reset PLL1FRACR register */\r
+ RCC->PLL1FRACR = 0x00000000;\r
+\r
+ /* Reset PLL2DIVR register */\r
+ RCC->PLL2DIVR = 0x00000000;\r
+\r
+ /* Reset PLL2FRACR register */\r
+ \r
+ RCC->PLL2FRACR = 0x00000000;\r
+ /* Reset PLL3DIVR register */\r
+ RCC->PLL3DIVR = 0x00000000;\r
+\r
+ /* Reset PLL3FRACR register */\r
+ RCC->PLL3FRACR = 0x00000000;\r
+ \r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= 0xFFFBFFFFU;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIER = 0x00000000;\r
+\r
+ /* Enable CortexM7 HSEM EXTI line (line 78)*/\r
+ EXTI_D2->EMR3 |= 0x4000UL; \r
+\r
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */\r
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)\r
+ {\r
+ /* if stm32h7 revY*/\r
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */\r
+ *((__IO uint32_t*)0x51008108) = 0x00000001U;\r
+ }\r
+ \r
+#if defined (DATA_IN_ExtSDRAM)\r
+ SystemInit_ExtMemCtl(); \r
+#endif /* DATA_IN_ExtSDRAM */\r
+ \r
+#endif /* CORE_CM7*/\r
+\r
+#ifdef CORE_CM4\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif \r
+\r
+#else\r
+#ifdef CORE_CM7\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif \r
+\r
+#else\r
+#error Please #define CORE_CM4 or CORE_CM7\r
+#endif \r
+#endif\r
+\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock , it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)\r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),\r
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.\r
+ *\r
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value\r
+ * 4 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value\r
+ * 64 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;\r
+ float_t fracn1, pllvco;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+\r
+ switch (RCC->CFGR & RCC_CFGR_SWS)\r
+ {\r
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */\r
+ SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));\r
+\r
+ break;\r
+\r
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */\r
+ SystemCoreClock = CSI_VALUE;\r
+ break;\r
+\r
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+\r
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN\r
+ SYSCLK = PLL_VCO / PLLR\r
+ */\r
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);\r
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;\r
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);\r
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));\r
+\r
+ if (pllm != 0U)\r
+ {\r
+ switch (pllsource)\r
+ {\r
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */\r
+ \r
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;\r
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ \r
+ break;\r
+ \r
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */\r
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+ \r
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */\r
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+ \r
+ default:\r
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );\r
+ break;\r
+ }\r
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;\r
+ SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);\r
+ }\r
+ else\r
+ {\r
+ SystemCoreClock = 0U;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ SystemCoreClock = CSI_VALUE;\r
+ break;\r
+ }\r
+\r
+ /* Compute SystemClock frequency --------------------------------------------------*/\r
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];\r
+\r
+ /* SystemCoreClock frequency : CM7 CPU frequency */\r
+ SystemCoreClock >>= tmp;\r
+\r
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */\r
+ SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));\r
+}\r
+#if defined (DATA_IN_ExtSDRAM)\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in startup_stm32h7xx.s before jump to main.\r
+ * This function configures the external memories SDRAM\r
+ * This SDRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;\r
+ register __IO uint32_t index;\r
+\r
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface \r
+ clock */\r
+ RCC->AHB4ENR |= 0x000001F8;\r
+\r
+ /* Delay after an RCC peripheral clock enabling */\r
+ tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\r
+ \r
+ /* Connect PDx pins to FMC Alternate function */\r
+ GPIOD->AFR[0] = 0x000000CC;\r
+ GPIOD->AFR[1] = 0xCC000CCC;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xAFEAFFFA;\r
+ /* Configure PDx pins speed to 100 MHz */ \r
+ GPIOD->OSPEEDR = 0xF03F000F;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* Configure PDx pins in Pull-up */\r
+ GPIOD->PUPDR = 0x50150005;\r
+ \r
+ /* Connect PEx pins to FMC Alternate function */\r
+ GPIOE->AFR[0] = 0xC00000CC;\r
+ GPIOE->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xAAAABFFA;\r
+ /* Configure PEx pins speed to 100 MHz */ \r
+ GPIOE->OSPEEDR = 0xFFFFC00F;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* Configure PEx pins in Pull-up */\r
+ GPIOE->PUPDR = 0x55554005;\r
+ \r
+ /* Connect PFx pins to FMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00CCCCCC;\r
+ GPIOF->AFR[1] = 0xCCCCC000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xAABFFAAA;\r
+ /* Configure PFx pins speed to 100 MHz */ \r
+ GPIOF->OSPEEDR = 0xFFC00FFF;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* Configure PFx pins in Pull-up */\r
+ GPIOF->PUPDR = 0x55400555;\r
+ \r
+ /* Connect PGx pins to FMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00CC00CC;\r
+ GPIOG->AFR[1] = 0xC000000C;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0xBFFEFAFA;\r
+ /* Configure PGx pins speed to 100 MHz */ \r
+ GPIOG->OSPEEDR = 0xC0030F0F;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* Configure PGx pins in Pull-up */ \r
+ GPIOG->PUPDR = 0x40010505;\r
+ \r
+ /* Connect PHx pins to FMC Alternate function */\r
+ GPIOH->AFR[0] = 0xCCC00000;\r
+ GPIOH->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PHx pins in Alternate function mode */ \r
+ GPIOH->MODER = 0xAAAAABFF;\r
+ /* Configure PHx pins speed to 100 MHz */ \r
+ GPIOH->OSPEEDR = 0xFFFFFC00;\r
+ /* Configure PHx pins Output type to push-pull */ \r
+ GPIOH->OTYPER = 0x00000000;\r
+ /* Configure PHx pins in Pull-up */\r
+ GPIOH->PUPDR = 0x55555400;\r
+ \r
+/*-- FMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FMC interface clock */\r
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));\r
+ /*SDRAM Timing and access interface configuration*/\r
+ /*LoadToActiveDelay = 2\r
+ ExitSelfRefreshDelay = 6\r
+ SelfRefreshTime = 4\r
+ RowCycleDelay = 6\r
+ WriteRecoveryTime = 2\r
+ RPDelay = 2\r
+ RCDDelay = 2\r
+ SDBank = FMC_SDRAM_BANK2\r
+ ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8 \r
+ RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12\r
+ MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16\r
+ InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4\r
+ CASLatency = FMC_SDRAM_CAS_LATENCY_2\r
+ WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE\r
+ SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2\r
+ ReadBurst = FMC_SDRAM_RBURST_ENABLE\r
+ ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/\r
+ \r
+ FMC_Bank5_6_R->SDCR[0] = 0x00001800;\r
+ FMC_Bank5_6_R->SDCR[1] = 0x00000154;\r
+ FMC_Bank5_6_R->SDTR[0] = 0x00105000;\r
+ FMC_Bank5_6_R->SDTR[1] = 0x01010351;\r
+\r
+ /* SDRAM initialization sequence */\r
+ /* Clock enable command */ \r
+ FMC_Bank5_6_R->SDCMR = 0x00000009; \r
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; \r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; \r
+ }\r
+\r
+ /* Delay */\r
+ for (index = 0; index<1000; index++);\r
+ \r
+ /* PALL command */ \r
+ FMC_Bank5_6_R->SDCMR = 0x0000000A; \r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; \r
+ }\r
+ \r
+ FMC_Bank5_6_R->SDCMR = 0x000000EB;\r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; \r
+ }\r
+\r
+ FMC_Bank5_6_R->SDCMR = 0x0004400C;\r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; \r
+ } \r
+ /* Set refresh count */\r
+ tmpreg = FMC_Bank5_6_R->SDRTR;\r
+ FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));\r
+\r
+ /* Disable write protection */\r
+ tmpreg = FMC_Bank5_6_R->SDCR[1]; \r
+ FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);\r
+\r
+ /*FMC controller Enable*/\r
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;\r
+ \r
+ (void)(tmp);\r
+}\r
+#endif /* DATA_IN_ExtSDRAM */\r
+\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
* This is the only clock brought over from the Mi-V Soft processor Libero design.\r
*/\r
#ifndef SYS_CLK_FREQ\r
-#define SYS_CLK_FREQ 70000000UL\r
+#define SYS_CLK_FREQ 66000000UL\r
#endif\r
\r
/***************************************************************************//**\r
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