2 ******************************************************************************
\r
3 * @file stm32h7xx_hal_rcc.h
\r
4 * @author MCD Application Team
\r
5 * @brief Header file of RCC HAL module.
\r
6 ******************************************************************************
\r
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
\r
10 * All rights reserved.</center></h2>
\r
12 * This software component is licensed by ST under BSD 3-Clause license,
\r
13 * the "License"; You may not use this file except in compliance with the
\r
14 * License. You may obtain a copy of the License at:
\r
15 * opensource.org/licenses/BSD-3-Clause
\r
17 ******************************************************************************
\r
20 /* Define to prevent recursive inclusion -------------------------------------*/
\r
21 #ifndef STM32H7xx_HAL_RCC_H
\r
22 #define STM32H7xx_HAL_RCC_H
\r
28 /* Includes ------------------------------------------------------------------*/
\r
29 #include "stm32h7xx_hal_def.h"
\r
31 /** @addtogroup STM32H7xx_HAL_Driver
\r
39 /* Exported types ------------------------------------------------------------*/
\r
41 /** @defgroup RCC_Exported_Types RCC Exported Types
\r
46 * @brief RCC PLL configuration structure definition
\r
50 uint32_t PLLState; /*!< The new state of the PLL.
\r
51 This parameter can be a value of @ref RCC_PLL_Config */
\r
53 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
\r
54 This parameter must be a value of @ref RCC_PLL_Clock_Source */
\r
56 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
\r
57 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
\r
59 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
\r
60 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
\r
62 uint32_t PLLP; /*!< PLLP: Division factor for system clock.
\r
63 This parameter must be a number between Min_Data = 2 and Max_Data = 128
\r
64 odd division factors are not allowed */
\r
66 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks.
\r
67 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
\r
69 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks.
\r
70 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
\r
71 uint32_t PLLRGE; /*!<PLLRGE: PLL1 clock Input range
\r
72 This parameter must be a value of @ref RCC_PLL1_VCI_Range */
\r
73 uint32_t PLLVCOSEL; /*!<PLLVCOSEL: PLL1 clock Output range
\r
74 This parameter must be a value of @ref RCC_PLL1_VCO_Range */
\r
76 uint32_t PLLFRACN; /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
\r
77 PLL1 VCO It should be a value between 0 and 8191 */
\r
79 }RCC_PLLInitTypeDef;
\r
83 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
\r
87 uint32_t OscillatorType; /*!< The oscillators to be configured.
\r
88 This parameter can be a value of @ref RCC_Oscillator_Type */
\r
90 uint32_t HSEState; /*!< The new state of the HSE.
\r
91 This parameter can be a value of @ref RCC_HSE_Config */
\r
93 uint32_t LSEState; /*!< The new state of the LSE.
\r
94 This parameter can be a value of @ref RCC_LSE_Config */
\r
96 uint32_t HSIState; /*!< The new state of the HSI.
\r
97 This parameter can be a value of @ref RCC_HSI_Config */
\r
99 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
\r
100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y
\r
101 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */
\r
103 uint32_t LSIState; /*!< The new state of the LSI.
\r
104 This parameter can be a value of @ref RCC_LSI_Config */
\r
106 uint32_t HSI48State; /*!< The new state of the HSI48.
\r
107 This parameter can be a value of @ref RCC_HSI48_Config */
\r
109 uint32_t CSIState; /*!< The new state of the CSI.
\r
110 This parameter can be a value of @ref RCC_CSI_Config */
\r
112 uint32_t CSICalibrationValue; /*!< The calibration trimming value.
\r
113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y
\r
114 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */
\r
116 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
\r
118 }RCC_OscInitTypeDef;
\r
121 * @brief RCC System, AHB and APB busses clock configuration structure definition
\r
125 uint32_t ClockType; /*!< The clock to be configured.
\r
126 This parameter can be a value of @ref RCC_System_Clock_Type */
\r
128 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
\r
129 This parameter can be a value of @ref RCC_System_Clock_Source */
\r
131 uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be
\r
132 a value of @ref RCC_SYS_Clock_Source */
\r
134 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
\r
135 This parameter can be a value of @ref RCC_HCLK_Clock_Source */
\r
137 uint32_t APB3CLKDivider; /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
\r
138 This parameter can be a value of @ref RCC_APB3_Clock_Source */
\r
140 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
\r
141 This parameter can be a value of @ref RCC_APB1_Clock_Source */
\r
142 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
\r
143 This parameter can be a value of @ref RCC_APB2_Clock_Source */
\r
144 uint32_t APB4CLKDivider; /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
\r
145 This parameter can be a value of @ref RCC_APB4_Clock_Source */
\r
146 }RCC_ClkInitTypeDef;
\r
152 /* Exported constants --------------------------------------------------------*/
\r
154 /** @defgroup RCC_Exported_Constants RCC Exported Constants
\r
158 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
\r
161 #define RCC_OSCILLATORTYPE_NONE (0x00000000U)
\r
162 #define RCC_OSCILLATORTYPE_HSE (0x00000001U)
\r
163 #define RCC_OSCILLATORTYPE_HSI (0x00000002U)
\r
164 #define RCC_OSCILLATORTYPE_LSE (0x00000004U)
\r
165 #define RCC_OSCILLATORTYPE_LSI (0x00000008U)
\r
166 #define RCC_OSCILLATORTYPE_CSI (0x00000010U)
\r
167 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
\r
173 /** @defgroup RCC_HSE_Config RCC HSE Config
\r
176 #define RCC_HSE_OFF (0x00000000U)
\r
177 #define RCC_HSE_ON RCC_CR_HSEON
\r
178 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
\r
184 /** @defgroup RCC_LSE_Config RCC LSE Config
\r
187 #define RCC_LSE_OFF (0x00000000U)
\r
188 #define RCC_LSE_ON RCC_BDCR_LSEON
\r
189 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
\r
195 /** @defgroup RCC_HSI_Config RCC HSI Config
\r
198 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
\r
199 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
\r
201 #define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
\r
202 #define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
\r
203 #define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
\r
204 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */
\r
208 #define RCC_HSICALIBRATION_DEFAULT (0x20U) /* Default HSI calibration trimming value */
\r
213 /** @defgroup RCC_HSI48_Config RCC HSI48 Config
\r
216 #define RCC_HSI48_OFF ((uint8_t)0x00)
\r
217 #define RCC_HSI48_ON ((uint8_t)0x01)
\r
223 /** @defgroup RCC_LSI_Config RCC LSI Config
\r
226 #define RCC_LSI_OFF (0x00000000U)
\r
227 #define RCC_LSI_ON RCC_CSR_LSION
\r
233 /** @defgroup RCC_CSI_Config RCC CSI Config
\r
236 #define RCC_CSI_OFF (0x00000000U)
\r
237 #define RCC_CSI_ON RCC_CR_CSION
\r
239 #define RCC_CSICALIBRATION_DEFAULT (0x10U) /* Default CSI calibration trimming value */
\r
245 /** @defgroup RCC_PLL_Config RCC PLL Config
\r
248 #define RCC_PLL_NONE (0x00000000U)
\r
249 #define RCC_PLL_OFF (0x00000001U)
\r
250 #define RCC_PLL_ON (0x00000002U)
\r
257 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
\r
260 #define RCC_PLLSOURCE_HSI (0x00000000U)
\r
261 #define RCC_PLLSOURCE_CSI (0x00000001U)
\r
262 #define RCC_PLLSOURCE_HSE (0x00000002U)
\r
263 #define RCC_PLLSOURCE_NONE (0x00000003U)
\r
268 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output
\r
271 #define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
\r
272 #define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
\r
273 #define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN
\r
281 /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range
\r
284 #define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
\r
285 #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
\r
286 #define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
\r
287 #define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3
\r
295 /** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range
\r
298 #define RCC_PLL1VCOWIDE (0x00000000U)
\r
299 #define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL
\r
306 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
\r
309 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U)
\r
310 #define RCC_CLOCKTYPE_HCLK (0x00000002U)
\r
311 #define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)
\r
312 #define RCC_CLOCKTYPE_PCLK1 (0x00000008U)
\r
313 #define RCC_CLOCKTYPE_PCLK2 (0x00000010U)
\r
314 #define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)
\r
320 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
\r
323 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
\r
324 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
\r
325 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
\r
326 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1
\r
332 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
\r
335 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */
\r
336 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
\r
337 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
\r
338 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */
\r
343 /** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source
\r
346 #define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1
\r
347 #define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2
\r
348 #define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4
\r
349 #define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8
\r
350 #define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16
\r
351 #define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64
\r
352 #define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128
\r
353 #define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256
\r
354 #define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512
\r
361 /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source
\r
364 #define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1
\r
365 #define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2
\r
366 #define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4
\r
367 #define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8
\r
368 #define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16
\r
369 #define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64
\r
370 #define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128
\r
371 #define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256
\r
372 #define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512
\r
378 /** @defgroup RCC_APB3_Clock_Source RCC APB3 Clock Source
\r
381 #define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1
\r
382 #define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2
\r
383 #define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4
\r
384 #define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8
\r
385 #define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16
\r
391 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
\r
394 #define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1
\r
395 #define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2
\r
396 #define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4
\r
397 #define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8
\r
398 #define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16
\r
404 /** @defgroup RCC_APB2_Clock_Source RCC APB2 Clock Source
\r
407 #define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1
\r
408 #define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2
\r
409 #define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4
\r
410 #define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8
\r
411 #define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16
\r
417 /** @defgroup RCC_APB4_Clock_Source RCC APB4 Clock Source
\r
420 #define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1
\r
421 #define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2
\r
422 #define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4
\r
423 #define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8
\r
424 #define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16
\r
430 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
\r
433 #define RCC_RTCCLKSOURCE_LSE (0x00000100U)
\r
434 #define RCC_RTCCLKSOURCE_LSI (0x00000200U)
\r
435 #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)
\r
436 #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)
\r
437 #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)
\r
438 #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)
\r
439 #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)
\r
440 #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)
\r
441 #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)
\r
442 #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)
\r
443 #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)
\r
444 #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)
\r
445 #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)
\r
446 #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)
\r
447 #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)
\r
448 #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)
\r
449 #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)
\r
450 #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)
\r
451 #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)
\r
452 #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)
\r
453 #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)
\r
454 #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)
\r
455 #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)
\r
456 #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)
\r
457 #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)
\r
458 #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)
\r
459 #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)
\r
460 #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)
\r
461 #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)
\r
462 #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)
\r
463 #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)
\r
464 #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)
\r
465 #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)
\r
466 #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)
\r
467 #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)
\r
468 #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)
\r
469 #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)
\r
470 #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)
\r
471 #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)
\r
472 #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)
\r
473 #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)
\r
474 #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)
\r
475 #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)
\r
476 #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)
\r
477 #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)
\r
478 #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)
\r
479 #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)
\r
480 #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)
\r
481 #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)
\r
482 #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)
\r
483 #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)
\r
484 #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)
\r
485 #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)
\r
486 #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)
\r
487 #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)
\r
488 #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)
\r
489 #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)
\r
490 #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)
\r
491 #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)
\r
492 #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)
\r
493 #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)
\r
494 #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)
\r
495 #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)
\r
496 #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)
\r
504 /** @defgroup RCC_MCO_Index RCC MCO Index
\r
507 #define RCC_MCO1 (0x00000000U)
\r
508 #define RCC_MCO2 (0x00000001U)
\r
514 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
\r
517 #define RCC_MCO1SOURCE_HSI (0x00000000U)
\r
518 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
\r
519 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
\r
520 #define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
\r
521 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2
\r
527 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
\r
530 #define RCC_MCO2SOURCE_SYSCLK (0x00000000U)
\r
531 #define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
\r
532 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
\r
533 #define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
\r
534 #define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
\r
535 #define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
\r
541 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCOx Clock Prescaler
\r
544 #define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
\r
545 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
\r
546 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
\r
547 #define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
\r
548 #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
\r
549 #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
\r
550 #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
\r
551 #define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
\r
552 #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
\r
553 #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
\r
554 #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
\r
555 #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
\r
556 #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
\r
557 #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
\r
558 #define RCC_MCODIV_15 RCC_CFGR_MCO1PRE
\r
565 /** @defgroup RCC_Interrupt RCC Interrupt
\r
568 #define RCC_IT_LSIRDY (0x00000001U)
\r
569 #define RCC_IT_LSERDY (0x00000002U)
\r
570 #define RCC_IT_HSIRDY (0x00000004U)
\r
571 #define RCC_IT_HSERDY (0x00000008U)
\r
572 #define RCC_IT_CSIRDY (0x00000010U)
\r
573 #define RCC_IT_HSI48RDY (0x00000020U)
\r
574 #define RCC_IT_PLLRDY (0x00000040U)
\r
575 #define RCC_IT_PLL2RDY (0x00000080U)
\r
576 #define RCC_IT_PLL3RDY (0x00000100U)
\r
577 #define RCC_IT_LSECSS (0x00000200U)
\r
578 #define RCC_IT_CSS (0x00000400U)
\r
583 /** @defgroup RCC_Flag RCC Flag
\r
584 * Elements values convention: XXXYYYYYb
\r
585 * - YYYYY : Flag position in the register
\r
586 * - XXX : Register index
\r
587 * - 001: CR register
\r
588 * - 010: BDCR register
\r
589 * - 011: CSR register
\r
590 * - 100: RSR register
\r
593 /* Flags in the CR register */
\r
594 #define RCC_FLAG_HSIRDY ((uint8_t)0x22)
\r
595 #define RCC_FLAG_HSIDIV ((uint8_t)0x25)
\r
596 #define RCC_FLAG_CSIRDY ((uint8_t)0x28)
\r
597 #define RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
\r
598 #define RCC_FLAG_D1CKRDY ((uint8_t)0x2E)
\r
599 #define RCC_FLAG_D2CKRDY ((uint8_t)0x2F)
\r
600 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
\r
601 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
\r
602 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
\r
603 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
\r
604 /* Flags in the BDCR register */
\r
605 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
\r
607 /* Flags in the CSR register */
\r
608 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
\r
610 /* Flags in the RSR register */
\r
611 #define RCC_FLAG_CPURST ((uint8_t)0x91)
\r
613 #define RCC_FLAG_D1RST ((uint8_t)0x93)
\r
614 #define RCC_FLAG_D2RST ((uint8_t)0x94)
\r
615 #define RCC_FLAG_BORRST ((uint8_t)0x95)
\r
616 #define RCC_FLAG_PINRST ((uint8_t)0x96)
\r
617 #define RCC_FLAG_PORRST ((uint8_t)0x97)
\r
618 #define RCC_FLAG_SFTRST ((uint8_t)0x98)
\r
619 #define RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
\r
620 #define RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
\r
621 #define RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
\r
622 #define RCC_FLAG_LPWR2RST ((uint8_t)0x9F)
\r
624 #if defined(DUAL_CORE)
\r
625 #define RCC_FLAG_C1RST (RCC_FLAG_CPURST)
\r
626 #define RCC_FLAG_C2RST ((uint8_t)0x92)
\r
627 #define RCC_FLAG_SFTR1ST (RCC_FLAG_SFTRST)
\r
628 #define RCC_FLAG_SFTR2ST ((uint8_t)0x99)
\r
629 #define RCC_FLAG_WWDG2RST ((uint8_t)0x9D)
\r
630 #define RCC_FLAG_IWDG2RST ((uint8_t)0x9B)
\r
631 #endif /*DUAL_CORE*/
\r
638 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
\r
641 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */
\r
642 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
\r
643 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
\r
644 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
\r
649 /** @defgroup RCC_Stop_WakeUpClock RCC Stop WakeUpClock
\r
652 #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)
\r
653 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK
\r
659 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock
\r
662 #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)
\r
663 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK
\r
673 /* Exported macros -----------------------------------------------------------*/
\r
675 /** @defgroup RCC_Exported_Macros RCC Exported Macros
\r
679 /** @brief Enable or disable the AHB3 peripheral clock.
\r
680 * @note After reset, the peripheral clock (used for registers read/write access)
\r
681 * is disabled and the application software has to enable this clock before
\r
684 #define __HAL_RCC_MDMA_CLK_ENABLE() do { \
\r
685 __IO uint32_t tmpreg; \
\r
686 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
\r
687 /* Delay after an RCC peripheral clock enabling */ \
\r
688 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
\r
692 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
\r
693 __IO uint32_t tmpreg; \
\r
694 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
\r
695 /* Delay after an RCC peripheral clock enabling */ \
\r
696 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
\r
700 #define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \
\r
701 __IO uint32_t tmpreg; \
\r
702 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
\r
703 /* Delay after an RCC peripheral clock enabling */ \
\r
704 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
\r
710 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
\r
711 __IO uint32_t tmpreg; \
\r
712 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
713 /* Delay after an RCC peripheral clock enabling */ \
\r
714 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
718 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
\r
719 __IO uint32_t tmpreg; \
\r
720 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
721 /* Delay after an RCC peripheral clock enabling */ \
\r
722 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
726 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
\r
727 __IO uint32_t tmpreg; \
\r
728 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
\r
729 /* Delay after an RCC peripheral clock enabling */ \
\r
730 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
\r
735 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
\r
736 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
\r
739 #define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
\r
742 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
\r
743 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
\r
744 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
\r
747 /** @brief Get the enable or disable status of the AHB3 peripheral clock
\r
748 * @note After reset, the peripheral clock (used for registers read/write access)
\r
749 * is disabled and the application software has to enable this clock before
\r
753 #define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
\r
754 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)
\r
757 #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
\r
760 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)
\r
761 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U)
\r
762 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
\r
764 #define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)
\r
765 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)
\r
768 #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
\r
771 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)
\r
772 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U)
\r
773 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
\r
776 /** @brief Enable or disable the AHB1 peripheral clock.
\r
777 * @note After reset, the peripheral clock (used for registers read/write access)
\r
778 * is disabled and the application software has to enable this clock before
\r
782 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
\r
783 __IO uint32_t tmpreg; \
\r
784 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
\r
785 /* Delay after an RCC peripheral clock enabling */ \
\r
786 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
\r
790 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
\r
791 __IO uint32_t tmpreg; \
\r
792 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
793 /* Delay after an RCC peripheral clock enabling */ \
\r
794 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
798 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \
\r
799 __IO uint32_t tmpreg; \
\r
800 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
\r
801 /* Delay after an RCC peripheral clock enabling */ \
\r
802 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
\r
806 #if defined(DUAL_CORE)
\r
807 #define __HAL_RCC_ART_CLK_ENABLE() do { \
\r
808 __IO uint32_t tmpreg; \
\r
809 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
\r
810 /* Delay after an RCC peripheral clock enabling */ \
\r
811 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
\r
814 #endif /*DUAL_CORE*/
\r
816 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \
\r
817 __IO uint32_t tmpreg; \
\r
818 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
\r
819 /* Delay after an RCC peripheral clock enabling */ \
\r
820 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
\r
824 #define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \
\r
825 __IO uint32_t tmpreg; \
\r
826 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
\r
827 /* Delay after an RCC peripheral clock enabling */ \
\r
828 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
\r
832 #define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \
\r
833 __IO uint32_t tmpreg; \
\r
834 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
\r
835 /* Delay after an RCC peripheral clock enabling */ \
\r
836 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
\r
840 #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \
\r
841 __IO uint32_t tmpreg; \
\r
842 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
\r
843 /* Delay after an RCC peripheral clock enabling */ \
\r
844 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
\r
848 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
\r
849 __IO uint32_t tmpreg; \
\r
850 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
\r
851 /* Delay after an RCC peripheral clock enabling */ \
\r
852 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
\r
856 #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \
\r
857 __IO uint32_t tmpreg; \
\r
858 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
\r
859 /* Delay after an RCC peripheral clock enabling */ \
\r
860 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
\r
864 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
\r
865 __IO uint32_t tmpreg; \
\r
866 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
\r
867 /* Delay after an RCC peripheral clock enabling */ \
\r
868 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
\r
872 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
\r
873 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
\r
874 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
\r
875 #if defined(DUAL_CORE)
\r
876 #define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
\r
877 #endif /*DUAL_CORE*/
\r
878 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
\r
879 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
\r
880 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
\r
881 #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
\r
882 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
\r
883 #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
\r
884 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
\r
887 /** @brief Get the enable or disable status of the AHB1 peripheral clock
\r
888 * @note After reset, the peripheral clock (used for registers read/write access)
\r
889 * is disabled and the application software has to enable this clock before
\r
893 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)
\r
894 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)
\r
895 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)
\r
896 #if defined(DUAL_CORE)
\r
897 #define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U)
\r
898 #endif /*DUAL_CORE*/
\r
899 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U)
\r
900 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U)
\r
901 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U)
\r
902 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)
\r
903 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
\r
904 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U)
\r
905 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
\r
907 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)
\r
908 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)
\r
909 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)
\r
910 #if defined(DUAL_CORE)
\r
911 #define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U)
\r
912 #endif /*DUAL_CORE*/
\r
913 #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U)
\r
914 #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U)
\r
915 #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U)
\r
916 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)
\r
917 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
\r
918 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U)
\r
919 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
\r
921 /** @brief Enable or disable the AHB2 peripheral clock.
\r
922 * @note After reset, the peripheral clock (used for registers read/write access)
\r
923 * is disabled and the application software has to enable this clock before
\r
927 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
\r
928 __IO uint32_t tmpreg; \
\r
929 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
930 /* Delay after an RCC peripheral clock enabling */ \
\r
931 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
935 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
\r
936 __IO uint32_t tmpreg; \
\r
937 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
938 /* Delay after an RCC peripheral clock enabling */ \
\r
939 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
943 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
\r
944 __IO uint32_t tmpreg; \
\r
945 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
946 /* Delay after an RCC peripheral clock enabling */ \
\r
947 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
951 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
\r
952 __IO uint32_t tmpreg; \
\r
953 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
954 /* Delay after an RCC peripheral clock enabling */ \
\r
955 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
959 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
\r
960 __IO uint32_t tmpreg; \
\r
961 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
\r
962 /* Delay after an RCC peripheral clock enabling */ \
\r
963 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
\r
967 #define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \
\r
968 __IO uint32_t tmpreg; \
\r
969 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
\r
970 /* Delay after an RCC peripheral clock enabling */ \
\r
971 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
\r
975 #define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \
\r
976 __IO uint32_t tmpreg; \
\r
977 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
\r
978 /* Delay after an RCC peripheral clock enabling */ \
\r
979 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
\r
983 #define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \
\r
984 __IO uint32_t tmpreg; \
\r
985 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
\r
986 /* Delay after an RCC peripheral clock enabling */ \
\r
987 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
\r
991 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
\r
992 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
\r
993 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
\r
994 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
\r
995 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
\r
996 #define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
\r
997 #define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
\r
998 #define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
\r
1001 /** @brief Get the enable or disable status of the AHB2 peripheral clock
\r
1002 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1003 * is disabled and the application software has to enable this clock before
\r
1007 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)
\r
1008 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)
\r
1009 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)
\r
1010 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
\r
1011 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
\r
1012 #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
\r
1013 #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
\r
1014 #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
\r
1016 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)
\r
1017 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)
\r
1018 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)
\r
1019 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
\r
1020 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
\r
1021 #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
\r
1022 #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
\r
1023 #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
\r
1025 /** @brief Enable or disable the AHB4 peripheral clock.
\r
1026 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1027 * is disabled and the application software has to enable this clock before
\r
1031 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
\r
1032 __IO uint32_t tmpreg; \
\r
1033 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
\r
1034 /* Delay after an RCC peripheral clock enabling */ \
\r
1035 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
\r
1039 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
\r
1040 __IO uint32_t tmpreg; \
\r
1041 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
\r
1042 /* Delay after an RCC peripheral clock enabling */ \
\r
1043 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
\r
1047 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
\r
1048 __IO uint32_t tmpreg; \
\r
1049 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
\r
1050 /* Delay after an RCC peripheral clock enabling */ \
\r
1051 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
\r
1055 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
\r
1056 __IO uint32_t tmpreg; \
\r
1057 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
\r
1058 /* Delay after an RCC peripheral clock enabling */ \
\r
1059 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
\r
1063 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
\r
1064 __IO uint32_t tmpreg; \
\r
1065 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
\r
1066 /* Delay after an RCC peripheral clock enabling */ \
\r
1067 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
\r
1071 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
\r
1072 __IO uint32_t tmpreg; \
\r
1073 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
\r
1074 /* Delay after an RCC peripheral clock enabling */ \
\r
1075 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
\r
1079 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
\r
1080 __IO uint32_t tmpreg; \
\r
1081 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
\r
1082 /* Delay after an RCC peripheral clock enabling */ \
\r
1083 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
\r
1087 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
\r
1088 __IO uint32_t tmpreg; \
\r
1089 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
\r
1090 /* Delay after an RCC peripheral clock enabling */ \
\r
1091 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
\r
1095 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
\r
1096 __IO uint32_t tmpreg; \
\r
1097 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
\r
1098 /* Delay after an RCC peripheral clock enabling */ \
\r
1099 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
\r
1103 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
\r
1104 __IO uint32_t tmpreg; \
\r
1105 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
\r
1106 /* Delay after an RCC peripheral clock enabling */ \
\r
1107 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
\r
1111 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
\r
1112 __IO uint32_t tmpreg; \
\r
1113 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
\r
1114 /* Delay after an RCC peripheral clock enabling */ \
\r
1115 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
\r
1119 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
\r
1120 __IO uint32_t tmpreg; \
\r
1121 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
\r
1122 /* Delay after an RCC peripheral clock enabling */ \
\r
1123 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
\r
1127 #define __HAL_RCC_BDMA_CLK_ENABLE() do { \
\r
1128 __IO uint32_t tmpreg; \
\r
1129 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
\r
1130 /* Delay after an RCC peripheral clock enabling */ \
\r
1131 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
\r
1135 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
\r
1136 __IO uint32_t tmpreg; \
\r
1137 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
\r
1138 /* Delay after an RCC peripheral clock enabling */ \
\r
1139 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
\r
1143 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \
\r
1144 __IO uint32_t tmpreg; \
\r
1145 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
\r
1146 /* Delay after an RCC peripheral clock enabling */ \
\r
1147 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
\r
1151 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \
\r
1152 __IO uint32_t tmpreg; \
\r
1153 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
\r
1154 /* Delay after an RCC peripheral clock enabling */ \
\r
1155 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
\r
1160 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
\r
1161 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
\r
1162 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
\r
1163 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
\r
1164 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
\r
1165 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
\r
1166 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
\r
1167 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
\r
1168 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
\r
1169 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
\r
1170 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
\r
1171 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
\r
1172 #define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
\r
1173 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
\r
1174 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
\r
1175 #define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
\r
1178 /** @brief Get the enable or disable status of the AHB4 peripheral clock
\r
1179 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1180 * is disabled and the application software has to enable this clock before
\r
1184 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)
\r
1185 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)
\r
1186 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)
\r
1187 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)
\r
1188 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)
\r
1189 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)
\r
1190 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)
\r
1191 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)
\r
1192 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)
\r
1193 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)
\r
1194 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)
\r
1195 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U)
\r
1196 #define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U)
\r
1197 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U)
\r
1198 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U)
\r
1199 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
\r
1201 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)
\r
1202 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)
\r
1203 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)
\r
1204 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)
\r
1205 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)
\r
1206 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)
\r
1207 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)
\r
1208 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)
\r
1209 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)
\r
1210 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)
\r
1211 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)
\r
1212 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U)
\r
1213 #define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U)
\r
1214 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U)
\r
1215 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U)
\r
1216 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
\r
1219 /** @brief Enable or disable the APB3 peripheral clock.
\r
1220 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1221 * is disabled and the application software has to enable this clock before
\r
1226 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
\r
1227 __IO uint32_t tmpreg; \
\r
1228 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
\r
1229 /* Delay after an RCC peripheral clock enabling */ \
\r
1230 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
\r
1236 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
\r
1237 __IO uint32_t tmpreg; \
\r
1238 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
\r
1239 /* Delay after an RCC peripheral clock enabling */ \
\r
1240 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
\r
1245 #define __HAL_RCC_WWDG1_CLK_ENABLE() do { \
\r
1246 __IO uint32_t tmpreg; \
\r
1247 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
\r
1248 /* Delay after an RCC peripheral clock enabling */ \
\r
1249 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
\r
1254 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
\r
1258 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
\r
1260 #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
\r
1263 /** @brief Get the enable or disable status of the APB3 peripheral clock
\r
1264 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1265 * is disabled and the application software has to enable this clock before
\r
1269 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U)
\r
1273 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U)
\r
1275 #define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
\r
1278 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U)
\r
1282 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U)
\r
1284 #define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
\r
1288 /** @brief Enable or disable the APB1 peripheral clock.
\r
1289 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1290 * is disabled and the application software has to enable this clock before
\r
1294 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
\r
1295 __IO uint32_t tmpreg; \
\r
1296 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
\r
1297 /* Delay after an RCC peripheral clock enabling */ \
\r
1298 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
\r
1302 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
\r
1303 __IO uint32_t tmpreg; \
\r
1304 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
\r
1305 /* Delay after an RCC peripheral clock enabling */ \
\r
1306 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
\r
1310 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
\r
1311 __IO uint32_t tmpreg; \
\r
1312 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
\r
1313 /* Delay after an RCC peripheral clock enabling */ \
\r
1314 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
\r
1318 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
\r
1319 __IO uint32_t tmpreg; \
\r
1320 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
\r
1321 /* Delay after an RCC peripheral clock enabling */ \
\r
1322 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
\r
1326 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
\r
1327 __IO uint32_t tmpreg; \
\r
1328 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
\r
1329 /* Delay after an RCC peripheral clock enabling */ \
\r
1330 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
\r
1334 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
\r
1335 __IO uint32_t tmpreg; \
\r
1336 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
\r
1337 /* Delay after an RCC peripheral clock enabling */ \
\r
1338 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
\r
1342 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
\r
1343 __IO uint32_t tmpreg; \
\r
1344 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
\r
1345 /* Delay after an RCC peripheral clock enabling */ \
\r
1346 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
\r
1350 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
\r
1351 __IO uint32_t tmpreg; \
\r
1352 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
\r
1353 /* Delay after an RCC peripheral clock enabling */ \
\r
1354 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
\r
1358 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
\r
1359 __IO uint32_t tmpreg; \
\r
1360 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
\r
1361 /* Delay after an RCC peripheral clock enabling */ \
\r
1362 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
\r
1366 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
\r
1367 __IO uint32_t tmpreg; \
\r
1368 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
\r
1369 /* Delay after an RCC peripheral clock enabling */ \
\r
1370 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
\r
1374 #if defined(DUAL_CORE)
\r
1375 #define __HAL_RCC_WWDG2_CLK_ENABLE() do { \
\r
1376 __IO uint32_t tmpreg; \
\r
1377 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
\r
1378 /* Delay after an RCC peripheral clock enabling */ \
\r
1379 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
\r
1382 #endif /*DUAL_CORE*/
\r
1384 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
\r
1385 __IO uint32_t tmpreg; \
\r
1386 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
\r
1387 /* Delay after an RCC peripheral clock enabling */ \
\r
1388 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
\r
1392 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
\r
1393 __IO uint32_t tmpreg; \
\r
1394 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
\r
1395 /* Delay after an RCC peripheral clock enabling */ \
\r
1396 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
\r
1400 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
\r
1401 __IO uint32_t tmpreg; \
\r
1402 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
\r
1403 /* Delay after an RCC peripheral clock enabling */ \
\r
1404 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
\r
1408 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
\r
1409 __IO uint32_t tmpreg; \
\r
1410 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
\r
1411 /* Delay after an RCC peripheral clock enabling */ \
\r
1412 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
\r
1416 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
\r
1417 __IO uint32_t tmpreg; \
\r
1418 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
\r
1419 /* Delay after an RCC peripheral clock enabling */ \
\r
1420 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
\r
1424 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
\r
1425 __IO uint32_t tmpreg; \
\r
1426 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
\r
1427 /* Delay after an RCC peripheral clock enabling */ \
\r
1428 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
\r
1432 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
\r
1433 __IO uint32_t tmpreg; \
\r
1434 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
\r
1435 /* Delay after an RCC peripheral clock enabling */ \
\r
1436 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
\r
1440 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
\r
1441 __IO uint32_t tmpreg; \
\r
1442 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
\r
1443 /* Delay after an RCC peripheral clock enabling */ \
\r
1444 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
\r
1448 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
\r
1449 __IO uint32_t tmpreg; \
\r
1450 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
\r
1451 /* Delay after an RCC peripheral clock enabling */ \
\r
1452 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
\r
1456 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
\r
1457 __IO uint32_t tmpreg; \
\r
1458 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
\r
1459 /* Delay after an RCC peripheral clock enabling */ \
\r
1460 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
\r
1464 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
\r
1465 __IO uint32_t tmpreg; \
\r
1466 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
\r
1467 /* Delay after an RCC peripheral clock enabling */ \
\r
1468 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
\r
1472 #define __HAL_RCC_DAC12_CLK_ENABLE() do { \
\r
1473 __IO uint32_t tmpreg; \
\r
1474 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
\r
1475 /* Delay after an RCC peripheral clock enabling */ \
\r
1476 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
\r
1480 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
\r
1481 __IO uint32_t tmpreg; \
\r
1482 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
\r
1483 /* Delay after an RCC peripheral clock enabling */ \
\r
1484 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
\r
1488 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
\r
1489 __IO uint32_t tmpreg; \
\r
1490 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
\r
1491 /* Delay after an RCC peripheral clock enabling */ \
\r
1492 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
\r
1496 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
\r
1497 __IO uint32_t tmpreg; \
\r
1498 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
\r
1499 /* Delay after an RCC peripheral clock enabling */ \
\r
1500 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
\r
1504 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
\r
1505 __IO uint32_t tmpreg; \
\r
1506 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
\r
1507 /* Delay after an RCC peripheral clock enabling */ \
\r
1508 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
\r
1512 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
\r
1513 __IO uint32_t tmpreg; \
\r
1514 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
\r
1515 /* Delay after an RCC peripheral clock enabling */ \
\r
1516 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
\r
1520 #define __HAL_RCC_MDIOS_CLK_ENABLE() do { \
\r
1521 __IO uint32_t tmpreg; \
\r
1522 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
\r
1523 /* Delay after an RCC peripheral clock enabling */ \
\r
1524 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
\r
1528 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
\r
1529 __IO uint32_t tmpreg; \
\r
1530 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
\r
1531 /* Delay after an RCC peripheral clock enabling */ \
\r
1532 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
\r
1537 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
\r
1538 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
\r
1539 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
\r
1540 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
\r
1541 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
\r
1542 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
\r
1543 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
\r
1544 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
\r
1545 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
\r
1546 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
\r
1548 #if defined(DUAL_CORE)
\r
1549 #define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
\r
1550 #endif /*DUAL_CORE*/
\r
1552 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
\r
1553 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
\r
1554 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
\r
1555 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
\r
1556 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
\r
1557 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
\r
1558 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
\r
1559 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
\r
1560 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
\r
1561 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
\r
1562 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
\r
1563 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
\r
1564 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
\r
1565 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
\r
1566 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
\r
1567 #define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
\r
1568 #define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
\r
1569 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
\r
1570 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
\r
1573 /** @brief Get the enable or disable status of the APB1 peripheral clock
\r
1574 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1575 * is disabled and the application software has to enable this clock before
\r
1579 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)
\r
1580 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)
\r
1581 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)
\r
1582 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)
\r
1583 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)
\r
1584 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)
\r
1585 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)
\r
1586 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)
\r
1587 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)
\r
1588 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)
\r
1589 #if defined(DUAL_CORE)
\r
1590 #define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U)
\r
1591 #endif /*DUAL_CORE*/
\r
1592 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)
\r
1593 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)
\r
1594 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
\r
1595 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)
\r
1596 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)
\r
1597 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)
\r
1598 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)
\r
1599 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)
\r
1600 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)
\r
1601 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)
\r
1602 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)
\r
1603 #define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)
\r
1604 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)
\r
1605 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)
\r
1606 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)
\r
1607 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)
\r
1608 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)
\r
1609 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)
\r
1610 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)
\r
1612 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)
\r
1613 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)
\r
1614 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)
\r
1615 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)
\r
1616 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)
\r
1617 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)
\r
1618 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)
\r
1619 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)
\r
1620 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)
\r
1621 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)
\r
1622 #if defined(DUAL_CORE)
\r
1623 #define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U)
\r
1624 #endif /*DUAL_CORE*/
\r
1625 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)
\r
1626 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)
\r
1627 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
\r
1628 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)
\r
1629 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)
\r
1630 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)
\r
1631 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)
\r
1632 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)
\r
1633 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)
\r
1634 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)
\r
1635 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)
\r
1636 #define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)
\r
1637 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)
\r
1638 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)
\r
1639 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)
\r
1640 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)
\r
1641 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)
\r
1642 #define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)
\r
1643 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)
\r
1646 /** @brief Enable or disable the APB2 peripheral clock.
\r
1647 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1648 * is disabled and the application software has to enable this clock before
\r
1652 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
\r
1653 __IO uint32_t tmpreg; \
\r
1654 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
1655 /* Delay after an RCC peripheral clock enabling */ \
\r
1656 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
1660 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
\r
1661 __IO uint32_t tmpreg; \
\r
1662 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
1663 /* Delay after an RCC peripheral clock enabling */ \
\r
1664 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
1668 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
\r
1669 __IO uint32_t tmpreg; \
\r
1670 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
1671 /* Delay after an RCC peripheral clock enabling */ \
\r
1672 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
1676 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
\r
1677 __IO uint32_t tmpreg; \
\r
1678 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
1679 /* Delay after an RCC peripheral clock enabling */ \
\r
1680 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
1684 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
\r
1685 __IO uint32_t tmpreg; \
\r
1686 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
1687 /* Delay after an RCC peripheral clock enabling */ \
\r
1688 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
1692 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
\r
1693 __IO uint32_t tmpreg; \
\r
1694 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
1695 /* Delay after an RCC peripheral clock enabling */ \
\r
1696 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
1700 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
\r
1701 __IO uint32_t tmpreg; \
\r
1702 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
\r
1703 /* Delay after an RCC peripheral clock enabling */ \
\r
1704 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
\r
1708 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
\r
1709 __IO uint32_t tmpreg; \
\r
1710 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
\r
1711 /* Delay after an RCC peripheral clock enabling */ \
\r
1712 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
\r
1716 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
\r
1717 __IO uint32_t tmpreg; \
\r
1718 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
\r
1719 /* Delay after an RCC peripheral clock enabling */ \
\r
1720 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
\r
1724 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
\r
1725 __IO uint32_t tmpreg; \
\r
1726 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
1727 /* Delay after an RCC peripheral clock enabling */ \
\r
1728 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
1732 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
\r
1733 __IO uint32_t tmpreg; \
\r
1734 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
1735 /* Delay after an RCC peripheral clock enabling */ \
\r
1736 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
1740 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
\r
1741 __IO uint32_t tmpreg; \
\r
1742 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
1743 /* Delay after an RCC peripheral clock enabling */ \
\r
1744 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
1748 #define __HAL_RCC_SAI3_CLK_ENABLE() do { \
\r
1749 __IO uint32_t tmpreg; \
\r
1750 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
\r
1751 /* Delay after an RCC peripheral clock enabling */ \
\r
1752 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
\r
1756 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
\r
1757 __IO uint32_t tmpreg; \
\r
1758 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
\r
1759 /* Delay after an RCC peripheral clock enabling */ \
\r
1760 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
\r
1764 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
\r
1765 __IO uint32_t tmpreg; \
\r
1766 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
\r
1767 /* Delay after an RCC peripheral clock enabling */ \
\r
1768 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
\r
1772 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
\r
1773 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
\r
1774 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
\r
1775 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
\r
1776 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
\r
1777 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
\r
1778 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
\r
1779 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
\r
1780 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
\r
1781 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
\r
1782 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
\r
1783 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
\r
1784 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
\r
1785 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
\r
1786 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
\r
1789 /** @brief Get the enable or disable status of the APB2 peripheral clock
\r
1790 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1791 * is disabled and the application software has to enable this clock before
\r
1795 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
\r
1796 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)
\r
1797 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
\r
1798 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
\r
1799 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)
\r
1800 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)
\r
1801 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)
\r
1802 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)
\r
1803 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)
\r
1804 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
\r
1805 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)
\r
1806 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)
\r
1807 #define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U)
\r
1808 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
\r
1809 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U)
\r
1811 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)
\r
1812 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)
\r
1813 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
\r
1814 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
\r
1815 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)
\r
1816 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)
\r
1817 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)
\r
1818 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)
\r
1819 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)
\r
1820 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
\r
1821 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)
\r
1822 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)
\r
1823 #define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U)
\r
1824 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
\r
1825 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U)
\r
1828 /** @brief Enable or disable the APB4 peripheral clock.
\r
1829 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1830 * is disabled and the application software has to enable this clock before
\r
1834 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
\r
1835 __IO uint32_t tmpreg; \
\r
1836 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
\r
1837 /* Delay after an RCC peripheral clock enabling */ \
\r
1838 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
\r
1842 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
\r
1843 __IO uint32_t tmpreg; \
\r
1844 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
\r
1845 /* Delay after an RCC peripheral clock enabling */ \
\r
1846 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
\r
1850 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
\r
1851 __IO uint32_t tmpreg; \
\r
1852 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
\r
1853 /* Delay after an RCC peripheral clock enabling */ \
\r
1854 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
\r
1858 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
\r
1859 __IO uint32_t tmpreg; \
\r
1860 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
\r
1861 /* Delay after an RCC peripheral clock enabling */ \
\r
1862 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
\r
1866 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
\r
1867 __IO uint32_t tmpreg; \
\r
1868 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
\r
1869 /* Delay after an RCC peripheral clock enabling */ \
\r
1870 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
\r
1874 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \
\r
1875 __IO uint32_t tmpreg; \
\r
1876 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
\r
1877 /* Delay after an RCC peripheral clock enabling */ \
\r
1878 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
\r
1882 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \
\r
1883 __IO uint32_t tmpreg; \
\r
1884 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
\r
1885 /* Delay after an RCC peripheral clock enabling */ \
\r
1886 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
\r
1890 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \
\r
1891 __IO uint32_t tmpreg; \
\r
1892 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
\r
1893 /* Delay after an RCC peripheral clock enabling */ \
\r
1894 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
\r
1898 #define __HAL_RCC_COMP12_CLK_ENABLE() do { \
\r
1899 __IO uint32_t tmpreg; \
\r
1900 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
\r
1901 /* Delay after an RCC peripheral clock enabling */ \
\r
1902 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
\r
1906 #define __HAL_RCC_VREF_CLK_ENABLE() do { \
\r
1907 __IO uint32_t tmpreg; \
\r
1908 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
\r
1909 /* Delay after an RCC peripheral clock enabling */ \
\r
1910 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
\r
1914 #define __HAL_RCC_SAI4_CLK_ENABLE() do { \
\r
1915 __IO uint32_t tmpreg; \
\r
1916 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
\r
1917 /* Delay after an RCC peripheral clock enabling */ \
\r
1918 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
\r
1922 #define __HAL_RCC_RTC_CLK_ENABLE() do { \
\r
1923 __IO uint32_t tmpreg; \
\r
1924 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
\r
1925 /* Delay after an RCC peripheral clock enabling */ \
\r
1926 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
\r
1930 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
\r
1931 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
\r
1932 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
\r
1933 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
\r
1934 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
\r
1935 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
\r
1936 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
\r
1937 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
\r
1938 #define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
\r
1939 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
\r
1940 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
\r
1941 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
\r
1943 /** @brief Get the enable or disable status of the APB4 peripheral clock
\r
1944 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1945 * is disabled and the application software has to enable this clock before
\r
1949 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)
\r
1950 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
\r
1951 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)
\r
1952 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)
\r
1953 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)
\r
1954 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)
\r
1955 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U)
\r
1956 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U)
\r
1957 #define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)
\r
1958 #define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)
\r
1959 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)
\r
1960 #define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U)
\r
1962 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)
\r
1963 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
\r
1964 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)
\r
1965 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)
\r
1966 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)
\r
1967 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)
\r
1968 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U)
\r
1969 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U)
\r
1970 #define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)
\r
1971 #define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)
\r
1972 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)
\r
1973 #define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U)
\r
1976 #if defined(DUAL_CORE)
\r
1978 /* Exported macros for RCC_C1 -------------------------------------------------*/
\r
1980 /** @brief Enable or disable the AHB3 peripheral clock.
\r
1981 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1982 * is disabled and the application software has to enable this clock before
\r
1986 #define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \
\r
1987 __IO uint32_t tmpreg; \
\r
1988 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
\r
1989 /* Delay after an RCC peripheral clock enabling */ \
\r
1990 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
\r
1994 #define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \
\r
1995 __IO uint32_t tmpreg; \
\r
1996 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
\r
1997 /* Delay after an RCC peripheral clock enabling */ \
\r
1998 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
\r
2002 #define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \
\r
2003 __IO uint32_t tmpreg; \
\r
2004 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
\r
2005 /* Delay after an RCC peripheral clock enabling */ \
\r
2006 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
\r
2011 #define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \
\r
2012 __IO uint32_t tmpreg; \
\r
2013 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
2014 /* Delay after an RCC peripheral clock enabling */ \
\r
2015 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
2019 #define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \
\r
2020 __IO uint32_t tmpreg; \
\r
2021 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
2022 /* Delay after an RCC peripheral clock enabling */ \
\r
2023 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
2027 #define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \
\r
2028 __IO uint32_t tmpreg; \
\r
2029 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
\r
2030 /* Delay after an RCC peripheral clock enabling */ \
\r
2031 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
\r
2038 #define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
\r
2039 #define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
\r
2040 #define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
\r
2041 #define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
\r
2042 #define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
\r
2043 #define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
\r
2048 /** @brief Enable or disable the AHB1 peripheral clock.
\r
2049 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2050 * is disabled and the application software has to enable this clock before
\r
2054 #define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \
\r
2055 __IO uint32_t tmpreg; \
\r
2056 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
\r
2057 /* Delay after an RCC peripheral clock enabling */ \
\r
2058 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
\r
2062 #define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \
\r
2063 __IO uint32_t tmpreg; \
\r
2064 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
2065 /* Delay after an RCC peripheral clock enabling */ \
\r
2066 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
2070 #define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \
\r
2071 __IO uint32_t tmpreg; \
\r
2072 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
\r
2073 /* Delay after an RCC peripheral clock enabling */ \
\r
2074 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
\r
2078 #define __HAL_RCC_C1_ART_CLK_ENABLE() do { \
\r
2079 __IO uint32_t tmpreg; \
\r
2080 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
\r
2081 /* Delay after an RCC peripheral clock enabling */ \
\r
2082 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
\r
2086 #define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \
\r
2087 __IO uint32_t tmpreg; \
\r
2088 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
\r
2089 /* Delay after an RCC peripheral clock enabling */ \
\r
2090 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
\r
2094 #define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \
\r
2095 __IO uint32_t tmpreg; \
\r
2096 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
\r
2097 /* Delay after an RCC peripheral clock enabling */ \
\r
2098 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
\r
2102 #define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \
\r
2103 __IO uint32_t tmpreg; \
\r
2104 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
\r
2105 /* Delay after an RCC peripheral clock enabling */ \
\r
2106 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
\r
2111 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \
\r
2112 __IO uint32_t tmpreg; \
\r
2113 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
\r
2114 /* Delay after an RCC peripheral clock enabling */ \
\r
2115 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
\r
2119 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
\r
2120 __IO uint32_t tmpreg; \
\r
2121 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
\r
2122 /* Delay after an RCC peripheral clock enabling */ \
\r
2123 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
\r
2127 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \
\r
2128 __IO uint32_t tmpreg; \
\r
2129 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
\r
2130 /* Delay after an RCC peripheral clock enabling */ \
\r
2131 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
\r
2135 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
\r
2136 __IO uint32_t tmpreg; \
\r
2137 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
\r
2138 /* Delay after an RCC peripheral clock enabling */ \
\r
2139 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
\r
2143 #define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
\r
2144 #define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
\r
2145 #define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
\r
2146 #define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
\r
2147 #define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
\r
2148 #define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
\r
2149 #define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
\r
2150 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
\r
2151 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
\r
2152 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
\r
2153 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
\r
2155 /** @brief Enable or disable the AHB2 peripheral clock.
\r
2156 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2157 * is disabled and the application software has to enable this clock before
\r
2161 #define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \
\r
2162 __IO uint32_t tmpreg; \
\r
2163 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
2164 /* Delay after an RCC peripheral clock enabling */ \
\r
2165 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
2169 #define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \
\r
2170 __IO uint32_t tmpreg; \
\r
2171 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
2172 /* Delay after an RCC peripheral clock enabling */ \
\r
2173 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
2177 #define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \
\r
2178 __IO uint32_t tmpreg; \
\r
2179 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
2180 /* Delay after an RCC peripheral clock enabling */ \
\r
2181 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
2185 #define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \
\r
2186 __IO uint32_t tmpreg; \
\r
2187 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
2188 /* Delay after an RCC peripheral clock enabling */ \
\r
2189 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
2193 #define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \
\r
2194 __IO uint32_t tmpreg; \
\r
2195 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
\r
2196 /* Delay after an RCC peripheral clock enabling */ \
\r
2197 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
\r
2201 #define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \
\r
2202 __IO uint32_t tmpreg; \
\r
2203 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
\r
2204 /* Delay after an RCC peripheral clock enabling */ \
\r
2205 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
\r
2209 #define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \
\r
2210 __IO uint32_t tmpreg; \
\r
2211 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
\r
2212 /* Delay after an RCC peripheral clock enabling */ \
\r
2213 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
\r
2217 #define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \
\r
2218 __IO uint32_t tmpreg; \
\r
2219 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
\r
2220 /* Delay after an RCC peripheral clock enabling */ \
\r
2221 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
\r
2225 #define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
\r
2226 #define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
\r
2227 #define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
\r
2228 #define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
\r
2229 #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
\r
2230 #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
\r
2231 #define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
\r
2232 #define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
\r
2234 /** @brief Enable or disable the AHB4 peripheral clock.
\r
2235 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2236 * is disabled and the application software has to enable this clock before
\r
2240 #define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \
\r
2241 __IO uint32_t tmpreg; \
\r
2242 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
\r
2243 /* Delay after an RCC peripheral clock enabling */ \
\r
2244 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
\r
2248 #define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \
\r
2249 __IO uint32_t tmpreg; \
\r
2250 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
\r
2251 /* Delay after an RCC peripheral clock enabling */ \
\r
2252 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
\r
2256 #define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \
\r
2257 __IO uint32_t tmpreg; \
\r
2258 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
\r
2259 /* Delay after an RCC peripheral clock enabling */ \
\r
2260 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
\r
2264 #define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \
\r
2265 __IO uint32_t tmpreg; \
\r
2266 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
\r
2267 /* Delay after an RCC peripheral clock enabling */ \
\r
2268 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
\r
2272 #define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \
\r
2273 __IO uint32_t tmpreg; \
\r
2274 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
\r
2275 /* Delay after an RCC peripheral clock enabling */ \
\r
2276 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
\r
2280 #define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \
\r
2281 __IO uint32_t tmpreg; \
\r
2282 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
\r
2283 /* Delay after an RCC peripheral clock enabling */ \
\r
2284 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
\r
2288 #define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \
\r
2289 __IO uint32_t tmpreg; \
\r
2290 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
\r
2291 /* Delay after an RCC peripheral clock enabling */ \
\r
2292 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
\r
2296 #define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \
\r
2297 __IO uint32_t tmpreg; \
\r
2298 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
\r
2299 /* Delay after an RCC peripheral clock enabling */ \
\r
2300 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
\r
2304 #define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \
\r
2305 __IO uint32_t tmpreg; \
\r
2306 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
\r
2307 /* Delay after an RCC peripheral clock enabling */ \
\r
2308 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
\r
2312 #define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \
\r
2313 __IO uint32_t tmpreg; \
\r
2314 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
\r
2315 /* Delay after an RCC peripheral clock enabling */ \
\r
2316 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
\r
2320 #define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \
\r
2321 __IO uint32_t tmpreg; \
\r
2322 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
\r
2323 /* Delay after an RCC peripheral clock enabling */ \
\r
2324 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
\r
2328 #define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \
\r
2329 __IO uint32_t tmpreg; \
\r
2330 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
\r
2331 /* Delay after an RCC peripheral clock enabling */ \
\r
2332 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
\r
2336 #define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \
\r
2337 __IO uint32_t tmpreg; \
\r
2338 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
\r
2339 /* Delay after an RCC peripheral clock enabling */ \
\r
2340 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
\r
2344 #define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \
\r
2345 __IO uint32_t tmpreg; \
\r
2346 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
\r
2347 /* Delay after an RCC peripheral clock enabling */ \
\r
2348 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
\r
2352 #define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \
\r
2353 __IO uint32_t tmpreg; \
\r
2354 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
\r
2355 /* Delay after an RCC peripheral clock enabling */ \
\r
2356 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
\r
2360 #define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \
\r
2361 __IO uint32_t tmpreg; \
\r
2362 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
\r
2363 /* Delay after an RCC peripheral clock enabling */ \
\r
2364 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
\r
2369 #define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
\r
2370 #define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
\r
2371 #define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
\r
2372 #define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
\r
2373 #define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
\r
2374 #define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
\r
2375 #define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
\r
2376 #define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
\r
2377 #define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
\r
2378 #define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
\r
2379 #define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
\r
2380 #define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
\r
2381 #define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
\r
2382 #define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
\r
2383 #define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
\r
2384 #define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
\r
2387 /** @brief Enable or disable the APB3 peripheral clock.
\r
2388 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2389 * is disabled and the application software has to enable this clock before
\r
2393 #define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \
\r
2394 __IO uint32_t tmpreg; \
\r
2395 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
\r
2396 /* Delay after an RCC peripheral clock enabling */ \
\r
2397 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
\r
2401 #define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \
\r
2402 __IO uint32_t tmpreg; \
\r
2403 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
\r
2404 /* Delay after an RCC peripheral clock enabling */ \
\r
2405 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
\r
2409 #define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \
\r
2410 __IO uint32_t tmpreg; \
\r
2411 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
\r
2412 /* Delay after an RCC peripheral clock enabling */ \
\r
2413 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
\r
2417 #define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
\r
2418 #define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
\r
2419 #define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
\r
2421 /** @brief Enable or disable the APB1 peripheral clock.
\r
2422 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2423 * is disabled and the application software has to enable this clock before
\r
2427 #define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \
\r
2428 __IO uint32_t tmpreg; \
\r
2429 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
\r
2430 /* Delay after an RCC peripheral clock enabling */ \
\r
2431 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
\r
2435 #define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \
\r
2436 __IO uint32_t tmpreg; \
\r
2437 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
\r
2438 /* Delay after an RCC peripheral clock enabling */ \
\r
2439 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
\r
2443 #define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \
\r
2444 __IO uint32_t tmpreg; \
\r
2445 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
\r
2446 /* Delay after an RCC peripheral clock enabling */ \
\r
2447 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
\r
2451 #define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \
\r
2452 __IO uint32_t tmpreg; \
\r
2453 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
\r
2454 /* Delay after an RCC peripheral clock enabling */ \
\r
2455 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
\r
2459 #define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \
\r
2460 __IO uint32_t tmpreg; \
\r
2461 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
\r
2462 /* Delay after an RCC peripheral clock enabling */ \
\r
2463 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
\r
2467 #define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \
\r
2468 __IO uint32_t tmpreg; \
\r
2469 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
\r
2470 /* Delay after an RCC peripheral clock enabling */ \
\r
2471 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
\r
2475 #define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \
\r
2476 __IO uint32_t tmpreg; \
\r
2477 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
\r
2478 /* Delay after an RCC peripheral clock enabling */ \
\r
2479 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
\r
2483 #define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \
\r
2484 __IO uint32_t tmpreg; \
\r
2485 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
\r
2486 /* Delay after an RCC peripheral clock enabling */ \
\r
2487 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
\r
2491 #define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \
\r
2492 __IO uint32_t tmpreg; \
\r
2493 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
\r
2494 /* Delay after an RCC peripheral clock enabling */ \
\r
2495 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
\r
2499 #define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \
\r
2500 __IO uint32_t tmpreg; \
\r
2501 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
\r
2502 /* Delay after an RCC peripheral clock enabling */ \
\r
2503 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
\r
2507 #define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \
\r
2508 __IO uint32_t tmpreg; \
\r
2509 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
\r
2510 /* Delay after an RCC peripheral clock enabling */ \
\r
2511 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
\r
2515 #define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \
\r
2516 __IO uint32_t tmpreg; \
\r
2517 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
\r
2518 /* Delay after an RCC peripheral clock enabling */ \
\r
2519 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
\r
2523 #define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \
\r
2524 __IO uint32_t tmpreg; \
\r
2525 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
\r
2526 /* Delay after an RCC peripheral clock enabling */ \
\r
2527 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
\r
2531 #define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \
\r
2532 __IO uint32_t tmpreg; \
\r
2533 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
\r
2534 /* Delay after an RCC peripheral clock enabling */ \
\r
2535 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
\r
2539 #define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \
\r
2540 __IO uint32_t tmpreg; \
\r
2541 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
\r
2542 /* Delay after an RCC peripheral clock enabling */ \
\r
2543 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
\r
2547 #define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \
\r
2548 __IO uint32_t tmpreg; \
\r
2549 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
\r
2550 /* Delay after an RCC peripheral clock enabling */ \
\r
2551 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
\r
2555 #define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \
\r
2556 __IO uint32_t tmpreg; \
\r
2557 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
\r
2558 /* Delay after an RCC peripheral clock enabling */ \
\r
2559 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
\r
2563 #define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \
\r
2564 __IO uint32_t tmpreg; \
\r
2565 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
\r
2566 /* Delay after an RCC peripheral clock enabling */ \
\r
2567 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
\r
2571 #define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \
\r
2572 __IO uint32_t tmpreg; \
\r
2573 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
\r
2574 /* Delay after an RCC peripheral clock enabling */ \
\r
2575 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
\r
2579 #define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \
\r
2580 __IO uint32_t tmpreg; \
\r
2581 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
\r
2582 /* Delay after an RCC peripheral clock enabling */ \
\r
2583 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
\r
2587 #define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \
\r
2588 __IO uint32_t tmpreg; \
\r
2589 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
\r
2590 /* Delay after an RCC peripheral clock enabling */ \
\r
2591 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
\r
2595 #define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \
\r
2596 __IO uint32_t tmpreg; \
\r
2597 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
\r
2598 /* Delay after an RCC peripheral clock enabling */ \
\r
2599 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
\r
2603 #define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \
\r
2604 __IO uint32_t tmpreg; \
\r
2605 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
\r
2606 /* Delay after an RCC peripheral clock enabling */ \
\r
2607 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
\r
2611 #define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \
\r
2612 __IO uint32_t tmpreg; \
\r
2613 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
\r
2614 /* Delay after an RCC peripheral clock enabling */ \
\r
2615 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
\r
2619 #define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \
\r
2620 __IO uint32_t tmpreg; \
\r
2621 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
\r
2622 /* Delay after an RCC peripheral clock enabling */ \
\r
2623 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
\r
2627 #define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \
\r
2628 __IO uint32_t tmpreg; \
\r
2629 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
\r
2630 /* Delay after an RCC peripheral clock enabling */ \
\r
2631 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
\r
2635 #define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \
\r
2636 __IO uint32_t tmpreg; \
\r
2637 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
\r
2638 /* Delay after an RCC peripheral clock enabling */ \
\r
2639 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
\r
2643 #define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \
\r
2644 __IO uint32_t tmpreg; \
\r
2645 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
\r
2646 /* Delay after an RCC peripheral clock enabling */ \
\r
2647 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
\r
2651 #define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \
\r
2652 __IO uint32_t tmpreg; \
\r
2653 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
\r
2654 /* Delay after an RCC peripheral clock enabling */ \
\r
2655 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
\r
2659 #define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \
\r
2660 __IO uint32_t tmpreg; \
\r
2661 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
\r
2662 /* Delay after an RCC peripheral clock enabling */ \
\r
2663 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
\r
2668 #define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
\r
2669 #define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
\r
2670 #define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
\r
2671 #define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
\r
2672 #define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
\r
2673 #define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
\r
2674 #define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
\r
2675 #define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
\r
2676 #define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
\r
2677 #define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
\r
2678 #define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
\r
2679 #define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
\r
2680 #define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
\r
2681 #define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
\r
2682 #define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
\r
2683 #define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
\r
2684 #define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
\r
2685 #define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
\r
2686 #define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
\r
2687 #define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
\r
2688 #define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
\r
2689 #define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
\r
2690 #define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
\r
2691 #define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
\r
2692 #define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
\r
2693 #define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
\r
2694 #define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
\r
2695 #define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
\r
2696 #define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
\r
2697 #define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
\r
2699 /** @brief Enable or disable the APB2 peripheral clock.
\r
2700 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2701 * is disabled and the application software has to enable this clock before
\r
2705 #define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \
\r
2706 __IO uint32_t tmpreg; \
\r
2707 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
2708 /* Delay after an RCC peripheral clock enabling */ \
\r
2709 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
2713 #define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \
\r
2714 __IO uint32_t tmpreg; \
\r
2715 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
2716 /* Delay after an RCC peripheral clock enabling */ \
\r
2717 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
2721 #define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \
\r
2722 __IO uint32_t tmpreg; \
\r
2723 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
2724 /* Delay after an RCC peripheral clock enabling */ \
\r
2725 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
2729 #define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \
\r
2730 __IO uint32_t tmpreg; \
\r
2731 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
2732 /* Delay after an RCC peripheral clock enabling */ \
\r
2733 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
2737 #define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \
\r
2738 __IO uint32_t tmpreg; \
\r
2739 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
2740 /* Delay after an RCC peripheral clock enabling */ \
\r
2741 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
2745 #define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \
\r
2746 __IO uint32_t tmpreg; \
\r
2747 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
2748 /* Delay after an RCC peripheral clock enabling */ \
\r
2749 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
2753 #define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \
\r
2754 __IO uint32_t tmpreg; \
\r
2755 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
\r
2756 /* Delay after an RCC peripheral clock enabling */ \
\r
2757 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
\r
2761 #define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \
\r
2762 __IO uint32_t tmpreg; \
\r
2763 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
\r
2764 /* Delay after an RCC peripheral clock enabling */ \
\r
2765 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
\r
2769 #define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \
\r
2770 __IO uint32_t tmpreg; \
\r
2771 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
\r
2772 /* Delay after an RCC peripheral clock enabling */ \
\r
2773 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
\r
2777 #define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \
\r
2778 __IO uint32_t tmpreg; \
\r
2779 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
2780 /* Delay after an RCC peripheral clock enabling */ \
\r
2781 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
2785 #define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \
\r
2786 __IO uint32_t tmpreg; \
\r
2787 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
2788 /* Delay after an RCC peripheral clock enabling */ \
\r
2789 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
2793 #define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \
\r
2794 __IO uint32_t tmpreg; \
\r
2795 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
2796 /* Delay after an RCC peripheral clock enabling */ \
\r
2797 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
2801 #define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \
\r
2802 __IO uint32_t tmpreg; \
\r
2803 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
\r
2804 /* Delay after an RCC peripheral clock enabling */ \
\r
2805 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
\r
2809 #define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \
\r
2810 __IO uint32_t tmpreg; \
\r
2811 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
\r
2812 /* Delay after an RCC peripheral clock enabling */ \
\r
2813 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
\r
2817 #define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \
\r
2818 __IO uint32_t tmpreg; \
\r
2819 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
\r
2820 /* Delay after an RCC peripheral clock enabling */ \
\r
2821 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
\r
2825 #define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
\r
2826 #define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
\r
2827 #define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
\r
2828 #define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
\r
2829 #define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
\r
2830 #define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
\r
2831 #define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
\r
2832 #define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
\r
2833 #define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
\r
2834 #define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
\r
2835 #define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
\r
2836 #define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
\r
2837 #define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
\r
2838 #define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
\r
2839 #define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
\r
2841 /** @brief Enable or disable the APB4 peripheral clock.
\r
2842 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2843 * is disabled and the application software has to enable this clock before
\r
2847 #define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \
\r
2848 __IO uint32_t tmpreg; \
\r
2849 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
\r
2850 /* Delay after an RCC peripheral clock enabling */ \
\r
2851 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
\r
2855 #define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \
\r
2856 __IO uint32_t tmpreg; \
\r
2857 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
\r
2858 /* Delay after an RCC peripheral clock enabling */ \
\r
2859 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
\r
2863 #define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \
\r
2864 __IO uint32_t tmpreg; \
\r
2865 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
\r
2866 /* Delay after an RCC peripheral clock enabling */ \
\r
2867 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
\r
2871 #define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \
\r
2872 __IO uint32_t tmpreg; \
\r
2873 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
\r
2874 /* Delay after an RCC peripheral clock enabling */ \
\r
2875 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
\r
2879 #define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \
\r
2880 __IO uint32_t tmpreg; \
\r
2881 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
\r
2882 /* Delay after an RCC peripheral clock enabling */ \
\r
2883 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
\r
2887 #define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \
\r
2888 __IO uint32_t tmpreg; \
\r
2889 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
\r
2890 /* Delay after an RCC peripheral clock enabling */ \
\r
2891 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
\r
2895 #define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \
\r
2896 __IO uint32_t tmpreg; \
\r
2897 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
\r
2898 /* Delay after an RCC peripheral clock enabling */ \
\r
2899 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
\r
2903 #define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \
\r
2904 __IO uint32_t tmpreg; \
\r
2905 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
\r
2906 /* Delay after an RCC peripheral clock enabling */ \
\r
2907 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
\r
2911 #define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \
\r
2912 __IO uint32_t tmpreg; \
\r
2913 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
\r
2914 /* Delay after an RCC peripheral clock enabling */ \
\r
2915 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
\r
2920 #define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \
\r
2921 __IO uint32_t tmpreg; \
\r
2922 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
\r
2923 /* Delay after an RCC peripheral clock enabling */ \
\r
2924 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
\r
2928 #define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \
\r
2929 __IO uint32_t tmpreg; \
\r
2930 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
\r
2931 /* Delay after an RCC peripheral clock enabling */ \
\r
2932 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
\r
2936 #define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \
\r
2937 __IO uint32_t tmpreg; \
\r
2938 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
\r
2939 /* Delay after an RCC peripheral clock enabling */ \
\r
2940 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
\r
2945 #define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
\r
2946 #define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
\r
2947 #define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
\r
2948 #define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
\r
2949 #define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
\r
2950 #define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
\r
2951 #define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
\r
2952 #define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
\r
2953 #define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
\r
2954 #define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
\r
2955 #define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
\r
2956 #define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
\r
2958 /* Exported macros for RCC_C2 -------------------------------------------------*/
\r
2960 /** @brief Enable or disable the AHB3 peripheral clock.
\r
2961 * @note After reset, the peripheral clock (used for registers read/write access)
\r
2962 * is disabled and the application software has to enable this clock before
\r
2967 #define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \
\r
2968 __IO uint32_t tmpreg; \
\r
2969 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
\r
2970 /* Delay after an RCC peripheral clock enabling */ \
\r
2971 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
\r
2975 #define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \
\r
2976 __IO uint32_t tmpreg; \
\r
2977 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
\r
2978 /* Delay after an RCC peripheral clock enabling */ \
\r
2979 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
\r
2983 #define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \
\r
2984 __IO uint32_t tmpreg; \
\r
2985 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
\r
2986 /* Delay after an RCC peripheral clock enabling */ \
\r
2987 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
\r
2991 #define __HAL_RCC_FLASH_C2_ALLOCATE() do { \
\r
2992 __IO uint32_t tmpreg; \
\r
2993 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
\r
2994 /* Delay after an RCC peripheral clock enabling */ \
\r
2995 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
\r
2999 #define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \
\r
3000 __IO uint32_t tmpreg; \
\r
3001 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
\r
3002 /* Delay after an RCC peripheral clock enabling */ \
\r
3003 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
\r
3007 #define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \
\r
3008 __IO uint32_t tmpreg; \
\r
3009 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
\r
3010 /* Delay after an RCC peripheral clock enabling */ \
\r
3011 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
\r
3015 #define __HAL_RCC_ITCM_C2_ALLOCATE() do { \
\r
3016 __IO uint32_t tmpreg; \
\r
3017 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
\r
3018 /* Delay after an RCC peripheral clock enabling */ \
\r
3019 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
\r
3023 #define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \
\r
3024 __IO uint32_t tmpreg; \
\r
3025 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
\r
3026 /* Delay after an RCC peripheral clock enabling */ \
\r
3027 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
\r
3031 #define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \
\r
3032 __IO uint32_t tmpreg; \
\r
3033 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
3034 /* Delay after an RCC peripheral clock enabling */ \
\r
3035 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
3039 #define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \
\r
3040 __IO uint32_t tmpreg; \
\r
3041 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
3042 /* Delay after an RCC peripheral clock enabling */ \
\r
3043 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
3047 #define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \
\r
3048 __IO uint32_t tmpreg; \
\r
3049 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
\r
3050 /* Delay after an RCC peripheral clock enabling */ \
\r
3051 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
\r
3058 #define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
\r
3059 #define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
\r
3060 #define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
\r
3061 #define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
\r
3062 #define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
\r
3063 #define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
\r
3064 #define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
\r
3065 #define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
\r
3066 #define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
\r
3067 #define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
\r
3068 #define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
\r
3070 /** @brief Enable or disable the AHB1 peripheral clock.
\r
3071 * @note After reset, the peripheral clock (used for registers read/write access)
\r
3072 * is disabled and the application software has to enable this clock before
\r
3076 #define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \
\r
3077 __IO uint32_t tmpreg; \
\r
3078 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
\r
3079 /* Delay after an RCC peripheral clock enabling */ \
\r
3080 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
\r
3084 #define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \
\r
3085 __IO uint32_t tmpreg; \
\r
3086 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
3087 /* Delay after an RCC peripheral clock enabling */ \
\r
3088 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
3092 #define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \
\r
3093 __IO uint32_t tmpreg; \
\r
3094 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
\r
3095 /* Delay after an RCC peripheral clock enabling */ \
\r
3096 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
\r
3100 #define __HAL_RCC_C2_ART_CLK_ENABLE() do { \
\r
3101 __IO uint32_t tmpreg; \
\r
3102 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
\r
3103 /* Delay after an RCC peripheral clock enabling */ \
\r
3104 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
\r
3108 #define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \
\r
3109 __IO uint32_t tmpreg; \
\r
3110 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
\r
3111 /* Delay after an RCC peripheral clock enabling */ \
\r
3112 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
\r
3116 #define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \
\r
3117 __IO uint32_t tmpreg; \
\r
3118 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
\r
3119 /* Delay after an RCC peripheral clock enabling */ \
\r
3120 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
\r
3124 #define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \
\r
3125 __IO uint32_t tmpreg; \
\r
3126 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
\r
3127 /* Delay after an RCC peripheral clock enabling */ \
\r
3128 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
\r
3132 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \
\r
3133 __IO uint32_t tmpreg; \
\r
3134 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
\r
3135 /* Delay after an RCC peripheral clock enabling */ \
\r
3136 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
\r
3140 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
\r
3141 __IO uint32_t tmpreg; \
\r
3142 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
\r
3143 /* Delay after an RCC peripheral clock enabling */ \
\r
3144 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
\r
3148 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \
\r
3149 __IO uint32_t tmpreg; \
\r
3150 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
\r
3151 /* Delay after an RCC peripheral clock enabling */ \
\r
3152 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
\r
3157 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
\r
3158 __IO uint32_t tmpreg; \
\r
3159 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
\r
3160 /* Delay after an RCC peripheral clock enabling */ \
\r
3161 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
\r
3165 #define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
\r
3166 #define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
\r
3167 #define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
\r
3168 #define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
\r
3169 #define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
\r
3170 #define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
\r
3171 #define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
\r
3172 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
\r
3173 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
\r
3174 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
\r
3175 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
\r
3177 /** @brief Enable or disable the AHB2 peripheral clock.
\r
3178 * @note After reset, the peripheral clock (used for registers read/write access)
\r
3179 * is disabled and the application software has to enable this clock before
\r
3183 #define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \
\r
3184 __IO uint32_t tmpreg; \
\r
3185 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
3186 /* Delay after an RCC peripheral clock enabling */ \
\r
3187 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
3191 #define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \
\r
3192 __IO uint32_t tmpreg; \
\r
3193 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
3194 /* Delay after an RCC peripheral clock enabling */ \
\r
3195 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
3199 #define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \
\r
3200 __IO uint32_t tmpreg; \
\r
3201 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
3202 /* Delay after an RCC peripheral clock enabling */ \
\r
3203 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
3207 #define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \
\r
3208 __IO uint32_t tmpreg; \
\r
3209 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
3210 /* Delay after an RCC peripheral clock enabling */ \
\r
3211 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
3215 #define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \
\r
3216 __IO uint32_t tmpreg; \
\r
3217 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
\r
3218 /* Delay after an RCC peripheral clock enabling */ \
\r
3219 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
\r
3223 #define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \
\r
3224 __IO uint32_t tmpreg; \
\r
3225 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
\r
3226 /* Delay after an RCC peripheral clock enabling */ \
\r
3227 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
\r
3231 #define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \
\r
3232 __IO uint32_t tmpreg; \
\r
3233 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
\r
3234 /* Delay after an RCC peripheral clock enabling */ \
\r
3235 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
\r
3239 #define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \
\r
3240 __IO uint32_t tmpreg; \
\r
3241 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
\r
3242 /* Delay after an RCC peripheral clock enabling */ \
\r
3243 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
\r
3247 #define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
\r
3248 #define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
\r
3249 #define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
\r
3250 #define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
\r
3251 #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
\r
3252 #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
\r
3253 #define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
\r
3254 #define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
\r
3256 /** @brief Enable or disable the AHB4 peripheral clock.
\r
3257 * @note After reset, the peripheral clock (used for registers read/write access)
\r
3258 * is disabled and the application software has to enable this clock before
\r
3262 #define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \
\r
3263 __IO uint32_t tmpreg; \
\r
3264 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
\r
3265 /* Delay after an RCC peripheral clock enabling */ \
\r
3266 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
\r
3270 #define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \
\r
3271 __IO uint32_t tmpreg; \
\r
3272 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
\r
3273 /* Delay after an RCC peripheral clock enabling */ \
\r
3274 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
\r
3278 #define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \
\r
3279 __IO uint32_t tmpreg; \
\r
3280 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
\r
3281 /* Delay after an RCC peripheral clock enabling */ \
\r
3282 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
\r
3286 #define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \
\r
3287 __IO uint32_t tmpreg; \
\r
3288 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
\r
3289 /* Delay after an RCC peripheral clock enabling */ \
\r
3290 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
\r
3294 #define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \
\r
3295 __IO uint32_t tmpreg; \
\r
3296 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
\r
3297 /* Delay after an RCC peripheral clock enabling */ \
\r
3298 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
\r
3302 #define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \
\r
3303 __IO uint32_t tmpreg; \
\r
3304 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
\r
3305 /* Delay after an RCC peripheral clock enabling */ \
\r
3306 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
\r
3310 #define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \
\r
3311 __IO uint32_t tmpreg; \
\r
3312 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
\r
3313 /* Delay after an RCC peripheral clock enabling */ \
\r
3314 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
\r
3318 #define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \
\r
3319 __IO uint32_t tmpreg; \
\r
3320 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
\r
3321 /* Delay after an RCC peripheral clock enabling */ \
\r
3322 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
\r
3326 #define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \
\r
3327 __IO uint32_t tmpreg; \
\r
3328 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
\r
3329 /* Delay after an RCC peripheral clock enabling */ \
\r
3330 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
\r
3334 #define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \
\r
3335 __IO uint32_t tmpreg; \
\r
3336 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
\r
3337 /* Delay after an RCC peripheral clock enabling */ \
\r
3338 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
\r
3342 #define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \
\r
3343 __IO uint32_t tmpreg; \
\r
3344 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
\r
3345 /* Delay after an RCC peripheral clock enabling */ \
\r
3346 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
\r
3350 #define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \
\r
3351 __IO uint32_t tmpreg; \
\r
3352 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
\r
3353 /* Delay after an RCC peripheral clock enabling */ \
\r
3354 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
\r
3358 #define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \
\r
3359 __IO uint32_t tmpreg; \
\r
3360 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
\r
3361 /* Delay after an RCC peripheral clock enabling */ \
\r
3362 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
\r
3366 #define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \
\r
3367 __IO uint32_t tmpreg; \
\r
3368 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
\r
3369 /* Delay after an RCC peripheral clock enabling */ \
\r
3370 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
\r
3374 #define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \
\r
3375 __IO uint32_t tmpreg; \
\r
3376 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
\r
3377 /* Delay after an RCC peripheral clock enabling */ \
\r
3378 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
\r
3382 #define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \
\r
3383 __IO uint32_t tmpreg; \
\r
3384 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
\r
3385 /* Delay after an RCC peripheral clock enabling */ \
\r
3386 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
\r
3391 #define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
\r
3392 #define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
\r
3393 #define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
\r
3394 #define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
\r
3395 #define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
\r
3396 #define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
\r
3397 #define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
\r
3398 #define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
\r
3399 #define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
\r
3400 #define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
\r
3401 #define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
\r
3402 #define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
\r
3403 #define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
\r
3404 #define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
\r
3405 #define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
\r
3406 #define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
\r
3409 /** @brief Enable or disable the APB3 peripheral clock.
\r
3410 * @note After reset, the peripheral clock (used for registers read/write access)
\r
3411 * is disabled and the application software has to enable this clock before
\r
3415 #define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \
\r
3416 __IO uint32_t tmpreg; \
\r
3417 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
\r
3418 /* Delay after an RCC peripheral clock enabling */ \
\r
3419 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
\r
3423 #define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \
\r
3424 __IO uint32_t tmpreg; \
\r
3425 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
\r
3426 /* Delay after an RCC peripheral clock enabling */ \
\r
3427 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
\r
3431 #define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \
\r
3432 __IO uint32_t tmpreg; \
\r
3433 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
\r
3434 /* Delay after an RCC peripheral clock enabling */ \
\r
3435 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
\r
3439 #define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
\r
3440 #define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
\r
3441 #define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
\r
3443 /** @brief Enable or disable the APB1 peripheral clock.
\r
3444 * @note After reset, the peripheral clock (used for registers read/write access)
\r
3445 * is disabled and the application software has to enable this clock before
\r
3449 #define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \
\r
3450 __IO uint32_t tmpreg; \
\r
3451 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
\r
3452 /* Delay after an RCC peripheral clock enabling */ \
\r
3453 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
\r
3457 #define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \
\r
3458 __IO uint32_t tmpreg; \
\r
3459 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
\r
3460 /* Delay after an RCC peripheral clock enabling */ \
\r
3461 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
\r
3465 #define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \
\r
3466 __IO uint32_t tmpreg; \
\r
3467 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
\r
3468 /* Delay after an RCC peripheral clock enabling */ \
\r
3469 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
\r
3473 #define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \
\r
3474 __IO uint32_t tmpreg; \
\r
3475 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
\r
3476 /* Delay after an RCC peripheral clock enabling */ \
\r
3477 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
\r
3481 #define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \
\r
3482 __IO uint32_t tmpreg; \
\r
3483 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
\r
3484 /* Delay after an RCC peripheral clock enabling */ \
\r
3485 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
\r
3489 #define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \
\r
3490 __IO uint32_t tmpreg; \
\r
3491 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
\r
3492 /* Delay after an RCC peripheral clock enabling */ \
\r
3493 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
\r
3497 #define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \
\r
3498 __IO uint32_t tmpreg; \
\r
3499 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
\r
3500 /* Delay after an RCC peripheral clock enabling */ \
\r
3501 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
\r
3505 #define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \
\r
3506 __IO uint32_t tmpreg; \
\r
3507 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
\r
3508 /* Delay after an RCC peripheral clock enabling */ \
\r
3509 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
\r
3513 #define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \
\r
3514 __IO uint32_t tmpreg; \
\r
3515 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
\r
3516 /* Delay after an RCC peripheral clock enabling */ \
\r
3517 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
\r
3521 #define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \
\r
3522 __IO uint32_t tmpreg; \
\r
3523 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
\r
3524 /* Delay after an RCC peripheral clock enabling */ \
\r
3525 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
\r
3529 #define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \
\r
3530 __IO uint32_t tmpreg; \
\r
3531 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
\r
3532 /* Delay after an RCC peripheral clock enabling */ \
\r
3533 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
\r
3537 #define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \
\r
3538 __IO uint32_t tmpreg; \
\r
3539 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
\r
3540 /* Delay after an RCC peripheral clock enabling */ \
\r
3541 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
\r
3545 #define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \
\r
3546 __IO uint32_t tmpreg; \
\r
3547 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
\r
3548 /* Delay after an RCC peripheral clock enabling */ \
\r
3549 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
\r
3553 #define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \
\r
3554 __IO uint32_t tmpreg; \
\r
3555 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
\r
3556 /* Delay after an RCC peripheral clock enabling */ \
\r
3557 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
\r
3561 #define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \
\r
3562 __IO uint32_t tmpreg; \
\r
3563 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
\r
3564 /* Delay after an RCC peripheral clock enabling */ \
\r
3565 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
\r
3569 #define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \
\r
3570 __IO uint32_t tmpreg; \
\r
3571 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
\r
3572 /* Delay after an RCC peripheral clock enabling */ \
\r
3573 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
\r
3577 #define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \
\r
3578 __IO uint32_t tmpreg; \
\r
3579 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
\r
3580 /* Delay after an RCC peripheral clock enabling */ \
\r
3581 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
\r
3585 #define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \
\r
3586 __IO uint32_t tmpreg; \
\r
3587 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
\r
3588 /* Delay after an RCC peripheral clock enabling */ \
\r
3589 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
\r
3593 #define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \
\r
3594 __IO uint32_t tmpreg; \
\r
3595 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
\r
3596 /* Delay after an RCC peripheral clock enabling */ \
\r
3597 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
\r
3601 #define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \
\r
3602 __IO uint32_t tmpreg; \
\r
3603 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
\r
3604 /* Delay after an RCC peripheral clock enabling */ \
\r
3605 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
\r
3609 #define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \
\r
3610 __IO uint32_t tmpreg; \
\r
3611 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
\r
3612 /* Delay after an RCC peripheral clock enabling */ \
\r
3613 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
\r
3617 #define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \
\r
3618 __IO uint32_t tmpreg; \
\r
3619 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
\r
3620 /* Delay after an RCC peripheral clock enabling */ \
\r
3621 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
\r
3625 #define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \
\r
3626 __IO uint32_t tmpreg; \
\r
3627 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
\r
3628 /* Delay after an RCC peripheral clock enabling */ \
\r
3629 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
\r
3633 #define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \
\r
3634 __IO uint32_t tmpreg; \
\r
3635 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
\r
3636 /* Delay after an RCC peripheral clock enabling */ \
\r
3637 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
\r
3641 #define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \
\r
3642 __IO uint32_t tmpreg; \
\r
3643 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
\r
3644 /* Delay after an RCC peripheral clock enabling */ \
\r
3645 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
\r
3649 #define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \
\r
3650 __IO uint32_t tmpreg; \
\r
3651 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
\r
3652 /* Delay after an RCC peripheral clock enabling */ \
\r
3653 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
\r
3657 #define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \
\r
3658 __IO uint32_t tmpreg; \
\r
3659 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
\r
3660 /* Delay after an RCC peripheral clock enabling */ \
\r
3661 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
\r
3665 #define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \
\r
3666 __IO uint32_t tmpreg; \
\r
3667 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
\r
3668 /* Delay after an RCC peripheral clock enabling */ \
\r
3669 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
\r
3673 #define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \
\r
3674 __IO uint32_t tmpreg; \
\r
3675 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
\r
3676 /* Delay after an RCC peripheral clock enabling */ \
\r
3677 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
\r
3681 #define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \
\r
3682 __IO uint32_t tmpreg; \
\r
3683 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
\r
3684 /* Delay after an RCC peripheral clock enabling */ \
\r
3685 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
\r
3690 #define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
\r
3691 #define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
\r
3692 #define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
\r
3693 #define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
\r
3694 #define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
\r
3695 #define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
\r
3696 #define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
\r
3697 #define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
\r
3698 #define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
\r
3699 #define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
\r
3700 #define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
\r
3701 #define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
\r
3702 #define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
\r
3703 #define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
\r
3704 #define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
\r
3705 #define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
\r
3706 #define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
\r
3707 #define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
\r
3708 #define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
\r
3709 #define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
\r
3710 #define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
\r
3711 #define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
\r
3712 #define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
\r
3713 #define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
\r
3714 #define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
\r
3715 #define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
\r
3716 #define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
\r
3717 #define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
\r
3718 #define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
\r
3719 #define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
\r
3721 /** @brief Enable or disable the APB2 peripheral clock.
\r
3722 * @note After reset, the peripheral clock (used for registers read/write access)
\r
3723 * is disabled and the application software has to enable this clock before
\r
3727 #define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \
\r
3728 __IO uint32_t tmpreg; \
\r
3729 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
3730 /* Delay after an RCC peripheral clock enabling */ \
\r
3731 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
3735 #define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \
\r
3736 __IO uint32_t tmpreg; \
\r
3737 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
3738 /* Delay after an RCC peripheral clock enabling */ \
\r
3739 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
3743 #define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \
\r
3744 __IO uint32_t tmpreg; \
\r
3745 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
3746 /* Delay after an RCC peripheral clock enabling */ \
\r
3747 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
3751 #define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \
\r
3752 __IO uint32_t tmpreg; \
\r
3753 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
3754 /* Delay after an RCC peripheral clock enabling */ \
\r
3755 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
3759 #define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \
\r
3760 __IO uint32_t tmpreg; \
\r
3761 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
3762 /* Delay after an RCC peripheral clock enabling */ \
\r
3763 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
3767 #define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \
\r
3768 __IO uint32_t tmpreg; \
\r
3769 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
3770 /* Delay after an RCC peripheral clock enabling */ \
\r
3771 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
3775 #define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \
\r
3776 __IO uint32_t tmpreg; \
\r
3777 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
\r
3778 /* Delay after an RCC peripheral clock enabling */ \
\r
3779 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
\r
3783 #define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \
\r
3784 __IO uint32_t tmpreg; \
\r
3785 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
\r
3786 /* Delay after an RCC peripheral clock enabling */ \
\r
3787 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
\r
3791 #define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \
\r
3792 __IO uint32_t tmpreg; \
\r
3793 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
\r
3794 /* Delay after an RCC peripheral clock enabling */ \
\r
3795 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
\r
3799 #define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \
\r
3800 __IO uint32_t tmpreg; \
\r
3801 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
3802 /* Delay after an RCC peripheral clock enabling */ \
\r
3803 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
3807 #define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \
\r
3808 __IO uint32_t tmpreg; \
\r
3809 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
3810 /* Delay after an RCC peripheral clock enabling */ \
\r
3811 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
3815 #define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \
\r
3816 __IO uint32_t tmpreg; \
\r
3817 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
3818 /* Delay after an RCC peripheral clock enabling */ \
\r
3819 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
3823 #define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \
\r
3824 __IO uint32_t tmpreg; \
\r
3825 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
\r
3826 /* Delay after an RCC peripheral clock enabling */ \
\r
3827 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
\r
3831 #define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \
\r
3832 __IO uint32_t tmpreg; \
\r
3833 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
\r
3834 /* Delay after an RCC peripheral clock enabling */ \
\r
3835 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
\r
3839 #define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \
\r
3840 __IO uint32_t tmpreg; \
\r
3841 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
\r
3842 /* Delay after an RCC peripheral clock enabling */ \
\r
3843 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
\r
3847 #define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
\r
3848 #define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
\r
3849 #define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
\r
3850 #define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
\r
3851 #define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
\r
3852 #define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
\r
3853 #define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
\r
3854 #define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
\r
3855 #define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
\r
3856 #define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
\r
3857 #define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
\r
3858 #define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
\r
3859 #define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
\r
3860 #define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
\r
3861 #define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
\r
3863 /** @brief Enable or disable the APB4 peripheral clock.
\r
3864 * @note After reset, the peripheral clock (used for registers read/write access)
\r
3865 * is disabled and the application software has to enable this clock before
\r
3869 #define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \
\r
3870 __IO uint32_t tmpreg; \
\r
3871 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
\r
3872 /* Delay after an RCC peripheral clock enabling */ \
\r
3873 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
\r
3877 #define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \
\r
3878 __IO uint32_t tmpreg; \
\r
3879 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
\r
3880 /* Delay after an RCC peripheral clock enabling */ \
\r
3881 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
\r
3885 #define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \
\r
3886 __IO uint32_t tmpreg; \
\r
3887 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
\r
3888 /* Delay after an RCC peripheral clock enabling */ \
\r
3889 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
\r
3893 #define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \
\r
3894 __IO uint32_t tmpreg; \
\r
3895 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
\r
3896 /* Delay after an RCC peripheral clock enabling */ \
\r
3897 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
\r
3901 #define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \
\r
3902 __IO uint32_t tmpreg; \
\r
3903 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
\r
3904 /* Delay after an RCC peripheral clock enabling */ \
\r
3905 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
\r
3909 #define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \
\r
3910 __IO uint32_t tmpreg; \
\r
3911 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
\r
3912 /* Delay after an RCC peripheral clock enabling */ \
\r
3913 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
\r
3917 #define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \
\r
3918 __IO uint32_t tmpreg; \
\r
3919 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
\r
3920 /* Delay after an RCC peripheral clock enabling */ \
\r
3921 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
\r
3925 #define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \
\r
3926 __IO uint32_t tmpreg; \
\r
3927 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
\r
3928 /* Delay after an RCC peripheral clock enabling */ \
\r
3929 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
\r
3933 #define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \
\r
3934 __IO uint32_t tmpreg; \
\r
3935 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
\r
3936 /* Delay after an RCC peripheral clock enabling */ \
\r
3937 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
\r
3941 #define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \
\r
3942 __IO uint32_t tmpreg; \
\r
3943 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
\r
3944 /* Delay after an RCC peripheral clock enabling */ \
\r
3945 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
\r
3949 #define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \
\r
3950 __IO uint32_t tmpreg; \
\r
3951 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
\r
3952 /* Delay after an RCC peripheral clock enabling */ \
\r
3953 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
\r
3957 #define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \
\r
3958 __IO uint32_t tmpreg; \
\r
3959 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
\r
3960 /* Delay after an RCC peripheral clock enabling */ \
\r
3961 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
\r
3967 #define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
\r
3968 #define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
\r
3969 #define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
\r
3970 #define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
\r
3971 #define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
\r
3972 #define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
\r
3973 #define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
\r
3974 #define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
\r
3975 #define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
\r
3976 #define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
\r
3977 #define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
\r
3978 #define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
\r
3980 #endif /*DUAL_CORE*/
\r
3982 /** @brief Enable or disable the AHB3 peripheral reset.
\r
3985 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
\r
3986 #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
\r
3987 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
\r
3990 #define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
\r
3993 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
\r
3994 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
\r
3995 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
\r
3998 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
\r
3999 #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
\r
4000 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
\r
4003 #define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
\r
4006 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
\r
4007 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
\r
4008 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
\r
4012 /** @brief Force or release the AHB1 peripheral reset.
\r
4014 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
\r
4015 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
\r
4016 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
\r
4017 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
\r
4018 #if defined(DUAL_CORE)
\r
4019 #define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
\r
4020 #endif /*DUAL_CORE*/
\r
4021 #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
\r
4022 #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
\r
4023 #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
\r
4025 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
\r
4026 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
\r
4027 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
\r
4028 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
\r
4029 #if defined(DUAL_CORE)
\r
4030 #define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
\r
4031 #endif /*DUAL_CORE*/
\r
4032 #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
\r
4033 #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
\r
4034 #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
\r
4037 /** @brief Force or release the AHB2 peripheral reset.
\r
4039 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
\r
4040 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
\r
4041 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
\r
4042 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
\r
4043 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
\r
4044 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
\r
4046 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
\r
4047 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
\r
4048 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
\r
4049 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
\r
4050 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
\r
4051 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
\r
4054 /** @brief Force or release the AHB4 peripheral reset.
\r
4057 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFFU)
\r
4058 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
\r
4059 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
\r
4060 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
\r
4061 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
\r
4062 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
\r
4063 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
\r
4064 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
\r
4065 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
\r
4066 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
\r
4067 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
\r
4068 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
\r
4069 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
\r
4070 #define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
\r
4071 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
\r
4072 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
\r
4074 #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)
\r
4075 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
\r
4076 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
\r
4077 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
\r
4078 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
\r
4079 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
\r
4080 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
\r
4081 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
\r
4082 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
\r
4083 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
\r
4084 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
\r
4085 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
\r
4086 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
\r
4087 #define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
\r
4088 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
\r
4089 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
\r
4092 /** @brief Force or release the APB3 peripheral reset.
\r
4094 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFFU)
\r
4097 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
\r
4101 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
\r
4104 #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)
\r
4107 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
\r
4111 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
\r
4114 /** @brief Force or release the APB1 peripheral reset.
\r
4116 #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFFU)
\r
4117 #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFFU)
\r
4118 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
\r
4119 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
\r
4120 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
\r
4121 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
\r
4122 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
\r
4123 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
\r
4124 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
\r
4125 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
\r
4126 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
\r
4127 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
\r
4128 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
\r
4129 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
\r
4130 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
\r
4131 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
\r
4132 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
\r
4133 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
\r
4134 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
\r
4135 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
\r
4136 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
\r
4137 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
\r
4138 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
\r
4139 #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
\r
4140 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
\r
4141 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
\r
4142 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
\r
4143 #define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
\r
4144 #define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
\r
4145 #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
\r
4146 #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
\r
4148 #define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)
\r
4149 #define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)
\r
4150 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
\r
4151 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
\r
4152 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
\r
4153 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
\r
4154 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
\r
4155 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
\r
4156 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
\r
4157 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
\r
4158 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
\r
4159 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
\r
4160 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
\r
4161 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
\r
4162 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
\r
4163 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
\r
4164 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
\r
4165 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
\r
4166 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
\r
4167 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
\r
4168 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
\r
4169 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
\r
4170 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
\r
4171 #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
\r
4172 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
\r
4173 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
\r
4174 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
\r
4175 #define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
\r
4176 #define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
\r
4177 #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
\r
4178 #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
\r
4180 /** @brief Force or release the APB2 peripheral reset.
\r
4182 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
\r
4183 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
\r
4184 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
\r
4185 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
\r
4186 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
\r
4187 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
\r
4188 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
\r
4189 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
\r
4190 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
\r
4191 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
\r
4192 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
\r
4193 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
\r
4194 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
\r
4195 #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
\r
4196 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
\r
4197 #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
\r
4199 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
\r
4200 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
\r
4201 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
\r
4202 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
\r
4203 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
\r
4204 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
\r
4205 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
\r
4206 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
\r
4207 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
\r
4208 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
\r
4209 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
\r
4210 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
\r
4211 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
\r
4212 #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
\r
4213 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
\r
4214 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
\r
4216 /** @brief Force or release the APB4 peripheral reset.
\r
4219 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFFU)
\r
4220 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
\r
4221 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
\r
4222 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
\r
4223 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
\r
4224 #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
\r
4225 #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
\r
4226 #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
\r
4227 #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
\r
4228 #define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
\r
4229 #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
\r
4230 #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
\r
4232 #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)
\r
4233 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
\r
4234 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
\r
4235 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
\r
4236 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
\r
4237 #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
\r
4238 #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
\r
4239 #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
\r
4240 #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
\r
4241 #define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
\r
4242 #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
\r
4243 #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
\r
4245 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
\r
4246 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4247 * power consumption.
\r
4248 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4249 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4253 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
\r
4254 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
\r
4257 #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
\r
4260 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
\r
4261 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
\r
4262 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
\r
4263 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
\r
4264 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
\r
4265 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
\r
4266 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
\r
4267 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
\r
4270 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
\r
4271 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
\r
4274 #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
\r
4277 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
\r
4278 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
\r
4279 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
\r
4280 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
\r
4281 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
\r
4282 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
\r
4283 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
\r
4284 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
\r
4287 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
\r
4288 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4289 * power consumption.
\r
4290 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4291 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4294 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)
\r
4295 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)
\r
4298 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U)
\r
4301 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)
\r
4302 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)
\r
4303 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U)
\r
4304 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)
\r
4305 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)
\r
4306 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)
\r
4307 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)
\r
4308 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
\r
4310 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)
\r
4311 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)
\r
4314 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U)
\r
4317 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)
\r
4318 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)
\r
4319 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U)
\r
4320 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)
\r
4321 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)
\r
4322 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)
\r
4323 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)
\r
4324 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
\r
4327 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
4328 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4329 * power consumption.
\r
4330 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4331 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4334 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
\r
4335 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
\r
4336 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
\r
4337 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
\r
4338 #if defined(DUAL_CORE)
\r
4339 #define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
\r
4340 #endif /*DUAL_CORE*/
\r
4341 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
\r
4342 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
\r
4343 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
\r
4344 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
\r
4345 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
\r
4346 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
\r
4348 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
\r
4349 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
\r
4350 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
\r
4351 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
\r
4352 #if defined(DUAL_CORE)
\r
4353 #define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
\r
4354 #endif /*DUAL_CORE*/
\r
4355 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
\r
4356 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
\r
4357 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
\r
4358 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
\r
4359 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
\r
4360 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
\r
4363 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
\r
4364 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4365 * power consumption.
\r
4366 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4367 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4370 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)
\r
4371 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)
\r
4372 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)
\r
4373 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U)
\r
4374 #if defined(DUAL_CORE)
\r
4375 #define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U)
\r
4376 #endif /*DUAL_CORE*/
\r
4377 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U)
\r
4378 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U)
\r
4379 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)
\r
4380 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
\r
4381 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U)
\r
4382 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
\r
4384 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)
\r
4385 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)
\r
4386 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)
\r
4387 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U)
\r
4388 #if defined(DUAL_CORE)
\r
4389 #define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U)
\r
4390 #endif /*DUAL_CORE*/
\r
4391 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U)
\r
4392 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U)
\r
4393 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)
\r
4394 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
\r
4395 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U)
\r
4396 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
\r
4399 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
4400 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4401 * power consumption.
\r
4402 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4403 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4406 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
\r
4407 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
\r
4408 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
\r
4409 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
\r
4410 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
\r
4411 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
\r
4412 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
\r
4413 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
\r
4415 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
\r
4416 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
\r
4417 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
\r
4418 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
\r
4419 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
\r
4420 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
\r
4421 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
\r
4422 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
\r
4425 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
\r
4426 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4427 * power consumption.
\r
4428 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4429 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4432 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)
\r
4433 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)
\r
4434 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)
\r
4435 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)
\r
4436 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)
\r
4437 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
\r
4438 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
\r
4439 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
\r
4441 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)
\r
4442 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)
\r
4443 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)
\r
4444 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)
\r
4445 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)
\r
4446 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
\r
4447 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
\r
4448 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
\r
4451 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
\r
4452 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4453 * power consumption.
\r
4454 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4455 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4458 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
\r
4459 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
\r
4460 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
\r
4461 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
\r
4462 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
\r
4463 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
\r
4464 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
\r
4465 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
\r
4466 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
\r
4467 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
\r
4468 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
\r
4469 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
\r
4470 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
\r
4471 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
\r
4472 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
\r
4473 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
\r
4475 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
\r
4476 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
\r
4477 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
\r
4478 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
\r
4479 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
\r
4480 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
\r
4481 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
\r
4482 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
\r
4483 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
\r
4484 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
\r
4485 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
\r
4486 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
\r
4487 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
\r
4488 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
\r
4489 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
\r
4490 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
\r
4493 /** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
\r
4494 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4495 * power consumption.
\r
4496 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4497 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4500 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)
\r
4501 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)
\r
4502 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)
\r
4503 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)
\r
4504 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)
\r
4505 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)
\r
4506 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)
\r
4507 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)
\r
4508 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)
\r
4509 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)
\r
4510 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)
\r
4511 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U)
\r
4512 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U)
\r
4513 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U)
\r
4514 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)
\r
4515 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
\r
4517 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)
\r
4518 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)
\r
4519 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)
\r
4520 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)
\r
4521 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)
\r
4522 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)
\r
4523 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)
\r
4524 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)
\r
4525 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)
\r
4526 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)
\r
4527 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)
\r
4528 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U)
\r
4529 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U)
\r
4530 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U)
\r
4531 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)
\r
4532 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
\r
4535 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
\r
4536 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4537 * power consumption.
\r
4538 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4539 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4543 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
\r
4547 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
\r
4549 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
\r
4552 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
\r
4556 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
\r
4558 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
\r
4561 /** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
\r
4562 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4563 * power consumption.
\r
4564 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4565 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4569 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U)
\r
4573 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U)
\r
4575 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
\r
4578 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U)
\r
4582 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U)
\r
4584 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
\r
4587 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
\r
4588 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4589 * power consumption.
\r
4590 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4591 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4594 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
\r
4595 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
\r
4596 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
\r
4597 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
\r
4598 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
\r
4599 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
\r
4600 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
\r
4601 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
\r
4602 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
\r
4603 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
\r
4605 #if defined(DUAL_CORE)
\r
4606 #define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
\r
4607 #endif /*DUAL_CORE*/
\r
4609 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
\r
4610 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
\r
4611 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
\r
4612 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
\r
4613 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
\r
4614 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
\r
4615 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
\r
4616 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
\r
4617 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
\r
4618 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
\r
4619 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
\r
4620 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
\r
4621 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
\r
4622 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
\r
4623 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
\r
4624 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
\r
4625 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
\r
4626 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
\r
4627 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
\r
4630 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
\r
4631 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
\r
4632 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
\r
4633 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
\r
4634 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
\r
4635 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
\r
4636 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
\r
4637 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
\r
4638 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
\r
4639 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
\r
4641 #if defined(DUAL_CORE)
\r
4642 #define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
\r
4643 #endif /*DUAL_CORE*/
\r
4645 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
\r
4646 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
\r
4647 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
\r
4648 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
\r
4649 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
\r
4650 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
\r
4651 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
\r
4652 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
\r
4653 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
\r
4654 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
\r
4655 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
\r
4656 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
\r
4657 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
\r
4658 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
\r
4659 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
\r
4660 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
\r
4661 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
\r
4662 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
\r
4663 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
\r
4666 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
\r
4667 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4668 * power consumption.
\r
4669 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4670 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4673 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)
\r
4674 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)
\r
4675 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)
\r
4676 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)
\r
4677 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)
\r
4678 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)
\r
4679 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)
\r
4680 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)
\r
4681 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)
\r
4682 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)
\r
4683 #if defined(DUAL_CORE)
\r
4684 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U)
\r
4685 #endif /*DUAL_CORE*/
\r
4686 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)
\r
4687 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)
\r
4688 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
\r
4689 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)
\r
4690 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)
\r
4691 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)
\r
4692 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)
\r
4693 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)
\r
4694 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)
\r
4695 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)
\r
4696 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)
\r
4697 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)
\r
4698 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)
\r
4699 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)
\r
4700 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)
\r
4701 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)
\r
4702 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)
\r
4703 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)
\r
4704 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)
\r
4706 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)
\r
4707 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)
\r
4708 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)
\r
4709 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)
\r
4710 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)
\r
4711 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)
\r
4712 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)
\r
4713 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)
\r
4714 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)
\r
4715 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)
\r
4716 #if defined(DUAL_CORE)
\r
4717 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U)
\r
4718 #endif /*DUAL_CORE*/
\r
4719 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)
\r
4720 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)
\r
4721 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
\r
4722 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)
\r
4723 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)
\r
4724 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)
\r
4725 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)
\r
4726 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)
\r
4727 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)
\r
4728 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)
\r
4729 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)
\r
4730 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)
\r
4731 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)
\r
4732 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)
\r
4733 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)
\r
4734 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)
\r
4735 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)
\r
4736 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)
\r
4737 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)
\r
4740 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
\r
4741 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4742 * power consumption.
\r
4743 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4744 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4747 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
\r
4748 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
\r
4749 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
\r
4750 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
\r
4751 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
\r
4752 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
\r
4753 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
\r
4754 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
\r
4755 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
\r
4756 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
\r
4757 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
\r
4758 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
\r
4759 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
\r
4760 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
\r
4761 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
\r
4763 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
\r
4764 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
\r
4765 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
\r
4766 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
\r
4767 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
\r
4768 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
\r
4769 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
\r
4770 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
\r
4771 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
\r
4772 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
\r
4773 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
\r
4774 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
\r
4775 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
\r
4776 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
\r
4777 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
\r
4780 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
\r
4781 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4782 * power consumption.
\r
4783 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4784 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4787 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)
\r
4788 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)
\r
4789 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
\r
4790 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
\r
4791 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
\r
4792 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)
\r
4793 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)
\r
4794 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)
\r
4795 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)
\r
4796 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)
\r
4797 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)
\r
4798 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)
\r
4799 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U)
\r
4800 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
\r
4801 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U)
\r
4803 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)
\r
4804 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)
\r
4805 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
\r
4806 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
\r
4807 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
\r
4808 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)
\r
4809 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)
\r
4810 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)
\r
4811 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)
\r
4812 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)
\r
4813 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)
\r
4814 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)
\r
4815 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U)
\r
4816 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
\r
4817 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U)
\r
4820 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
\r
4821 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4822 * power consumption.
\r
4823 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4824 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4827 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
\r
4828 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
\r
4829 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
\r
4830 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
\r
4831 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
\r
4832 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
\r
4833 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
\r
4834 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
\r
4835 #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
\r
4836 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
\r
4837 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
\r
4838 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
\r
4840 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
\r
4841 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
\r
4842 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
\r
4843 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
\r
4844 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
\r
4845 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
\r
4846 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
\r
4847 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
\r
4848 #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
\r
4849 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
\r
4850 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
\r
4851 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
\r
4855 /** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
\r
4856 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4857 * power consumption.
\r
4858 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4859 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4862 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)
\r
4863 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
\r
4864 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)
\r
4865 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)
\r
4866 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)
\r
4867 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)
\r
4868 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U)
\r
4869 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U)
\r
4870 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)
\r
4871 #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)
\r
4872 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)
\r
4873 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U)
\r
4875 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)
\r
4876 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
\r
4877 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)
\r
4878 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)
\r
4879 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)
\r
4880 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)
\r
4881 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U)
\r
4882 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U)
\r
4883 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)
\r
4884 #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)
\r
4885 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)
\r
4886 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U)
\r
4889 #if defined(DUAL_CORE)
\r
4891 /** @brief Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.
\r
4892 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4893 * power consumption.
\r
4894 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
4895 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
4897 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
\r
4898 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
\r
4899 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
\r
4900 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
\r
4901 #define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
\r
4902 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
\r
4903 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
\r
4904 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
\r
4905 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
\r
4906 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
\r
4907 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
\r
4910 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
\r
4911 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
\r
4912 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
\r
4913 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
\r
4914 #define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
\r
4915 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
\r
4916 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
\r
4917 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
\r
4918 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
\r
4919 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
\r
4920 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
\r
4924 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
4925 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4926 * power consumption.
\r
4927 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4928 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4931 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
\r
4932 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
\r
4933 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
\r
4934 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
\r
4935 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
\r
4936 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
\r
4937 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
\r
4938 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
\r
4939 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
\r
4940 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
\r
4942 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
\r
4943 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
\r
4944 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
\r
4945 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
\r
4946 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
\r
4947 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
\r
4948 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
\r
4949 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
\r
4950 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
\r
4951 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
\r
4953 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
4954 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4955 * power consumption.
\r
4956 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4957 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4960 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
\r
4961 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
\r
4962 #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
\r
4963 #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
\r
4964 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
\r
4965 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
\r
4966 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
\r
4967 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
\r
4969 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
\r
4970 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
\r
4971 #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
\r
4972 #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
\r
4973 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
\r
4974 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
\r
4975 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
\r
4976 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
\r
4978 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
\r
4979 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
4980 * power consumption.
\r
4981 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
4982 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
4985 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
\r
4986 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
\r
4987 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
\r
4988 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
\r
4989 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
\r
4990 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
\r
4991 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
\r
4992 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
\r
4993 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
\r
4994 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
\r
4995 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
\r
4996 #define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
\r
4997 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
\r
4998 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
\r
4999 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
\r
5000 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
\r
5002 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
\r
5003 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
\r
5004 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
\r
5005 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
\r
5006 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
\r
5007 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
\r
5008 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
\r
5009 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
\r
5010 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
\r
5011 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
\r
5012 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
\r
5013 #define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
\r
5014 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
\r
5015 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
\r
5016 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
\r
5017 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
\r
5019 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
\r
5020 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5021 * power consumption.
\r
5022 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5023 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5026 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
\r
5027 #define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
\r
5028 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
\r
5030 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
\r
5031 #define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
\r
5032 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
\r
5034 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
\r
5035 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5036 * power consumption.
\r
5037 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5038 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5041 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
\r
5042 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
\r
5043 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
\r
5044 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
\r
5045 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
\r
5046 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
\r
5047 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
\r
5048 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
\r
5049 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
\r
5050 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
\r
5051 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
\r
5052 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
\r
5053 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
\r
5054 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
\r
5055 #define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
\r
5056 #define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
\r
5057 #define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
\r
5058 #define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
\r
5059 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
\r
5060 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
\r
5061 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
\r
5062 #define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
\r
5063 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
\r
5064 #define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
\r
5065 #define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
\r
5066 #define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
\r
5067 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
\r
5068 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
\r
5069 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
\r
5070 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
\r
5073 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
\r
5074 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
\r
5075 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
\r
5076 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
\r
5077 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
\r
5078 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
\r
5079 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
\r
5080 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
\r
5081 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
\r
5082 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
\r
5083 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
\r
5084 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
\r
5085 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
\r
5086 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
\r
5087 #define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
\r
5088 #define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
\r
5089 #define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
\r
5090 #define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
\r
5091 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
\r
5092 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
\r
5093 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
\r
5094 #define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
\r
5095 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
\r
5096 #define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
\r
5097 #define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
\r
5098 #define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
\r
5099 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
\r
5100 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
\r
5101 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
\r
5102 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
\r
5104 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
\r
5105 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5106 * power consumption.
\r
5107 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5108 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5111 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
\r
5112 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
\r
5113 #define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
\r
5114 #define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
\r
5115 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
\r
5116 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
\r
5117 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
\r
5118 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
\r
5119 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
\r
5120 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
\r
5121 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
\r
5122 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
\r
5123 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
\r
5124 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
\r
5125 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
\r
5127 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
\r
5128 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
\r
5129 #define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
\r
5130 #define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
\r
5131 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
\r
5132 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
\r
5133 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
\r
5134 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
\r
5135 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
\r
5136 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
\r
5137 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
\r
5138 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
\r
5139 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
\r
5140 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
\r
5141 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
\r
5143 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
\r
5144 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5145 * power consumption.
\r
5146 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5147 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5150 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
\r
5151 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
\r
5152 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
\r
5153 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
\r
5154 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
\r
5155 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
\r
5156 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
\r
5157 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
\r
5158 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
\r
5159 #define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
\r
5160 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
\r
5161 #define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
\r
5164 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
\r
5165 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
\r
5166 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
\r
5167 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
\r
5168 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
\r
5169 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
\r
5170 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
\r
5171 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
\r
5172 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
\r
5173 #define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
\r
5174 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
\r
5175 #define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
\r
5177 /** @brief Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.
\r
5178 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5179 * power consumption.
\r
5180 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
5181 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
5185 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
\r
5186 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
\r
5187 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
\r
5188 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
\r
5189 #define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
\r
5190 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
\r
5191 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
\r
5192 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
\r
5193 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
\r
5194 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
\r
5195 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
\r
5198 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
\r
5199 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
\r
5200 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
\r
5201 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
\r
5202 #define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
\r
5203 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
\r
5204 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
\r
5205 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
\r
5206 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
\r
5207 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
\r
5208 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
\r
5212 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
5213 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5214 * power consumption.
\r
5215 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5216 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5219 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
\r
5220 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
\r
5221 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
\r
5222 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
\r
5223 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
\r
5224 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
\r
5225 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
\r
5226 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
\r
5227 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
\r
5228 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
\r
5230 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
\r
5231 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
\r
5232 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
\r
5233 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
\r
5234 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
\r
5235 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
\r
5236 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
\r
5237 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
\r
5238 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
\r
5239 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
\r
5241 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
5242 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5243 * power consumption.
\r
5244 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5245 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5248 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
\r
5249 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
\r
5250 #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
\r
5251 #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
\r
5252 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
\r
5253 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
\r
5254 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
\r
5255 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
\r
5257 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
\r
5258 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
\r
5259 #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
\r
5260 #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
\r
5261 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
\r
5262 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
\r
5263 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
\r
5264 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
\r
5266 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
\r
5267 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5268 * power consumption.
\r
5269 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5270 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5273 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
\r
5274 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
\r
5275 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
\r
5276 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
\r
5277 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
\r
5278 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
\r
5279 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
\r
5280 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
\r
5281 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
\r
5282 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
\r
5283 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
\r
5284 #define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
\r
5285 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
\r
5286 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
\r
5287 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
\r
5288 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
\r
5290 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
\r
5291 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
\r
5292 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
\r
5293 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
\r
5294 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
\r
5295 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
\r
5296 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
\r
5297 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
\r
5298 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
\r
5299 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
\r
5300 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
\r
5301 #define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
\r
5302 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
\r
5303 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
\r
5304 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
\r
5305 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
\r
5307 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
\r
5308 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5309 * power consumption.
\r
5310 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5311 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5314 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
\r
5315 #define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
\r
5316 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
\r
5318 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
\r
5319 #define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
\r
5320 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
\r
5322 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
\r
5323 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5324 * power consumption.
\r
5325 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5326 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5329 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
\r
5330 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
\r
5331 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
\r
5332 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
\r
5333 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
\r
5334 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
\r
5335 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
\r
5336 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
\r
5337 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
\r
5338 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
\r
5339 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
\r
5340 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
\r
5341 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
\r
5342 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
\r
5343 #define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
\r
5344 #define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
\r
5345 #define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
\r
5346 #define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
\r
5347 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
\r
5348 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
\r
5349 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
\r
5350 #define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
\r
5351 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
\r
5352 #define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
\r
5353 #define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
\r
5354 #define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
\r
5355 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
\r
5356 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
\r
5357 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
\r
5358 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
\r
5361 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
\r
5362 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
\r
5363 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
\r
5364 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
\r
5365 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
\r
5366 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
\r
5367 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
\r
5368 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
\r
5369 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
\r
5370 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
\r
5371 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
\r
5372 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
\r
5373 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
\r
5374 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
\r
5375 #define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
\r
5376 #define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
\r
5377 #define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
\r
5378 #define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
\r
5379 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
\r
5380 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
\r
5381 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
\r
5382 #define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
\r
5383 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
\r
5384 #define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
\r
5385 #define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
\r
5386 #define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
\r
5387 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
\r
5388 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
\r
5389 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
\r
5390 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
\r
5392 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
\r
5393 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5394 * power consumption.
\r
5395 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5396 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5399 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
\r
5400 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
\r
5401 #define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
\r
5402 #define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
\r
5403 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
\r
5404 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
\r
5405 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
\r
5406 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
\r
5407 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
\r
5408 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
\r
5409 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
\r
5410 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
\r
5411 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
\r
5412 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
\r
5413 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
\r
5415 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
\r
5416 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
\r
5417 #define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
\r
5418 #define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
\r
5419 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
\r
5420 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
\r
5421 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
\r
5422 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
\r
5423 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
\r
5424 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
\r
5425 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
\r
5426 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
\r
5427 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
\r
5428 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
\r
5429 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
\r
5431 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
\r
5432 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
5433 * power consumption.
\r
5434 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
\r
5435 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
\r
5438 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
\r
5439 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
\r
5440 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
\r
5441 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
\r
5442 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
\r
5443 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
\r
5444 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
\r
5445 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
\r
5446 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
\r
5447 #define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
\r
5448 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
\r
5449 #define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
\r
5451 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
\r
5452 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
\r
5453 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
\r
5454 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
\r
5455 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
\r
5456 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
\r
5457 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
\r
5458 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
\r
5459 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
\r
5460 #define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
\r
5461 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
\r
5462 #define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
\r
5464 #endif /*DUAL_CORE*/
\r
5466 #if defined(DUAL_CORE)
\r
5467 /** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN
\r
5468 * @note After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP
\r
5471 /** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN
\r
5472 * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP
\r
5474 #endif /*DUAL_CORE*/
\r
5476 #define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
\r
5477 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
\r
5478 #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
\r
5479 #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
\r
5480 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
\r
5481 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
\r
5482 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
\r
5483 #define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
\r
5484 #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
\r
5485 #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
\r
5486 #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
\r
5487 #define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
\r
5488 #define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
\r
5489 #define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
\r
5491 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
\r
5492 #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
\r
5494 #define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
\r
5495 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
\r
5496 #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
\r
5497 #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
\r
5498 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
\r
5499 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
\r
5500 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
\r
5501 #define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
\r
5502 #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
\r
5503 #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
\r
5504 #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN)
\r
5505 #define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN)
\r
5506 #define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN)
\r
5507 #define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN)
\r
5509 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
\r
5510 #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
\r
5513 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
\r
5514 * @note After enabling the HSI, the application software should wait on
\r
5515 * HSIRDY flag to be set indicating that HSI clock is stable and can
\r
5516 * be used to clock the PLL and/or system clock.
\r
5517 * @note HSI can not be stopped if it is used directly or through the PLL
\r
5518 * as system clock. In this case, you have to select another source
\r
5519 * of the system clock then stop the HSI.
\r
5520 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
\r
5521 * @param __STATE__ specifies the new state of the HSI.
\r
5522 * This parameter can be one of the following values:
\r
5523 * @arg RCC_HSI_OFF turn OFF the HSI oscillator
\r
5524 * @arg RCC_HSI_ON turn ON the HSI oscillator
\r
5525 * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
\r
5526 * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
\r
5527 * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
\r
5528 * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
\r
5529 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
\r
5532 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
\r
5533 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
\r
5536 /** @brief Macro to get the HSI divider.
\r
5537 * @retval The HSI divider. The returned value can be one
\r
5538 * of the following:
\r
5539 * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset)
\r
5540 * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2
\r
5541 * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4
\r
5542 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8
\r
5544 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
\r
5546 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
\r
5547 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
\r
5548 * It is used (enabled by hardware) as system clock source after start-up
\r
5549 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
\r
5550 * of the HSE used directly or indirectly as system clock (if the Clock
\r
5551 * Security System CSS is enabled).
\r
5552 * @note HSI can not be stopped if it is used as system clock source. In this case,
\r
5553 * you have to select another source of the system clock then stop the HSI.
\r
5554 * @note After enabling the HSI, the application software should wait on HSIRDY
\r
5555 * flag to be set indicating that HSI clock is stable and can be used as
\r
5556 * system clock source.
\r
5557 * This parameter can be: ENABLE or DISABLE.
\r
5558 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
\r
5561 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
\r
5562 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
\r
5565 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
\r
5566 * @note The calibration is used to compensate for the variations in voltage
\r
5567 * and temperature that influence the frequency of the internal HSI RC.
\r
5568 * @param __HSICalibrationValue__: specifies the calibration trimming value.
\r
5569 * This parameter must be a number between 0 and 0x7F (3F for Rev Y device).
\r
5571 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
\r
5573 if(HAL_GetREVID() <= REV_ID_Y) \
\r
5575 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);\
\r
5579 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \
\r
5584 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
\r
5585 * in STOP mode to be quickly available as kernel clock for some peripherals.
\r
5586 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
\r
5587 * speed because of the HSI start-up time.
\r
5588 * @note The enable of this function has not effect on the HSION bit.
\r
5589 * This parameter can be: ENABLE or DISABLE.
\r
5592 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
\r
5593 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
\r
5597 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
\r
5598 * @note After enabling the HSI48, the application software should wait on
\r
5599 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
\r
5600 * be used to clock the USB.
\r
5601 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
\r
5603 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
\r
5605 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
\r
5608 * @brief Macros to enable or disable the Internal oscillator (CSI).
\r
5609 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes.
\r
5610 * It is used (enabled by hardware) as system clock source after
\r
5611 * start-up from Reset, wakeup from STOP and STANDBY mode, or in case
\r
5612 * of failure of the HSE used directly or indirectly as system clock
\r
5613 * (if the Clock Security System CSS is enabled).
\r
5614 * @note CSI can not be stopped if it is used as system clock source.
\r
5615 * In this case, you have to select another source of the system
\r
5616 * clock then stop the CSI.
\r
5617 * @note After enabling the CSI, the application software should wait on
\r
5618 * CSIRDY flag to be set indicating that CSI clock is stable and can
\r
5619 * be used as system clock source.
\r
5620 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
\r
5623 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
\r
5624 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
\r
5626 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value.
\r
5627 * @note The calibration is used to compensate for the variations in voltage
\r
5628 * and temperature that influence the frequency of the internal CSI RC.
\r
5629 * @param __CSICalibrationValue__: specifies the calibration trimming value.
\r
5630 * This parameter must be a number between 0 and 0x1F.
\r
5632 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
\r
5634 if(HAL_GetREVID() <= REV_ID_Y) \
\r
5636 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \
\r
5640 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \
\r
5645 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
\r
5646 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
\r
5647 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
\r
5648 * speed because of the CSI start-up time.
\r
5649 * @note The enable of this function has not effect on the CSION bit.
\r
5650 * This parameter can be: ENABLE or DISABLE.
\r
5653 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
\r
5654 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
\r
5657 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
\r
5658 * @note After enabling the LSI, the application software should wait on
\r
5659 * LSIRDY flag to be set indicating that LSI clock is stable and can
\r
5660 * be used to clock the IWDG and/or the RTC.
\r
5661 * @note LSI can not be disabled if the IWDG is running.
\r
5662 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
\r
5665 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
\r
5666 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
\r
5669 * @brief Macro to configure the External High Speed oscillator (__HSE__).
\r
5670 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
\r
5671 * software should wait on HSERDY flag to be set indicating that HSE clock
\r
5672 * is stable and can be used to clock the PLL and/or system clock.
\r
5673 * @note HSE state can not be changed if it is used directly or through the
\r
5674 * PLL as system clock. In this case, you have to select another source
\r
5675 * of the system clock then change the HSE state (ex. disable it).
\r
5676 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
\r
5677 * @note This function reset the CSSON bit, so if the clock security system(CSS)
\r
5678 * was previously enabled you have to enable it again after calling this
\r
5680 * @param __STATE__: specifies the new state of the HSE.
\r
5681 * This parameter can be one of the following values:
\r
5682 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
\r
5683 * 6 HSE oscillator clock cycles.
\r
5684 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
\r
5685 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
\r
5687 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
\r
5689 if ((__STATE__) == RCC_HSE_ON) \
\r
5691 SET_BIT(RCC->CR, RCC_CR_HSEON); \
\r
5693 else if ((__STATE__) == RCC_HSE_OFF) \
\r
5695 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
\r
5696 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
5698 else if ((__STATE__) == RCC_HSE_BYPASS) \
\r
5700 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
5701 SET_BIT(RCC->CR, RCC_CR_HSEON); \
\r
5705 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
\r
5706 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
5710 /** @defgroup RCC_LSE_Configuration LSE Configuration
\r
5715 * @brief Macro to configure the External Low Speed oscillator (LSE).
\r
5716 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
\r
5717 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
\r
5718 * @note As the LSE is in the Backup domain and write access is denied to
\r
5719 * this domain after reset, you have to enable write access using
\r
5720 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
\r
5721 * (to be done once after reset).
\r
5722 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
\r
5723 * software should wait on LSERDY flag to be set indicating that LSE clock
\r
5724 * is stable and can be used to clock the RTC.
\r
5725 * @param __STATE__: specifies the new state of the LSE.
\r
5726 * This parameter can be one of the following values:
\r
5727 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
\r
5728 * 6 LSE oscillator clock cycles.
\r
5729 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
\r
5730 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
\r
5732 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
\r
5734 if((__STATE__) == RCC_LSE_ON) \
\r
5736 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
5738 else if((__STATE__) == RCC_LSE_OFF) \
\r
5740 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
5741 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
5743 else if((__STATE__) == RCC_LSE_BYPASS) \
\r
5745 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
5746 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
5750 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
5751 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
5758 /** @brief Macros to enable or disable the the RTC clock.
\r
5759 * @note These macros must be used only after the RTC clock source was selected.
\r
5761 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
\r
5762 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
\r
5764 /** @brief Macros to configure the RTC clock (RTCCLK).
\r
5765 * @note As the RTC clock configuration bits are in the Backup domain and write
\r
5766 * access is denied to this domain after reset, you have to enable write
\r
5767 * access using the Power Backup Access macro before to configure
\r
5768 * the RTC clock source (to be done once after reset).
\r
5769 * @note Once the RTC clock is configured it can't be changed unless the
\r
5770 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
\r
5771 * a Power On Reset (POR).
\r
5772 * @param __RTCCLKSource__: specifies the RTC clock source.
\r
5773 * This parameter can be one of the following values:
\r
5774 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
\r
5775 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
\r
5776 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
\r
5777 * as RTC clock, where x:[2,31]
\r
5778 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
\r
5779 * work in STOP and STANDBY modes, and can be used as wakeup source.
\r
5780 * However, when the HSE clock is used as RTC clock source, the RTC
\r
5781 * cannot be used in STOP and STANDBY modes.
\r
5782 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
\r
5783 * RTC clock source).
\r
5785 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
\r
5786 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
\r
5788 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
\r
5789 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
\r
5792 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
\r
5795 /** @brief Macros to force or release the Backup domain reset.
\r
5796 * @note This function resets the RTC peripheral (including the backup registers)
\r
5797 * and the RTC clock source selection in RCC_CSR register.
\r
5798 * @note The BKPSRAM is not affected by this reset.
\r
5800 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
\r
5801 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
\r
5803 /** @brief Macros to enable or disable the main PLL.
\r
5804 * @note After enabling the main PLL, the application software should wait on
\r
5805 * PLLRDY flag to be set indicating that PLL clock is stable and can
\r
5806 * be used as system clock source.
\r
5807 * @note The main PLL can not be disabled if it is used as system clock source
\r
5808 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
\r
5810 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
\r
5811 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
\r
5814 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
\r
5815 * @note Enabling/disabling those Clocks can be done only when the PLL is disabled.
\r
5816 * This is mainly used to save Power.
\r
5817 * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
\r
5818 * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
\r
5819 * This parameter can be one of the following values:
\r
5820 * @arg RCC_PLL1_DIVP: This clock is used to generate system clock (up to 400MHZ)
\r
5821 * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
\r
5822 * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
\r
5825 #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
\r
5827 #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
\r
5831 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
\r
5832 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1
\r
5835 #define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
\r
5837 #define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
\r
5841 * @brief Macro to configures the main PLL clock source, multiplication and division factors.
\r
5842 * @note This function must be used only when the main PLL is disabled.
\r
5844 * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
\r
5845 * This parameter can be one of the following values:
\r
5846 * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
\r
5847 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
\r
5848 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
\r
5849 * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
\r
5851 * @param __PLLM1__: specifies the division factor for PLL VCO input clock
\r
5852 * This parameter must be a number between 1 and 63.
\r
5853 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
\r
5854 * frequency ranges from 1 to 16 MHz.
\r
5856 * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock
\r
5857 * This parameter must be a number between 4 and 512.
\r
5858 * @note You have to set the PLLN parameter correctly to ensure that the VCO
\r
5859 * output frequency is between 150 and 420 MHz (when in medium VCO range) or
\r
5860 * between 192 and 836 MHZ (when in wide VCO range)
\r
5862 * @param __PLLP1__: specifies the division factor for system clock.
\r
5863 * This parameter must be a number between 2 and 128 (where odd numbers not allowed)
\r
5865 * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks
\r
5866 * This parameter must be a number between 1 and 128
\r
5868 * @param __PLLR1__: specifies the division factor for peripheral kernel clocks
\r
5869 * This parameter must be a number between 1 and 128
\r
5875 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
\r
5876 do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \
\r
5877 WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
\r
5878 ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
\r
5882 /** @brief Macro to configure the PLLs clock source.
\r
5883 * @note This function must be used only when all PLLs are disabled.
\r
5884 * @param __PLLSOURCE__: specifies the PLLs entry clock source.
\r
5885 * This parameter can be one of the following values:
\r
5886 * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
\r
5887 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
\r
5888 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
\r
5891 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
\r
5895 * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
\r
5897 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
\r
5899 * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
\r
5900 * It should be a value between 0 and 8191
\r
5901 * @note Warning: The software has to set correctly these bits to insure that the VCO
\r
5902 * output frequency is between its valid frequency range, which is:
\r
5903 * 192 to 836 MHz if PLL1VCOSEL = 0
\r
5904 * 150 to 420 MHz if PLL1VCOSEL = 1.
\r
5909 #define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
\r
5912 /** @brief Macro to select the PLL1 reference frequency range.
\r
5913 * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
\r
5914 * This parameter can be one of the following values:
\r
5915 * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
\r
5916 * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
\r
5917 * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
\r
5918 * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
\r
5921 #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
\r
5922 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
\r
5925 /** @brief Macro to select the PLL1 reference frequency range.
\r
5926 * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
\r
5927 * This parameter can be one of the following values:
\r
5928 * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz
\r
5929 * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
\r
5932 #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
\r
5933 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
\r
5937 /** @brief Macro to get the clock source used as system clock.
\r
5938 * @retval The clock source used as system clock. The returned value can be one
\r
5939 * of the following:
\r
5940 * - RCC_CFGR_SWS_CSI: CSI used as system clock.
\r
5941 * - RCC_CFGR_SWS_HSI: HSI used as system clock.
\r
5942 * - RCC_CFGR_SWS_HSE: HSE used as system clock.
\r
5943 * - RCC_CFGR_SWS_PLL: PLL used as system clock.
\r
5945 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
\r
5949 * @brief Macro to configure the system clock source.
\r
5950 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
\r
5951 * This parameter can be one of the following values:
\r
5952 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
\r
5953 * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
\r
5954 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
\r
5955 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
\r
5957 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
\r
5959 /** @brief Macro to get the oscillator used as PLL clock source.
\r
5960 * @retval The oscillator used as PLL clock source. The returned value can be one
\r
5961 * of the following:
\r
5962 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
\r
5963 * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
\r
5964 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
\r
5965 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
\r
5967 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
\r
5969 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
\r
5973 /** @brief Macro to configure the MCO1 clock.
\r
5974 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
\r
5975 * This parameter can be one of the following values:
\r
5976 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
\r
5977 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
\r
5978 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
\r
5979 * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
\r
5980 * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
\r
5981 * @param __MCODIV__ specifies the MCO clock prescaler.
\r
5982 * This parameter can be one of the following values:
\r
5983 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock
\r
5985 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
\r
5986 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
\r
5988 /** @brief Macro to configure the MCO2 clock.
\r
5989 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
\r
5990 * This parameter can be one of the following values:
\r
5991 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
\r
5992 * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
\r
5993 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
\r
5994 * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
\r
5995 * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
\r
5996 * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
\r
5997 * @param __MCODIV__ specifies the MCO clock prescaler.
\r
5998 * This parameter can be one of the following values:
\r
5999 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock
\r
6001 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
\r
6002 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
\r
6009 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
\r
6010 * @note As the LSE is in the Backup domain and write access is denied to
\r
6011 * this domain after reset, you have to enable write access using
\r
6012 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
\r
6013 * (to be done once after reset).
\r
6014 * @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
\r
6015 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
\r
6016 * This parameter can be one of the following values:
\r
6017 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
\r
6018 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
\r
6019 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
\r
6020 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
\r
6023 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
\r
6025 if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \
\r
6027 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \
\r
6031 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \
\r
6035 * @brief Macro to configure the wake up from stop clock.
\r
6036 * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
\r
6037 * This parameter can be one of the following values:
\r
6038 * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
\r
6039 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
\r
6042 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
\r
6043 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
\r
6046 * @brief Macro to configure the Kernel wake up from stop clock.
\r
6047 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
\r
6048 * This parameter can be one of the following values:
\r
6049 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
\r
6050 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
\r
6053 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
\r
6054 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
\r
6056 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
\r
6057 * @brief macros to manage the specified RCC Flags and interrupts.
\r
6060 /** @brief Enable RCC interrupt.
\r
6061 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
\r
6062 * This parameter can be any combination of the following values:
\r
6063 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
6064 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
6065 * @arg RCC_IT_CSIRDY: HSI ready interrupt
\r
6066 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
6067 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
6068 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
\r
6069 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
\r
6070 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
\r
6071 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
\r
6072 * @arg RCC_IT_LSECSS: Clock security system interrupt
\r
6074 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
\r
6076 /** @brief Disable RCC interrupt
\r
6077 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
\r
6078 * This parameter can be any combination of the following values:
\r
6079 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
6080 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
6081 * @arg RCC_IT_CSIRDY: HSI ready interrupt
\r
6082 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
6083 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
6084 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
\r
6085 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
\r
6086 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
\r
6087 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
\r
6088 * @arg RCC_IT_LSECSS: Clock security system interrupt
\r
6090 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
\r
6092 /** @brief Clear the RCC's interrupt pending bits
\r
6093 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
\r
6094 * This parameter can be any combination of the following values:
\r
6095 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
6096 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
6097 * @arg RCC_IT_CSIRDY: CSI ready interrupt
\r
6098 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
6099 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
6100 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
\r
6101 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
\r
6102 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
\r
6103 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
\r
6104 * @arg RCC_IT_HSECSS: HSE Clock Security interrupt
\r
6105 * @arg RCC_IT_LSECSS: Clock security system interrupt
\r
6107 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
\r
6109 /** @brief Check the RCC's interrupt has occurred or not.
\r
6110 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
\r
6111 * This parameter can be any combination of the following values:
\r
6112 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
6113 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
6114 * @arg RCC_IT_CSIRDY: CSI ready interrupt
\r
6115 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
6116 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
6117 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
\r
6118 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
\r
6119 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
\r
6120 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
\r
6121 * @arg RCC_IT_HSECSS: HSE Clock Security interrupt
\r
6122 * @arg RCC_IT_LSECSS: Clock security system interrupt
\r
6123 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
\r
6125 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
\r
6127 /** @brief Set RMVF bit to clear the reset flags.
\r
6129 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
\r
6131 #if defined(DUAL_CORE)
\r
6132 #define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
\r
6134 #define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
\r
6135 #endif /*DUAL_CORE*/
\r
6137 #if defined(DUAL_CORE)
\r
6138 /** @brief Check RCC flag is set or not.
\r
6139 * @param __FLAG__: specifies the flag to check.
\r
6140 * This parameter can be one of the following values:
\r
6141 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
\r
6142 * @arg RCC_FLAG_HSIDIV: HSI divider flag
\r
6143 * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
\r
6144 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
\r
6145 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
\r
6146 * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready
\r
6147 * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready
\r
6148 * @arg RCC_FLAG_PLLRDY: PLL1 clock ready
\r
6149 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
\r
6150 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
\r
6151 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
\r
6152 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
\r
6153 * @arg RCC_FLAG_C1RST: CPU reset flag
\r
6154 * @arg RCC_FLAG_C2RST: CPU2 reset flag
\r
6155 * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag
\r
6156 * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag
\r
6157 * @arg RCC_FLAG_BORRST: BOR reset flag
\r
6158 * @arg RCC_FLAG_PINRST: Pin reset
\r
6159 * @arg RCC_FLAG_PORRST: POR/PDR reset
\r
6160 * @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag
\r
6161 * @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag
\r
6162 * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag
\r
6163 * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
\r
6164 * @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset
\r
6165 * @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset
\r
6166 * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
\r
6167 * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
\r
6168 * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag
\r
6169 * @retval The new state of __FLAG__ (TRUE or FALSE).
\r
6171 #define RCC_FLAG_MASK ((uint8_t)0x1F)
\r
6172 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
\r
6173 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
\r
6175 #define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
\r
6176 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
\r
6178 #define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
\r
6179 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
\r
6183 /** @brief Check RCC flag is set or not.
\r
6184 * @param __FLAG__: specifies the flag to check.
\r
6185 * This parameter can be one of the following values:
\r
6186 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
\r
6187 * @arg RCC_FLAG_HSIDIV: HSI divider flag
\r
6188 * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
\r
6189 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
\r
6190 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
\r
6191 * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready
\r
6192 * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready
\r
6193 * @arg RCC_FLAG_PLLRDY: PLL1 clock ready
\r
6194 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
\r
6195 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
\r
6196 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
\r
6197 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
\r
6198 * @arg RCC_FLAG_CPURST: CPU reset flag
\r
6199 * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag
\r
6200 * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag
\r
6201 * @arg RCC_FLAG_BORRST: BOR reset flag
\r
6202 * @arg RCC_FLAG_PINRST: Pin reset
\r
6203 * @arg RCC_FLAG_PORRST: POR/PDR reset
\r
6204 * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
\r
6205 * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag
\r
6206 * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
\r
6207 * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
\r
6208 * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
\r
6209 * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
\r
6210 * @retval The new state of __FLAG__ (TRUE or FALSE).
\r
6212 #define RCC_FLAG_MASK ((uint8_t)0x1F)
\r
6213 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
\r
6214 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
\r
6216 #endif /*DUAL_CORE*/
\r
6222 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
\r
6228 /* Include RCC HAL Extension module */
\r
6229 #include "stm32h7xx_hal_rcc_ex.h"
\r
6231 /* Exported functions --------------------------------------------------------*/
\r
6232 /** @addtogroup RCC_Exported_Functions
\r
6236 /** @addtogroup RCC_Exported_Functions_Group1
\r
6239 /* Initialization and de-initialization functions ******************************/
\r
6240 HAL_StatusTypeDef HAL_RCC_DeInit(void);
\r
6241 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
\r
6242 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
\r
6248 /** @addtogroup RCC_Exported_Functions_Group2
\r
6251 /* Peripheral Control functions ************************************************/
\r
6252 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
\r
6253 void HAL_RCC_EnableCSS(void);
\r
6254 void HAL_RCC_DisableCSS(void);
\r
6255 uint32_t HAL_RCC_GetSysClockFreq(void);
\r
6256 uint32_t HAL_RCC_GetHCLKFreq(void);
\r
6257 uint32_t HAL_RCC_GetPCLK1Freq(void);
\r
6258 uint32_t HAL_RCC_GetPCLK2Freq(void);
\r
6259 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
\r
6260 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
\r
6261 /* CSS NMI IRQ handler */
\r
6262 void HAL_RCC_NMI_IRQHandler(void);
\r
6263 /* User Callbacks in non blocking mode (IT mode) */
\r
6264 void HAL_RCC_CCSCallback(void);
\r
6274 /* Private types -------------------------------------------------------------*/
\r
6275 /* Private variables ---------------------------------------------------------*/
\r
6276 /* Private constants ---------------------------------------------------------*/
\r
6277 /** @defgroup RCC_Private_Constants RCC Private Constants
\r
6281 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
\r
6282 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms */
\r
6283 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */
\r
6284 #define CSI_TIMEOUT_VALUE (2U) /* 2 ms */
\r
6285 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms */
\r
6286 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms */
\r
6287 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
\r
6288 #define RCC_DBP_TIMEOUT_VALUE (100U)
\r
6289 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
\r
6295 /* Private macros ------------------------------------------------------------*/
\r
6296 /** @addtogroup RCC_Private_Macros RCC Private Macros
\r
6300 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
\r
6304 #define HAL_RCC_REV_Y_HSITRIM_Pos (12U)
\r
6305 #define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U)
\r
6306 #define HAL_RCC_REV_Y_CSITRIM_Pos (26U)
\r
6307 #define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U)
\r
6309 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
\r
6310 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
\r
6311 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
\r
6312 (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
\r
6313 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
\r
6314 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
\r
6315 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
\r
6317 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
\r
6318 ((HSE) == RCC_HSE_BYPASS))
\r
6320 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
\r
6321 ((LSE) == RCC_LSE_BYPASS))
\r
6323 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \
\r
6324 ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
\r
6325 ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
\r
6327 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
\r
6329 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
\r
6331 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
\r
6333 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
\r
6334 ((PLL) == RCC_PLL_ON))
\r
6336 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \
\r
6337 ((SOURCE) == RCC_PLLSOURCE_HSI) || \
\r
6338 ((SOURCE) == RCC_PLLSOURCE_NONE) || \
\r
6339 ((SOURCE) == RCC_PLLSOURCE_HSE))
\r
6340 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
\r
6341 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
\r
6342 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
\r
6343 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
\r
6344 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
\r
6346 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
\r
6347 ((VALUE) == RCC_PLL1_DIVQ) || \
\r
6348 ((VALUE) == RCC_PLL1_DIVR))
\r
6350 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
\r
6352 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
\r
6353 ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
\r
6354 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
\r
6355 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
\r
6357 #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \
\r
6358 ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \
\r
6359 ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \
\r
6360 ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
\r
6361 ((SYSCLK) == RCC_SYSCLK_DIV512))
\r
6364 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \
\r
6365 ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \
\r
6366 ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \
\r
6367 ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
\r
6368 ((HCLK) == RCC_HCLK_DIV512))
\r
6370 #define IS_RCC_D1PCLK1(D1PCLK1) (((D1PCLK1) == RCC_APB3_DIV1) || ((D1PCLK1) == RCC_APB3_DIV2) || \
\r
6371 ((D1PCLK1) == RCC_APB3_DIV4) || ((D1PCLK1) == RCC_APB3_DIV8) || \
\r
6372 ((D1PCLK1) == RCC_APB3_DIV16))
\r
6374 #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
\r
6375 ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
\r
6376 ((PCLK1) == RCC_APB1_DIV16))
\r
6378 #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
\r
6379 ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
\r
6380 ((PCLK2) == RCC_APB2_DIV16))
\r
6382 #define IS_RCC_D3PCLK1(D3PCLK1) (((D3PCLK1) == RCC_APB4_DIV1) || ((D3PCLK1) == RCC_APB4_DIV2) || \
\r
6383 ((D3PCLK1) == RCC_APB4_DIV4) || ((D3PCLK1) == RCC_APB4_DIV8) || \
\r
6384 ((D3PCLK1) == RCC_APB4_DIV16))
\r
6386 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
\r
6387 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
\r
6388 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
\r
6389 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
\r
6390 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
\r
6391 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
\r
6392 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
\r
6393 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
\r
6394 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
\r
6395 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
\r
6396 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
\r
6397 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
\r
6398 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
\r
6399 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
\r
6400 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
\r
6401 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
\r
6402 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
\r
6403 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
\r
6404 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
\r
6405 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
\r
6406 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
\r
6407 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
\r
6408 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
\r
6409 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
\r
6410 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
\r
6411 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
\r
6412 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
\r
6413 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
\r
6414 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
\r
6415 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
\r
6416 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
\r
6417 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
\r
6419 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
\r
6421 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
\r
6422 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \
\r
6423 ((SOURCE) == RCC_MCO1SOURCE_HSI48))
\r
6425 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
\r
6426 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \
\r
6427 ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
\r
6429 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
\r
6430 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
\r
6431 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \
\r
6432 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \
\r
6433 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \
\r
6434 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \
\r
6435 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \
\r
6436 ((DIV) == RCC_MCODIV_15))
\r
6438 #if defined(DUAL_CORE)
\r
6439 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
\r
6440 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
\r
6441 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \
\r
6442 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
\r
6443 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
\r
6444 ((FLAG) == RCC_FLAG_LSIRDY) || \
\r
6445 ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \
\r
6446 ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
\r
6447 ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \
\r
6448 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \
\r
6449 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
\r
6450 ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
\r
6451 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
\r
6452 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV))
\r
6456 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
\r
6457 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
\r
6458 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \
\r
6459 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
\r
6460 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
\r
6461 ((FLAG) == RCC_FLAG_LSIRDY) || \
\r
6462 ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \
\r
6463 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \
\r
6464 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
\r
6465 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
\r
6466 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
\r
6467 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))
\r
6469 #endif /*DUAL_CORE*/
\r
6471 #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
\r
6472 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
\r
6474 #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
\r
6475 ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
\r
6477 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
\r
6478 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
\r
6494 #ifdef __cplusplus
\r
6498 #endif /* STM32H7xx_HAL_RCC_H */
\r
6500 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
projects / freertos / blob