2 ******************************************************************************
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3 * @file stm32h7xx_hal_dma_ex.c
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4 * @author MCD Application Team
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5 * @brief DMA Extension HAL module driver
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6 * This file provides firmware functions to manage the following
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7 * functionalities of the DMA Extension peripheral:
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8 * + Extended features functions
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11 ==============================================================================
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12 ##### How to use this driver #####
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13 ==============================================================================
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15 The DMA Extension HAL driver can be used as follows:
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16 (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
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17 for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
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19 (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
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20 (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
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21 Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
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22 to respectively enable/disable the request generator.
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24 (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
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25 the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
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26 As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
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27 called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
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28 (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
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30 -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
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31 -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
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32 -@- In Multi (Double) buffer mode, it is possible to update the base address for
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33 the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
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34 -@- Multi (Double) buffer mode is possible with DMA and BDMA instances.
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37 ******************************************************************************
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40 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
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41 * All rights reserved.</center></h2>
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43 * This software component is licensed by ST under BSD 3-Clause license,
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44 * the "License"; You may not use this file except in compliance with the
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45 * License. You may obtain a copy of the License at:
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46 * opensource.org/licenses/BSD-3-Clause
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48 ******************************************************************************
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51 /* Includes ------------------------------------------------------------------*/
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52 #include "stm32h7xx_hal.h"
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54 /** @addtogroup STM32H7xx_HAL_Driver
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58 /** @defgroup DMAEx DMAEx
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59 * @brief DMA Extended HAL module driver
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63 #ifdef HAL_DMA_MODULE_ENABLED
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65 /* Private types -------------------------------------------------------------*/
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66 /* Private variables ---------------------------------------------------------*/
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67 /* Private Constants ---------------------------------------------------------*/
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68 /* Private macros ------------------------------------------------------------*/
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69 /* Private functions ---------------------------------------------------------*/
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70 /** @addtogroup DMAEx_Private_Functions
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74 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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80 /* Exported functions ---------------------------------------------------------*/
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82 /** @addtogroup DMAEx_Exported_Functions
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87 /** @addtogroup DMAEx_Exported_Functions_Group1
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90 ===============================================================================
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91 ##### Extended features functions #####
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92 ===============================================================================
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93 [..] This section provides functions allowing to:
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94 (+) Configure the source, destination address and data length and
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95 Start MultiBuffer DMA transfer
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96 (+) Configure the source, destination address and data length and
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97 Start MultiBuffer DMA transfer with interrupt
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98 (+) Change on the fly the memory0 or memory1 address.
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99 (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
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100 (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
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101 (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
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102 to respectively enable/disable the request generator.
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103 (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
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104 the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
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112 * @brief Starts the multi_buffer DMA Transfer.
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113 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
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114 * the configuration information for the specified DMA Stream.
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115 * @param SrcAddress: The source memory Buffer address
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116 * @param DstAddress: The destination memory Buffer address
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117 * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
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118 * @param DataLength: The length of data to be transferred from source to destination
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119 * @retval HAL status
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121 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
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123 HAL_StatusTypeDef status = HAL_OK;
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124 __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
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126 /* Check the parameters */
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127 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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128 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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130 /* Memory-to-memory transfer not supported in double buffering mode */
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131 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
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133 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
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134 status = HAL_ERROR;
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138 /* Process Locked */
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141 if(HAL_DMA_STATE_READY == hdma->State)
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143 /* Change DMA peripheral state */
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144 hdma->State = HAL_DMA_STATE_BUSY;
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146 /* Initialize the error code */
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147 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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149 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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151 /* Enable the Double buffer mode */
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152 ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
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154 /* Configure DMA Stream destination address */
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155 ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
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157 /* Calculate the interrupt clear flag register (IFCR) base address */
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158 ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
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160 /* Clear all flags */
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161 *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
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163 else /* BDMA instance(s) */
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165 /* Enable the Double buffer mode */
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166 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
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168 /* Configure DMA Stream destination address */
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169 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
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171 /* Calculate the interrupt clear flag register (IFCR) base address */
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172 ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
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174 /* Clear all flags */
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175 *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
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178 /* Configure the source, destination address and the data length */
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179 DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
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181 /* Clear the DMAMUX synchro overrun flag */
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182 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
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184 if(hdma->DMAmuxRequestGen != 0U)
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186 /* Clear the DMAMUX request generator overrun flag */
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187 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
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190 /* Enable the peripheral */
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191 __HAL_DMA_ENABLE(hdma);
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195 /* Set the error code to busy */
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196 hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
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198 /* Return error status */
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199 status = HAL_ERROR;
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206 * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
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207 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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208 * the configuration information for the specified DMA Stream.
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209 * @param SrcAddress: The source memory Buffer address
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210 * @param DstAddress: The destination memory Buffer address
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211 * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
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212 * @param DataLength: The length of data to be transferred from source to destination
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213 * @retval HAL status
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215 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
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217 HAL_StatusTypeDef status = HAL_OK;
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218 __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
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220 /* Check the parameters */
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221 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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222 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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224 /* Memory-to-memory transfer not supported in double buffering mode */
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225 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
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227 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
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231 /* Process locked */
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234 if(HAL_DMA_STATE_READY == hdma->State)
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236 /* Change DMA peripheral state */
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237 hdma->State = HAL_DMA_STATE_BUSY;
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239 /* Initialize the error code */
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240 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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242 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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244 /* Enable the Double buffer mode */
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245 ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
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247 /* Configure DMA Stream destination address */
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248 ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
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250 /* Calculate the interrupt clear flag register (IFCR) base address */
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251 ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
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253 /* Clear all flags */
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254 *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
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256 else /* BDMA instance(s) */
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258 /* Enable the Double buffer mode */
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259 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
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261 /* Configure DMA Stream destination address */
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262 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
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264 /* Calculate the interrupt clear flag register (IFCR) base address */
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265 ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
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267 /* Clear all flags */
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268 *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
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271 /* Configure the source, destination address and the data length */
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272 DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
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274 /* Clear the DMAMUX synchro overrun flag */
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275 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
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277 if(hdma->DMAmuxRequestGen != 0U)
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279 /* Clear the DMAMUX request generator overrun flag */
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280 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
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283 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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285 /* Enable Common interrupts*/
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286 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
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287 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
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289 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
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291 /*Enable Half Transfer IT if corresponding Callback is set*/
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292 ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
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295 else /* BDMA instance(s) */
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297 /* Enable Common interrupts*/
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298 MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
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300 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
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302 /*Enable Half Transfer IT if corresponding Callback is set*/
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303 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;
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307 /* Check if DMAMUX Synchronization is enabled*/
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308 if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
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310 /* Enable DMAMUX sync overrun IT*/
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311 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
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314 if(hdma->DMAmuxRequestGen != 0U)
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316 /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
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317 /* enable the request gen overrun IT*/
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318 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
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321 /* Enable the peripheral */
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322 __HAL_DMA_ENABLE(hdma);
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326 /* Set the error code to busy */
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327 hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
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329 /* Return error status */
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330 status = HAL_ERROR;
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336 * @brief Change the memory0 or memory1 address on the fly.
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337 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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338 * the configuration information for the specified DMA Stream.
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339 * @param Address: The new address
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340 * @param memory: the memory to be changed, This parameter can be one of
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341 * the following values:
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344 * @note The MEMORY0 address can be changed only when the current transfer use
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345 * MEMORY1 and the MEMORY1 address can be changed only when the current
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346 * transfer use MEMORY0.
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347 * @retval HAL status
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349 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
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351 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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353 if(memory == MEMORY0)
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355 /* change the memory0 address */
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356 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;
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360 /* change the memory1 address */
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361 ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;
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364 else /* BDMA instance(s) */
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366 if(memory == MEMORY0)
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368 /* change the memory0 address */
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369 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address;
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373 /* change the memory1 address */
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374 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address;
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382 * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
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383 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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384 * the configuration information for the specified DMA Stream.
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385 * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
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386 * @retval HAL status
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388 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
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390 uint32_t syncSignalID = 0;
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391 uint32_t syncPolarity = 0;
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393 /* Check the parameters */
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394 assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
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395 assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
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396 assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
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397 assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
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399 if(pSyncConfig->SyncEnable == ENABLE)
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401 assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
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403 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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405 assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
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409 assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
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411 syncSignalID = pSyncConfig->SyncSignalID;
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412 syncPolarity = pSyncConfig->SyncPolarity;
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415 /*Check if the DMA state is ready */
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416 if(hdma->State == HAL_DMA_STATE_READY)
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418 /* Process Locked */
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421 /* Disable the synchronization and event generation before applying a new config */
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422 CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
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424 /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
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425 MODIFY_REG( hdma->DMAmuxChannel->CCR, \
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426 (~DMAMUX_CxCR_DMAREQ_ID) , \
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427 (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \
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428 ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
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429 syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
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430 ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
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432 /* Process Locked */
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433 __HAL_UNLOCK(hdma);
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439 /* Set the error code to busy */
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440 hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
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442 /* Return error status */
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448 * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).
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449 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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450 * the configuration information for the specified DMA Stream.
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451 * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
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452 * contains the request generator parameters.
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454 * @retval HAL status
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456 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
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458 HAL_StatusTypeDef status;
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459 HAL_DMA_StateTypeDef temp_state = hdma->State;
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461 /* Check the parameters */
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462 assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
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464 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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466 assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
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470 assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
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474 assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
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475 assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
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477 /* check if the DMA state is ready
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478 and DMA is using a DMAMUX request generator block
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480 if(hdma->DMAmuxRequestGen == 0U)
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482 /* Set the error code to busy */
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483 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
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486 status = HAL_ERROR;
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488 else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
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490 /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
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492 /* Process Locked */
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495 /* Set the request generator new parameters */
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496 hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
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497 ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
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498 pRequestGeneratorConfig->Polarity;
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499 /* Process Locked */
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500 __HAL_UNLOCK(hdma);
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506 /* Set the error code to busy */
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507 hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
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510 status = HAL_ERROR;
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517 * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).
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518 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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519 * the configuration information for the specified DMA Stream.
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520 * @retval HAL status
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522 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
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524 /* Check the parameters */
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525 assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
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527 /* check if the DMA state is ready
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528 and DMA is using a DMAMUX request generator block */
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529 if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
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531 /* Enable the request generator*/
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532 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
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543 * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).
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544 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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545 * the configuration information for the specified DMA Stream.
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546 * @retval HAL status
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548 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
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550 /* Check the parameters */
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551 assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
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553 /* check if the DMA state is ready
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554 and DMA is using a DMAMUX request generator block */
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555 if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
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557 /* Disable the request generator*/
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558 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
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569 * @brief Handles DMAMUX interrupt request.
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570 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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571 * the configuration information for the specified DMA Stream.
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574 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
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576 /* Check for DMAMUX Synchronization overrun */
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577 if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
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579 /* Disable the synchro overrun interrupt */
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580 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
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582 /* Clear the DMAMUX synchro overrun flag */
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583 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
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585 /* Update error code */
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586 hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
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588 if(hdma->XferErrorCallback != NULL)
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590 /* Transfer error callback */
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591 hdma->XferErrorCallback(hdma);
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595 if(hdma->DMAmuxRequestGen != 0)
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597 /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
\r
598 if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
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600 /* Disable the request gen overrun interrupt */
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601 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
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603 /* Clear the DMAMUX request generator overrun flag */
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604 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
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606 /* Update error code */
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607 hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
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609 if(hdma->XferErrorCallback != NULL)
\r
611 /* Transfer error callback */
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612 hdma->XferErrorCallback(hdma);
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627 /** @addtogroup DMAEx_Private_Functions
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632 * @brief Set the DMA Transfer parameter.
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633 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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634 * the configuration information for the specified DMA Stream.
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635 * @param SrcAddress: The source memory Buffer address
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636 * @param DstAddress: The destination memory Buffer address
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637 * @param DataLength: The length of data to be transferred from source to destination
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638 * @retval HAL status
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640 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
\r
642 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
\r
644 /* Configure DMA Stream data length */
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645 ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
\r
647 /* Peripheral to Memory */
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648 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
\r
650 /* Configure DMA Stream destination address */
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651 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
\r
653 /* Configure DMA Stream source address */
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654 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
\r
656 /* Memory to Peripheral */
\r
659 /* Configure DMA Stream source address */
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660 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
\r
662 /* Configure DMA Stream destination address */
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663 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
\r
666 else /* BDMA instance(s) */
\r
668 /* Configure DMA Stream data length */
\r
669 ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
\r
671 /* Peripheral to Memory */
\r
672 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
\r
674 /* Configure DMA Stream destination address */
\r
675 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
\r
677 /* Configure DMA Stream source address */
\r
678 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
\r
680 /* Memory to Peripheral */
\r
683 /* Configure DMA Stream source address */
\r
684 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
\r
686 /* Configure DMA Stream destination address */
\r
687 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
\r
696 #endif /* HAL_DMA_MODULE_ENABLED */
\r
705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r