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31 ******************************************************************************/
33 /*****************************************************************************/
36 * @addtogroup bram_v4_0
39 * Implements BRAM interrupt processing functions for the
40 * XBram driver. See xbram.h for more information
43 * The functions in this file require the hardware device to be built with
44 * interrupt capabilities. The functions will assert if called using hardware
45 * that does not have interrupt capabilities.
48 * MODIFICATION HISTORY:
50 * Ver Who Date Changes
51 * ----- ---- -------- -----------------------------------------------
52 * 1.00a sa 05/11/10 Initial release
55 *****************************************************************************/
57 /***************************** Include Files ********************************/
61 /************************** Constant Definitions ****************************/
63 /**************************** Type Definitions ******************************/
65 /***************** Macros (Inline Functions) Definitions ********************/
67 /************************** Variable Definitions ****************************/
69 /************************** Function Prototypes *****************************/
72 /****************************************************************************/
74 * Enable interrupts. This function will assert if the hardware device has not
75 * been built with interrupt capabilities.
77 * @param InstancePtr is the BRAM instance to operate on.
78 * @param Mask is the mask to enable. Bit positions of 1 are enabled.
79 * This mask is formed by OR'ing bits from XBRAM_IR*
80 * bits which are contained in xbram_hw.h.
86 *****************************************************************************/
87 void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
91 Xil_AssertVoid(InstancePtr != NULL);
92 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
93 Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
96 * Read the interrupt enable register and only enable the specified
97 * interrupts without disabling or enabling any others.
99 Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
100 XBRAM_ECC_EN_IRQ_OFFSET);
101 XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
102 XBRAM_ECC_EN_IRQ_OFFSET,
107 /****************************************************************************/
109 * Disable interrupts. This function allows each specific interrupt to be
110 * disabled. This function will assert if the hardware device has not been
111 * built with interrupt capabilities.
113 * @param InstancePtr is the BRAM instance to operate on.
114 * @param Mask is the mask to disable. Bits set to 1 are disabled. This
115 * mask is formed by OR'ing bits from XBRAM_IR* bits
116 * which are contained in xbram_hw.h.
122 *****************************************************************************/
123 void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask)
127 Xil_AssertVoid(InstancePtr != NULL);
128 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
129 Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
132 * Read the interrupt enable register and only disable the specified
133 * interrupts without enabling or disabling any others.
135 Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
136 XBRAM_ECC_EN_IRQ_OFFSET);
137 XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
138 XBRAM_ECC_EN_IRQ_OFFSET,
142 /****************************************************************************/
144 * Clear pending interrupts with the provided mask. This function should be
145 * called after the software has serviced the interrupts that are pending.
146 * This function will assert if the hardware device has not been built with
147 * interrupt capabilities.
149 * @param InstancePtr is the BRAM instance to operate on.
150 * @param Mask is the mask to clear pending interrupts for. Bit positions
151 * of 1 are cleared. This mask is formed by OR'ing bits from
152 * XBRAM_IR* bits which are contained in
159 *****************************************************************************/
160 void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
164 Xil_AssertVoid(InstancePtr != NULL);
165 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
166 Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
169 * Read the interrupt status register and only clear the interrupts
170 * that are specified without affecting any others. Since the register
171 * is a toggle on write, make sure any bits to be written are already
174 Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
175 XBRAM_ECC_STATUS_OFFSET);
176 XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
177 XBRAM_ECC_STATUS_OFFSET,
184 /****************************************************************************/
186 * Returns the interrupt enable mask. This function will assert if the
187 * hardware device has not been built with interrupt capabilities.
189 * @param InstancePtr is the BRAM instance to operate on.
191 * @return A mask of bits made from XBRAM_IR* bits which
192 * are contained in xbram_hw.h.
198 *****************************************************************************/
199 u32 XBram_InterruptGetEnabled(XBram * InstancePtr)
201 Xil_AssertNonvoid(InstancePtr != NULL);
202 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
203 Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
205 return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
206 XBRAM_ECC_EN_IRQ_OFFSET);
210 /****************************************************************************/
212 * Returns the status of interrupt signals. Any bit in the mask set to 1
213 * indicates that the channel associated with the bit has asserted an interrupt
214 * condition. This function will assert if the hardware device has not been
215 * built with interrupt capabilities.
217 * @param InstancePtr is the BRAM instance to operate on.
219 * @return A pointer to a mask of bits made from XBRAM_IR*
220 * bits which are contained in xbram_hw.h.
224 * The interrupt status indicates the status of the device irregardless if
225 * the interrupts from the devices have been enabled or not through
226 * XBram_InterruptEnable().
228 *****************************************************************************/
229 u32 XBram_InterruptGetStatus(XBram * InstancePtr)
231 Xil_AssertNonvoid(InstancePtr != NULL);
232 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
233 Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
235 return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
236 XBRAM_ECC_EN_IRQ_OFFSET);