<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
<storageModule moduleId="org.eclipse.cdt.core.settings">\r
- <cconfiguration id="org.eclipse.cdt.core.default.config.1741365255">\r
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1741365255" moduleId="org.eclipse.cdt.core.settings" name="Configuration">\r
+ <cconfiguration id="org.eclipse.cdt.core.default.config.1709418136">\r
+ <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1709418136" moduleId="org.eclipse.cdt.core.settings" name="Configuration">\r
<externalSettings/>\r
<extensions/>\r
</storageModule>\r
<?xml version="1.0" encoding="UTF-8"?>\r
<projectDescription>\r
<name>BSP</name>\r
- <comment>Created by SDK v2014.4</comment>\r
+ <comment>Created by SDK v2016.1</comment>\r
<projects>\r
</projects>\r
<buildSpec>\r
\r
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)\r
@echo "Running Make include in $(subst /make.include,,$@)"\r
- $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"\r
+ $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.6 -mlittle-endian -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g"\r
\r
%/make.libs: include\r
@echo "Running Make libs in $(subst /make.libs,,$@)"\r
- $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"\r
+ $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.6 -mlittle-endian -mno-xl-soft-div -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g"\r
\r
clean:\r
rm -f ${PROCESSOR}/lib/libxil.a\r
\r
\r
/* Definitions for peripheral MICROBLAZE_0 */\r
-#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 15\r
+#define XPAR_MICROBLAZE_0_ADDR_SIZE 32\r
+#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 16\r
#define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1\r
#define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1\r
#define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0\r
#define XPAR_MICROBLAZE_0_ASYNC_INTERRUPT 1\r
+#define XPAR_MICROBLAZE_0_ASYNC_WAKEUP 3\r
#define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0\r
-#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x00000000\r
+#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x0000000000000000\r
#define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0\r
#define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 32768\r
+#define XPAR_MICROBLAZE_0_DADDR_SIZE 32\r
#define XPAR_MICROBLAZE_0_DATA_SIZE 32\r
-#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 15\r
+#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 16\r
#define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 1\r
#define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x80000000\r
#define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 32768\r
#define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 0\r
#define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0\r
-#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xBFFFFFFF\r
+#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0xFFFFFFFF\r
#define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 8\r
-#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 1\r
-#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 8\r
+#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 0\r
+#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 0\r
+#define XPAR_MICROBLAZE_0_DC_AXI_MON 0\r
#define XPAR_MICROBLAZE_0_DEBUG_COUNTER_WIDTH 32\r
-#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1\r
+#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 2\r
#define XPAR_MICROBLAZE_0_DEBUG_EVENT_COUNTERS 5\r
#define XPAR_MICROBLAZE_0_DEBUG_EXTERNAL_TRACE 0\r
#define XPAR_MICROBLAZE_0_DEBUG_LATENCY_COUNTERS 1\r
#define XPAR_MICROBLAZE_0_DEBUG_PROFILE_SIZE 0\r
#define XPAR_MICROBLAZE_0_DEBUG_TRACE_SIZE 8192\r
-#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 0\r
+#define XPAR_MICROBLAZE_0_DP_AXI_MON 0\r
#define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 0\r
#define XPAR_MICROBLAZE_0_D_AXI 1\r
#define XPAR_MICROBLAZE_0_D_LMB 1\r
+#define XPAR_MICROBLAZE_0_D_LMB_MON 0\r
#define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0\r
#define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1\r
#define XPAR_MICROBLAZE_0_ENABLE_DISCRETE_PORTS 0\r
#define XPAR_MICROBLAZE_0_ENDIANNESS 1\r
#define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0\r
-#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 0\r
#define XPAR_MICROBLAZE_0_FREQ 100000000\r
#define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0\r
#define XPAR_MICROBLAZE_0_FSL_LINKS 0\r
+#define XPAR_MICROBLAZE_0_IADDR_SIZE 32\r
#define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 1\r
#define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x80000000\r
#define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 0\r
#define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0\r
-#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xBFFFFFFF\r
+#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0xFFFFFFFF\r
#define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 8\r
-#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 1\r
-#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 8\r
-#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 0\r
+#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 0\r
+#define XPAR_MICROBLAZE_0_IC_AXI_MON 0\r
+#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 0\r
+#define XPAR_MICROBLAZE_0_IMPRECISE_EXCEPTIONS 0\r
+#define XPAR_MICROBLAZE_0_INSTR_SIZE 32\r
#define XPAR_MICROBLAZE_0_INTERCONNECT 2\r
#define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0\r
+#define XPAR_MICROBLAZE_0_INTERRUPT_MON 0\r
+#define XPAR_MICROBLAZE_0_IP_AXI_MON 0\r
#define XPAR_MICROBLAZE_0_I_AXI 0\r
#define XPAR_MICROBLAZE_0_I_LMB 1\r
+#define XPAR_MICROBLAZE_0_I_LMB_MON 0\r
#define XPAR_MICROBLAZE_0_LOCKSTEP_SELECT 0\r
#define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0\r
#define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2\r
#define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0\r
#define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3\r
-#define XPAR_MICROBLAZE_0_MMU_ZONES 2\r
+#define XPAR_MICROBLAZE_0_MMU_ZONES 16\r
#define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32\r
#define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0\r
#define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1\r
-#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 0\r
#define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32\r
#define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32\r
#define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1\r
-#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 0\r
#define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 8\r
#define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 2\r
#define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 2\r
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_DEBUG 2\r
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_CLK_IRQ 1\r
#define XPAR_MICROBLAZE_0_NUM_SYNC_FF_DBG_CLK 1\r
-#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 1\r
+#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 0\r
#define XPAR_MICROBLAZE_0_OPTIMIZATION 0\r
#define XPAR_MICROBLAZE_0_PC_WIDTH 32\r
#define XPAR_MICROBLAZE_0_PVR 0\r
#define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC\r
#define XPAR_MICROBLAZE_0_SCO 0\r
-#define XPAR_MICROBLAZE_0_TRACE 1\r
-#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 1\r
+#define XPAR_MICROBLAZE_0_TRACE 0\r
+#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 0\r
#define XPAR_MICROBLAZE_0_USE_BARREL 1\r
#define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 1\r
#define XPAR_MICROBLAZE_0_USE_CONFIG_RESET 0\r
#define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0\r
#define XPAR_MICROBLAZE_0_USE_EXT_BRK 0\r
#define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 0\r
-#define XPAR_MICROBLAZE_0_USE_FPU 2\r
-#define XPAR_MICROBLAZE_0_USE_HW_MUL 2\r
+#define XPAR_MICROBLAZE_0_USE_FPU 0\r
+#define XPAR_MICROBLAZE_0_USE_HW_MUL 0\r
#define XPAR_MICROBLAZE_0_USE_ICACHE 1\r
-#define XPAR_MICROBLAZE_0_USE_INTERRUPT 1\r
+#define XPAR_MICROBLAZE_0_USE_INTERRUPT 0\r
#define XPAR_MICROBLAZE_0_USE_MMU 0\r
#define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1\r
+#define XPAR_MICROBLAZE_0_USE_NON_SECURE 0\r
#define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1\r
#define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1\r
-#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 1\r
-#define XPAR_MICROBLAZE_0_COMPONENT_NAME base_microblaze_design_microblaze_0_0\r
+#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 0\r
+#define XPAR_MICROBLAZE_0_COMPONENT_NAME mb_subsystem_microblaze_0_0\r
#define XPAR_MICROBLAZE_0_EDK_IPTYPE PROCESSOR\r
#define XPAR_MICROBLAZE_0_EDK_SPECIAL microblaze\r
-#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 2\r
-#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 1\r
+#define XPAR_MICROBLAZE_0_G_TEMPLATE_LIST 0\r
+#define XPAR_MICROBLAZE_0_G_USE_EXCEPTIONS 0\r
\r
/******************************************************************/\r
\r
#define XPAR_CPU_ID 0\r
#define XPAR_MICROBLAZE_ID 0\r
-#define XPAR_MICROBLAZE_ADDR_TAG_BITS 15\r
+#define XPAR_MICROBLAZE_ADDR_SIZE 32\r
+#define XPAR_MICROBLAZE_ADDR_TAG_BITS 16\r
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1\r
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1\r
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0\r
#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1\r
+#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3\r
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0\r
-#define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000\r
+#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000\r
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0\r
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 32768\r
+#define XPAR_MICROBLAZE_DADDR_SIZE 32\r
#define XPAR_MICROBLAZE_DATA_SIZE 32\r
-#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 15\r
+#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 16\r
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1\r
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000\r
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 32768\r
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0\r
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0\r
-#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xBFFFFFFF\r
+#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0xFFFFFFFF\r
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 8\r
-#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1\r
-#define XPAR_MICROBLAZE_DCACHE_VICTIMS 8\r
+#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0\r
+#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0\r
+#define XPAR_MICROBLAZE_DC_AXI_MON 0\r
#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32\r
-#define XPAR_MICROBLAZE_DEBUG_ENABLED 1\r
+#define XPAR_MICROBLAZE_DEBUG_ENABLED 2\r
#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5\r
#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0\r
#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1\r
#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0\r
#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192\r
-#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0\r
+#define XPAR_MICROBLAZE_DP_AXI_MON 0\r
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0\r
#define XPAR_MICROBLAZE_D_AXI 1\r
#define XPAR_MICROBLAZE_D_LMB 1\r
+#define XPAR_MICROBLAZE_D_LMB_MON 0\r
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0\r
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1\r
#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0\r
#define XPAR_MICROBLAZE_ENDIANNESS 1\r
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0\r
-#define XPAR_MICROBLAZE_FPU_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_FPU_EXCEPTION 0\r
#define XPAR_MICROBLAZE_FREQ 100000000\r
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0\r
#define XPAR_MICROBLAZE_FSL_LINKS 0\r
+#define XPAR_MICROBLAZE_IADDR_SIZE 32\r
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1\r
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000\r
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0\r
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0\r
-#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xBFFFFFFF\r
+#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0xFFFFFFFF\r
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 8\r
-#define XPAR_MICROBLAZE_ICACHE_STREAMS 1\r
-#define XPAR_MICROBLAZE_ICACHE_VICTIMS 8\r
-#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_ICACHE_STREAMS 0\r
+#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0\r
+#define XPAR_MICROBLAZE_IC_AXI_MON 0\r
+#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0\r
+#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0\r
+#define XPAR_MICROBLAZE_INSTR_SIZE 32\r
#define XPAR_MICROBLAZE_INTERCONNECT 2\r
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0\r
+#define XPAR_MICROBLAZE_INTERRUPT_MON 0\r
+#define XPAR_MICROBLAZE_IP_AXI_MON 0\r
#define XPAR_MICROBLAZE_I_AXI 0\r
#define XPAR_MICROBLAZE_I_LMB 1\r
+#define XPAR_MICROBLAZE_I_LMB_MON 0\r
#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0\r
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0\r
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2\r
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0\r
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3\r
-#define XPAR_MICROBLAZE_MMU_ZONES 2\r
+#define XPAR_MICROBLAZE_MMU_ZONES 16\r
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32\r
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0\r
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1\r
-#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 0\r
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32\r
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5\r
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32\r
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1\r
-#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1\r
+#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 0\r
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 8\r
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 2\r
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 2\r
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2\r
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1\r
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1\r
-#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1\r
+#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0\r
#define XPAR_MICROBLAZE_OPTIMIZATION 0\r
#define XPAR_MICROBLAZE_PC_WIDTH 32\r
#define XPAR_MICROBLAZE_PVR 0\r
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32\r
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC\r
#define XPAR_MICROBLAZE_SCO 0\r
-#define XPAR_MICROBLAZE_TRACE 1\r
-#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1\r
+#define XPAR_MICROBLAZE_TRACE 0\r
+#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0\r
#define XPAR_MICROBLAZE_USE_BARREL 1\r
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 1\r
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0\r
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0\r
#define XPAR_MICROBLAZE_USE_EXT_BRK 0\r
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0\r
-#define XPAR_MICROBLAZE_USE_FPU 2\r
-#define XPAR_MICROBLAZE_USE_HW_MUL 2\r
+#define XPAR_MICROBLAZE_USE_FPU 0\r
+#define XPAR_MICROBLAZE_USE_HW_MUL 0\r
#define XPAR_MICROBLAZE_USE_ICACHE 1\r
-#define XPAR_MICROBLAZE_USE_INTERRUPT 1\r
+#define XPAR_MICROBLAZE_USE_INTERRUPT 0\r
#define XPAR_MICROBLAZE_USE_MMU 0\r
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1\r
+#define XPAR_MICROBLAZE_USE_NON_SECURE 0\r
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1\r
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1\r
-#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1\r
-#define XPAR_MICROBLAZE_COMPONENT_NAME base_microblaze_design_microblaze_0_0\r
+#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0\r
+#define XPAR_MICROBLAZE_COMPONENT_NAME mb_subsystem_microblaze_0_0\r
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR\r
#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze\r
-#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 2\r
-#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1\r
+#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 0\r
+#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 0\r
\r
/******************************************************************/\r
\r
+#define STDIN_BASEADDRESS 0x40600000\r
+#define STDOUT_BASEADDRESS 0x40600000\r
\r
/******************************************************************/\r
\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000\r
-#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF\r
+#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF \r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF \r
\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000\r
-#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0003FFFF\r
+#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFF\r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFF \r
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF \r
\r
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1\r
#define XPAR_BRAM_0_WRITE_ACCESS 2\r
#define XPAR_BRAM_0_BASEADDR 0x00000000\r
-#define XPAR_BRAM_0_HIGHADDR 0x0003FFFF\r
+#define XPAR_BRAM_0_HIGHADDR 0x0000FFFF\r
\r
/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */\r
#define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID\r
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1\r
#define XPAR_BRAM_1_WRITE_ACCESS 2\r
#define XPAR_BRAM_1_BASEADDR 0x00000000\r
-#define XPAR_BRAM_1_HIGHADDR 0x0003FFFF\r
+#define XPAR_BRAM_1_HIGHADDR 0x0000FFFF\r
\r
\r
/******************************************************************/\r
#define XPAR_GPIO_0_IS_DUAL 0\r
\r
\r
-/******************************************************************/\r
-\r
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3\r
-#define XPAR_XINTC_HAS_IPR 1\r
-#define XPAR_XINTC_HAS_SIE 1\r
-#define XPAR_XINTC_HAS_CIE 1\r
-#define XPAR_XINTC_HAS_IVR 1\r
-/* Definitions for driver INTC */\r
-#define XPAR_XINTC_NUM_INSTANCES 1\r
-\r
-/* Definitions for peripheral AXI_INTC_0 */\r
-#define XPAR_AXI_INTC_0_DEVICE_ID 0\r
-#define XPAR_AXI_INTC_0_BASEADDR 0x41200000\r
-#define XPAR_AXI_INTC_0_HIGHADDR 0x4120FFFF\r
-#define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFFFE\r
-#define XPAR_AXI_INTC_0_HAS_FAST 0\r
-#define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x00000010\r
-#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 3\r
-\r
-\r
-/******************************************************************/\r
-\r
-#define XPAR_INTC_SINGLE_BASEADDR 0x41200000\r
-#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF\r
-#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID\r
-#define XPAR_AXI_INTC_0_TYPE 0\r
-#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001\r
-#define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0\r
-#define XPAR_AXI_UARTLITE_0_INTERRUPT_MASK 0X000002\r
-#define XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR 1\r
-#define XPAR_AXI_ETHERNETLITE_0_IP2INTC_IRPT_MASK 0X000004\r
-#define XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR 2\r
-\r
-/******************************************************************/\r
-\r
-/* Canonical definitions for peripheral AXI_INTC_0 */\r
-#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID\r
-#define XPAR_INTC_0_BASEADDR 0x41200000\r
-#define XPAR_INTC_0_HIGHADDR 0x4120FFFF\r
-#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFE\r
-#define XPAR_INTC_0_HAS_FAST 0\r
-#define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010\r
-#define XPAR_INTC_0_NUM_INTR_INPUTS 3\r
-#define XPAR_INTC_0_INTC_TYPE 0\r
-\r
-#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR\r
-#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR\r
-#define XPAR_INTC_0_EMACLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR\r
-\r
/******************************************************************/\r
\r
/* Definitions for driver MIG_7SERIES */\r
\r
/* Definitions for peripheral MIG_7SERIES_0 */\r
#define XPAR_MIG_7SERIES_0_BASEADDR 0x80000000\r
-#define XPAR_MIG_7SERIES_0_HIGHADDR 0xBFFFFFFF\r
+#define XPAR_MIG_7SERIES_0_HIGHADDR 0x9FFFFFFF\r
\r
\r
/******************************************************************/\r
#define XPAR_MIG7SERIES_0_DDR_BANK_WIDTH 3\r
#define XPAR_MIG7SERIES_0_DDR_DQ_WIDTH 64\r
#define XPAR_MIG7SERIES_0_BASEADDR 0x80000000\r
-#define XPAR_MIG7SERIES_0_HIGHADDR 0xBFFFFFFF\r
-\r
-\r
-/******************************************************************/\r
-\r
-/* Definitions for driver TMRCTR */\r
-#define XPAR_XTMRCTR_NUM_INSTANCES 1\r
-\r
-/* Definitions for peripheral AXI_TIMER_0 */\r
-#define XPAR_AXI_TIMER_0_DEVICE_ID 0\r
-#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000\r
-#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFF\r
-#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000\r
-\r
-\r
-/******************************************************************/\r
+#define XPAR_MIG7SERIES_0_HIGHADDR 0x9FFFFFFF\r
\r
-/* Canonical definitions for peripheral AXI_TIMER_0 */\r
-#define XPAR_TMRCTR_0_DEVICE_ID 0\r
-#define XPAR_TMRCTR_0_BASEADDR 0x41C00000\r
-#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFF\r
-#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ\r
\r
/******************************************************************/\r
\r
#define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000\r
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF\r
#define XPAR_AXI_UARTLITE_0_DEVICE_ID 0\r
-#define XPAR_AXI_UARTLITE_0_BAUDRATE 115200\r
+#define XPAR_AXI_UARTLITE_0_BAUDRATE 9600\r
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0\r
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0\r
#define XPAR_AXI_UARTLITE_0_DATA_BITS 8\r
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID\r
#define XPAR_UARTLITE_0_BASEADDR 0x40600000\r
#define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF\r
-#define XPAR_UARTLITE_0_BAUDRATE 115200\r
+#define XPAR_UARTLITE_0_BAUDRATE 9600\r
#define XPAR_UARTLITE_0_USE_PARITY 0\r
#define XPAR_UARTLITE_0_ODD_PARITY 0\r
#define XPAR_UARTLITE_0_DATA_BITS 8\r
+++ /dev/null
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-
-LIBSOURCES=*.c
-OUTS = *.o
-
-
-libs:
- echo "Compiling bram"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
- make clean
-
-include:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OUTS}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/**
-* @file xbram.c
-*
-* The implementation of the XBram driver's basic functionality.
-* See xbram.h for more information about the driver.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sa 05/11/10 First release
-* 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and
-* UncorrectableFailingDataRegs in
-* XBram_CfgInitialize API.
-*</pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xbram.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Initialize the XBram instance provided by the caller based on the given
-* configuration data.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XBram instance.
-* The memory the pointer references must be pre-allocated by
-* the caller. Further calls to manipulate the driver through
-* the XBram API must be made with this pointer.
-* @param Config is a reference to a structure containing information
-* about a specific BRAM device. This function
-* initializes an InstancePtr object for a specific device
-* specified by the contents of Config. This function can
-* initialize multiple instance objects with the use of multiple
-* calls giving different Config information on each call.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the
-* address mapping from EffectiveAddr to the device physical base
-* address unchanged once this function is invoked. Unexpected
-* errors may occur if the address mapping changes after this
-* function is called. If address translation is not used, use
-* Config->BaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS Initialization was successful.
-*
-* @note None.
-*
-*****************************************************************************/
-int XBram_CfgInitialize(XBram *InstancePtr,
- XBram_Config *Config,
- u32 EffectiveAddr)
-{
- /*
- * Assert arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Set some default values.
- */
- InstancePtr->Config.CtrlBaseAddress = EffectiveAddr;
- InstancePtr->Config.MemBaseAddress = Config->MemBaseAddress;
- InstancePtr->Config.MemHighAddress = Config->MemHighAddress;
- InstancePtr->Config.DataWidth = Config->DataWidth;
- InstancePtr->Config.EccPresent = Config->EccPresent;
- InstancePtr->Config.FaultInjectionPresent =
- Config->FaultInjectionPresent;
- InstancePtr->Config.CorrectableFailingRegisters =
- Config->CorrectableFailingRegisters;
- InstancePtr->Config.CorrectableFailingDataRegs =
- Config->CorrectableFailingDataRegs;
- InstancePtr->Config.UncorrectableFailingRegisters =
- Config->UncorrectableFailingRegisters;
- InstancePtr->Config.UncorrectableFailingDataRegs =
- Config->UncorrectableFailingDataRegs;
- InstancePtr->Config.EccStatusInterruptPresent =
- Config->EccStatusInterruptPresent;
- InstancePtr->Config.CorrectableCounterBits =
- Config->CorrectableCounterBits;
- InstancePtr->Config.WriteAccess = Config->WriteAccess;
-
- /*
- * Indicate the instance is now ready to use, initialized without error
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- return (XST_SUCCESS);
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xbram.h
-*
-* If ECC is not enabled, this driver exists only to allow the tools to
-* create a memory test application and to populate xparameters.h with memory
-* range constants. In this case there is no source code.
-*
-* If ECC is enabled, this file contains the software API definition of the
-* Xilinx BRAM Interface Controller (XBram) device driver.
-*
-* The Xilinx BRAM controller is a soft IP core designed for Xilinx
-* FPGAs and contains the following general features:
-* - LMB v2.0 bus interfaces with byte enable support
-* - Used in conjunction with bram_block peripheral to provide fast BRAM
-* memory solution for MicroBlaze ILMB and DLMB ports
-* - Supports byte, half-word, and word transfers
-* - Supports optional BRAM error correction and detection.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XBram_Config structure is used by the driver to configure
-* itself. This configuration structure is typically created by the tool-chain
-* based on HW build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized as
-* follows:
-*
-* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
-* Uses a configuration structure provided by the caller. If running in a
-* system with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the BRAM registers. With less
-* than 32 bits, the unused bits from registers are read as zero and written as
-* don't cares.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 3.00a sa 05/11/10 Added ECC support
-* 3.01a sa 01/13/12 Changed Selftest API from
-* XBram_SelfTest(XBram *InstancePtr) to
-* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
-* fixed a problem with interrupt generation for CR 639274
-* Modified Selftest example to return XST_SUCCESS when
-* ECC is not enabled and return XST_FAILURE when ECC is
-* enabled and Control Base Address is zero (CR 636581)
-* Modified Selftest to use correct CorrectableCounterBits
-* for CR 635655
-* Updated to check CorrectableFailingDataRegs in the case
-* of LMB BRAM.
-* Added CorrectableFailingDataRegs and
-* UncorrectableFailingDataRegs to the config structure to
-* distinguish between AXI BRAM and LMB BRAM.
-* These registers are not present in the current version of
-* the AXI BRAM Controller.
-* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
-* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
-* to support both xps and vivado designs.
-* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
-* when ecc is disabled cr:705002.
-* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
-* flush the Cache after writing to BRAM in InjectErrors
-* API(CR #719011)
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* </pre>
-*****************************************************************************/
-#ifndef XBRAM_H /* prevent circular inclusions */
-#define XBRAM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xbram_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 DataWidth; /**< BRAM data width */
- int EccPresent; /**< Is ECC supported in H/W */
- int FaultInjectionPresent; /**< Is Fault Injection
- * supported in H/W */
- int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
- * supported in H/W */
- int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
- * Registers supported in H/W */
- int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
- * Registers supported in H/W */
- int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
- * Registers supported in H/W */
- int EccStatusInterruptPresent; /**< Are ECC status and interrupts
- * supported in H/W */
- int CorrectableCounterBits; /**< Number of bits in the
- * Correctable Error Counter */
- int EccOnOffRegister; /**< Is ECC on/off register supported
- * in h/w */
- int EccOnOffResetValue; /**< Reset value of the ECC on/off
- * register in h/w */
- int WriteAccess; /**< Is write access enabled in
- * h/w */
- u32 MemBaseAddress; /**< Device memory base address */
- u32 MemHighAddress; /**< Device memory high address */
- u32 CtrlBaseAddress; /**< Device register base address.*/
- u32 CtrlHighAddress; /**< Device register base address.*/
-} XBram_Config;
-
-/**
- * The XBram driver instance data. The user is required to
- * allocate a variable of this type for every BRAM device in the
- * system. A pointer to a variable of this type is then passed to the driver
- * API functions.
- */
-typedef struct {
- XBram_Config Config; /* BRAM config structure */
- u32 IsReady; /* Device is initialized and ready */
-} XBram;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Functions in xbram_sinit.c
- */
-XBram_Config *XBram_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xbram.c
- */
-int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
- u32 EffectiveAddr);
-
-/*
- * Functions implemented in xbram_selftest.c
- */
-int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
-
-/*
- * Functions implemented in xbram_intr.c
- */
-void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
-void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
-void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
-u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
-u32 XBram_InterruptGetStatus(XBram *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Driver configuration\r
-*\r
-*******************************************************************/\r
-\r
-#include "xparameters.h"\r
-#include "xbram.h"\r
-\r
-/*\r
-* The configuration table for devices\r
-*/\r
-\r
-XBram_Config XBram_ConfigTable[] =\r
-{\r
- {\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR\r
- },\r
- {\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,\r
- XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR\r
- }\r
-};\r
-\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbram_hw.h
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sa 24/11/10 First release
-* </pre>
-*
-******************************************************************************/
-#ifndef XBRAM_HW_H /* prevent circular inclusions */
-#define XBRAM_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-
-#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
-#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
-#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
-#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
-
-#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
- * data Register, 31-0 */
-#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
- * data Register, 63-32 */
-#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
- * data Register, 95-64 */
-#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
- * data Register, 127-96 */
-#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
- * data Register, 159-128 */
-#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
- * data Register, 191-160 */
-#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
- * data Register, 223-192 */
-#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
- * data Register, 255-224 */
-#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
- * data Register, 287-256 */
-#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
- * data Register, 319-288 */
-#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
- * data Register, 351-320 */
-#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
- * data Register, 383-352 */
-#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
- * data Register, 415-384 */
-#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
- * data Register, 447-416 */
-#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
- * data Register, 479-448 */
-#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
- * data Register, 511-480 */
-#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
- * data Register, 543-512 */
-#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
- * data Register, 575-544 */
-#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
- * data Register, 607-576 */
-#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
- * data Register, 639-608 */
-#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
- * data Register, 671-640 */
-#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
- * data Register, 703-672 */
-#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
- * data Register, 735-704 */
-#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
- * data Register, 767-736 */
-#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
- * data Register, 799-768 */
-#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
- * data Register, 831-800 */
-#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
- * data Register, 863-832 */
-#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
- * data Register, 895-864 */
-#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
- * data Register, 927-896 */
-#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
- * data Register, 959-928 */
-#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
- * data Register, 991-960 */
-#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
- * data Register, 1023-992 */
-
-#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
- * ECC Register, 31-0 */
-#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
- * ECC Register, 63-32 */
-#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
- * ECC Register, 95-64 */
-#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
- * ECC Register, 127-96 */
-#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
- * ECC Register, 159-128 */
-#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
- * ECC Register, 191-160 */
-#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
- * ECC Register, 223-192 */
-#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
- * ECC Register, 255-224 */
-
-#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
- * address Register 31-0 */
-#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
- * address Register 63-32 */
-
-#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
- * data Register, 31-0 */
-#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
- * data Register, 63-32 */
-#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
- * data Register, 95-64 */
-#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
- * data Register, 127-96 */
-#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
- * data Register, 159-128 */
-#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
- * data Register, 191-160 */
-#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
- * data Register, 223-192 */
-#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
- * data Register, 255-224 */
-#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
- * data Register, 287-256 */
-#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
- * data Register, 319-288 */
-#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
- * data Register, 351-320 */
-#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
- * data Register, 383-352 */
-#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
- * data Register, 415-384 */
-#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
- * data Register, 447-416 */
-#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
- * data Register, 479-448 */
-#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
- * data Register, 511-480 */
-#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
- * data Register, 543-512 */
-#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
- * data Register, 575-544 */
-#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
- * data Register, 607-576 */
-#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
- * data Register, 639-608 */
-#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
- * data Register, 671-640 */
-#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
- * data Register, 703-672 */
-#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
- * data Register, 735-704 */
-#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
- * data Register, 767-736 */
-#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
- * data Register, 799-768 */
-#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
- * data Register, 831-800 */
-#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
- * data Register, 863-832 */
-#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
- * data Register, 895-864 */
-#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
- * data Register, 927-896 */
-#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
- * data Register, 959-928 */
-#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
- * data Register, 991-960 */
-#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
- * data Register, 1023-992 */
-
-#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
- * ECC Register, 31-0 */
-#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
- * ECC Register, 63-32 */
-#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
- * ECC Register, 95-64 */
-#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
- * ECC Register, 127-96 */
-#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
- * ECC Register, 159-128 */
-#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
- * ECC Register, 191-160 */
-#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
- * ECC Register, 223-192 */
-#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
- * ECC Register, 255-224 */
-
-#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
- * address Register 31-0 */
-#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
- * address Register 63-32 */
-
-#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
- * 31-0 */
-#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
- * 63-32 */
-#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
- * 95-64 */
-#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
- * 127-96 */
-#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
- * 159-128 */
-#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
- * 191-160 */
-#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
- * 223-192 */
-#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
- * 255-224 */
-#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
- * 287-256 */
-#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
- * 319-288 */
-#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
- * 351-320 */
-#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
- * 383-352 */
-#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
- * 415-384 */
-#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
- * 447-416 */
-#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
- * 479-448 */
-#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
- * 511-480 */
-#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
- * 543-512 */
-#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
- * 575-544 */
-#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
- * 607-576 */
-#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
- * 639-608 */
-#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
- * 671-640 */
-#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
- * 703-672 */
-#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
- * 735-704 */
-#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
- * 767-736 */
-#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
- * 799-768 */
-#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
- * 831-800 */
-#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
- * 863-832 */
-#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
- * 895-864 */
-#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
- * 927-896 */
-#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
- * 959-928 */
-#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
- * 991-960 */
-#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
- * 1023-992 */
-
-#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
- * 31-0 */
-#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
- * 63-32 */
-#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
- * 95-64 */
-#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
- * 127-96 */
-#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
- * 159-128 */
-#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
- * 191-160 */
-#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
- * 223-192 */
-#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
- * 255-224 */
-
-
-/* @} */
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the ECC status register and ECC interrupt enable register.
- * @{
- */
-#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
-#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
-#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
-/*@}*/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XBram_In32 Xil_In32
-#define XBram_Out32 Xil_Out32
-
-#define XBram_In16 Xil_In16
-#define XBram_Out16 Xil_Out16
-
-#define XBram_In8 Xil_In8
-#define XBram_Out8 Xil_Out8
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a BRAM register. A 32 bit write is performed.
-*
-* @param BaseAddress is the base address of the BRAM device register.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
- XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a BRAM register. A 32 bit read is performed.
-*
-* @param BaseAddress is the base address of the BRAM device registers.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XBram_ReadReg(BaseAddress, RegOffset) \
- XBram_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xbram_intr.c
-*
-* Implements BRAM interrupt processing functions for the
-* XBram driver. See xbram.h for more information
-* about the driver.
-*
-* The functions in this file require the hardware device to be built with
-* interrupt capabilities. The functions will assert if called using hardware
-* that does not have interrupt capabilities.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sa 05/11/10 Initial release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xbram.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Enable interrupts. This function will assert if the hardware device has not
-* been built with interrupt capabilities.
-*
-* @param InstancePtr is the BRAM instance to operate on.
-* @param Mask is the mask to enable. Bit positions of 1 are enabled.
-* This mask is formed by OR'ing bits from XBRAM_IR*
-* bits which are contained in xbram_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
-
- /*
- * Read the interrupt enable register and only enable the specified
- * interrupts without disabling or enabling any others.
- */
- Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_EN_IRQ_OFFSET);
- XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_EN_IRQ_OFFSET,
- Register | Mask);
-}
-
-
-/****************************************************************************/
-/**
-* Disable interrupts. This function allows each specific interrupt to be
-* disabled. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the BRAM instance to operate on.
-* @param Mask is the mask to disable. Bits set to 1 are disabled. This
-* mask is formed by OR'ing bits from XBRAM_IR* bits
-* which are contained in xbram_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
-
- /*
- * Read the interrupt enable register and only disable the specified
- * interrupts without enabling or disabling any others.
- */
- Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_EN_IRQ_OFFSET);
- XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_EN_IRQ_OFFSET,
- Register & (~Mask));
-}
-
-/****************************************************************************/
-/**
-* Clear pending interrupts with the provided mask. This function should be
-* called after the software has serviced the interrupts that are pending.
-* This function will assert if the hardware device has not been built with
-* interrupt capabilities.
-*
-* @param InstancePtr is the BRAM instance to operate on.
-* @param Mask is the mask to clear pending interrupts for. Bit positions
-* of 1 are cleared. This mask is formed by OR'ing bits from
-* XBRAM_IR* bits which are contained in
-* xbram_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
-
- /*
- * Read the interrupt status register and only clear the interrupts
- * that are specified without affecting any others. Since the register
- * is a toggle on write, make sure any bits to be written are already
- * set.
- */
- Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_STATUS_OFFSET);
- XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_STATUS_OFFSET,
- Register & Mask);
-
-
-}
-
-
-/****************************************************************************/
-/**
-* Returns the interrupt enable mask. This function will assert if the
-* hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the BRAM instance to operate on.
-*
-* @return A mask of bits made from XBRAM_IR* bits which
-* are contained in xbram_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XBram_InterruptGetEnabled(XBram * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
-
- return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_EN_IRQ_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-* Returns the status of interrupt signals. Any bit in the mask set to 1
-* indicates that the channel associated with the bit has asserted an interrupt
-* condition. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the BRAM instance to operate on.
-*
-* @return A pointer to a mask of bits made from XBRAM_IR*
-* bits which are contained in xbram_hw.h.
-*
-* @note
-*
-* The interrupt status indicates the status of the device irregardless if
-* the interrupts from the devices have been enabled or not through
-* XBram_InterruptEnable().
-*
-*****************************************************************************/
-u32 XBram_InterruptGetStatus(XBram * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
-
- return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
- XBRAM_ECC_EN_IRQ_OFFSET);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xbram_selftest.c
-*
-* The implementation of the XBram driver's self test function. This SelfTest
-* is only applicable if ECC is enabled.
-* If ECC is not enabled then this function will return XST_SUCCESS.
-* See xbram.h for more information about the driver.
-* Temp change
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sa 11/24/10 First release
-* 3.01a sa 01/13/12 Changed Selftest API from
-* XBram_SelfTest(XBram *InstancePtr) to
-* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
-* fixed a problem with interrupt generation for CR 639274
-* Modified Selftest example to return XST_SUCCESS when
-* ECC is not enabled and return XST_FAILURE when ECC is
-* enabled and Control Base Address is zero (CR 636581)
-* Modified Selftest to use correct CorrectableCounterBits
-* for CR 635655
-* Updated to check CorrectableFailingDataRegs in the case
-* of LMB BRAM.
-* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
-* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in InjectErrors API to
-* flush the Cache after writing to BRAM (CR #719011)
-* </pre>
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xbram.h"
-#include "xil_cache.h"
-/************************** Constant Definitions ****************************/
-#define TOTAL_BITS 39
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-#define RD(reg) XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress, \
- XBRAM_ ## reg)
-#define WR(reg, data) XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress, \
- XBRAM_ ## reg, data)
-
-#define CHECK(reg, data, result) if (result!=XST_SUCCESS || RD(reg)!=data) \
- result = XST_FAILURE;
-
-/************************** Variable Definitions ****************************/
-static u32 PrngResult;
-
-/************************** Function Prototypes *****************************/
-static inline u32 PrngData(u32 *PrngResult);
-
-static inline u32 CalculateEcc(u32 Data);
-
-static void InjectErrors(XBram * InstancePtr, u32 Addr,
- int Index1, int Index2, int Width,
- u32 *ActualData, u32 *ActualEcc);
-
-
-/*****************************************************************************/
-/**
-* Generate a pseudo random number.
-*
-* @param The PrngResult is the previous random number in the pseudo
-* random sequence, also knwon as the seed. It is modified to
-* the calculated pseudo random number by the function.
-*
-* @return The generated pseudo random number
-*
-* @note None.
-*
-******************************************************************************/
-static inline u32 PrngData(u32 *PrngResult)
-{
- *PrngResult = *PrngResult * 0x77D15E25 + 0x3617C161;
- return *PrngResult;
-}
-
-
-/*****************************************************************************/
-/**
-* Calculate ECC from Data.
-*
-* @param The Data Value
-*
-* @return The calculated ECC
-*
-* @note None.
-*
-******************************************************************************/
-static inline u32 CalculateEcc(u32 Data)
-{
- unsigned char c[7], d[32];
- u32 Result = 0;
- int Index;
-
- for (Index = 0; Index < 32; Index++) {
- d[31 - Index] = Data & 1;
- Data = Data >> 1;
- }
-
- c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[11] ^
- d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^
- d[28] ^ d[30];
-
- c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10] ^ d[12] ^
- d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[27] ^
- d[28] ^ d[31];
-
- c[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[14] ^
- d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[29] ^
- d[30] ^ d[31];
-
- c[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[18] ^
- d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
-
- c[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^
- d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
-
- c[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
-
- c[6] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^
- d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
- d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
- d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^
- c[5] ^ c[4] ^ c[3] ^ c[2] ^ c[1] ^ c[0];
-
- for (Index = 0; Index < 7; Index++) {
- Result = Result << 1;
- Result |= c[Index] & 1;
- }
-
- return Result;
-}
-
-/*****************************************************************************/
-/**
-* Get the expected actual data read in case of uncorrectable errors.
-*
-* @param The injected data value including errors (if any)
-* @param The syndrome (calculated ecc ^ actual ecc read)
-*
-* @return The actual data value read
-*
-* @note None.
-*
-******************************************************************************/
-static inline u32 UncorrectableData(u32 Data, u8 Syndrome)
-{
- switch (Syndrome) {
- case 0x03: return Data ^ 0x00000034;
- case 0x05: return Data ^ 0x001a2000;
- case 0x09: return Data ^ 0x0d000000;
- case 0x0d: return Data ^ 0x00001a00;
-
- case 0x11: return Data ^ 0x60000000;
- case 0x13: return Data ^ 0x00000003;
- case 0x15: return Data ^ 0x00018000;
- case 0x19: return Data ^ 0x00c00000;
- case 0x1d: return Data ^ 0x00000180;
-
- case 0x21: return Data ^ 0x80000000;
- case 0x23: return Data ^ 0x00000008;
- case 0x25: return Data ^ 0x00040000;
- case 0x29: return Data ^ 0x02000000;
- case 0x2d: return Data ^ 0x00000400;
-
- case 0x31: return Data ^ 0x10000000;
- case 0x35: return Data ^ 0x00004000;
- case 0x39: return Data ^ 0x00200000;
- case 0x3d: return Data ^ 0x00000040;
- }
- return Data;
-}
-
-/*****************************************************************************/
-/**
-* Inject errors using the hardware fault injection functionality, and write
-* random data and read it back using the indicated location.
-*
-* @param InstancePtr is a pointer to the XBram instance to
-* be worked on.
-* @param The Addr is the indicated memory location to use
-* @param The Index1 is the bit location of the first injected error
-* @param The Index2 is the bit location of the second injected error
-* @param The Width is the data byte width
-* @param The ActualData is filled in with expected data for checking
-* @param The ActualEcc is filled in with expected ECC for checking
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void InjectErrors(XBram * InstancePtr, u32 Addr,
- int Index1, int Index2, int Width,
- u32 *ActualData, u32 *ActualEcc)
-{
- u32 InjectedData = 0;
- u32 InjectedEcc = 0;
- u32 RandomData = PrngData(&PrngResult);
-
- if (Index1 < 32) {
- InjectedData = 1 << Index1;
- } else {
- InjectedEcc = 1 << (Index1 - 32);
- }
-
- if (Index2 < 32) {
- InjectedData |= (1 << Index2);
- } else {
- InjectedEcc |= 1 << (Index2 - 32);
- }
-
- WR(FI_D_0_OFFSET, InjectedData);
- WR(FI_ECC_0_OFFSET, InjectedEcc);
-
- XBram_Out32(Addr, RandomData);
- Xil_DCacheFlushRange(Addr, 4);
- switch (Width) {
- case 1: /* Byte - Write to do Read-Modify-Write */
- XBram_Out8(Addr, PrngData(&PrngResult) & 0xFF);
- break;
- case 2: /* Halfword - Write to do Read-Modify-Write */
- XBram_Out16(Addr, PrngData(&PrngResult) & 0xFFFF);
- break;
- case 4: /* Word - Read */
- (void) XBram_In32(Addr);
- break;
- }
- *ActualData = InjectedData ^ RandomData;
- *ActualEcc = InjectedEcc ^ CalculateEcc(RandomData);
-}
-
-
-/*****************************************************************************/
-/**
-* Run a self-test on the driver/device. Unless fault injection is implemented
-* in hardware, this function only does a minimal test in which available
-* registers (if any) are written and read.
-*
-* With fault injection, all possible single-bit and double-bit errors are
-* injected, and checked to the extent possible, given the implemented hardware.
-*
-* @param InstancePtr is a pointer to the XBram instance.
-* @param IntMask is the interrupt mask to use. When testing
-* with interrupts, this should be set to allow interrupt
-* generation, otherwise it should be 0.
-*
-* @return
-* - XST_SUCCESS if fault injection/detection is working properly OR
-* if ECC is Not Enabled in the HW.
-* - XST_FAILURE if the injected fault is not correctly detected or
-* the Control Base Address is Zero when ECC is enabled.
-* .
-*
-* If the BRAM device is not present in the
-* hardware a bus error could be generated. Other indicators of a
-* bus error, such as registers in bridges or buses, may be
-* necessary to determine if this function caused a bus error.
-*
-* @note None.
-*
-******************************************************************************/
-int XBram_SelfTest(XBram *InstancePtr, u8 IntMask)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
-
- if (InstancePtr->Config.EccPresent == 0) {
- return (XST_SUCCESS);
- }
-
- if (InstancePtr->Config.CtrlBaseAddress == 0) {
- return (XST_SUCCESS);
- }
-
- /*
- * Only 32-bit data width is supported as of yet. 64-bit and 128-bit
- * widths will be supported in future.
- */
- if (InstancePtr->Config.DataWidth != 32)
- return (XST_SUCCESS);
-
- /*
- * Read from the implemented readable registers in the hardware device.
- */
- if (InstancePtr->Config.CorrectableFailingRegisters) {
- (void) RD(CE_FFA_0_OFFSET);
- }
- if (InstancePtr->Config.CorrectableFailingDataRegs) {
- (void) RD(CE_FFD_0_OFFSET);
- (void) RD(CE_FFE_0_OFFSET);
- }
- if (InstancePtr->Config.UncorrectableFailingRegisters) {
- (void) RD(UE_FFA_0_OFFSET);
- }
- if (InstancePtr->Config.UncorrectableFailingDataRegs) {
- (void) RD(UE_FFD_0_OFFSET);
- (void) RD(UE_FFE_0_OFFSET);
- }
-
- /*
- * Write and read the implemented read/write registers in the hardware
- * device.
- */
- if (InstancePtr->Config.EccStatusInterruptPresent) {
- WR(ECC_EN_IRQ_OFFSET, 0);
- if (RD(ECC_EN_IRQ_OFFSET) != 0) {
- return (XST_FAILURE);
- }
- }
-
- if (InstancePtr->Config.CorrectableCounterBits > 0) {
- u32 Value;
-
- /* Calculate counter max value */
- if (InstancePtr->Config.CorrectableCounterBits == 32) {
- Value = 0xFFFFFFFF;
- } else {
- Value = (1 <<
- InstancePtr->Config.CorrectableCounterBits) - 1;
- }
-
- WR(CE_CNT_OFFSET, Value);
- if (RD(CE_CNT_OFFSET) != Value) {
- return (XST_FAILURE);
- }
-
- WR(CE_CNT_OFFSET, 0);
- if (RD(CE_CNT_OFFSET) != 0) {
- return (XST_FAILURE);
- }
- }
-
- /*
- * If fault injection is implemented, inject all possible single-bit
- * and double-bit errors, and check all observable effects.
- */
- if (InstancePtr->Config.FaultInjectionPresent &&
- InstancePtr->Config.WriteAccess != 0) {
-
- const u32 Addr[2] = {InstancePtr->Config.MemBaseAddress &
- 0xfffffffc,
- InstancePtr->Config.MemHighAddress &
- 0xfffffffc};
- u32 SavedWords[2];
- u32 ActualData;
- u32 ActualEcc;
- u32 CounterValue = 0;
- u32 CounterMax;
- int WordIndex = 0;
- int Result = XST_SUCCESS;
- int Index1;
- int Index2;
- int Width;
-
- PrngResult = 42; /* Random seed */
-
- /* Save two words in BRAM used for test */
- SavedWords[0] = XBram_In32(Addr[0]);
- SavedWords[1] = XBram_In32(Addr[1]);
-
- for (Width = 1; Width <= 4; Width <<= 1) {
- /* Calculate counter max value */
- if (InstancePtr->Config.CorrectableCounterBits == 32) {
- CounterMax = 0xFFFFFFFF;
- } else {
- CounterMax =(1 <<
- InstancePtr->Config.CorrectableCounterBits) - 1;
- }
-
- /* Inject and check all single bit errors */
- for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
- /* Save counter value */
- if (InstancePtr->Config.CorrectableCounterBits > 0) {
- CounterValue = RD(CE_CNT_OFFSET);
- }
-
- /* Inject single bit error */
- InjectErrors(InstancePtr, Addr[WordIndex], Index1,
- Index1, Width, &ActualData, &ActualEcc);
-
- /* Check that CE is set */
- if (InstancePtr->Config.EccStatusInterruptPresent) {
- CHECK(ECC_STATUS_OFFSET,
- XBRAM_IR_CE_MASK, Result);
- }
-
- /* Check that address, data, ECC are correct */
- if (InstancePtr->Config.CorrectableFailingRegisters) {
- CHECK(CE_FFA_0_OFFSET, Addr[WordIndex], Result);
- }
- /* Checks are only for LMB BRAM */
- if (InstancePtr->Config.CorrectableFailingDataRegs) {
- CHECK(CE_FFD_0_OFFSET, ActualData, Result);
- CHECK(CE_FFE_0_OFFSET, ActualEcc, Result);
- }
-
- /* Check that counter has incremented */
- if (InstancePtr->Config.CorrectableCounterBits > 0 &&
- CounterValue < CounterMax) {
- CHECK(CE_CNT_OFFSET,
- CounterValue + 1, Result);
- }
-
- /* Restore correct data in the used word */
- XBram_Out32(Addr[WordIndex], SavedWords[WordIndex]);
-
- /* Allow interrupts to occur */
- /* Clear status register */
- if (InstancePtr->Config.EccStatusInterruptPresent) {
- WR(ECC_EN_IRQ_OFFSET, IntMask);
- WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
- WR(ECC_EN_IRQ_OFFSET, 0);
- }
-
- /* Switch to the other word */
- WordIndex = WordIndex ^ 1;
-
- if (Result != XST_SUCCESS) break;
-
- }
-
- if (Result != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
- for (Index2 = 0; Index2 < TOTAL_BITS; Index2++) {
- if (Index1 != Index2) {
- /* Inject double bit error */
- InjectErrors(InstancePtr,
- Addr[WordIndex],
- Index1, Index2, Width,
- &ActualData,
- &ActualEcc);
-
- /* Check that UE is set */
- if (InstancePtr->Config.
- EccStatusInterruptPresent) {
- CHECK(ECC_STATUS_OFFSET,
- XBRAM_IR_UE_MASK,
- Result);
- }
-
- /* Check that address, data, ECC are correct */
- if (InstancePtr->Config.
- UncorrectableFailingRegisters) {
- CHECK(UE_FFA_0_OFFSET, Addr[WordIndex],
- Result);
- CHECK(UE_FFD_0_OFFSET,
- ActualData, Result);
- CHECK(UE_FFE_0_OFFSET, ActualEcc,
- Result);
- }
-
- /* Restore correct data in the used word */
- XBram_Out32(Addr[WordIndex],
- SavedWords[WordIndex]);
-
- /* Allow interrupts to occur */
- /* Clear status register */
- if (InstancePtr->Config.
- EccStatusInterruptPresent) {
- WR(ECC_EN_IRQ_OFFSET, IntMask);
- WR(ECC_STATUS_OFFSET,
- XBRAM_IR_ALL_MASK);
- WR(ECC_EN_IRQ_OFFSET, 0);
- }
-
- /* Switch to the other word */
- WordIndex = WordIndex ^ 1;
- }
- if (Result != XST_SUCCESS) break;
- }
- if (Result != XST_SUCCESS) break;
- }
-
- /* Check saturation of correctable error counter */
- if (InstancePtr->Config.CorrectableCounterBits > 0 &&
- Result == XST_SUCCESS) {
-
- WR(CE_CNT_OFFSET, CounterMax);
-
- InjectErrors(InstancePtr, Addr[WordIndex], 0, 0,
- 4, &ActualData, &ActualEcc);
-
- CHECK(CE_CNT_OFFSET, CounterMax, Result);
- }
-
- /* Restore the two words used for test */
- XBram_Out32(Addr[0], SavedWords[0]);
- XBram_Out32(Addr[1], SavedWords[1]);
-
- /* Clear the Status Register. */
- if (InstancePtr->Config.EccStatusInterruptPresent) {
- WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
- }
-
- /* Set Correctable Counter to zero */
- if (InstancePtr->Config.CorrectableCounterBits > 0) {
- WR(CE_CNT_OFFSET, 0);
- }
-
- if (Result != XST_SUCCESS) break;
-
- } /* Width loop */
-
- return (Result);
- }
-
- return (XST_SUCCESS);
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xbram_sinit.c
-*
-* The implementation of the XBram driver's static initialzation
-* functionality.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.01a jvb 10/13/05 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xbram.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-extern XBram_Config XBram_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* ConfigTable contains the configuration info for each device in the system.
-*
-* @param DeviceId is the device identifier to lookup.
-*
-* @return
-* - A pointer of data type XBram_Config which
-* points to the device configuration if DeviceID is found.
-* - NULL if DeviceID is not found.
-*
-* @note None.
-*
-******************************************************************************/
-XBram_Config *XBram_LookupConfig(u16 DeviceId)
-{
- XBram_Config *CfgPtr = NULL;
-
- int Index;
-
- for (Index = 0; Index < XPAR_XBRAM_NUM_INSTANCES; Index++) {
- if (XBram_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XBram_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
--- /dev/null
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+
+LIBSOURCES=*.c
+OUTS = *.o
+
+
+libs:
+ echo "Compiling bram"
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+ make clean
+
+include:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OUTS}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/**
+* @file xbram.c
+* @addtogroup bram_v4_0
+* @{
+*
+* The implementation of the XBram driver's basic functionality.
+* See xbram.h for more information about the driver.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 05/11/10 First release
+* 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and
+* UncorrectableFailingDataRegs in
+* XBram_CfgInitialize API.
+* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XBram_CfgInitialize API.
+*</pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xbram.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Initialize the XBram instance provided by the caller based on the given
+* configuration data.
+*
+* Nothing is done except to initialize the InstancePtr.
+*
+* @param InstancePtr is a pointer to an XBram instance.
+* The memory the pointer references must be pre-allocated by
+* the caller. Further calls to manipulate the driver through
+* the XBram API must be made with this pointer.
+* @param Config is a reference to a structure containing information
+* about a specific BRAM device. This function
+* initializes an InstancePtr object for a specific device
+* specified by the contents of Config. This function can
+* initialize multiple instance objects with the use of multiple
+* calls giving different Config information on each call.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the
+* address mapping from EffectiveAddr to the device physical base
+* address unchanged once this function is invoked. Unexpected
+* errors may occur if the address mapping changes after this
+* function is called. If address translation is not used, use
+* Config->BaseAddress for this parameters, passing the physical
+* address instead.
+*
+* @return
+* - XST_SUCCESS Initialization was successful.
+*
+* @note None.
+*
+*****************************************************************************/
+int XBram_CfgInitialize(XBram *InstancePtr,
+ XBram_Config *Config,
+ UINTPTR EffectiveAddr)
+{
+ /*
+ * Assert arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Set some default values.
+ */
+ InstancePtr->Config.CtrlBaseAddress = EffectiveAddr;
+ InstancePtr->Config.MemBaseAddress = Config->MemBaseAddress;
+ InstancePtr->Config.MemHighAddress = Config->MemHighAddress;
+ InstancePtr->Config.DataWidth = Config->DataWidth;
+ InstancePtr->Config.EccPresent = Config->EccPresent;
+ InstancePtr->Config.FaultInjectionPresent =
+ Config->FaultInjectionPresent;
+ InstancePtr->Config.CorrectableFailingRegisters =
+ Config->CorrectableFailingRegisters;
+ InstancePtr->Config.CorrectableFailingDataRegs =
+ Config->CorrectableFailingDataRegs;
+ InstancePtr->Config.UncorrectableFailingRegisters =
+ Config->UncorrectableFailingRegisters;
+ InstancePtr->Config.UncorrectableFailingDataRegs =
+ Config->UncorrectableFailingDataRegs;
+ InstancePtr->Config.EccStatusInterruptPresent =
+ Config->EccStatusInterruptPresent;
+ InstancePtr->Config.CorrectableCounterBits =
+ Config->CorrectableCounterBits;
+ InstancePtr->Config.WriteAccess = Config->WriteAccess;
+
+ /*
+ * Indicate the instance is now ready to use, initialized without error
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ return (XST_SUCCESS);
+}
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xbram.h
+* @addtogroup bram_v4_0
+* @{
+* @details
+*
+* If ECC is not enabled, this driver exists only to allow the tools to
+* create a memory test application and to populate xparameters.h with memory
+* range constants. In this case there is no source code.
+*
+* If ECC is enabled, this file contains the software API definition of the
+* Xilinx BRAM Interface Controller (XBram) device driver.
+*
+* The Xilinx BRAM controller is a soft IP core designed for Xilinx
+* FPGAs and contains the following general features:
+* - LMB v2.0 bus interfaces with byte enable support
+* - Used in conjunction with bram_block peripheral to provide fast BRAM
+* memory solution for MicroBlaze ILMB and DLMB ports
+* - Supports byte, half-word, and word transfers
+* - Supports optional BRAM error correction and detection.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XBram_Config structure is used by the driver to configure
+* itself. This configuration structure is typically created by the tool-chain
+* based on HW build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized as
+* follows:
+*
+* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
+* Uses a configuration structure provided by the caller. If running in a
+* system with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the BRAM registers. With less
+* than 32 bits, the unused bits from registers are read as zero and written as
+* don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 3.00a sa 05/11/10 Added ECC support
+* 3.01a sa 01/13/12 Changed Selftest API from
+* XBram_SelfTest(XBram *InstancePtr) to
+* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
+* fixed a problem with interrupt generation for CR 639274
+* Modified Selftest example to return XST_SUCCESS when
+* ECC is not enabled and return XST_FAILURE when ECC is
+* enabled and Control Base Address is zero (CR 636581)
+* Modified Selftest to use correct CorrectableCounterBits
+* for CR 635655
+* Updated to check CorrectableFailingDataRegs in the case
+* of LMB BRAM.
+* Added CorrectableFailingDataRegs and
+* UncorrectableFailingDataRegs to the config structure to
+* distinguish between AXI BRAM and LMB BRAM.
+* These registers are not present in the current version of
+* the AXI BRAM Controller.
+* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
+* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
+* to support both xps and vivado designs.
+* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
+* when ecc is disabled cr:705002.
+* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
+* flush the Cache after writing to BRAM in InjectErrors
+* API(CR #719011)
+* 4.0 adk 19/12/13 Updated as per the New Tcl API's
+* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XBram_CfgInitialize API.
+* </pre>
+*****************************************************************************/
+#ifndef XBRAM_H /* prevent circular inclusions */
+#define XBRAM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xbram_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 DataWidth; /**< BRAM data width */
+ int EccPresent; /**< Is ECC supported in H/W */
+ int FaultInjectionPresent; /**< Is Fault Injection
+ * supported in H/W */
+ int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
+ * supported in H/W */
+ int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
+ * Registers supported in H/W */
+ int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
+ * Registers supported in H/W */
+ int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
+ * Registers supported in H/W */
+ int EccStatusInterruptPresent; /**< Are ECC status and interrupts
+ * supported in H/W */
+ int CorrectableCounterBits; /**< Number of bits in the
+ * Correctable Error Counter */
+ int EccOnOffRegister; /**< Is ECC on/off register supported
+ * in h/w */
+ int EccOnOffResetValue; /**< Reset value of the ECC on/off
+ * register in h/w */
+ int WriteAccess; /**< Is write access enabled in
+ * h/w */
+ u32 MemBaseAddress; /**< Device memory base address */
+ u32 MemHighAddress; /**< Device memory high address */
+ UINTPTR CtrlBaseAddress; /**< Device register base address.*/
+ UINTPTR CtrlHighAddress; /**< Device register base address.*/
+} XBram_Config;
+
+/**
+ * The XBram driver instance data. The user is required to
+ * allocate a variable of this type for every BRAM device in the
+ * system. A pointer to a variable of this type is then passed to the driver
+ * API functions.
+ */
+typedef struct {
+ XBram_Config Config; /* BRAM config structure */
+ u32 IsReady; /* Device is initialized and ready */
+} XBram;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Functions in xbram_sinit.c
+ */
+XBram_Config *XBram_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xbram.c
+ */
+int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
+ UINTPTR EffectiveAddr);
+
+/*
+ * Functions implemented in xbram_selftest.c
+ */
+int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
+
+/*
+ * Functions implemented in xbram_intr.c
+ */
+void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
+u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
+u32 XBram_InterruptGetStatus(XBram *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
--- /dev/null
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Driver configuration\r
+*\r
+*******************************************************************/\r
+\r
+#include "xparameters.h"\r
+#include "xbram.h"\r
+\r
+/*\r
+* The configuration table for devices\r
+*/\r
+\r
+XBram_Config XBram_ConfigTable[] =\r
+{\r
+ {\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR\r
+ },\r
+ {\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR,\r
+ XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR\r
+ }\r
+};\r
+\r
+\r
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbram_hw.h
+* @addtogroup bram_v4_0
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 24/11/10 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XBRAM_HW_H /* prevent circular inclusions */
+#define XBRAM_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+
+#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
+#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
+#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
+#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
+
+#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
+ * data Register, 31-0 */
+#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
+ * data Register, 63-32 */
+#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
+ * data Register, 95-64 */
+#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
+ * data Register, 127-96 */
+#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
+ * data Register, 159-128 */
+#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
+ * data Register, 191-160 */
+#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
+ * data Register, 223-192 */
+#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
+ * data Register, 255-224 */
+#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
+ * data Register, 287-256 */
+#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
+ * data Register, 319-288 */
+#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
+ * data Register, 351-320 */
+#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
+ * data Register, 383-352 */
+#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
+ * data Register, 415-384 */
+#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
+ * data Register, 447-416 */
+#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
+ * data Register, 479-448 */
+#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
+ * data Register, 511-480 */
+#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
+ * data Register, 543-512 */
+#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
+ * data Register, 575-544 */
+#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
+ * data Register, 607-576 */
+#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
+ * data Register, 639-608 */
+#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
+ * data Register, 671-640 */
+#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
+ * data Register, 703-672 */
+#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
+ * data Register, 735-704 */
+#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
+ * data Register, 767-736 */
+#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
+ * data Register, 799-768 */
+#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
+ * data Register, 831-800 */
+#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
+ * data Register, 863-832 */
+#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
+ * data Register, 895-864 */
+#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
+ * data Register, 927-896 */
+#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
+ * data Register, 959-928 */
+#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
+ * data Register, 991-960 */
+#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
+ * data Register, 1023-992 */
+
+#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
+ * ECC Register, 31-0 */
+#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
+ * ECC Register, 63-32 */
+#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
+ * ECC Register, 95-64 */
+#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
+ * ECC Register, 127-96 */
+#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
+ * ECC Register, 159-128 */
+#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
+ * ECC Register, 191-160 */
+#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
+ * ECC Register, 223-192 */
+#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
+ * ECC Register, 255-224 */
+
+#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
+ * address Register 31-0 */
+#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
+ * address Register 63-32 */
+
+#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
+ * data Register, 31-0 */
+#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
+ * data Register, 63-32 */
+#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
+ * data Register, 95-64 */
+#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
+ * data Register, 127-96 */
+#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
+ * data Register, 159-128 */
+#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
+ * data Register, 191-160 */
+#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
+ * data Register, 223-192 */
+#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
+ * data Register, 255-224 */
+#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
+ * data Register, 287-256 */
+#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
+ * data Register, 319-288 */
+#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
+ * data Register, 351-320 */
+#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
+ * data Register, 383-352 */
+#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
+ * data Register, 415-384 */
+#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
+ * data Register, 447-416 */
+#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
+ * data Register, 479-448 */
+#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
+ * data Register, 511-480 */
+#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
+ * data Register, 543-512 */
+#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
+ * data Register, 575-544 */
+#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
+ * data Register, 607-576 */
+#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
+ * data Register, 639-608 */
+#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
+ * data Register, 671-640 */
+#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
+ * data Register, 703-672 */
+#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
+ * data Register, 735-704 */
+#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
+ * data Register, 767-736 */
+#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
+ * data Register, 799-768 */
+#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
+ * data Register, 831-800 */
+#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
+ * data Register, 863-832 */
+#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
+ * data Register, 895-864 */
+#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
+ * data Register, 927-896 */
+#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
+ * data Register, 959-928 */
+#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
+ * data Register, 991-960 */
+#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
+ * data Register, 1023-992 */
+
+#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
+ * ECC Register, 31-0 */
+#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
+ * ECC Register, 63-32 */
+#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
+ * ECC Register, 95-64 */
+#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
+ * ECC Register, 127-96 */
+#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
+ * ECC Register, 159-128 */
+#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
+ * ECC Register, 191-160 */
+#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
+ * ECC Register, 223-192 */
+#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
+ * ECC Register, 255-224 */
+
+#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
+ * address Register 31-0 */
+#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
+ * address Register 63-32 */
+
+#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
+ * 31-0 */
+#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
+ * 63-32 */
+#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
+ * 95-64 */
+#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
+ * 127-96 */
+#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
+ * 159-128 */
+#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
+ * 191-160 */
+#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
+ * 223-192 */
+#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
+ * 255-224 */
+#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
+ * 287-256 */
+#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
+ * 319-288 */
+#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
+ * 351-320 */
+#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
+ * 383-352 */
+#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
+ * 415-384 */
+#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
+ * 447-416 */
+#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
+ * 479-448 */
+#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
+ * 511-480 */
+#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
+ * 543-512 */
+#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
+ * 575-544 */
+#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
+ * 607-576 */
+#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
+ * 639-608 */
+#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
+ * 671-640 */
+#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
+ * 703-672 */
+#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
+ * 735-704 */
+#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
+ * 767-736 */
+#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
+ * 799-768 */
+#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
+ * 831-800 */
+#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
+ * 863-832 */
+#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
+ * 895-864 */
+#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
+ * 927-896 */
+#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
+ * 959-928 */
+#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
+ * 991-960 */
+#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
+ * 1023-992 */
+
+#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
+ * 31-0 */
+#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
+ * 63-32 */
+#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
+ * 95-64 */
+#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
+ * 127-96 */
+#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
+ * 159-128 */
+#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
+ * 191-160 */
+#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
+ * 223-192 */
+#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
+ * 255-224 */
+
+
+/* @} */
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the ECC status register and ECC interrupt enable register.
+ * @{
+ */
+#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
+#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
+#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
+/*@}*/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XBram_In32 Xil_In32
+#define XBram_Out32 Xil_Out32
+
+#define XBram_In16 Xil_In16
+#define XBram_Out16 Xil_Out16
+
+#define XBram_In8 Xil_In8
+#define XBram_Out8 Xil_Out8
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a BRAM register. A 32 bit write is performed.
+*
+* @param BaseAddress is the base address of the BRAM device register.
+* @param RegOffset is the register offset from the base to write to.
+* @param Data is the data written to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
+ XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a BRAM register. A 32 bit read is performed.
+*
+* @param BaseAddress is the base address of the BRAM device registers.
+* @param RegOffset is the register offset from the base to read from.
+*
+* @return Data read from the register.
+*
+* @note C-style signature:
+* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XBram_ReadReg(BaseAddress, RegOffset) \
+ XBram_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xbram_intr.c
+* @addtogroup bram_v4_0
+* @{
+*
+* Implements BRAM interrupt processing functions for the
+* XBram driver. See xbram.h for more information
+* about the driver.
+*
+* The functions in this file require the hardware device to be built with
+* interrupt capabilities. The functions will assert if called using hardware
+* that does not have interrupt capabilities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 05/11/10 Initial release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xbram.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Enable interrupts. This function will assert if the hardware device has not
+* been built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+* @param Mask is the mask to enable. Bit positions of 1 are enabled.
+* This mask is formed by OR'ing bits from XBRAM_IR*
+* bits which are contained in xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ /*
+ * Read the interrupt enable register and only enable the specified
+ * interrupts without disabling or enabling any others.
+ */
+ Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+ XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET,
+ Register | Mask);
+}
+
+
+/****************************************************************************/
+/**
+* Disable interrupts. This function allows each specific interrupt to be
+* disabled. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+* @param Mask is the mask to disable. Bits set to 1 are disabled. This
+* mask is formed by OR'ing bits from XBRAM_IR* bits
+* which are contained in xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ /*
+ * Read the interrupt enable register and only disable the specified
+ * interrupts without enabling or disabling any others.
+ */
+ Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+ XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET,
+ Register & (~Mask));
+}
+
+/****************************************************************************/
+/**
+* Clear pending interrupts with the provided mask. This function should be
+* called after the software has serviced the interrupts that are pending.
+* This function will assert if the hardware device has not been built with
+* interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+* @param Mask is the mask to clear pending interrupts for. Bit positions
+* of 1 are cleared. This mask is formed by OR'ing bits from
+* XBRAM_IR* bits which are contained in
+* xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ /*
+ * Read the interrupt status register and only clear the interrupts
+ * that are specified without affecting any others. Since the register
+ * is a toggle on write, make sure any bits to be written are already
+ * set.
+ */
+ Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_STATUS_OFFSET);
+ XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_STATUS_OFFSET,
+ Register & Mask);
+
+
+}
+
+
+/****************************************************************************/
+/**
+* Returns the interrupt enable mask. This function will assert if the
+* hardware device has not been built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+*
+* @return A mask of bits made from XBRAM_IR* bits which
+* are contained in xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XBram_InterruptGetEnabled(XBram * InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+* Returns the status of interrupt signals. Any bit in the mask set to 1
+* indicates that the channel associated with the bit has asserted an interrupt
+* condition. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+*
+* @return A pointer to a mask of bits made from XBRAM_IR*
+* bits which are contained in xbram_hw.h.
+*
+* @note
+*
+* The interrupt status indicates the status of the device irregardless if
+* the interrupts from the devices have been enabled or not through
+* XBram_InterruptEnable().
+*
+*****************************************************************************/
+u32 XBram_InterruptGetStatus(XBram * InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xbram_selftest.c
+* @addtogroup bram_v4_0
+* @{
+*
+* The implementation of the XBram driver's self test function. This SelfTest
+* is only applicable if ECC is enabled.
+* If ECC is not enabled then this function will return XST_SUCCESS.
+* See xbram.h for more information about the driver.
+* Temp change
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 11/24/10 First release
+* 3.01a sa 01/13/12 Changed Selftest API from
+* XBram_SelfTest(XBram *InstancePtr) to
+* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
+* fixed a problem with interrupt generation for CR 639274
+* Modified Selftest example to return XST_SUCCESS when
+* ECC is not enabled and return XST_FAILURE when ECC is
+* enabled and Control Base Address is zero (CR 636581)
+* Modified Selftest to use correct CorrectableCounterBits
+* for CR 635655
+* Updated to check CorrectableFailingDataRegs in the case
+* of LMB BRAM.
+* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
+* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in InjectErrors API to
+* flush the Cache after writing to BRAM (CR #719011)
+* </pre>
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xbram.h"
+#include "xil_cache.h"
+/************************** Constant Definitions ****************************/
+#define TOTAL_BITS 39
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#define RD(reg) XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress, \
+ XBRAM_ ## reg)
+#define WR(reg, data) XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress, \
+ XBRAM_ ## reg, data)
+
+#define CHECK(reg, data, result) if (result!=XST_SUCCESS || RD(reg)!=data) \
+ result = XST_FAILURE;
+
+/************************** Variable Definitions ****************************/
+static u32 PrngResult;
+
+/************************** Function Prototypes *****************************/
+static inline u32 PrngData(u32 *PrngResult);
+
+static inline u32 CalculateEcc(u32 Data);
+
+static void InjectErrors(XBram * InstancePtr, u32 Addr,
+ int Index1, int Index2, int Width,
+ u32 *ActualData, u32 *ActualEcc);
+
+
+/*****************************************************************************/
+/**
+* Generate a pseudo random number.
+*
+* @param The PrngResult is the previous random number in the pseudo
+* random sequence, also knwon as the seed. It is modified to
+* the calculated pseudo random number by the function.
+*
+* @return The generated pseudo random number
+*
+* @note None.
+*
+******************************************************************************/
+static inline u32 PrngData(u32 *PrngResult)
+{
+ *PrngResult = *PrngResult * 0x77D15E25 + 0x3617C161;
+ return *PrngResult;
+}
+
+
+/*****************************************************************************/
+/**
+* Calculate ECC from Data.
+*
+* @param The Data Value
+*
+* @return The calculated ECC
+*
+* @note None.
+*
+******************************************************************************/
+static inline u32 CalculateEcc(u32 Data)
+{
+ unsigned char c[7], d[32];
+ u32 Result = 0;
+ int Index;
+
+ for (Index = 0; Index < 32; Index++) {
+ d[31 - Index] = Data & 1;
+ Data = Data >> 1;
+ }
+
+ c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[11] ^
+ d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^
+ d[28] ^ d[30];
+
+ c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10] ^ d[12] ^
+ d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[27] ^
+ d[28] ^ d[31];
+
+ c[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[14] ^
+ d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[29] ^
+ d[30] ^ d[31];
+
+ c[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[18] ^
+ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
+
+ c[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^
+ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
+
+ c[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
+
+ c[6] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^
+ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
+ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
+ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^
+ c[5] ^ c[4] ^ c[3] ^ c[2] ^ c[1] ^ c[0];
+
+ for (Index = 0; Index < 7; Index++) {
+ Result = Result << 1;
+ Result |= c[Index] & 1;
+ }
+
+ return Result;
+}
+
+/*****************************************************************************/
+/**
+* Get the expected actual data read in case of uncorrectable errors.
+*
+* @param The injected data value including errors (if any)
+* @param The syndrome (calculated ecc ^ actual ecc read)
+*
+* @return The actual data value read
+*
+* @note None.
+*
+******************************************************************************/
+static inline u32 UncorrectableData(u32 Data, u8 Syndrome)
+{
+ switch (Syndrome) {
+ case 0x03: return Data ^ 0x00000034;
+ case 0x05: return Data ^ 0x001a2000;
+ case 0x09: return Data ^ 0x0d000000;
+ case 0x0d: return Data ^ 0x00001a00;
+
+ case 0x11: return Data ^ 0x60000000;
+ case 0x13: return Data ^ 0x00000003;
+ case 0x15: return Data ^ 0x00018000;
+ case 0x19: return Data ^ 0x00c00000;
+ case 0x1d: return Data ^ 0x00000180;
+
+ case 0x21: return Data ^ 0x80000000;
+ case 0x23: return Data ^ 0x00000008;
+ case 0x25: return Data ^ 0x00040000;
+ case 0x29: return Data ^ 0x02000000;
+ case 0x2d: return Data ^ 0x00000400;
+
+ case 0x31: return Data ^ 0x10000000;
+ case 0x35: return Data ^ 0x00004000;
+ case 0x39: return Data ^ 0x00200000;
+ case 0x3d: return Data ^ 0x00000040;
+ }
+ return Data;
+}
+
+/*****************************************************************************/
+/**
+* Inject errors using the hardware fault injection functionality, and write
+* random data and read it back using the indicated location.
+*
+* @param InstancePtr is a pointer to the XBram instance to
+* be worked on.
+* @param The Addr is the indicated memory location to use
+* @param The Index1 is the bit location of the first injected error
+* @param The Index2 is the bit location of the second injected error
+* @param The Width is the data byte width
+* @param The ActualData is filled in with expected data for checking
+* @param The ActualEcc is filled in with expected ECC for checking
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void InjectErrors(XBram * InstancePtr, u32 Addr,
+ int Index1, int Index2, int Width,
+ u32 *ActualData, u32 *ActualEcc)
+{
+ u32 InjectedData = 0;
+ u32 InjectedEcc = 0;
+ u32 RandomData = PrngData(&PrngResult);
+
+ if (Index1 < 32) {
+ InjectedData = 1 << Index1;
+ } else {
+ InjectedEcc = 1 << (Index1 - 32);
+ }
+
+ if (Index2 < 32) {
+ InjectedData |= (1 << Index2);
+ } else {
+ InjectedEcc |= 1 << (Index2 - 32);
+ }
+
+ WR(FI_D_0_OFFSET, InjectedData);
+ WR(FI_ECC_0_OFFSET, InjectedEcc);
+
+ XBram_Out32(Addr, RandomData);
+ Xil_DCacheFlushRange(Addr, 4);
+ switch (Width) {
+ case 1: /* Byte - Write to do Read-Modify-Write */
+ XBram_Out8(Addr, PrngData(&PrngResult) & 0xFF);
+ break;
+ case 2: /* Halfword - Write to do Read-Modify-Write */
+ XBram_Out16(Addr, PrngData(&PrngResult) & 0xFFFF);
+ break;
+ case 4: /* Word - Read */
+ (void) XBram_In32(Addr);
+ break;
+ }
+ *ActualData = InjectedData ^ RandomData;
+ *ActualEcc = InjectedEcc ^ CalculateEcc(RandomData);
+}
+
+
+/*****************************************************************************/
+/**
+* Run a self-test on the driver/device. Unless fault injection is implemented
+* in hardware, this function only does a minimal test in which available
+* registers (if any) are written and read.
+*
+* With fault injection, all possible single-bit and double-bit errors are
+* injected, and checked to the extent possible, given the implemented hardware.
+*
+* @param InstancePtr is a pointer to the XBram instance.
+* @param IntMask is the interrupt mask to use. When testing
+* with interrupts, this should be set to allow interrupt
+* generation, otherwise it should be 0.
+*
+* @return
+* - XST_SUCCESS if fault injection/detection is working properly OR
+* if ECC is Not Enabled in the HW.
+* - XST_FAILURE if the injected fault is not correctly detected or
+* the Control Base Address is Zero when ECC is enabled.
+* .
+*
+* If the BRAM device is not present in the
+* hardware a bus error could be generated. Other indicators of a
+* bus error, such as registers in bridges or buses, may be
+* necessary to determine if this function caused a bus error.
+*
+* @note None.
+*
+******************************************************************************/
+int XBram_SelfTest(XBram *InstancePtr, u8 IntMask)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+
+ if (InstancePtr->Config.EccPresent == 0) {
+ return (XST_SUCCESS);
+ }
+
+ if (InstancePtr->Config.CtrlBaseAddress == 0) {
+ return (XST_SUCCESS);
+ }
+
+ /*
+ * Only 32-bit data width is supported as of yet. 64-bit and 128-bit
+ * widths will be supported in future.
+ */
+ if (InstancePtr->Config.DataWidth != 32)
+ return (XST_SUCCESS);
+
+ /*
+ * Read from the implemented readable registers in the hardware device.
+ */
+ if (InstancePtr->Config.CorrectableFailingRegisters) {
+ (void) RD(CE_FFA_0_OFFSET);
+ }
+ if (InstancePtr->Config.CorrectableFailingDataRegs) {
+ (void) RD(CE_FFD_0_OFFSET);
+ (void) RD(CE_FFE_0_OFFSET);
+ }
+ if (InstancePtr->Config.UncorrectableFailingRegisters) {
+ (void) RD(UE_FFA_0_OFFSET);
+ }
+ if (InstancePtr->Config.UncorrectableFailingDataRegs) {
+ (void) RD(UE_FFD_0_OFFSET);
+ (void) RD(UE_FFE_0_OFFSET);
+ }
+
+ /*
+ * Write and read the implemented read/write registers in the hardware
+ * device.
+ */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ WR(ECC_EN_IRQ_OFFSET, 0);
+ if (RD(ECC_EN_IRQ_OFFSET) != 0) {
+ return (XST_FAILURE);
+ }
+ }
+
+ if (InstancePtr->Config.CorrectableCounterBits > 0) {
+ u32 Value;
+
+ /* Calculate counter max value */
+ if (InstancePtr->Config.CorrectableCounterBits == 32) {
+ Value = 0xFFFFFFFF;
+ } else {
+ Value = (1 <<
+ InstancePtr->Config.CorrectableCounterBits) - 1;
+ }
+
+ WR(CE_CNT_OFFSET, Value);
+ if (RD(CE_CNT_OFFSET) != Value) {
+ return (XST_FAILURE);
+ }
+
+ WR(CE_CNT_OFFSET, 0);
+ if (RD(CE_CNT_OFFSET) != 0) {
+ return (XST_FAILURE);
+ }
+ }
+
+ /*
+ * If fault injection is implemented, inject all possible single-bit
+ * and double-bit errors, and check all observable effects.
+ */
+ if (InstancePtr->Config.FaultInjectionPresent &&
+ InstancePtr->Config.WriteAccess != 0) {
+
+ const u32 Addr[2] = {InstancePtr->Config.MemBaseAddress &
+ 0xfffffffc,
+ InstancePtr->Config.MemHighAddress &
+ 0xfffffffc};
+ u32 SavedWords[2];
+ u32 ActualData;
+ u32 ActualEcc;
+ u32 CounterValue = 0;
+ u32 CounterMax;
+ int WordIndex = 0;
+ int Result = XST_SUCCESS;
+ int Index1;
+ int Index2;
+ int Width;
+
+ PrngResult = 42; /* Random seed */
+
+ /* Save two words in BRAM used for test */
+ SavedWords[0] = XBram_In32(Addr[0]);
+ SavedWords[1] = XBram_In32(Addr[1]);
+
+ for (Width = 1; Width <= 4; Width <<= 1) {
+ /* Calculate counter max value */
+ if (InstancePtr->Config.CorrectableCounterBits == 32) {
+ CounterMax = 0xFFFFFFFF;
+ } else {
+ CounterMax =(1 <<
+ InstancePtr->Config.CorrectableCounterBits) - 1;
+ }
+
+ /* Inject and check all single bit errors */
+ for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
+ /* Save counter value */
+ if (InstancePtr->Config.CorrectableCounterBits > 0) {
+ CounterValue = RD(CE_CNT_OFFSET);
+ }
+
+ /* Inject single bit error */
+ InjectErrors(InstancePtr, Addr[WordIndex], Index1,
+ Index1, Width, &ActualData, &ActualEcc);
+
+ /* Check that CE is set */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ CHECK(ECC_STATUS_OFFSET,
+ XBRAM_IR_CE_MASK, Result);
+ }
+
+ /* Check that address, data, ECC are correct */
+ if (InstancePtr->Config.CorrectableFailingRegisters) {
+ CHECK(CE_FFA_0_OFFSET, Addr[WordIndex], Result);
+ }
+ /* Checks are only for LMB BRAM */
+ if (InstancePtr->Config.CorrectableFailingDataRegs) {
+ CHECK(CE_FFD_0_OFFSET, ActualData, Result);
+ CHECK(CE_FFE_0_OFFSET, ActualEcc, Result);
+ }
+
+ /* Check that counter has incremented */
+ if (InstancePtr->Config.CorrectableCounterBits > 0 &&
+ CounterValue < CounterMax) {
+ CHECK(CE_CNT_OFFSET,
+ CounterValue + 1, Result);
+ }
+
+ /* Restore correct data in the used word */
+ XBram_Out32(Addr[WordIndex], SavedWords[WordIndex]);
+
+ /* Allow interrupts to occur */
+ /* Clear status register */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ WR(ECC_EN_IRQ_OFFSET, IntMask);
+ WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
+ WR(ECC_EN_IRQ_OFFSET, 0);
+ }
+
+ /* Switch to the other word */
+ WordIndex = WordIndex ^ 1;
+
+ if (Result != XST_SUCCESS) break;
+
+ }
+
+ if (Result != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
+ for (Index2 = 0; Index2 < TOTAL_BITS; Index2++) {
+ if (Index1 != Index2) {
+ /* Inject double bit error */
+ InjectErrors(InstancePtr,
+ Addr[WordIndex],
+ Index1, Index2, Width,
+ &ActualData,
+ &ActualEcc);
+
+ /* Check that UE is set */
+ if (InstancePtr->Config.
+ EccStatusInterruptPresent) {
+ CHECK(ECC_STATUS_OFFSET,
+ XBRAM_IR_UE_MASK,
+ Result);
+ }
+
+ /* Check that address, data, ECC are correct */
+ if (InstancePtr->Config.
+ UncorrectableFailingRegisters) {
+ CHECK(UE_FFA_0_OFFSET, Addr[WordIndex],
+ Result);
+ CHECK(UE_FFD_0_OFFSET,
+ ActualData, Result);
+ CHECK(UE_FFE_0_OFFSET, ActualEcc,
+ Result);
+ }
+
+ /* Restore correct data in the used word */
+ XBram_Out32(Addr[WordIndex],
+ SavedWords[WordIndex]);
+
+ /* Allow interrupts to occur */
+ /* Clear status register */
+ if (InstancePtr->Config.
+ EccStatusInterruptPresent) {
+ WR(ECC_EN_IRQ_OFFSET, IntMask);
+ WR(ECC_STATUS_OFFSET,
+ XBRAM_IR_ALL_MASK);
+ WR(ECC_EN_IRQ_OFFSET, 0);
+ }
+
+ /* Switch to the other word */
+ WordIndex = WordIndex ^ 1;
+ }
+ if (Result != XST_SUCCESS) break;
+ }
+ if (Result != XST_SUCCESS) break;
+ }
+
+ /* Check saturation of correctable error counter */
+ if (InstancePtr->Config.CorrectableCounterBits > 0 &&
+ Result == XST_SUCCESS) {
+
+ WR(CE_CNT_OFFSET, CounterMax);
+
+ InjectErrors(InstancePtr, Addr[WordIndex], 0, 0,
+ 4, &ActualData, &ActualEcc);
+
+ CHECK(CE_CNT_OFFSET, CounterMax, Result);
+ }
+
+ /* Restore the two words used for test */
+ XBram_Out32(Addr[0], SavedWords[0]);
+ XBram_Out32(Addr[1], SavedWords[1]);
+
+ /* Clear the Status Register. */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
+ }
+
+ /* Set Correctable Counter to zero */
+ if (InstancePtr->Config.CorrectableCounterBits > 0) {
+ WR(CE_CNT_OFFSET, 0);
+ }
+
+ if (Result != XST_SUCCESS) break;
+
+ } /* Width loop */
+
+ return (Result);
+ }
+
+ return (XST_SUCCESS);
+}
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xbram_sinit.c
+* @addtogroup bram_v4_0
+* @{
+*
+* The implementation of the XBram driver's static initialzation
+* functionality.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.01a jvb 10/13/05 First release
+* 2.11a mta 03/21/07 Updated to new coding style
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xbram.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XBram_Config XBram_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* ConfigTable contains the configuration info for each device in the system.
+*
+* @param DeviceId is the device identifier to lookup.
+*
+* @return
+* - A pointer of data type XBram_Config which
+* points to the device configuration if DeviceID is found.
+* - NULL if DeviceID is not found.
+*
+* @note None.
+*
+******************************************************************************/
+XBram_Config *XBram_LookupConfig(u16 DeviceId)
+{
+ XBram_Config *CfgPtr = NULL;
+
+ int Index;
+
+ for (Index = 0; Index < XPAR_XBRAM_NUM_INSTANCES; Index++) {
+ if (XBram_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XBram_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
+++ /dev/null
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES=*.c
-INCLUDEFILES=xio.h
-
-libs:
- echo "Compiling cpu"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OUTS}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file fsl.h
-*
-* This file contains macros for interfacing to the Fast Simplex Link (FSL)
-* interface..
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 06/20/07 Initial version, moved over from bsp area
-* 1.11c ecm 08/26/08 Fixed the missing 'FSL_DEFAULT' define that was causing
-* assembly errors.
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-
-#ifndef _FSL_H
-#define _FSL_H
-
-/***************************** Include Files *********************************/
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/* if these have not been defined already, define here */
-#ifndef stringify
-
-/* necessary for pre-processor */
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-
-#endif /* stringify */
-
-/* Extended FSL macros. These now replace all of the previous FSL macros */
-#define FSL_DEFAULT
-#define FSL_NONBLOCKING n
-#define FSL_EXCEPTION e
-#define FSL_CONTROL c
-#define FSL_ATOMIC a
-
-#define FSL_NONBLOCKING_EXCEPTION ne
-#define FSL_NONBLOCKING_CONTROL nc
-#define FSL_NONBLOCKING_ATOMIC na
-#define FSL_EXCEPTION_CONTROL ec
-#define FSL_EXCEPTION_ATOMIC ea
-#define FSL_CONTROL_ATOMIC ca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
-#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
-#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
-#define FSL_EXCEPTION_CONTROL_ATOMIC eca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
-
-#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
-
-#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
-
-#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
-
-#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
-
-/* if the mb_interface.h file has been included already, the following are not needed and will not be defined */
-
-/* Legacy FSL Access Macros */
-
-#ifndef getfsl
-
-/* Blocking Data Read and Write to FSL no. id */
-#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
-#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Non-blocking Data Read and Write to FSL no. id */
-#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
-#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Blocking Control Read and Write to FSL no. id */
-#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
-#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Non-blocking Control Read and Write to FSL no. id */
-#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
-#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Polling versions of FSL access macros. This makes the FSL access interruptible */
-#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- : "=d" (val) :: "r18")
-
-#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- :: "d" (val) : "r18")
-
-#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- : "=d" (val) :: "r18")
-
-#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- :: "d" (val) : "r18")
-/* FSL valid and error check macros. */
-#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
-#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
- "andi\t%0,%0,0x10" : "=d" (error))
-
-#endif /* legacy FSL defines */
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FSL_H */
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xio.c
-*
-* Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures. These functions encapsulate generic CPU I/O requirements.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
-* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
-* and bumped version to 1.01.a.
-* 2.11a mta 03/21/07 Updated to new coding style.
-*
-* </pre>
-*
-* @note
-*
-* This file may contain architecture-dependent code.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xio.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Performs a 16-bit endian converion.
-*
-* @param Source contains the value to be converted.
-* @param DestPtr contains a pointer to the location to put the
-* converted value.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIo_EndianSwap16(u16 Source, u16 *DestPtr)
-{
- *DestPtr = (u16) (((Source & 0xFF00) >> 8) | ((Source & 0x00FF) << 8));
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs a 32-bit endian converion.
-*
-* @param Source contains the value to be converted.
-* @param DestPtr contains a pointer to the location to put the
-* converted value.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIo_EndianSwap32(u32 Source, u32 *DestPtr)
-{
- /* get each of the half words from the 32 bit word */
-
- u16 LoWord = (u16) (Source & 0x0000FFFF);
- u16 HiWord = (u16) ((Source & 0xFFFF0000) >> 16);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
- HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
-
- /* swap the half words before returning the value */
-
- *DestPtr = (u32) ((LoWord << 16) | HiWord);
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the byte-swapped value read from that
-* address.
-*
-* @param InAddress contains the address to perform the input
-* operation at.
-*
-* @return The byte-swapped value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-u16 XIo_InSwap16(XIo_Address InAddress)
-{
- u16 InData;
-
- /* get the data then swap it */
- InData = XIo_In16(InAddress);
-
- return (u16) (((InData & 0xFF00) >> 8) | ((InData & 0x00FF) << 8));
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the byte-swapped value read from that
-* address.
-*
-* @param InAddress contains the address to perform the input
-* operation at.
-*
-* @return The byte-swapped value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XIo_InSwap32(XIo_Address InAddress)
-{
- u32 InData;
- u32 SwapData;
-
- /* get the data then swap it */
- InData = XIo_In32(InAddress);
- XIo_EndianSwap32(InData, &SwapData);
-
- return SwapData;
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 16-bit memory location by writing the
-* specified value to the the specified address. The value is byte-swapped
-* before being written.
-*
-* @param OutAddress contains the address to perform the output
-* operation at.
-* @param Value contains the value to be output at the specified address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIo_OutSwap16(XIo_Address OutAddress, u16 Value)
-{
- u16 OutData;
-
- /* swap the data then output it */
- OutData = (u16) (((Value & 0xFF00) >> 8) | ((Value & 0x00FF) << 8));
-
- XIo_Out16(OutAddress, OutData);
-}
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 32-bit memory location by writing the
-* specified value to the the specified address. The value is byte-swapped
-* before being written.
-*
-* @param OutAddress contains the address at which the
-* output operation has to be done.
-* @param Value contains the value to be output at the specified address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIo_OutSwap32(XIo_Address OutAddress, u32 Value)
-{
- u32 OutData;
-
- /* swap the data then output it */
- XIo_EndianSwap32(Value, &OutData);
- XIo_Out32(OutAddress, OutData);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xio.h
-*
-* This file contains the interface for the XIo component, which encapsulates
-* the Input/Output functions for processors that do not require any special
-* I/O handling.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
-* 1.00a xd 11/04/04 Improved support for doxygen
-* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
-* and bumped version to 1.01.a.
-* 1.11a mta 03/21/07 Updated to new coding style.
-* 1.11b va 04/17/08 Updated Tcl for better CORE_CLOCK_FREQ_HZ definition
-* 1.11a sdm 03/12/09 Updated Tcl to define correct value for CORE_CLOCK_FREQ_HZ
-* (CR #502010)
-* 1.13a sdm 03/12/09 Updated the Tcl to pull appropriate libraries for Little
-* Endian Microblaze
-* 2.0 adk 19/12/13 Updated as per the New Tcl API's
-* 2.1 bss 04/14/14 Updated tcl to copy libgloss.a and libgcc.a libraries
-* 2.1 bss 04/29/14 Updated to copy libgloss.a if exists otherwise libxil.a
-* CR#794205
-* 2.2 bss 08/04/14 Updated driver tcl to add protection macros for
-* xparameters.h (CR#802257).
-*
-* </pre>
-*
-* @note
-*
-* This file may contain architecture-dependent items (memory-mapped or
-* non-memory-mapped I/O).
-*
-******************************************************************************/
-
-#ifndef XIO_H /* prevent circular inclusions */
-#define XIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/**
- * Typedef for an I/O address. Typically correlates to the width of the
- * address bus.
- */
-typedef u32 XIo_Address;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * The following macros allow optimized I/O operations for memory mapped I/O.
- * It should be noted that macros cannot be used if synchronization of the I/O
- * operation is needed as it will likely break some code.
- */
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for an 8-bit memory location by reading from the
-* specified address and returning the value read from that address.
-*
-* @param InputPtr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-#define XIo_In8(InputPtr) (*(volatile u8 *)(InputPtr))
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the value read from that address.
-*
-* @param InputPtr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-#define XIo_In16(InputPtr) (*(volatile u16 *)(InputPtr))
-
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the value read from that address.
-*
-* @param InputPtr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-#define XIo_In32(InputPtr) (*(volatile u32 *)(InputPtr))
-
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for an 8-bit memory location by writing the
-* specified value to the the specified address.
-*
-* @param OutputPtr contains the address to perform the output operation
-* at.
-* @param Value contains the value to be output at the specified address.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define XIo_Out8(OutputPtr, Value) \
- (*(volatile u8 *)((OutputPtr)) = (Value))
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 16-bit memory location by writing the
-* specified value to the the specified address.
-*
-* @param OutputPtr contains the address to perform the output operation
-* at.
-* @param Value contains the value to be output at the specified address.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define XIo_Out16(OutputPtr, Value) \
- (*(volatile u16 *)((OutputPtr)) = (Value))
-
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 32-bit memory location by writing the
-* specified value to the the specified address.
-*
-* @param OutputPtr contains the address to perform the output operation
-* at.
-* @param Value contains the value to be output at the specified address.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define XIo_Out32(OutputPtr, Value) \
- (*(volatile u32 *)((OutputPtr)) = (Value))
-
-
-/* The following macros allow the software to be transportable across
- * processors which use big or little endian memory models.
- *
- * Defined first is a no-op endian conversion macro. This macro is not to
- * be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
- * XIo_To/FromBigEndianXX macros below are to be used to allow the endian
- * conversion to only be performed when necessary
- */
-#define XIo_EndianNoop(Source, DestPtr) (*DestPtr = Source)
-
-#ifdef XLITTLE_ENDIAN
-
-#define XIo_ToLittleEndian16 XIo_EndianNoop
-#define XIo_ToLittleEndian32 XIo_EndianNoop
-#define XIo_FromLittleEndian16 XIo_EndianNoop
-#define XIo_FromLittleEndian32 XIo_EndianNoop
-
-#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
-#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
-#define XIo_FromBigEndian16 XIo_ToBigEndian16
-#define XIo_FromBigEndian32 XIo_ToBigEndian32
-
-#else
-
-#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
-#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
-#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
-#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
-
-#define XIo_ToBigEndian16 XIo_EndianNoop
-#define XIo_ToBigEndian32 XIo_EndianNoop
-#define XIo_FromBigEndian16 XIo_EndianNoop
-#define XIo_FromBigEndian32 XIo_EndianNoop
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-/* The following functions allow the software to be transportable across
- * processors which use big or little endian memory models. These functions
- * should not be directly called, but the macros XIo_To/FromLittleEndianXX and
- * XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
- * be performed when necessary.
- */
-void XIo_EndianSwap16(u16 Source, u16 *DestPtr);
-void XIo_EndianSwap32(u32 Source, u32 *DestPtr);
-
-/* The following functions handle IO addresses where data must be swapped
- * They cannot be implemented as macros
- */
-u16 XIo_InSwap16(XIo_Address InAddress);
-u32 XIo_InSwap32(XIo_Address InAddress);
-void XIo_OutSwap16(XIo_Address OutAddress, u16 Value);
-void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
--- /dev/null
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES=*.c
+INCLUDEFILES=xio.h
+
+libs:
+ echo "Compiling cpu"
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OUTS}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file fsl.h
+* @addtogroup cpu_v2_3
+* @{
+*
+* This file contains macros for interfacing to the Fast Simplex Link (FSL)
+* interface..
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 06/20/07 Initial version, moved over from bsp area
+* 1.11c ecm 08/26/08 Fixed the missing 'FSL_DEFAULT' define that was causing
+* assembly errors.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+
+#ifndef _FSL_H
+#define _FSL_H
+
+/***************************** Include Files *********************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/* if these have not been defined already, define here */
+#ifndef stringify
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#endif /* stringify */
+
+/* Extended FSL macros. These now replace all of the previous FSL macros */
+#define FSL_DEFAULT
+#define FSL_NONBLOCKING n
+#define FSL_EXCEPTION e
+#define FSL_CONTROL c
+#define FSL_ATOMIC a
+
+#define FSL_NONBLOCKING_EXCEPTION ne
+#define FSL_NONBLOCKING_CONTROL nc
+#define FSL_NONBLOCKING_ATOMIC na
+#define FSL_EXCEPTION_CONTROL ec
+#define FSL_EXCEPTION_ATOMIC ea
+#define FSL_CONTROL_ATOMIC ca
+
+#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
+#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
+#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
+#define FSL_EXCEPTION_CONTROL_ATOMIC eca
+
+#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
+
+#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
+#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
+
+#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
+#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
+
+#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
+#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
+
+#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
+#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
+
+/* if the mb_interface.h file has been included already, the following are not needed and will not be defined */
+
+/* Legacy FSL Access Macros */
+
+#ifndef getfsl
+
+/* Blocking Data Read and Write to FSL no. id */
+#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
+#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Non-blocking Data Read and Write to FSL no. id */
+#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
+#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Blocking Control Read and Write to FSL no. id */
+#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
+#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Non-blocking Control Read and Write to FSL no. id */
+#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
+#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Polling versions of FSL access macros. This makes the FSL access interruptible */
+#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ : "=d" (val) :: "r18")
+
+#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ :: "d" (val) : "r18")
+
+#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ : "=d" (val) :: "r18")
+
+#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ :: "d" (val) : "r18")
+/* FSL valid and error check macros. */
+#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
+#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
+ "andi\t%0,%0,0x10" : "=d" (error))
+
+#endif /* legacy FSL defines */
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FSL_H */
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xio.c
+* @addtogroup cpu_v2_3
+* @{
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures. These functions encapsulate generic CPU I/O requirements.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
+* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
+* and bumped version to 1.01.a.
+* 2.11a mta 03/21/07 Updated to new coding style.
+*
+* </pre>
+*
+* @note
+*
+* This file may contain architecture-dependent code.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xio.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Performs a 16-bit endian converion.
+*
+* @param Source contains the value to be converted.
+* @param DestPtr contains a pointer to the location to put the
+* converted value.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XIo_EndianSwap16(u16 Source, u16 *DestPtr)
+{
+ *DestPtr = (u16) (((Source & 0xFF00) >> 8) | ((Source & 0x00FF) << 8));
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs a 32-bit endian converion.
+*
+* @param Source contains the value to be converted.
+* @param DestPtr contains a pointer to the location to put the
+* converted value.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XIo_EndianSwap32(u32 Source, u32 *DestPtr)
+{
+ /* get each of the half words from the 32 bit word */
+
+ u16 LoWord = (u16) (Source & 0x0000FFFF);
+ u16 HiWord = (u16) ((Source & 0xFFFF0000) >> 16);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
+ HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
+
+ /* swap the half words before returning the value */
+
+ *DestPtr = (u32) ((LoWord << 16) | HiWord);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the byte-swapped value read from that
+* address.
+*
+* @param InAddress contains the address to perform the input
+* operation at.
+*
+* @return The byte-swapped value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+u16 XIo_InSwap16(XIo_Address InAddress)
+{
+ u16 InData;
+
+ /* get the data then swap it */
+ InData = XIo_In16(InAddress);
+
+ return (u16) (((InData & 0xFF00) >> 8) | ((InData & 0x00FF) << 8));
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the byte-swapped value read from that
+* address.
+*
+* @param InAddress contains the address to perform the input
+* operation at.
+*
+* @return The byte-swapped value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XIo_InSwap32(XIo_Address InAddress)
+{
+ u32 InData;
+ u32 SwapData;
+
+ /* get the data then swap it */
+ InData = XIo_In32(InAddress);
+ XIo_EndianSwap32(InData, &SwapData);
+
+ return SwapData;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified value to the the specified address. The value is byte-swapped
+* before being written.
+*
+* @param OutAddress contains the address to perform the output
+* operation at.
+* @param Value contains the value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XIo_OutSwap16(XIo_Address OutAddress, u16 Value)
+{
+ u16 OutData;
+
+ /* swap the data then output it */
+ OutData = (u16) (((Value & 0xFF00) >> 8) | ((Value & 0x00FF) << 8));
+
+ XIo_Out16(OutAddress, OutData);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified value to the the specified address. The value is byte-swapped
+* before being written.
+*
+* @param OutAddress contains the address at which the
+* output operation has to be done.
+* @param Value contains the value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XIo_OutSwap32(XIo_Address OutAddress, u32 Value)
+{
+ u32 OutData;
+
+ /* swap the data then output it */
+ XIo_EndianSwap32(Value, &OutData);
+ XIo_Out32(OutAddress, OutData);
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xio.h
+* @addtogroup cpu_v2_3
+* @{
+* @details
+*
+* This file contains the interface for the XIo component, which encapsulates
+* the Input/Output functions for processors that do not require any special
+* I/O handling.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
+* 1.00a xd 11/04/04 Improved support for doxygen
+* 1.01a ecm 02/24/06 CR225908 corrected the extra curly braces in macros
+* and bumped version to 1.01.a.
+* 1.11a mta 03/21/07 Updated to new coding style.
+* 1.11b va 04/17/08 Updated Tcl for better CORE_CLOCK_FREQ_HZ definition
+* 1.11a sdm 03/12/09 Updated Tcl to define correct value for CORE_CLOCK_FREQ_HZ
+* (CR #502010)
+* 1.13a sdm 03/12/09 Updated the Tcl to pull appropriate libraries for Little
+* Endian Microblaze
+* 2.0 adk 19/12/13 Updated as per the New Tcl API's
+* 2.1 bss 04/14/14 Updated tcl to copy libgloss.a and libgcc.a libraries
+* 2.1 bss 04/29/14 Updated to copy libgloss.a if exists otherwise libxil.a
+* CR#794205
+* 2.2 bss 08/04/14 Updated driver tcl to add protection macros for
+* xparameters.h (CR#802257).
+* 2.3 sk 12/15/14 Updated mdd file to delete �ffunction-sections &
+* -fdata-sections flags from extra compiler flags CR#838648
+* Changed default os to latest version in mdd file.
+* 2.4 nsk 11/05/15 Updated generate and post_generate procs in driver tcl
+* not to generate cpu macros, when microblaze is connected
+* as one of the streaming slaves to itself. CR#876604
+*
+* </pre>
+*
+* @note
+*
+* This file may contain architecture-dependent items (memory-mapped or
+* non-memory-mapped I/O).
+*
+******************************************************************************/
+
+#ifndef XIO_H /* prevent circular inclusions */
+#define XIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * Typedef for an I/O address. Typically correlates to the width of the
+ * address bus.
+ */
+typedef u32 XIo_Address;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * The following macros allow optimized I/O operations for memory mapped I/O.
+ * It should be noted that macros cannot be used if synchronization of the I/O
+ * operation is needed as it will likely break some code.
+ */
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the value read from that address.
+*
+* @param InputPtr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+#define XIo_In8(InputPtr) (*(volatile u8 *)(InputPtr))
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the value read from that address.
+*
+* @param InputPtr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+#define XIo_In16(InputPtr) (*(volatile u16 *)(InputPtr))
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the value read from that address.
+*
+* @param InputPtr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+#define XIo_In32(InputPtr) (*(volatile u32 *)(InputPtr))
+
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified value to the the specified address.
+*
+* @param OutputPtr contains the address to perform the output operation
+* at.
+* @param Value contains the value to be output at the specified address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+#define XIo_Out8(OutputPtr, Value) \
+ (*(volatile u8 *)((OutputPtr)) = (Value))
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified value to the the specified address.
+*
+* @param OutputPtr contains the address to perform the output operation
+* at.
+* @param Value contains the value to be output at the specified address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+#define XIo_Out16(OutputPtr, Value) \
+ (*(volatile u16 *)((OutputPtr)) = (Value))
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified value to the the specified address.
+*
+* @param OutputPtr contains the address to perform the output operation
+* at.
+* @param Value contains the value to be output at the specified address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+#define XIo_Out32(OutputPtr, Value) \
+ (*(volatile u32 *)((OutputPtr)) = (Value))
+
+
+/* The following macros allow the software to be transportable across
+ * processors which use big or little endian memory models.
+ *
+ * Defined first is a no-op endian conversion macro. This macro is not to
+ * be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
+ * XIo_To/FromBigEndianXX macros below are to be used to allow the endian
+ * conversion to only be performed when necessary
+ */
+#define XIo_EndianNoop(Source, DestPtr) (*DestPtr = Source)
+
+#ifdef XLITTLE_ENDIAN
+
+#define XIo_ToLittleEndian16 XIo_EndianNoop
+#define XIo_ToLittleEndian32 XIo_EndianNoop
+#define XIo_FromLittleEndian16 XIo_EndianNoop
+#define XIo_FromLittleEndian32 XIo_EndianNoop
+
+#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
+#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
+#define XIo_FromBigEndian16 XIo_ToBigEndian16
+#define XIo_FromBigEndian32 XIo_ToBigEndian32
+
+#else
+
+#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
+#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
+#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
+#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
+
+#define XIo_ToBigEndian16 XIo_EndianNoop
+#define XIo_ToBigEndian32 XIo_EndianNoop
+#define XIo_FromBigEndian16 XIo_EndianNoop
+#define XIo_FromBigEndian32 XIo_EndianNoop
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which use big or little endian memory models. These functions
+ * should not be directly called, but the macros XIo_To/FromLittleEndianXX and
+ * XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
+ * be performed when necessary.
+ */
+void XIo_EndianSwap16(u16 Source, u16 *DestPtr);
+void XIo_EndianSwap32(u32 Source, u32 *DestPtr);
+
+/* The following functions handle IO addresses where data must be swapped
+ * They cannot be implemented as macros
+ */
+u16 XIo_InSwap16(XIo_Address InAddress);
+u32 XIo_InSwap32(XIo_Address InAddress);
+void XIo_OutSwap16(XIo_Address OutAddress, u16 Value);
+void XIo_OutSwap32(XIo_Address OutAddress, u32 Value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
+++ /dev/null
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-libs:
- echo "Compiling emaclite"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OUTS}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemaclite.c
-*
-* Functions in this file are the minimum required functions for the EmacLite
-* driver. See xemaclite.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.01a ecm 01/31/04 First release
-* 1.11a mta 03/21/07 Updated to new coding style
-* 1.11a ecm 05/18/07 Updated the TxBufferAvailable routine to look at both
-* the active and busy bits
-* 1.13a sv 02/1/08 Updated the TxBufferAvailable routine to return
-* busy status properly
-* 2.00a ktn 02/16/09 Added support for MDIO
-* 2.01a ktn 07/20/09 Modified XEmacLite_Send function to use Ping buffers
-* Interrupt enable bit since this alone is used to enable
-* the interrupts for both Ping and Pong Buffers.
-* 3.00a ktn 10/22/09 Updated driver to use the HAL APIs/macros.
-* The macros have been renamed to remove _m from the name.
-* 3.01a ktn 07/08/10 The macro XEmacLite_GetReceiveDataLength is changed to
-* a static function.
-* Updated the XEmacLite_GetReceiveDataLength and
-* XEmacLite_Recv functions to support little endian
-* MicroBlaze.
-* 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for
-* CR617290
-* 3.04a srt 04/13/13 Removed warnings (CR 705000).
-*
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-#include "xenv.h"
-#include "xemaclite.h"
-#include "xemaclite_i.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Initialize a specific XEmacLite instance/driver. The initialization entails:
-* - Initialize fields of the XEmacLite instance structure.
-*
-* The driver defaults to polled mode operation.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance.
-* @param EmacLiteConfigPtr points to the XEmacLite device configuration
-* structure.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. If the address translation is not used then the
-* physical address is passed.
-* Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-*
-* @note The initialization of the PHY device is not done in this
-* function. The user needs to use XEmacLite_PhyRead and
-* XEmacLite_PhyWrite functions to access the PHY device.
-*
-******************************************************************************/
-int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
- XEmacLite_Config *EmacLiteConfigPtr,
- u32 EffectiveAddr)
-{
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(EmacLiteConfigPtr != NULL);
-
- /*
- * Zero the provided instance memory.
- */
- memset(InstancePtr, 0, sizeof(XEmacLite));
-
- /*
- * Set some default values for instance data, don't indicate the device
- * is ready to use until everything has been initialized successfully.
- */
- InstancePtr->EmacLiteConfig.BaseAddress = EffectiveAddr;
- InstancePtr->EmacLiteConfig.DeviceId = EmacLiteConfigPtr->DeviceId;
- InstancePtr->EmacLiteConfig.TxPingPong = EmacLiteConfigPtr->TxPingPong;
- InstancePtr->EmacLiteConfig.RxPingPong = EmacLiteConfigPtr->RxPingPong;
- InstancePtr->EmacLiteConfig.MdioInclude = EmacLiteConfigPtr->MdioInclude;
- InstancePtr->EmacLiteConfig.Loopback = EmacLiteConfigPtr->Loopback;
-
- InstancePtr->NextTxBufferToUse = 0x0;
- InstancePtr->NextRxBufferToUse = 0x0;
- InstancePtr->RecvHandler = (XEmacLite_Handler) StubHandler;
- InstancePtr->SendHandler = (XEmacLite_Handler) StubHandler;
-
- /*
- * Clear the TX CSR's in case this is a restart.
- */
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_TSR_OFFSET, 0);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_BUFFER_OFFSET + XEL_TSR_OFFSET, 0);
-
- /*
- * Since there were no failures, indicate the device is ready to use.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Send an Ethernet frame. The ByteCount is the total frame size, including
-* header.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance.
-* @param FramePtr is a pointer to frame. For optimal performance, a
-* 32-bit aligned buffer should be used but it is not required, the
-* function will align the data if necessary.
-* @param ByteCount is the size, in bytes, of the frame
-*
-* @return
-* - XST_SUCCESS if data was transmitted.
-* - XST_FAILURE if buffer(s) was (were) full and no valid data was
-* transmitted.
-*
-* @note
-*
-* This function call is not blocking in nature, i.e. it will not wait until the
-* frame is transmitted.
-*
-******************************************************************************/
-int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount)
-{
- u32 Register;
- u32 BaseAddress;
- u32 EmacBaseAddress;
- u32 IntrEnableStatus;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Determine the expected TX buffer address.
- */
- BaseAddress = XEmacLite_NextTransmitAddr(InstancePtr);
- EmacBaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
-
- /*
- * Check the Length if it is too large, truncate it.
- * The maximum Tx packet size is
- * Ethernet header (14 Bytes) + Maximum MTU (1500 bytes).
- */
- if (ByteCount > XEL_MAX_TX_FRAME_SIZE) {
-
- ByteCount = XEL_MAX_TX_FRAME_SIZE;
- }
-
- /*
- * Determine if the expected buffer address is empty.
- */
- Register = XEmacLite_GetTxStatus(BaseAddress);
-
- /*
- * If the expected buffer is available, fill it with the provided data
- * Align if necessary.
- */
- if ((Register & (XEL_TSR_XMIT_BUSY_MASK |
- XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
-
- /*
- * Switch to next buffer if configured.
- */
- if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
- InstancePtr->NextTxBufferToUse ^= XEL_BUFFER_OFFSET;
- }
-
- /*
- * Write the frame to the buffer.
- */
- XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress,
- ByteCount);
-
-
- /*
- * The frame is in the buffer, now send it.
- */
- XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
- (ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
- XEL_TPLR_LENGTH_MASK_LO)));
-
- /*
- * Update the Tx Status Register to indicate that there is a
- * frame to send.
- * If the interrupt enable bit of Ping buffer(since this
- * controls both the buffers) is enabled then set the
- * XEL_TSR_XMIT_ACTIVE_MASK flag which is used by the interrupt
- * handler to call the callback function provided by the user
- * to indicate that the frame has been transmitted.
- */
- Register = XEmacLite_GetTxStatus(BaseAddress);
- Register |= XEL_TSR_XMIT_BUSY_MASK;
- IntrEnableStatus = XEmacLite_GetTxStatus(EmacBaseAddress);
- if ((IntrEnableStatus & XEL_TSR_XMIT_IE_MASK) != 0) {
- Register |= XEL_TSR_XMIT_ACTIVE_MASK;
- }
- XEmacLite_SetTxStatus(BaseAddress, Register);
-
- return XST_SUCCESS;
- }
-
- /*
- * If the expected buffer was full, try the other buffer if configured.
- */
- if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
-
- BaseAddress ^= XEL_BUFFER_OFFSET;
-
- /*
- * Determine if the expected buffer address is empty.
- */
- Register = XEmacLite_GetTxStatus(BaseAddress);
-
- /*
- * If the next buffer is available, fill it with the provided
- * data.
- */
- if ((Register & (XEL_TSR_XMIT_BUSY_MASK |
- XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
-
- /*
- * Write the frame to the buffer.
- */
- XEmacLite_AlignedWrite(FramePtr, (u32 *) BaseAddress,
- ByteCount);
-
- /*
- * The frame is in the buffer, now send it.
- */
- XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
- (ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
- XEL_TPLR_LENGTH_MASK_LO)));
-
- /*
- * Update the Tx Status Register to indicate that there
- * is a frame to send.
- * If the interrupt enable bit of Ping buffer(since this
- * controls both the buffers) is enabled then set the
- * XEL_TSR_XMIT_ACTIVE_MASK flag which is used by the
- * interrupt handler to call the callback function
- * provided by the user to indicate that the frame has
- * been transmitted.
- */
- Register = XEmacLite_GetTxStatus(BaseAddress);
- Register |= XEL_TSR_XMIT_BUSY_MASK;
- IntrEnableStatus =
- XEmacLite_GetTxStatus(EmacBaseAddress);
- if ((IntrEnableStatus & XEL_TSR_XMIT_IE_MASK) != 0) {
- Register |= XEL_TSR_XMIT_ACTIVE_MASK;
- }
- XEmacLite_SetTxStatus(BaseAddress, Register);
-
- /*
- * Do not switch to next buffer, there is a sync problem
- * and the expected buffer should not change.
- */
- return XST_SUCCESS;
- }
- }
-
-
- /*
- * Buffer(s) was(were) full, return failure to allow for polling usage.
- */
- return XST_FAILURE;
-}
-
-/*****************************************************************************/
-/**
-*
-* Receive a frame. Intended to be called from the interrupt context or
-* with a wrapper which waits for the receive frame to be available.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance.
-* @param FramePtr is a pointer to a buffer where the frame will
-* be stored. The buffer must be at least XEL_MAX_FRAME_SIZE bytes.
-* For optimal performance, a 32-bit aligned buffer should be used
-* but it is not required, the function will align the data if
-* necessary.
-*
-* @return
-*
-* The type/length field of the frame received. When the type/length field
-* contains the type, XEL_MAX_FRAME_SIZE bytes will be copied out of the
-* buffer and it is up to the higher layers to sort out the frame.
-* Function returns 0 if there is no data waiting in the receive buffer or
-* the pong buffer if configured.
-*
-* @note
-*
-* This function call is not blocking in nature, i.e. it will not wait until
-* a frame arrives.
-*
-******************************************************************************/
-u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr)
-{
- u16 LengthType;
- u16 Length;
- u32 Register;
- u32 BaseAddress;
-
- /*
- * Verify that each of the inputs are valid.
- */
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Determine the expected buffer address.
- */
- BaseAddress = XEmacLite_NextReceiveAddr(InstancePtr);
-
- /*
- * Verify which buffer has valid data.
- */
- Register = XEmacLite_GetRxStatus(BaseAddress);
-
- if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
-
- /*
- * The driver is in sync, update the next expected buffer if
- * configured.
- */
-
- if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
- InstancePtr->NextRxBufferToUse ^= XEL_BUFFER_OFFSET;
- }
- }
- else {
- /*
- * The instance is out of sync, try other buffer if other
- * buffer is configured, return 0 otherwise. If the instance is
- * out of sync, do not update the 'NextRxBufferToUse' since it
- * will correct on subsequent calls.
- */
- if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
- BaseAddress ^= XEL_BUFFER_OFFSET;
- }
- else {
- return 0; /* No data was available */
- }
-
- /*
- * Verify that buffer has valid data.
- */
- Register = XEmacLite_GetRxStatus(BaseAddress);
- if ((Register & XEL_RSR_RECV_DONE_MASK) !=
- XEL_RSR_RECV_DONE_MASK) {
- return 0; /* No data was available */
- }
- }
-
- /*
- * Get the length of the frame that arrived.
- */
- LengthType = XEmacLite_GetReceiveDataLength(BaseAddress);
-
- /*
- * Check if length is valid.
- */
- if (LengthType > XEL_MAX_FRAME_SIZE) {
-
-
- if (LengthType == XEL_ETHER_PROTO_TYPE_IP) {
-
- /*
- * The packet is a an IP Packet.
- */
-#ifdef __LITTLE_ENDIAN__
- Length = (XEmacLite_ReadReg((BaseAddress),
- XEL_HEADER_IP_LENGTH_OFFSET +
- XEL_RXBUFF_OFFSET) &
- (XEL_RPLR_LENGTH_MASK_HI |
- XEL_RPLR_LENGTH_MASK_LO));
- Length = (u16) (((Length & 0xFF00) >> 8) | ((Length & 0x00FF) << 8));
-#else
- Length = ((XEmacLite_ReadReg((BaseAddress),
- XEL_HEADER_IP_LENGTH_OFFSET +
- XEL_RXBUFF_OFFSET) >>
- XEL_HEADER_SHIFT) &
- (XEL_RPLR_LENGTH_MASK_HI |
- XEL_RPLR_LENGTH_MASK_LO));
-#endif
-
- Length += XEL_HEADER_SIZE + XEL_FCS_SIZE;
-
- } else if (LengthType == XEL_ETHER_PROTO_TYPE_ARP) {
-
- /*
- * The packet is an ARP Packet.
- */
- Length = XEL_ARP_PACKET_SIZE + XEL_HEADER_SIZE +
- XEL_FCS_SIZE;
-
- } else {
- /*
- * Field contains type other than IP or ARP, use max
- * frame size and let user parse it.
- */
- Length = XEL_MAX_FRAME_SIZE;
-
- }
- } else {
-
- /*
- * Use the length in the frame, plus the header and trailer.
- */
- Length = LengthType + XEL_HEADER_SIZE + XEL_FCS_SIZE;
- }
-
- /*
- * Read from the EmacLite.
- */
- XEmacLite_AlignedRead(((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET)),
- FramePtr, Length);
-
- /*
- * Acknowledge the frame.
- */
- Register = XEmacLite_GetRxStatus(BaseAddress);
- Register &= ~XEL_RSR_RECV_DONE_MASK;
- XEmacLite_SetRxStatus(BaseAddress, Register);
-
- return Length;
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the MAC address for this device. The address is a 48-bit value.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance.
-* @param AddressPtr is a pointer to a 6-byte MAC address.
-* the format of the MAC address is major octet to minor octet
-*
-* @return None.
-*
-* @note
-*
-* - TX must be idle and RX should be idle for deterministic results.
-* It is recommended that this function should be called after the
-* initialization and before transmission of any packets from the device.
-* - Function will not return if hardware is absent or not functioning
-* properly.
-* - The MAC address can be programmed using any of the two transmit
-* buffers (if configured).
-*
-******************************************************************************/
-void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr)
-{
- u32 BaseAddress;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Determine the expected TX buffer address.
- */
- BaseAddress = XEmacLite_NextTransmitAddr(InstancePtr);
-
- /*
- * Copy the MAC address to the Transmit buffer.
- */
- XEmacLite_AlignedWrite(AddressPtr,
- (u32 *) BaseAddress,
- XEL_MAC_ADDR_SIZE);
-
- /*
- * Set the length.
- */
- XEmacLite_WriteReg(BaseAddress,
- XEL_TPLR_OFFSET,
- XEL_MAC_ADDR_SIZE);
-
- /*
- * Update the MAC address in the EmacLite.
- */
- XEmacLite_SetTxStatus(BaseAddress, XEL_TSR_PROG_MAC_ADDR);
-
-
- /*
- * Wait for EmacLite to finish with the MAC address update.
- */
- while ((XEmacLite_GetTxStatus(BaseAddress) &
- XEL_TSR_PROG_MAC_ADDR) != 0);
-
-}
-
-/******************************************************************************/
-/**
-*
-* This is a stub for the send and receive callbacks. The stub
-* is here in case the upper layers forget to set the handlers.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void StubHandler(void *CallBackRef)
-{
- (void)(CallBackRef);
- Xil_AssertVoidAlways();
-}
-
-
-/****************************************************************************/
-/**
-*
-* Determine if there is a transmit buffer available.
-*
-* @param InstancePtr is the pointer to the instance of the driver to
-* be worked on.
-*
-* @return
-* - TRUE if there is a TX buffer available for data to be written
-* - FALSE if Tx Buffer is not available.
-*
-* @note None.
-*
-*****************************************************************************/
-int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr)
-{
-
- u32 Register;
- int TxPingBusy;
- int TxPongBusy;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Read the Tx Status and determine if the buffer is available.
- */
- Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig.
- BaseAddress);
-
- TxPingBusy = (Register & (XEL_TSR_XMIT_BUSY_MASK |
- XEL_TSR_XMIT_ACTIVE_MASK));
-
-
- /*
- * Read the Tx Status of the second buffer register and determine if the
- * buffer is available.
- */
- if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
- Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig.
- BaseAddress +
- XEL_BUFFER_OFFSET);
-
- TxPongBusy = (Register & (XEL_TSR_XMIT_BUSY_MASK |
- XEL_TSR_XMIT_ACTIVE_MASK));
-
- return (!(TxPingBusy && TxPongBusy));
- }
-
- return (!TxPingBusy);
-
-
-}
-
-/****************************************************************************/
-/**
-*
-* Flush the Receive buffers. All data will be lost.
-*
-* @param InstancePtr is the pointer to the instance of the driver to
-* be worked on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XEmacLite_FlushReceive(XEmacLite *InstancePtr)
-{
-
- u32 Register;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Read the current buffer register and determine if the buffer is
- * available.
- */
- Register = XEmacLite_GetRxStatus(InstancePtr->EmacLiteConfig.
- BaseAddress);
-
- /*
- * Preserve the IE bit.
- */
- Register &= XEL_RSR_RECV_IE_MASK;
-
- /*
- * Write out the value to flush the RX buffer.
- */
- XEmacLite_SetRxStatus(InstancePtr->EmacLiteConfig.BaseAddress,
- Register);
-
- /*
- * If the pong buffer is available, flush it also.
- */
- if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
- /*
- * Read the current buffer register and determine if the buffer
- * is available.
- */
- Register = XEmacLite_GetRxStatus(InstancePtr->EmacLiteConfig.
- BaseAddress +
- XEL_BUFFER_OFFSET);
-
- /*
- * Preserve the IE bit.
- */
- Register &= XEL_RSR_RECV_IE_MASK;
-
- /*
- * Write out the value to flush the RX buffer.
- */
- XEmacLite_SetRxStatus(InstancePtr->EmacLiteConfig.BaseAddress +
- XEL_BUFFER_OFFSET, Register);
-
- }
-
-}
-
-/******************************************************************************/
-/**
-*
-* Read the specified PHY register.
-*
-* @param InstancePtr is the pointer to the instance of the driver.
-* @param PhyAddress is the address of the PHY device. The valid range is
-* is from 0 to 31.
-* @param RegNum is the register number in the PHY device which
-* is to be read. The valid range is is from 0 to 31.
-* @param PhyDataPtr is a pointer to the data in which the data read
-* from the PHY device is returned.
-*
-* @return
-* - XST_SUCCESS if the data is read from the PHY.
-* - XST_DEVICE_BUSY if MDIO is busy.
-*
-* @note This function waits for the completion of MDIO data transfer.
-*
-*****************************************************************************/
-int XEmacLite_PhyRead(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
- u16 *PhyDataPtr)
-{
- u32 PhyAddrReg;
- u32 MdioCtrlReg;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->EmacLiteConfig.MdioInclude == TRUE);
- Xil_AssertNonvoid(PhyAddress <= 31);
- Xil_AssertNonvoid(RegNum <= 31);
- Xil_AssertNonvoid(PhyDataPtr != NULL);
-
- /*
- * Verify MDIO master status.
- */
- if (XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET) &
- XEL_MDIOCNTR_STATUS_MASK) {
- return XST_DEVICE_BUSY;
- }
-
- PhyAddrReg = ((((PhyAddress << XEL_MDIO_ADDRESS_SHIFT) &
- XEL_MDIO_ADDRESS_MASK) | RegNum) | XEL_MDIO_OP_MASK);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOADDR_OFFSET, PhyAddrReg);
-
- /*
- * Enable MDIO and start the transfer.
- */
- MdioCtrlReg =
- XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET,
- MdioCtrlReg |
- XEL_MDIOCNTR_STATUS_MASK |
- XEL_MDIOCNTR_ENABLE_MASK);
-
- /*
- * Wait till the completion of transfer.
- */
- while ((XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET) &
- XEL_MDIOCNTR_STATUS_MASK));
-
- /*
- * Read data from MDIO read data register.
- */
- *PhyDataPtr = (u16)XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIORD_OFFSET);
-
- /*
- * Disable the MDIO.
- */
- MdioCtrlReg =
- XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET);
-
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET,
- MdioCtrlReg & ~XEL_MDIOCNTR_ENABLE_MASK);
-
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* Write the given data to the specified register in the PHY device.
-*
-* @param InstancePtr is the pointer to the instance of the driver.
-* @param PhyAddress is the address of the PHY device. The valid range is
-* is from 0 to 31.
-* @param RegNum is the register number in the PHY device which
-* is to be written. The valid range is is from 0 to 31.
-* @param PhyData is the data to be written to the specified register in
-* the PHY device.
-*
-* @return
-* - XST_SUCCESS if the data is written to the PHY.
-* - XST_DEVICE_BUSY if MDIO is busy.
-*
-* @note This function waits for the completion of MDIO data transfer.
-*
-*******************************************************************************/
-int XEmacLite_PhyWrite(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
- u16 PhyData)
-{
- u32 PhyAddrReg;
- u32 MdioCtrlReg;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->EmacLiteConfig.MdioInclude == TRUE);
- Xil_AssertNonvoid(PhyAddress <= 31);
- Xil_AssertNonvoid(RegNum <= 31);
-
- /*
- * Verify MDIO master status.
- */
- if (XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET) &
- XEL_MDIOCNTR_STATUS_MASK) {
- return XST_DEVICE_BUSY;
- }
-
-
-
- PhyAddrReg = ((((PhyAddress << XEL_MDIO_ADDRESS_SHIFT) &
- XEL_MDIO_ADDRESS_MASK) | RegNum) & ~XEL_MDIO_OP_MASK);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOADDR_OFFSET, PhyAddrReg);
-
- /*
- * Write data to MDIO write data register.
- */
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOWR_OFFSET, (u32)PhyData);
-
- /*
- * Enable MDIO and start the transfer.
- */
- MdioCtrlReg =
- XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET,
- MdioCtrlReg | XEL_MDIOCNTR_STATUS_MASK |
- XEL_MDIOCNTR_ENABLE_MASK);
-
- /*
- * Wait till the completion of transfer.
- */
- while ((XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET) & XEL_MDIOCNTR_STATUS_MASK));
-
-
- /*
- * Disable the MDIO.
- */
- MdioCtrlReg =
- XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_MDIOCNTR_OFFSET,
- MdioCtrlReg & ~XEL_MDIOCNTR_ENABLE_MASK);
-
-
-
- return XST_SUCCESS;
-}
-
-
-
-/****************************************************************************/
-/**
-*
-* Enable Internal loop back functionality.
-*
-* @param InstancePtr is the pointer to the instance of the driver.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XEmacLite_EnableLoopBack(XEmacLite *InstancePtr)
-{
- u32 TsrReg;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->EmacLiteConfig.Loopback == TRUE);
-
- TsrReg = XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_TSR_OFFSET);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_TSR_OFFSET, TsrReg | XEL_TSR_LOOPBACK_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* Disable Internal loop back functionality.
-*
-* @param InstancePtr is the pointer to the instance of the driver.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr)
-{
- u32 TsrReg;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->EmacLiteConfig.Loopback == TRUE);
-
- TsrReg = XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_TSR_OFFSET);
- XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
- XEL_TSR_OFFSET, TsrReg & (~XEL_TSR_LOOPBACK_MASK));
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Return the length of the data in the Receive Buffer.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return The type/length field of the frame received.
-*
-* @note None.
-*
-******************************************************************************/
-static u16 XEmacLite_GetReceiveDataLength(u32 BaseAddress)
-{
- u16 Length;
-
-#ifdef __LITTLE_ENDIAN__
- Length = (XEmacLite_ReadReg((BaseAddress),
- XEL_HEADER_OFFSET + XEL_RXBUFF_OFFSET) &
- (XEL_RPLR_LENGTH_MASK_HI | XEL_RPLR_LENGTH_MASK_LO));
- Length = (u16) (((Length & 0xFF00) >> 8) | ((Length & 0x00FF) << 8));
-#else
- Length = ((XEmacLite_ReadReg((BaseAddress),
- XEL_HEADER_OFFSET + XEL_RXBUFF_OFFSET) >>
- XEL_HEADER_SHIFT) &
- (XEL_RPLR_LENGTH_MASK_HI | XEL_RPLR_LENGTH_MASK_LO));
-#endif
-
- return Length;
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemaclite.h
-*
-* The Xilinx Ethernet Lite (EmacLite) driver. This driver supports the Xilinx
-* Ethernet Lite 10/100 MAC (EmacLite).
-*
-* The Xilinx Ethernet Lite 10/100 MAC supports the following features:
-* - Media Independent Interface (MII) for connection to external
-* 10/100 Mbps PHY transceivers
-* - Independent internal transmit and receive buffers
-* - CSMA/CD compliant operations for half-duplex modes
-* - Unicast and broadcast
-* - Automatic FCS insertion
-* - Automatic pad insertion on transmit
-* - Configurable ping/pong buffers for either/both transmit and receive
-* buffer areas
-* - Interrupt driven mode
-* - Internal loop back
-* - MDIO Support to access PHY Registers
-*
-* The Xilinx Ethernet Lite 10/100 MAC does not support the following features:
-* - multi-frame buffering
-* only 1 transmit frame is allowed into each transmit buffer,
-* only 1 receive frame is allowed into each receive buffer.
-* the hardware blocks reception until buffer is emptied
-* - Pause frame (flow control) detection in full-duplex mode
-* - Programmable inter frame gap
-* - Multicast and promiscuous address filtering
-* - Automatic source address insertion or overwrite
-*
-* <b>Driver Description</b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the EmacLite. The driver handles transmission and reception
-* of Ethernet frames, as well as configuration of the controller. It does not
-* handle protocol stack functionality such as Link Layer Control (LLC) or the
-* Address Resolution Protocol (ARP). The protocol stack that makes use of the
-* driver handles this functionality. This implies that the driver is simply a
-* pass-through mechanism between a protocol stack and the EmacLite.
-*
-* Since the driver is a simple pass-through mechanism between a protocol stack
-* and the EmacLite, no assembly or disassembly of Ethernet frames is done at
-* the driver-level. This assumes that the protocol stack passes a correctly
-* formatted Ethernet frame to the driver for transmission, and that the driver
-* does not validate the contents of an incoming frame. A single device driver
-* can support multiple EmacLite devices.
-*
-* The driver supports interrupt driven mode and the default mode of operation
-* is polled mode. If interrupts are desired, XEmacLite_InterruptEnable() must
-* be called.
-*
-* <b>Device Configuration</b>
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xemaclite_g.c file.
-* A table is defined where each entry contains configuration information for an
-* EmacLite device. This information includes such things as the base address
-* of the memory-mapped device and the number of buffers.
-*
-* <b>Interrupt Processing</b>
-*
-* After _Initialize is called, _InterruptEnable can be called to enable the
-* interrupt driven functionality. If polled operation is desired, just call
-* _Send and check the return code. If XST_FAILURE is returned, call _Send with
-* the same data until XST_SUCCESS is returned. The same idea applies to _Recv.
-* Call _Recv until the returned length is non-zero at which point the received
-* data is in the buffer provided in the function call.
-*
-* The Transmit and Receive interrupts are enabled within the _InterruptEnable
-* function and disabled in the _InterruptDisable function. The _Send and _Recv
-* functions acknowledge the EmacLite generated interrupts associated with each
-* function.
-* It is the application's responsibility to acknowledge any associated Interrupt
-* Controller interrupts if it is used in the system.
-*
-* <b>Memory Buffer Alignment</b>
-*
-* The alignment of the input/output buffers for the _Send and _Recv routine is
-* not required to be 32 bits. If the buffer is not aligned on a 32-bit boundary
-* there will be a performance impact while the driver aligns the data for
-* transmission or upon reception.
-*
-* For optimum performance, the user should provide a 32-bit aligned buffer
-* to the _Send and _Recv routines.
-*
-* <b>Asserts</b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that application developers leave asserts on during
-* development.
-*
-* @note
-*
-* This driver requires EmacLite hardware version 1.01a and higher. It is not
-* compatible with earlier versions of the EmacLite hardware. Use version 1.00a
-* software driver for hardware version 1.00a/b.
-*
-* The RX hardware is enabled from powerup and there is no disable. It is
-* possible that frames have been received prior to the initialization
-* of the driver. If this situation is possible, call XEmacLite_FlushReceive()
-* to empty the receive buffers after initialization.
-*
-* This driver is intended to be RTOS and processor independent. It works
-* with physical addresses only. Any needs for dynamic memory management,
-* threads or thread mutual exclusion, virtual memory, or cache control must
-* be satisfied by the layer above this driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.01a ecm 01/30/04 First release
-* 1.11a mta 03/21/07 Updated to new coding style
-* 1.12a mta 11/28/07 Added the function XEmacLite_CfgInitialize,
-* moved the functions XEmacLite_LookupConfig and
-* XEmacLite_Initialize to xemaclite_sinit.c for removing
-* the dependency on the static config table and
-* xparameters.h from the driver initialization
-* 1.13a sv 02/1/08 Updated the TxBufferAvailable routine to return
-* busy status properly and added macros for Tx/Rx status
-* 1.14a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 2.00a ktn 02/16/09 Added support for MDIO and internal loop back
-* 2.01a ktn 07/20/09 Updated the XEmacLite_AlignedWrite and
-* XEmacLite_AlignedRead functions to use volatile
-* variables so that they are not optimized.
-* Modified the XEmacLite_EnableInterrupts and
-* XEmacLite_DisableInterrupts functions to enable/disable
-* the interrupt in the Ping buffer as this is used to enable
-* the interrupts for both Ping and Pong Buffers.
-* The interrupt enable bit in the Pong buffer is not used by
-* the HW.
-* Modified XEmacLite_Send function to use Ping buffers
-* Interrupt enable bit since this alone is used to enable
-* the interrupts for both Ping and Pong Buffers.
-* 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros.
-* The macros have been renamed to remove _m from the name in
-* all the driver files.
-* The macros changed in this file are
-* XEmacLite_mNextTransmitAddr is XEmacLite_NextTransmitAddr,
-* XEmacLite_mNextReceiveAddr is XEmacLite_NextReceiveAddr,
-* XEmacLite_mIsMdioConfigured is XEmacLite_IsMdioConfigured,
-* XEmacLite_mIsLoopbackConfigured is
-* XEmacLite_IsLoopbackConfigured.
-* See xemaclite_i.h for the macros which have changed.
-* 3.01a ktn 07/08/10 The macro XEmacLite_GetReceiveDataLength in the
-* xemaclite.c file is changed to a static function.
-* XEmacLite_GetReceiveDataLength and XEmacLite_Recv
-* functions are updated to support little endian
-* MicroBlaze.
-* 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for
-* CR617290
-* 3.03a asa 04/05/12 Defined the flag __LITTLE_ENDIAN__ for cases where the
-* driver is compiled with ARM toolchain.
-* 3.04a srt 04/13/13 Removed warnings (CR 705000).
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-*
-* </pre>
-*
-*
-******************************************************************************/
-#ifndef XEMACLITE_H /* prevent circular inclusions */
-#define XEMACLITE_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xenv.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemaclite_l.h"
-
-#ifdef __ARMEL__
-#ifndef __LITTLE_ENDIAN__
-#define __LITTLE_ENDIAN__
-#endif
-#endif
-/************************** Constant Definitions *****************************/
-/*
- * Device information
- */
-#define XEL_DEVICE_NAME "xemaclite"
-#define XEL_DEVICE_DESC "Xilinx Ethernet Lite 10/100 MAC"
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
- u8 TxPingPong; /**< 1 if TX Pong buffer configured, 0 otherwise */
- u8 RxPingPong; /**< 1 if RX Pong buffer configured, 0 otherwise */
- u8 MdioInclude; /**< 1 if MDIO is enabled, 0 otherwise */
- u8 Loopback; /**< 1 if internal loopback is enabled, 0 otherwise */
-} XEmacLite_Config;
-
-
-/*
- * Callback when data is sent or received .
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions, and passed back to the
- * upper layer when the callback is invoked.
- */
-typedef void (*XEmacLite_Handler) (void *CallBackRef);
-
-/**
- * The XEmacLite driver instance data. The user is required to allocate a
- * variable of this type for every EmacLite device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XEmacLite_Config EmacLiteConfig; /* Device configuration */
- u32 IsReady; /* Device is initialized and ready */
-
- u32 NextTxBufferToUse; /* Next TX buffer to write to */
- u32 NextRxBufferToUse; /* Next RX buffer to read from */
-
- /*
- * Callbacks
- */
- XEmacLite_Handler RecvHandler;
- void *RecvRef;
- XEmacLite_Handler SendHandler;
- void *SendRef;
-
-} XEmacLite;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Return the next expected Transmit Buffer's address.
-*
-* @param InstancePtr is the pointer to the instance of the driver to
-* be worked on
-*
-* @note C-Style signature:
-* u32 XEmacLite_NextTransmitAddr(XEmacLite *InstancePtr);
-*
-* This macro returns the address of the next transmit buffer to put data into.
-* This is used to determine the destination of the next transmit data frame.
-*
-*****************************************************************************/
-#define XEmacLite_NextTransmitAddr(InstancePtr) \
- ((InstancePtr)->EmacLiteConfig.BaseAddress + \
- (InstancePtr)->NextTxBufferToUse) + XEL_TXBUFF_OFFSET
-
-/****************************************************************************/
-/**
-*
-* Return the next expected Receive Buffer's address.
-*
-* @param InstancePtr is the pointer to the instance of the driver to
-* be worked on
-*
-* @note C-Style signature:
-* u32 XEmacLite_NextReceiveAddr(XEmacLite *InstancePtr);
-*
-* This macro returns the address of the next receive buffer to read data from.
-* This is the expected receive buffer address if the driver is in sync.
-*
-*****************************************************************************/
-#define XEmacLite_NextReceiveAddr(InstancePtr) \
- ((InstancePtr)->EmacLiteConfig.BaseAddress + \
- (InstancePtr)->NextRxBufferToUse)
-
-/*****************************************************************************/
-/**
-*
-* This macro determines if the device is currently configured for MDIO.
-*
-* @param InstancePtr is the pointer to the instance of the
-* EmacLite driver.
-*
-* @return
-* - TRUE if the device is configured for MDIO.
-* - FALSE if the device is NOT configured for MDIO.
-*
-* @note C-Style signature:
-* int XEmacLite_IsMdioConfigured(XEmacLite *InstancePtr)
-*
-******************************************************************************/
-#define XEmacLite_IsMdioConfigured(InstancePtr) \
- ((InstancePtr)->EmacLiteConfig.MdioInclude == 1)
-
-/*****************************************************************************/
-/**
-*
-* This macro determines if the device is currently configured for internal
-* loopback.
-*
-* @param InstancePtr is the pointer to the instance of the
-* EmacLite driver.
-*
-* @return
-* - TRUE if the device is configured for internal loopback.
-* - FALSE if the device is NOT configured for internal loopback.
-*
-* @note C-Style signature:
-* int XEmacLite_IsLoopbackConfigured(XEmacLite *InstancePtr)
-*
-******************************************************************************/
-#define XEmacLite_IsLoopbackConfigured(InstancePtr) \
- ((InstancePtr)->EmacLiteConfig.Loopback == 1)
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions in xemaclite.c
- */
-int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
- XEmacLite_Config *EmacLiteConfigPtr,
- u32 EffectiveAddr);
-void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr);
-int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr);
-void XEmacLite_FlushReceive(XEmacLite *InstancePtr);
-
-int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount);
-u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr);
-
-int XEmacLite_PhyRead(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
- u16 *PhyDataPtr);
-int XEmacLite_PhyWrite(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
- u16 PhyData);
-
-void XEmacLite_EnableLoopBack(XEmacLite *InstancePtr);
-void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr);
-
-/*
- * Initialization functions in xemaclite_sinit.c
- */
-XEmacLite_Config *XEmacLite_LookupConfig(u16 DeviceId);
-int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId);
-
-/*
- * Interrupt driven functions in xemaclite_intr.c
- */
-int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr);
-void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr);
-
-void XEmacLite_InterruptHandler(void *InstancePtr);
-
-void XEmacLite_SetRecvHandler(XEmacLite *InstancePtr, void *CallBackRef,
- XEmacLite_Handler FuncPtr);
-void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef,
- XEmacLite_Handler FuncPtr);
-
-/*
- * Selftest function in xemaclite_selftest.c
- */
-int XEmacLite_SelfTest(XEmacLite *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Driver configuration\r
-*\r
-*******************************************************************/\r
-\r
-#include "xparameters.h"\r
-#include "xemaclite.h"\r
-\r
-/*\r
-* The configuration table for devices\r
-*/\r
-\r
-XEmacLite_Config XEmacLite_ConfigTable[] =\r
-{\r
- {\r
- XPAR_AXI_ETHERNETLITE_0_DEVICE_ID,\r
- XPAR_AXI_ETHERNETLITE_0_BASEADDR,\r
- XPAR_AXI_ETHERNETLITE_0_TX_PING_PONG,\r
- XPAR_AXI_ETHERNETLITE_0_RX_PING_PONG,\r
- XPAR_AXI_ETHERNETLITE_0_INCLUDE_MDIO,\r
- XPAR_AXI_ETHERNETLITE_0_INCLUDE_INTERNAL_LOOPBACK\r
- }\r
-};\r
-\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/******************************************************************************/
-/**
-* @file xemaclite_i.h
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.01a ecm 05/21/04 First release
-* 1.11a mta 03/21/07 Updated to new coding style
-* 1.13a sv 02/1/08 Added macros to Get/Set Tx/Rx status
-* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
-* The macros changed in this file are
-* XEmacLite_mGetTxActive changed to XEmacLite_GetTxActive,
-* XEmacLite_mSetTxActive changed to XEmacLite_SetTxActive.
-*
-* </pre>
-******************************************************************************/
-
-#ifndef XEMACLITE_I_H /* prevent circular inclusions */
-#define XEMACLITE_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xemaclite.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Get the TX active location to check status. This is used to check if
-* the TX buffer is currently active. There isn't any way in the hardware
-* to implement this but the register is fully populated so the driver can
-* set the bit in the send routine and the ISR can clear the bit when
-* the handler is complete. This mimics the correct operation of the hardware
-* if it was possible to do this in hardware.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return Contents of active bit in register.
-*
-* @note C-Style signature:
-* u32 XEmacLite_GetTxActive(u32 BaseAddress)
-*
-*****************************************************************************/
-#define XEmacLite_GetTxActive(BaseAddress) \
- (XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Set the TX active location to update status. This is used to set the bit
-* indicating which TX buffer is currently active. There isn't any way in the
-* hardware to implement this but the register is fully populated so the driver
-* can set the bit in the send routine and the ISR can clear the bit when
-* the handler is complete. This mimics the correct operation of the hardware
-* if it was possible to do this in hardware.
-*
-* @param BaseAddress is the base address of the device
-* @param Mask is the data to be written
-*
-* @return None
-*
-* @note C-Style signature:
-* void XEmacLite_SetTxActive(u32 BaseAddress, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacLite_SetTxActive(BaseAddress, Mask) \
- (XEmacLite_WriteReg((BaseAddress), XEL_TSR_OFFSET, (Mask)))
-
-/************************** Variable Definitions ****************************/
-
-extern XEmacLite_Config XEmacLite_ConfigTable[];
-
-/************************** Function Prototypes ******************************/
-
-void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount);
-void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount);
-
-void StubHandler(void *CallBackRef);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemaclite_intr.c
-*
-* Functions in this file are for the interrupt driven processing functionality.
-* See xemaclite.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.01a ecm 03/31/04 First release
-* 1.11a mta 03/21/07 Updated to new coding style
-* 2.01a ktn 07/20/09 Modified the XEmacLite_EnableInterrupts and
-* XEmacLite_DisableInterrupts functions to enable/disable
-* the interrupt in the Ping buffer as this is used to enable
-* the interrupts for both Ping and Pong Buffers.
-* The interrupt enable bit in the Pong buffer is not used by
-* the HW.
-* 3.00a ktn 10/22/09 Updated file to use the HAL Processor APIs/macros.
-* The macros have been renamed to remove _m from the name.
-*
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemaclite_i.h"
-#include "xil_io.h"
-#include "xemaclite.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-/*****************************************************************************/
-/**
-*
-* Enable the EmacLite Interrupts.
-*
-* This function must be called before other functions to send or receive data
-* in interrupt driven mode. The user should have connected the
-* interrupt handler of the driver to an interrupt source such as an interrupt
-* controller or the processor interrupt prior to this function being called.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance.
-*
-* @return
-* - XST_SUCCESS if the device interrupts were enabled
-* successfully.
-* - XST_NO_CALLBACK if the callbacks were not set.
-*
-* @note None.
-*
-******************************************************************************/
-int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr)
-{
- u32 Register;
- u32 BaseAddress;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
-
- /*
- * Verify that the handlers are in place.
- */
- if ((InstancePtr->RecvHandler == (XEmacLite_Handler) StubHandler) ||
- (InstancePtr->SendHandler == (XEmacLite_Handler) StubHandler)) {
- return XST_NO_CALLBACK;
- }
-
- /*
- * Enable the TX interrupts for both the buffers, the Interrupt Enable
- * is common for the both the buffers and is defined in the
- * Ping buffer.
- */
- Register = XEmacLite_GetTxStatus(BaseAddress);
- Register |= XEL_TSR_XMIT_IE_MASK;
- XEmacLite_SetTxStatus(BaseAddress, Register);
-
- /*
- * Enable the RX interrupts for both the buffers, the Interrupt Enable
- * is common for the both the buffers and is defined in the
- * Ping buffer.
- */
- Register = XEmacLite_GetRxStatus(BaseAddress);
- Register |= XEL_RSR_RECV_IE_MASK;
- XEmacLite_SetRxStatus(BaseAddress, Register);
-
- /*
- * Enable the global interrupt output.
- */
- XEmacLite_WriteReg(BaseAddress, XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupts from the device (the higher layer software is
-* responsible for disabling interrupts at the interrupt controller).
-*
-* To start using the device again, _EnableInterrupts must be called.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance .
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr)
-{
- u32 Register;
- u32 BaseAddress;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
-
- /*
- * Disable the global interrupt output.
- */
- XEmacLite_WriteReg(BaseAddress, XEL_GIER_OFFSET, 0);
-
- /*
- * Disable the TX interrupts for both the buffers, the Interrupt Enable
- * is common for the both the buffers and is defined in the
- * Ping buffer.
- */
- Register = XEmacLite_GetTxStatus(BaseAddress);
- Register &= ~XEL_TSR_XMIT_IE_MASK;
- XEmacLite_SetTxStatus(BaseAddress, Register);
-
- /*
- * Disable the RX interrupts for both the buffers, the Interrupt Enable
- * is common for the both the buffers and is defined in the
- * Ping buffer.
- */
- Register = XEmacLite_GetRxStatus(BaseAddress);
- Register &= ~XEL_RSR_RECV_IE_MASK;
- XEmacLite_SetRxStatus(BaseAddress, Register);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Interrupt handler for the EmacLite driver. It performs the following
-* processing:
-*
-* - Get the interrupt status from the registers to determine the source
-* of the interrupt.
-* - Call the appropriate handler based on the source of the interrupt.
-*
-* @param InstancePtr contains a pointer to the EmacLite device instance
-* for the interrupt.
-*
-* @return None.
-*
-* @note None.
-*
-*
-******************************************************************************/
-void XEmacLite_InterruptHandler(void *InstancePtr)
-{
-
- XEmacLite *EmacLitePtr;
- int TxCompleteIntr = FALSE;
- u32 BaseAddress;
- u32 TxStatus;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Convert the non-typed pointer to an EmacLite instance pointer
- * such that there is access to the device.
- */
- EmacLitePtr = (XEmacLite *) InstancePtr;
- BaseAddress = EmacLitePtr->EmacLiteConfig.BaseAddress;
-
- if ((XEmacLite_IsRxEmpty(BaseAddress) != TRUE) ||
- (XEmacLite_IsRxEmpty(BaseAddress +
- XEL_BUFFER_OFFSET) != TRUE)) {
- /*
- * Call the RX callback.
- */
- EmacLitePtr->RecvHandler(EmacLitePtr->RecvRef);
-
- }
-
- TxStatus = XEmacLite_GetTxStatus(BaseAddress);
- if (((TxStatus & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
- (TxStatus & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
-
- /*
- * Clear the Tx Active bit in the Tx Status Register.
- */
- TxStatus &= ~XEL_TSR_XMIT_ACTIVE_MASK;
- XEmacLite_SetTxStatus(BaseAddress, TxStatus);
-
- /*
- * Update the flag indicating that there was a Tx Interrupt.
- */
- TxCompleteIntr = TRUE;
-
- }
-
- TxStatus = XEmacLite_GetTxStatus(BaseAddress + XEL_BUFFER_OFFSET);
- if (((TxStatus & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
- (TxStatus & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
-
- /*
- * Clear the Tx Active bit in the Tx Status Register.
- */
- TxStatus &= ~XEL_TSR_XMIT_ACTIVE_MASK;
- XEmacLite_SetTxStatus(BaseAddress + XEL_BUFFER_OFFSET,
- TxStatus);
- /*
- * Update the flag indicating that there was a Tx Interrupt.
- */
- TxCompleteIntr = TRUE;
- }
-
- /*
- * If there was a TX interrupt, call the callback.
- */
- if (TxCompleteIntr == TRUE) {
-
- /*
- * Call the TX callback.
- */
- EmacLitePtr->SendHandler(EmacLitePtr->SendRef);
-
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the callback function for handling received frames in interrupt mode.
-* The upper layer software should call this function during initialization.
-* The callback is called when a frame is received. The callback function
-* should communicate the data to a thread such that the processing is not
-* performed in an interrupt context.
-*
-* The callback is invoked by the driver within interrupt context, so it needs
-* to do its job quickly. If there are other potentially slow operations
-* within the callback, these should be done at task-level.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance..
-* @param CallBackRef is a reference pointer to be passed back to the
-* application in the callback. This helps the application
-* correlate the callback to a particular driver.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XEmacLite_SetRecvHandler(XEmacLite *InstancePtr, void *CallBackRef,
- XEmacLite_Handler FuncPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->RecvHandler = FuncPtr;
- InstancePtr->RecvRef = CallBackRef;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Sets the callback function for handling transmitted frames in interrupt mode.
-* The upper layer software should call this function during initialization.
-* The callback is called when a frame is transmitted. The callback function
-* should communicate the data to a thread such that the processing is not
-* performed in an interrupt context.
-*
-* The callback is invoked by the driver within interrupt context, so it needs
-* to do its job quickly. If there are other potentially slow operations
-* within the callback, these should be done at task-level.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance.
-* @param CallBackRef is a reference pointer to be passed back to the
-* application in the callback. This helps the application
-* correlate the callback to a particular driver.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef,
- XEmacLite_Handler FuncPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->SendHandler = FuncPtr;
- InstancePtr->SendRef = CallBackRef;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemaclite_l.c
-*
-* This file contains the minimal, polled functions to send and receive Ethernet
-* frames.
-*
-* Refer to xemaclite.h for more details.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 06/01/02 First release
-* 1.01a ecm 03/31/04 Additional functionality and the _AlignedRead and
-* _AlignedWrite functions.
-* 1.11a mta 03/21/07 Updated to new coding style
-* 2.01a ktn 07/20/09 Updated the XEmacLite_AlignedWrite and
-* XEmacLite_AlignedRead functions to use volatile
-* variables so that they are not optimized.
-* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xemaclite_l.h"
-#include "xemaclite_i.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount);
-void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Send an Ethernet frame. The size is the total frame size, including header.
-* This function blocks waiting for the frame to be transmitted.
-*
-* @param BaseAddress is the base address of the device
-* @param FramePtr is a pointer to frame
-* @param ByteCount is the size, in bytes, of the frame
-*
-* @return None.
-*
-* @note
-*
-* This function call is blocking in nature, i.e. it will wait until the
-* frame is transmitted. This function can hang and not exit if the
-* hardware is not configured properly.
-*
-* If the ping buffer is the destination of the data, the argument should be
-* DeviceAddress + XEL_TXBUFF_OFFSET.
-* If the pong buffer is the destination of the data, the argument should be
-* DeviceAddress + XEL_TXBUFF_OFFSET + XEL_BUFFER_OFFSET.
-* The function does not take the different buffers into consideration.
-*
-******************************************************************************/
-void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount)
-{
- u32 Register;
-
- /*
- * Write data to the EmacLite
- */
- XEmacLite_AlignedWrite(FramePtr, (u32 *) (BaseAddress), ByteCount);
-
- /*
- * The frame is in the buffer, now send it
- */
- XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
- (ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
- XEL_TPLR_LENGTH_MASK_LO)));
-
-
- Register = XEmacLite_GetTxStatus(BaseAddress);
- XEmacLite_SetTxStatus(BaseAddress, Register | XEL_TSR_XMIT_BUSY_MASK);
-
- /*
- * Loop on the status waiting for the transmit to be complete.
- */
- while (!XEmacLite_IsTxDone(BaseAddress));
-
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Receive a frame. Wait for a frame to arrive.
-*
-* @param BaseAddress is the base address of the device
-* @param FramePtr is a pointer to a buffer where the frame will
-* be stored.
-*
-* @return
-*
-* The type/length field of the frame received. When the type/length field
-* contains the type , XEL_MAX_FRAME_SIZE bytes will be copied out of the
-* buffer and it is up to the higher layers to sort out the frame.
-*
-* @note
-*
-* This function call is blocking in nature, i.e. it will wait until a
-* frame arrives.
-*
-* If the ping buffer is the source of the data, the argument should be
-* DeviceAddress + XEL_RXBUFF_OFFSET.
-* If the pong buffer is the source of the data, the argument should be
-* DeviceAddress + XEL_RXBUFF_OFFSET + XEL_BUFFER_OFFSET.
-* The function does not take the different buffers into consideration.
-*
-******************************************************************************/
-u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr)
-{
- u16 LengthType;
- u16 Length;
- u32 Register;
-
- /*
- * Wait for a frame to arrive - this is a blocking call
- */
- while (XEmacLite_IsRxEmpty(BaseAddress));
-
- /*
- * Get the length of the frame that arrived, only 32-bit reads are
- * allowed LengthType is in the upper half of the 32-bit word.
- */
- Register = XEmacLite_ReadReg(BaseAddress, XEL_RPLR_OFFSET);
- LengthType = (u16) ((Register >> 16) &
- (XEL_RPLR_LENGTH_MASK_HI |
- XEL_RPLR_LENGTH_MASK_LO));
-
- /*
- * Check if length is valid
- */
- if (LengthType > XEL_MAX_FRAME_SIZE) {
- /*
- * Field contain type, use max frame size and
- * let user parse it
- */
- Length = XEL_MAX_FRAME_SIZE;
- }
- else {
- /*
- * Use the length in the frame, plus the header and trailer
- */
- Length = LengthType + XEL_HEADER_SIZE + XEL_FCS_SIZE;
- }
-
- /*
- * Read each byte from the EmacLite
- */
- XEmacLite_AlignedRead((u32 *) (BaseAddress + XEL_RXBUFF_OFFSET),
- FramePtr, Length);
-
- /*
- * Acknowledge the frame
- */
- Register = XEmacLite_GetRxStatus(BaseAddress);
- Register &= ~XEL_RSR_RECV_DONE_MASK;
- XEmacLite_SetRxStatus(BaseAddress, Register);
-
- return LengthType;
-}
-
-/******************************************************************************/
-/**
-*
-* This function aligns the incoming data and writes it out to a 32-bit
-* aligned destination address range.
-*
-* @param SrcPtr is a pointer to incoming data of any alignment.
-* @param DestPtr is a pointer to outgoing data of 32-bit alignment.
-* @param ByteCount is the number of bytes to write.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XEmacLite_AlignedWrite(void *SrcPtr, u32 *DestPtr, unsigned ByteCount)
-{
- unsigned Index;
- unsigned Length = ByteCount;
- volatile u32 AlignBuffer;
- volatile u32 *To32Ptr;
- u32 *From32Ptr;
- volatile u16 *To16Ptr;
- u16 *From16Ptr;
- volatile u8 *To8Ptr;
- u8 *From8Ptr;
-
- To32Ptr = DestPtr;
-
- if ((((u32) SrcPtr) & 0x00000003) == 0) {
-
- /*
- * Word aligned buffer, no correction needed.
- */
- From32Ptr = (u32 *) SrcPtr;
-
- while (Length > 3) {
- /*
- * Output each word destination.
- */
- *To32Ptr++ = *From32Ptr++;
-
- /*
- * Adjust length accordingly
- */
- Length -= 4;
- }
-
- /*
- * Set up to output the remaining data, zero the temp buffer
- first.
- */
- AlignBuffer = 0;
- To8Ptr = (u8 *) &AlignBuffer;
- From8Ptr = (u8 *) From32Ptr;
-
- }
- else if ((((u32) SrcPtr) & 0x00000001) != 0) {
- /*
- * Byte aligned buffer, correct.
- */
- AlignBuffer = 0;
- To8Ptr = (u8 *) &AlignBuffer;
- From8Ptr = (u8 *) SrcPtr;
-
- while (Length > 3) {
- /*
- * Copy each byte into the temporary buffer.
- */
- for (Index = 0; Index < 4; Index++) {
- *To8Ptr++ = *From8Ptr++;
- }
-
- /*
- * Output the buffer
- */
- *To32Ptr++ = AlignBuffer;
-
- /*.
- * Reset the temporary buffer pointer and adjust length.
- */
- To8Ptr = (u8 *) &AlignBuffer;
- Length -= 4;
- }
-
- /*
- * Set up to output the remaining data, zero the temp buffer
- * first.
- */
- AlignBuffer = 0;
- To8Ptr = (u8 *) &AlignBuffer;
-
- }
- else {
- /*
- * Half-Word aligned buffer, correct.
- */
- AlignBuffer = 0;
-
- /*
- * This is a funny looking cast. The new gcc, version 3.3.x has
- * a strict cast check for 16 bit pointers, aka short pointers.
- * The following warning is issued if the initial 'void *' cast
- * is not used:
- * 'dereferencing type-punned pointer will break strict-aliasing
- * rules'
- */
-
- To16Ptr = (u16 *) ((void *) &AlignBuffer);
- From16Ptr = (u16 *) SrcPtr;
-
- while (Length > 3) {
- /*
- * Copy each half word into the temporary buffer.
- */
- for (Index = 0; Index < 2; Index++) {
- *To16Ptr++ = *From16Ptr++;
- }
-
- /*
- * Output the buffer.
- */
- *To32Ptr++ = AlignBuffer;
-
- /*
- * Reset the temporary buffer pointer and adjust length.
- */
-
- /*
- * This is a funny looking cast. The new gcc, version
- * 3.3.x has a strict cast check for 16 bit pointers,
- * aka short pointers. The following warning is issued
- * if the initial 'void *' cast is not used:
- * 'dereferencing type-punned pointer will break
- * strict-aliasing rules'
- */
- To16Ptr = (u16 *) ((void *) &AlignBuffer);
- Length -= 4;
- }
-
- /*
- * Set up to output the remaining data, zero the temp buffer
- * first.
- */
- AlignBuffer = 0;
- To8Ptr = (u8 *) &AlignBuffer;
- From8Ptr = (u8 *) From16Ptr;
- }
-
- /*
- * Output the remaining data, zero the temp buffer first.
- */
- for (Index = 0; Index < Length; Index++) {
- *To8Ptr++ = *From8Ptr++;
- }
-
- *To32Ptr++ = AlignBuffer;
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function reads from a 32-bit aligned source address range and aligns
-* the writes to the provided destination pointer alignment.
-*
-* @param SrcPtr is a pointer to incoming data of 32-bit alignment.
-* @param DestPtr is a pointer to outgoing data of any alignment.
-* @param ByteCount is the number of bytes to read.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XEmacLite_AlignedRead(u32 *SrcPtr, void *DestPtr, unsigned ByteCount)
-{
- unsigned Index;
- unsigned Length = ByteCount;
- volatile u32 AlignBuffer;
- u32 *To32Ptr;
- volatile u32 *From32Ptr;
- u16 *To16Ptr;
- volatile u16 *From16Ptr;
- u8 *To8Ptr;
- volatile u8 *From8Ptr;
-
- From32Ptr = (u32 *) SrcPtr;
-
- if ((((u32) DestPtr) & 0x00000003) == 0) {
-
- /*
- * Word aligned buffer, no correction needed.
- */
- To32Ptr = (u32 *) DestPtr;
-
- while (Length > 3) {
- /*
- * Output each word.
- */
- *To32Ptr++ = *From32Ptr++;
-
- /*
- * Adjust length accordingly.
- */
- Length -= 4;
- }
-
- /*
- * Set up to read the remaining data.
- */
- To8Ptr = (u8 *) To32Ptr;
-
- }
- else if ((((u32) DestPtr) & 0x00000001) != 0) {
- /*
- * Byte aligned buffer, correct.
- */
- To8Ptr = (u8 *) DestPtr;
-
- while (Length > 3) {
- /*
- * Copy each word into the temporary buffer.
- */
- AlignBuffer = *From32Ptr++;
- From8Ptr = (u8 *) &AlignBuffer;
-
- /*
- * Write data to destination.
- */
- for (Index = 0; Index < 4; Index++) {
- *To8Ptr++ = *From8Ptr++;
- }
-
- /*
- * Adjust length
- */
- Length -= 4;
- }
-
- }
- else {
- /*
- * Half-Word aligned buffer, correct.
- */
- To16Ptr = (u16 *) DestPtr;
-
- while (Length > 3) {
- /*
- * Copy each word into the temporary buffer.
- */
- AlignBuffer = *From32Ptr++;
-
- /*
- * This is a funny looking cast. The new gcc, version
- * 3.3.x has a strict cast check for 16 bit pointers,
- * aka short pointers. The following warning is issued
- * if the initial 'void *' cast is not used:
- * 'dereferencing type-punned pointer will break
- * strict-aliasing rules'
- */
- From16Ptr = (u16 *) ((void *) &AlignBuffer);
-
- /*
- * Write data to destination.
- */
- for (Index = 0; Index < 2; Index++) {
- *To16Ptr++ = *From16Ptr++;
- }
-
- /*
- * Adjust length.
- */
- Length -= 4;
- }
-
- /*
- * Set up to read the remaining data.
- */
- To8Ptr = (u8 *) To16Ptr;
- }
-
- /*
- * Read the remaining data.
- */
- AlignBuffer = *From32Ptr++;
- From8Ptr = (u8 *) &AlignBuffer;
-
- for (Index = 0; Index < Length; Index++) {
- *To8Ptr++ = *From8Ptr++;
- }
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemaclite_l.h
-*
-* This header file contains identifiers and basic driver functions and macros
-* that can be used to access the Xilinx Ethernet Lite 10/100 MAC (EmacLite).
-*
-* Refer to xemaclite.h for more details.
-*
-* @note
-*
-* The functions and macros in this file assume that the proper device address is
-* provided in the argument. If the ping buffer is the source or destination,
-* the argument should be DeviceAddress + XEL_(T/R)XBUFF_OFFSET. If the pong
-* buffer is the source or destination, the argument should be
-* DeviceAddress + XEL_(T/R)XBUFF_OFFSET + XEL_BUFFER_OFFSET. The driver does
-* not take the different buffers into consideration.
-* For more details on the ping/pong buffer configuration please refer to the
-* Ethernet Lite 10/100 Media Access Controller hardware specification.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 06/01/02 First release
-* 1.01a ecm 03/31/04 Additional functionality and the _AlignedRead and
-* AlignedWrite functions.
-* Moved the bulk of description to xemaclite.h
-* 1.11a mta 03/21/07 Updated to new coding style
-* 2.00a ktn 02/16/09 Added support for MDIO and internal loop back
-* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
-* The macros changed in this file are
-* XEmacLite_mReadReg changed to XEmacLite_mReadReg,
-* XEmacLite_mWriteReg changed to XEmacLite_mWriteReg,
-* XEmacLite_mGetTxStatus changed to XEmacLite_GetTxStatus,
-* XEmacLite_mSetTxStatus changed to XEmacLite_SetTxStatus,
-* XEmacLite_mGetRxStatus changed to XEmacLite_GetRxStatus,
-* XEmacLite_mSetRxStatus changed to XEmacLite_SetRxStatus,
-* XEmacLite_mIsTxDone changed to XEmacLite_IsTxDone and
-* XEmacLite_mIsRxEmpty changed to XEmacLite_IsRxEmpty.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMAC_LITE_L_H /* prevent circular inclusions */
-#define XEMAC_LITE_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-/**
- * Register offsets for the Ethernet MAC.
- */
-#define XEL_TXBUFF_OFFSET (0x00000000) /**< Transmit Buffer */
-#define XEL_MDIOADDR_OFFSET (XEL_TXBUFF_OFFSET + 0x07E4)/**< MDIO Address offset
- register */
-#define XEL_MDIOWR_OFFSET (XEL_TXBUFF_OFFSET + 0x07E8) /**< MDIO write data
- register offset */
-#define XEL_MDIORD_OFFSET (XEL_TXBUFF_OFFSET + 0x07EC) /**< MDIO read data
- register offset*/
-#define XEL_MDIOCNTR_OFFSET (XEL_TXBUFF_OFFSET + 0x07F0)/**< MDIO Control
- Register offset */
-#define XEL_GIER_OFFSET (XEL_TXBUFF_OFFSET + 0x07F8) /**< Offset for the GIE
- Register */
-#define XEL_TSR_OFFSET (XEL_TXBUFF_OFFSET + 0x07FC) /**< Tx status */
-#define XEL_TPLR_OFFSET (XEL_TXBUFF_OFFSET + 0x07F4) /**< Tx packet length */
-
-#define XEL_RXBUFF_OFFSET (0x00001000) /**< Receive Buffer */
-#define XEL_RSR_OFFSET (XEL_RXBUFF_OFFSET + 0x07FC) /**< Rx status */
-#define XEL_RPLR_OFFSET (XEL_RXBUFF_OFFSET + 0x0C) /**< Rx packet length */
-
-#define XEL_MAC_HI_OFFSET (XEL_TXBUFF_OFFSET + 0x14) /**< MAC address hi
- offset */
-#define XEL_MAC_LO_OFFSET (XEL_TXBUFF_OFFSET) /**< MAC address lo
- offset */
-
-#define XEL_BUFFER_OFFSET (0x00000800) /**< Next buffer's
- offset same for
- both TX and RX */
-/**
- * MDIO Address/Write Data/Read Data Register Bit Masks
- */
-#define XEL_MDIO_ADDRESS_MASK 0x00003E0 /**< PHY Address mask */
-#define XEL_MDIO_ADDRESS_SHIFT 0x5 /**< PHY Address shift*/
-#define XEL_MDIO_OP_MASK 0x00000400 /**< PHY read access */
-
-/**
- * MDIO Control Register Bit Masks
- */
-#define XEL_MDIOCNTR_STATUS_MASK 0x00000001 /**< MDIO transfer in
- Progress */
-#define XEL_MDIOCNTR_ENABLE_MASK 0x00000008 /**< MDIO Enable */
-
-/**
- * Global Interrupt Enable Register (GIER) Bit Masks
- */
-#define XEL_GIER_GIE_MASK 0x80000000 /**< Global Enable */
-
-/**
- * Transmit Status Register (TSR) Bit Masks
- */
-#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /**< Xmit complete */
-#define XEL_TSR_PROGRAM_MASK 0x00000002 /**< Program the MAC
- address */
-#define XEL_TSR_XMIT_IE_MASK 0x00000008 /**< Xmit interrupt
- enable bit */
-#define XEL_TSR_LOOPBACK_MASK 0x00000010 /**< Loop back enable
- bit */
-#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /**< Buffer is active,
- SW bit only. This
- is not documented
- in the HW spec */
-
-/**
- * define for programming the MAC address into the EmacLite
- */
-#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
-
-/**
- * Receive Status Register (RSR)
- */
-#define XEL_RSR_RECV_DONE_MASK 0x00000001 /**< Recv complete */
-#define XEL_RSR_RECV_IE_MASK 0x00000008 /**< Recv interrupt
- enable bit */
-
-/**
- * Transmit Packet Length Register (TPLR)
- */
-#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00 /**< Transmit packet length
- upper byte */
-#define XEL_TPLR_LENGTH_MASK_LO 0x000000FF /**< Transmit packet length
- lower byte */
-
-/**
- * Receive Packet Length Register (RPLR)
- */
-#define XEL_RPLR_LENGTH_MASK_HI 0x0000FF00 /**< Receive packet length
- upper byte */
-#define XEL_RPLR_LENGTH_MASK_LO 0x000000FF /**< Receive packet length
- lower byte */
-
-#define XEL_HEADER_SIZE 14 /**< Size of header in bytes */
-#define XEL_MTU_SIZE 1500 /**< Max size of data in frame */
-#define XEL_FCS_SIZE 4 /**< Size of CRC */
-
-#define XEL_HEADER_OFFSET 12 /**< Offset to length field */
-#define XEL_HEADER_SHIFT 16 /**< Right shift value to align
- length */
-
-
-#define XEL_MAX_FRAME_SIZE (XEL_HEADER_SIZE+XEL_MTU_SIZE+ XEL_FCS_SIZE) /**< Max
- length of Rx frame used if
- length/type field
- contains the type (> 1500) */
-
-#define XEL_MAX_TX_FRAME_SIZE (XEL_HEADER_SIZE + XEL_MTU_SIZE) /**< Max
- length of Tx frame */
-
-
-#define XEL_MAC_ADDR_SIZE 6 /**< length of MAC address */
-
-
-/*
- * General Ethernet Definitions
- */
-#define XEL_ETHER_PROTO_TYPE_IP 0x0800 /**< IP Protocol */
-#define XEL_ETHER_PROTO_TYPE_ARP 0x0806 /**< ARP Protocol */
-#define XEL_ETHER_PROTO_TYPE_VLAN 0x8100 /**< VLAN Tagged */
-#define XEL_ARP_PACKET_SIZE 28 /**< Max ARP packet size */
-#define XEL_HEADER_IP_LENGTH_OFFSET 16 /**< IP Length Offset */
-#define XEL_VLAN_TAG_SIZE 4 /**< VLAN Tag Size */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XEmacLite_In32 Xil_In32
-#define XEmacLite_Out32 Xil_Out32
-
-/****************************************************************************/
-/**
-*
-* Read from the specified EmacLite device register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to select the specific register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XEmacLite_ReadReg(u32 BaseAddress, u32 RegOffset);
-*
-******************************************************************************/
-#define XEmacLite_ReadReg(BaseAddress, RegOffset) \
- XEmacLite_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-*
-* Write to the specified EmacLite device register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to select the specific register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XEmacLite_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 RegisterValue);
-******************************************************************************/
-#define XEmacLite_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XEmacLite_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-
-/****************************************************************************/
-/**
-*
-* Get the Tx Status Register Contents.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return The contents of the Tx Status Register.
-*
-* @note C-Style signature:
-* u32 XEmacLite_GetTxStatus(u32 BaseAddress)
-*
-*****************************************************************************/
-#define XEmacLite_GetTxStatus(BaseAddress) \
- (XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET))
-
-
-/****************************************************************************/
-/**
-*
-* Set the Tx Status Register Contents.
-*
-* @param BaseAddress is the base address of the device
-* @param Data is the value to be written to the Register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* u32 XEmacLite_SetTxStatus(u32 BaseAddress, u32 Data)
-*
-*****************************************************************************/
-#define XEmacLite_SetTxStatus(BaseAddress, Data) \
- (XEmacLite_WriteReg((BaseAddress), XEL_TSR_OFFSET, (Data)))
-
-
-/****************************************************************************/
-/**
-*
-* Get the Rx Status Register Contents.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return The contents of the Rx Status Register.
-*
-* @note C-Style signature:
-* u32 XEmacLite_GetRxStatus(u32 BaseAddress)
-*
-*****************************************************************************/
-#define XEmacLite_GetRxStatus(BaseAddress) \
- (XEmacLite_ReadReg((BaseAddress), XEL_RSR_OFFSET))
-
-
-/****************************************************************************/
-/**
-*
-* Set the Rx Status Register Contents.
-*
-* @param BaseAddress is the base address of the device
-* @param Data is the value to be written to the Register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* u32 XEmacLite_SetRxStatus(u32 BaseAddress, u32 Data)
-*
-*****************************************************************************/
-#define XEmacLite_SetRxStatus(BaseAddress, Data) \
- (XEmacLite_WriteReg((BaseAddress), XEL_RSR_OFFSET, (Data)))
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the transmission is complete.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return TRUE if it is done, or FALSE if it is not.
-*
-* @note C-Style signature:
-* int XEmacLite_IsTxDone(u32 BaseAddress)
-*
-*****************************************************************************/
-#define XEmacLite_IsTxDone(BaseAddress) \
- ((XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET) & \
- XEL_TSR_XMIT_BUSY_MASK) != XEL_TSR_XMIT_BUSY_MASK)
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the receive is empty.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return TRUE if it is empty, or FALSE if it is not.
-*
-* @note C-Style signature:
-* int XEmacLite_IsRxEmpty(u32 BaseAddress)
-*
-*****************************************************************************/
-#define XEmacLite_IsRxEmpty(BaseAddress) \
- ((XEmacLite_ReadReg((BaseAddress), XEL_RSR_OFFSET) & \
- XEL_RSR_RECV_DONE_MASK) != XEL_RSR_RECV_DONE_MASK)
-
-/************************** Function Prototypes ******************************/
-
-void XEmacLite_SendFrame(u32 BaseAddress, u8 *FramePtr, unsigned ByteCount);
-u16 XEmacLite_RecvFrame(u32 BaseAddress, u8 *FramePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemaclite_selftest.c
-*
-* Function(s) in this file are the required functions for the EMAC Lite
-* driver sefftest for the hardware.
-* See xemaclite.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.01a ecm 01/31/04 First release
-* 1.11a mta 03/21/07 Updated to new coding style
-* 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros.
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-#include "xemaclite.h"
-#include "xemaclite_i.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Performs a SelfTest on the EmacLite device as follows:
-* - Writes to the mandatory TX buffer and reads back to verify.
-* - If configured, writes to the secondary TX buffer and reads back to verify.
-* - Writes to the mandatory RX buffer and reads back to verify.
-* - If configured, writes to the secondary RX buffer and reads back to verify.
-*
-*
-* @param InstancePtr is a pointer to the XEmacLite instance .
-*
-* @return
-* - XST_SUCCESS if the device Passed the Self Test.
-* - XST_FAILURE if any of the data read backs fail.
-*
-* @note None.
-*
-******************************************************************************/
-int XEmacLite_SelfTest(XEmacLite * InstancePtr)
-{
- u32 BaseAddress;
- u8 Index;
- u8 TestString[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
- u8 ReturnString[4] = { 0x0, 0x0, 0x0, 0x0 };
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Determine the TX buffer address
- */
- BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress +
- XEL_TXBUFF_OFFSET;
-
- /*
- * Write the TestString to the TX buffer in EMAC Lite then
- * back from the EMAC Lite and verify
- */
- XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
- sizeof(TestString));
- XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
- sizeof(ReturnString));
-
- for (Index = 0; Index < 4; Index++) {
-
- if (ReturnString[Index] != TestString[Index]) {
- return XST_FAILURE;
- }
-
- /*
- * Zero the return string for the next test
- */
- ReturnString[Index] = 0;
- }
-
- /*
- * If the second buffer is configured, test it also
- */
- if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
- BaseAddress += XEL_BUFFER_OFFSET;
- /*
- * Write the TestString to the optional TX buffer in EMAC Lite
- * then back from the EMAC Lite and verify
- */
- XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
- sizeof(TestString));
- XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
- sizeof(ReturnString));
-
- for (Index = 0; Index < 4; Index++) {
-
- if (ReturnString[Index] != TestString[Index]) {
- return XST_FAILURE;
- }
-
- /*
- * Zero the return string for the next test
- */
- ReturnString[Index] = 0;
- }
- }
-
- /*
- * Determine the RX buffer address
- */
- BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress +
- XEL_RXBUFF_OFFSET;
-
- /*
- * Write the TestString to the RX buffer in EMAC Lite then
- * back from the EMAC Lite and verify
- */
- XEmacLite_AlignedWrite(TestString, (u32 *) (BaseAddress),
- sizeof(TestString));
- XEmacLite_AlignedRead((u32 *) (BaseAddress), ReturnString,
- sizeof(ReturnString));
-
- for (Index = 0; Index < 4; Index++) {
-
- if (ReturnString[Index] != TestString[Index]) {
- return XST_FAILURE;
- }
-
- /*
- * Zero the return string for the next test
- */
- ReturnString[Index] = 0;
- }
-
- /*
- * If the second buffer is configured, test it also
- */
- if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
- BaseAddress += XEL_BUFFER_OFFSET;
- /*
- * Write the TestString to the optional RX buffer in EMAC Lite
- * then back from the EMAC Lite and verify
- */
- XEmacLite_AlignedWrite(TestString, (u32 *) BaseAddress,
- sizeof(TestString));
- XEmacLite_AlignedRead((u32 *) BaseAddress, ReturnString,
- sizeof(ReturnString));
-
- for (Index = 0; Index < 4; Index++) {
-
- if (ReturnString[Index] != TestString[Index]) {
- return XST_FAILURE;
- }
-
- /*
- * Zero the return string for the next test
- */
- ReturnString[Index] = 0;
- }
- }
-
- return XST_SUCCESS;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemaclite_sinit.c
-*
-* This file contains the implementation of the XEmacLite driver's static
-* initialization functionality.
-*
-* @note None.
-*
-* <pre>
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.12a sv 11/28/07 First release
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xemaclite.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XEmacLite_Config XEmacLite_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* Lookup the device configuration based on the unique device ID. The table
-* XEmacLite_ConfigTable contains the configuration info for each device in the
-* system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XEmacLite_Config *XEmacLite_LookupConfig(u16 DeviceId)
-{
- XEmacLite_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0; Index < XPAR_XEMACLITE_NUM_INSTANCES; Index++) {
- if (XEmacLite_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XEmacLite_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Initialize a specific XEmacLite instance/driver. The initialization entails:
-* - Initialize fields of the XEmacLite instance structure.
-*
-* The driver defaults to polled mode operation.
-*
-* @param InstancePtr is a pointer to the XEmacLite instance.
-* @param DeviceId is the unique id of the device controlled by this
-* XEmacLite instance. Passing in a device id associates the
-* generic XEmacLite instance to a specific device, as chosen by
-* the caller or application developer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_NOT_FOUND/XST_FAILURE if device configuration
-* information was not found for a device with the supplied
-* device ID.
-*
-* @note None
-*
-******************************************************************************/
-int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId)
-{
- int Status;
- XEmacLite_Config *EmacLiteConfigPtr;/* Pointer to Configuration data. */
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Lookup the device configuration in the configuration table. Use this
- * configuration info down below when initializing this driver.
- */
- EmacLiteConfigPtr = XEmacLite_LookupConfig(DeviceId);
- if (EmacLiteConfigPtr == NULL) {
- return XST_DEVICE_NOT_FOUND;
- }
-
- Status = XEmacLite_CfgInitialize(InstancePtr,
- EmacLiteConfigPtr,
- EmacLiteConfigPtr->BaseAddress);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
--- /dev/null
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling emaclite"
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemaclite.c
+* @addtogroup emaclite_v4_1
+* @{
+*
+* Functions in this file are the minimum required functions for the EmacLite
+* driver. See xemaclite.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.01a ecm 01/31/04 First release
+* 1.11a mta 03/21/07 Updated to new coding style
+* 1.11a ecm 05/18/07 Updated the TxBufferAvailable routine to look at both
+* the active and busy bits
+* 1.13a sv 02/1/08 Updated the TxBufferAvailable routine to return
+* busy status properly
+* 2.00a ktn 02/16/09 Added support for MDIO
+* 2.01a ktn 07/20/09 Modified XEmacLite_Send function to use Ping buffers
+* Interrupt enable bit since this alone is used to enable
+* the interrupts for both Ping and Pong Buffers.
+* 3.00a ktn 10/22/09 Updated driver to use the HAL APIs/macros.
+* The macros have been renamed to remove _m from the name.
+* 3.01a ktn 07/08/10 The macro XEmacLite_GetReceiveDataLength is changed to
+* a static function.
+* Updated the XEmacLite_GetReceiveDataLength and
+* XEmacLite_Recv functions to support little endian
+* MicroBlaze.
+* 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for
+* CR617290
+* 3.04a srt 04/13/13 Removed warnings (CR 705000).
+* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototypes of XEmacLite_GetReceiveDataLength,
+* XEmacLite_CfgInitialize API's.
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+#include "xenv.h"
+#include "xemaclite.h"
+#include "xemaclite_i.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+static u16 XEmacLite_GetReceiveDataLength(UINTPTR BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Initialize a specific XEmacLite instance/driver. The initialization entails:
+* - Initialize fields of the XEmacLite instance structure.
+*
+* The driver defaults to polled mode operation.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance.
+* @param EmacLiteConfigPtr points to the XEmacLite device configuration
+* structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address is passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+*
+* @note The initialization of the PHY device is not done in this
+* function. The user needs to use XEmacLite_PhyRead and
+* XEmacLite_PhyWrite functions to access the PHY device.
+*
+******************************************************************************/
+int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
+ XEmacLite_Config *EmacLiteConfigPtr,
+ UINTPTR EffectiveAddr)
+{
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(EmacLiteConfigPtr != NULL);
+
+ /*
+ * Zero the provided instance memory.
+ */
+ memset(InstancePtr, 0, sizeof(XEmacLite));
+
+ /*
+ * Set some default values for instance data, don't indicate the device
+ * is ready to use until everything has been initialized successfully.
+ */
+ InstancePtr->EmacLiteConfig.BaseAddress = EffectiveAddr;
+ InstancePtr->EmacLiteConfig.DeviceId = EmacLiteConfigPtr->DeviceId;
+ InstancePtr->EmacLiteConfig.TxPingPong = EmacLiteConfigPtr->TxPingPong;
+ InstancePtr->EmacLiteConfig.RxPingPong = EmacLiteConfigPtr->RxPingPong;
+ InstancePtr->EmacLiteConfig.MdioInclude = EmacLiteConfigPtr->MdioInclude;
+ InstancePtr->EmacLiteConfig.Loopback = EmacLiteConfigPtr->Loopback;
+
+ InstancePtr->NextTxBufferToUse = 0x0;
+ InstancePtr->NextRxBufferToUse = 0x0;
+ InstancePtr->RecvHandler = (XEmacLite_Handler) StubHandler;
+ InstancePtr->SendHandler = (XEmacLite_Handler) StubHandler;
+
+ /*
+ * Clear the TX CSR's in case this is a restart.
+ */
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_TSR_OFFSET, 0);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_BUFFER_OFFSET + XEL_TSR_OFFSET, 0);
+
+ /*
+ * Since there were no failures, indicate the device is ready to use.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Send an Ethernet frame. The ByteCount is the total frame size, including
+* header.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance.
+* @param FramePtr is a pointer to frame. For optimal performance, a
+* 32-bit aligned buffer should be used but it is not required, the
+* function will align the data if necessary.
+* @param ByteCount is the size, in bytes, of the frame
+*
+* @return
+* - XST_SUCCESS if data was transmitted.
+* - XST_FAILURE if buffer(s) was (were) full and no valid data was
+* transmitted.
+*
+* @note
+*
+* This function call is not blocking in nature, i.e. it will not wait until the
+* frame is transmitted.
+*
+******************************************************************************/
+int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount)
+{
+ u32 Register;
+ UINTPTR BaseAddress;
+ UINTPTR EmacBaseAddress;
+ u32 IntrEnableStatus;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Determine the expected TX buffer address.
+ */
+ BaseAddress = XEmacLite_NextTransmitAddr(InstancePtr);
+ EmacBaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
+
+ /*
+ * Check the Length if it is too large, truncate it.
+ * The maximum Tx packet size is
+ * Ethernet header (14 Bytes) + Maximum MTU (1500 bytes).
+ */
+ if (ByteCount > XEL_MAX_TX_FRAME_SIZE) {
+
+ ByteCount = XEL_MAX_TX_FRAME_SIZE;
+ }
+
+ /*
+ * Determine if the expected buffer address is empty.
+ */
+ Register = XEmacLite_GetTxStatus(BaseAddress);
+
+ /*
+ * If the expected buffer is available, fill it with the provided data
+ * Align if necessary.
+ */
+ if ((Register & (XEL_TSR_XMIT_BUSY_MASK |
+ XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
+
+ /*
+ * Switch to next buffer if configured.
+ */
+ if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
+ InstancePtr->NextTxBufferToUse ^= XEL_BUFFER_OFFSET;
+ }
+
+ /*
+ * Write the frame to the buffer.
+ */
+ XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) BaseAddress,
+ ByteCount);
+
+
+ /*
+ * The frame is in the buffer, now send it.
+ */
+ XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
+ (ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
+ XEL_TPLR_LENGTH_MASK_LO)));
+
+ /*
+ * Update the Tx Status Register to indicate that there is a
+ * frame to send.
+ * If the interrupt enable bit of Ping buffer(since this
+ * controls both the buffers) is enabled then set the
+ * XEL_TSR_XMIT_ACTIVE_MASK flag which is used by the interrupt
+ * handler to call the callback function provided by the user
+ * to indicate that the frame has been transmitted.
+ */
+ Register = XEmacLite_GetTxStatus(BaseAddress);
+ Register |= XEL_TSR_XMIT_BUSY_MASK;
+ IntrEnableStatus = XEmacLite_GetTxStatus(EmacBaseAddress);
+ if ((IntrEnableStatus & XEL_TSR_XMIT_IE_MASK) != 0) {
+ Register |= XEL_TSR_XMIT_ACTIVE_MASK;
+ }
+ XEmacLite_SetTxStatus(BaseAddress, Register);
+
+ return XST_SUCCESS;
+ }
+
+ /*
+ * If the expected buffer was full, try the other buffer if configured.
+ */
+ if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
+
+ BaseAddress ^= XEL_BUFFER_OFFSET;
+
+ /*
+ * Determine if the expected buffer address is empty.
+ */
+ Register = XEmacLite_GetTxStatus(BaseAddress);
+
+ /*
+ * If the next buffer is available, fill it with the provided
+ * data.
+ */
+ if ((Register & (XEL_TSR_XMIT_BUSY_MASK |
+ XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
+
+ /*
+ * Write the frame to the buffer.
+ */
+ XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) BaseAddress,
+ ByteCount);
+
+ /*
+ * The frame is in the buffer, now send it.
+ */
+ XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
+ (ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
+ XEL_TPLR_LENGTH_MASK_LO)));
+
+ /*
+ * Update the Tx Status Register to indicate that there
+ * is a frame to send.
+ * If the interrupt enable bit of Ping buffer(since this
+ * controls both the buffers) is enabled then set the
+ * XEL_TSR_XMIT_ACTIVE_MASK flag which is used by the
+ * interrupt handler to call the callback function
+ * provided by the user to indicate that the frame has
+ * been transmitted.
+ */
+ Register = XEmacLite_GetTxStatus(BaseAddress);
+ Register |= XEL_TSR_XMIT_BUSY_MASK;
+ IntrEnableStatus =
+ XEmacLite_GetTxStatus(EmacBaseAddress);
+ if ((IntrEnableStatus & XEL_TSR_XMIT_IE_MASK) != 0) {
+ Register |= XEL_TSR_XMIT_ACTIVE_MASK;
+ }
+ XEmacLite_SetTxStatus(BaseAddress, Register);
+
+ /*
+ * Do not switch to next buffer, there is a sync problem
+ * and the expected buffer should not change.
+ */
+ return XST_SUCCESS;
+ }
+ }
+
+
+ /*
+ * Buffer(s) was(were) full, return failure to allow for polling usage.
+ */
+ return XST_FAILURE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Receive a frame. Intended to be called from the interrupt context or
+* with a wrapper which waits for the receive frame to be available.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance.
+* @param FramePtr is a pointer to a buffer where the frame will
+* be stored. The buffer must be at least XEL_MAX_FRAME_SIZE bytes.
+* For optimal performance, a 32-bit aligned buffer should be used
+* but it is not required, the function will align the data if
+* necessary.
+*
+* @return
+*
+* The type/length field of the frame received. When the type/length field
+* contains the type, XEL_MAX_FRAME_SIZE bytes will be copied out of the
+* buffer and it is up to the higher layers to sort out the frame.
+* Function returns 0 if there is no data waiting in the receive buffer or
+* the pong buffer if configured.
+*
+* @note
+*
+* This function call is not blocking in nature, i.e. it will not wait until
+* a frame arrives.
+*
+******************************************************************************/
+u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr)
+{
+ u16 LengthType;
+ u16 Length;
+ u32 Register;
+ UINTPTR BaseAddress;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Determine the expected buffer address.
+ */
+ BaseAddress = XEmacLite_NextReceiveAddr(InstancePtr);
+
+ /*
+ * Verify which buffer has valid data.
+ */
+ Register = XEmacLite_GetRxStatus(BaseAddress);
+
+ if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
+
+ /*
+ * The driver is in sync, update the next expected buffer if
+ * configured.
+ */
+
+ if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
+ InstancePtr->NextRxBufferToUse ^= XEL_BUFFER_OFFSET;
+ }
+ }
+ else {
+ /*
+ * The instance is out of sync, try other buffer if other
+ * buffer is configured, return 0 otherwise. If the instance is
+ * out of sync, do not update the 'NextRxBufferToUse' since it
+ * will correct on subsequent calls.
+ */
+ if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
+ BaseAddress ^= XEL_BUFFER_OFFSET;
+ }
+ else {
+ return 0; /* No data was available */
+ }
+
+ /*
+ * Verify that buffer has valid data.
+ */
+ Register = XEmacLite_GetRxStatus(BaseAddress);
+ if ((Register & XEL_RSR_RECV_DONE_MASK) !=
+ XEL_RSR_RECV_DONE_MASK) {
+ return 0; /* No data was available */
+ }
+ }
+
+ /*
+ * Get the length of the frame that arrived.
+ */
+ LengthType = XEmacLite_GetReceiveDataLength(BaseAddress);
+
+ /*
+ * Check if length is valid.
+ */
+ if (LengthType > XEL_MAX_FRAME_SIZE) {
+
+
+ if (LengthType == XEL_ETHER_PROTO_TYPE_IP) {
+
+ /*
+ * The packet is a an IP Packet.
+ */
+#ifdef __LITTLE_ENDIAN__
+ Length = (XEmacLite_ReadReg((BaseAddress),
+ XEL_HEADER_IP_LENGTH_OFFSET +
+ XEL_RXBUFF_OFFSET) &
+ (XEL_RPLR_LENGTH_MASK_HI |
+ XEL_RPLR_LENGTH_MASK_LO));
+ Length = (u16) (((Length & 0xFF00) >> 8) | ((Length & 0x00FF) << 8));
+#else
+ Length = ((XEmacLite_ReadReg((BaseAddress),
+ XEL_HEADER_IP_LENGTH_OFFSET +
+ XEL_RXBUFF_OFFSET) >>
+ XEL_HEADER_SHIFT) &
+ (XEL_RPLR_LENGTH_MASK_HI |
+ XEL_RPLR_LENGTH_MASK_LO));
+#endif
+
+ Length += XEL_HEADER_SIZE + XEL_FCS_SIZE;
+
+ } else if (LengthType == XEL_ETHER_PROTO_TYPE_ARP) {
+
+ /*
+ * The packet is an ARP Packet.
+ */
+ Length = XEL_ARP_PACKET_SIZE + XEL_HEADER_SIZE +
+ XEL_FCS_SIZE;
+
+ } else {
+ /*
+ * Field contains type other than IP or ARP, use max
+ * frame size and let user parse it.
+ */
+ Length = XEL_MAX_FRAME_SIZE;
+
+ }
+ } else {
+
+ /*
+ * Use the length in the frame, plus the header and trailer.
+ */
+ Length = LengthType + XEL_HEADER_SIZE + XEL_FCS_SIZE;
+ }
+
+ /*
+ * Read from the EmacLite.
+ */
+ XEmacLite_AlignedRead(((UINTPTR *) (BaseAddress + XEL_RXBUFF_OFFSET)),
+ FramePtr, Length);
+
+ /*
+ * Acknowledge the frame.
+ */
+ Register = XEmacLite_GetRxStatus(BaseAddress);
+ Register &= ~XEL_RSR_RECV_DONE_MASK;
+ XEmacLite_SetRxStatus(BaseAddress, Register);
+
+ return Length;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the MAC address for this device. The address is a 48-bit value.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance.
+* @param AddressPtr is a pointer to a 6-byte MAC address.
+* the format of the MAC address is major octet to minor octet
+*
+* @return None.
+*
+* @note
+*
+* - TX must be idle and RX should be idle for deterministic results.
+* It is recommended that this function should be called after the
+* initialization and before transmission of any packets from the device.
+* - Function will not return if hardware is absent or not functioning
+* properly.
+* - The MAC address can be programmed using any of the two transmit
+* buffers (if configured).
+*
+******************************************************************************/
+void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr)
+{
+ UINTPTR BaseAddress;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Determine the expected TX buffer address.
+ */
+ BaseAddress = XEmacLite_NextTransmitAddr(InstancePtr);
+
+ /*
+ * Copy the MAC address to the Transmit buffer.
+ */
+ XEmacLite_AlignedWrite(AddressPtr,
+ (UINTPTR *) BaseAddress,
+ XEL_MAC_ADDR_SIZE);
+
+ /*
+ * Set the length.
+ */
+ XEmacLite_WriteReg(BaseAddress,
+ XEL_TPLR_OFFSET,
+ XEL_MAC_ADDR_SIZE);
+
+ /*
+ * Update the MAC address in the EmacLite.
+ */
+ XEmacLite_SetTxStatus(BaseAddress, XEL_TSR_PROG_MAC_ADDR);
+
+
+ /*
+ * Wait for EmacLite to finish with the MAC address update.
+ */
+ while ((XEmacLite_GetTxStatus(BaseAddress) &
+ XEL_TSR_PROG_MAC_ADDR) != 0);
+
+}
+
+/******************************************************************************/
+/**
+*
+* This is a stub for the send and receive callbacks. The stub
+* is here in case the upper layers forget to set the handlers.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef)
+{
+ (void)(CallBackRef);
+ Xil_AssertVoidAlways();
+}
+
+
+/****************************************************************************/
+/**
+*
+* Determine if there is a transmit buffer available.
+*
+* @param InstancePtr is the pointer to the instance of the driver to
+* be worked on.
+*
+* @return
+* - TRUE if there is a TX buffer available for data to be written
+* - FALSE if Tx Buffer is not available.
+*
+* @note None.
+*
+*****************************************************************************/
+int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr)
+{
+
+ u32 Register;
+ int TxPingBusy;
+ int TxPongBusy;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Read the Tx Status and determine if the buffer is available.
+ */
+ Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig.
+ BaseAddress);
+
+ TxPingBusy = (Register & (XEL_TSR_XMIT_BUSY_MASK |
+ XEL_TSR_XMIT_ACTIVE_MASK));
+
+
+ /*
+ * Read the Tx Status of the second buffer register and determine if the
+ * buffer is available.
+ */
+ if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
+ Register = XEmacLite_GetTxStatus(InstancePtr->EmacLiteConfig.
+ BaseAddress +
+ XEL_BUFFER_OFFSET);
+
+ TxPongBusy = (Register & (XEL_TSR_XMIT_BUSY_MASK |
+ XEL_TSR_XMIT_ACTIVE_MASK));
+
+ return (!(TxPingBusy && TxPongBusy));
+ }
+
+ return (!TxPingBusy);
+
+
+}
+
+/****************************************************************************/
+/**
+*
+* Flush the Receive buffers. All data will be lost.
+*
+* @param InstancePtr is the pointer to the instance of the driver to
+* be worked on.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XEmacLite_FlushReceive(XEmacLite *InstancePtr)
+{
+
+ u32 Register;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Read the current buffer register and determine if the buffer is
+ * available.
+ */
+ Register = XEmacLite_GetRxStatus(InstancePtr->EmacLiteConfig.
+ BaseAddress);
+
+ /*
+ * Preserve the IE bit.
+ */
+ Register &= XEL_RSR_RECV_IE_MASK;
+
+ /*
+ * Write out the value to flush the RX buffer.
+ */
+ XEmacLite_SetRxStatus(InstancePtr->EmacLiteConfig.BaseAddress,
+ Register);
+
+ /*
+ * If the pong buffer is available, flush it also.
+ */
+ if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
+ /*
+ * Read the current buffer register and determine if the buffer
+ * is available.
+ */
+ Register = XEmacLite_GetRxStatus(InstancePtr->EmacLiteConfig.
+ BaseAddress +
+ XEL_BUFFER_OFFSET);
+
+ /*
+ * Preserve the IE bit.
+ */
+ Register &= XEL_RSR_RECV_IE_MASK;
+
+ /*
+ * Write out the value to flush the RX buffer.
+ */
+ XEmacLite_SetRxStatus(InstancePtr->EmacLiteConfig.BaseAddress +
+ XEL_BUFFER_OFFSET, Register);
+
+ }
+
+}
+
+/******************************************************************************/
+/**
+*
+* Read the specified PHY register.
+*
+* @param InstancePtr is the pointer to the instance of the driver.
+* @param PhyAddress is the address of the PHY device. The valid range is
+* is from 0 to 31.
+* @param RegNum is the register number in the PHY device which
+* is to be read. The valid range is is from 0 to 31.
+* @param PhyDataPtr is a pointer to the data in which the data read
+* from the PHY device is returned.
+*
+* @return
+* - XST_SUCCESS if the data is read from the PHY.
+* - XST_DEVICE_BUSY if MDIO is busy.
+*
+* @note This function waits for the completion of MDIO data transfer.
+*
+*****************************************************************************/
+int XEmacLite_PhyRead(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
+ u16 *PhyDataPtr)
+{
+ u32 PhyAddrReg;
+ u32 MdioCtrlReg;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->EmacLiteConfig.MdioInclude == TRUE);
+ Xil_AssertNonvoid(PhyAddress <= 31);
+ Xil_AssertNonvoid(RegNum <= 31);
+ Xil_AssertNonvoid(PhyDataPtr != NULL);
+
+ /*
+ * Verify MDIO master status.
+ */
+ if (XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET) &
+ XEL_MDIOCNTR_STATUS_MASK) {
+ return XST_DEVICE_BUSY;
+ }
+
+ PhyAddrReg = ((((PhyAddress << XEL_MDIO_ADDRESS_SHIFT) &
+ XEL_MDIO_ADDRESS_MASK) | RegNum) | XEL_MDIO_OP_MASK);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOADDR_OFFSET, PhyAddrReg);
+
+ /*
+ * Enable MDIO and start the transfer.
+ */
+ MdioCtrlReg =
+ XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET,
+ MdioCtrlReg |
+ XEL_MDIOCNTR_STATUS_MASK |
+ XEL_MDIOCNTR_ENABLE_MASK);
+
+ /*
+ * Wait till the completion of transfer.
+ */
+ while ((XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET) &
+ XEL_MDIOCNTR_STATUS_MASK));
+
+ /*
+ * Read data from MDIO read data register.
+ */
+ *PhyDataPtr = (u16)XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIORD_OFFSET);
+
+ /*
+ * Disable the MDIO.
+ */
+ MdioCtrlReg =
+ XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET);
+
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET,
+ MdioCtrlReg & ~XEL_MDIOCNTR_ENABLE_MASK);
+
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* Write the given data to the specified register in the PHY device.
+*
+* @param InstancePtr is the pointer to the instance of the driver.
+* @param PhyAddress is the address of the PHY device. The valid range is
+* is from 0 to 31.
+* @param RegNum is the register number in the PHY device which
+* is to be written. The valid range is is from 0 to 31.
+* @param PhyData is the data to be written to the specified register in
+* the PHY device.
+*
+* @return
+* - XST_SUCCESS if the data is written to the PHY.
+* - XST_DEVICE_BUSY if MDIO is busy.
+*
+* @note This function waits for the completion of MDIO data transfer.
+*
+*******************************************************************************/
+int XEmacLite_PhyWrite(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
+ u16 PhyData)
+{
+ u32 PhyAddrReg;
+ u32 MdioCtrlReg;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->EmacLiteConfig.MdioInclude == TRUE);
+ Xil_AssertNonvoid(PhyAddress <= 31);
+ Xil_AssertNonvoid(RegNum <= 31);
+
+ /*
+ * Verify MDIO master status.
+ */
+ if (XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET) &
+ XEL_MDIOCNTR_STATUS_MASK) {
+ return XST_DEVICE_BUSY;
+ }
+
+
+
+ PhyAddrReg = ((((PhyAddress << XEL_MDIO_ADDRESS_SHIFT) &
+ XEL_MDIO_ADDRESS_MASK) | RegNum) & ~XEL_MDIO_OP_MASK);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOADDR_OFFSET, PhyAddrReg);
+
+ /*
+ * Write data to MDIO write data register.
+ */
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOWR_OFFSET, (u32)PhyData);
+
+ /*
+ * Enable MDIO and start the transfer.
+ */
+ MdioCtrlReg =
+ XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET,
+ MdioCtrlReg | XEL_MDIOCNTR_STATUS_MASK |
+ XEL_MDIOCNTR_ENABLE_MASK);
+
+ /*
+ * Wait till the completion of transfer.
+ */
+ while ((XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET) & XEL_MDIOCNTR_STATUS_MASK));
+
+
+ /*
+ * Disable the MDIO.
+ */
+ MdioCtrlReg =
+ XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_MDIOCNTR_OFFSET,
+ MdioCtrlReg & ~XEL_MDIOCNTR_ENABLE_MASK);
+
+
+
+ return XST_SUCCESS;
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Enable Internal loop back functionality.
+*
+* @param InstancePtr is the pointer to the instance of the driver.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XEmacLite_EnableLoopBack(XEmacLite *InstancePtr)
+{
+ u32 TsrReg;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->EmacLiteConfig.Loopback == TRUE);
+
+ TsrReg = XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_TSR_OFFSET);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_TSR_OFFSET, TsrReg | XEL_TSR_LOOPBACK_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* Disable Internal loop back functionality.
+*
+* @param InstancePtr is the pointer to the instance of the driver.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr)
+{
+ u32 TsrReg;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->EmacLiteConfig.Loopback == TRUE);
+
+ TsrReg = XEmacLite_ReadReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_TSR_OFFSET);
+ XEmacLite_WriteReg(InstancePtr->EmacLiteConfig.BaseAddress,
+ XEL_TSR_OFFSET, TsrReg & (~XEL_TSR_LOOPBACK_MASK));
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Return the length of the data in the Receive Buffer.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return The type/length field of the frame received.
+*
+* @note None.
+*
+******************************************************************************/
+static u16 XEmacLite_GetReceiveDataLength(UINTPTR BaseAddress)
+{
+ u16 Length;
+
+#ifdef __LITTLE_ENDIAN__
+ Length = (XEmacLite_ReadReg((BaseAddress),
+ XEL_HEADER_OFFSET + XEL_RXBUFF_OFFSET) &
+ (XEL_RPLR_LENGTH_MASK_HI | XEL_RPLR_LENGTH_MASK_LO));
+ Length = (u16) (((Length & 0xFF00) >> 8) | ((Length & 0x00FF) << 8));
+#else
+ Length = ((XEmacLite_ReadReg((BaseAddress),
+ XEL_HEADER_OFFSET + XEL_RXBUFF_OFFSET) >>
+ XEL_HEADER_SHIFT) &
+ (XEL_RPLR_LENGTH_MASK_HI | XEL_RPLR_LENGTH_MASK_LO));
+#endif
+
+ return Length;
+}
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemaclite.h
+* @addtogroup emaclite_v4_1
+* @{
+* @details
+*
+* The Xilinx Ethernet Lite (EmacLite) driver. This driver supports the Xilinx
+* Ethernet Lite 10/100 MAC (EmacLite).
+*
+* The Xilinx Ethernet Lite 10/100 MAC supports the following features:
+* - Media Independent Interface (MII) for connection to external
+* 10/100 Mbps PHY transceivers
+* - Independent internal transmit and receive buffers
+* - CSMA/CD compliant operations for half-duplex modes
+* - Unicast and broadcast
+* - Automatic FCS insertion
+* - Automatic pad insertion on transmit
+* - Configurable ping/pong buffers for either/both transmit and receive
+* buffer areas
+* - Interrupt driven mode
+* - Internal loop back
+* - MDIO Support to access PHY Registers
+*
+* The Xilinx Ethernet Lite 10/100 MAC does not support the following features:
+* - multi-frame buffering
+* only 1 transmit frame is allowed into each transmit buffer,
+* only 1 receive frame is allowed into each receive buffer.
+* the hardware blocks reception until buffer is emptied
+* - Pause frame (flow control) detection in full-duplex mode
+* - Programmable inter frame gap
+* - Multicast and promiscuous address filtering
+* - Automatic source address insertion or overwrite
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the EmacLite. The driver handles transmission and reception
+* of Ethernet frames, as well as configuration of the controller. It does not
+* handle protocol stack functionality such as Link Layer Control (LLC) or the
+* Address Resolution Protocol (ARP). The protocol stack that makes use of the
+* driver handles this functionality. This implies that the driver is simply a
+* pass-through mechanism between a protocol stack and the EmacLite.
+*
+* Since the driver is a simple pass-through mechanism between a protocol stack
+* and the EmacLite, no assembly or disassembly of Ethernet frames is done at
+* the driver-level. This assumes that the protocol stack passes a correctly
+* formatted Ethernet frame to the driver for transmission, and that the driver
+* does not validate the contents of an incoming frame. A single device driver
+* can support multiple EmacLite devices.
+*
+* The driver supports interrupt driven mode and the default mode of operation
+* is polled mode. If interrupts are desired, XEmacLite_InterruptEnable() must
+* be called.
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xemaclite_g.c file.
+* A table is defined where each entry contains configuration information for an
+* EmacLite device. This information includes such things as the base address
+* of the memory-mapped device and the number of buffers.
+*
+* <b>Interrupt Processing</b>
+*
+* After _Initialize is called, _InterruptEnable can be called to enable the
+* interrupt driven functionality. If polled operation is desired, just call
+* _Send and check the return code. If XST_FAILURE is returned, call _Send with
+* the same data until XST_SUCCESS is returned. The same idea applies to _Recv.
+* Call _Recv until the returned length is non-zero at which point the received
+* data is in the buffer provided in the function call.
+*
+* The Transmit and Receive interrupts are enabled within the _InterruptEnable
+* function and disabled in the _InterruptDisable function. The _Send and _Recv
+* functions acknowledge the EmacLite generated interrupts associated with each
+* function.
+* It is the application's responsibility to acknowledge any associated Interrupt
+* Controller interrupts if it is used in the system.
+*
+* <b>Memory Buffer Alignment</b>
+*
+* The alignment of the input/output buffers for the _Send and _Recv routine is
+* not required to be 32 bits. If the buffer is not aligned on a 32-bit boundary
+* there will be a performance impact while the driver aligns the data for
+* transmission or upon reception.
+*
+* For optimum performance, the user should provide a 32-bit aligned buffer
+* to the _Send and _Recv routines.
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that application developers leave asserts on during
+* development.
+*
+* @note
+*
+* This driver requires EmacLite hardware version 1.01a and higher. It is not
+* compatible with earlier versions of the EmacLite hardware. Use version 1.00a
+* software driver for hardware version 1.00a/b.
+*
+* The RX hardware is enabled from powerup and there is no disable. It is
+* possible that frames have been received prior to the initialization
+* of the driver. If this situation is possible, call XEmacLite_FlushReceive()
+* to empty the receive buffers after initialization.
+*
+* This driver is intended to be RTOS and processor independent. It works
+* with physical addresses only. Any needs for dynamic memory management,
+* threads or thread mutual exclusion, virtual memory, or cache control must
+* be satisfied by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.01a ecm 01/30/04 First release
+* 1.11a mta 03/21/07 Updated to new coding style
+* 1.12a mta 11/28/07 Added the function XEmacLite_CfgInitialize,
+* moved the functions XEmacLite_LookupConfig and
+* XEmacLite_Initialize to xemaclite_sinit.c for removing
+* the dependency on the static config table and
+* xparameters.h from the driver initialization
+* 1.13a sv 02/1/08 Updated the TxBufferAvailable routine to return
+* busy status properly and added macros for Tx/Rx status
+* 1.14a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
+* file
+* 2.00a ktn 02/16/09 Added support for MDIO and internal loop back
+* 2.01a ktn 07/20/09 Updated the XEmacLite_AlignedWrite and
+* XEmacLite_AlignedRead functions to use volatile
+* variables so that they are not optimized.
+* Modified the XEmacLite_EnableInterrupts and
+* XEmacLite_DisableInterrupts functions to enable/disable
+* the interrupt in the Ping buffer as this is used to enable
+* the interrupts for both Ping and Pong Buffers.
+* The interrupt enable bit in the Pong buffer is not used by
+* the HW.
+* Modified XEmacLite_Send function to use Ping buffers
+* Interrupt enable bit since this alone is used to enable
+* the interrupts for both Ping and Pong Buffers.
+* 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros.
+* The macros have been renamed to remove _m from the name in
+* all the driver files.
+* The macros changed in this file are
+* XEmacLite_mNextTransmitAddr is XEmacLite_NextTransmitAddr,
+* XEmacLite_mNextReceiveAddr is XEmacLite_NextReceiveAddr,
+* XEmacLite_mIsMdioConfigured is XEmacLite_IsMdioConfigured,
+* XEmacLite_mIsLoopbackConfigured is
+* XEmacLite_IsLoopbackConfigured.
+* See xemaclite_i.h for the macros which have changed.
+* 3.01a ktn 07/08/10 The macro XEmacLite_GetReceiveDataLength in the
+* xemaclite.c file is changed to a static function.
+* XEmacLite_GetReceiveDataLength and XEmacLite_Recv
+* functions are updated to support little endian
+* MicroBlaze.
+* 3.02a sdm 07/22/11 Removed redundant code in XEmacLite_Recv functions for
+* CR617290
+* 3.03a asa 04/05/12 Defined the flag __LITTLE_ENDIAN__ for cases where the
+* driver is compiled with ARM toolchain.
+* 3.04a srt 04/13/13 Removed warnings (CR 705000).
+* 4.0 adk 19/12/13 Updated as per the New Tcl API's
+* 4.1 nsk 07/13/15 Added Length check in XEmacLite_AlignedWrite function
+* in xemaclite_l.c file to avoid extra write operation
+* (CR 843707).
+* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XEmacLite_CfgInitialize API.
+* 4.2 adk 11/18/15 Fix compilation errors due to conflicting data types
+* CR#917930
+* 4.2 adk 29/02/16 Updated interrupt example to support Zynq and ZynqMP
+* CR#938244.
+*
+* </pre>
+*
+*
+******************************************************************************/
+#ifndef XEMACLITE_H /* prevent circular inclusions */
+#define XEMACLITE_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xenv.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemaclite_l.h"
+
+#ifdef __ARMEL__
+#ifndef __LITTLE_ENDIAN__
+#define __LITTLE_ENDIAN__
+#endif
+#endif
+/************************** Constant Definitions *****************************/
+/*
+ * Device information
+ */
+#define XEL_DEVICE_NAME "xemaclite"
+#define XEL_DEVICE_DESC "Xilinx Ethernet Lite 10/100 MAC"
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress; /**< Device base address */
+ u8 TxPingPong; /**< 1 if TX Pong buffer configured, 0 otherwise */
+ u8 RxPingPong; /**< 1 if RX Pong buffer configured, 0 otherwise */
+ u8 MdioInclude; /**< 1 if MDIO is enabled, 0 otherwise */
+ u8 Loopback; /**< 1 if internal loopback is enabled, 0 otherwise */
+} XEmacLite_Config;
+
+
+/*
+ * Callback when data is sent or received .
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+ */
+typedef void (*XEmacLite_Handler) (void *CallBackRef);
+
+/**
+ * The XEmacLite driver instance data. The user is required to allocate a
+ * variable of this type for every EmacLite device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XEmacLite_Config EmacLiteConfig; /* Device configuration */
+ u32 IsReady; /* Device is initialized and ready */
+
+ u32 NextTxBufferToUse; /* Next TX buffer to write to */
+ u32 NextRxBufferToUse; /* Next RX buffer to read from */
+
+ /*
+ * Callbacks
+ */
+ XEmacLite_Handler RecvHandler;
+ void *RecvRef;
+ XEmacLite_Handler SendHandler;
+ void *SendRef;
+
+} XEmacLite;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Return the next expected Transmit Buffer's address.
+*
+* @param InstancePtr is the pointer to the instance of the driver to
+* be worked on
+*
+* @note C-Style signature:
+* u32 XEmacLite_NextTransmitAddr(XEmacLite *InstancePtr);
+*
+* This macro returns the address of the next transmit buffer to put data into.
+* This is used to determine the destination of the next transmit data frame.
+*
+*****************************************************************************/
+#define XEmacLite_NextTransmitAddr(InstancePtr) \
+ ((InstancePtr)->EmacLiteConfig.BaseAddress + \
+ (InstancePtr)->NextTxBufferToUse) + XEL_TXBUFF_OFFSET
+
+/****************************************************************************/
+/**
+*
+* Return the next expected Receive Buffer's address.
+*
+* @param InstancePtr is the pointer to the instance of the driver to
+* be worked on
+*
+* @note C-Style signature:
+* u32 XEmacLite_NextReceiveAddr(XEmacLite *InstancePtr);
+*
+* This macro returns the address of the next receive buffer to read data from.
+* This is the expected receive buffer address if the driver is in sync.
+*
+*****************************************************************************/
+#define XEmacLite_NextReceiveAddr(InstancePtr) \
+ ((InstancePtr)->EmacLiteConfig.BaseAddress + \
+ (InstancePtr)->NextRxBufferToUse)
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured for MDIO.
+*
+* @param InstancePtr is the pointer to the instance of the
+* EmacLite driver.
+*
+* @return
+* - TRUE if the device is configured for MDIO.
+* - FALSE if the device is NOT configured for MDIO.
+*
+* @note C-Style signature:
+* int XEmacLite_IsMdioConfigured(XEmacLite *InstancePtr)
+*
+******************************************************************************/
+#define XEmacLite_IsMdioConfigured(InstancePtr) \
+ ((InstancePtr)->EmacLiteConfig.MdioInclude == 1)
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured for internal
+* loopback.
+*
+* @param InstancePtr is the pointer to the instance of the
+* EmacLite driver.
+*
+* @return
+* - TRUE if the device is configured for internal loopback.
+* - FALSE if the device is NOT configured for internal loopback.
+*
+* @note C-Style signature:
+* int XEmacLite_IsLoopbackConfigured(XEmacLite *InstancePtr)
+*
+******************************************************************************/
+#define XEmacLite_IsLoopbackConfigured(InstancePtr) \
+ ((InstancePtr)->EmacLiteConfig.Loopback == 1)
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xemaclite.c
+ */
+int XEmacLite_CfgInitialize(XEmacLite *InstancePtr,
+ XEmacLite_Config *EmacLiteConfigPtr,
+ UINTPTR EffectiveAddr);
+void XEmacLite_SetMacAddress(XEmacLite *InstancePtr, u8 *AddressPtr);
+int XEmacLite_TxBufferAvailable(XEmacLite *InstancePtr);
+void XEmacLite_FlushReceive(XEmacLite *InstancePtr);
+
+int XEmacLite_Send(XEmacLite *InstancePtr, u8 *FramePtr, unsigned ByteCount);
+u16 XEmacLite_Recv(XEmacLite *InstancePtr, u8 *FramePtr);
+
+int XEmacLite_PhyRead(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
+ u16 *PhyDataPtr);
+int XEmacLite_PhyWrite(XEmacLite *InstancePtr, u32 PhyAddress, u32 RegNum,
+ u16 PhyData);
+
+void XEmacLite_EnableLoopBack(XEmacLite *InstancePtr);
+void XEmacLite_DisableLoopBack(XEmacLite *InstancePtr);
+
+/*
+ * Initialization functions in xemaclite_sinit.c
+ */
+XEmacLite_Config *XEmacLite_LookupConfig(u16 DeviceId);
+int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId);
+
+/*
+ * Interrupt driven functions in xemaclite_intr.c
+ */
+int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr);
+void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr);
+
+void XEmacLite_InterruptHandler(void *InstancePtr);
+
+void XEmacLite_SetRecvHandler(XEmacLite *InstancePtr, void *CallBackRef,
+ XEmacLite_Handler FuncPtr);
+void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef,
+ XEmacLite_Handler FuncPtr);
+
+/*
+ * Selftest function in xemaclite_selftest.c
+ */
+int XEmacLite_SelfTest(XEmacLite *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
+
+/** @} */
--- /dev/null
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Driver configuration\r
+*\r
+*******************************************************************/\r
+\r
+#include "xparameters.h"\r
+#include "xemaclite.h"\r
+\r
+/*\r
+* The configuration table for devices\r
+*/\r
+\r
+XEmacLite_Config XEmacLite_ConfigTable[] =\r
+{\r
+ {\r
+ XPAR_AXI_ETHERNETLITE_0_DEVICE_ID,\r
+ XPAR_AXI_ETHERNETLITE_0_BASEADDR,\r
+ XPAR_AXI_ETHERNETLITE_0_TX_PING_PONG,\r
+ XPAR_AXI_ETHERNETLITE_0_RX_PING_PONG,\r
+ XPAR_AXI_ETHERNETLITE_0_INCLUDE_MDIO,\r
+ XPAR_AXI_ETHERNETLITE_0_INCLUDE_INTERNAL_LOOPBACK\r
+ }\r
+};\r
+\r
+\r
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+* @file xemaclite_i.h
+* @addtogroup emaclite_v4_1
+* @{
+*
+* This header file contains internal identifiers, which are those shared
+* between the files of the driver. It is intended for internal use only.
+*
+* NOTES:
+*
+* None.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.01a ecm 05/21/04 First release
+* 1.11a mta 03/21/07 Updated to new coding style
+* 1.13a sv 02/1/08 Added macros to Get/Set Tx/Rx status
+* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
+* The macros changed in this file are
+* XEmacLite_mGetTxActive changed to XEmacLite_GetTxActive,
+* XEmacLite_mSetTxActive changed to XEmacLite_SetTxActive.
+*
+* </pre>
+******************************************************************************/
+
+#ifndef XEMACLITE_I_H /* prevent circular inclusions */
+#define XEMACLITE_I_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xemaclite.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Get the TX active location to check status. This is used to check if
+* the TX buffer is currently active. There isn't any way in the hardware
+* to implement this but the register is fully populated so the driver can
+* set the bit in the send routine and the ISR can clear the bit when
+* the handler is complete. This mimics the correct operation of the hardware
+* if it was possible to do this in hardware.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return Contents of active bit in register.
+*
+* @note C-Style signature:
+* u32 XEmacLite_GetTxActive(u32 BaseAddress)
+*
+*****************************************************************************/
+#define XEmacLite_GetTxActive(BaseAddress) \
+ (XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Set the TX active location to update status. This is used to set the bit
+* indicating which TX buffer is currently active. There isn't any way in the
+* hardware to implement this but the register is fully populated so the driver
+* can set the bit in the send routine and the ISR can clear the bit when
+* the handler is complete. This mimics the correct operation of the hardware
+* if it was possible to do this in hardware.
+*
+* @param BaseAddress is the base address of the device
+* @param Mask is the data to be written
+*
+* @return None
+*
+* @note C-Style signature:
+* void XEmacLite_SetTxActive(u32 BaseAddress, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacLite_SetTxActive(BaseAddress, Mask) \
+ (XEmacLite_WriteReg((BaseAddress), XEL_TSR_OFFSET, (Mask)))
+
+/************************** Variable Definitions ****************************/
+
+extern XEmacLite_Config XEmacLite_ConfigTable[];
+
+/************************** Function Prototypes ******************************/
+
+void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount);
+void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount);
+
+void StubHandler(void *CallBackRef);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemaclite_intr.c
+* @addtogroup emaclite_v4_1
+* @{
+*
+* Functions in this file are for the interrupt driven processing functionality.
+* See xemaclite.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.01a ecm 03/31/04 First release
+* 1.11a mta 03/21/07 Updated to new coding style
+* 2.01a ktn 07/20/09 Modified the XEmacLite_EnableInterrupts and
+* XEmacLite_DisableInterrupts functions to enable/disable
+* the interrupt in the Ping buffer as this is used to enable
+* the interrupts for both Ping and Pong Buffers.
+* The interrupt enable bit in the Pong buffer is not used by
+* the HW.
+* 3.00a ktn 10/22/09 Updated file to use the HAL Processor APIs/macros.
+* The macros have been renamed to remove _m from the name.
+* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemaclite_i.h"
+#include "xil_io.h"
+#include "xemaclite.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+*
+* Enable the EmacLite Interrupts.
+*
+* This function must be called before other functions to send or receive data
+* in interrupt driven mode. The user should have connected the
+* interrupt handler of the driver to an interrupt source such as an interrupt
+* controller or the processor interrupt prior to this function being called.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance.
+*
+* @return
+* - XST_SUCCESS if the device interrupts were enabled
+* successfully.
+* - XST_NO_CALLBACK if the callbacks were not set.
+*
+* @note None.
+*
+******************************************************************************/
+int XEmacLite_EnableInterrupts(XEmacLite *InstancePtr)
+{
+ u32 Register;
+ UINTPTR BaseAddress;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
+
+ /*
+ * Verify that the handlers are in place.
+ */
+ if ((InstancePtr->RecvHandler == (XEmacLite_Handler) StubHandler) ||
+ (InstancePtr->SendHandler == (XEmacLite_Handler) StubHandler)) {
+ return XST_NO_CALLBACK;
+ }
+
+ /*
+ * Enable the TX interrupts for both the buffers, the Interrupt Enable
+ * is common for the both the buffers and is defined in the
+ * Ping buffer.
+ */
+ Register = XEmacLite_GetTxStatus(BaseAddress);
+ Register |= XEL_TSR_XMIT_IE_MASK;
+ XEmacLite_SetTxStatus(BaseAddress, Register);
+
+ /*
+ * Enable the RX interrupts for both the buffers, the Interrupt Enable
+ * is common for the both the buffers and is defined in the
+ * Ping buffer.
+ */
+ Register = XEmacLite_GetRxStatus(BaseAddress);
+ Register |= XEL_RSR_RECV_IE_MASK;
+ XEmacLite_SetRxStatus(BaseAddress, Register);
+
+ /*
+ * Enable the global interrupt output.
+ */
+ XEmacLite_WriteReg(BaseAddress, XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupts from the device (the higher layer software is
+* responsible for disabling interrupts at the interrupt controller).
+*
+* To start using the device again, _EnableInterrupts must be called.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance .
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XEmacLite_DisableInterrupts(XEmacLite *InstancePtr)
+{
+ u32 Register;
+ UINTPTR BaseAddress;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress;
+
+ /*
+ * Disable the global interrupt output.
+ */
+ XEmacLite_WriteReg(BaseAddress, XEL_GIER_OFFSET, 0);
+
+ /*
+ * Disable the TX interrupts for both the buffers, the Interrupt Enable
+ * is common for the both the buffers and is defined in the
+ * Ping buffer.
+ */
+ Register = XEmacLite_GetTxStatus(BaseAddress);
+ Register &= ~XEL_TSR_XMIT_IE_MASK;
+ XEmacLite_SetTxStatus(BaseAddress, Register);
+
+ /*
+ * Disable the RX interrupts for both the buffers, the Interrupt Enable
+ * is common for the both the buffers and is defined in the
+ * Ping buffer.
+ */
+ Register = XEmacLite_GetRxStatus(BaseAddress);
+ Register &= ~XEL_RSR_RECV_IE_MASK;
+ XEmacLite_SetRxStatus(BaseAddress, Register);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Interrupt handler for the EmacLite driver. It performs the following
+* processing:
+*
+* - Get the interrupt status from the registers to determine the source
+* of the interrupt.
+* - Call the appropriate handler based on the source of the interrupt.
+*
+* @param InstancePtr contains a pointer to the EmacLite device instance
+* for the interrupt.
+*
+* @return None.
+*
+* @note None.
+*
+*
+******************************************************************************/
+void XEmacLite_InterruptHandler(void *InstancePtr)
+{
+
+ XEmacLite *EmacLitePtr;
+ int TxCompleteIntr = FALSE;
+ UINTPTR BaseAddress;
+ u32 TxStatus;
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Convert the non-typed pointer to an EmacLite instance pointer
+ * such that there is access to the device.
+ */
+ EmacLitePtr = (XEmacLite *) InstancePtr;
+ BaseAddress = EmacLitePtr->EmacLiteConfig.BaseAddress;
+
+ if ((XEmacLite_IsRxEmpty(BaseAddress) != TRUE) ||
+ (XEmacLite_IsRxEmpty(BaseAddress +
+ XEL_BUFFER_OFFSET) != TRUE)) {
+ /*
+ * Call the RX callback.
+ */
+ EmacLitePtr->RecvHandler(EmacLitePtr->RecvRef);
+
+ }
+
+ TxStatus = XEmacLite_GetTxStatus(BaseAddress);
+ if (((TxStatus & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
+ (TxStatus & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
+
+ /*
+ * Clear the Tx Active bit in the Tx Status Register.
+ */
+ TxStatus &= ~XEL_TSR_XMIT_ACTIVE_MASK;
+ XEmacLite_SetTxStatus(BaseAddress, TxStatus);
+
+ /*
+ * Update the flag indicating that there was a Tx Interrupt.
+ */
+ TxCompleteIntr = TRUE;
+
+ }
+
+ TxStatus = XEmacLite_GetTxStatus(BaseAddress + XEL_BUFFER_OFFSET);
+ if (((TxStatus & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
+ (TxStatus & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
+
+ /*
+ * Clear the Tx Active bit in the Tx Status Register.
+ */
+ TxStatus &= ~XEL_TSR_XMIT_ACTIVE_MASK;
+ XEmacLite_SetTxStatus(BaseAddress + XEL_BUFFER_OFFSET,
+ TxStatus);
+ /*
+ * Update the flag indicating that there was a Tx Interrupt.
+ */
+ TxCompleteIntr = TRUE;
+ }
+
+ /*
+ * If there was a TX interrupt, call the callback.
+ */
+ if (TxCompleteIntr == TRUE) {
+
+ /*
+ * Call the TX callback.
+ */
+ EmacLitePtr->SendHandler(EmacLitePtr->SendRef);
+
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the callback function for handling received frames in interrupt mode.
+* The upper layer software should call this function during initialization.
+* The callback is called when a frame is received. The callback function
+* should communicate the data to a thread such that the processing is not
+* performed in an interrupt context.
+*
+* The callback is invoked by the driver within interrupt context, so it needs
+* to do its job quickly. If there are other potentially slow operations
+* within the callback, these should be done at task-level.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance..
+* @param CallBackRef is a reference pointer to be passed back to the
+* application in the callback. This helps the application
+* correlate the callback to a particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XEmacLite_SetRecvHandler(XEmacLite *InstancePtr, void *CallBackRef,
+ XEmacLite_Handler FuncPtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->RecvHandler = FuncPtr;
+ InstancePtr->RecvRef = CallBackRef;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Sets the callback function for handling transmitted frames in interrupt mode.
+* The upper layer software should call this function during initialization.
+* The callback is called when a frame is transmitted. The callback function
+* should communicate the data to a thread such that the processing is not
+* performed in an interrupt context.
+*
+* The callback is invoked by the driver within interrupt context, so it needs
+* to do its job quickly. If there are other potentially slow operations
+* within the callback, these should be done at task-level.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance.
+* @param CallBackRef is a reference pointer to be passed back to the
+* application in the callback. This helps the application
+* correlate the callback to a particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XEmacLite_SetSendHandler(XEmacLite *InstancePtr, void *CallBackRef,
+ XEmacLite_Handler FuncPtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->SendHandler = FuncPtr;
+ InstancePtr->SendRef = CallBackRef;
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemaclite_l.c
+* @addtogroup emaclite_v4_1
+* @{
+*
+* This file contains the minimal, polled functions to send and receive Ethernet
+* frames.
+*
+* Refer to xemaclite.h for more details.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 06/01/02 First release
+* 1.01a ecm 03/31/04 Additional functionality and the _AlignedRead and
+* _AlignedWrite functions.
+* 1.11a mta 03/21/07 Updated to new coding style
+* 2.01a ktn 07/20/09 Updated the XEmacLite_AlignedWrite and
+* XEmacLite_AlignedRead functions to use volatile
+* variables so that they are not optimized.
+* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
+* 4.1 nsk 07/13/15 Added Length check in XEmacLite_AlignedWrite function
+* to avoid extra write operation (CR 843707).
+* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototypes of XEmacLite_SendFrame,
+* XEmacLite_RecvFrame, XEmacLite_AlignedWrite,
+* XEmacLite_AlignedRead APIs.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xemaclite_l.h"
+#include "xemaclite_i.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount);
+void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Send an Ethernet frame. The size is the total frame size, including header.
+* This function blocks waiting for the frame to be transmitted.
+*
+* @param BaseAddress is the base address of the device
+* @param FramePtr is a pointer to frame
+* @param ByteCount is the size, in bytes, of the frame
+*
+* @return None.
+*
+* @note
+*
+* This function call is blocking in nature, i.e. it will wait until the
+* frame is transmitted. This function can hang and not exit if the
+* hardware is not configured properly.
+*
+* If the ping buffer is the destination of the data, the argument should be
+* DeviceAddress + XEL_TXBUFF_OFFSET.
+* If the pong buffer is the destination of the data, the argument should be
+* DeviceAddress + XEL_TXBUFF_OFFSET + XEL_BUFFER_OFFSET.
+* The function does not take the different buffers into consideration.
+*
+******************************************************************************/
+void XEmacLite_SendFrame(UINTPTR BaseAddress, u8 *FramePtr, unsigned ByteCount)
+{
+ u32 Register;
+
+ /*
+ * Write data to the EmacLite
+ */
+ XEmacLite_AlignedWrite(FramePtr, (UINTPTR *) (BaseAddress), ByteCount);
+
+ /*
+ * The frame is in the buffer, now send it
+ */
+ XEmacLite_WriteReg(BaseAddress, XEL_TPLR_OFFSET,
+ (ByteCount & (XEL_TPLR_LENGTH_MASK_HI |
+ XEL_TPLR_LENGTH_MASK_LO)));
+
+
+ Register = XEmacLite_GetTxStatus(BaseAddress);
+ XEmacLite_SetTxStatus(BaseAddress, Register | XEL_TSR_XMIT_BUSY_MASK);
+
+ /*
+ * Loop on the status waiting for the transmit to be complete.
+ */
+ while (!XEmacLite_IsTxDone(BaseAddress));
+
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Receive a frame. Wait for a frame to arrive.
+*
+* @param BaseAddress is the base address of the device
+* @param FramePtr is a pointer to a buffer where the frame will
+* be stored.
+*
+* @return
+*
+* The type/length field of the frame received. When the type/length field
+* contains the type , XEL_MAX_FRAME_SIZE bytes will be copied out of the
+* buffer and it is up to the higher layers to sort out the frame.
+*
+* @note
+*
+* This function call is blocking in nature, i.e. it will wait until a
+* frame arrives.
+*
+* If the ping buffer is the source of the data, the argument should be
+* DeviceAddress + XEL_RXBUFF_OFFSET.
+* If the pong buffer is the source of the data, the argument should be
+* DeviceAddress + XEL_RXBUFF_OFFSET + XEL_BUFFER_OFFSET.
+* The function does not take the different buffers into consideration.
+*
+******************************************************************************/
+u16 XEmacLite_RecvFrame(UINTPTR BaseAddress, u8 *FramePtr)
+{
+ u16 LengthType;
+ u16 Length;
+ u32 Register;
+
+ /*
+ * Wait for a frame to arrive - this is a blocking call
+ */
+ while (XEmacLite_IsRxEmpty(BaseAddress));
+
+ /*
+ * Get the length of the frame that arrived, only 32-bit reads are
+ * allowed LengthType is in the upper half of the 32-bit word.
+ */
+ Register = XEmacLite_ReadReg(BaseAddress, XEL_RPLR_OFFSET);
+ LengthType = (u16) ((Register >> 16) &
+ (XEL_RPLR_LENGTH_MASK_HI |
+ XEL_RPLR_LENGTH_MASK_LO));
+
+ /*
+ * Check if length is valid
+ */
+ if (LengthType > XEL_MAX_FRAME_SIZE) {
+ /*
+ * Field contain type, use max frame size and
+ * let user parse it
+ */
+ Length = XEL_MAX_FRAME_SIZE;
+ }
+ else {
+ /*
+ * Use the length in the frame, plus the header and trailer
+ */
+ Length = LengthType + XEL_HEADER_SIZE + XEL_FCS_SIZE;
+ }
+
+ /*
+ * Read each byte from the EmacLite
+ */
+ XEmacLite_AlignedRead((UINTPTR *) (BaseAddress + XEL_RXBUFF_OFFSET),
+ FramePtr, Length);
+
+ /*
+ * Acknowledge the frame
+ */
+ Register = XEmacLite_GetRxStatus(BaseAddress);
+ Register &= ~XEL_RSR_RECV_DONE_MASK;
+ XEmacLite_SetRxStatus(BaseAddress, Register);
+
+ return LengthType;
+}
+
+/******************************************************************************/
+/**
+*
+* This function aligns the incoming data and writes it out to a 32-bit
+* aligned destination address range.
+*
+* @param SrcPtr is a pointer to incoming data of any alignment.
+* @param DestPtr is a pointer to outgoing data of 32-bit alignment.
+* @param ByteCount is the number of bytes to write.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XEmacLite_AlignedWrite(void *SrcPtr, UINTPTR *DestPtr, unsigned ByteCount)
+{
+ unsigned Index;
+ unsigned Length = ByteCount;
+ volatile u32 AlignBuffer;
+ volatile u32 *To32Ptr;
+ u32 *From32Ptr;
+ volatile u16 *To16Ptr;
+ u16 *From16Ptr;
+ volatile u8 *To8Ptr;
+ u8 *From8Ptr;
+
+ To32Ptr = DestPtr;
+
+ if ((((u32) SrcPtr) & 0x00000003) == 0) {
+
+ /*
+ * Word aligned buffer, no correction needed.
+ */
+ From32Ptr = (u32 *) SrcPtr;
+
+ while (Length > 3) {
+ /*
+ * Output each word destination.
+ */
+ *To32Ptr++ = *From32Ptr++;
+
+ /*
+ * Adjust length accordingly
+ */
+ Length -= 4;
+ }
+
+ /*
+ * Set up to output the remaining data, zero the temp buffer
+ first.
+ */
+ AlignBuffer = 0;
+ To8Ptr = (u8 *) &AlignBuffer;
+ From8Ptr = (u8 *) From32Ptr;
+
+ }
+ else if ((((u32) SrcPtr) & 0x00000001) != 0) {
+ /*
+ * Byte aligned buffer, correct.
+ */
+ AlignBuffer = 0;
+ To8Ptr = (u8 *) &AlignBuffer;
+ From8Ptr = (u8 *) SrcPtr;
+
+ while (Length > 3) {
+ /*
+ * Copy each byte into the temporary buffer.
+ */
+ for (Index = 0; Index < 4; Index++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+
+ /*
+ * Output the buffer
+ */
+ *To32Ptr++ = AlignBuffer;
+
+ /*.
+ * Reset the temporary buffer pointer and adjust length.
+ */
+ To8Ptr = (u8 *) &AlignBuffer;
+ Length -= 4;
+ }
+
+ /*
+ * Set up to output the remaining data, zero the temp buffer
+ * first.
+ */
+ AlignBuffer = 0;
+ To8Ptr = (u8 *) &AlignBuffer;
+
+ }
+ else {
+ /*
+ * Half-Word aligned buffer, correct.
+ */
+ AlignBuffer = 0;
+
+ /*
+ * This is a funny looking cast. The new gcc, version 3.3.x has
+ * a strict cast check for 16 bit pointers, aka short pointers.
+ * The following warning is issued if the initial 'void *' cast
+ * is not used:
+ * 'dereferencing type-punned pointer will break strict-aliasing
+ * rules'
+ */
+
+ To16Ptr = (u16 *) ((void *) &AlignBuffer);
+ From16Ptr = (u16 *) SrcPtr;
+
+ while (Length > 3) {
+ /*
+ * Copy each half word into the temporary buffer.
+ */
+ for (Index = 0; Index < 2; Index++) {
+ *To16Ptr++ = *From16Ptr++;
+ }
+
+ /*
+ * Output the buffer.
+ */
+ *To32Ptr++ = AlignBuffer;
+
+ /*
+ * Reset the temporary buffer pointer and adjust length.
+ */
+
+ /*
+ * This is a funny looking cast. The new gcc, version
+ * 3.3.x has a strict cast check for 16 bit pointers,
+ * aka short pointers. The following warning is issued
+ * if the initial 'void *' cast is not used:
+ * 'dereferencing type-punned pointer will break
+ * strict-aliasing rules'
+ */
+ To16Ptr = (u16 *) ((void *) &AlignBuffer);
+ Length -= 4;
+ }
+
+ /*
+ * Set up to output the remaining data, zero the temp buffer
+ * first.
+ */
+ AlignBuffer = 0;
+ To8Ptr = (u8 *) &AlignBuffer;
+ From8Ptr = (u8 *) From16Ptr;
+ }
+
+ /*
+ * Output the remaining data, zero the temp buffer first.
+ */
+ for (Index = 0; Index < Length; Index++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+ if (Length) {
+ *To32Ptr++ = AlignBuffer;
+ }
+}
+
+/******************************************************************************/
+/**
+*
+* This function reads from a 32-bit aligned source address range and aligns
+* the writes to the provided destination pointer alignment.
+*
+* @param SrcPtr is a pointer to incoming data of 32-bit alignment.
+* @param DestPtr is a pointer to outgoing data of any alignment.
+* @param ByteCount is the number of bytes to read.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XEmacLite_AlignedRead(UINTPTR *SrcPtr, void *DestPtr, unsigned ByteCount)
+{
+ unsigned Index;
+ unsigned Length = ByteCount;
+ volatile u32 AlignBuffer;
+ u32 *To32Ptr;
+ volatile u32 *From32Ptr;
+ u16 *To16Ptr;
+ volatile u16 *From16Ptr;
+ u8 *To8Ptr;
+ volatile u8 *From8Ptr;
+
+ From32Ptr = (u32 *) SrcPtr;
+
+ if ((((u32) DestPtr) & 0x00000003) == 0) {
+
+ /*
+ * Word aligned buffer, no correction needed.
+ */
+ To32Ptr = (u32 *) DestPtr;
+
+ while (Length > 3) {
+ /*
+ * Output each word.
+ */
+ *To32Ptr++ = *From32Ptr++;
+
+ /*
+ * Adjust length accordingly.
+ */
+ Length -= 4;
+ }
+
+ /*
+ * Set up to read the remaining data.
+ */
+ To8Ptr = (u8 *) To32Ptr;
+
+ }
+ else if ((((u32) DestPtr) & 0x00000001) != 0) {
+ /*
+ * Byte aligned buffer, correct.
+ */
+ To8Ptr = (u8 *) DestPtr;
+
+ while (Length > 3) {
+ /*
+ * Copy each word into the temporary buffer.
+ */
+ AlignBuffer = *From32Ptr++;
+ From8Ptr = (u8 *) &AlignBuffer;
+
+ /*
+ * Write data to destination.
+ */
+ for (Index = 0; Index < 4; Index++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+
+ /*
+ * Adjust length
+ */
+ Length -= 4;
+ }
+
+ }
+ else {
+ /*
+ * Half-Word aligned buffer, correct.
+ */
+ To16Ptr = (u16 *) DestPtr;
+
+ while (Length > 3) {
+ /*
+ * Copy each word into the temporary buffer.
+ */
+ AlignBuffer = *From32Ptr++;
+
+ /*
+ * This is a funny looking cast. The new gcc, version
+ * 3.3.x has a strict cast check for 16 bit pointers,
+ * aka short pointers. The following warning is issued
+ * if the initial 'void *' cast is not used:
+ * 'dereferencing type-punned pointer will break
+ * strict-aliasing rules'
+ */
+ From16Ptr = (u16 *) ((void *) &AlignBuffer);
+
+ /*
+ * Write data to destination.
+ */
+ for (Index = 0; Index < 2; Index++) {
+ *To16Ptr++ = *From16Ptr++;
+ }
+
+ /*
+ * Adjust length.
+ */
+ Length -= 4;
+ }
+
+ /*
+ * Set up to read the remaining data.
+ */
+ To8Ptr = (u8 *) To16Ptr;
+ }
+
+ /*
+ * Read the remaining data.
+ */
+ AlignBuffer = *From32Ptr++;
+ From8Ptr = (u8 *) &AlignBuffer;
+
+ for (Index = 0; Index < Length; Index++) {
+ *To8Ptr++ = *From8Ptr++;
+ }
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemaclite_l.h
+* @addtogroup emaclite_v4_1
+* @{
+*
+* This header file contains identifiers and basic driver functions and macros
+* that can be used to access the Xilinx Ethernet Lite 10/100 MAC (EmacLite).
+*
+* Refer to xemaclite.h for more details.
+*
+* @note
+*
+* The functions and macros in this file assume that the proper device address is
+* provided in the argument. If the ping buffer is the source or destination,
+* the argument should be DeviceAddress + XEL_(T/R)XBUFF_OFFSET. If the pong
+* buffer is the source or destination, the argument should be
+* DeviceAddress + XEL_(T/R)XBUFF_OFFSET + XEL_BUFFER_OFFSET. The driver does
+* not take the different buffers into consideration.
+* For more details on the ping/pong buffer configuration please refer to the
+* Ethernet Lite 10/100 Media Access Controller hardware specification.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 06/01/02 First release
+* 1.01a ecm 03/31/04 Additional functionality and the _AlignedRead and
+* AlignedWrite functions.
+* Moved the bulk of description to xemaclite.h
+* 1.11a mta 03/21/07 Updated to new coding style
+* 2.00a ktn 02/16/09 Added support for MDIO and internal loop back
+* 3.00a ktn 10/22/09 The macros have been renamed to remove _m from the name.
+* The macros changed in this file are
+* XEmacLite_mReadReg changed to XEmacLite_mReadReg,
+* XEmacLite_mWriteReg changed to XEmacLite_mWriteReg,
+* XEmacLite_mGetTxStatus changed to XEmacLite_GetTxStatus,
+* XEmacLite_mSetTxStatus changed to XEmacLite_SetTxStatus,
+* XEmacLite_mGetRxStatus changed to XEmacLite_GetRxStatus,
+* XEmacLite_mSetRxStatus changed to XEmacLite_SetRxStatus,
+* XEmacLite_mIsTxDone changed to XEmacLite_IsTxDone and
+* XEmacLite_mIsRxEmpty changed to XEmacLite_IsRxEmpty.
+* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototypes of XEmacLite_SendFrame,
+* XEmacLite_RecvFrame APIs.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMAC_LITE_L_H /* prevent circular inclusions */
+#define XEMAC_LITE_L_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+/**
+ * Register offsets for the Ethernet MAC.
+ */
+#define XEL_TXBUFF_OFFSET (0x00000000) /**< Transmit Buffer */
+#define XEL_MDIOADDR_OFFSET (XEL_TXBUFF_OFFSET + 0x07E4)/**< MDIO Address offset
+ register */
+#define XEL_MDIOWR_OFFSET (XEL_TXBUFF_OFFSET + 0x07E8) /**< MDIO write data
+ register offset */
+#define XEL_MDIORD_OFFSET (XEL_TXBUFF_OFFSET + 0x07EC) /**< MDIO read data
+ register offset*/
+#define XEL_MDIOCNTR_OFFSET (XEL_TXBUFF_OFFSET + 0x07F0)/**< MDIO Control
+ Register offset */
+#define XEL_GIER_OFFSET (XEL_TXBUFF_OFFSET + 0x07F8) /**< Offset for the GIE
+ Register */
+#define XEL_TSR_OFFSET (XEL_TXBUFF_OFFSET + 0x07FC) /**< Tx status */
+#define XEL_TPLR_OFFSET (XEL_TXBUFF_OFFSET + 0x07F4) /**< Tx packet length */
+
+#define XEL_RXBUFF_OFFSET (0x00001000) /**< Receive Buffer */
+#define XEL_RSR_OFFSET (XEL_RXBUFF_OFFSET + 0x07FC) /**< Rx status */
+#define XEL_RPLR_OFFSET (XEL_RXBUFF_OFFSET + 0x0C) /**< Rx packet length */
+
+#define XEL_MAC_HI_OFFSET (XEL_TXBUFF_OFFSET + 0x14) /**< MAC address hi
+ offset */
+#define XEL_MAC_LO_OFFSET (XEL_TXBUFF_OFFSET) /**< MAC address lo
+ offset */
+
+#define XEL_BUFFER_OFFSET (0x00000800) /**< Next buffer's
+ offset same for
+ both TX and RX */
+/**
+ * MDIO Address/Write Data/Read Data Register Bit Masks
+ */
+#define XEL_MDIO_ADDRESS_MASK 0x00003E0 /**< PHY Address mask */
+#define XEL_MDIO_ADDRESS_SHIFT 0x5 /**< PHY Address shift*/
+#define XEL_MDIO_OP_MASK 0x00000400 /**< PHY read access */
+
+/**
+ * MDIO Control Register Bit Masks
+ */
+#define XEL_MDIOCNTR_STATUS_MASK 0x00000001 /**< MDIO transfer in
+ Progress */
+#define XEL_MDIOCNTR_ENABLE_MASK 0x00000008 /**< MDIO Enable */
+
+/**
+ * Global Interrupt Enable Register (GIER) Bit Masks
+ */
+#define XEL_GIER_GIE_MASK 0x80000000 /**< Global Enable */
+
+/**
+ * Transmit Status Register (TSR) Bit Masks
+ */
+#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /**< Xmit complete */
+#define XEL_TSR_PROGRAM_MASK 0x00000002 /**< Program the MAC
+ address */
+#define XEL_TSR_XMIT_IE_MASK 0x00000008 /**< Xmit interrupt
+ enable bit */
+#define XEL_TSR_LOOPBACK_MASK 0x00000010 /**< Loop back enable
+ bit */
+#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /**< Buffer is active,
+ SW bit only. This
+ is not documented
+ in the HW spec */
+
+/**
+ * define for programming the MAC address into the EmacLite
+ */
+#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
+
+/**
+ * Receive Status Register (RSR)
+ */
+#define XEL_RSR_RECV_DONE_MASK 0x00000001 /**< Recv complete */
+#define XEL_RSR_RECV_IE_MASK 0x00000008 /**< Recv interrupt
+ enable bit */
+
+/**
+ * Transmit Packet Length Register (TPLR)
+ */
+#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00 /**< Transmit packet length
+ upper byte */
+#define XEL_TPLR_LENGTH_MASK_LO 0x000000FF /**< Transmit packet length
+ lower byte */
+
+/**
+ * Receive Packet Length Register (RPLR)
+ */
+#define XEL_RPLR_LENGTH_MASK_HI 0x0000FF00 /**< Receive packet length
+ upper byte */
+#define XEL_RPLR_LENGTH_MASK_LO 0x000000FF /**< Receive packet length
+ lower byte */
+
+#define XEL_HEADER_SIZE 14 /**< Size of header in bytes */
+#define XEL_MTU_SIZE 1500 /**< Max size of data in frame */
+#define XEL_FCS_SIZE 4 /**< Size of CRC */
+
+#define XEL_HEADER_OFFSET 12 /**< Offset to length field */
+#define XEL_HEADER_SHIFT 16 /**< Right shift value to align
+ length */
+
+
+#define XEL_MAX_FRAME_SIZE (XEL_HEADER_SIZE+XEL_MTU_SIZE+ XEL_FCS_SIZE) /**< Max
+ length of Rx frame used if
+ length/type field
+ contains the type (> 1500) */
+
+#define XEL_MAX_TX_FRAME_SIZE (XEL_HEADER_SIZE + XEL_MTU_SIZE) /**< Max
+ length of Tx frame */
+
+
+#define XEL_MAC_ADDR_SIZE 6 /**< length of MAC address */
+
+
+/*
+ * General Ethernet Definitions
+ */
+#define XEL_ETHER_PROTO_TYPE_IP 0x0800 /**< IP Protocol */
+#define XEL_ETHER_PROTO_TYPE_ARP 0x0806 /**< ARP Protocol */
+#define XEL_ETHER_PROTO_TYPE_VLAN 0x8100 /**< VLAN Tagged */
+#define XEL_ARP_PACKET_SIZE 28 /**< Max ARP packet size */
+#define XEL_HEADER_IP_LENGTH_OFFSET 16 /**< IP Length Offset */
+#define XEL_VLAN_TAG_SIZE 4 /**< VLAN Tag Size */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XEmacLite_In32 Xil_In32
+#define XEmacLite_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+*
+* Read from the specified EmacLite device register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to select the specific register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XEmacLite_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XEmacLite_ReadReg(BaseAddress, RegOffset) \
+ XEmacLite_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+*
+* Write to the specified EmacLite device register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to select the specific register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XEmacLite_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 RegisterValue);
+******************************************************************************/
+#define XEmacLite_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XEmacLite_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+
+/****************************************************************************/
+/**
+*
+* Get the Tx Status Register Contents.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return The contents of the Tx Status Register.
+*
+* @note C-Style signature:
+* u32 XEmacLite_GetTxStatus(u32 BaseAddress)
+*
+*****************************************************************************/
+#define XEmacLite_GetTxStatus(BaseAddress) \
+ (XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET))
+
+
+/****************************************************************************/
+/**
+*
+* Set the Tx Status Register Contents.
+*
+* @param BaseAddress is the base address of the device
+* @param Data is the value to be written to the Register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* u32 XEmacLite_SetTxStatus(u32 BaseAddress, u32 Data)
+*
+*****************************************************************************/
+#define XEmacLite_SetTxStatus(BaseAddress, Data) \
+ (XEmacLite_WriteReg((BaseAddress), XEL_TSR_OFFSET, (Data)))
+
+
+/****************************************************************************/
+/**
+*
+* Get the Rx Status Register Contents.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return The contents of the Rx Status Register.
+*
+* @note C-Style signature:
+* u32 XEmacLite_GetRxStatus(u32 BaseAddress)
+*
+*****************************************************************************/
+#define XEmacLite_GetRxStatus(BaseAddress) \
+ (XEmacLite_ReadReg((BaseAddress), XEL_RSR_OFFSET))
+
+
+/****************************************************************************/
+/**
+*
+* Set the Rx Status Register Contents.
+*
+* @param BaseAddress is the base address of the device
+* @param Data is the value to be written to the Register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* u32 XEmacLite_SetRxStatus(u32 BaseAddress, u32 Data)
+*
+*****************************************************************************/
+#define XEmacLite_SetRxStatus(BaseAddress, Data) \
+ (XEmacLite_WriteReg((BaseAddress), XEL_RSR_OFFSET, (Data)))
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the transmission is complete.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return TRUE if it is done, or FALSE if it is not.
+*
+* @note C-Style signature:
+* int XEmacLite_IsTxDone(u32 BaseAddress)
+*
+*****************************************************************************/
+#define XEmacLite_IsTxDone(BaseAddress) \
+ ((XEmacLite_ReadReg((BaseAddress), XEL_TSR_OFFSET) & \
+ XEL_TSR_XMIT_BUSY_MASK) != XEL_TSR_XMIT_BUSY_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the receive is empty.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return TRUE if it is empty, or FALSE if it is not.
+*
+* @note C-Style signature:
+* int XEmacLite_IsRxEmpty(u32 BaseAddress)
+*
+*****************************************************************************/
+#define XEmacLite_IsRxEmpty(BaseAddress) \
+ ((XEmacLite_ReadReg((BaseAddress), XEL_RSR_OFFSET) & \
+ XEL_RSR_RECV_DONE_MASK) != XEL_RSR_RECV_DONE_MASK)
+
+/************************** Function Prototypes ******************************/
+
+void XEmacLite_SendFrame(UINTPTR BaseAddress, u8 *FramePtr, unsigned ByteCount);
+u16 XEmacLite_RecvFrame(UINTPTR BaseAddress, u8 *FramePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemaclite_selftest.c
+* @addtogroup emaclite_v4_1
+* @{
+*
+* Function(s) in this file are the required functions for the EMAC Lite
+* driver sefftest for the hardware.
+* See xemaclite.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.01a ecm 01/31/04 First release
+* 1.11a mta 03/21/07 Updated to new coding style
+* 3.00a ktn 10/22/09 Updated driver to use the HAL Processor APIs/macros.
+* 4.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+#include "xemaclite.h"
+#include "xemaclite_i.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Performs a SelfTest on the EmacLite device as follows:
+* - Writes to the mandatory TX buffer and reads back to verify.
+* - If configured, writes to the secondary TX buffer and reads back to verify.
+* - Writes to the mandatory RX buffer and reads back to verify.
+* - If configured, writes to the secondary RX buffer and reads back to verify.
+*
+*
+* @param InstancePtr is a pointer to the XEmacLite instance .
+*
+* @return
+* - XST_SUCCESS if the device Passed the Self Test.
+* - XST_FAILURE if any of the data read backs fail.
+*
+* @note None.
+*
+******************************************************************************/
+int XEmacLite_SelfTest(XEmacLite * InstancePtr)
+{
+ UINTPTR BaseAddress;
+ u8 Index;
+ u8 TestString[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
+ u8 ReturnString[4] = { 0x0, 0x0, 0x0, 0x0 };
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Determine the TX buffer address
+ */
+ BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress +
+ XEL_TXBUFF_OFFSET;
+
+ /*
+ * Write the TestString to the TX buffer in EMAC Lite then
+ * back from the EMAC Lite and verify
+ */
+ XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress,
+ sizeof(TestString));
+ XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString,
+ sizeof(ReturnString));
+
+ for (Index = 0; Index < 4; Index++) {
+
+ if (ReturnString[Index] != TestString[Index]) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Zero the return string for the next test
+ */
+ ReturnString[Index] = 0;
+ }
+
+ /*
+ * If the second buffer is configured, test it also
+ */
+ if (InstancePtr->EmacLiteConfig.TxPingPong != 0) {
+ BaseAddress += XEL_BUFFER_OFFSET;
+ /*
+ * Write the TestString to the optional TX buffer in EMAC Lite
+ * then back from the EMAC Lite and verify
+ */
+ XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress,
+ sizeof(TestString));
+ XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString,
+ sizeof(ReturnString));
+
+ for (Index = 0; Index < 4; Index++) {
+
+ if (ReturnString[Index] != TestString[Index]) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Zero the return string for the next test
+ */
+ ReturnString[Index] = 0;
+ }
+ }
+
+ /*
+ * Determine the RX buffer address
+ */
+ BaseAddress = InstancePtr->EmacLiteConfig.BaseAddress +
+ XEL_RXBUFF_OFFSET;
+
+ /*
+ * Write the TestString to the RX buffer in EMAC Lite then
+ * back from the EMAC Lite and verify
+ */
+ XEmacLite_AlignedWrite(TestString, (UINTPTR *) (BaseAddress),
+ sizeof(TestString));
+ XEmacLite_AlignedRead((UINTPTR *) (BaseAddress), ReturnString,
+ sizeof(ReturnString));
+
+ for (Index = 0; Index < 4; Index++) {
+
+ if (ReturnString[Index] != TestString[Index]) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Zero the return string for the next test
+ */
+ ReturnString[Index] = 0;
+ }
+
+ /*
+ * If the second buffer is configured, test it also
+ */
+ if (InstancePtr->EmacLiteConfig.RxPingPong != 0) {
+ BaseAddress += XEL_BUFFER_OFFSET;
+ /*
+ * Write the TestString to the optional RX buffer in EMAC Lite
+ * then back from the EMAC Lite and verify
+ */
+ XEmacLite_AlignedWrite(TestString, (UINTPTR *) BaseAddress,
+ sizeof(TestString));
+ XEmacLite_AlignedRead((UINTPTR *) BaseAddress, ReturnString,
+ sizeof(ReturnString));
+
+ for (Index = 0; Index < 4; Index++) {
+
+ if (ReturnString[Index] != TestString[Index]) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Zero the return string for the next test
+ */
+ ReturnString[Index] = 0;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemaclite_sinit.c
+* @addtogroup emaclite_v4_1
+* @{
+*
+* This file contains the implementation of the XEmacLite driver's static
+* initialization functionality.
+*
+* @note None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.12a sv 11/28/07 First release
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xemaclite.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XEmacLite_Config XEmacLite_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Lookup the device configuration based on the unique device ID. The table
+* XEmacLite_ConfigTable contains the configuration info for each device in the
+* system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XEmacLite_Config *XEmacLite_LookupConfig(u16 DeviceId)
+{
+ XEmacLite_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0; Index < XPAR_XEMACLITE_NUM_INSTANCES; Index++) {
+ if (XEmacLite_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XEmacLite_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Initialize a specific XEmacLite instance/driver. The initialization entails:
+* - Initialize fields of the XEmacLite instance structure.
+*
+* The driver defaults to polled mode operation.
+*
+* @param InstancePtr is a pointer to the XEmacLite instance.
+* @param DeviceId is the unique id of the device controlled by this
+* XEmacLite instance. Passing in a device id associates the
+* generic XEmacLite instance to a specific device, as chosen by
+* the caller or application developer.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_NOT_FOUND/XST_FAILURE if device configuration
+* information was not found for a device with the supplied
+* device ID.
+*
+* @note None
+*
+******************************************************************************/
+int XEmacLite_Initialize(XEmacLite *InstancePtr, u16 DeviceId)
+{
+ int Status;
+ XEmacLite_Config *EmacLiteConfigPtr;/* Pointer to Configuration data. */
+
+ /*
+ * Verify that each of the inputs are valid.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Lookup the device configuration in the configuration table. Use this
+ * configuration info down below when initializing this driver.
+ */
+ EmacLiteConfigPtr = XEmacLite_LookupConfig(DeviceId);
+ if (EmacLiteConfigPtr == NULL) {
+ return XST_DEVICE_NOT_FOUND;
+ }
+
+ Status = XEmacLite_CfgInitialize(InstancePtr,
+ EmacLiteConfigPtr,
+ EmacLiteConfigPtr->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/** @} */
+++ /dev/null
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=xgpio_l.h xgpio.h
-
-LIBSOURCES=*.c
-OUTS = *.o
-
-
-libs:
- echo "Compiling gpio"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
- make clean
-
-include:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-clean:
- rm -rf ${OUTS}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio.c
-*
-* The implementation of the XGpio driver's basic functionality. See xgpio.h
-* for more information about the driver.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
-* CfgInitialize() take a pointer to a config structure
-* instead of a device id. Moved Initialize() into
-* xgpio_sinit.c, and had Initialize() call CfgInitialize()
-* after it retrieved the config structure using the device
-* id. Removed include of xparameters.h along with any
-* dependencies on xparameters.h and the _g.c config table.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
-* macros to remove _m from the name.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Initialize the XGpio instance provided by the caller based on the
-* given configuration data.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XGpio instance. The memory the
-* pointer references must be pre-allocated by the caller. Further
-* calls to manipulate the driver through the XGpio API must be
-* made with this pointer.
-* @param Config is a reference to a structure containing information
-* about a specific GPIO device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config. This function can initialize multiple
-* instance objects with the use of multiple calls giving different
-* Config information on each call.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* Config->BaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS Initialization was successfull.
-*
-* @note None.
-*
-*****************************************************************************/
-int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
- u32 EffectiveAddr)
-{
- /*
- * Assert arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Set some default values.
- */
-#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
- InstancePtr->BaseAddress = ((EffectiveAddr >> 2)) & 0xFFF;
-#else
- InstancePtr->BaseAddress = EffectiveAddr;
-#endif
-
- InstancePtr->InterruptPresent = Config->InterruptPresent;
- InstancePtr->IsDual = Config->IsDual;
-
- /*
- * Indicate the instance is now ready to use, initialized without error
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- return (XST_SUCCESS);
-}
-
-
-/****************************************************************************/
-/**
-* Set the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param DirectionMask is a bitmask specifying which discretes are input
-* and which are output. Bits set to 0 are output and bits set to 1
-* are input.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-void XGpio_SetDataDirection(XGpio * InstancePtr, unsigned Channel,
- u32 DirectionMask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
- DirectionMask);
-}
-
-/****************************************************************************/
-/**
-* Get the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Bitmask specifying which discretes are input and
-* which are output. Bits set to 0 are output and bits set to 1 are
-* input.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-*****************************************************************************/
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) &&
- (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Read state of discretes for the specified GPIO channnel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Current copy of the discretes register.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) +
- XGPIO_DATA_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Write to discretes register for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Data is the value to be written to the discretes register.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert. See also XGpio_DiscreteSet() and
-* XGpio_DiscreteClear().
-*
-*****************************************************************************/
-void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
- Data);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio.h
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* </pre>
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /* Unique ID of device */
- u32 BaseAddress; /* Device base address */
- int InterruptPresent; /* Are interrupts supported in h/w */
- int IsDual; /* Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- u32 BaseAddress; /* Device base address */
- u32 IsReady; /* Device is initialized and ready */
- int InterruptPresent; /* Are interrupts supported in h/w */
- int IsDual; /* Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- u32 EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_extra.c
-*
-* The implementation of the XGpio driver's advanced discrete functions.
-* See xgpio.h for more information about the driver.
-*
-* @note
-*
-* These APIs can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xgpio_i.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 1 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 1 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /*
- * Calculate the offset to the data register of the GPIO once
- */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current |= Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 0 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 0 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /*
- * Calculate the offset to the data register of the GPIO once
- */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current &= ~Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Driver configuration\r
-*\r
-*******************************************************************/\r
-\r
-#include "xparameters.h"\r
-#include "xgpio.h"\r
-\r
-/*\r
-* The configuration table for devices\r
-*/\r
-\r
-XGpio_Config XGpio_ConfigTable[] =\r
-{\r
- {\r
- XPAR_AXI_GPIO_0_DEVICE_ID,\r
- XPAR_AXI_GPIO_0_BASEADDR,\r
- XPAR_AXI_GPIO_0_INTERRUPT_PRESENT,\r
- XPAR_AXI_GPIO_0_IS_DUAL\r
- }\r
-};\r
-\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/******************************************************************************/
-/**
-* @file xgpio_i.h
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-* </pre>
-******************************************************************************/
-
-#ifndef XGPIO_I_H /* prevent circular inclusions */
-#define XGPIO_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions ****************************/
-
-extern XGpio_Config XGpio_ConfigTable[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_intr.c
-*
-* Implements GPIO interrupt processing functions for the XGpio driver.
-* See xgpio.h for more information about the driver.
-*
-* The functions in this file require the hardware device to be built with
-* interrupt capabilities. The functions will assert if called using hardware
-* that does not have interrupt capabilities.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.00a jhl 11/26/03 Initial release
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xgpio.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Enable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will not be passed through until the global enable
-* bit is set by this function. This function is designed to allow all
-* interrupts (both channels) to be enabled easily for exiting a critical
-* section. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalEnable(XGpio * InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
- XGPIO_GIE_GINTR_ENABLE_MASK);
-}
-
-
-/****************************************************************************/
-/**
-* Disable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will no longer be passed through until the global
-* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
-* designed to allow all interrupts (both channels) to be disabled easily for
-* entering a critical section. This function will assert if the hardware
-* device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalDisable(XGpio * InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
-
-}
-
-
-/****************************************************************************/
-/**
-* Enable interrupts. The global interrupt must also be enabled by calling
-* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
-* assert if the hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to enable. Bit positions of 1 are enabled.
-* This mask is formed by OR'ing bits from XGPIO_IR* bits which
-* are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only enable the specified
- * interrupts without disabling or enabling any others.
- */
-
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register | Mask);
-
-}
-
-
-/****************************************************************************/
-/**
-* Disable interrupts. This function allows specific interrupts for each
-* channel to be disabled. This function will assert if the hardware device
-* has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to disable. Bits set to 1 are disabled. This
-* mask is formed by OR'ing bits from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptDisable(XGpio * InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only disable the specified
- * interrupts without enabling or disabling any others.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register & (~Mask));
-
-}
-
-/****************************************************************************/
-/**
-* Clear pending interrupts with the provided mask. This function should be
-* called after the software has serviced the interrupts that are pending.
-* This function will assert if the hardware device has not been built with
-* interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to clear pending interrupts for. Bit positions
-* of 1 are cleared. This mask is formed by OR'ing bits from
-* XGPIO_IR* bits which are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt status register and only clear the interrupts
- * that are specified without affecting any others. Since the register
- * is a toggle on write, make sure any bits to be written are already
- * set.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
- Register & Mask);
-
-
-}
-
-
-/****************************************************************************/
-/**
-* Returns the interrupt enable mask. This function will assert if the
-* hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A mask of bits made from XGPIO_IR* bits which are contained in
-* xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-* Returns the status of interrupt signals. Any bit in the mask set to 1
-* indicates that the channel associated with the bit has asserted an interrupt
-* condition. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @note
-*
-* The interrupt status indicates the status of the device irregardless if
-* the interrupts from the devices have been enabled or not through
-* XGpio_InterruptEnable().
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/*
- * XPAR_XGPIO_USE_DCR_BRIDGE has to be set to 1 if the GPIO device is
- * accessed through a DCR bus connected to a bridge
- */
-#define XPAR_XGPIO_USE_DCR_BRIDGE 0
-
-
-#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
-#include "xio_dcr.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
-
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x1 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x2 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0x3 /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x47 /**< Global interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x48 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x4A /**< Interrupt enable register */
-
-#else
-
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-#endif
-
-/* @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/*@}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
-/*@}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
- /*
- * Define the appropriate I/O access method to memory mapped I/O or DCR.
- */
-#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0)
-
-#define XGpio_In32 XIo_DcrIn
-#define XGpio_Out32 XIo_DcrOut
-
-#else
-
-#define XGpio_In32 Xil_In32
-#define XGpio_Out32 Xil_Out32
-
-#endif
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_selftest.c
-*
-* The implementation of the XGpio driver's self test function.
-* See xgpio.h for more information about the driver.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/******************************************************************************/
-/**
-* Run a self-test on the driver/device. This function does a minimal test
-* in which the data register is read. It only does a read without any kind
-* of test because the hardware has been parameterized such that it may be only
-* an input such that the state of the inputs won't be known.
-*
-* All other hardware features of the device are not guaranteed to be in the
-* hardware since they are parameterizable.
-*
-*
-* @param InstancePtr is a pointer to the XGpio instance to be worked on.
-* This parameter must have been previously initialized with
-* XGpio_Initialize().
-*
-* @return XST_SUCCESS always. If the GPIO device was not present in the
-* hardware a bus error could be generated. Other indicators of a
-* bus error, such as registers in bridges or buses, may be
-* necessary to determine if this function caused a bus error.
-*
-* @note None.
-*
-******************************************************************************/
-int XGpio_SelfTest(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read from the data register of channel 1 which is always guaranteed
- * to be in the hardware device. Since the data may be configured as
- * all inputs, there is not way to guarantee the value read so don't
- * test it.
- */
- (void) XGpio_DiscreteRead(InstancePtr, 1);
-
- return (XST_SUCCESS);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2003 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xgpio_sinit.c
-*
-* The implementation of the XGpio driver's static initialzation
-* functionality.
-*
-* @note
-*
-* None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.01a jvb 10/13/05 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xgpio_i.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/******************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* ConfigTable contains the configuration info for each device in the system.
-*
-* @param DeviceId is the device identifier to lookup.
-*
-* @return
-* - A pointer of data type XGpio_Config which points to the
-* device configuration if DeviceID is found.
-* - NULL if DeviceID is not found.
-*
-* @note None.
-*
-******************************************************************************/
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId)
-{
- XGpio_Config *CfgPtr = NULL;
-
- int Index;
-
- for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) {
- if (XGpio_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XGpio_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-
-/****************************************************************************/
-/**
-* Initialize the XGpio instance provided by the caller based on the
-* given DeviceID.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XGpio instance. The memory the
-* pointer references must be pre-allocated by the caller. Further
-* calls to manipulate the instance/driver through the XGpio API
-* must be made with this pointer.
-* @param DeviceId is the unique id of the device controlled by this XGpio
-* instance. Passing in a device id associates the generic XGpio
-* instance to a specific device, as chosen by the caller or
-* application developer.
-*
-* @return
-* - XST_SUCCESS if the initialization was successfull.
-* - XST_DEVICE_NOT_FOUND if the device configuration data was not
-* found for a device with the supplied device ID.
-*
-* @note None.
-*
-*****************************************************************************/
-int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
-{
- XGpio_Config *ConfigPtr;
-
- /*
- * Assert arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Lookup configuration data in the device configuration table.
- * Use this configuration info down below when initializing this
- * driver.
- */
- ConfigPtr = XGpio_LookupConfig(DeviceId);
- if (ConfigPtr == (XGpio_Config *) NULL) {
- InstancePtr->IsReady = 0;
- return (XST_DEVICE_NOT_FOUND);
- }
-
- return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
- ConfigPtr->BaseAddress);
-}
--- /dev/null
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=xgpio_l.h xgpio.h
+
+LIBSOURCES=*.c
+OUTS = *.o
+
+
+libs:
+ echo "Compiling gpio"
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+ make clean
+
+include:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OUTS}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio.c
+* @addtogroup gpio_v4_1
+* @{
+*
+* The implementation of the XGpio driver's basic functionality. See xgpio.h
+* for more information about the driver.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm 02/04/02 First release
+* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
+* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
+* CfgInitialize() take a pointer to a config structure
+* instead of a device id. Moved Initialize() into
+* xgpio_sinit.c, and had Initialize() call CfgInitialize()
+* after it retrieved the config structure using the device
+* id. Removed include of xparameters.h along with any
+* dependencies on xparameters.h and the _g.c config table.
+* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
+* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
+* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
+* macros to remove _m from the name.
+* 4.1 lks 11/18/15 Clean up of the comments in the code and
+* removed support for DCR bridge
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xgpio.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Initialize the XGpio instance provided by the caller based on the
+* given configuration data.
+*
+* Nothing is done except to initialize the InstancePtr.
+*
+* @param InstancePtr is a pointer to an XGpio instance. The memory the
+* pointer references must be pre-allocated by the caller. Further
+* calls to manipulate the driver through the XGpio API must be
+* made with this pointer.
+* @param Config is a reference to a structure containing information
+* about a specific GPIO device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config. This function can initialize multiple
+* instance objects with the use of multiple calls giving different
+* Config information on each call.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* Config->BaseAddress for this parameters, passing the physical
+* address instead.
+*
+* @return
+* - XST_SUCCESS if the initialization is successfull.
+*
+* @note None.
+*
+*****************************************************************************/
+int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
+ u32 EffectiveAddr)
+{
+ /* Assert arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Set some default values. */
+ InstancePtr->BaseAddress = EffectiveAddr;
+
+ InstancePtr->InterruptPresent = Config->InterruptPresent;
+ InstancePtr->IsDual = Config->IsDual;
+
+ /*
+ * Indicate the instance is now ready to use, initialized without error
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ return (XST_SUCCESS);
+}
+
+
+/****************************************************************************/
+/**
+* Set the input/output direction of all discrete signals for the specified
+* GPIO channel.
+*
+* @param InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param DirectionMask is a bitmask specifying which discretes are input
+* and which are output. Bits set to 0 are output and bits set to 1
+* are input.
+*
+* @return None.
+*
+* @note The hardware must be built for dual channels if this function
+* is used with any channel other than 1. If it is not, this
+* function will assert.
+*
+*****************************************************************************/
+void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
+ u32 DirectionMask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((Channel == 1) ||
+ ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+ XGpio_WriteReg(InstancePtr->BaseAddress,
+ ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
+ DirectionMask);
+}
+
+/****************************************************************************/
+/**
+* Get the input/output direction of all discrete signals for the specified
+* GPIO channel.
+*
+* @param InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
+*
+* @return Bitmask specifying which discretes are input and
+* which are output. Bits set to 0 are output and bits set to 1 are
+* input.
+*
+* @note
+*
+* The hardware must be built for dual channels if this function is used
+* with any channel other than 1. If it is not, this function will assert.
+*
+*****************************************************************************/
+u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel == 1) ||
+ ((Channel == 2) &&
+ (InstancePtr->IsDual == TRUE)));
+
+ return XGpio_ReadReg(InstancePtr->BaseAddress,
+ ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
+}
+
+/****************************************************************************/
+/**
+* Read state of discretes for the specified GPIO channnel.
+*
+* @param InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
+*
+* @return Current copy of the discretes register.
+*
+* @note The hardware must be built for dual channels if this function
+* is used with any channel other than 1. If it is not, this
+* function will assert.
+*
+*****************************************************************************/
+u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel == 1) ||
+ ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+ return XGpio_ReadReg(InstancePtr->BaseAddress,
+ ((Channel - 1) * XGPIO_CHAN_OFFSET) +
+ XGPIO_DATA_OFFSET);
+}
+
+/****************************************************************************/
+/**
+* Write to discretes register for the specified GPIO channel.
+*
+* @param InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param Data is the value to be written to the discretes register.
+*
+* @return None.
+*
+* @note The hardware must be built for dual channels if this function
+* is used with any channel other than 1. If it is not, this
+* function will assert. See also XGpio_DiscreteSet() and
+* XGpio_DiscreteClear().
+*
+*****************************************************************************/
+void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((Channel == 1) ||
+ ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+ XGpio_WriteReg(InstancePtr->BaseAddress,
+ ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
+ Data);
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio.h
+* @addtogroup gpio_v4_1
+* @{
+* @details
+*
+* This file contains the software API definition of the Xilinx General Purpose
+* I/O (XGpio) device driver.
+*
+* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
+* contains the following general features:
+* - Support for up to 32 I/O discretes for each channel (64 bits total).
+* - Each of the discretes can be configured for input or output.
+* - Configurable support for dual channels and interrupt generation.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XGpio_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in one
+* of the following ways:
+*
+* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
+* configuration structure created by the tool-chain based on an ID provided
+* by the tool-chain.
+*
+* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
+* the unused bits from registers are read as zero and written as don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm 03/13/02 First release
+* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
+* 2.01a jvb 12/14/05 I separated dependency on the static config table and
+* xparameters.h from the driver initialization by moving
+* _Initialize and _LookupConfig to _sinit.c. I also added
+* the new _CfgInitialize routine.
+* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
+* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
+* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
+* to properly update the Interrupt Enable register
+* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
+* file
+* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
+* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
+* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
+* XGpio_mSetDataDirection, XGpio_mGetDataReg and
+* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
+* XGpio_ReadReg to achieve the same functionality.
+* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
+* xparameters.h. CR#698589
+* 4.0 adk 19/12/13 Updated as per the New Tcl API's
+* 4.1 lks 11/18/15 Updated to use cannonical xparameters in examples and
+* clean up of the comments, removed support for DCR bridge
+* and removed xgpio_intr_example for CR 900381
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XGPIO_H /* prevent circular inclusions */
+#define XGPIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xgpio_l.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /* Unique ID of device */
+ u32 BaseAddress; /* Device base address */
+ int InterruptPresent; /* Are interrupts supported in h/w */
+ int IsDual; /* Are 2 channels supported in h/w */
+} XGpio_Config;
+
+/**
+ * The XGpio driver instance data. The user is required to allocate a
+ * variable of this type for every GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ u32 BaseAddress; /* Device base address */
+ u32 IsReady; /* Device is initialized and ready */
+ int InterruptPresent; /* Are interrupts supported in h/w */
+ int IsDual; /* Are 2 channels supported in h/w */
+} XGpio;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xgpio_sinit.c
+ */
+int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
+XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
+
+/*
+ * API Basic functions implemented in xgpio.c
+ */
+int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
+ u32 EffectiveAddr);
+void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
+ u32 DirectionMask);
+u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
+u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
+void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+
+/*
+ * API Functions implemented in xgpio_extra.c
+ */
+void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+/*
+ * API Functions implemented in xgpio_selftest.c
+ */
+int XGpio_SelfTest(XGpio *InstancePtr);
+
+/*
+ * API Functions implemented in xgpio_intr.c
+ */
+void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
+void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
+void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
+u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
+u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_extra.c
+* @addtogroup gpio_v4_1
+* @{
+*
+* The implementation of the XGpio driver's advanced discrete functions.
+* See xgpio.h for more information about the driver.
+*
+* @note
+*
+* These APIs can only be used if the GPIO_IO ports in the IP are used for
+* connecting to the external output ports.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm 02/04/02 First release
+* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
+* 2.11a mta 03/21/07 Updated to new coding style
+* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
+* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
+* to XGpio_ReadReg.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xgpio.h"
+#include "xgpio_i.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Set output discrete(s) to logic 1 for the specified GPIO channel.
+*
+* @param InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param Mask is the set of bits that will be set to 1 in the discrete
+* data register. All other bits in the data register are
+* unaffected.
+*
+* @return None.
+*
+* @note
+*
+* The hardware must be built for dual channels if this function is used
+* with any channel other than 1. If it is not, this function will assert.
+*
+* This API can only be used if the GPIO_IO ports in the IP are used for
+* connecting to the external output ports.
+*
+*****************************************************************************/
+void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
+{
+ u32 Current;
+ unsigned DataOffset;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((Channel == 1) ||
+ ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+ /* Calculate the offset to the data register of the GPIO */
+ DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
+
+ /*
+ * Read the contents of the data register, merge in Mask and write
+ * back results
+ */
+ Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
+ Current |= Mask;
+ XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
+}
+
+
+/****************************************************************************/
+/**
+* Set output discrete(s) to logic 0 for the specified GPIO channel.
+*
+* @param InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param Mask is the set of bits that will be set to 0 in the discrete
+* data register. All other bits in the data register are
+* unaffected.
+*
+* @return None.
+*
+* @note
+*
+* The hardware must be built for dual channels if this function is used
+* with any channel other than 1. If it is not, this function will assert.
+*
+* This API can only be used if the GPIO_IO ports in the IP are used for
+* connecting to the external output ports.
+*
+*****************************************************************************/
+void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
+{
+ u32 Current;
+ unsigned DataOffset;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((Channel == 1) ||
+ ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+ /* Calculate the offset to the data register of the GPIO */
+ DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
+
+ /*
+ * Read the contents of the data register, merge in Mask and write
+ * back results
+ */
+ Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
+ Current &= ~Mask;
+ XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
+}
+/** @} */
--- /dev/null
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Driver configuration\r
+*\r
+*******************************************************************/\r
+\r
+#include "xparameters.h"\r
+#include "xgpio.h"\r
+\r
+/*\r
+* The configuration table for devices\r
+*/\r
+\r
+XGpio_Config XGpio_ConfigTable[] =\r
+{\r
+ {\r
+ XPAR_AXI_GPIO_0_DEVICE_ID,\r
+ XPAR_AXI_GPIO_0_BASEADDR,\r
+ XPAR_AXI_GPIO_0_INTERRUPT_PRESENT,\r
+ XPAR_AXI_GPIO_0_IS_DUAL\r
+ }\r
+};\r
+\r
+\r
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+* @file xgpio_i.h
+* @addtogroup gpio_v4_1
+* @{
+*
+* This header file contains internal identifiers, which are those shared
+* between the files of the driver. It is intended for internal use only.
+*
+* NOTES:
+*
+* None.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm 03/13/02 First release
+* 2.11a mta 03/21/07 Updated to new coding style
+* </pre>
+******************************************************************************/
+
+#ifndef XGPIO_I_H /* prevent circular inclusions */
+#define XGPIO_I_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xgpio.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions ****************************/
+
+extern XGpio_Config XGpio_ConfigTable[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_intr.c
+* @addtogroup gpio_v4_1
+* @{
+*
+* Implements GPIO interrupt processing functions for the XGpio driver.
+* See xgpio.h for more information about the driver.
+*
+* The functions in this file require the hardware device to be built with
+* interrupt capabilities. The functions will assert if called using hardware
+* that does not have interrupt capabilities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.00a jhl 11/26/03 Initial release
+* 2.11a mta 03/21/07 Updated to new coding style
+* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
+* to properly update the Interrupt Enable register
+* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
+* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
+* to XGpio_ReadReg.
+
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xgpio.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Enable the interrupt output signal. Interrupts enabled through
+* XGpio_InterruptEnable() will not be passed through until the global enable
+* bit is set by this function. This function is designed to allow all
+* interrupts (both channels) to be enabled easily for exiting a critical
+* section. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param InstancePtr is the GPIO instance to operate on.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+ XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
+ XGPIO_GIE_GINTR_ENABLE_MASK);
+}
+
+
+/****************************************************************************/
+/**
+* Disable the interrupt output signal. Interrupts enabled through
+* XGpio_InterruptEnable() will no longer be passed through until the global
+* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
+* designed to allow all interrupts (both channels) to be disabled easily for
+* entering a critical section. This function will assert if the hardware
+* device has not been built with interrupt capabilities.
+*
+* @param InstancePtr is the GPIO instance to operate on.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+
+ XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
+
+}
+
+
+/****************************************************************************/
+/**
+* Enable interrupts. The global interrupt must also be enabled by calling
+* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
+* assert if the hardware device has not been built with interrupt capabilities.
+*
+* @param InstancePtr is the GPIO instance to operate on.
+* @param Mask is the mask to enable. Bit positions of 1 are enabled.
+* This mask is formed by OR'ing bits from XGPIO_IR* bits which
+* are contained in xgpio_l.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+ /*
+ * Read the interrupt enable register and only enable the specified
+ * interrupts without disabling or enabling any others.
+ */
+
+ Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
+ XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
+ Register | Mask);
+
+}
+
+
+/****************************************************************************/
+/**
+* Disable interrupts. This function allows specific interrupts for each
+* channel to be disabled. This function will assert if the hardware device
+* has not been built with interrupt capabilities.
+*
+* @param InstancePtr is the GPIO instance to operate on.
+* @param Mask is the mask to disable. Bits set to 1 are disabled. This
+* mask is formed by OR'ing bits from XGPIO_IR* bits which are
+* contained in xgpio_l.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+ /*
+ * Read the interrupt enable register and only disable the specified
+ * interrupts without enabling or disabling any others.
+ */
+ Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
+ XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
+ Register & (~Mask));
+
+}
+
+/****************************************************************************/
+/**
+* Clear pending interrupts with the provided mask. This function should be
+* called after the software has serviced the interrupts that are pending.
+* This function will assert if the hardware device has not been built with
+* interrupt capabilities.
+*
+* @param InstancePtr is the GPIO instance to operate on.
+* @param Mask is the mask to clear pending interrupts for. Bit positions
+* of 1 are cleared. This mask is formed by OR'ing bits from
+* XGPIO_IR* bits which are contained in xgpio_l.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+ /*
+ * Read the interrupt status register and only clear the interrupts
+ * that are specified without affecting any others. Since the register
+ * is a toggle on write, make sure any bits to be written are already
+ * set.
+ */
+ Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
+ XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
+ Register & Mask);
+
+
+}
+
+
+/****************************************************************************/
+/**
+* Returns the interrupt enable mask. This function will assert if the
+* hardware device has not been built with interrupt capabilities.
+*
+* @param InstancePtr is the GPIO instance to operate on.
+*
+* @return A mask of bits made from XGPIO_IR* bits which are contained in
+* xgpio_l.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
+
+ return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+* Returns the status of interrupt signals. Any bit in the mask set to 1
+* indicates that the channel associated with the bit has asserted an interrupt
+* condition. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param InstancePtr is the GPIO instance to operate on.
+*
+* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
+* contained in xgpio_l.h.
+*
+* @note
+*
+* The interrupt status indicates the status of the device irregardless if
+* the interrupts from the devices have been enabled or not through
+* XGpio_InterruptEnable().
+*
+*****************************************************************************/
+u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
+
+
+ return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpio_l.h
+* @addtogroup gpio_v4_1
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* The macros that are available in this file use a multiply to calculate the
+* addresses of registers. The user can control whether that multiply is done
+* at run time or at compile time. A constant passed as the channel parameter
+* will cause the multiply to be done at compile time. A variable passed as the
+* channel parameter will cause it to occur at run time.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a jhl 04/24/02 First release of low level driver
+* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
+* change required the functions to be changed such that
+* the interface is not compatible with previous versions.
+* See the examples in the example directory for macros
+* to help compile an application that was designed for
+* previous versions of the driver. The interrupt registers
+* are accessible using the ReadReg and WriteReg macros and
+* a channel parameter was added to the other macros.
+* 2.11a mta 03/21/07 Updated to new coding style
+* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
+* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
+* XGpio_mReadReg to XGpio_ReadReg.
+* Removed the macros XGpio_mSetDataDirection,
+* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
+* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
+* same functionality.
+* 4.1 lks 11/18/15 Removed support for DCR bridge
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XGPIO_L_H /* prevent circular inclusions */
+#define XGPIO_L_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
+#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
+#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
+#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
+
+#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
+#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
+#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
+
+/* @} */
+
+/* The following constant describes the offset of each channels data and
+ * tristate register from the base address.
+ */
+#define XGPIO_CHAN_OFFSET 8
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the interrupt status register and interrupt enable
+ * registers.
+ * @{
+ */
+#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
+#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
+#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
+/*@}*/
+
+
+/** @name Global Interrupt Enable Register bitmaps and masks
+ *
+ * Bit definitions for the Global Interrupt Enable register
+ * @{
+ */
+#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
+/*@}*/
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XGpio_In32 Xil_In32
+#define XGpio_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a GPIO register. A 32 bit write is performed. If the
+* GPIO core is implemented in a smaller width, only the least significant data
+* is written.
+*
+* @param BaseAddress is the base address of the GPIO device.
+* @param RegOffset is the register offset from the base to write to.
+* @param Data is the data written to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
+ XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a GPIO register. A 32 bit read is performed. If the
+* GPIO core is implemented in a smaller width, only the least
+* significant data is read from the register. The most significant data
+* will be read as 0.
+*
+* @param BaseAddress is the base address of the GPIO device.
+* @param RegOffset is the register offset from the base to read from.
+*
+* @return Data read from the register.
+*
+* @note C-style signature:
+* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XGpio_ReadReg(BaseAddress, RegOffset) \
+ XGpio_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_selftest.c
+* @addtogroup gpio_v4_1
+* @{
+*
+* The implementation of the XGpio driver's self test function.
+* See xgpio.h for more information about the driver.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm 02/04/02 First release
+* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
+* 2.11a mta 03/21/07 Updated to new coding style
+* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xgpio.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/******************************************************************************/
+/**
+* Run a self-test on the driver/device. This function does a minimal test
+* in which the data register is read. It only does a read without any kind
+* of test because the hardware has been parameterized such that it may be only
+* an input such that the state of the inputs won't be known.
+*
+* All other hardware features of the device are not guaranteed to be in the
+* hardware since they are parameterizable.
+*
+*
+* @param InstancePtr is a pointer to the XGpio instance to be worked on.
+* This parameter must have been previously initialized with
+* XGpio_Initialize().
+*
+* @return XST_SUCCESS always. If the GPIO device was not present in the
+* hardware a bus error could be generated. Other indicators of a
+* bus error, such as registers in bridges or buses, may be
+* necessary to determine if this function caused a bus error.
+*
+* @note None.
+*
+******************************************************************************/
+int XGpio_SelfTest(XGpio * InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read from the data register of channel 1 which is always guaranteed
+ * to be in the hardware device. Since the data may be configured as
+ * all inputs, there is not way to guarantee the value read so don't
+ * test it.
+ */
+ (void) XGpio_DiscreteRead(InstancePtr, 1);
+
+ return (XST_SUCCESS);
+}
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_sinit.c
+* @addtogroup gpio_v4_1
+* @{
+*
+* The implementation of the XGpio driver's static initialzation
+* functionality.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.01a jvb 10/13/05 First release
+* 2.11a mta 03/21/07 Updated to new coding style
+* 4.0 sha 07/15/15 Defined macro XPAR_XGPIO_NUM_INSTANCES if not
+* defined in xparameters.h
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xgpio_i.h"
+
+/************************** Constant Definitions ****************************/
+
+#ifndef XPAR_XGPIO_NUM_INSTANCES
+#define XPAR_XGPIO_NUM_INSTANCES 0
+#endif
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/******************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* ConfigTable contains the configuration info for each device in the system.
+*
+* @param DeviceId is the device identifier to lookup.
+*
+* @return
+* - A pointer of data type XGpio_Config which points to the
+* device configuration if DeviceID is found.
+* - NULL if DeviceID is not found.
+*
+* @note None.
+*
+******************************************************************************/
+XGpio_Config *XGpio_LookupConfig(u16 DeviceId)
+{
+ XGpio_Config *CfgPtr = NULL;
+
+ int Index;
+
+ for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) {
+ if (XGpio_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XGpio_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+
+
+/****************************************************************************/
+/**
+* Initialize the XGpio instance provided by the caller based on the
+* given DeviceID.
+*
+* Nothing is done except to initialize the InstancePtr.
+*
+* @param InstancePtr is a pointer to an XGpio instance. The memory the
+* pointer references must be pre-allocated by the caller. Further
+* calls to manipulate the instance/driver through the XGpio API
+* must be made with this pointer.
+* @param DeviceId is the unique id of the device controlled by this XGpio
+* instance. Passing in a device id associates the generic XGpio
+* instance to a specific device, as chosen by the caller or
+* application developer.
+*
+* @return
+* - XST_SUCCESS if the initialization was successfull.
+* - XST_DEVICE_NOT_FOUND if the device configuration data was not
+* found for a device with the supplied device ID.
+*
+* @note None.
+*
+*****************************************************************************/
+int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
+{
+ XGpio_Config *ConfigPtr;
+
+ /*
+ * Assert arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Lookup configuration data in the device configuration table.
+ * Use this configuration info down below when initializing this
+ * driver.
+ */
+ ConfigPtr = XGpio_LookupConfig(DeviceId);
+ if (ConfigPtr == (XGpio_Config *) NULL) {
+ InstancePtr->IsReady = 0;
+ return (XST_DEVICE_NOT_FOUND);
+ }
+
+ return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
+ ConfigPtr->BaseAddress);
+}
+/** @} */
+++ /dev/null
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-LEVEL=0
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-
-OUTS = *.o
-
-libs:
- echo "Compiling intc"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OUTS}
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc.c
-*
-* Contains required functions for the XIntc driver for the Xilinx Interrupt
-* Controller. See xintc.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a ecm 08/16/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.00b jhl 04/24/02 Made LookupConfig global and compressed ack before table
-* in the configuration into a bit mask
-* 1.00c rpm 10/17/03 New release. Support the static vector table created
-* in the xintc_g.c configuration table.
-* 1.00c rpm 04/23/04 Removed check in XIntc_Connect for a previously connected
-* handler. Always overwrite the vector table handler with
-* the handler provided as an argument.
-* 1.10c mta 03/21/07 Updated to new coding style
-* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
-* 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
-* and XIntc_SetNormalIntrMode for setting to normal
-* interrupt mode.
-* 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
-* updated XIntc_SetNormalIntrMode to use IntVectorAddr
-* which is the interrupt vector address
-* 2.06a bss 01/28/13 To support Cascade mode:
-* Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
-* XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
-* XIntc_Acknowledge,XIntc_ConnectFastHandler and
-* XIntc_SetNormalIntrMode APIs.
-* Added XIntc_InitializeSlaves API.
-* 3.0 bss 01/28/13 Modified to initialize IVAR register with
-* XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
-* CR#765931
-*
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xintc.h"
-#include "xintc_l.h"
-#include "xintc_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Variable Definitions *****************************/
-
-/*
- * Array of masks associated with the bit position, improves performance
- * in the ISR and acknowledge functions, this table is shared between all
- * instances of the driver. XIN_CONTROLLER_MAX_INTRS is the maximum number of
- * sources of Interrupt controller
- */
-u32 XIntc_BitPosMask[XIN_CONTROLLER_MAX_INTRS];
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void *CallBackRef);
-static void XIntc_InitializeSlaves(XIntc * InstancePtr);
-
-/*****************************************************************************/
-/**
-*
-* Initialize a specific interrupt controller instance/driver. The
-* initialization entails:
-*
-* - Initialize fields of the XIntc structure
-* - Initial vector table with stub function calls
-* - All interrupt sources are disabled
-* - Interrupt output is disabled
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param DeviceId is the unique id of the device controlled by this XIntc
-* instance. Passing in a device id associates the generic XIntc
-* instance to a specific device, as chosen by the caller or
-* application developer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_DEVICE_IS_STARTED if the device has already been started
-* - XST_DEVICE_NOT_FOUND if device configuration information was
-* not found for a device with the supplied device ID.
-*
-* @note In Cascade mode this function calls XIntc_InitializeSlaves to
-* initialiaze Slave Interrupt controllers.
-*
-******************************************************************************/
-int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId)
-{
- u8 Id;
- XIntc_Config *CfgPtr;
- u32 NextBitMask = 1;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * If the device is started, disallow the initialize and return a status
- * indicating it is started. This allows the user to stop the device
- * and reinitialize, but prevents a user from inadvertently initializing
- */
- if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Lookup the device configuration in the CROM table. Use this
- * configuration info down below when initializing this component.
- */
- CfgPtr = XIntc_LookupConfig(DeviceId);
- if (CfgPtr == NULL) {
- return XST_DEVICE_NOT_FOUND;
- }
-
- /*
- * Set some default values
- */
- InstancePtr->IsReady = 0;
- InstancePtr->IsStarted = 0; /* not started */
- InstancePtr->CfgPtr = CfgPtr;
-
- InstancePtr->CfgPtr->Options = XIN_SVC_SGL_ISR_OPTION;
- InstancePtr->CfgPtr->IntcType = CfgPtr->IntcType;
-
- /*
- * Save the base address pointer such that the registers of the
- * interrupt can be accessed
- */
-#if (XPAR_XINTC_USE_DCR_BRIDGE != 0)
- InstancePtr->BaseAddress = ((CfgPtr->BaseAddress >> 2)) & 0xFFF;
-#else
- InstancePtr->BaseAddress = CfgPtr->BaseAddress;
-#endif
-
- /*
- * Initialize all the data needed to perform interrupt processing for
- * each interrupt ID up to the maximum used
- */
- for (Id = 0; Id < CfgPtr->NumberofIntrs; Id++) {
-
- /*
- * Initalize the handler to point to a stub to handle an
- * interrupt which has not been connected to a handler. Only
- * initialize it if the handler is 0 or XNullHandler, which
- * means it was not initialized statically by the tools/user.
- * Set the callback reference to this instance so that
- * unhandled interrupts can be tracked.
- */
- if ((InstancePtr->CfgPtr->HandlerTable[Id].Handler == 0) ||
- (InstancePtr->CfgPtr->HandlerTable[Id].Handler ==
- XNullHandler)) {
- InstancePtr->CfgPtr->HandlerTable[Id].Handler =
- StubHandler;
- }
- InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;
-
- /*
- * Initialize the bit position mask table such that bit
- * positions are lookups only for each interrupt id, with 0
- * being a special case
- * (XIntc_BitPosMask[] = { 1, 2, 4, 8, ... })
- */
- XIntc_BitPosMask[Id] = NextBitMask;
- NextBitMask *= 2;
- }
-
- /*
- * Disable IRQ output signal
- * Disable all interrupt sources
- * Acknowledge all sources
- */
- XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0);
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, 0);
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, 0xFFFFFFFF);
-
- /*
- * If the fast Interrupt mode is enabled then set all the
- * interrupts as normal mode.
- */
- if(InstancePtr->CfgPtr->FastIntr == TRUE) {
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, 0);
-
-#ifdef XPAR_MICROBLAZE_BASE_VECTORS
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
- + (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
- + 0x10);
- }
-#else
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
- + (Id * 4), 0x10);
- }
-#endif
- }
-
- /* Initialize slaves in Cascade mode*/
- if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
- XIntc_InitializeSlaves(InstancePtr);
- }
-
- /*
- * Indicate the instance is now ready to use, successfully initialized
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Starts the interrupt controller by enabling the output from the controller
-* to the processor. Interrupts may be generated by the interrupt controller
-* after this function is called.
-*
-* It is necessary for the caller to connect the interrupt handler of this
-* component to the proper interrupt source. This function also starts Slave
-* controllers in Cascade mode.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Mode determines if software is allowed to simulate interrupts or
-* real interrupts are allowed to occur. Note that these modes are
-* mutually exclusive. The interrupt controller hardware resets in
-* a mode that allows software to simulate interrupts until this
-* mode is exited. It cannot be reentered once it has been exited.
-*
-* One of the following values should be used for the mode.
-* - XIN_SIMULATION_MODE enables simulation of interrupts only
-* - XIN_REAL_MODE enables hardware interrupts only
-*
-* @return
-* - XST_SUCCESS if the device was started successfully
-* - XST_FAILURE if simulation mode was specified and it could not
-* be set because real mode has already been entered.
-*
-* @note Must be called after XIntc initialization is completed.
-*
-******************************************************************************/
-int XIntc_Start(XIntc * InstancePtr, u8 Mode)
-{
- u32 MasterEnable = XIN_INT_MASTER_ENABLE_MASK;
- XIntc_Config *CfgPtr;
- int Index;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid((Mode == XIN_SIMULATION_MODE) ||
- (Mode == XIN_REAL_MODE))
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check for simulation mode
- */
- if (Mode == XIN_SIMULATION_MODE) {
- if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
- return XST_FAILURE;
- }
- }
- else {
- MasterEnable |= XIN_INT_HARDWARE_ENABLE_MASK;
- }
-
- /*
- * Indicate the instance is ready to be used and is started before we
- * enable the device.
- */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-
- /* Start the Slaves for Cascade Mode */
- if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
- for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++)
- {
- CfgPtr = XIntc_LookupConfig(Index);
- XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET,
- MasterEnable);
- }
- }
-
- /* Start the master */
- XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, MasterEnable);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Stops the interrupt controller by disabling the output from the controller
-* so that no interrupts will be caused by the interrupt controller.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIntc_Stop(XIntc * InstancePtr)
-{
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Stop all interrupts from occurring thru the interrupt controller by
- * disabling all interrupts in the MER register
- */
- XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0);
-
- InstancePtr->IsStarted = 0;
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Id of the interrupt source and the
-* associated handler that is to run when the interrupt is recognized. The
-* argument provided in this call as the Callbackref is used as the argument
-* for the handler when it is called. In Cascade mode, connects handler to
-* Slave controller handler table depending on the interrupt Id.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id contains the ID of the interrupt source and should be in the
-* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
-* the highest priority interrupt.
-* @param Handler to the handler for that interrupt.
-* @param CallBackRef is the callback reference, usually the instance
-* pointer of the connecting driver.
-*
-* @return
-*
-* - XST_SUCCESS if the handler was connected correctly.
-*
-* @note
-*
-* WARNING: The handler provided as an argument will overwrite any handler
-* that was previously connected.
-*
-****************************************************************************/
-int XIntc_Connect(XIntc * InstancePtr, u8 Id,
- XInterruptHandler Handler, void *CallBackRef)
-{
- XIntc_Config *CfgPtr;
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
- Xil_AssertNonvoid(Handler != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Connect Handlers for Slave controllers in Cascade Mode */
- if (Id > 31) {
-
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- CfgPtr->HandlerTable[Id%32].Handler = Handler;
- CfgPtr->HandlerTable[Id%32].CallBackRef = CallBackRef;
- }
- /* Connect Handlers for Master/primary controller */
- else {
- /*
- * The Id is used as an index into the table to select the
- * proper handler
- */
- InstancePtr->CfgPtr->HandlerTable[Id].Handler = Handler;
- InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef =
- CallBackRef;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Updates the interrupt table with the Null Handler and NULL arguments at the
-* location pointed at by the Id. This effectively disconnects that interrupt
-* source from any handler. The interrupt is disabled also. In Cascade mode,
-* disconnects handler from Slave controller handler table depending on the
-* interrupt Id.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id contains the ID of the interrupt source and should be in the
-* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
-* the highest priority interrupt.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIntc_Disconnect(XIntc * InstancePtr, u8 Id)
-{
- u32 CurrentIER;
- u32 Mask;
- XIntc_Config *CfgPtr;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the interrupt such that it won't occur while disconnecting
- * the handler, only disable the specified interrupt id without
- * modifying the other interrupt ids
- */
-
- /* Disconnect Handlers for Slave controllers in Cascade Mode */
- if (Id > 31) {
-
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[(Id%32)];
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER & ~Mask));
- /*
- * Disconnect the handler and connect a stub, the callback
- * reference must be set to this instance to allow unhandled
- * interrupts to be tracked
- */
- CfgPtr->HandlerTable[Id%32].Handler = StubHandler;
- CfgPtr->HandlerTable[Id%32].CallBackRef = InstancePtr;
- }
- /* Disconnect Handlers for Master/primary controller */
- else {
- CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
- XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[Id];
-
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER & ~Mask));
- InstancePtr->CfgPtr->HandlerTable[Id%32].Handler =
- StubHandler;
- InstancePtr->CfgPtr->HandlerTable[Id%32].CallBackRef =
- InstancePtr;
- }
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Enables the interrupt source provided as the argument Id. Any pending
-* interrupt condition for the specified Id will occur after this function is
-* called. In Cascade mode, enables corresponding interrupt of Slave controllers
-* depending on the Id.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id contains the ID of the interrupt source and should be in the
-* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
-* the highest priority interrupt.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIntc_Enable(XIntc * InstancePtr, u8 Id)
-{
- u32 CurrentIER;
- u32 Mask;
- XIntc_Config *CfgPtr;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (Id > 31) {
-
- /* Enable user required Id in Slave controller */
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[(Id%32)];
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER | Mask));
- }
- else {
- /*
- * The Id is used to create the appropriate mask for the
- * desired bit position.
- */
- Mask = XIntc_BitPosMask[Id];
-
- /*
- * Enable the selected interrupt source by reading the
- * interrupt enable register and then modifying only the
- * specified interrupt id enable
- */
- CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
- XIN_IER_OFFSET);
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER | Mask));
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupt source provided as the argument Id such that the
-* interrupt controller will not cause interrupts for the specified Id. The
-* interrupt controller will continue to hold an interrupt condition for the
-* Id, but will not cause an interrupt.In Cascade mode, disables corresponding
-* interrupt of Slave controllers depending on the Id.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id contains the ID of the interrupt source and should be in the
-* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the
-* highest priority interrupt.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIntc_Disable(XIntc * InstancePtr, u8 Id)
-{
- u32 CurrentIER;
- u32 Mask;
- XIntc_Config *CfgPtr;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (Id > 31) {
- /* Enable user required Id in Slave controller */
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[(Id%32)];
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER & ~Mask));
- } else {
- /*
- * The Id is used to create the appropriate mask for the
- * desired bit position. Id currently limited to 0 - 31
- */
- Mask = XIntc_BitPosMask[Id];
-
- /*
- * Disable the selected interrupt source by reading the
- * interrupt enable register and then modifying only the
- * specified interrupt id
- */
- CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
- XIN_IER_OFFSET);
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER & ~Mask));
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Acknowledges the interrupt source provided as the argument Id. When the
-* interrupt is acknowledged, it causes the interrupt controller to clear its
-* interrupt condition.In Cascade mode, acknowledges corresponding interrupt
-* source of Slave controllers depending on the Id.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id contains the ID of the interrupt source and should be in the
-* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
-* the highest priority interrupt.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id)
-{
- u32 Mask;
- XIntc_Config *CfgPtr;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (Id > 31) {
- /* Enable user required Id in Slave controller */
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[(Id%32)];
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, Mask);
- } else {
- /*
- * The Id is used to create the appropriate mask for the
- * desired bit position.
- */
- Mask = XIntc_BitPosMask[Id];
-
- /*
- * Acknowledge the selected interrupt source, no read of the
- * acknowledge register is necessary since only the bits set
- * in the mask will be affected by the write
- */
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Mask);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* A stub for the asynchronous callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubHandler(void *CallBackRef)
-{
- /*
- * Verify that the inputs are valid
- */
- Xil_AssertVoid(CallBackRef != NULL);
-
- /*
- * Indicate another unhandled interrupt for stats
- */
- ((XIntc *) CallBackRef)->UnhandledInterrupts++;
-}
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique identifier for a device.
-*
-* @return A pointer to the XIntc configuration structure for the specified
-* device, or NULL if the device was not found.
-*
-* @note None.
-*
-******************************************************************************/
-XIntc_Config *XIntc_LookupConfig(u16 DeviceId)
-{
- XIntc_Config *CfgPtr = NULL;
- int Index;
-
- for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
- if (XIntc_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XIntc_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Id of the interrupt source and the
-* associated handler that is to run when the interrupt is recognized.In Cascade
-* mode, connects handler to corresponding Slave controller IVAR register
-* depending on the Id and sets all interrupt sources of the Slave controller as
-* fast interrupts.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id contains the ID of the interrupt source and should be in the
-* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
-* the highest priority interrupt.
-* @param Handler to the handler for that interrupt.
-*
-* @return
-* - XST_SUCCESS
-*
-* @note
-* Slave controllers in Cascade Mode should have all as Fast
-* interrupts or Normal interrupts, mixed interrupts are not
-* supported
-*
-* WARNING: The handler provided as an argument will overwrite any handler
-* that was previously connected.
-*
-****************************************************************************/
-int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
- XFastInterruptHandler Handler)
-{
- u32 Imr;
- u32 CurrentIER;
- u32 Mask;
- XIntc_Config *CfgPtr;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
- Xil_AssertNonvoid(Handler != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->CfgPtr->FastIntr == TRUE);
-
-
- if (Id > 31) {
- /* Enable user required Id in Slave controller */
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- if (CfgPtr->FastIntr != TRUE) {
- /*Fast interrupts of slave controller are not enabled*/
- return XST_FAILURE;
- }
-
- /* Get the Enabled Interrupts */
- CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[(Id%32)];
-
- /* Disable the Interrupt if it was enabled before calling
- * this function
- */
- if (CurrentIER & Mask) {
- XIntc_Disable(InstancePtr, Id);
- }
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
- ((Id%32) * 4), (u32) Handler);
-
- /* Slave controllers in Cascade Mode should have all as Fast
- * interrupts or Normal interrupts, mixed interrupts are not
- * supported
- */
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
-
- /* Enable the Interrupt if it was enabled before calling this
- * function
- */
- if (CurrentIER & Mask) {
- XIntc_Enable(InstancePtr, Id);
- }
- }
- else {
- /* Get the Enabled Interrupts */
- CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
- XIN_IER_OFFSET);
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[Id];
-
- /* Disable the Interrupt if it was enabled before calling
- * this function
- */
- if (CurrentIER & Mask) {
- XIntc_Disable(InstancePtr, Id);
- }
-
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET +
- (Id * 4), (u32) Handler);
-
- Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
- Imr | Mask);
-
- /* Enable the Interrupt if it was enabled before
- * calling this function
- */
- if (CurrentIER & Mask) {
- XIntc_Enable(InstancePtr, Id);
- }
-
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Sets the normal interrupt mode for the specified interrupt in the Interrupt
-* Mode Register. In Cascade mode disconnects handler from corresponding Slave
-* controller IVAR register depending on the Id and sets all interrupt sources
-* of the Slave controller as normal interrupts.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id contains the ID of the interrupt source and should be in the
-* range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the
-* highest priority interrupt.
-*
-* @return None.
-*
-* @note
-* Slave controllers in Cascade Mode should have all as Fast
-* interrupts or Normal interrupts, mixed interrupts are not
-* supported
-*
-****************************************************************************/
-void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id)
-{
- u32 Imr;
- u32 CurrentIER;
- u32 Mask;
- XIntc_Config *CfgPtr;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->CfgPtr->FastIntr == TRUE);
-
- if (Id > 31) {
- /* Enable user required Id in Slave controller */
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- /* Get the Enabled Interrupts */
- CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[(Id%32)];
-
- /* Disable the Interrupt if it was enabled before calling
- * this function
- */
- if (CurrentIER & Mask) {
- XIntc_Disable(InstancePtr, Id);
- }
-
- /* Slave controllers in Cascade Mode should have all as Fast
- * interrupts or Normal interrupts, mixed interrupts are not
- * supported
- */
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0x0);
-
-#ifdef XPAR_MICROBLAZE_BASE_VECTORS
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
- + (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
- + 0x10);
- }
-#else
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
- + (Id * 4), 0x10);
- }
-#endif
-
- /* Enable the Interrupt if it was enabled before calling this
- * function
- */
- if (CurrentIER & Mask) {
- XIntc_Enable(InstancePtr, Id);
- }
-
- }
- else {
-
- /* Get the Enabled Interrupts */
- CurrentIER = XIntc_In32(InstancePtr->BaseAddress + XIN_IER_OFFSET);
- Mask = XIntc_BitPosMask[Id];/* Convert from integer id to bit mask */
-
-
- /* Disable the Interrupt if it was enabled before
- * calling this function
- */
- if (CurrentIER & Mask) {
- XIntc_Disable(InstancePtr, Id);
- }
-
- /*
- * Disable the selected interrupt as Fast Interrupt by reading the
- * interrupt mode register and then modifying only the
- * specified interrupt id
- */
- Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
- Imr & ~Mask);
-
-#ifdef XPAR_MICROBLAZE_BASE_VECTORS
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
- + (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
- + 0x10);
- }
-#else
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
- + (Id * 4), 0x10);
- }
-#endif
- /* Enable the Interrupt if it was enabled before
- * calling this function
- */
- if (CurrentIER & Mask) {
- XIntc_Enable(InstancePtr, Id);
- }
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Initializes Slave controllers in Cascade mode. The initialization entails:
-* - Initial vector table with stub function calls
-* - All interrupt sources are disabled for last controller.
-* - All interrupt sources are disabled except sources to 31 pin of
-* primary and secondary controllers
-* - Interrupt outputs are disabled
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void XIntc_InitializeSlaves(XIntc * InstancePtr)
-{
- int Index;
- u32 Mask;
- XIntc_Config *CfgPtr;
- int Id;
-
- Mask = XIntc_BitPosMask[31]; /* Convert from integer id to bit mask */
-
- /* Enable interrupt id with 31 for Master
- * interrupt controller
- */
- XIntc_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IER_OFFSET, Mask);
-
- for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++) {
- CfgPtr = XIntc_LookupConfig(Index);
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET,
- 0xFFFFFFFF);
- if (CfgPtr->IntcType != XIN_INTC_LAST) {
-
- /* Enable interrupt ids with 31 for secondary
- * interrupt controllers
- */
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
- Mask);
- } else {
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, 0x0);
- }
-
- /* Disable Interrupt output */
- XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET, 0);
-
- /* Set all interrupts as normal mode if Fast Interrupts
- * are enabled
- */
- if(CfgPtr->FastIntr == TRUE) {
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0);
-
-#ifdef XPAR_MICROBLAZE_BASE_VECTORS
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(CfgPtr->BaseAddress +
- XIN_IVAR_OFFSET + (Id * 4),
- XPAR_MICROBLAZE_BASE_VECTORS + 0x10);
- }
-#else
- for (Id = 0; Id < 32 ; Id++)
- {
- XIntc_Out32(CfgPtr->BaseAddress +
- XIN_IVAR_OFFSET + (Id * 4), 0x10);
- }
-#endif
- }
-
- /*
- * Initialize all the data needed to perform interrupt
- * processing for each interrupt ID up to the maximum used
- */
- for (Id = 0; Id < CfgPtr->NumberofIntrs; Id++) {
-
- /*
- * Initalize the handler to point to a stub to handle an
- * interrupt which has not been connected to a handler.
- * Only initialize it if the handler is 0 or
- * XNullHandler, which means it was not initialized
- * statically by the tools/user.Set the callback
- * reference to this instance so that unhandled
- * interrupts can be tracked.
- */
- if ((CfgPtr->HandlerTable[Id].Handler == 0) ||
- (CfgPtr->HandlerTable[Id].Handler ==
- XNullHandler)) {
- CfgPtr->HandlerTable[Id].Handler = StubHandler;
- }
- CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;
- }
- }
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc.h
-*
-* The Xilinx interrupt controller driver component. This component supports the
-* Xilinx interrupt controller.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 0 and 31 inclusive with
-* 0 being the highest priority interrupt source.
-*
-* The Xilinx interrupt controller supports the following features:
-*
-* - specific individual interrupt enabling/disabling
-* - specific individual interrupt acknowledging
-* - attaching specific callback function to handle interrupt source
-* - master enable/disable
-* - single callback per interrupt or all pending interrupts handled for
-* each interrupt of the processor
-*
-* The acknowledgement of the interrupt within the interrupt controller is
-* selectable, either prior to the device's handler being called or after
-* the handler is called. This is necessary to support interrupt signal inputs
-* which are either edge or level signals. Edge driven interrupt signals
-* require that the interrupt is acknowledged prior to the interrupt being
-* serviced in order to prevent the loss of interrupts which are occurring
-* extremely close together. A level driven interrupt input signal requires
-* the interrupt to acknowledged after servicing the interrupt to ensure that
-* the interrupt only generates a single interrupt condition.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xintc_intr.c.
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <b>Interrupt Vector Tables</b>
-*
-* The interrupt vector table for each interrupt controller device is declared
-* statically in xintc_g.c within the configuration data for each instance.
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table - to retrieve the vector table
-* for an instance of the interrupt controller. The user should populate the
-* vector table with handlers and callbacks at run-time using the XIntc_Connect()
-* and XIntc_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an argument
-* to be passed to the handler when an interrupt occurs. The tools default this
-* argument to the base address of the interrupting device. Note that the
-* device driver interrupt handlers given in this file do not take a base
-* address as an argument, but instead take a pointer to the driver instance.
-* This means that although the table is created statically, the user must still
-* use XIntc_Connect() when the interrupt handler takes an argument other than
-* the base address. This is only to say that the existence of the static vector
-* tables should not mislead the user into thinking they no longer need to
-* register/connect interrupt handlers with this driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 08/16/01 First release
-* 1.00a rpm 01/09/02 Removed the AckLocation argument from XIntc_Connect().
-* This information is now internal in xintc_g.c.
-* 1.00b jhl 02/13/02 Repartitioned the driver for smaller files
-* 1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
-* data type
-* 1.00c rpm 10/17/03 New release. Support the static vector table created
-* in the xintc_g.c configuration table. Moved vector
-* table and options out of instance structure and into
-* the configuration table.
-* 1.10c mta 03/21/07 Updated to new coding style
-* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed from
-* all the macro names/definitions.
-* 2.01a sdm 04/27/10 Updated the tcl so that the defintions are generated in
-* the xparameters.h to know whether the optional registers
-* SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
-* This driver doesnot make use of these definitions and does
-* not use the optional registers.
-* 2.03a hvm 05/24/11 Updated the tcl to generate vector Ids for external
-* interrupts. CR565336
-* 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
-* and XIntc_SetNormalIntrMode for setting to normal
-* interrupt mode.
-* 2.04a asa 03/19/12 Changed the XIntc_Config struct. The order of entries
-* declared in the structure now matches with the
-* XIntc_ConfigTable generated by the driver tcl.
-* 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
-* added IntVectorAddr to XIntc_Config for this.
-* Added XIntc_RegisterFastHandler API to register fast
-* interrupt handlers using base address.
-* 2.06a bss 01/28/13 To support Cascade mode:
-* Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
-* XIN_INTC_SECONDARY,XIN_INTC_LAST and
-* XIN_CONTROLLER_MAX_INTRS macros
-* Added NumberofIntrs and IntcType fields in XIntc_Config
-* structure.
-* Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
-* XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
-* XIntc_Acknowledge,XIntc_ConnectFastHandler and
-* XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
-* API in xintc.c
-* Modified XIntc_DeviceInterruptHandler,
-* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
-* XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
-* API in xintc_l.c.
-* Modified XIntc_SetOptions API in xintc_options.c.
-* Modified XIntc_SimulateIntr API in xintc_selftest.c.
-* Modified driver tcl:
-* to check for Cascade mode and generate XPAR_INTC_TYPE
-* for each controller.
-* Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
-* interrupt sources of all Controllers in Cascade mode.
-* 2.07a bss 10/18/13 To support Nested interrupts:
-* Modified XIntc_DeviceInterruptHandler API.
-* Added XIN_ILR_OFFSET macro in xintc_l.h.
-* Modified driver tcl to generate HAS_ILR parameter in
-* xparameters.h
-* 3.0 bss 01/28/13 Modified xintc.c to initialize IVAR register with
-* XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
-* CR#765931.
-* Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
-* correctly(CR#764865).
-*
-* @note
-* For Cascade mode, Interrupt IDs are generated in xparameters.h
-* as shown below:
-*
-* Master/Primary INTC
-* ______
-* | |-0 Secondary INTC
-* | |-. ______
-* | |-. | |-32 Last INTC
-* | |-. | |-. ______
-* |______|<-31------| |-. | |-64
-* | |-. | |-.
-* |______|<-63-------| |-.
-* | |-.
-* |______|-95
-*
-* All driver functions has to be called using DeviceId/
-* InstancePtr/BaseAddress of Primary/Master Controller and
-* Interrupts IDs generated in xparameters.h only.
-* Driver functions takes care of Slave Controllers based on
-* Interrupt ID passed. User must not use Interrupt source/ID
-* 31 of Primary and Secondary controllers to call driver
-* functions.
-*
-* For nested interrupts, XIntc_DeviceInterruptHandler saves
-* microblaze r14 register on entry and restores on exit. This is
-* required since compiler does not support nesting. It enables
-* Microblaze interrupts after blocking further interrupts from
-* the current interrupt number and interrupts below current
-* interrupt proirity by writing to Interrupt Level Register of
-* INTC on entry. On exit, it disables microblaze interrupts and
-* restores ILR register default value(0xFFFFFFFF)back. It is
-* recommended to increase STACK_SIZE in linker script for nested
-* interrupts.
-* 3.0 adk 12/10/13 Updated as per the New Tcl API's
-* 3.0 adk 17/02/14 Fixed the CR:771287 Changes are made in the intc
-* driver tcl.
-* 3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
-* the test-app tcl
-* 3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
-* correctly (CR#799609).
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XINTC_H /* prevent circular inclusions */
-#define XINTC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xstatus.h"
-#include "xintc_l.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name Configuration options
- * These options are used in XIntc_SetOptions() to configure the device.
- * @{
- */
-/**
- * <pre>
- * XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
- * and then return.
- * XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
- * return.
- * </pre>
- */
-#define XIN_SVC_SGL_ISR_OPTION 1UL
-#define XIN_SVC_ALL_ISRS_OPTION 2UL
-/*@}*/
-
-/**
- * @name Start modes
- * One of these values is passed to XIntc_Start() to start the device.
- * @{
- */
-/** Simulation only mode, no hardware interrupts recognized */
-#define XIN_SIMULATION_MODE 0
-/** Real mode, no simulation allowed, hardware interrupts recognized */
-#define XIN_REAL_MODE 1
-/*@}*/
-
-/**
- * @name Masks to specify Interrupt Controller Mode
- * @{
- */
-#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
-#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
-#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
-#define XIN_INTC_LAST 3 /* Last Slave Controller */
-
-/*@}*/
-
-/**
- * @name Mask to specify maximum number of interrupt sources per controller
- * @{
- */
-#define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32
- interrupt pins */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Register base address */
- u32 AckBeforeService; /**< Ack location per interrupt */
- int FastIntr; /**< Fast Interrupt enabled */
- u32 IntVectorAddr; /**< Interrupt Vector Address */
- int NumberofIntrs; /**< Number of Interrupt sources */
- u32 Options; /**< Device options */
- int IntcType; /**< Intc type 0 - No Cascade Mode
- 1 - primary instance
- 2 - secondary instance
- 3 - last instance */
-
-/** Static vector table of interrupt handlers */
-#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
- XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
-#else
- XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
-#endif
-
-} XIntc_Config;
-
-/**
- * The XIntc driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- u32 BaseAddress; /**< Base address of registers */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device has been started */
- u32 UnhandledInterrupts; /**< Intc Statistics */
- XIntc_Config *CfgPtr; /**< Pointer to instance config entry */
-
-} XIntc;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xintc.c
- */
-int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
-
-int XIntc_Start(XIntc * InstancePtr, u8 Mode);
-void XIntc_Stop(XIntc * InstancePtr);
-
-int XIntc_Connect(XIntc * InstancePtr, u8 Id,
- XInterruptHandler Handler, void *CallBackRef);
-void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
-
-void XIntc_Enable(XIntc * InstancePtr, u8 Id);
-void XIntc_Disable(XIntc * InstancePtr, u8 Id);
-
-void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
-
-XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
-
-int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
- XFastInterruptHandler Handler);
-void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
-
-/*
- * Interrupt functions in xintr_intr.c
- */
-void XIntc_VoidInterruptHandler(void);
-void XIntc_InterruptHandler(XIntc * InstancePtr);
-
-/*
- * Options functions in xintc_options.c
- */
-int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
-u32 XIntc_GetOptions(XIntc * InstancePtr);
-
-/*
- * Self-test functions in xintc_selftest.c
- */
-int XIntc_SelfTest(XIntc * InstancePtr);
-int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Driver configuration\r
-*\r
-*******************************************************************/\r
-\r
-#include "xparameters.h"\r
-#include "xintc.h"\r
-\r
-\r
-extern void XNullHandler (void *);\r
-\r
-/*\r
-* The configuration table for devices\r
-*/\r
-\r
-XIntc_Config XIntc_ConfigTable[] =\r
-{\r
- {\r
- XPAR_AXI_INTC_0_DEVICE_ID,\r
- XPAR_AXI_INTC_0_BASEADDR,\r
- XPAR_AXI_INTC_0_KIND_OF_INTR,\r
- XPAR_AXI_INTC_0_HAS_FAST,\r
- XPAR_AXI_INTC_0_IVAR_RESET_VALUE,\r
- XPAR_AXI_INTC_0_NUM_INTR_INPUTS,\r
- XIN_SVC_SGL_ISR_OPTION,\r
- XPAR_AXI_INTC_0_TYPE,\r
- {\r
- {\r
- XNullHandler,\r
- (void *) XNULL\r
- },\r
- {\r
- XNullHandler,\r
- (void *) XNULL\r
- },\r
- {\r
- XNullHandler,\r
- (void *) XNULL\r
- }\r
- }\r
-\r
- }\r
-};\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc_i.h
-*
-* This file contains data which is shared between files and internal to the
-* XIntc component. It is intended for internal use only.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.00b jhl 04/24/02 Moved register definitions to xintc_l.h
-* 1.00c rpm 10/17/03 New release. Removed extern of global, single instance
-* pointer.
-* 1.10c mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XINTC_I_H /* prevent circular inclusions */
-#define XINTC_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xintc.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-extern u32 XIntc_BitPosMask[];
-
-extern XIntc_Config XIntc_ConfigTable[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc_intr.c
-*
-* This file contains the interrupt processing for the XIntc component which
-* is the driver for the Xilinx Interrupt Controller. The interrupt
-* processing is partitioned seperately such that users are not required to
-* use the provided interrupt processing. This file requires other files of
-* the driver to be linked in also.
-*
-* Two different interrupt handlers are provided for this driver such that the
-* user must select the appropriate handler for the application. The first
-* interrupt handler, XIntc_VoidInterruptHandler, is provided for systems
-* which use only a single interrupt controller or for systems that cannot
-* otherwise provide an argument to the XIntc interrupt handler (e.g., the RTOS
-* interrupt vector handler may not provide such a facility). The constant
-* XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler to be included in
-* the driver. The second interrupt handler, XIntc_InterruptHandler, uses an
-* input argument which is an instance pointer to an interrupt controller driver
-* such that multiple interrupt controllers can be supported. This handler
-* requires the calling function to pass it the appropriate argument, so another
-* level of indirection may be required.
-*
-* Note that both of these handlers are now only provided for backward
-* compatibility. The handler defined in xintc_l.c is the recommended handler.
-*
-* The interrupt processing may be used by connecting one of the interrupt
-* handlers to the interrupt system. These handlers do not save and restore
-* the processor context but only handle the processing of the Interrupt
-* Controller. The two handlers are provided as working examples. The user is
-* encouraged to supply their own interrupt handler when performance tuning is
-* deemed necessary.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00b jhl 02/13/02 First release
-* 1.00c rpm 10/17/03 New release. Support the static vector table created
-* in the xintc_g.c configuration table. Collapse handlers
-* to use the XIntc_DeviceInterruptHandler() in xintc_l.c.
-* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
-* XIntc_VoidInterruptHandler(). This handler will only be
-* include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is defined.
-* 1.10c mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
-*
-* </pre>
-*
-* @internal
-*
-* This driver assumes that the context of the processor has been saved prior to
-* the calling of the Interrupt Controller interrupt handler and then restored
-* after the handler returns. This requires either the running RTOS to save the
-* state of the machine or that a wrapper be used as the destination of the
-* interrupt vector to save the state of the processor and restore the state
-* after the interrupt handler returns.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xintc.h"
-
-/************************** Constant Definitions *****************************/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Interrupt handler for the driver used when there can be no argument passed
-* to the handler. This function is provided mostly for backward compatibility.
-* The user should use XIntc_DeviceInterruptHandler(), defined in xintc_l.c,
-* if possible.
-*
-* The user must connect this function to the interrupt system such that it is
-* called whenever the devices which are connected to it cause an interrupt.
-*
-* @return None.
-*
-* @note
-*
-* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
-* to be included in the driver compilation.
-*
-******************************************************************************/
-#ifdef XPAR_INTC_SINGLE_DEVICE_ID
-void XIntc_VoidInterruptHandler(void)
-{
- /* Use the single instance to call the main interrupt handler */
- XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* The interrupt handler for the driver. This function is provided mostly for
-* backward compatibility. The user should use XIntc_DeviceInterruptHandler(),
-* defined in xintc_l.c when possible and pass the device ID of the interrupt
-* controller device as its argument.
-*
-* The user must connect this function to the interrupt system such that it is
-* called whenever the devices which are connected to it cause an interrupt.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XIntc_InterruptHandler(XIntc * InstancePtr)
-{
- /* Assert that the pointer to the instance is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /* Use the instance's device ID to call the main interrupt handler.
- * (the casts are to avoid a compiler warning)
- */
- XIntc_DeviceInterruptHandler((void *)
- ((u32) (InstancePtr->CfgPtr->DeviceId)));
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc_l.c
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b jhl 04/24/02 First release
-* 1.00c rpm 10/17/03 New release. Support the static vector table created
-* in the xintc_g.c configuration table.
-* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
-* XIntc_LowLevelInterruptHandler(). This handler will only
-* be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
-* defined.
-* 1.10c mta 03/21/07 Updated to new coding style
-* 1.10c ecm 07/09/07 Read the ISR after the Acknowledge in the interrupt
-* handler to support architectures with posted write bus
-* access issues.
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed
-* from all the macro definitions.
-* 2.04a bss 01/13/12 Removed the unused Register variable for warnings.
-* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
-* interrupt handlers using base address.
-* 2.06a bss 01/28/13 To support Cascade mode:
-* Modified XIntc_DeviceInterruptHandler,
-* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
-* XIntc_RegisterFastHandler APIs.
-* Added XIntc_CascadeHandler API.
-* 2.07a bss 10/18/13 Modified XIntc_DeviceInterruptHandler to support
-* nested interrupts.
-*
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xintc.h"
-#include "xintc_i.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress);
-
-#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
-static void XIntc_CascadeHandler(void *DeviceId);
-#endif
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This is the interrupt handler for the driver interface provided in this file
-* when there can be no argument passed to the handler. In this case, we just
-* use the globally defined device ID for the interrupt controller. This function
-* is provided mostly for backward compatibility. The user should use
-* XIntc_DeviceInterruptHandler() if possible.
-*
-* This function does not support multiple interrupt controller instances to be
-* handled.
-*
-* The user must connect this function to the interrupt system such that it is
-* called whenever the devices which are connected to it cause an interrupt.
-*
-* @return None.
-*
-* @note
-*
-* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
-* to be included in the driver compilation.
-*
-******************************************************************************/
-#ifdef XPAR_INTC_SINGLE_DEVICE_ID
-void XIntc_LowLevelInterruptHandler(void)
-{
- /*
- * A level of indirection here because the interrupt handler used with
- * the driver interface given in this file needs to remain void - no
- * arguments. So we need the globally defined device ID of THE
- * interrupt controller.
- */
- XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This function is the primary interrupt handler for the driver. It must be
-* connected to the interrupt source such that is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the AckBeforeService flag in the configuration data to determine when to
-* acknowledge the interrupt. Highest priority interrupts are serviced first.
-* This function assumes that an interrupt vector table has been previously
-* initialized.It does not verify that entries in the table are valid before
-* calling an interrupt handler. In Cascade mode this function calls
-* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers.
-* This functions also handles interrupts nesting by saving and restoring link
-* register of Microblaze and Interrupt Level register of interrupt controller
-* properly.
-
-* @param DeviceId is the zero-based device ID defined in xparameters.h
-* of the interrupting interrupt controller. It is used as a direct
-* index into the configuration data, which contains the vector
-* table for the interrupt controller. Note that even though the
-* argument is a void pointer, the value is not a pointer but the
-* actual device ID. The void pointer type is necessary to meet
-* the XInterruptHandler typedef for interrupt handlers.
-*
-* @return None.
-*
-* @note For nested interrupts, this function saves microblaze r14
-* register on entry and restores on exit. This is required since
-* compiler does not support nesting. This function enables
-* Microblaze interrupts after blocking further interrupts
-* from the current interrupt number and interrupts below current
-* interrupt proirity by writing to Interrupt Level Register of
-* INTC on entry. On exit, it disables microblaze interrupts and
-* restores ILR register default value(0xFFFFFFFF)back. It is
-* recommended to increase STACK_SIZE in linker script for nested
-* interrupts.
-*
-******************************************************************************/
-void XIntc_DeviceInterruptHandler(void *DeviceId)
-{
- u32 IntrStatus;
- u32 IntrMask = 1;
- int IntrNumber;
- XIntc_Config *CfgPtr;
- u32 Imr;
-
- /* Get the configuration data using the device ID */
- CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
-
-#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
- if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
- XIntc_CascadeHandler(DeviceId);
- }
- else
-#endif
- { /* This extra brace is required for compilation in Cascade Mode */
-
-#if XPAR_XINTC_HAS_ILR == TRUE
-#ifdef __MICROBLAZE__
- volatile u32 R14_register;
- /* Save r14 register */
- R14_register = mfgpr(r14);
-#endif
- volatile u32 ILR_reg;
- /* Save ILR register */
- ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET);
-#endif
- /* Get the interrupts that are waiting to be serviced */
- IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
-
- /* Mask the Fast Interrupts */
- if (CfgPtr->FastIntr == TRUE) {
- Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
- IntrStatus &= ~Imr;
- }
-
- /* Service each interrupt that is active and enabled by
- * checking each bit in the register from LSB to MSB which
- * corresponds to an interrupt input signal
- */
- for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs;
- IntrNumber++) {
- if (IntrStatus & 1) {
- XIntc_VectorTableEntry *TablePtr;
-#if XPAR_XINTC_HAS_ILR == TRUE
- /* Write to ILR the current interrupt
- * number
- */
- Xil_Out32(CfgPtr->BaseAddress +
- XIN_ILR_OFFSET, IntrNumber);
-
- /* Read back ILR to ensure the value
- * has been updated and it is safe to
- * enable interrupts
- */
-
- Xil_In32(CfgPtr->BaseAddress +
- XIN_ILR_OFFSET);
-
- /* Enable interrupts */
- Xil_ExceptionEnable();
-#endif
- /* If the interrupt has been setup to
- * acknowledge it before servicing the
- * interrupt, then ack it */
- if (CfgPtr->AckBeforeService & IntrMask) {
- XIntc_AckIntr(CfgPtr->BaseAddress,
- IntrMask);
- }
-
- /* The interrupt is active and enabled, call
- * the interrupt handler that was setup with
- * the specified parameter
- */
- TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
- TablePtr->Handler(TablePtr->CallBackRef);
-
- /* If the interrupt has been setup to
- * acknowledge it after it has been serviced
- * then ack it
- */
- if ((CfgPtr->AckBeforeService &
- IntrMask) == 0) {
- XIntc_AckIntr(CfgPtr->BaseAddress,
- IntrMask);
- }
-
-#if XPAR_XINTC_HAS_ILR == TRUE
- /* Disable interrupts */
- Xil_ExceptionDisable();
- /* Restore ILR */
- Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET,
- ILR_reg);
-#endif
- /*
- * Read the ISR again to handle architectures
- * with posted write bus access issues.
- */
- XIntc_GetIntrStatus(CfgPtr->BaseAddress);
-
- /*
- * If only the highest priority interrupt is to
- * be serviced, exit loop and return after
- * servicing
- * the interrupt
- */
- if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
-
-#if XPAR_XINTC_HAS_ILR == TRUE
-#ifdef __MICROBLAZE__
- /* Restore r14 */
- mtgpr(r14, R14_register);
-#endif
-#endif
- return;
- }
- }
-
- /* Move to the next interrupt to check */
- IntrMask <<= 1;
- IntrStatus >>= 1;
-
- /* If there are no other bits set indicating that all
- * interrupts have been serviced, then exit the loop
- */
- if (IntrStatus == 0) {
- break;
- }
- }
-#if XPAR_XINTC_HAS_ILR == TRUE
-#ifdef __MICROBLAZE__
- /* Restore r14 */
- mtgpr(r14, R14_register);
-#endif
-#endif
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the interrupt service option, which can configure the driver so that it
-* services only a single interrupt at a time when an interrupt occurs, or
-* services all pending interrupts when an interrupt occurs. The default
-* behavior when using the driver interface given in xintc.h file is to service
-* only a single interrupt, whereas the default behavior when using the driver
-* interface given in this file is to service all outstanding interrupts when an
-* interrupt occurs. In Cascade mode same Option is set to Slave controllers.
-*
-* @param BaseAddress is the unique identifier for a device.
-* @param Option is XIN_SVC_SGL_ISR_OPTION if you want only a single
-* interrupt serviced when an interrupt occurs, or
-* XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts
-* serviced when an interrupt occurs.
-*
-* @return None.
-*
-* @note
-*
-* Note that this function has no effect if the input base address is invalid.
-*
-******************************************************************************/
-void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option)
-{
- XIntc_Config *CfgPtr;
-
- CfgPtr = LookupConfigByBaseAddress(BaseAddress);
- if (CfgPtr != NULL) {
- CfgPtr->Options = Option;
- /* If Cascade mode set the option for all Slaves */
- if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
- int Index;
- for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
- Index++) {
- CfgPtr = XIntc_LookupConfig(Index);
- CfgPtr->Options = Option;
- }
- }
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Register a handler function for a specific interrupt ID. The vector table
-* of the interrupt controller is updated, overwriting any previous handler.
-* The handler function will be called when an interrupt occurs for the given
-* interrupt ID.
-*
-* This function can also be used to remove a handler from the vector table
-* by passing in the XIntc_DefaultHandler() as the handler and NULL as the
-* callback reference.
-* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
-* Controller
-*
-* @param BaseAddress is the base address of the interrupt controller
-* whose vector table will be modified.
-* @param InterruptId is the interrupt ID to be associated with the input
-* handler.
-* @param Handler is the function pointer that will be added to
-* the vector table for the given interrupt ID.
-* @param CallBackRef is the argument that will be passed to the new
-* handler function when it is called. This is user-specific.
-*
-* @return None.
-*
-* @note
-*
-* Note that this function has no effect if the input base address is invalid.
-*
-******************************************************************************/
-void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
- XInterruptHandler Handler, void *CallBackRef)
-{
- XIntc_Config *CfgPtr;
-
- CfgPtr = LookupConfigByBaseAddress(BaseAddress);
-
- if (CfgPtr != NULL) {
-
- if (InterruptId > 31) {
- CfgPtr = XIntc_LookupConfig(InterruptId/32);
- CfgPtr->HandlerTable[InterruptId%32].Handler = Handler;
- CfgPtr->HandlerTable[InterruptId%32].CallBackRef =
- CallBackRef;
- }
- else {
- CfgPtr->HandlerTable[InterruptId].Handler = Handler;
- CfgPtr->HandlerTable[InterruptId].CallBackRef =
- CallBackRef;
- }
- }
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the base address of the device.
-* A table contains the configuration info for each device in the system.
-*
-* @param BaseAddress is the unique identifier for a device.
-*
-* @return
-*
-* A pointer to the configuration structure for the specified device, or
-* NULL if the device was not found.
-*
-* @note None.
-*
-******************************************************************************/
-static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress)
-{
- XIntc_Config *CfgPtr = NULL;
- int Index;
-
- for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
- if (XIntc_ConfigTable[Index].BaseAddress == BaseAddress) {
- CfgPtr = &XIntc_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Register a fast handler function for a specific interrupt ID. The handler
-* function will be called when an interrupt occurs for the given interrupt ID.
-* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
-* Controller
-*
-* @param BaseAddress is the base address of the interrupt controller
-* whose vector table will be modified.
-* @param InterruptId is the interrupt ID to be associated with the input
-* handler.
-* @param FastHandler is the function pointer that will be called when
-* interrupt occurs
-*
-* @return None.
-*
-* @note
-*
-* Note that this function has no effect if the input base address is invalid.
-*
-******************************************************************************/
-void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
- XFastInterruptHandler FastHandler)
-{
- u32 CurrentIER;
- u32 Mask;
- u32 Imr;
- XIntc_Config *CfgPtr;
-
-
- if (Id > 31) {
- /* Enable user required Id in Slave controller */
- CfgPtr = XIntc_LookupConfig(Id/32);
-
- /* Get the Enabled Interrupts */
- CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[(Id%32)];
-
- /* Disable the Interrupt if it was enabled before calling
- * this function
- */
- if (CurrentIER & Mask) {
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER & ~Mask));
- }
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
- ((Id%32) * 4), (u32) FastHandler);
-
- /* Slave controllers in Cascade Mode should have all as Fast
- * interrupts or Normal interrupts, mixed interrupts are not
- * supported
- */
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
-
- /* Enable the Interrupt if it was enabled before calling this
- * function
- */
- if (CurrentIER & Mask) {
- XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
- (CurrentIER | Mask));
- }
- }
- else {
-
- CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
-
- /* Convert from integer id to bit mask */
- Mask = XIntc_BitPosMask[Id];
-
- if (CurrentIER & Mask) {
- /* Disable Interrupt if it was enabled */
- CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
- XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
- (CurrentIER & ~Mask));
- }
-
- XIntc_Out32(BaseAddress + XIN_IVAR_OFFSET + (Id * 4),
- (u32) FastHandler);
-
- Imr = XIntc_In32(BaseAddress + XIN_IMR_OFFSET);
- XIntc_Out32(BaseAddress + XIN_IMR_OFFSET, Imr | Mask);
-
-
- /* Enable Interrupt if it was enabled before calling
- * this function
- */
- if (CurrentIER & Mask) {
- CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
- XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
- (CurrentIER | Mask));
- }
- }
-}
-
-#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
-/*****************************************************************************/
-/**
-*
-* This function is called by primary interrupt handler for the driver to handle
-* all Controllers in Cascade mode.It will resolve which interrupts are active
-* and enabled and call the appropriate interrupt handler. It uses the
-* AckBeforeService flag in the configuration data to determine when to
-* acknowledge the interrupt. Highest priority interrupts are serviced first.
-* This function assumes that an interrupt vector table has been previously
-* initialized. It does not verify that entries in the table are valid before
-* calling an interrupt handler.This function calls itself recursively to handle
-* all interrupt controllers.
-*
-* @param DeviceId is the zero-based device ID defined in xparameters.h
-* of the interrupting interrupt controller. It is used as a direct
-* index into the configuration data, which contains the vector
-* table for the interrupt controller.
-*
-* @return None.
-*
-* @note
-*
-******************************************************************************/
-static void XIntc_CascadeHandler(void *DeviceId)
-{
- u32 IntrStatus;
- u32 IntrMask = 1;
- int IntrNumber;
- u32 Imr;
- XIntc_Config *CfgPtr;
- static int Id = 0;
-
- /* Get the configuration data using the device ID */
- CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
-
- /* Get the interrupts that are waiting to be serviced */
- IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
-
- /* Mask the Fast Interrupts */
- if (CfgPtr->FastIntr == TRUE) {
- Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
- IntrStatus &= ~Imr;
- }
-
- /* Service each interrupt that is active and enabled by
- * checking each bit in the register from LSB to MSB which
- * corresponds to an interrupt input signal
- */
- for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; IntrNumber++) {
- if (IntrStatus & 1) {
- XIntc_VectorTableEntry *TablePtr;
-
- /* In Cascade mode call this function recursively
- * for interrupt id 31 and until interrupts of last
- * instance/controller are handled
- */
- if ((IntrNumber == 31) &&
- (CfgPtr->IntcType != XIN_INTC_LAST) &&
- (CfgPtr->IntcType != XIN_INTC_NOCASCADE)) {
- XIntc_CascadeHandler((void *)++Id);
- Id--;
- }
-
- /* If the interrupt has been setup to
- * acknowledge it before servicing the
- * interrupt, then ack it */
- if (CfgPtr->AckBeforeService & IntrMask) {
- XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
- }
-
- /* Handler of 31 interrupt Id has to be called only
- * for Last controller in cascade Mode
- */
- if (!((IntrNumber == 31) &&
- (CfgPtr->IntcType != XIN_INTC_LAST) &&
- (CfgPtr->IntcType != XIN_INTC_NOCASCADE))) {
-
- /* The interrupt is active and enabled, call
- * the interrupt handler that was setup with
- * the specified parameter
- */
- TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
- TablePtr->Handler(TablePtr->CallBackRef);
- }
- /* If the interrupt has been setup to acknowledge it
- * after it has been serviced then ack it
- */
- if ((CfgPtr->AckBeforeService & IntrMask) == 0) {
- XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
- }
-
- /*
- * Read the ISR again to handle architectures with
- * posted write bus access issues.
- */
- XIntc_GetIntrStatus(CfgPtr->BaseAddress);
-
- /*
- * If only the highest priority interrupt is to be
- * serviced, exit loop and return after servicing
- * the interrupt
- */
- if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
- return;
- }
- }
-
- /* Move to the next interrupt to check */
- IntrMask <<= 1;
- IntrStatus >>= 1;
-
- /* If there are no other bits set indicating that all interrupts
- * have been serviced, then exit the loop
- */
- if (IntrStatus == 0) {
- break;
- }
- }
-}
-#endif
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-*
-* Note that users of the driver interface given in this file can register
-* an interrupt handler dynamically (at run-time) using the
-* XIntc_RegisterHandler() function.
-* User of the driver interface given in xintc.h should still use
-* XIntc_Connect(), as always.
-* Also see the discussion of the interrupt vector tables in xintc.h.
-*
-* There are currently two interrupt handlers specified in this interface.
-*
-* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
-* is used in cases where there is a single interrupt controller device in
-* the system and the handler cannot be passed an argument. This function is
-* provided mostly for backward compatibility.
-*
-* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
-* argument, indicating which interrupt controller device in the system is
-* causing the interrupt - thereby supporting multiple interrupt controllers.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00b jhl 04/24/02 First release
-* 1.00c rpm 10/17/03 New release. Support the static vector table created
-* in the xintc_g.c configuration table.
-* 1.10c mta 03/21/07 Updated to new coding style
-* 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. _m is removed from all
-* the macro definitions.
-* 2.04a bss 01/13/12 Updated for adding defines for IMR and IVAR for
-* the FAST Interrupt
-* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
-* interrupt handlers using base address.
-* 2.07a bss 10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
-*
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XINTC_L_H /* prevent circular inclusions */
-#define XINTC_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xil_io.h"
-
-/*
- * XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
- * accessed through a DCR bus connected to a bridge.
- */
-#define XPAR_XINTC_USE_DCR_BRIDGE 0
-
-#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
-#include "xio_dcr.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* define the offsets from the base address for all the registers of the
- * interrupt controller, some registers may be optional in the hardware device
- */
-#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
-
-#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
-#define XIN_IPR_OFFSET 1 /* Interrupt Pending Register */
-#define XIN_IER_OFFSET 2 /* Interrupt Enable Register */
-#define XIN_IAR_OFFSET 3 /* Interrupt Acknowledge Register */
-#define XIN_SIE_OFFSET 4 /* Set Interrupt Enable Register */
-#define XIN_CIE_OFFSET 5 /* Clear Interrupt Enable Register */
-#define XIN_IVR_OFFSET 6 /* Interrupt Vector Register */
-#define XIN_MER_OFFSET 7 /* Master Enable Register */
-#define XIN_IMR_OFFSET 8 /* Interrupt Mode Register , this is present
- * only for Fast Interrupt */
-#define XIN_IVAR_OFFSET 64 /* Interrupt Vector Address Register
- * Interrupt 0 Offest, this is present
- * only for Fast Interrupt */
-
-#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
-
-#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
-#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
-#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
-#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
-#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
-#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
-#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
-#define XIN_MER_OFFSET 28 /* Master Enable Register */
-#define XIN_IMR_OFFSET 32 /* Interrupt Mode Register , this is present
- * only for Fast Interrupt */
-#define XIN_ILR_OFFSET 36 /* Interrupt level register */
-#define XIN_IVAR_OFFSET 0x100 /* Interrupt Vector Address Register
- * Interrupt 0 Offest, this is present
- * only for Fast Interrupt */
-
-
-
-#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
-
-/* Bit definitions for the bits of the MER register */
-
-#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
-#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
-
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the driver interface given in this file and an instance pointer for the
- * driver interface given in xintc.h file.
- */
-typedef struct {
- XInterruptHandler Handler;
- void *CallBackRef;
-} XIntc_VectorTableEntry;
-
-typedef void (*XFastInterruptHandler) (void);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * Define the appropriate I/O access method to memory mapped I/O or DCR.
- */
-#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
-
-#define XIntc_In32 XIo_DcrIn
-#define XIntc_Out32 XIo_DcrOut
-
-#else
-
-#define XIntc_In32 Xil_In32
-#define XIntc_Out32 Xil_Out32
-
-#endif
-
-/****************************************************************************/
-/**
-*
-* Enable all interrupts in the Master Enable register of the interrupt
-* controller. The interrupt controller defaults to all interrupts disabled
-* from reset such that this macro must be used to enable interrupts.
-*
-* @param BaseAddress is the base address of the device.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XIntc_MasterEnable(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XIntc_MasterEnable(BaseAddress) \
- XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
- XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable all interrupts in the Master Enable register of the interrupt
-* controller.
-*
-* @param BaseAddress is the base address of the device.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XIntc_MasterDisable(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XIntc_MasterDisable(BaseAddress) \
- XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Enable specific interrupt(s) in the interrupt controller.
-*
-* @param BaseAddress is the base address of the device
-* @param EnableMask is the 32-bit value to write to the enable register.
-* Each bit of the mask corresponds to an interrupt input signal
-* that is connected to the interrupt controller (INT0 = LSB).
-* Only the bits which are set in the mask will enable interrupts.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
-*
-*****************************************************************************/
-#define XIntc_EnableIntr(BaseAddress, EnableMask) \
- XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
-
-/****************************************************************************/
-/**
-*
-* Disable specific interrupt(s) in the interrupt controller.
-*
-* @param BaseAddress is the base address of the device
-* @param DisableMask is the 32-bit value to write to the enable register.
-* Each bit of the mask corresponds to an interrupt input signal
-* that is connected to the interrupt controller (INT0 = LSB).
-* Only the bits which are set in the mask will disable interrupts.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
-*
-*****************************************************************************/
-#define XIntc_DisableIntr(BaseAddress, DisableMask) \
- XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
-
-/****************************************************************************/
-/**
-*
-* Acknowledge specific interrupt(s) in the interrupt controller.
-*
-* @param BaseAddress is the base address of the device
-* @param AckMask is the 32-bit value to write to the acknowledge
-* register. Each bit of the mask corresponds to an interrupt input
-* signal that is connected to the interrupt controller (INT0 =
-* LSB). Only the bits which are set in the mask will acknowledge
-* interrupts.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
-*
-*****************************************************************************/
-#define XIntc_AckIntr(BaseAddress, AckMask) \
- XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
-
-/****************************************************************************/
-/**
-*
-* Get the interrupt status from the interrupt controller which indicates
-* which interrupts are active and enabled.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return The 32-bit contents of the interrupt status register. Each bit
-* corresponds to an interrupt input signal that is connected to
-* the interrupt controller (INT0 = LSB). Bits which are set
-* indicate an active interrupt which is also enabled.
-*
-* @note C-style signature:
-* u32 XIntc_GetIntrStatus(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XIntc_GetIntrStatus(BaseAddress) \
- (XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
- XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Interrupt controller handlers, to be connected to processor exception
- * handling code.
- */
-void XIntc_LowLevelInterruptHandler(void);
-void XIntc_DeviceInterruptHandler(void *DeviceId);
-
-/* Various configuration functions */
-void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option);
-
-void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
- XInterruptHandler Handler, void *CallBackRef);
-
-void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
- XFastInterruptHandler FastHandler);
-
-/************************** Variable Definitions *****************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc_options.c
-*
-* Contains option functions for the XIntc driver. These functions allow the
-* user to configure an instance of the XIntc driver. This file requires other
-* files of the component to be linked in also.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00b jhl 02/21/02 First release
-* 1.00c rpm 10/17/03 New release. Support the relocation of the options flag
-* from the instance structure to the xintc_g.c
-* configuration table.
-* 1.10c mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
-* 2.06a bss 01/28/13 To support Cascade mode:
-* Modified XIntc_SetOptions API.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xintc.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Set the options for the interrupt controller driver. In Cascade mode same
-* Option is set to Slave controllers.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Options to be set. The available options are described in
-* xintc.h.
-*
-* @return
-* - XST_SUCCESS if the options were set successfully
-* - XST_INVALID_PARAM if the specified option was not valid
-*
-* @note None.
-*
-****************************************************************************/
-int XIntc_SetOptions(XIntc * InstancePtr, u32 Options)
-{
- XIntc_Config *CfgPtr;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Make sure option request is valid
- */
- if ((Options == XIN_SVC_SGL_ISR_OPTION) ||
- (Options == XIN_SVC_ALL_ISRS_OPTION)) {
- InstancePtr->CfgPtr->Options = Options;
- /* If Cascade mode set the option for all Slaves */
- if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
- int Index;
- for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
- Index++) {
- CfgPtr = XIntc_LookupConfig(Index);
- CfgPtr->Options = Options;
- }
- }
- return XST_SUCCESS;
- }
- else {
- return XST_INVALID_PARAM;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Return the currently set options.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-*
-* @return The currently set options. The options are described in xintc.h.
-*
-* @note None.
-*
-****************************************************************************/
-u32 XIntc_GetOptions(XIntc * InstancePtr)
-{
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return InstancePtr->CfgPtr->Options;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xintc_selftest.c
-*
-* Contains diagnostic self-test functions for the XIntc component. This file
-* requires other files of the component to be linked in also.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/21/02 First release
-* 1.10c mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs
-* 2.04a bss 01/16/12 Removed CurrentMIE variable and reading of the
-* MER register to remove warnings
-* 2.06a bss 01/28/13 To support Cascade mode:
-* Modified XIntc_SimulateIntr API.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xintc.h"
-#include "xintc_i.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XIN_TEST_MASK 1
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. This is a destructive test.
-*
-* This involves forcing interrupts into the controller and verifying that they
-* are recognized and can be acknowledged. This test will not succeed if the
-* interrupt controller has been started in real mode such that interrupts
-* cannot be forced.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if self-test is successful.
-* - XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the
-* self-test. It will fail the self test if the device has
-* previously been started in real mode.
-*
-* @note None.
-*
-******************************************************************************/
-int XIntc_SelfTest(XIntc * InstancePtr)
-{
- u32 CurrentISR;
- u32 Temp;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- /*
- * Acknowledge all pending interrupts by reading the interrupt status
- * register and writing the value to the acknowledge register
- */
- Temp = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
-
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp);
-
- /*
- * Verify that there are no interrupts by reading the interrupt status
- */
- CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
-
- /*
- * ISR should be zero after all interrupts are acknowledged
- */
- if (CurrentISR != 0) {
- return XST_INTC_FAIL_SELFTEST;
- }
-
- /*
- * Set a bit in the ISR which simulates an interrupt
- */
- XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, XIN_TEST_MASK);
-
- /*
- * Verify that it was set
- */
- CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
-
- if (CurrentISR != XIN_TEST_MASK) {
- return XST_INTC_FAIL_SELFTEST;
- }
-
- /*
- * Acknowledge the interrupt
- */
- XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, XIN_TEST_MASK);
-
- /*
- * Read back the ISR to verify that the interrupt is gone
- */
- CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
-
- if (CurrentISR != 0) {
- return XST_INTC_FAIL_SELFTEST;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Allows software to simulate an interrupt in the interrupt controller. This
-* function will only be successful when the interrupt controller has been
-* started in simulation mode. Once it has been started in real mode,
-* interrupts cannot be simulated. A simulated interrupt allows the interrupt
-* controller to be tested without any device to drive an interrupt input
-* signal into it. In Cascade mode writes to ISR of appropraite Slave
-* controller depending on Id.
-*
-* @param InstancePtr is a pointer to the XIntc instance to be worked on.
-* @param Id is the interrupt ID for which to simulate an interrupt.
-*
-* @return
-* - XST_SUCCESS if successful
-* - XST_FAILURE if the interrupt could not be
-* simulated because the interrupt controller is or
-* has previously been in real mode.
-*
-* @note None.
-*
-******************************************************************************/
-int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id)
-{
- u32 Mask;
- u32 MasterEnable;
- XIntc_Config *CfgPtr;
- int Index;
- int DeviceId;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
-
-
- /* Get the contents of the master enable register and determine if
- * hardware interrupts have already been enabled, if so, this is a write
- * once bit such that simulation can't be done at this point because
- * the ISR register is no longer writable by software
- */
- MasterEnable = XIntc_In32(InstancePtr->BaseAddress + XIN_MER_OFFSET);
- if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
- return XST_FAILURE;
- }
-
-
- if (Id > 31) {
-
- DeviceId = Id/32;
-
- CfgPtr = XIntc_LookupConfig(Id/32);
- Mask = XIntc_BitPosMask[Id%32];
- XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, Mask);
-
- /* Generate interrupt for 31 by writing to Interrupt Status
- * register of parent controllers. Primary controller ISR
- * will be written last in the loop
- */
- Mask = XIntc_BitPosMask[31];
- for (Index = DeviceId - 1; Index >= 0; Index--)
- {
- CfgPtr = XIntc_LookupConfig(Index);
-
- XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET,
- Mask);
- }
- }
- else {
- /*
- * The Id is used to create the appropriate mask for the
- * desired bit position.
- */
- Mask = XIntc_BitPosMask[Id];
-
- /*
- * Enable the selected interrupt source by reading the interrupt
- * enable register and then modifying only the specified
- * interrupt id enable
- */
- XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, Mask);
-
- }
- /* indicate the interrupt was successfully simulated */
-
- return XST_SUCCESS;
-}
/**
*
* @file xmig_7series.h
+* @addtogroup mig_7series_v2_0
+* @{
+* @details
* This driver exists only to allow the SDK tools to create a memory test
* application and to populate xparameters.h with memory range constants.
* There is no source code.
* 2.0 adk 19/12/13 Updated as per the New Tcl API's
*
******************************************************************************/
+/** @} */
+++ /dev/null
-###############################################################################
-#
-# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# Use of the Software is limited solely to applications:
-# (a) running on a Xilinx device, or
-# (b) that interact with a Xilinx device through a bus or interconnect.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-#
-# Except as contained in this notice, the name of the Xilinx shall not be used
-# in advertising or otherwise to promote the sale, use or other dealings in
-# this Software without prior written authorization from Xilinx.
-######################################################################
-
-# The following are defined in config.make
-# LIBSOURCES - Based on if MicroBlaze support Exceptions
-# LIBS - Do Build Profile Libraries
-include config.make
-
-AS=mb-as
-CC=mb-gcc
-AR=mb-ar
-CP=cp
-COMPILER_FLAGS=-O2 -c
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-INCLUDEFILES=*.h
-
-libs: $(LIBS)
-
-standalone_libs: $(LIBSOURCES)
- echo "Compiling standalone";
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
- $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
-
-profile_libs:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs
-
-include: standalone_includes profile_includes
-
-standalone_includes:
- ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
-
-profile_includes:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" include
-
-clean:
- rm -rf ${OUTS}
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" clean
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <unistd.h>
-
-/* _exit - Simple implementation. Does not return.
-*/
-void _exit (int status)
-{
- (void) status;
- while (1);
-}
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Configurations for Standalone BSP\r
-*\r
-*******************************************************************/\r
-\r
-#define MICROBLAZE_PVR_NONE\r
+++ /dev/null
-/*****************************************************************************
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ---------------------------------------------------
- * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
- * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
- * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
- * cacheable regions
- * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
- * generated by the cpu driver, for enabling caches
- * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
- * write-thru caches
- * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
- * Updated the MMU table to mark OCM in high address space
- * as inner cacheable and reserved space as Invalid
- * 3.03a sdm 08/20/11 Changes to support FreeRTOS
- * Updated the MMU table to mark upper half of the DDR as
- * non-cacheable
- * Setup supervisor and abort mode stacks
- * Do not initialize/enable L2CC in case of AMP
- * Initialize UART1 for 9600bps in case of AMP
- * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
- * in case of AMP
- * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
- * counters
- * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
- * xparameters.h file for CR630532 - Xil_DCacheFlush()/
- * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
- * for MicroBlaze will invalidate data in the cache instead
- * of flushing it for writeback caches
- * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
- * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
- * Remove redundant dsb/dmb instructions in cache maintenance
- * APIs
- * Remove redundant dsb in mcr instruction
- * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
- * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
- * driver tcl in xparameters.h. Update the gcc/translationtable.s
- * for the QSPI complete address range - DT644567
- * Removed profile directory for armcc compiler and changed
- * profiling setting to false in standalone_v2_1_0.tcl file
- * Deleting boot.S file after preprocessing for armcc compiler
- * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
- * invalidate the caches before enabling back the MMU and
- * D cache.
- * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
- * xil_mmu.c. Now we invalidate UTLB, Branch predictor
- * array, flush the D-cache before changing the attributes
- * in translation table. The user need not call Xil_DisableMMU
- * before calling Xil_SetTlbAttributes.
- * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
- * sgd initialization is present. Changes for this were done in
- * uart.c and xil-crt0.s.
- * Made changes in xil_io.c to use volatile pointers.
- * Made changes in xil_mmu.c to correct the function
- * Xil_SetTlbAttributes.
- * Changes are made xil-crt0.s to initialize the static
- * C++ constructors.
- * Changes are made in boot.s, to fix the TTBR settings,
- * correct the L2 Cache Auxiliary register settings, L2 cache
- * latency settings.
- * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
- * sgd usleep.c to use global timer intstead of CP15.
- * Made changes in cortexa9/gcc/translation_table.s to map
- * the peripheral devices as shareable device memory.
- * Made changes in cortexa9/gcc/xil-crt0.s to initialize
- * the global timer.
- * Made changes in cortexa9/armcc/boot.S to initialize
- * the global timer.
- * Made changes in cortexa9/armcc/translation_table.s to
- * map the peripheral devices as shareable device memory.
- * Made changes in cortexa9/gcc/boot.S to optimize the
- * L2 cache settings. Changes the section properties for
- * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
- * and cortexa9/gcc/translation_table.S.
- * Made changes in cortexa9/xil_cache.c to change the
- * cache invalidation order.
- * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
- * compilation/linking issues for C++ compiler.
- * Made changes in mb_interface.h to remove compilation/
- * linking issues for C++ compiler.
- * Added macros for swapb and swaph microblaze instructions
- * mb_interface.h
- * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
- * for CortexA9.
- * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
- * 3.07a asa 08/31/12 Added xil_printf.h include
- * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
- * Corrected L2 cache sequence disable sequence
- * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
- * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
- * irq/fiq handling.
- * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
- * fixes the CR #692094.
- * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
- * 3.10a srt 04/18/13 Implemented ARM Erratas.
- * Cortex A9 Errata - 742230, 743622, 775420, 794073
- * L2Cache PL310 Errata - 588369, 727915, 759370
- * Please refer to file 'xil_errata.h' for errata
- * description.
- * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
- * cache APIs were corresponding to only Layer 1 cache
- * memories. New APIs were now added and the existing cache
- * related APIs were changed to provide a uniform interface
- * to flush/invalidate/enable/disable the complete cache
- * system which includes both L1 and L2 caches. The changes
- * for these were done in:
- * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
- * files.
- * Four new files were added for supporting L2 cache. They are:
- * microblaze_flush_cache_ext.S-> Flushes L2 cache
- * microblaze_flush_cache_ext_range.S -> Flushes a range of
- * memory in L2 cache.
- * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
- * microblaze_invalidate_cache_ext_range -> Invalidates a
- * range of memory in L2 cache.
- * These changes are done to implement PR #697214.
- * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
- * fix the CR #706464. L2 cache disabling happens independent
- * of L1 data cache disable operation. Changes are done in the
- * same file in cache handling APIs to do a L2 cache sync
- * (poll reg7_?cache_?sync). This fixes CR #700542.
- * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
- * interrupts for ARM. These are done to fix the CR#699680.
- * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
- * sync operation. This fixes the CR# 716781.
- * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
- * for armcc toolchain.
- * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
- * fix issues related to NEON context saving. The assembly
- * routines for IRQ and FIQ handling are modified.
- * Deprecated the older BSP (3.10a).
- * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
- * various potential issues. Made changes in the function
- * Xil_SetAttributes in file xil_mmu.c.
- * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
- * in src\cortexa9 and src\microblaze folders.
- * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
- * L2 cache sync operation and to fix issues around complete
- * L2 cache flush/invalidation by ways.
- * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
- * to fix linking issues with armcc/DS-5. Modified the armcc
- * makefile to fix issues.
- * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
- * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
- * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
- * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
- * src\cortexa9\armcc\) to fix CR#767251
- * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
- * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
- * Few cache lines were missed to invalidate when unaligned address
- * invalidation was accommodated in Xil_DCacheInvalidateRange.
- * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
- * stack memory (which contains return address) was invalidated. So
- * stack memory is flushed first and then L1D cache is invalidated.
- * This is done to fix CR #763829
- * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
- * mblaze_nt_types.h file and replace uint32_t with u32 in the
- * profile_hist.c to fix the above CR.
- * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
- * instead of libxil.a and added prototypes for
- * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
- * mb_interface.h
- * 4.1 hk 04/18/14 Add sleep function.
- * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
- * some of the *.s files inMB BSP source to *.S.
- * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
- * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
- * CR#794205
- * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
- * common/xil_testcache.c
- * Fix for CR#764881.
- * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
- * output the DEBUG logs when -DDEBUG flag is enabled in BSP.
- * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
- * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
- * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
- * cortexa9/armcc/boot.s. Added default exception handlers for data
- * abort and prefetch abort using handlers called
- * DataAbortHandler and PrefetchAbortHandler respectively in
- * cortexa9/xil_exception.c to fix CR#802862.
- * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
- * issue of improper linking of translation_table.s
- * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
- * in tool chain to avoid conflicts into some special cases
- * 4.2 pkp 07/21/14 Corrected reset value of event counter in function
- * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
- * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
- * containing type def u32 defined in xil_types.g to resolve issue of
- * CR#805869
- * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
- * it is not possible to generate timer in nanosecond due to limited
- * cpu frequency
- * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
- * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
- * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
- * removed function definition of XSmc_NorInit and XSmc_NorInit from
- * cortexa9/smc.h
- * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
- * cache_ext_range declarations in mb_interface.h CR#783821.
- * Modified profile_mcount_mb.S to fix CR#808412.
- * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
- * cortexa9/iccarm to fix CR#816701
- * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
- * armcc/translation_table.s and iccarm/translation_table.s
- * to properly defined reserved entries according to address map for
- * fixing CR#820146
- * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
- * and cortexa9/armcc/translation_table.s to resolve compilation
- * error for solving CR#822897
-******************************************************************************************/
+++ /dev/null
-LIBSOURCES = *.c *.S\r
-PROFILE_ARCH_OBJS = profile_mcount_mb.o\r
-LIBS = standalone_libs\r
+++ /dev/null
-/* The errno variable is stored in the reentrancy structure. This
- function returns its address for use by the macro errno defined in
- errno.h. */
-
-#include <errno.h>
-#include <reent.h>
-
-int *
-__errno ()
-{
- return &_REENT->_errno;
-}
+++ /dev/null
-#include <stdio.h>
-
-/*
- * fcntl -- Manipulate a file descriptor.
- * We don't have a filesystem, so we do nothing.
- */
-int fcntl (int fd, int cmd, long arg)
-{
- (void) fd;
- (void) cmd;
- (void) arg;
- return 0;
-}
+++ /dev/null
-#ifndef _FSL_H
-#define _FSL_H
-
-#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Extended FSL macros. These now replace all of the previous FSL macros */
-#define FSL_DEFAULT
-#define FSL_NONBLOCKING n
-#define FSL_EXCEPTION e
-#define FSL_CONTROL c
-#define FSL_ATOMIC a
-
-#define FSL_NONBLOCKING_EXCEPTION ne
-#define FSL_NONBLOCKING_CONTROL nc
-#define FSL_NONBLOCKING_ATOMIC na
-#define FSL_EXCEPTION_CONTROL ec
-#define FSL_EXCEPTION_ATOMIC ea
-#define FSL_CONTROL_ATOMIC ca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
-#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
-#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
-#define FSL_EXCEPTION_CONTROL_ATOMIC eca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
-
-#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
-
-#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
-
-#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
-
-#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FSL_H */
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*
- * Microblaze HW Exception Handler
- * - Non self-modifying exception handler for the following exception conditions
- * - Unalignment
- * - Instruction bus error
- * - Data bus error
- * - Illegal instruction opcode
- * - Divide-by-zero
- * - Stack protection violation
- */
-
-#include "microblaze_exceptions_g.h"
-#include "xparameters.h"
-
-/* Helpful Macros */
-#define EX_HANDLER_STACK_SIZ (4*21)
-#define RMSR_OFFSET (20 * 4)
-#define R17_OFFSET (0)
-#define REG_OFFSET(regnum) (4 * (regnum + 1))
-#define NUM_TO_REG(num) r ## num
-
-#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum)
-#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
-
-#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
-#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
-
-/* Uses r5 */
-#define PUSH_MSR \
- mfs r5, rmsr; \
- swi r5, r1, RMSR_OFFSET;
-
-#define PUSH_MSR_AND_ENABLE_EXC \
- mfs r5, rmsr; \
- swi r5, r1, RMSR_OFFSET; \
- ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
- mts rmsr, r5;
-
-/* Uses r5 */
-#define POP_MSR \
- lwi r5, r1, RMSR_OFFSET; \
- mts rmsr, r5;
-
-/* Push r17 */
-#define PUSH_R17 swi r17, r1, R17_OFFSET
-/* Pop r17 */
-#define POP_R17 lwi r17, r1, R17_OFFSET
-
-#define LWREG_NOP \
- bri ex_handler_unhandled; \
- nop;
-
-#define SWREG_NOP \
- bri ex_handler_unhandled; \
- nop;
-
-/* r3 is the source */
-#define R3_TO_LWREG_V(regnum) \
- R3_TO_STACK (regnum); \
- bri ex_handler_done;
-
-/* r3 is the source */
-#define R3_TO_LWREG(regnum) \
- or NUM_TO_REG (regnum), r0, r3; \
- bri ex_handler_done;
-
-/* r3 is the target */
-#define SWREG_TO_R3_V(regnum) \
- R3_FROM_STACK (regnum); \
- bri ex_sw_tail;
-
-/* r3 is the target */
-#define SWREG_TO_R3(regnum) \
- or r3, r0, NUM_TO_REG (regnum); \
- bri ex_sw_tail;
-
-/* regnum is the source */
-#define FP_EX_OPB_SAVE(regnum) \
- swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
- nop; \
- bri handle_fp_ex_opa;
-
-/* regnum is the source */
-#define FP_EX_OPB_SAVE_V(regnum) \
- R3_FROM_STACK (regnum); \
- swi r3, r0, mb_fpex_op_b; \
- bri handle_fp_ex_opa;
-
-/* regnum is the source */
-#define FP_EX_OPA_SAVE(regnum) \
- swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
- nop; \
- bri handle_fp_ex_done;
-
-/* regnum is the source */
-#define FP_EX_OPA_SAVE_V(regnum) \
- R3_FROM_STACK (regnum); \
- swi r3, r0, mb_fpex_op_a; \
- bri handle_fp_ex_done;
-
-#define FP_EX_UNHANDLED \
- bri fp_ex_unhandled; \
- nop; \
- nop;
-
-/* ESR masks */
-#define ESR_EXC_MASK 0x0000001F
-#define ESR_REG_MASK 0x000003E0
-#define ESR_LW_SW_MASK 0x00000400
-#define ESR_WORD_MASK 0x00000800
-#define ESR_DS_MASK 0x00001000
-
-/* Extern declarations */
-.extern XNullHandler
-
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
-
-/*
- * hw_exception_handler - Handler for unaligned exceptions
- * Exception handler notes:
- * - Does not handle exceptions other than unaligned exceptions
- * - Does not handle exceptions during load into r17, r1, r0.
- * - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
- *
- * Relevant register structures
- *
- * EAR - |----|----|----|----|----|----|----|----|
- * - < ## 32 bit faulting address ## >
- *
- * ESR - |----|----|----|----|----| - | - |-----|-----|
- * - W S REG EXC
- *
- *
- * STACK FRAME STRUCTURE
- * ---------------------
- *
- * +-------------+ + 0
- * | r17 |
- * +-------------+ + 4
- * | Args for |
- * | next func |
- * +-------------+ + 8
- * | r1 |
- * | . |
- * | . |
- * | . |
- * | . |
- * | r18 |
- * +-------------+ + 80
- * | MSR |
- * +-------------+ + 84
- * | . |
- * | . |
- */
-
-
-.global _hw_exception_handler
-.section .text
-.align 2
-.ent _hw_exception_handler
-.type _hw_exception_handler, @function
-_hw_exception_handler:
-
-#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
- /* Immediately halt for stack protection violation exception without using any stack */
- swi r3, r0, mb_sp_save_r3; /* Save temporary register */
- mfs r3, resr; /* Extract ESR[DS] */
- andi r3, r3, ESR_EXC_MASK;
- xori r3, r3, 0x7; /* Check for stack protection violation */
- bnei r3, ex_handler_not_sp_violation;
-ex_handler_sp_violation:
- bri 0; /* Halt here if stack protection violation */
-ex_handler_not_sp_violation:
- lwi r3, r0, mb_sp_save_r3; /* Restore temporary register */
-#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
-
- addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
- PUSH_REG(3);
- PUSH_REG(4);
- PUSH_REG(5);
- PUSH_REG(6);
-#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
- mfs r6, resr;
- andi r6, r6, ESR_DS_MASK;
- beqi r6, ex_handler_no_ds;
- mfs r17, rbtr;
-ex_handler_no_ds:
-#endif
- PUSH_R17;
- PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
-
- mfs r3, resr;
- andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
-#ifndef NO_UNALIGNED_EXCEPTIONS
- xori r6, r5, 1; /* 00001 = Unaligned Exception */
- bnei r6, handle_ex_regular;
-
- la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
- lwi r4, r4, 8;
- la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
- xor r6, r4, r6; /* the default exception handler */
- beqi r6, handle_unaligned_ex ;
-
-handle_ex_regular:
-#endif /* ! NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
- xori r6, r5, 6; /* 00110 = FPU exception */
- beqi r6, handle_fp_ex; /* Go and decode the FP exception */
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-handle_other_ex: /* Handle Other exceptions here */
- ori r6, r0, 20;
- cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
- blei r6, ex_handler_unhandled;
-
- ori r6, r0, 7;
- cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
- bgti r6, handle_other_ex_tail;
- ori r5, r0, 0x7;
-
-handle_other_ex_tail:
- PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
- PUSH_REG(8);
- PUSH_REG(9);
- PUSH_REG(10);
- PUSH_REG(11);
- PUSH_REG(12);
- PUSH_REG(15);
- PUSH_REG(18);
-
- la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
- addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */
- addk r7, r7, r7;
- addk r7, r7, r7;
- addk r7, r7, r4; /* Get pointer to exception vector */
- lwi r5, r7, 4; /* Load argument to exception handler from table */
- lw r7, r7, r0; /* Load vector itself here */
-
- brald r15, r7; /* Branch to handler */
- nop;
-
- POP_REG(7); /* Restore other volatiles */
- POP_REG(8);
- POP_REG(9);
- POP_REG(10);
- POP_REG(11);
- POP_REG(12);
- POP_REG(15);
- POP_REG(18);
-
- bri ex_handler_done; /* Complete exception handling */
-
-#ifndef NO_UNALIGNED_EXCEPTIONS
-handle_unaligned_ex:
- andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
- srl r6, r6; /* r6 >> 5 */
- srl r6, r6;
- srl r6, r6;
- srl r6, r6;
- srl r6, r6;
- sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
- mfs r4, rear;
- andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
- bnei r6, ex_sw;
-ex_lw:
- andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
- beqi r6, ex_lhw;
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lbui r5, r4, 2;
- sbi r5, r0, ex_tmp_data_loc_2;
- lbui r5, r4, 3;
- sbi r5, r0, ex_tmp_data_loc_3;
- lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
- bri ex_lw_tail;
-ex_lhw:
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
-ex_lw_tail:
- lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
- la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
- addk r5, r5, r5;
- addk r5, r5, r5;
- addk r5, r5, r5;
- addk r5, r5, r6;
- bra r5;
-ex_lw_end: /* Exception handling of load word, ends */
-ex_sw:
- lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
- la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
- add r5, r5, r5;
- add r5, r5, r5;
- add r5, r5, r5;
- add r5, r5, r6;
- bra r5;
-ex_sw_tail:
- mfs r6, resr;
- andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
- beqi r6, ex_shw;
- swi r3, r0, ex_tmp_data_loc_0;
- lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
- sbi r3, r4, 0;
- lbui r3, r0, ex_tmp_data_loc_1;
- sbi r3, r4, 1;
- lbui r3, r0, ex_tmp_data_loc_2;
- sbi r3, r4, 2;
- lbui r3, r0, ex_tmp_data_loc_3;
- sbi r3, r4, 3;
- bri ex_handler_done;
-ex_shw:
- swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
-
-#ifdef __LITTLE_ENDIAN__
- lbui r3, r0, ex_tmp_data_loc_0;
-#else
- lbui r3, r0, ex_tmp_data_loc_2;
-#endif
- sbi r3, r4, 0;
-#ifdef __LITTLE_ENDIAN__
- lbui r3, r0, ex_tmp_data_loc_1;
-#else
- lbui r3, r0, ex_tmp_data_loc_3;
-#endif
- sbi r3, r4, 1;
-ex_sw_end: /* Exception handling of store word, ends. */
- bri ex_handler_done;
-#endif /* !NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
-handle_fp_ex:
- addik r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */
- lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */
-
-handle_fp_ex_opb:
- la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- andi r3, r4, 0x1F;
- add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
- add r3, r3, r3;
- add r5, r3, r3;
- add r5, r5, r3;
- add r5, r5, r6;
- bra r5;
-
-handle_fp_ex_opa:
- la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- andi r3, r4, 0x1F;
- add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
- add r3, r3, r3;
- add r5, r3, r3;
- add r5, r5, r3;
- add r5, r5, r6;
- bra r5;
-
-handle_fp_ex_done:
- ori r5, r0, 6; /* Set exception number back to 6 */
- bri handle_other_ex_tail;
-
-fp_ex_unhandled:
- bri 0;
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-ex_handler_done:
- POP_R17;
- POP_MSR;
- POP_REG(3);
- POP_REG(4);
- POP_REG(5);
- POP_REG(6);
-
- rted r17, 0
- addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
-ex_handler_unhandled:
- bri 0 /* UNHANDLED. TRAP HERE */
-.end _hw_exception_handler
-
-#ifndef NO_UNALIGNED_EXCEPTIONS
-
-/*
- * hw_exception_handler Jump Table
- * - Contains code snippets for each register that caused the unaligned exception.
- * - Hence exception handler is NOT self-modifying
- * - Separate table for load exceptions and store exceptions.
- * - Each table is of size: (8 * 32) = 256 bytes
- */
-
-.section .text
-.align 4
-lw_table:
-lw_r0: R3_TO_LWREG (0);
-lw_r1: LWREG_NOP;
-lw_r2: R3_TO_LWREG (2);
-lw_r3: R3_TO_LWREG_V (3);
-lw_r4: R3_TO_LWREG_V (4);
-lw_r5: R3_TO_LWREG_V (5);
-lw_r6: R3_TO_LWREG_V (6);
-lw_r7: R3_TO_LWREG (7);
-lw_r8: R3_TO_LWREG (8);
-lw_r9: R3_TO_LWREG (9);
-lw_r10: R3_TO_LWREG (10);
-lw_r11: R3_TO_LWREG (11);
-lw_r12: R3_TO_LWREG (12);
-lw_r13: R3_TO_LWREG (13);
-lw_r14: R3_TO_LWREG (14);
-lw_r15: R3_TO_LWREG (15);
-lw_r16: R3_TO_LWREG (16);
-lw_r17: LWREG_NOP;
-lw_r18: R3_TO_LWREG (18);
-lw_r19: R3_TO_LWREG (19);
-lw_r20: R3_TO_LWREG (20);
-lw_r21: R3_TO_LWREG (21);
-lw_r22: R3_TO_LWREG (22);
-lw_r23: R3_TO_LWREG (23);
-lw_r24: R3_TO_LWREG (24);
-lw_r25: R3_TO_LWREG (25);
-lw_r26: R3_TO_LWREG (26);
-lw_r27: R3_TO_LWREG (27);
-lw_r28: R3_TO_LWREG (28);
-lw_r29: R3_TO_LWREG (29);
-lw_r30: R3_TO_LWREG (30);
-lw_r31: R3_TO_LWREG (31);
-
-sw_table:
-sw_r0: SWREG_TO_R3 (0);
-sw_r1: SWREG_NOP;
-sw_r2: SWREG_TO_R3 (2);
-sw_r3: SWREG_TO_R3_V (3);
-sw_r4: SWREG_TO_R3_V (4);
-sw_r5: SWREG_TO_R3_V (5);
-sw_r6: SWREG_TO_R3_V (6);
-sw_r7: SWREG_TO_R3 (7);
-sw_r8: SWREG_TO_R3 (8);
-sw_r9: SWREG_TO_R3 (9);
-sw_r10: SWREG_TO_R3 (10);
-sw_r11: SWREG_TO_R3 (11);
-sw_r12: SWREG_TO_R3 (12);
-sw_r13: SWREG_TO_R3 (13);
-sw_r14: SWREG_TO_R3 (14);
-sw_r15: SWREG_TO_R3 (15);
-sw_r16: SWREG_TO_R3 (16);
-sw_r17: SWREG_NOP;
-sw_r18: SWREG_TO_R3 (18);
-sw_r19: SWREG_TO_R3 (19);
-sw_r20: SWREG_TO_R3 (20);
-sw_r21: SWREG_TO_R3 (21);
-sw_r22: SWREG_TO_R3 (22);
-sw_r23: SWREG_TO_R3 (23);
-sw_r24: SWREG_TO_R3 (24);
-sw_r25: SWREG_TO_R3 (25);
-sw_r26: SWREG_TO_R3 (26);
-sw_r27: SWREG_TO_R3 (27);
-sw_r28: SWREG_TO_R3 (28);
-sw_r29: SWREG_TO_R3 (29);
-sw_r30: SWREG_TO_R3 (30);
-sw_r31: SWREG_TO_R3 (31);
-
-/* Temporary data structures used in the handler */
-.section .data
-.align 2
-ex_tmp_data_loc_0:
- .byte 0
-ex_tmp_data_loc_1:
- .byte 0
-ex_tmp_data_loc_2:
- .byte 0
-ex_tmp_data_loc_3:
- .byte 0
-ex_reg_op:
- .byte 0
-
-#endif /* ! NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
-/*
- * FP exception decode jump table.
- * - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
- * - Hence exception handler is NOT self-modifying
- * - Separate table for opA and opB
- * - Each table is of size: (12 * 32) = 384 bytes
- */
-
-.section .text
-.align 4
-fp_table_opa:
-opa_r0: FP_EX_OPA_SAVE (0);
-opa_r1: FP_EX_UNHANDLED;
-opa_r2: FP_EX_OPA_SAVE (2);
-opa_r3: FP_EX_OPA_SAVE_V (3);
-opa_r4: FP_EX_OPA_SAVE_V (4);
-opa_r5: FP_EX_OPA_SAVE_V (5);
-opa_r6: FP_EX_OPA_SAVE_V (6);
-opa_r7: FP_EX_OPA_SAVE (7);
-opa_r8: FP_EX_OPA_SAVE (8);
-opa_r9: FP_EX_OPA_SAVE (9);
-opa_r10: FP_EX_OPA_SAVE (10);
-opa_r11: FP_EX_OPA_SAVE (11);
-opa_r12: FP_EX_OPA_SAVE (12);
-opa_r13: FP_EX_OPA_SAVE (13);
-opa_r14: FP_EX_UNHANDLED;
-opa_r15: FP_EX_UNHANDLED;
-opa_r16: FP_EX_UNHANDLED;
-opa_r17: FP_EX_UNHANDLED;
-opa_r18: FP_EX_OPA_SAVE (18);
-opa_r19: FP_EX_OPA_SAVE (19);
-opa_r20: FP_EX_OPA_SAVE (20);
-opa_r21: FP_EX_OPA_SAVE (21);
-opa_r22: FP_EX_OPA_SAVE (22);
-opa_r23: FP_EX_OPA_SAVE (23);
-opa_r24: FP_EX_OPA_SAVE (24);
-opa_r25: FP_EX_OPA_SAVE (25);
-opa_r26: FP_EX_OPA_SAVE (26);
-opa_r27: FP_EX_OPA_SAVE (27);
-opa_r28: FP_EX_OPA_SAVE (28);
-opa_r29: FP_EX_OPA_SAVE (29);
-opa_r30: FP_EX_OPA_SAVE (30);
-opa_r31: FP_EX_OPA_SAVE (31);
-
-fp_table_opb:
-opb_r0: FP_EX_OPB_SAVE (0);
-opb_r1: FP_EX_UNHANDLED;
-opb_r2: FP_EX_OPB_SAVE (2);
-opb_r3: FP_EX_OPB_SAVE_V (3);
-opb_r4: FP_EX_OPB_SAVE_V (4);
-opb_r5: FP_EX_OPB_SAVE_V (5);
-opb_r6: FP_EX_OPB_SAVE_V (6);
-opb_r7: FP_EX_OPB_SAVE (7);
-opb_r8: FP_EX_OPB_SAVE (8);
-opb_r9: FP_EX_OPB_SAVE (9);
-opb_r10: FP_EX_OPB_SAVE (10);
-opb_r11: FP_EX_OPB_SAVE (11);
-opb_r12: FP_EX_OPB_SAVE (12);
-opb_r13: FP_EX_OPB_SAVE (13);
-opb_r14: FP_EX_UNHANDLED;
-opb_r15: FP_EX_UNHANDLED;
-opb_r16: FP_EX_UNHANDLED;
-opb_r17: FP_EX_UNHANDLED;
-opb_r18: FP_EX_OPB_SAVE (18);
-opb_r19: FP_EX_OPB_SAVE (19);
-opb_r20: FP_EX_OPB_SAVE (20);
-opb_r21: FP_EX_OPB_SAVE (21);
-opb_r22: FP_EX_OPB_SAVE (22);
-opb_r23: FP_EX_OPB_SAVE (23);
-opb_r24: FP_EX_OPB_SAVE (24);
-opb_r25: FP_EX_OPB_SAVE (25);
-opb_r26: FP_EX_OPB_SAVE (26);
-opb_r27: FP_EX_OPB_SAVE (27);
-opb_r28: FP_EX_OPB_SAVE (28);
-opb_r29: FP_EX_OPB_SAVE (29);
-opb_r30: FP_EX_OPB_SAVE (30);
-opb_r31: FP_EX_OPB_SAVE (31);
-
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
-/* This is where we store the opA and opB of the last excepting FP instruction */
-.section .data
-.align 2
-.global mb_fpex_op_a
-.global mb_fpex_op_b
-mb_fpex_op_a:
- .long 0
-mb_fpex_op_b:
- .long 0
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
-/* This is where we store the register used to check which exception occurred */
- .section .data
- .align 2
-mb_sp_save_r3:
- .long 0
-#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
-
-/* The exception vector table */
-.section .data
-.align 2
-.global MB_ExceptionVectorTable
-MB_ExceptionVectorTable:
- .long XNullHandler
- .long 0 /* -- FSL Exception -- */
- .long XNullHandler
- .long 1 /* -- Unaligned Access Exception -- */
- .long XNullHandler
- .long 2 /* -- Illegal Opcode Exception -- */
- .long XNullHandler
- .long 3 /* -- Instruction Bus Exception -- */
- .long XNullHandler
- .long 4 /* -- Data Bus Exception -- */
- .long XNullHandler
- .long 5 /* -- Div-by-0 Exception -- */
- .long XNullHandler
- .long 6 /* -- FPU Exception -- */
- .long XNullHandler
- .long 7 /* -- MMU Exceptions -- */
-
-#else /* Dummy exception handler, in case exceptions are not present in the processor */
-
-.global _hw_exception_handler
-.section .text
-.align 2
-.ent _hw_exception_handler
-_hw_exception_handler:
- bri 0;
-.end _hw_exception_handler
-
-#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef _MICROBLAZE_INTERFACE_H_
-#define _MICROBLAZE_INTERFACE_H_
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
-extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
-extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
-extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
-extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
-extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
-extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
-extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
-extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
-extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
-
-extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
-extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
-extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
-extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */
-extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */
-extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */
-extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
-extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
-extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
-extern void microblaze_flush_cache_ext_range(unsigned int cacheaddr,
- unsigned int len); /* Flush cache ext range */
-extern void microblaze_invalidate_cache_ext_range(unsigned int cacheaddr,
- unsigned int len); /* Invalidate cache ext range */
-
-/* Deprecated */
-extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated));
-extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated));
-extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated));
-extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated));
-
-/* necessary for pre-processor */
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-
-/* FSL Access Macros */
-
-/* Blocking Data Read and Write to FSL no. id */
-#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
-#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Non-blocking Data Read and Write to FSL no. id */
-#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
-#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Blocking Control Read and Write to FSL no. id */
-#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
-#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Non-blocking Control Read and Write to FSL no. id */
-#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
-#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Polling versions of FSL access macros. This makes the FSL access interruptible */
-#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- : "=d" (val) :: "r18")
-
-#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- :: "d" (val) : "r18")
-
-#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- : "=d" (val) :: "r18")
-
-#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- :: "d" (val) : "r18")
-/* FSL valid and error check macros. */
-#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
-#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
- "andi\t%0,%0,0x10" : "=d" (error))
-
-/* Pseudo assembler instructions */
-#define clz(v) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
- ); \
- _rval; \
- })
-
-#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
-#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
-
-#define mb_swapb(v) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
- ); \
- _rval; \
- })
-
-#define mb_swaph(v) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
- ); \
- _rval; \
- })
-
-#define mfgpr(rn) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfmsr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rmsr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfear() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rear\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfesr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,resr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mffsr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rfsr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfpvr(rn) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfbtr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rbtr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfedr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,redr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfpid() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rpid\n" : "=d"(_rval)\
- ); \
- _rval; \
- })
-
-#define mfzpr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rzpr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mftlbx() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rtlbx\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mftlblo() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rtlblo\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mftlbhi() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rtlbhi\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfslr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rslr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfshr() ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rshr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
- "or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
- ); \
- })
-
-#define mtmsr(v) ({ __asm__ __volatile__ ( \
- "mts\trmsr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-
-#define mtfsr(v) ({ __asm__ __volatile__ ( \
- "mts\trfsr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtpid(v) ({ __asm__ __volatile__ ( \
- "mts\trpid,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtzpr(v) ({ __asm__ __volatile__ ( \
- "mts\trzpr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlbx(v) ({ __asm__ __volatile__ ( \
- "mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlblo(v) ({ __asm__ __volatile__ ( \
- "mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlbhi(v) ({ __asm__ __volatile__ ( \
- "mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlbsx(v) ({ __asm__ __volatile__ ( \
- "mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtslr(v) ({ __asm__ __volatile__ ( \
- "mts\trslr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtshr(v) ({ __asm__ __volatile__ ( \
- "mts\trshr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define lwx(address) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-#define lwr(address) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-#define lhur(address) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-#define lbur(address) ({ unsigned int _rval; \
- __asm__ __volatile__ ( \
- "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-#define swx(address, data) ({ __asm__ __volatile__ ( \
- "swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define swr(address, data) ({ __asm__ __volatile__ ( \
- "swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define shr(address, data) ({ __asm__ __volatile__ ( \
- "shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define sbr(address, data) ({ __asm__ __volatile__ ( \
- "sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define microblaze_getfpex_operand_a() ({ \
- extern unsigned int mb_fpex_op_a; \
- mb_fpex_op_a; \
- })
-
-#define microblaze_getfpex_operand_b() ({ \
- extern unsigned int mb_fpex_op_b; \
- mb_fpex_op_b; \
- })
-
-/* Deprecated MicroBlaze FSL macros */
-#define microblaze_bread_datafsl(val, id) getfsl(val,id)
-#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
-#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
-#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
-#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
-#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
-#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
-#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
-
-#ifdef __cplusplus
-}
-#endif
-#endif // _MICROBLAZE_INTERFACE_H_
+++ /dev/null
-/******************************************************************************
-* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.
-*
-* Xilinx, Inc.
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
-* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
-* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
-* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
-* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
-* AND FITNESS FOR A PARTICULAR PURPOSE.
-*
-* File : microblaze_disable_dcache.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Disable the L1 dcache on the microblaze.
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_dcache
- .ent microblaze_disable_dcache
- .align 2
-microblaze_disable_dcache:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
-
-#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
- addik r1, r1, -4
- swi r15, r1, 0
- brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
- nop
- lwi r15, r1, 0
- addi r1, r1, 4
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
- rtsd r15, 8
- msrclr r0, 0x80
-
-#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
-
- addik r1, r1, -4
-
-#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
- swi r15, r1, 0
- brlid r15, microblaze_flush_dcache
- nop
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
- mfs r11, rmsr
- andi r11, r11, ~(0x80)
- mts rmsr, r11
-
-#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
- lwi r15, r1, 0
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
-
- rtsd r15, 8
- addi r1, r1, 4
-
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_disable_dcache
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#
-# Disable exceptions on microblaze.
-#
-#
-####################################################################
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_exceptions
- .ent microblaze_disable_exceptions
- .align 2
-microblaze_disable_exceptions:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x100
-#else
- mfs r4, rmsr;
- andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
- mts rmsr, r4;
- rtsd r15, 8;
- nop;
-#endif
-.end microblaze_disable_exceptions
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#
-# File : microblaze_disable_icache.s
-# Date : 2002, March 20.
-# Company: Xilinx
-# Group : Emerging Software Technologies
-#
-# Summary:
-# Disable L1 icache on the microblaze.
-#
-#
-####################################################################
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_icache
- .ent microblaze_disable_icache
- .align 2
-microblaze_disable_icache:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x20
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r8, rmsr
- #Clear the icache enable bit
- andi r8, r8, ~(0x20)
- #Save the MSR register
- mts rmsr, r8
- #Return
- rtsd r15, 8
- nop
-#endif
- .end microblaze_disable_icache
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#
-# File : microblaze_disable_interrupts.s
-# Date : 2002, March 20.
-# Company: Xilinx
-# Group : Emerging Software Technologies
-#
-# Summary:
-# Disable interrupts on the microblaze.
-#
-#
-####################################################################
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_interrupts
- .ent microblaze_disable_interrupts
- .align 2
-microblaze_disable_interrupts:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x2
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r12, rmsr
- #Clear the interrupt enable bit
- andi r12, r12, ~(0x2)
- #Save the MSR register
- mts rmsr, r12
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_disable_interrupts
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#
-# File : microblaze_enable_dcache.s
-# Date : 2002, March 20.
-# Company: Xilinx
-# Group : Emerging Software Technologies
-#
-# Summary:
-# Enable L1 dcache on the microblaze.
-#
-#
-####################################################################
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_dcache
- .ent microblaze_enable_dcache
- .align 2
-microblaze_enable_dcache:
-
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrset r0, 0x80
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r8, rmsr
- #Set the interrupt enable bit
- ori r8, r8, 0x80
- #Save the MSR register
- mts rmsr, r8
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_enable_dcache
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#
-# Enable exceptions on microblaze.
-#
-#
-####################################################################
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_exceptions
- .ent microblaze_enable_exceptions
- .align 2
-microblaze_enable_exceptions:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8;
- msrset r0, 0x100
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- mfs r4, rmsr;
- ori r4, r4, 0x100; /* Turn ON the EE bit */
- mts rmsr, r4;
- rtsd r15, 8;
- nop;
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
-.end microblaze_enable_exceptions
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#
-# File : microblaze_enable_icache.s
-# Date : 2002, March 20.
-# Company: Xilinx
-# Group : Emerging Software Technologies
-#
-# Summary:
-# Enable icache on the microblaze.
-#
-#
-####################################################################
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_icache
- .ent microblaze_enable_icache
- .align 2
-microblaze_enable_icache:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrset r0, 0x20
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r8, rmsr
- #Set the interrupt enable bit
- ori r8, r8, 0x20
- #Save the MSR register
- mts rmsr, r8
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_enable_icache
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#
-# File : microblaze_enable_interrupts.s
-# Date : 2002, March 20.
-# Company: Xilinx
-# Group : Emerging Software Technologies
-#
-# Summary:
-# Enable interrupts on the microblaze.
-#
-#
-####################################################################
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_interrupts
- .ent microblaze_enable_interrupts
- .align 2
-microblaze_enable_interrupts:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrset r0, 0x2
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r12, rmsr
- #Set the interrupt enable bit
- ori r12, r12, 0x2
- #Save the MSR register
- mts rmsr, r12
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_enable_interrupts
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_exception_handler.c
-*
-* This file contains exception handler registration routines for
-* the MicroBlaze processor.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 06/24/04 First release
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "microblaze_exceptions_i.h"
-#include "microblaze_exceptions_g.h"
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
-/****************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* Registers an exception handler for the MicroBlaze. The
-* argument provided in this call as the DataPtr is used as the argument
-* for the handler when it is called.
-*
-* @param ExceptionId is the id of the exception to register this handler
-* for.
-* @param Top level handler.
-* @param DataPtr is a reference to data that will be passed to the handler
-* when it gets called.
-* @return None.
-*
-* @note
-*
-* None.
-*
-****************************************************************************/
-void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr)
-{
- MB_ExceptionVectorTable[ExceptionId].Handler = Handler;
- MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr;
-}
-
-#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Exception Handling Header for MicroBlaze Processor\r
-*\r
-*******************************************************************/\r
-\r
-#define MICROBLAZE_EXCEPTIONS_ENABLED 1\r
-#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS\r
-#define MICROBLAZE_FP_EXCEPTION_ENABLED 1\r
-\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file microblaze_exceptions_i.h
-*
-* This header file contains defines for structures used by the microblaze
-* hardware exception handler.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00a 06/24/04 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
-#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct
-{
- Xil_ExceptionHandler Handler;
- void *CallBackRef;
-} MB_ExceptionVectorTableEntry;
-
-/* Exception IDs */
-#define XEXC_ID_FSL 0
-#define XEXC_ID_UNALIGNED_ACCESS 1
-#define XEXC_ID_ILLEGAL_OPCODE 2
-#define XEXC_ID_M_AXI_I_EXCEPTION 3
-#define XEXC_ID_IPLB_EXCEPTION 3
-#define XEXC_ID_M_AXI_D_EXCEPTION 4
-#define XEXC_ID_DPLB_EXCEPTION 4
-#define XEXC_ID_DIV_BY_ZERO 5
-#define XEXC_ID_FPU 6
-#define XEXC_ID_STACK_VIOLATION 7
-#define XEXC_ID_MMU 7
-
-void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_flush_cache_ext()
-*
-* Flush the entire L2 Cache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
- .text
- .globl microblaze_flush_cache_ext
- .ent microblaze_flush_cache_ext
- .align 2
-
-microblaze_flush_cache_ext:
-
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
-
- addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
-Loop_start:
- wdc.ext.flush r5, r6
- bgtid r6,Loop_start
- addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
- rtsd r15, 8
- nop
- .end microblaze_flush_cache_ext
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
-*
-*Flush a L2 Cache range
-*
-*Parameters:
-* 'cacheaddr' - address in the L2 cache where the flush begins
-* 'len ' - length (in bytes) worth of L2 cache to be flushed
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
- .text
- .globl microblaze_flush_cache_ext_range
- .ent microblaze_flush_cache_ext_range
- .align 2
-
-microblaze_flush_cache_ext_range:
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- beqi r6, Loop_done
-
- addik r6, r6, -1
- add r6, r5, r6
-
- andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
- rsubk r6, r5, r6
-Loop_start:
- wdc.ext.flush r5, r6
- bneid r6, Loop_start
- addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
-Loop_done:
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_flush_cache_ext_range
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_flush_dcache()
-*
-* Flush the L1 DCache
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_flush_dcache
- .ent microblaze_flush_dcache
- .align 2
-
-microblaze_flush_dcache:
- addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
- addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
-
-L_start:
- wdc.flush r5, r0 /* Flush the Cache */
-
- cmpu r18, r5, r6 /* Are we at the end? */
- blei r18, L_done
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
- nop
- .end microblaze_flush_dcache
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len)
-*
-* Flush a L1 DCache range
-*
-* Parameters:
-* 'cacheaddr' - address in the Dcache where the flush begins
-* 'len ' - length (in bytes) worth of Dcache to be flushed
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#define MB_HAS_WRITEBACK_SET 0
-#else
-#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#endif
-
- .text
- .globl microblaze_flush_dcache_range
- .ent microblaze_flush_dcache_range
- .align 2
-
-microblaze_flush_dcache_range:
-
-#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
-
- beqi r6, L_done /* Skip loop if size is zero */
-
- add r6, r5, r6 /* Compute end address */
- addik r6, r6, -1
-
- andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
- andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
-
-#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
-
-L_start:
- cmpu r18, r5, r6 /* Are we at the end? */
- blti r18, L_done
-
- wdc r5, r0 /* Invalidate the cache line */
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-#else
- rsubk r6, r5, r6
- /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
-L_start:
- wdc.flush r5, r6 /* Flush the cache line */
- bneid r6, L_start
- addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
-
-#endif
-
-L_done:
- rtsd r15, 8
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
- .end microblaze_flush_dcache_range
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len)
-*
-* Invalidate dcache on the microblaze
-*
-* Parameters:
-* 'cache_start' - address in the Dcache where invalidation begins
-* 'cache_len' - length (in bytes) worth of Dcache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_init_dcache_range
- .ent microblaze_init_dcache_range
- .align 2
-
-microblaze_init_dcache_range:
-
- mfs r9, rmsr /* Disable Dcache and interrupts before invalidating */
- andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-
- andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
-
- add r6, r5, r6 /* Compute end */
- andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
-
-L_start:
- wdc r5, r0 /* Invalidate the Cache (delay slot) */
-
- cmpu r18, r5, r6 /* Are we at the end ? */
- blei r18, L_done
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
- mts rmsr, r9
- .end microblaze_init_dcache_range
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-*
-* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len)
-*
-* Invalidate icache on the microblaze
-*
-* Parameters:
-* 'cache_start' - address in the Icache where invalidation begins
-* 'cache_len' - length (in bytes) worth of Icache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_init_icache_range
- .ent microblaze_init_icache_range
- .align 2
-
-microblaze_init_icache_range:
-
- mfs r9, rmsr /* Disable Icache and interrupts before invalidating */
- andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-
- andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
-
- add r6, r5, r6 /* Compute end */
- andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
-
-L_start:
- wic r5, r0 /* Invalidate the Cache (delay slot) */
-
- cmpu r18, r5, r6 /* Are we at the end ? */
- blei r18, L_done
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
- mts rmsr, r9
- .end microblaze_init_icache_range
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file microblaze_interrupt_handler.c
-*
-* This file contains the standard interrupt handler for the MicroBlaze processor.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 10/03/03 First release
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xil_exception.h"
-#include "microblaze_interrupts_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-void __interrupt_handler (void) __attribute__ ((interrupt_handler));
-
-/************************** Variable Definitions *****************************/
-
-extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
-/*****************************************************************************/
-/**
-*
-* This function is the standard interrupt handler used by the MicroBlaze processor.
-* It saves all volatile registers, calls the users top level interrupt handler.
-* When this returns, it restores all registers, and returns using a rtid instruction.
-*
-* @param
-*
-* None
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void __interrupt_handler(void)
-{
- /* The compiler saves all volatiles and the MSR */
- MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
- /* The compiler restores all volatiles and MSR, and returns from interrupt */
-}
-
-/****************************************************************************/
-/*****************************************************************************/
-/**
-*
-* Registers a top-level interrupt handler for the MicroBlaze. The
-* argument provided in this call as the DataPtr is used as the argument
-* for the handler when it is called.
-*
-* @param Top level handler.
-* @param DataPtr is a reference to data that will be passed to the handler
-* when it gets called.
-
-* @return None.
-*
-* @note
-*
-* None.
-*
-****************************************************************************/
-void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
-{
- MB_InterruptVectorTable.Handler = Handler;
- MB_InterruptVectorTable.CallBackRef = DataPtr;
-}
-
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Interrupt Handler Table for MicroBlaze Processor\r
-*\r
-*******************************************************************/\r
-\r
-#include "microblaze_interrupts_i.h"\r
-#include "xparameters.h"\r
-\r
-\r
-extern void XIntc_DeviceInterruptHandler (void *);\r
-\r
-/*\r
-* The interrupt handler table for microblaze processor\r
-*/\r
-\r
-MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =\r
-{\r
-{ XIntc_DeviceInterruptHandler,\r
- (void*) XPAR_AXI_INTC_0_DEVICE_ID}\r
-};\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file microblaze_interrupts_i.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* High-level driver functions are defined in xintc.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 10/03/03 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
-#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct
-{
- XInterruptHandler Handler;
- void *CallBackRef;
-} MB_InterruptVectorTableEntry;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_invalidate_cache_ext()
-*
-*Invalidate the entire L2 Cache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
- .text
- .globl microblaze_invalidate_cache_ext
- .ent microblaze_invalidate_cache_ext
- .align 2
-
-microblaze_invalidate_cache_ext:
-
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
-
- addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
-Loop_start:
- wdc.ext.clear r5, r6
- bgtid r6,Loop_start
- addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_invalidate_cache_ext
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
-*
-*Invalidate an L2 cache range
-*
-*Parameters:
-* 'cacheaddr' - address in the L2 cache where invalidation begins
-* 'len ' - length (in bytes) worth of Dcache to be invalidated
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
- .text
- .globl microblaze_invalidate_cache_ext_range
- .ent microblaze_invalidate_cache_ext_range
- .align 2
-
-microblaze_invalidate_cache_ext_range:
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- beqi r6, Loop_done
-
- add r6, r5, r6
- addik r6, r6, -1
-
- andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
- rsubk r6, r5, r6
-
-Loop_start:
- wdc.ext.clear r5, r6
- bneid r6, Loop_start
- addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
-Loop_done:
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_invalidate_cache_ext_range
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_invalidate_dcache()
-*
-* Invalidate the entire L1 DCache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#endif
-
- .text
- .globl microblaze_invalidate_dcache
- .ent microblaze_invalidate_dcache
- .align 2
-
-microblaze_invalidate_dcache:
-
-#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
- addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
- addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
-
-L_start:
- wdc r5, r0 /* Invalidate the Cache */
-
- cmpu r18, r5, r6 /* Are we at the end? */
- blei r18, L_done
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
-
- .end microblaze_invalidate_dcache
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-*
-* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
-*
-* Invalidate a Dcache range
-*
-* Parameters:
-* 'cacheaddr' - address in the Dcache where invalidation begins
-* 'len ' - length (in bytes) worth of Dcache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#define MB_HAS_WRITEBACK_SET 0
-#else
-#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#endif
-
- .text
- .globl microblaze_invalidate_dcache_range
- .ent microblaze_invalidate_dcache_range
- .align 2
-
-microblaze_invalidate_dcache_range:
-
-
-#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
-
- beqi r6, L_done /* Skip loop if size is zero */
-
- add r6, r5, r6 /* Compute end address */
- addik r6, r6, -1
-
- andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
- andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
-
-#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
-
-L_start:
- cmpu r18, r5, r6 /* Are we at the end? */
- blti r18, L_done
-
- wdc r5, r0
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-#else
-
- rsubk r6, r5, r6
- /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
-L_start:
- wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
- bneid r6, L_start
- addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
-
-#endif
-
-L_done:
- rtsd r15, 8
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
- .end microblaze_invalidate_dcache_range
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-*
-* microblaze_invalidate_icache()
-*
-* Invalidate the entire ICache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#endif
-
- .text
- .globl microblaze_invalidate_icache
- .ent microblaze_invalidate_icache
- .align 2
-
-microblaze_invalidate_icache:
-
-#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
- addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
- addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
-L_start:
- wic r5, r0 /* Invalidate the Cache */
-
- cmpu r18, r5, r6 /* Are we at the end? */
- blei r18, L_done
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
-
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
- .end microblaze_invalidate_icache
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-*
-* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
-*
-* Invalidate an ICache range
-*
-* Parameters:
-* 'cacheaddr' - address in the Icache where invalidation begins
-* 'len' - length (in bytes) worth of Icache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#endif
-
- .text
- .globl microblaze_invalidate_icache_range
- .ent microblaze_invalidate_icache_range
- .align 2
-
-microblaze_invalidate_icache_range:
-
-#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
-
- beqi r6, L_done /* Skip loop if size is zero */
-
- add r6, r5, r6 /* Compute end address */
- addik r6, r6, -1
-
- andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
- andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
-
-L_start:
- cmpu r18, r5, r6 /* Are we at the end? */
- blti r18, L_done
-
- wic r5, r0 /* Invalidate the cache line */
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
- .end microblaze_invalidate_icache_range
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* microblaze_scrub ()
-*
-* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
-* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
-* of an uncorrectable error when fault tolerance support is enabled.
-*
-* This routine assumes that the processor is in privileged mode when it is
-* called, if the MMU is enabled.
-*
-* Call this routine regularly from a timer interrupt.
-*
-* Parameters:
-* None
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-/* Define if fault tolerance is used */
-#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
- #if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
- #define FAULT_TOLERANT
- #endif
-#endif
-
-/* Define if LMB is used and can be scrubbed */
-#if defined(XPAR_MICROBLAZE_D_LMB) && \
- defined(XPAR_DLMB_CNTLR_BASEADDR) && \
- defined(XPAR_DLMB_CNTLR_HIGHADDR)
- #if XPAR_MICROBLAZE_D_LMB == 1
- #define HAS_SCRUBBABLE_LMB
- #define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
- #endif
-#endif
-
-/* Set default cache line lengths */
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
- #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
-#endif
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
- #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
-#endif
-
-/* Define if internal Data Cache BRAMs are used */
-#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
- #if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
- #define HAS_BRAM_DCACHE
- #define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
- #define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
- #endif
-#endif
-
-/* Define if internal Instruction Cache BRAMs are used */
-#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
- #if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
- #define HAS_BRAM_ICACHE
- #define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
- #define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
- #endif
-#endif
-
-/* Define if internal MMU UTLB BRAM is used */
-#ifdef XPAR_MICROBLAZE_USE_MMU
- #if XPAR_MICROBLAZE_USE_MMU > 1
- #define HAS_BRAM_MMU_UTLB
- #endif
-#endif
-
-/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
-#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
- defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
- #if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
- #if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
- XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
- #define HAS_BRAM_BRANCH_TARGET_CACHE
- #ifdef HAS_BRAM_DCACHE
- #define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
- #else
- #define BTC_MASK_D 256
- #endif
- #ifdef HAS_BRAM_ICACHE
- #define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
- #else
- #define BTC_MASK_I 256
- #endif
- #if BTC_MASK_D > BTC_MASK_I
- #define BTC_MASK BTC_MASK_D
- #else
- #define BTC_MASK BTC_MASK_I
- #endif
- #endif
- #endif
-#endif
-
-/* Define index offsets to persistent data used by this routine */
-#define DLMB_INDEX_OFFSET 0
-#define DCACHE_INDEX_OFFSET 4
-#define ICACHE_INDEX_OFFSET 8
-#define MMU_INDEX_OFFSET 12
-#define BTC_CALL_COUNT_OFFSET 16
-
- .text
- .globl microblaze_scrub
- .ent microblaze_scrub
- .align 2
-
-microblaze_scrub:
-#ifdef FAULT_TOLERANT
- la r6, r0, L_persistent_data /* Get pointer to data */
-
-#ifdef HAS_SCRUBBABLE_LMB
-L_dlmb:
- lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
- lw r7, r5, r0 /* Load and store */
- sw r7, r5, r0
- addik r5, r5, 4 /* Increment and save dlmb index */
- andi r5, r5, DLMB_MASK
- swi r5, r6, DLMB_INDEX_OFFSET
-#endif /* HAS_SCRUBBABLE_LMB */
-
-#ifdef HAS_BRAM_DCACHE
-L_dcache:
- lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
- wdc r5, r0 /* Invalidate data cache line */
- addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
- andi r5, r5, DCACHE_MASK
- swi r5, r6, DCACHE_INDEX_OFFSET
-#endif /* HAS_BRAM_DCACHE */
-
-#ifdef HAS_BRAM_ICACHE
-L_icache:
- lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
- wic r5, r0 /* Invalidate data cache line */
- addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
- andi r5, r5, ICACHE_MASK
- swi r5, r6, ICACHE_INDEX_OFFSET
-#endif /* HAS_BRAM_ICACHE */
-
-#ifdef HAS_BRAM_MMU_UTLB
-L_mmu:
- lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
- mts rtlbx, r5 /* Access next entry in UTLB */
- mts rtlbhi, r0 /* Clear the UTLB entry */
-
- addik r5, r5, 1 /* Increment and save entry index */
- andi r5, r5, 0x3F
- swi r5, r6, MMU_INDEX_OFFSET
-#endif /* HAS_BRAM_MMU_UTLB */
-
-#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
-L_btc:
- lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
- addik r5, r5, 1 /* Increment and save call count */
- andi r5, r5, BTC_MASK
- swi r5, r6, BTC_CALL_COUNT_OFFSET
-
- bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
- bri 4 /* Clear branch target cache */
-L_skip_btc_scrub:
-#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
-
-#endif /* FAULT_TOLERANT */
-L_done:
- rtsd r15, 8 /* Return */
- nop
- .end microblaze_scrub
-
- /* Persistent data used by this routine */
- .data
- .align 2
-L_persistent_data:
- .long 0 /* dlmb index */
- .long 0 /* dcache index */
- .long 0 /* icache index */
- .long 0 /* mmu entry index */
- .long 0 /* btc call count */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file microblaze_sleep.c
-*
-* Contains implementation of microblaze sleep function.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.1 hk 04/18/14 Add sleep function.
-*
-* </pre>
-*
-* @note
-*
-* This file may contain architecture-dependent code.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "microblaze_sleep.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-
-/*****************************************************************************/
-/**
-*
-* Provides delay for requested duration.
-*
-* @param Delay time in milliseconds.
-*
-* @return None.
-*
-* @note Instruction cache should be enabled for this to work.
-*
-******************************************************************************/
-void MB_Sleep(unsigned int MilliSeconds)
-{
- if (((mfmsr() & 0x20) == 0)) {
- /*
- * Instruction cache not enabled.
- * Delay will be much higher than expected.
- */
- }
-
- asm volatile ("\n"
- "1: \n\t"
- "addik r7, r0, %0 \n\t"
- "2: \n\t"
- "addik r7, r7, -1 \n\t"
- "bneid r7, 2b \n\t"
- "or r0, r0, r0 \n\t"
- "bneid %1, 1b \n\t"
- "addik %1, %1, -1 \n\t"
- :: "i"(ITERS_PER_MSEC), "d" (MilliSeconds));
-
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file microblaze_sleep.h
-*
-* Contains microblaze sleep function API.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.1 asa 04/18/14 Add sleep function - first release.
-*
-* </pre>
-*
-* @note
-*
-* This file may contain architecture-dependent items.
-*
-******************************************************************************/
-
-#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */
-#define MICROBLAZE_SLEEP_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "mb_interface.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define ITERS_PER_MSEC ((XPAR_CPU_CORE_CLOCK_FREQ_HZ / 1000) / 6)
-
-/************************** Function Prototypes ******************************/
-
-void MB_Sleep(unsigned int MilliSeconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-*
-* File : microblaze_update_dcache.s
-* Date : 2003, September 24
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Update dcache on the microblaze.
-* Takes in three parameters
-* r5 : Cache Tag Line
-* r6 : Cache Data
-* r7 : Lock/Valid information
-* Bit 30 is Lock [ 1 indicates locked ]
-* Bit 31 is Valid [ 1 indicates valid ]
-*
-* --------------------------------------------------------------
-* | Lock | Valid | Effect
-* --------------------------------------------------------------
-* | 0 | 0 | Invalidate Cache
-* | 0 | 1 | Valid, but unlocked cacheline
-* | 1 | 0 | Invalidate Cache, No effect of lock
-* | 1 | 1 | Valid cache. Locked to a
-* | | | particular addrees
-* --------------------------------------------------------------
-*
-*
-**********************************************************************************/
-#include "xparameters.h"
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_update_dcache
- .ent microblaze_update_dcache
- .align 2
-microblaze_update_dcache:
-
-#if XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1
-
-/* Read the MSR register into a temp register */
- mfs r18, rmsr
-
-/* Clear the dcache enable bit to disable the cache
- Register r10,r18 are volatile registers and hence do not need to be saved before use */
- andi r10, r18, ~128
- mts rmsr, r10
-
-/* Update the lock and valid info */
- andi r5, r5, 0xfffffffc
- or r5, r5, r7
-
-/* Update dcache */
- wdc r5, r6
-
-/* Return */
- rtsd r15, 8
- mts rmsr, r18
-
-#else
-
- /* The only valid usage of this routine for larger cache line lengths is to invalidate a data cache line
- So call microblaze_init_dcache_range appropriately to do the job */
-
- brid microblaze_init_dcache_range
- addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
-
- /* We don't have a return instruction here. This is tail call optimization :) */
-
-#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */
-
- .end microblaze_update_dcache
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-* File : microblaze_update_icache.s
-* Date : 2003, September 24
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Update icache on the microblaze.
-* Takes in three parameters
-* r5 : Cache Tag Line
-* r6 : Cache Data
-* r7 : Lock/Valid information
-* Bit 30 is Lock [ 1 indicates locked ]
-* Bit 31 is Valid [ 1 indicates valid ]
-*
-* --------------------------------------------------------------
-* | Lock | Valid | Effect
-* --------------------------------------------------------------
-* | 0 | 0 | Invalidate Cache
-* | 0 | 1 | Valid, but unlocked cacheline
-* | 1 | 0 | Invalidate Cache, No effect of lock
-* | 1 | 1 | Valid cache. Locked to a
-* | | | particular addrees
-* --------------------------------------------------------------
-*
-*
-**********************************************************************************/
-#include "xparameters.h"
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_update_icache
- .ent microblaze_update_icache
- .align 2
-microblaze_update_icache:
-
-#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
-
-/* Read the MSR register into a temp register */
- mfs r18, rmsr
-
-/* Clear the icache enable bit to disable the cache
- Register r10,r18 are volatile registers and hence do not need to be saved before use */
- andi r10, r18, ~32
- mts rmsr, r10
-
-/* Update the lock and valid info */
- andi r5, r5, 0xfffffffc
- or r5, r5, r7
-
-/* Update icache */
- wic r5, r6
-
-/* Return */
- rtsd r15, 8
- mts rmsr, r18
-
-#else
-
- /* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line
- So call microblaze_init_icache_range appropriately to do the job */
-
- brid microblaze_init_icache_range
- addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
-
- /* We don't have a return instruction here. This is tail call optimization :) */
-
-#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
-
- .end microblaze_update_icache
-
+++ /dev/null
-#$Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
-###############################################################################
-#
-# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# Use of the Software is limited solely to applications:
-# (a) running on a Xilinx device, or
-# (b) that interact with a Xilinx device through a bus or interconnect.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-#
-# Except as contained in this notice, the name of the Xilinx shall not be used
-# in advertising or otherwise to promote the sale, use or other dealings in
-# this Software without prior written authorization from Xilinx.
-#
-###############################################################################
-#
-# Makefile for profiler
-#
-#######################################################################
-
-# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
-include ../config.make
-
-AS=mb-as
-COMPILER = mb-gcc
-ARCHIVER = mb-ar
-CP = cp
-COMPILER_FLAGS=-O2
-EXTRA_COMPILER_FLAGS=
-LIB = libxil.a
-DUMMYLIB = libxilprofile.a
-
-CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
-
-RELEASEDIR = ../../../../lib
-INCLUDEDIR = ../../../../include
-INCLUDES = -I./. -I${INCLUDEDIR}
-
-OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
-DUMMYOBJ = dummy.o
-INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
-
-libs : reallibs dummylibs
-
-reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
- $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
-
-dummylibs : $(DUMMYOBJ)
- $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
-
-%.o:%.c
- $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
-
-%.o:%.S
- $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
-
-include:
- $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
+++ /dev/null
-// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#include "xil_exception.h"
-
-/*
- * This function is the exit routine and is called by the crtinit, when the
- * program terminates. The name needs to be changed later..
- */
-void _profile_clean( void )
-{
- Xil_ExceptionDisable();
- disable_timer();
-}
-
+++ /dev/null
-// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_init.c:
-* Initialize the Profiling Structures.
-*
-******************************************************************************/
-
-#include "profile.h"
-
-// XMD Initializes the following Global Variables Value during Program
-// Download with appropriate values.
-
-#ifdef PROC_MICROBLAZE
-
-extern int microblaze_init(void);
-
-#elif defined PROC_PPC
-
-extern int powerpc405_init(void);
-
-#else
-
-extern int cortexa9_init(void);
-
-#endif
-
-
-
-int profile_version = 1; // Version of S/W Intrusive Profiling library
-
-int binsize = BINSIZE; // Histogram Bin Size
-unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency
-unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency
-unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer
-
-// Structure for Storing the Profiling Data
-struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff;
-int n_gmon_sections = 1;
-
-// This is the initialization code, which is called from the crtinit.
-//
-void _profile_init( void )
-{
-/* print("Gmon Init called....\r\n") ; */
-/* putnum(n_gmon_sections) ; print("\r\n") ; */
-/* if( _gmonparam == 0xffffffff ) */
-/* printf("Gmonparam is NULL !!\r\n"); */
-/* for( i = 0; i < n_gmon_sections; i++ ){ */
-/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */
-/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */
-/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */
-/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */
-/* } */
-
-#ifdef PROC_MICROBLAZE
- microblaze_init();
-#elif defined PROC_PPC
- powerpc405_init();
-#else
- cortexa9_init ();
-#endif
-}
-
+++ /dev/null
-// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_timer_hw.c:
-* Timer related functions
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-
-#include "xil_exception.h"
-
-#ifdef PROC_PPC
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif // TIMER_CONNECT_INTC
-
-//#ifndef PPC_PIT_INTERRUPT
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-extern unsigned int timer_clk_ticks ;
-
-//--------------------------------------------------------------------
-// PowerPC Target - Timer related functions
-//--------------------------------------------------------------------
-#ifdef PROC_PPC405
-
-
-//--------------------------------------------------------------------
-// PowerPC PIT Timer Init.
-// Defined only if PIT Timer is used for Profiling
-//
-//--------------------------------------------------------------------
-#ifdef PPC_PIT_INTERRUPT
-int ppc_pit_init( void )
-{
- // 1. Register Profile_intr_handler as Interrupt handler
- // 2. Set PIT Timer Interrupt and Enable it.
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
- (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
- XTime_PITSetInterval( timer_clk_ticks ) ;
- XTime_PITEnableAutoReload() ;
- return 0;
-}
-#endif
-
-
-//--------------------------------------------------------------------
-// PowerPC Timer Initialization functions.
-// For PowerPC, PIT and opb_timer can be used for Profiling. This
-// is selected by the user in standalone BSP
-//
-//--------------------------------------------------------------------
-int powerpc405_init()
-{
- Xil_ExceptionInit() ;
- Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-
- // Initialize the Timer.
- // 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
- // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
-#ifdef PPC_PIT_INTERRUPT
- ppc_pit_init();
-#else
-#ifdef TIMER_CONNECT_INTC
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,(void*)0);
-#else
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
-#endif
- // Initialize the timer with Timer Ticks
- opb_timer_init() ;
-#endif
-
- // Enable Interrupts in the System, if Profile Timer is the only Interrupt
- // in the System.
-#ifdef ENABLE_SYS_INTR
-#ifdef PPC_PIT_INTERRUPT
- XTime_PITEnableInterrupt() ;
-#elif TIMER_CONNECT_INTC
- XIntc_MasterEnable( INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
-#endif
- Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-#endif
- return 0;
-}
-
-#endif // PROC_PPC
-
-
-
-//--------------------------------------------------------------------
-// PowerPC440 Target - Timer related functions
-//--------------------------------------------------------------------
-#ifdef PROC_PPC440
-
-
-//--------------------------------------------------------------------
-// PowerPC DEC Timer Init.
-// Defined only if DEC Timer is used for Profiling
-//
-//--------------------------------------------------------------------
-#ifdef PPC_PIT_INTERRUPT
-int ppc_dec_init( void )
-{
- // 1. Register Profile_intr_handler as Interrupt handler
- // 2. Set DEC Timer Interrupt and Enable it.
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
- (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
- XTime_DECSetInterval( timer_clk_ticks ) ;
- XTime_DECEnableAutoReload() ;
- return 0;
-}
-#endif
-
-
-//--------------------------------------------------------------------
-// PowerPC Timer Initialization functions.
-// For PowerPC, DEC and opb_timer can be used for Profiling. This
-// is selected by the user in standalone BSP
-//
-//--------------------------------------------------------------------
-int powerpc405_init(void)
-{
- Xil_ExceptionInit();
- Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-
- // Initialize the Timer.
- // 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
- // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
-#ifdef PPC_PIT_INTERRUPT
- ppc_dec_init();
-#else
-#ifdef TIMER_CONNECT_INTC
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
-
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,(void*)0);
-#else
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
-#endif
- // Initialize the timer with Timer Ticks
- opb_timer_init() ;
-#endif
-
- // Enable Interrupts in the System, if Profile Timer is the only Interrupt
- // in the System.
-#ifdef ENABLE_SYS_INTR
-#ifdef PPC_PIT_INTERRUPT
- XTime_DECEnableInterrupt() ;
-#elif TIMER_CONNECT_INTC
- XIntc_MasterEnable( INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
-#endif
- Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
-#endif
- return 0;
-}
-
-#endif // PROC_PPC440
-
-//--------------------------------------------------------------------
-// opb_timer Initialization for PowerPC and MicroBlaze. This function
-// is not needed if DEC timer is used in PowerPC
-//
-//--------------------------------------------------------------------
-//#ifndef PPC_PIT_INTERRUPT
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-int opb_timer_init( void )
-{
- // set the number of cycles the timer counts before interrupting
- XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks);
-
- // reset the timers, and clear interrupts
- XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0,
- XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
-
- // start the timers
- XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK
- | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
- return 0;
-}
-#endif
-
-
-//--------------------------------------------------------------------
-// MicroBlaze Target - Timer related functions
-//--------------------------------------------------------------------
-#ifdef PROC_MICROBLAZE
-
-//--------------------------------------------------------------------
-// Initialize the Profile Timer for MicroBlaze Target.
-// For MicroBlaze, opb_timer is used. The opb_timer can be directly
-// connected to MicroBlaze or connected through Interrupt Controller.
-//
-//--------------------------------------------------------------------
-int microblaze_init(void)
-{
- // Register profile_intr_handler
- // 1. If timer is connected to Interrupt Controller, register the handler
- // to Interrupt Controllers vector table.
- // 2. If timer is directly connected to MicroBlaze, register the handler
- // as Interrupt handler
- Xil_ExceptionInit();
-
-#ifdef TIMER_CONNECT_INTC
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,(void*)0);
-#else
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler)profile_intr_handler,
- (void *)0) ;
-#endif
-
- // Initialize the timer with Timer Ticks
- opb_timer_init() ;
-
- // Enable Interrupts in the System, if Profile Timer is the only Interrupt
- // in the System.
-#ifdef ENABLE_SYS_INTR
-#ifdef TIMER_CONNECT_INTC
- XIntc_MasterEnable( INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
-#endif
-
-#endif
-
- Xil_ExceptionEnable();
-
- return 0;
-
-}
-
-#endif // PROC_MICROBLAZE
-
-
-
-//--------------------------------------------------------------------
-// Cortex A9 Target - Timer related functions
-//--------------------------------------------------------------------
-#ifdef PROC_CORTEXA9
-
-//--------------------------------------------------------------------
-// Initialize the Profile Timer for Cortex A9 Target.
-// The scu private timer is connected to the Scu GIC controller.
-//
-//--------------------------------------------------------------------
-int scu_timer_init( void )
-{
- // set the number of cycles the timer counts before interrupting
- // scu timer runs at half the cpu clock
- XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2);
-
- // clear any pending interrupts
- XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1);
-
- // enable interrupts, auto-reload mode and start the timer
- XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
-
- return 0;
-}
-
-int cortexa9_init(void)
-{
-
- Xil_ExceptionInit();
-
- XScuGic_DeviceInitialize(0);
-
- /*
- * Connect the interrupt controller interrupt handler to the hardware
- * interrupt handling logic in the processor.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
- (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
- (void *)0);
-
- /*
- * Connect the device driver handler that will be called when an
- * interrupt for the device occurs, the handler defined above performs
- * the specific interrupt processing for the device.
- */
- XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
- PROFILE_TIMER_INTR_ID,
- (Xil_ExceptionHandler)profile_intr_handler,
- (void *)0);
-
- /*
- * Enable the interrupt for scu timer.
- */
- XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
-
- /*
- * Enable interrupts in the Processor.
- */
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
-
- /*
- * Initialize the timer with Timer Ticks
- */
- scu_timer_init() ;
-
- Xil_ExceptionEnable();
-
- return 0;
-}
-
-#endif // PROC_CORTEXA9
+++ /dev/null
-// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
-/******************************************************************************
-*
-* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************
-*
-* _program_timer_hw.h:
-* Timer related functions
-*
-******************************************************************************/
-
-#ifndef _PROFILE_TIMER_HW_H
-#define _PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (RegOffset)), (ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif // TIMER_CONNECT_INTC
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern unsigned int timer_clk_ticks ;
-
-//--------------------------------------------------------------------
-// PowerPC Target - Timer related functions
-//--------------------------------------------------------------------
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-//--------------------------------------------------------------------
-// Disable the Timer - During Profiling
-//
-// For PIT Timer -
-// 1. XTime_PITDisableInterrupt() ;
-// 2. Store the remaining timer clk tick
-// 3. Stop the PIT Timer
-//--------------------------------------------------------------------
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- unsigned long val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-//--------------------------------------------------------------------
-// Enable the Timer
-//
-// For PIT Timer -
-// 1. Load the remaining timer clk ticks
-// 2. XTime_PITEnableInterrupt() ;
-//--------------------------------------------------------------------
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- unsigned long val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-//--------------------------------------------------------------------
-// Send Ack to Timer Interrupt
-//
-// For PIT Timer -
-// 1. Load the timer clk ticks
-// 2. Enable AutoReload and Interrupt
-// 3. Clear PIT Timer Status bits
-//--------------------------------------------------------------------
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- unsigned long val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- unsigned int csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-//--------------------------------------------------------------------
-#endif // PROC_PPC
-//--------------------------------------------------------------------
-
-
-
-
-//--------------------------------------------------------------------
-// MicroBlaze Target - Timer related functions
-//--------------------------------------------------------------------
-#ifdef PROC_MICROBLAZE
-
-//--------------------------------------------------------------------
-// Disable the Timer during Call-Graph Data collection
-//
-//--------------------------------------------------------------------
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-
-
-//--------------------------------------------------------------------
-// Enable the Timer after Call-Graph Data collection
-//
-//--------------------------------------------------------------------
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-
-
-//--------------------------------------------------------------------
-// Send Ack to Timer Interrupt
-//
-//--------------------------------------------------------------------
-#define timer_ack() \
- { \
- unsigned int csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-
-//--------------------------------------------------------------------
-#endif // PROC_MICROBLAZE
-//--------------------------------------------------------------------
-
-//--------------------------------------------------------------------
-// Cortex A9 Target - Timer related functions
-//--------------------------------------------------------------------
-#ifdef PROC_CORTEXA9
-
-//--------------------------------------------------------------------
-// Disable the Timer during Call-Graph Data collection
-//
-//--------------------------------------------------------------------
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-} \
-
-
-//--------------------------------------------------------------------
-// Enable the Timer after Call-Graph Data collection
-//
-//--------------------------------------------------------------------
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-} \
-
-
-//--------------------------------------------------------------------
-// Send Ack to Timer Interrupt
-//
-//--------------------------------------------------------------------
-#define timer_ack() \
-{ \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
- XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-//--------------------------------------------------------------------
-#endif // PROC_CORTEXA9
-//--------------------------------------------------------------------
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+++ /dev/null
-// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
- .globl dummy_f
-
-#ifdef PROC_MICROBLAZE
- .text
- .align 2
- .ent dummy_f
-
-dummy_f:
- nop
-
- .end dummy_f
-#endif
-
-#ifdef PROC_PPC
- .section .text
- .align 2
- .type dummy_f@function
-
-dummy_f:
- b dummy_f
-
-#endif
-
-#ifdef PROC_CORTEXA9
- .section .text
- .align 2
- .type dummy_f, %function
-
-dummy_f:
- b dummy_f
-
-#endif
+++ /dev/null
-// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+++ /dev/null
-// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef _PROFILE_H
-#define _PROFILE_H 1
-
-#include <stdio.h>
-#include "profile_config.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void _system_init( void ) ;
-void _system_clean( void ) ;
-void mcount(unsigned long frompc, unsigned long selfpc);
-void profile_intr_handler( void ) ;
-
-
-
-/****************************************************************************
- * Profiling on hardware - Hash table maintained on hardware and data sent
- * to xmd for gmon.out generation.
- ****************************************************************************/
-/*
- * histogram counters are unsigned shorts (according to the kernel).
- */
-#define HISTCOUNTER unsigned short
-
-struct tostruct {
- unsigned long selfpc;
- long count;
- short link;
- unsigned short pad;
-};
-
-struct fromstruct {
- unsigned long frompc ;
- short link ;
- unsigned short pad ;
-} ;
-
-/*
- * general rounding functions.
- */
-#define ROUNDDOWN(x,y) (((x)/(y))*(y))
-#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
-
-/*
- * The profiling data structures are housed in this structure.
- */
-struct gmonparam {
- long int state;
-
- // Histogram Information
- unsigned short *kcount; /* No. of bins in histogram */
- unsigned long kcountsize; /* Histogram samples */
-
- // Call-graph Information
- struct fromstruct *froms;
- unsigned long fromssize;
- struct tostruct *tos;
- unsigned long tossize;
-
- // Initialization I/Ps
- unsigned long lowpc;
- unsigned long highpc;
- unsigned long textsize;
- //unsigned long cg_froms;
- //unsigned long cg_tos;
-};
-extern struct gmonparam *_gmonparam;
-extern int n_gmon_sections;
-
-/*
- * Possible states of profiling.
- */
-#define GMON_PROF_ON 0
-#define GMON_PROF_BUSY 1
-#define GMON_PROF_ERROR 2
-#define GMON_PROF_OFF 3
-
-/*
- * Sysctl definitions for extracting profiling information from the kernel.
- */
-#define GPROF_STATE 0 /* int: profiling enabling variable */
-#define GPROF_COUNT 1 /* struct: profile tick count buffer */
-#define GPROF_FROMS 2 /* struct: from location hash bucket */
-#define GPROF_TOS 3 /* struct: destination/count structure */
-#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _PROFILE_H */
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
-// $Id: profile_cg.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-/*
- * The mcount fucntion is excluded from the library, if the user defines
- * PROFILE_NO_GRAPH.
- */
-#ifndef PROFILE_NO_GRAPH
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-extern struct gmonparam *_gmonparam;
-
-#ifdef PROFILE_NO_FUNCPTR
-int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc )
-{
- int index = 0 ;
-
- while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
- index++ ;
- }
- if( index == cgtable_size )
- return -1 ;
- else
- return index ;
-}
-#else
-int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc )
-{
- int index = 0 ;
-
- while( (index < fromssize) && (froms[index].frompc != frompc) ){
- index++ ;
- }
- if( index == fromssize )
- return -1 ;
- else
- return index ;
-}
-#endif /* PROFILE_NO_FUNCPTR */
-
-
-void mcount( unsigned long frompc, unsigned long selfpc )
-{
- register struct gmonparam *p = NULL;
- register long toindex, fromindex;
- int j;
-
- disable_timer();
-
- //print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n");
- // check that frompcindex is a reasonable pc value.
- // for example: signal catchers get called from the stack,
- // not from text space. too bad.
- //
- for(j = 0; j < n_gmon_sections; j++ ){
- if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
- p = &_gmonparam[j];
- break;
- }
- }
- if( j == n_gmon_sections )
- goto done;
-
-#ifdef PROFILE_NO_FUNCPTR
- fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
- if( fromindex == -1 ) {
- fromindex = p->cgtable_size ;
- p->cgtable_size++ ;
- p->cgtable[fromindex].frompc = frompc ;
- p->cgtable[fromindex].selfpc = selfpc ;
- p->cgtable[fromindex].count = 1 ;
- goto done ;
- }
- p->cgtable[fromindex].count++ ;
-#else
- fromindex = searchpc( p->froms, p->fromssize, frompc ) ;
- if( fromindex == -1 ) {
- fromindex = p->fromssize ;
- p->fromssize++ ;
- //if( fromindex >= N_FROMS ) {
- //print("Error : From PC table overflow\r\n") ;
- //goto overflow ;
- //}
- p->froms[fromindex].frompc = frompc ;
- p->froms[fromindex].link = -1 ;
- }else {
- toindex = p->froms[fromindex].link ;
- while(toindex != -1) {
- toindex = (p->tossize - toindex)-1 ;
- if( p->tos[toindex].selfpc == selfpc ) {
- p->tos[toindex].count++ ;
- goto done ;
- }
- toindex = p->tos[toindex].link ;
- }
- }
-
- //if( toindex == -1 ) {
- p->tos-- ;
- p->tossize++ ;
- //if( toindex >= N_TOS ) {
- //print("Error : To PC table overflow\r\n") ;
- //goto overflow ;
- //}
- p->tos[0].selfpc = selfpc ;
- p->tos[0].count = 1 ;
- p->tos[0].link = p->froms[fromindex].link ;
- p->froms[fromindex].link = p->tossize-1 ;
-#endif
-
- done:
- p->state = GMON_PROF_ON;
- goto enable_timer ;
- //overflow:
- p->state = GMON_PROF_ERROR;
- enable_timer:
- enable_timer();
- return ;
-}
-
-
-#endif /* PROFILE_NO_GRAPH */
-
+++ /dev/null
-// $Id: profile_config.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-
-#ifndef _PROFILE_CONFIG_H
-#define _PROFILE_CONFIG_H
-
-#define BINSIZE 4
-#define SAMPLE_FREQ_HZ 100000
-#define TIMER_CLK_TICKS 1000
-
-#define PROFILE_NO_FUNCPTR_FLAG 0
-
-#define PROFILE_TIMER_BASEADDR 0x00608000
-#define PROFILE_TIMER_INTR_ID 0
-
-#define TIMER_CONNECT_INTC
-
-#endif
+++ /dev/null
-// $Id: profile_hist.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef PROC_PPC
-#include "xpseudo_asm.h"
-#define SPR_SRR0 0x01A
-#endif
-
-#include "xil_types.h"
-
-extern int binsize ;
-u32 prof_pc ;
-
-void profile_intr_handler( void )
-{
-
- int j;
-
-#ifdef PROC_MICROBLAZE
- asm( "swi r14, r0, prof_pc" ) ;
-#elif defined PROC_PPC
- prof_pc = mfspr(SPR_SRR0);
-#else
- // for cortexa9, lr is saved in asm interrupt handler
-#endif
- //print("PC: "); putnum(prof_pc); print("\r\n");
- for(j = 0; j < n_gmon_sections; j++ ){
- if((prof_pc >= _gmonparam[j].lowpc) && (prof_pc < _gmonparam[j].highpc)) {
- _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/(4 * binsize)]++;
- break;
- }
- }
- // Ack the Timer Interrupt
- timer_ack();
-}
-
+++ /dev/null
-// $Id: profile_mcount_arm.S,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
-
-.globl __gnu_mcount_nc
-.type __gnu_mcount_nc, %function
-
-__gnu_mcount_nc:
- push {r0, r1, r2, r3, lr}
- subs r1, lr, #0 /* callee - current lr */
- ldr r0, [sp, #20] /* caller - at the top of the stack */
- bl mcount /* when __gnu_mcount_nc is called */
- pop {r0, r1, r2, r3, ip, lr}
- bx ip
-
- .end __gnu_mcount_nc
+++ /dev/null
-// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
- .globl _mcount
- .text
- .align 2
- .ent _mcount
-
- #ifndef PROFILE_NO_GRAPH
-
-_mcount:
- addi r1, r1, -48
- swi r11, r1, 44
- swi r12, r1, 40
- swi r5, r1, 36
- swi r6, r1, 32
- swi r7, r1, 28
- swi r8, r1, 24
- swi r9, r1, 20
- swi r10, r1, 16
- swi r15, r1, 12
- add r6, r0, r15
- brlid r15, mcount
- lwi r5, r1, 48
-
- lwi r11, r1, 44
- lwi r12, r1, 40
- lwi r5, r1, 36
- lwi r6, r1, 32
- lwi r7, r1, 28
- lwi r8, r1, 24
- lwi r9, r1, 20
- lwi r10, r1, 16
- lwi r15, r1, 12
- rtsd r15, 4
- addi r1, r1, 48
-
- #endif /* PROFILE_NO_GRAPH */
-
- .end _mcount
+++ /dev/null
-// $Id: profile_mcount_ppc.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
- .globl _mcount
-
- #define _MCOUNT_STACK_FRAME 48
- .section .text
- .align 2
- .type _mcount@function
-
-
-_mcount:
- stwu 1, -_MCOUNT_STACK_FRAME(1)
- stw 3, 8(1)
- stw 4, 12(1)
- stw 5, 16(1)
- stw 6, 20(1)
- stw 7, 24(1)
- stw 8, 28(1)
- stw 9, 32(1)
- stw 10, 36(1)
- stw 11, 40(1)
- stw 12, 44(1)
- mflr 4
- stw 4, (_MCOUNT_STACK_FRAME+4)(1)
- lwz 3, (_MCOUNT_STACK_FRAME)(1)
- lwz 3, 4(3)
- bl mcount
- lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
- mtlr 4
- lwz 12, 44(1)
- lwz 11, 40(1)
- lwz 10, 36(1)
- lwz 9, 32(1)
- lwz 8, 28(1)
- lwz 7, 24(1)
- lwz 6, 20(1)
- lwz 5, 16(1)
- lwz 4, 12(1)
- lwz 3, 8(1)
- addi 1,1, _MCOUNT_STACK_FRAME
- blr
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file pvr.c
-*
-* This header file contains defines for structures used by the microblaze
-* PVR routines
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "pvr.h"
-#include <string.h>
-
-/* Definitions */
-int microblaze_get_pvr (pvr_t *pvr)
-{
- if (!pvr)
- return -1;
-
- bzero ((void*)pvr, sizeof (pvr_t));
-
-#ifdef MICROBLAZE_PVR_NONE
- return -1;
-#else
- getpvr (0, pvr->pvr[0]);
-#endif /* MICROBLAZE_PVR_NONE */
-
-#ifdef MICROBLAZE_PVR_FULL
- getpvr (1, pvr->pvr[1]);
- getpvr (2, pvr->pvr[2]);
- getpvr (3, pvr->pvr[3]);
-
- getpvr (4, pvr->pvr[4]);
- getpvr (5, pvr->pvr[5]);
- getpvr (6, pvr->pvr[6]);
- getpvr (7, pvr->pvr[7]);
-
- getpvr (8, pvr->pvr[8]);
- getpvr (9, pvr->pvr[9]);
- getpvr (10, pvr->pvr[10]);
- getpvr (11, pvr->pvr[11]);
-
-/* getpvr (12, pvr->pvr[12]); */
-/* getpvr (13, pvr->pvr[13]); */
-/* getpvr (14, pvr->pvr[14]); */
-/* getpvr (15, pvr->pvr[15]); */
-
-#endif /* MICROBLAZE_PVR_FULL */
-
- return 0;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file pvr.h
-*
-* This header file contains defines for structures used by the microblaze
-* PVR routines
-*
-******************************************************************************/
-
-#ifndef _PVR_H
-#define _PVR_H
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "mb_interface.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Defs */
-typedef struct pvr_s {
-#ifdef MICROBLAZE_PVR_FULL
- unsigned int pvr[16];
-#else
- unsigned int pvr[1];
-#endif
-} pvr_t;
-
-
-#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
-
-/* Basic PVR mask */
-#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000
-#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000
-#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000
-#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000
-#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000
-#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000
-#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000
-#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000
-#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000
-#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000
-#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000
-#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000
-#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000
-#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00
-#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF
-
-/* User 2 PVR mask */
-#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF
-
-/* Configuration PVR masks */
-#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000
-#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000
-#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000
-#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000
-#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000
-#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000
-#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
-#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
-#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000
-#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000
-#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
-#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000
-#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000
-#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000
-#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000
-#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000
-#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000
-#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800
-#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200
-#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400
-#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040
-#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020
-#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010
-#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008
-#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004
-#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100
-#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080
-#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002
-#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001
-#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000
-
-/* Debug and exception PVR masks */
-#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000
-#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
-#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
-#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
-#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380
-#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007
-
-/* ICache config PVR masks */
-#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000
-#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
-#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
-#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
-#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
-#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000
-#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000
-#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00
-#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300
-#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
-#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040
-
-/* DCache config PVR masks */
-#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000
-#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
-#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
-#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
-#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
-#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000
-#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000
-#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000
-#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00
-#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
-#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040
-
-/* ICache base address PVR mask */
-#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
-
-/* ICache high address PVR mask */
-#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
-
-/* DCache base address PVR mask */
-#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
-
-/* DCache high address PVR mask */
-#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
-
-/* Target family PVR mask */
-#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000
-
-/* MSR Reset value PVR mask */
-#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF
-
-/* MMU value PVR mask */
-#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000
-#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000
-#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000
-#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000
-#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000
-#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000
-
-/* PVR access macros */
-#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
-#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
-#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
-#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
-#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
-#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
-#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
-#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
-#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
-#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
-#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
-#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
-#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
-#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
-
-#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
-
-#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
-#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
-#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
-#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
-#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
-#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
-#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
-#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
-#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
-#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
-#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
-#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
-#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
-#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
-#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
-#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
-#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
-#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
-
-#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
-#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
-#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
-#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
-#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
-#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
-
-#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
-#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
-#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
-#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
-#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
-#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
-#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
-#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
-#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
-#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
-
-#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
-#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
-#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
-#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
-#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
-#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
-#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
-#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
-#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
-#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
-
-#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
-#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
-
-#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
-#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
-
-#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
-
-#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
-
-#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
-#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
-#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
-#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
-#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
-#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
-
-/* Protos */
-int microblaze_get_pvr (pvr_t *pvr);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _PVR_H */
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef unsigned char Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef unsigned short Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef unsigned long Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include <linux/types.h>
-#endif
-
-#ifndef TRUE
-# define TRUE 1
-#endif
-
-#ifndef FALSE
-# define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-
-#endif /* end of protection macro */
+++ /dev/null
-#ifndef XDEBUG
-#define XDEBUG
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */
-#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */
-#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */
-
-#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */
-#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */
-#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */
-#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */
-
-#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */
-#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */
-
-#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */
-#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */
-
-#define xdbg_current_types (XDBG_DEBUG_ERROR)
-
-#define xdbg_stmnt(x) x
-
-/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
- * macros that accept variable number of arguments
- */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
-#else /* ANSI Syntax */
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-#endif
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-/* See VxWorks comments above */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...)
-#else /* ANSI Syntax */
-#define xdbg_printf(...)
-#endif
-
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#endif /* XDEBUG */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-* </pre>
-*
-*
-******************************************************************************/
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include <string.h>
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implemention MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (int) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef int XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- * <br><br>
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((int)(Addr), (int)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.c
-*
-* This file contains basic assert related functions for Xilinx software IP.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 Initial release
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-unsigned int Xil_AssertStatus;
-
-/**
- * This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-int Xil_AssertWait = TRUE;
-
-/* The callback function to be invoked when an assert is taken */
-static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Implement assert. Currently, it calls a user-defined callback function
-* if one has been set. Then, it potentially enters an infinite loop depending
-* on the value of the Xil_AssertWait variable.
-*
-* @param file is the name of the filename of the source
-* @param line is the linenumber within File
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Assert(const char *File, int Line)
-{
- /* if the callback has been set then invoke it */
- if (Xil_AssertCallbackRoutine != 0) {
- (*Xil_AssertCallbackRoutine)(File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (Xil_AssertWait) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Set up a callback function to be invoked when an assert occurs. If there
-* was already a callback installed, then it is replaced.
-*
-* @param routine is the callback to be invoked when an assert is taken
-*
-* @return None.
-*
-* @note This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void Xil_AssertSetCallback(Xil_AssertCallback Routine)
-{
- Xil_AssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* Null handler function. This follows the XInterruptHandler signature for
-* interrupt handlers. It can be used to assign a null handler (a stub) to an
-* interrupt controller vector table.
-*
-* @param NullParameter is an arbitrary void pointer and not used.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XNullHandler(void *NullParameter)
-{
- (void) NullParameter;
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* This file contains assert related functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0
-#define XIL_ASSERT_OCCURRED 1
-#define XNULL NULL
-
-extern unsigned int Xil_AssertStatus;
-extern void Xil_Assert(const char *, int);
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char *File, int Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the Xil_AssertWait boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
-* so that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* This contains implementation of cache related driver functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 3.10 asa 05/04/13 This version of MicroBlaze BSP adds support for system
-* cache/L2 cache. Existing APIs in this file are modified
-* to add support for L2 cache.
-* These changes are done for implementing PR #697214.
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xil_cache.h"
-
-
-/****************************************************************************/
-/**
-*
-* Disable the data cache.
-*
-* @param None
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
- Xil_DCacheFlush();
- Xil_DCacheInvalidate();
- Xil_L1DCacheDisable();
-}
-
-/****************************************************************************/
-/**
-*
-* Disable the instruction cache.
-*
-* @param None
-*
-* @return None.
-*
-* @note
-*
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
- Xil_ICacheInvalidate();
- Xil_L1ICacheDisable();
-}
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* This header file contains cache related driver functions (or macros)
-* that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The functions in this header file can be used across all Xilinx supported
-* processors.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
-* the correct cache flush routines are used based on
-* whether the write-back or write-through caches are
-* used (cr #630532).
-* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
-* cache/L2 cache. The existing/old APIs/macros in this
-* file are renamed to imply that they deal with L1 cache.
-* New macros/APIs are added to address similar features for
-* L2 cache. Users can include this file in their application
-* to use the various cache related APIs. These changes are
-* done for implementing PR #697214.
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#if defined XENV_VXWORKS
-/* VxWorks environment */
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#else
-/* standalone environment */
-
-#include "mb_interface.h"
-#include "xil_types.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/****************************************************************************/
-/**
-*
-* Invalidate the entire L1 data cache. If the cacheline is modified (dirty),
-* the modified contents are lost.
-*
-* @param None.
-*
-* @return None.
-*
-* @note
-*
-* Processor must be in real mode.
-****************************************************************************/
-#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
-
-/****************************************************************************/
-/**
-*
-* Invalidate the entire L2 data cache. If the cacheline is modified (dirty),
-* the modified contents are lost.
-*
-* @param None.
-*
-* @return None.
-*
-* @note
-*
-* Processor must be in real mode.
-****************************************************************************/
-#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
-
-/****************************************************************************/
-/**
-*
-* Invalidate the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the L1 data cache,
-* the cacheline containing that byte is invalidated. If the cacheline
-* is modified (dirty), the modified contents are lost.
-*
-* @param Addr is address of ragne to be invalidated.
-* @param Len is the length in bytes to be invalidated.
-*
-* @return None.
-*
-* @note
-*
-* Processor must be in real mode.
-****************************************************************************/
-#define Xil_L1DCacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_dcache_range(Addr, Len)
-
-/****************************************************************************/
-/**
-*
-* Invalidate the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the L1 data cache,
-* the cacheline containing that byte is invalidated. If the cacheline
-* is modified (dirty), the modified contents are lost.
-*
-* @param Addr is address of ragne to be invalidated.
-* @param Len is the length in bytes to be invalidated.
-*
-* @return None.
-*
-* @note
-*
-* Processor must be in real mode.
-****************************************************************************/
-#define Xil_L2CacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_cache_ext_range(Addr, Len)
-
-/****************************************************************************/
-/**
-* Flush the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the data cache,
-* and is modified (dirty), the cacheline will be written to system memory.
-* The cacheline will also be invalidated.
-*
-* @param Addr is the starting address of the range to be flushed.
-* @param Len is the length in byte to be flushed.
-*
-* @return None.
-*
-****************************************************************************/
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define Xil_L1DCacheFlushRange(Addr, Len) \
- microblaze_flush_dcache_range(Addr, Len)
-#else
-# define Xil_L1DCacheFlushRange(Addr, Len) \
- microblaze_invalidate_dcache_range(Addr, Len)
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
-
-/****************************************************************************/
-/**
-* Flush the L2 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the data cache,
-* and is modified (dirty), the cacheline will be written to system memory.
-* The cacheline will also be invalidated.
-*
-* @param Addr is the starting address of the range to be flushed.
-* @param Len is the length in byte to be flushed.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L2CacheFlushRange(Addr, Len) \
- microblaze_flush_cache_ext_range(Addr, Len)
-
-/****************************************************************************/
-/**
-* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be
-* written to system memory. The entire data cache will be invalidated.
-*
-* @return None.
-*
-* @note
-*
-****************************************************************************/
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define Xil_L1DCacheFlush() microblaze_flush_dcache()
-#else
-# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
-
-/****************************************************************************/
-/**
-* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be
-* written to system memory. The entire data cache will be invalidated.
-*
-* @return None.
-*
-* @note
-*
-****************************************************************************/
-#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
-
-/****************************************************************************/
-/**
-*
-* Invalidate the instruction cache for the given address range.
-*
-* @param Addr is address of ragne to be invalidated.
-* @param Len is the length in bytes to be invalidated.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L1ICacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_icache_range(Addr, Len)
-
-/****************************************************************************/
-/**
-*
-* Invalidate the entire instruction cache.
-*
-* @param None
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L1ICacheInvalidate() \
- microblaze_invalidate_icache()
-
-
-/****************************************************************************/
-/**
-*
-* Enable the L1 data cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1DCacheEnable() \
- microblaze_enable_dcache()
-
-/****************************************************************************/
-/**
-*
-* Disable the L1 data cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1DCacheDisable() \
- microblaze_disable_dcache()
-
-/****************************************************************************/
-/**
-*
-* Enable the instruction cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1ICacheEnable() \
- microblaze_enable_icache()
-
-/****************************************************************************/
-/**
-*
-* Disable the L1 Instruction cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1ICacheDisable() \
- microblaze_disable_icache()
-
-/****************************************************************************/
-/**
-*
-* Enable the data cache.
-*
-* @param None
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheEnable() Xil_L1DCacheEnable()
-
-/****************************************************************************/
-/**
-*
-* Enable the instruction cache.
-*
-* @param None
-*
-* @return None.
-*
-* @note
-*
-*
-****************************************************************************/
-#define Xil_ICacheEnable() Xil_L1ICacheEnable()
-
-/****************************************************************************
-*
-* Invalidate the entire Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#define Xil_DCacheInvalidate() \
- Xil_L2CacheInvalidate(); \
- Xil_L1DCacheInvalidate();
-
-
-/****************************************************************************
-*
-* Invalidate the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the Data cache,
-* the cacheline containing that byte is invalidated. If the cacheline
-* is modified (dirty), the modified contents are lost and are NOT
-* written to system memory before the line is invalidated.
-*
-* @param Start address of ragne to be invalidated.
-* @param Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- Xil_L2CacheInvalidateRange(Addr, Len); \
- Xil_L1DCacheInvalidateRange(Addr, Len);
-
-
-/****************************************************************************
-*
-* Flush the entire Data cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#define Xil_DCacheFlush() \
- Xil_L2CacheFlush(); \
- Xil_L1DCacheFlush();
-
-/****************************************************************************
-* Flush the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the Data cache,
-* the cacheline containing that byte is invalidated. If the cacheline
-* is modified (dirty), the written to system memory first before the
-* before the line is invalidated.
-*
-* @param Start address of range to be flushed.
-* @param Length of range to be flushed in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#define Xil_DCacheFlushRange(Addr, Len) \
- Xil_L2CacheFlushRange(Addr, Len); \
- Xil_L1DCacheFlushRange(Addr, Len);
-
-
-/****************************************************************************
-*
-* Invalidate the entire instruction cache.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#define Xil_ICacheInvalidate() \
- Xil_L2CacheInvalidate(); \
- Xil_L1ICacheInvalidate();
-
-
-/****************************************************************************
-*
-* Invalidate the instruction cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the Data cache,
-* the cacheline containing that byte is invalidated. If the cacheline
-* is modified (dirty), the modified contents are lost and are NOT
-* written to system memory before the line is invalidated.
-*
-* @param Start address of ragne to be invalidated.
-* @param Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- Xil_L2CacheInvalidateRange(Addr, Len); \
- Xil_L1ICacheInvalidateRange(Addr, Len);
-
-void Xil_DCacheDisable(void);
-void Xil_ICacheDisable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
- cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.c
-*
-* This file contains implementation of exception related driver functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xil_types.h"
-#include "xil_exception.h"
-
-#include "microblaze_exceptions_g.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern void microblaze_enable_exceptions(void);
-extern void microblaze_disable_exceptions(void);
-extern void microblaze_enable_interrupts(void);
-extern void microblaze_disable_interrupts(void);
-
-/**
-* Currently HAL is an augmented part of standalone BSP, so the old definition
-* of MB_ExceptionVectorTableEntry is used here.
-*/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *CallBackRef;
-} MB_ExceptionVectorTableEntry;
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *CallBackRef;
-} MB_InterruptVectorTableEntry;
-
-#ifdef __cplusplus
-}
-#endif
-
-
-/************************** Variable Definitions *****************************/
-extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
-extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
-
-/**
- *
- * This function is a stub handler that is the default handler that gets called
- * if the application has not setup a handler for a specific exception. The
- * function interface has to match the interface specified for a handler even
- * though none of the arguments are used.
- *
- * @param Data is unused by this function.
- *
- * @return
- *
- * None.
- *
- * @note
- *
- * None.
- *
- *****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-}
-
-/****************************************************************************/
-/**
-*
-* Initialize exception handling for the processor. The exception vector table
-* is setup with the stub handler for all exceptions.
-*
-* @param None.
-*
-* @return None.
-*
-* @note
-*
-* None.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- /*
- * there is no need to setup the exception table here
- */
-
-}
-
-/****************************************************************************/
-/**
-* Enable Exceptions.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_ExceptionEnable(void)
-{
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- microblaze_enable_exceptions();
-#endif
- microblaze_enable_interrupts();
-}
-
-/****************************************************************************/
-/**
-* Disable Exceptions.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_ExceptionDisable(void)
-{
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- microblaze_disable_exceptions();
-#endif
- microblaze_disable_interrupts();
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Id of the exception source and the
-* associated handler that is to run when the exception is recognized. The
-* argument provided in this call as the DataPtr is used as the argument
-* for the handler when it is called.
-*
-* @param Id contains the ID of the exception source and should
-* be XIL_EXCEPTION_INT or be in the range of 0 to XIL_EXCEPTION_LAST.
-* See xil_mach_exception.h for further information.
-* @param Handler to the handler for that exception.
-* @param Data is a reference to data that will be passed to the handler
-* when it gets called.
-*
-* @return None.
-*
-* @note
-*
-* None.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Id, Xil_ExceptionHandler Handler,
- void *Data)
-{
- if (Id == XIL_EXCEPTION_ID_INT) {
- MB_InterruptVectorTable.Handler = Handler;
- MB_InterruptVectorTable.CallBackRef = Data;
- }
- else {
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- MB_ExceptionVectorTable[Id].Handler = Handler;
- MB_ExceptionVectorTable[Id].CallBackRef = Data;
-#endif
- }
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Removes the handler for a specific exception Id. The stub handler is then
-* registered for this exception Id.
-*
-* @param Id contains the ID of the exception source and should
-* be XIL_EXCEPTION_INT or in the range of 0 to XIL_EXCEPTION_LAST.
-* See xexception_l.h for further information.
-*
-* @return None.
-*
-* @note
-*
-* None.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Id)
-{
- if (Id == XIL_EXCEPTION_ID_INT) {
- MB_InterruptVectorTable.Handler = Xil_ExceptionNullHandler;
- MB_InterruptVectorTable.CallBackRef = NULL;
- }
- else {
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- MB_ExceptionVectorTable[Id].Handler =
- Xil_ExceptionNullHandler;
- MB_ExceptionVectorTable[Id].CallBackRef = NULL;
-#endif
- }
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains exception related driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/*
- * These constants are specific to Microblaze processor.
- */
-
-#define XIL_EXCEPTION_ID_FIRST 0
-#define XIL_EXCEPTION_ID_FSL 0
-#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1
-#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2
-#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3
-#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3
-#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4
-#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4
-#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5
-#define XIL_EXCEPTION_ID_FPU 6
-#define XIL_EXCEPTION_ID_STACK_VIOLATION 7
-#define XIL_EXCEPTION_ID_MMU 7
-#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
- */
-#define XIL_EXCEPTION_ID_INT 16 /**
- * exception ID for interrupt
- */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *Data);
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Id);
-
-extern void Xil_ExceptionInit(void);
-extern void Xil_ExceptionEnable(void);
-extern void Xil_ExceptionDisable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#endif
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.c
-*
-* Contains I/O functions for memory-mapped architectures. These functions
-* encapsulate generic CPU I/O requirements.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a hbm 07/28/09 Initial release
-* 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s
-*
-* </pre>
-*
-* @note
-*
-* This file may contain architecture-dependent code.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-
-/*****************************************************************************/
-/**
-*
-* Perform a 16-bit endian converion.
-*
-* @param Data contains the value to be converted.
-*
-* @return converted value.
-*
-* @note None.
-*
-******************************************************************************/
-u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00) >> 8) | ((Data & 0x00FF) << 8));
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a 32-bit endian converion.
-*
-* @param Data contains the value to be converted.
-*
-* @return converted value.
-*
-* @note None.
-*
-******************************************************************************/
-u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFF);
- HiWord = (u16) ((Data & 0xFFFF0000) >> 16);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
- HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
-
- /* swap the half words before returning the value */
-
- return (u32) ((LoWord << 16) | HiWord);
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a little-endian input operation for a 16-bit memory location
-* by reading from the specified address and returning the byte-swapped value
-* read from that address.
-*
-* @param Addr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address with the
-* proper endianness. The return value has the same endianness
-* as that of the processor, i.e. if the processor is big-engian,
-* the return value is the byte-swapped value read from the
-* address.
-*
-*
-* @note None.
-*
-******************************************************************************/
-#ifndef __LITTLE_ENDIAN__
-u16 Xil_In16LE(u32 Addr)
-#else
-u16 Xil_In16BE(u32 Addr)
-#endif
-{
- u16 Value;
-
- /* get the data then swap it */
- Value = Xil_In16(Addr);
-
- return Xil_EndianSwap16(Value);
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a little-endian input operation for a 32-bit memory location
-* by reading from the specified address and returning the byte-swapped value
-* read from that address.
-*
-* @param Addr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address with the
-* proper endianness. The return value has the same endianness
-* as that of the processor, i.e. if the processor is big-engian,
-* the return value is the byte-swapped value read from the
-* address.
-*
-* @note None.
-*
-******************************************************************************/
-#ifndef __LITTLE_ENDIAN__
-u32 Xil_In32LE(u32 Addr)
-#else
-u32 Xil_In32BE(u32 Addr)
-#endif
-{
- u32 InValue;
-
- /* get the data then swap it */
- InValue = Xil_In32(Addr);
- return Xil_EndianSwap32(InValue);
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a little-endian output operation for a 16-bit memory location by
-* writing the specified value to the the specified address. The value is
-* byte-swapped before being written.
-*
-* @param Addr contains the address to perform the output operation at.
-* @param Value contains the value to be output at the specified address.
-* The value has the same endianness as that of the processor.
-* If the processor is big-endian, the byte-swapped value is
-* written to the address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#ifndef __LITTLE_ENDIAN__
-void Xil_Out16LE(u32 Addr, u16 Value)
-#else
-void Xil_Out16BE(u32 Addr, u16 Value)
-#endif
-{
- u16 OutValue;
-
- /* swap the data then output it */
- OutValue = Xil_EndianSwap16(Value);
-
- Xil_Out16(Addr, OutValue);
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a little-endian output operation for a 32-bit memory location
-* by writing the specified value to the the specified address. The value is
-* byte-swapped before being written.
-*
-* @param Addr contains the address at which the output operation at.
-* @param Value contains the value to be output at the specified address.
-* The value has the same endianness as that of the processor.
-* If the processor is big-endian, the byte-swapped value is
-* written to the address.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#ifndef __LITTLE_ENDIAN__
-void Xil_Out32LE(u32 Addr, u32 Value)
-#else
-void Xil_Out32BE(u32 Addr, u32 Value)
-#endif
-{
- u32 OutValue;
-
- /* swap the data then output it */
- OutValue = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, OutValue);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* This file contains the interface for the general IO component, which
-* encapsulates the Input/Output functions for processors that do not
-* require any special I/O handling.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a hbm 07/28/09 Initial release
-* 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s
-* 3.03a sdm 08/18/11 Added INST_SYNC and DATA_SYNC macros.
-* 3.07a asa 08/31/12 Added xil_printf.h include
-*
-* </pre>
-*
-* @note
-*
-* This file may contain architecture-dependent items.
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "mb_interface.h"
-#include "xil_printf.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#if defined __GNUC__
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-#else
-# define INST_SYNC
-# define DATA_SYNC
-#endif /* __GNUC__ */
-
-/*
- * The following macros allow optimized I/O operations for memory mapped I/O.
- * It should be noted that macros cannot be used if synchronization of the I/O
- * operation is needed as it will likely break some code.
- */
-
-/*****************************************************************************/
-/**
-*
-* Perform an input operation for an 8-bit memory location by reading from the
-* specified address and returning the value read from that address.
-*
-* @param Addr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_In8(Addr) (*(volatile u8 *)(Addr))
-
-/*****************************************************************************/
-/**
-*
-* Perform an input operation for a 16-bit memory location by reading from the
-* specified address and returning the value read from that address.
-*
-* @param Addr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_In16(Addr) (*(volatile u16 *)(Addr))
-
-/*****************************************************************************/
-/**
-*
-* Perform an input operation for a 32-bit memory location by reading from the
-* specified address and returning the value read from that address.
-*
-* @param Addr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_In32(Addr) (*(volatile u32 *)(Addr))
-
-
-/*****************************************************************************/
-/**
-*
-* Perform an output operation for an 8-bit memory location by writing the
-* specified value to the specified address.
-*
-* @param Addr contains the address to perform the output operation at.
-* @param value contains the value to be output at the specified address.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Out8(Addr, Value) \
- (*(volatile u8 *)((Addr)) = (Value))
-
-/*****************************************************************************/
-/**
-*
-* Perform an output operation for a 16-bit memory location by writing the
-* specified value to the specified address.
-*
-* @param Addr contains the address to perform the output operation at.
-* @param value contains the value to be output at the specified address.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Out16(Addr, Value) \
- (*(volatile u16 *)((Addr)) = (Value))
-
-/*****************************************************************************/
-/**
-*
-* Perform an output operation for a 32-bit memory location by writing the
-* specified value to the specified address.
-*
-* @param addr contains the address to perform the output operation at.
-* @param value contains the value to be output at the specified address.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Out32(Addr, Value) \
- (*(volatile u32 *)((Addr)) = (Value))
-
-
-extern u16 Xil_EndianSwap16(u16 Data);
-extern u32 Xil_EndianSwap32(u32 Data);
-
-#ifndef __LITTLE_ENDIAN__
-extern u16 Xil_In16LE(u32 Addr);
-extern u32 Xil_In32LE(u32 Addr);
-extern void Xil_Out16LE(u32 Addr, u16 Value);
-extern void Xil_Out32LE(u32 Addr, u32 Value);
-
-/**
-*
-* Perform an big-endian input operation for a 16-bit memory location
-* by reading from the specified address and returning the value read from
-* that address.
-*
-* @param addr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address with the
-* proper endianness. The return value has the same endianness
-* as that of the processor, i.e. if the processor is
-* little-engian, the return value is the byte-swapped value read
-* from the address.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_In16BE(Addr) Xil_In16(Addr)
-
-/**
-*
-* Perform a big-endian input operation for a 32-bit memory location
-* by reading from the specified address and returning the value read from
-* that address.
-*
-* @param Addr contains the address to perform the input operation at.
-*
-* @return The value read from the specified input address with the
-* proper endianness. The return value has the same endianness
-* as that of the processor, i.e. if the processor is
-* little-engian, the return value is the byte-swapped value read
-* from the address.
-*
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_In32BE(Addr) Xil_In32(Addr)
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian output operation for a 16-bit memory location
-* by writing the specified value to the specified address.
-*
-* @param Addr contains the address to perform the output operation at.
-* @param Value contains the value to be output at the specified address.
-* The value has the same endianness as that of the processor.
-* If the processor is little-endian, the byte-swapped value is
-* written to the address.
-*
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Out16BE(Addr, Value) Xil_Out16(Addr, Value)
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian output operation for a 32-bit memory location
-* by writing the specified value to the specified address.
-*
-* @param Addr contains the address to perform the output operation at.
-* @param Value contains the value to be output at the specified address.
-* The value has the same endianness as that of the processor.
-* If the processor is little-endian, the byte-swapped value is
-* written to the address.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Out32BE(Addr, Value) Xil_Out32(Addr, Value)
-
-#define Xil_Htonl(Data) (Data)
-#define Xil_Htons(Data) (Data)
-#define Xil_Ntohl(Data) (Data)
-#define Xil_Ntohs(Data) (Data)
-
-#else
-
-extern u16 Xil_In16BE(u32 Addr);
-extern u32 Xil_In32BE(u32 Addr);
-extern void Xil_Out16BE(u32 Addr, u16 Value);
-extern void Xil_Out32BE(u32 Addr, u32 Value);
-
-#define Xil_In16LE(Addr) Xil_In16(Addr)
-#define Xil_In32LE(Addr) Xil_In32(Addr)
-#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value)
-#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value)
-
-
-/*****************************************************************************/
-/**
-*
-* Convert a 32-bit number from host byte order to network byte order.
-*
-* @param Data the 32-bit number to be converted.
-*
-* @return The converted 32-bit number in network byte order.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Htonl(Data) Xil_EndianSwap32(Data)
-
-/*****************************************************************************/
-/**
-*
-* Convert a 16-bit number from host byte order to network byte order.
-*
-* @param Data the 16-bit number to be converted.
-*
-* @return The converted 16-bit number in network byte order.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Htons(Data) Xil_EndianSwap16(Data)
-
-/*****************************************************************************/
-/**
-*
-* Convert a 32-bit number from network byte order to host byte order.
-*
-* @param Value the 32-bit number to be converted.
-*
-* @return The converted 32-bit number in host byte order.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Ntohl(Data) Xil_EndianSwap32(Data)
-
-/*****************************************************************************/
-/**
-*
-* Convert a 16-bit number from network byte order to host byte order.
-*
-* @param Value the 16-bit number to be converted.
-*
-* @return The converted 16-bit number in host byte order.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_Ntohs(Data) Xil_EndianSwap16(Data)
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*********************************************************************/
-/**
- * @file xil_macroback.h
- *
- * This header file is meant to bring back the removed _m macros.
- * This header file must be included last.
- * The following macros are not defined here due to the driver change:
- * XGpio_mSetDataDirection
- * XGpio_mGetDataReg
- * XGpio_mSetDataReg
- * XIIC_RESET
- * XIIC_CLEAR_STATS
- * XSpi_mReset
- * XSysAce_mSetCfgAddr
- * XSysAce_mIsCfgDone
- * XTft_mSetPixel
- * XTft_mGetPixel
- * XWdtTb_mEnableWdt
- * XWdtTb_mDisbleWdt
- * XWdtTb_mRestartWdt
- * XWdtTb_mGetTimebaseReg
- * XWdtTb_mHasReset
- *
- * Please refer the corresonding driver document for replacement.
- *
- *********************************************************************/
-
-#ifndef XIL_MACROBACK_H
-#define XIL_MACROBACK_H
-
-/*********************************************************************/
-/**
- * Macros for Driver XCan
- *
- *********************************************************************/
-#ifndef XCan_mReadReg
-#define XCan_mReadReg XCan_ReadReg
-#endif
-
-#ifndef XCan_mWriteReg
-#define XCan_mWriteReg XCan_WriteReg
-#endif
-
-#ifndef XCan_mIsTxDone
-#define XCan_mIsTxDone XCan_IsTxDone
-#endif
-
-#ifndef XCan_mIsTxFifoFull
-#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
-#endif
-
-#ifndef XCan_mIsHighPriorityBufFull
-#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
-#endif
-
-#ifndef XCan_mIsRxEmpty
-#define XCan_mIsRxEmpty XCan_IsRxEmpty
-#endif
-
-#ifndef XCan_mIsAcceptFilterBusy
-#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
-#endif
-
-#ifndef XCan_mCreateIdValue
-#define XCan_mCreateIdValue XCan_CreateIdValue
-#endif
-
-#ifndef XCan_mCreateDlcValue
-#define XCan_mCreateDlcValue XCan_CreateDlcValue
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDmaCentral
- *
- *********************************************************************/
-#ifndef XDmaCentral_mWriteReg
-#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
-#endif
-
-#ifndef XDmaCentral_mReadReg
-#define XDmaCentral_mReadReg XDmaCentral_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsAdc
- *
- *********************************************************************/
-#ifndef XDsAdc_mWriteReg
-#define XDsAdc_mWriteReg XDsAdc_WriteReg
-#endif
-
-#ifndef XDsAdc_mReadReg
-#define XDsAdc_mReadReg XDsAdc_ReadReg
-#endif
-
-#ifndef XDsAdc_mIsEmpty
-#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
-#endif
-
-#ifndef XDsAdc_mSetFstmReg
-#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
-#endif
-
-#ifndef XDsAdc_mGetFstmReg
-#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
-#endif
-
-#ifndef XDsAdc_mEnableConversion
-#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
-#endif
-
-#ifndef XDsAdc_mDisableConversion
-#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
-#endif
-
-#ifndef XDsAdc_mGetFifoOccyReg
-#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XDsDac
- *
- *********************************************************************/
-#ifndef XDsDac_mWriteReg
-#define XDsDac_mWriteReg XDsDac_WriteReg
-#endif
-
-#ifndef XDsDac_mReadReg
-#define XDsDac_mReadReg XDsDac_ReadReg
-#endif
-
-#ifndef XDsDac_mIsEmpty
-#define XDsDac_mIsEmpty XDsDac_IsEmpty
-#endif
-
-#ifndef XDsDac_mFifoIsFull
-#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
-#endif
-
-#ifndef XDsDac_mGetVacancy
-#define XDsDac_mGetVacancy XDsDac_GetVacancy
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XEmacLite
- *
- *********************************************************************/
-#ifndef XEmacLite_mReadReg
-#define XEmacLite_mReadReg XEmacLite_ReadReg
-#endif
-
-#ifndef XEmacLite_mWriteReg
-#define XEmacLite_mWriteReg XEmacLite_WriteReg
-#endif
-
-#ifndef XEmacLite_mGetTxStatus
-#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
-#endif
-
-#ifndef XEmacLite_mSetTxStatus
-#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
-#endif
-
-#ifndef XEmacLite_mGetRxStatus
-#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
-#endif
-
-#ifndef XEmacLite_mSetRxStatus
-#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
-#endif
-
-#ifndef XEmacLite_mIsTxDone
-#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
-#endif
-
-#ifndef XEmacLite_mIsRxEmpty
-#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
-#endif
-
-#ifndef XEmacLite_mNextTransmitAddr
-#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
-#endif
-
-#ifndef XEmacLite_mNextReceiveAddr
-#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
-#endif
-
-#ifndef XEmacLite_mIsMdioConfigured
-#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
-#endif
-
-#ifndef XEmacLite_mIsLoopbackConfigured
-#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
-#endif
-
-#ifndef XEmacLite_mGetReceiveDataLength
-#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
-#endif
-
-#ifndef XEmacLite_mGetTxActive
-#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
-#endif
-
-#ifndef XEmacLite_mSetTxActive
-#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XGpio
- *
- *********************************************************************/
-#ifndef XGpio_mWriteReg
-#define XGpio_mWriteReg XGpio_WriteReg
-#endif
-
-#ifndef XGpio_mReadReg
-#define XGpio_mReadReg XGpio_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XHwIcap
- *
- *********************************************************************/
-#ifndef XHwIcap_mFifoWrite
-#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
-#endif
-
-#ifndef XHwIcap_mFifoRead
-#define XHwIcap_mFifoRead XHwIcap_FifoRead
-#endif
-
-#ifndef XHwIcap_mSetSizeReg
-#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
-#endif
-
-#ifndef XHwIcap_mGetControlReg
-#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
-#endif
-
-#ifndef XHwIcap_mStartConfig
-#define XHwIcap_mStartConfig XHwIcap_StartConfig
-#endif
-
-#ifndef XHwIcap_mStartReadBack
-#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
-#endif
-
-#ifndef XHwIcap_mGetStatusReg
-#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
-#endif
-
-#ifndef XHwIcap_mIsTransferDone
-#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
-#endif
-
-#ifndef XHwIcap_mIsDeviceBusy
-#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
-#endif
-
-#ifndef XHwIcap_mIntrGlobalEnable
-#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
-#endif
-
-#ifndef XHwIcap_mIntrGlobalDisable
-#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
-#endif
-
-#ifndef XHwIcap_mIntrGetStatus
-#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
-#endif
-
-#ifndef XHwIcap_mIntrDisable
-#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
-#endif
-
-#ifndef XHwIcap_mIntrEnable
-#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
-#endif
-
-#ifndef XHwIcap_mIntrGetEnabled
-#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
-#endif
-
-#ifndef XHwIcap_mIntrClear
-#define XHwIcap_mIntrClear XHwIcap_IntrClear
-#endif
-
-#ifndef XHwIcap_mGetWrFifoVacancy
-#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
-#endif
-
-#ifndef XHwIcap_mGetRdFifoOccupancy
-#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
-#endif
-
-#ifndef XHwIcap_mSliceX2Col
-#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
-#endif
-
-#ifndef XHwIcap_mSliceY2Row
-#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
-#endif
-
-#ifndef XHwIcap_mSliceXY2Slice
-#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
-#endif
-
-#ifndef XHwIcap_mReadReg
-#define XHwIcap_mReadReg XHwIcap_ReadReg
-#endif
-
-#ifndef XHwIcap_mWriteReg
-#define XHwIcap_mWriteReg XHwIcap_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIic
- *
- *********************************************************************/
-#ifndef XIic_mReadReg
-#define XIic_mReadReg XIic_ReadReg
-#endif
-
-#ifndef XIic_mWriteReg
-#define XIic_mWriteReg XIic_WriteReg
-#endif
-
-#ifndef XIic_mEnterCriticalRegion
-#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIic_mExitCriticalRegion
-#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_GINTR_DISABLE
-#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
-#endif
-
-#ifndef XIIC_GINTR_ENABLE
-#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
-#endif
-
-#ifndef XIIC_IS_GINTR_ENABLED
-#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
-#endif
-
-#ifndef XIIC_WRITE_IISR
-#define XIIC_WRITE_IISR XIic_WriteIisr
-#endif
-
-#ifndef XIIC_READ_IISR
-#define XIIC_READ_IISR XIic_ReadIisr
-#endif
-
-#ifndef XIIC_WRITE_IIER
-#define XIIC_WRITE_IIER XIic_WriteIier
-#endif
-
-#ifndef XIic_mClearIisr
-#define XIic_mClearIisr XIic_ClearIisr
-#endif
-
-#ifndef XIic_mSend7BitAddress
-#define XIic_mSend7BitAddress XIic_Send7BitAddress
-#endif
-
-#ifndef XIic_mDynSend7BitAddress
-#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
-#endif
-
-#ifndef XIic_mDynSendStartStopAddress
-#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
-#endif
-
-#ifndef XIic_mDynSendStop
-#define XIic_mDynSendStop XIic_DynSendStop
-#endif
-
-#ifndef XIic_mSend10BitAddrByte1
-#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
-#endif
-
-#ifndef XIic_mSend10BitAddrByte2
-#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
-#endif
-
-#ifndef XIic_mSend7BitAddr
-#define XIic_mSend7BitAddr XIic_Send7BitAddr
-#endif
-
-#ifndef XIic_mDisableIntr
-#define XIic_mDisableIntr XIic_DisableIntr
-#endif
-
-#ifndef XIic_mEnableIntr
-#define XIic_mEnableIntr XIic_EnableIntr
-#endif
-
-#ifndef XIic_mClearIntr
-#define XIic_mClearIntr XIic_ClearIntr
-#endif
-
-#ifndef XIic_mClearEnableIntr
-#define XIic_mClearEnableIntr XIic_ClearEnableIntr
-#endif
-
-#ifndef XIic_mFlushRxFifo
-#define XIic_mFlushRxFifo XIic_FlushRxFifo
-#endif
-
-#ifndef XIic_mFlushTxFifo
-#define XIic_mFlushTxFifo XIic_FlushTxFifo
-#endif
-
-#ifndef XIic_mReadRecvByte
-#define XIic_mReadRecvByte XIic_ReadRecvByte
-#endif
-
-#ifndef XIic_mWriteSendByte
-#define XIic_mWriteSendByte XIic_WriteSendByte
-#endif
-
-#ifndef XIic_mSetControlRegister
-#define XIic_mSetControlRegister XIic_SetControlRegister
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XIntc
- *
- *********************************************************************/
-#ifndef XIntc_mMasterEnable
-#define XIntc_mMasterEnable XIntc_MasterEnable
-#endif
-
-#ifndef XIntc_mMasterDisable
-#define XIntc_mMasterDisable XIntc_MasterDisable
-#endif
-
-#ifndef XIntc_mEnableIntr
-#define XIntc_mEnableIntr XIntc_EnableIntr
-#endif
-
-#ifndef XIntc_mDisableIntr
-#define XIntc_mDisableIntr XIntc_DisableIntr
-#endif
-
-#ifndef XIntc_mAckIntr
-#define XIntc_mAckIntr XIntc_AckIntr
-#endif
-
-#ifndef XIntc_mGetIntrStatus
-#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XLlDma
- *
- *********************************************************************/
-#ifndef XLlDma_mBdRead
-#define XLlDma_mBdRead XLlDma_BdRead
-#endif
-
-#ifndef XLlDma_mBdWrite
-#define XLlDma_mBdWrite XLlDma_BdWrite
-#endif
-
-#ifndef XLlDma_mWriteReg
-#define XLlDma_mWriteReg XLlDma_WriteReg
-#endif
-
-#ifndef XLlDma_mReadReg
-#define XLlDma_mReadReg XLlDma_ReadReg
-#endif
-
-#ifndef XLlDma_mBdClear
-#define XLlDma_mBdClear XLlDma_BdClear
-#endif
-
-#ifndef XLlDma_mBdSetStsCtrl
-#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdGetStsCtrl
-#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
-#endif
-
-#ifndef XLlDma_mBdSetLength
-#define XLlDma_mBdSetLength XLlDma_BdSetLength
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mBdSetId
-#define XLlDma_mBdSetId XLlDma_BdSetId
-#endif
-
-#ifndef XLlDma_mBdGetId
-#define XLlDma_mBdGetId XLlDma_BdGetId
-#endif
-
-#ifndef XLlDma_mBdSetBufAddr
-#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetBufAddr
-#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
-#endif
-
-#ifndef XLlDma_mBdGetLength
-#define XLlDma_mBdGetLength XLlDma_BdGetLength
-#endif
-
-#ifndef XLlDma_mGetTxRing
-#define XLlDma_mGetTxRing XLlDma_GetTxRing
-#endif
-
-#ifndef XLlDma_mGetRxRing
-#define XLlDma_mGetRxRing XLlDma_GetRxRing
-#endif
-
-#ifndef XLlDma_mGetCr
-#define XLlDma_mGetCr XLlDma_GetCr
-#endif
-
-#ifndef XLlDma_mSetCr
-#define XLlDma_mSetCr XLlDma_SetCr
-#endif
-
-#ifndef XLlDma_mBdRingCntCalc
-#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
-#endif
-
-#ifndef XLlDma_mBdRingMemCalc
-#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
-#endif
-
-#ifndef XLlDma_mBdRingGetCnt
-#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
-#endif
-
-#ifndef XLlDma_mBdRingGetFreeCnt
-#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
-#endif
-
-#ifndef XLlDma_mBdRingSnapShotCurrBd
-#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
-#endif
-
-#ifndef XLlDma_mBdRingNext
-#define XLlDma_mBdRingNext XLlDma_BdRingNext
-#endif
-
-#ifndef XLlDma_mBdRingPrev
-#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
-#endif
-
-#ifndef XLlDma_mBdRingGetSr
-#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
-#endif
-
-#ifndef XLlDma_mBdRingSetSr
-#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
-#endif
-
-#ifndef XLlDma_mBdRingGetCr
-#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
-#endif
-
-#ifndef XLlDma_mBdRingSetCr
-#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
-#endif
-
-#ifndef XLlDma_mBdRingBusy
-#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
-#endif
-
-#ifndef XLlDma_mBdRingIntEnable
-#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
-#endif
-
-#ifndef XLlDma_mBdRingIntDisable
-#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
-#endif
-
-#ifndef XLlDma_mBdRingIntGetEnabled
-#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
-#endif
-
-#ifndef XLlDma_mBdRingGetIrq
-#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
-#endif
-
-#ifndef XLlDma_mBdRingAckIrq
-#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMbox
- *
- *********************************************************************/
-#ifndef XMbox_mWriteReg
-#define XMbox_mWriteReg XMbox_WriteReg
-#endif
-
-#ifndef XMbox_mReadReg
-#define XMbox_mReadReg XMbox_ReadReg
-#endif
-
-#ifndef XMbox_mWriteMBox
-#define XMbox_mWriteMBox XMbox_WriteMBox
-#endif
-
-#ifndef XMbox_mReadMBox
-#define XMbox_mReadMBox XMbox_ReadMBox
-#endif
-
-#ifndef XMbox_mFSLReadMBox
-#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
-#endif
-
-#ifndef XMbox_mFSLWriteMBox
-#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
-#endif
-
-#ifndef XMbox_mFSLIsEmpty
-#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
-#endif
-
-#ifndef XMbox_mFSLIsFull
-#define XMbox_mFSLIsFull XMbox_FSLIsFull
-#endif
-
-#ifndef XMbox_mIsEmpty
-#define XMbox_mIsEmpty XMbox_IsEmptyHw
-#endif
-
-#ifndef XMbox_mIsFull
-#define XMbox_mIsFull XMbox_IsFullHw
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMpmc
- *
- *********************************************************************/
-#ifndef XMpmc_mReadReg
-#define XMpmc_mReadReg XMpmc_ReadReg
-#endif
-
-#ifndef XMpmc_mWriteReg
-#define XMpmc_mWriteReg XMpmc_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XMutex
- *
- *********************************************************************/
-#ifndef XMutex_mWriteReg
-#define XMutex_mWriteReg XMutex_WriteReg
-#endif
-
-#ifndef XMutex_mReadReg
-#define XMutex_mReadReg XMutex_ReadReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XPcie
- *
- *********************************************************************/
-#ifndef XPcie_mReadReg
-#define XPcie_mReadReg XPcie_ReadReg
-#endif
-
-#ifndef XPcie_mWriteReg
-#define XPcie_mWriteReg XPcie_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSpi
- *
- *********************************************************************/
-#ifndef XSpi_mIntrGlobalEnable
-#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
-#endif
-
-#ifndef XSpi_mIntrGlobalDisable
-#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
-#endif
-
-#ifndef XSpi_mIsIntrGlobalEnabled
-#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
-#endif
-
-#ifndef XSpi_mIntrGetStatus
-#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
-#endif
-
-#ifndef XSpi_mIntrClear
-#define XSpi_mIntrClear XSpi_IntrClear
-#endif
-
-#ifndef XSpi_mIntrEnable
-#define XSpi_mIntrEnable XSpi_IntrEnable
-#endif
-
-#ifndef XSpi_mIntrDisable
-#define XSpi_mIntrDisable XSpi_IntrDisable
-#endif
-
-#ifndef XSpi_mIntrGetEnabled
-#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
-#endif
-
-#ifndef XSpi_mSetControlReg
-#define XSpi_mSetControlReg XSpi_SetControlReg
-#endif
-
-#ifndef XSpi_mGetControlReg
-#define XSpi_mGetControlReg XSpi_GetControlReg
-#endif
-
-#ifndef XSpi_mGetStatusReg
-#define XSpi_mGetStatusReg XSpi_GetStatusReg
-#endif
-
-#ifndef XSpi_mSetSlaveSelectReg
-#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mGetSlaveSelectReg
-#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
-#endif
-
-#ifndef XSpi_mEnable
-#define XSpi_mEnable XSpi_Enable
-#endif
-
-#ifndef XSpi_mDisable
-#define XSpi_mDisable XSpi_Disable
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysAce
- *
- *********************************************************************/
-#ifndef XSysAce_mGetControlReg
-#define XSysAce_mGetControlReg XSysAce_GetControlReg
-#endif
-
-#ifndef XSysAce_mSetControlReg
-#define XSysAce_mSetControlReg XSysAce_SetControlReg
-#endif
-
-#ifndef XSysAce_mOrControlReg
-#define XSysAce_mOrControlReg XSysAce_OrControlReg
-#endif
-
-#ifndef XSysAce_mAndControlReg
-#define XSysAce_mAndControlReg XSysAce_AndControlReg
-#endif
-
-#ifndef XSysAce_mGetErrorReg
-#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
-#endif
-
-#ifndef XSysAce_mGetStatusReg
-#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
-#endif
-
-#ifndef XSysAce_mWaitForLock
-#define XSysAce_mWaitForLock XSysAce_WaitForLock
-#endif
-
-#ifndef XSysAce_mEnableIntr
-#define XSysAce_mEnableIntr XSysAce_EnableIntr
-#endif
-
-#ifndef XSysAce_mDisableIntr
-#define XSysAce_mDisableIntr XSysAce_DisableIntr
-#endif
-
-#ifndef XSysAce_mIsReadyForCmd
-#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
-#endif
-
-#ifndef XSysAce_mIsMpuLocked
-#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
-#endif
-
-#ifndef XSysAce_mIsIntrEnabled
-#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XSysMon
- *
- *********************************************************************/
-#ifndef XSysMon_mIsEventSamplingModeSet
-#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
-#endif
-
-#ifndef XSysMon_mIsDrpBusy
-#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
-#endif
-
-#ifndef XSysMon_mIsDrpLocked
-#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
-#endif
-
-#ifndef XSysMon_mRawToTemperature
-#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
-#endif
-
-#ifndef XSysMon_mRawToVoltage
-#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
-#endif
-
-#ifndef XSysMon_mTemperatureToRaw
-#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
-#endif
-
-#ifndef XSysMon_mVoltageToRaw
-#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
-#endif
-
-#ifndef XSysMon_mReadReg
-#define XSysMon_mReadReg XSysMon_ReadReg
-#endif
-
-#ifndef XSysMon_mWriteReg
-#define XSysMon_mWriteReg XSysMon_WriteReg
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XTmrCtr
- *
- *********************************************************************/
-#ifndef XTimerCtr_mReadReg
-#define XTimerCtr_mReadReg XTimerCtr_ReadReg
-#endif
-
-#ifndef XTmrCtr_mWriteReg
-#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
-#endif
-
-#ifndef XTmrCtr_mSetControlStatusReg
-#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetControlStatusReg
-#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
-#endif
-
-#ifndef XTmrCtr_mGetTimerCounterReg
-#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mSetLoadReg
-#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
-#endif
-
-#ifndef XTmrCtr_mGetLoadReg
-#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
-#endif
-
-#ifndef XTmrCtr_mEnable
-#define XTmrCtr_mEnable XTmrCtr_Enable
-#endif
-
-#ifndef XTmrCtr_mDisable
-#define XTmrCtr_mDisable XTmrCtr_Disable
-#endif
-
-#ifndef XTmrCtr_mEnableIntr
-#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
-#endif
-
-#ifndef XTmrCtr_mDisableIntr
-#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
-#endif
-
-#ifndef XTmrCtr_mLoadTimerCounterReg
-#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
-#endif
-
-#ifndef XTmrCtr_mHasEventOccurred
-#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartLite
- *
- *********************************************************************/
-#ifndef XUartLite_mUpdateStats
-#define XUartLite_mUpdateStats XUartLite_UpdateStats
-#endif
-
-#ifndef XUartLite_mWriteReg
-#define XUartLite_mWriteReg XUartLite_WriteReg
-#endif
-
-#ifndef XUartLite_mReadReg
-#define XUartLite_mReadReg XUartLite_ReadReg
-#endif
-
-#ifndef XUartLite_mClearStats
-#define XUartLite_mClearStats XUartLite_ClearStats
-#endif
-
-#ifndef XUartLite_mSetControlReg
-#define XUartLite_mSetControlReg XUartLite_SetControlReg
-#endif
-
-#ifndef XUartLite_mGetStatusReg
-#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
-#endif
-
-#ifndef XUartLite_mIsReceiveEmpty
-#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
-#endif
-
-#ifndef XUartLite_mIsTransmitFull
-#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
-#endif
-
-#ifndef XUartLite_mIsIntrEnabled
-#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
-#endif
-
-#ifndef XUartLite_mEnableIntr
-#define XUartLite_mEnableIntr XUartLite_EnableIntr
-#endif
-
-#ifndef XUartLite_mDisableIntr
-#define XUartLite_mDisableIntr XUartLite_DisableIntr
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUartNs550
- *
- *********************************************************************/
-#ifndef XUartNs550_mUpdateStats
-#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
-#endif
-
-#ifndef XUartNs550_mReadReg
-#define XUartNs550_mReadReg XUartNs550_ReadReg
-#endif
-
-#ifndef XUartNs550_mWriteReg
-#define XUartNs550_mWriteReg XUartNs550_WriteReg
-#endif
-
-#ifndef XUartNs550_mClearStats
-#define XUartNs550_mClearStats XUartNs550_ClearStats
-#endif
-
-#ifndef XUartNs550_mGetLineStatusReg
-#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
-#endif
-
-#ifndef XUartNs550_mGetLineControlReg
-#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
-#endif
-
-#ifndef XUartNs550_mSetLineControlReg
-#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
-#endif
-
-#ifndef XUartNs550_mEnableIntr
-#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
-#endif
-
-#ifndef XUartNs550_mDisableIntr
-#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
-#endif
-
-#ifndef XUartNs550_mIsReceiveData
-#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
-#endif
-
-#ifndef XUartNs550_mIsTransmitEmpty
-#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
-#endif
-
-/*********************************************************************/
-/**
- * Macros for Driver XUsb
- *
- *********************************************************************/
-#ifndef XUsb_mReadReg
-#define XUsb_mReadReg XUsb_ReadReg
-#endif
-
-#ifndef XUsb_mWriteReg
-#define XUsb_mWriteReg XUsb_WriteReg
-#endif
-
-#endif
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_misc_reset.c
-*
-* This file contains the implementation of the reset sequence for various
-* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
-* sequence provided to the interfaces is based on the provision in
-* slcr reset functional blcok.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XDdr_ResetHw()
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= ~XDDRPS_CTRL_RESET_MASK;
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= XDDRPS_CTRL_RESET_MASK;
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XOcm_Remap()
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & ~XSLCR_OCM_CFG_HIADDR_MASK) | XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal = RegVal | XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues()
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0; i<=1;i++);
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8;i++);
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53 ;i++);
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues()
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters()
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & ~XSLCR_LVL_SHFTR_EN_MASK;
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_OCM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_OCM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_GEM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_GEM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_USB_RST_CTRL_VAL;
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_USB_RST_CTRL_VAL;
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_QSPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_QSPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_SPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_SPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_I2C_RST_CTRL_VAL;
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_I2C_RST_CTRL_VAL;
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_UART_RST_CTRL_VAL;
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_UART_RST_CTRL_VAL;
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_CAN_RST_CTRL_VAL;
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_CAN_RST_CTRL_VAL;
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_SMC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_SMC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_DMAC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_DMAC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @param N/A.
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal | XSLCR_GPIO_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & ~XSLCR_GPIO_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
\ No newline at end of file
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register defintions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-#define XDDRC_CTRL_BASEADDR 0xF8006000
-#define XSLCR_BASEADDR 0xF8000000
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C)
-/**< SLCR USB reset control address register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210)
-/**< SLCR GEM reset control address register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214)
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230)
-/**< SLCR SMC reset control address register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234)
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x404
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x404
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x404
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0D
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x1
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x8
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0xF
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0xF
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x1
-#define XSLCR_GEM_RST_CTRL_VAL 0xF3
-#define XSLCR_USB_RST_CTRL_VAL 0x3
-#define XSLCR_I2C_RST_CTRL_VAL 0x3
-#define XSLCR_SPI_RST_CTRL_VAL 0xF
-#define XSLCR_UART_RST_CTRL_VAL 0xF
-#define XSLCR_QSPI_RST_CTRL_VAL 0x3
-#define XSLCR_GPIO_RST_CTRL_VAL 0x1
-#define XSLCR_SMC_RST_CTRL_VAL 0x3
-#define XSLCR_OCM_RST_CTRL_VAL 0x1
-#define XSLCR_SDIO_RST_CTRL_VAL 0x33
-#define XSLCR_CAN_RST_CTRL_VAL 0x3
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw();
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap();
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues();
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues();
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters();
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-#ifndef XIL_PRINTF_H
-#define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void xil_printf(const char *ctrl1, ...);
-void print(char *ptr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.c
-*
-* Contains utility functions to test cache.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
-* cache line.
-* </pre>
-*
-* @note
-*
-* This file contain functions that all operate on HAL.
-*
-******************************************************************************/
-#include "xil_cache.h"
-#include "xil_testcache.h"
-
-extern void xil_printf(const char *ctrl1, ...);
-
-#define DATA_LENGTH 128
-
-#ifdef __GNUC__
-static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
-#elif defined (__ICCARM__)
-static u32 Data[DATA_LENGTH];
-#else
-static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
-#endif
-
-/**
-* Perform DCache range related API test such as Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange. This test function writes a constant value
-* to the Data array, flushes the range, writes a new value, then invalidates
-* the corresponding range.
-*
-* @return
-*
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*/
-int Xil_TestDCacheRange(void)
-{
- int Index;
- int Status;
-
- u32 Value;
-
- xil_printf("-- Cache Range Test --\n\r");
-
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A00505;
-
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32));
-
- xil_printf(" flush range done\r\n");
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidateRange((u32)Data, DATA_LENGTH * sizeof(u32));
-
- xil_printf(" invalidate dcache range done\r\n");
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A00505) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Invalidate worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache range not working\r\n");
- }
-
- xil_printf("-- Cache Range Test Complete --\r\n");
-
- return Status;
-
-}
-
-/**
-* Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value, then invalidates
-* the DCache.
-*
-* @return
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*/
-int Xil_TestDCacheAll(void)
-{
- int Index;
- int Status;
- u32 Value;
-
- xil_printf("-- Cache All Test --\n\r");
-
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50500A0A;
-
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlush();
-
- xil_printf(" flush all done\r\n");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidate();
-
- xil_printf(" invalidate all done\r\n");
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0x50500A0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Invalidate all worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache all not working\r\n");
- }
-
- xil_printf("-- DCache all Test Complete --\n\r");
-
- return Status;
-
-}
-
-
-/**
-* Perform Xil_ICacheInvalidateRange() on a few function pointers.
-*
-* @return
-*
-* - 0 is returned for a pass
-* The function will hang if it fails.
-*/
-int Xil_TestICacheRange(void)
-{
-
- Xil_ICacheInvalidateRange((u32)Xil_TestICacheRange, 1024);
- Xil_ICacheInvalidateRange((u32)Xil_TestDCacheRange, 1024);
- Xil_ICacheInvalidateRange((u32)Xil_TestDCacheAll, 1024);
-
- xil_printf("-- Invalidate icache range done --\r\n");
-
- return 0;
-}
-
-/**
-* Perform Xil_ICacheInvalidate().
-*
-* @return
-*
-* - 0 is returned for a pass
-* The function will hang if it fails.
-*/
-int Xil_TestICacheAll(void)
-{
- Xil_ICacheInvalidate();
- xil_printf("-- Invalidate icache all done --\r\n");
- return 0;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* This file contains utility functions to test cache.
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-*
-******************************************************************************/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern int Xil_TestDCacheRange(void);
-extern int Xil_TestDCacheAll(void);
-extern int Xil_TestICacheRange(void);
-extern int Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmemend.c
-*
-* Contains the memory test utility functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testio.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- *
- * Endian swap a 16-bit word.
- * @param Data is the 16-bit word to be swapped.
- * @return The endian swapped valud.
- *
- */
-static u16 Swap16(u16 Data)
-{
- return ((Data >> 8) & 0x00FF) | ((Data << 8) & 0xFF00);
-}
-
-/**
- *
- * Endian swap a 32-bit word.
- * @param Data is the 32-bit word to be swapped.
- * @return The endian swapped valud.
- *
- */
-static u32 Swap32(u32 Data)
-{
- u16 Lo16;
- u16 Hi16;
-
- u16 Swap16Lo;
- u16 Swap16Hi;
-
- Hi16 = (u16)((Data >> 16) & 0x0000FFFF);
- Lo16 = (u16)(Data & 0x0000FFFF);
-
- Swap16Lo = Swap16(Lo16);
- Swap16Hi = Swap16(Hi16);
-
- return (((u32)(Swap16Lo)) << 16) | ((u32)Swap16Hi);
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 8-bit wide register IO test where the register is
-* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
-* values.
-*
-* @param Addr is a pointer to the region of memory to be tested.
-* @param Len is the length of the block.
-* @param Value is the constant used for writting the memory.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-int Xil_TestIO8(u8 *Addr, int Len, u8 Value)
-{
- u8 ValueIn;
- int Index;
-
- for (Index = 0; Index < Len; Index++) {
- Xil_Out8((u32)Addr, Value);
-
- ValueIn = Xil_In8((u32)Addr);
-
- if (Value != ValueIn) {
- return -1;
- }
- }
-
- return 0;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 16-bit wide register IO test. Each location is tested
-* by sequentially writing a 16-bit wide register, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function performs the following
-* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
-* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
-* read-in value before comparing is controlled by the 5th argument.
-*
-* @param Addr is a pointer to the region of memory to be tested.
-* @param Len is the length of the block.
-* @param Value is the constant used for writting the memory.
-* @param Kind is the test kind. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap indicates whether to byte swap the read-in value.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap)
-{
- u16 ValueIn;
- int Index;
-
- for (Index = 0; Index < Len; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out16LE((u32)Addr, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out16BE((u32)Addr, Value);
- break;
- default:
- Xil_Out16((u32)Addr, Value);
- break;
- }
-
- ValueIn = Xil_In16((u32)Addr);
-
- if (Kind && Swap)
- ValueIn = Swap16(ValueIn);
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out16((u32)Addr, Value);
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In16LE((u32)Addr);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In16BE((u32)Addr);
- break;
- default:
- ValueIn = Xil_In16((u32)Addr);
- break;
- }
-
-
- if (Kind && Swap)
- ValueIn = Swap16(ValueIn);
-
- if (Value != ValueIn) {
- return -1;
- }
- Addr++;
- }
-
- return 0;
-
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 32-bit wide register IO test. Each location is tested
-* by sequentially writing a 32-bit wide regsiter, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function perform the following
-* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
-* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
-* before comparing is controlled by the 5th argument.
-*
-* @param Addr is a pointer to the region of memory to be tested.
-* @param Len is the length of the block.
-* @param Value is the constant used for writting the memory.
-* @param Kind is the test kind. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap indicates whether to byte swap the read-in value.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap)
-{
- u32 ValueIn;
- int Index;
-
- for (Index = 0; Index < Len; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out32LE((u32)Addr, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out32BE((u32)Addr, Value);
- break;
- default:
- Xil_Out32((u32)Addr, Value);
- break;
- }
-
- ValueIn = Xil_In32((u32)Addr);
-
- if (Kind && Swap)
- ValueIn = Swap32(ValueIn);
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out32((u32)Addr, Value);
-
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In32LE((u32)Addr);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In32BE((u32)Addr);
- break;
- default:
- ValueIn = Xil_In32((u32)Addr);
- break;
- }
-
- if (Kind && Swap)
- ValueIn = Swap32(ValueIn);
-
- if (Value != ValueIn) {
- return -1;
- }
- Addr++;
- }
- return 0;
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmemend.h
-*
-* This file contains utility functions to teach endian related memory
-* IO functions.
-*
-* <b>Memory test description</b>
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTIO_H /* prevent circular inclusions */
-#define XIL_TESTIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 0
-#define XIL_TESTIO_LE 1
-#define XIL_TESTIO_BE 2
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value);
-extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap);
-extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.c
-*
-* Contains the memory test utility functions.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testmem.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static u32 RotateLeft(u32 Input, u8 Width);
-
-/* define ROTATE_RIGHT to give access to this functionality */
-/* #define ROTATE_RIGHT */
-#ifdef ROTATE_RIGHT
-static u32 RotateRight(u32 Input, u8 Width);
-#endif /* ROTATE_RIGHT */
-
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 32-bit wide memory test.
-*
-* @param Addr is a pointer to the region of memory to be tested.
-* @param Words is the length of the block.
-* @param Pattern is the constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest is the test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 J;
- u32 Val;
- u32 FirtVal;
- u32 Word;
-
- Xil_AssertNonvoid(Words != 0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Select the proper Subtest
- */
- switch (Subtest) {
-
- case XIL_TESTMEM_ALLMEMTESTS:
-
- /* this case executes all of the Subtests */
-
- /* fall through case statement */
-
- case XIL_TESTMEM_INCREMENT:
-
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0L; I < Words; I++) {
- Addr[I] = Val;
- Val++;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0L; I < Words; I++) {
- Word = Addr[I];
-
- if (Word != Val) {
- return -1;
- }
-
- Val++;
- }
-
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
-
-
- /* end of case 1 */
-
- /* fall through case statement */
-
- case XIL_TESTMEM_WALKONES:
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (J = 0L; J < 32; J++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = 1 << J;
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0L; I < 32; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val = (u32) RotateLeft(Val, 32);
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1 << J;
-
- /* Read the values from each location that was
- * written */
- for (I = 0L; I < 32; I++) {
- /* read memory location */
-
- Word = Addr[I];
-
- if (Word != Val) {
- return -1;
- }
-
- Val = (u32)RotateLeft(Val, 32);
- }
-
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
-
- /* end of case 2 */
- /* fall through case statement */
-
- case XIL_TESTMEM_WALKZEROS:
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (J = 0L; J < 32; J++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1 << J);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0L; I < 32; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val = ~((u32)RotateLeft(~Val, 32));
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1 << J);
-
- /* Read the values from each location that was
- * written */
- for (I = 0L; I < 32; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- Val = ~((u32)RotateLeft(~Val, 32));
- }
-
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
-
- /* end of case 3 */
-
- /* fall through case statement */
-
- case XIL_TESTMEM_INVERSEADDR:
- /* Fill the memory with inverse of address */
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Val = (u32) (~((u32) (&Addr[I])));
- Addr[I] = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0L; I < Words; I++) {
- /* Read the location */
- Word = Addr[I];
- Val = (u32) (~((u32) (&Addr[I])));
-
- if ((Word ^ Val) != 0x00000000) {
- return -1;
- }
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 4 */
-
- /* fall through case statement */
-
- case XIL_TESTMEM_FIXEDPATTERN:
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == 0) {
- Val = 0xDEADBEEF;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Addr[I] = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0L; I < Words; I++) {
-
- /* read memory location */
-
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 5 */
-
- /* this break is for the prior fall through case statements */
-
- break;
-
- default:
- return -1;
-
- } /* end of switch */
-
- /* Successfully passed memory test ! */
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 16-bit wide memory test.
-*
-* @param Addr is a pointer to the region of memory to be tested.
-* @param Words is the length of the block.
-* @param Pattern is the constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest is the test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 J;
- u16 Val;
- u16 FirtVal;
- u16 Word;
-
- Xil_AssertNonvoid(Words != 0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- switch (Subtest) {
-
- case XIL_TESTMEM_ALLMEMTESTS:
-
- /* this case executes all of the Subtests */
-
- /* fall through case statement */
-
- case XIL_TESTMEM_INCREMENT:
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0L; I < Words; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- Val++;
- }
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
-
- /* end of case 1 */
- /* fall through case statement */
-
- case XIL_TESTMEM_WALKONES:
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (J = 0L; J < 16; J++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = 1 << J;
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0L; I < 16; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val = (u16)RotateLeft(Val, 16);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = 1 << J;
- /* Read the values from each location that was written */
- for (I = 0L; I < 16; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- Val = (u16)RotateLeft(Val, 16);
- }
-
- }
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 2 */
- /* fall through case statement */
-
- case XIL_TESTMEM_WALKZEROS:
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (J = 0L; J < 16; J++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1 << J);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0L; I < 16; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val = ~((u16)RotateLeft(~Val, 16));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1 << J);
- /* Read the values from each location that was written */
- for (I = 0L; I < 16; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- Val = ~((u16)RotateLeft(~Val, 16));
- }
-
- }
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 3 */
- /* fall through case statement */
-
- case XIL_TESTMEM_INVERSEADDR:
- /* Fill the memory with inverse of address */
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Val = (u16) (~((u32) (&Addr[I])));
- Addr[I] = Val;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0L; I < Words; I++) {
- /* read memory location */
- Word = Addr[I];
- Val = (u16) (~((u32) (&Addr[I])));
- if ((Word ^ Val) != 0x0000) {
- return -1;
- }
- }
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 4 */
- /* fall through case statement */
-
- case XIL_TESTMEM_FIXEDPATTERN:
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == 0) {
- Val = 0xDEAD;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Addr[I] = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0L; I < Words; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- }
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 5 */
- /* this break is for the prior fall through case statements */
-
- break;
-
- default:
- return -1;
-
- } /* end of switch */
-
- /* Successfully passed memory test ! */
-
- return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Perform a destructive 8-bit wide memory test.
-*
-* @param Addr is a pointer to the region of memory to be tested.
-* @param Words is the length of the block.
-* @param Pattern is the constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest is the test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 J;
- u8 Val;
- u8 FirtVal;
- u8 Word;
-
- Xil_AssertNonvoid(Words != 0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- switch (Subtest) {
-
- case XIL_TESTMEM_ALLMEMTESTS:
- /* this case executes all of the Subtests */
- /* fall through case statement */
-
- case XIL_TESTMEM_INCREMENT:
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0L; I < Words; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- Val++;
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 1 */
-
- /* fall through case statement */
-
- case XIL_TESTMEM_WALKONES:
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (J = 0L; J < 8; J++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = 1 << J;
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0L; I < 8; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val = (u8)RotateLeft(Val, 8);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = 1 << J;
- /* Read the values from each location that was written */
- for (I = 0L; I < 8; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- Val = (u8)RotateLeft(Val, 8);
- }
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 2 */
- /* fall through case statement */
-
- case XIL_TESTMEM_WALKZEROS:
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (J = 0L; J < 8; J++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = ~(1 << J);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0L; I < 8; I++) {
- /* write memory location */
- Addr[I] = Val;
- Val = ~((u8)RotateLeft(~Val, 8));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1 << J);
- /* Read the values from each location that was written */
- for (I = 0L; I < 8; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
-
- Val = ~((u8)RotateLeft(~Val, 8));
- }
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 3 */
- /* fall through case statement */
-
- case XIL_TESTMEM_INVERSEADDR:
- /* Fill the memory with inverse of address */
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((u32) (&Addr[I])));
- Addr[I] = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0L; I < Words; I++) {
- /* read memory location */
- Word = Addr[I];
- Val = (u8) (~((u32) (&Addr[I])));
- if ((Word ^ Val) != 0x00) {
- return -1;
- }
- }
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
- /* end of case 4 */
- /* fall through case statement */
-
- case XIL_TESTMEM_FIXEDPATTERN:
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == 0) {
- Val = 0xA5;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0L; I < Words; I++) {
- /* write memory location */
- Addr[I] = Val;
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0L; I < Words; I++) {
- /* read memory location */
- Word = Addr[I];
- if (Word != Val) {
- return -1;
- }
- }
-
- if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
- return 0;
- }
-
- /* end of case 5 */
-
- /* this break is for the prior fall through case statements */
-
- break;
-
- default:
- return -1;
-
- } /* end of switch */
-
- /* Successfully passed memory test ! */
-
- return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Rotates the provided value to the left one bit position
-*
-* @param Input is value to be rotated to the left
-* @param Width is the number of bits in the input data
-*
-* @return
-*
-* The resulting unsigned long value of the rotate left
-*
-* @note
-*
-* None.
-*
-*****************************************************************************/
-static u32 RotateLeft(u32 Input, u8 Width)
-{
- u32 Msb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
-
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1 << (Width - 1);
-
- WidthMask = (MsbMask << 1) - 1;
-
- /*
- * set the Width of the Input to the correct width
- */
-
- Input = Input & WidthMask;
-
- Msb = Input & MsbMask;
-
- ReturnVal = Input << 1;
-
- if (Msb != 0x00000000) {
- ReturnVal = ReturnVal | 0x00000001;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-
-#ifdef ROTATE_RIGHT
-/*****************************************************************************/
-/**
-*
-* Rotates the provided value to the right one bit position
-*
-* @param Input is value to be rotated to the right
-* @param Width is the number of bits in the input data
-*
-* @return
-*
-* The resulting u32 value of the rotate right
-*
-* @note
-*
-* None.
-*
-*****************************************************************************/
-static u32 RotateRight(u32 Input, u8 Width)
-{
- u32 Lsb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
-
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1 << (Width - 1);
-
- WidthMask = (MsbMask << 1) - 1;
-
- /*
- * set the width of the input to the correct width
- */
-
- Input = Input & WidthMask;
-
- ReturnVal = Input >> 1;
-
- Lsb = Input & 0x00000001;
-
- if (Lsb != 0x00000000) {
- ReturnVal = ReturnVal | MsbMask;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-#endif /* ROTATE_RIGHT */
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-*
-* This file contains utility functions to test memory.
-*
-* <b>Memory test description</b>
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* Subtest descriptions:
-* <pre>
-* XIL_TESTMEM_ALLMEMTESTS:
-* Runs all of the following tests
-*
-* XIL_TESTMEM_INCREMENT:
-* Incrementing Value Test.
-* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
-* incrementing value as the test value for memory.
-*
-* XIL_TESTMEM_WALKONES:
-* Walking Ones Test.
-* This test uses a walking '1' as the test value for memory.
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-*
-* XIL_TESTMEM_WALKZEROS:
-* Walking Zero's Test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*
-* XIL_TESTMEM_INVERSEADDR:
-* Inverse Address Test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* XIL_TESTMEM_FIXEDPATTERN:
-* Fixed Pattern Test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-* </pre>
-*
-* <i>WARNING</i>
-*
-* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
-* have been set up.
-*
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-*
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundry of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
-#define XIL_TESTMEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* xutil_memtest defines */
-
-#define XIL_TESTMEM_INIT_VALUE 1
-
-/** @name Memory subtests
- * @{
- */
-/**
- * See the detailed description of the subtests in the file description.
- */
-#define XIL_TESTMEM_ALLMEMTESTS 0
-#define XIL_TESTMEM_INCREMENT 1
-#define XIL_TESTMEM_WALKONES 2
-#define XIL_TESTMEM_WALKZEROS 3
-#define XIL_TESTMEM_INVERSEADDR 4
-#define XIL_TESTMEM_FIXEDPATTERN 5
-#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
-/* @} */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/* xutil_testmem prototypes */
-
-extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
-extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
-extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* This file contains basic types for Xilinx software IP.
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 4.2 srt 07/03/14 Use standard definitions from stdint.h
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#include <stdint.h>
-#include <stddef.h>
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1
-#endif
-
-#ifndef FALSE
-# define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */
-#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/**
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-* @note None.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-* @note None.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/**
- * xbasic_types.h does not typedef s* or u64
- */
-typedef uint64_t u64;
-
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-
-#else
-#include <linux/types.h>
-#endif
-
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/*@}*/
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* This file contains Xilinx software status codes. Status codes have their
-* own data type called int. These codes are used throughout the Xilinx
-* device drivers.
-*
-******************************************************************************/
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /* an error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /* an error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /* the device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /* there was no data available */
-#define XST_REGISTER_ERROR 14L /* a register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /* the device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
-#define XST_NO_CALLBACK 18L /* a callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /* device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /* device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /* device is busy */
-#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /* used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /* used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /* driver defined error */
-#define XST_RECV_ERROR 27L /* generic receive error */
-#define XST_SEND_ERROR 28L /* generic transmit error */
-#define XST_NOT_ENABLED 29L /* a requested service is not
- available because it has not
- been enabled */
-
-/***************** Utility Component statuses 401 - 500 *********************/
-
-#define XST_MEMTEST_FAILED 401L /* memory test failed */
-
-
-/***************** Common Components statuses 501 - 1000 *********************/
-
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
- * empty and full simultaneously
- */
-
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
- put into the scatter gather
- list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
- error */
-
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /* generic ipif error */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
-#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
- * collision on polled send */
-
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
-#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
-
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /* Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
-
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
-
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
-
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
-
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
-
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /* Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /* Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /* Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
- */
-
-/**************************** Type Definitions *******************************/
-
-typedef int XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
--- /dev/null
+###############################################################################
+#
+# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+# The following are defined in config.make
+# LIBSOURCES - Based on if MicroBlaze support Exceptions
+# LIBS - Do Build Profile Libraries
+include config.make
+
+AS=mb-as
+CC=mb-gcc
+AR=mb-ar
+CP=cp
+COMPILER_FLAGS=-O2 -c
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+ echo "Compiling standalone";
+ $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+ $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+profile_libs:
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs
+
+include: standalone_includes profile_includes
+
+standalone_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+profile_includes:
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" include
+
+clean:
+ rm -rf ${OUTS}
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" clean
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <unistd.h>
+#include "xil_types.h"
+void _exit (sint32 status);
+
+/* _exit - Simple implementation. Does not return.
+*/
+void _exit (sint32 status)
+{
+ (void) status;
+ while (1)
+ {
+ ;
+ }
+}
--- /dev/null
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Configurations for Standalone BSP\r
+*\r
+*******************************************************************/\r
+\r
+#define MICROBLAZE_PVR_NONE\r
--- /dev/null
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ---------------------------------------------------
+ * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ * cacheable regions
+ * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ * generated by the cpu driver, for enabling caches
+ * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
+ * write-thru caches
+ * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
+ * Updated the MMU table to mark OCM in high address space
+ * as inner cacheable and reserved space as Invalid
+ * 3.03a sdm 08/20/11 Changes to support FreeRTOS
+ * Updated the MMU table to mark upper half of the DDR as
+ * non-cacheable
+ * Setup supervisor and abort mode stacks
+ * Do not initialize/enable L2CC in case of AMP
+ * Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ * in case of AMP
+ * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
+ * counters
+ * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
+ * xparameters.h file for CR630532 - Xil_DCacheFlush()/
+ * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ * for MicroBlaze will invalidate data in the cache instead
+ * of flushing it for writeback caches
+ * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
+ * Remove redundant dsb/dmb instructions in cache maintenance
+ * APIs
+ * Remove redundant dsb in mcr instruction
+ * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
+ * driver tcl in xparameters.h. Update the gcc/translationtable.s
+ * for the QSPI complete address range - DT644567
+ * Removed profile directory for armcc compiler and changed
+ * profiling setting to false in standalone_v2_1_0.tcl file
+ * Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ * invalidate the caches before enabling back the MMU and
+ * D cache.
+ * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
+ * xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ * array, flush the D-cache before changing the attributes
+ * in translation table. The user need not call Xil_DisableMMU
+ * before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ * sgd initialization is present. Changes for this were done in
+ * uart.c and xil-crt0.s.
+ * Made changes in xil_io.c to use volatile pointers.
+ * Made changes in xil_mmu.c to correct the function
+ * Xil_SetTlbAttributes.
+ * Changes are made xil-crt0.s to initialize the static
+ * C++ constructors.
+ * Changes are made in boot.s, to fix the TTBR settings,
+ * correct the L2 Cache Auxiliary register settings, L2 cache
+ * latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ * sgd usleep.c to use global timer intstead of CP15.
+ * Made changes in cortexa9/gcc/translation_table.s to map
+ * the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/boot.S to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/translation_table.s to
+ * map the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/boot.S to optimize the
+ * L2 cache settings. Changes the section properties for
+ * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ * and cortexa9/gcc/translation_table.S.
+ * Made changes in cortexa9/xil_cache.c to change the
+ * cache invalidation order.
+ * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
+ * compilation/linking issues for C++ compiler.
+ * Made changes in mb_interface.h to remove compilation/
+ * linking issues for C++ compiler.
+ * Added macros for swapb and swaph microblaze instructions
+ * mb_interface.h
+ * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ * for CortexA9.
+ * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa 08/31/12 Added xil_printf.h include
+ * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
+ * Corrected L2 cache sequence disable sequence
+ * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
+ * irq/fiq handling.
+ * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ * fixes the CR #692094.
+ * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt 04/18/13 Implemented ARM Erratas.
+ * Cortex A9 Errata - 742230, 743622, 775420, 794073
+ * L2Cache PL310 Errata - 588369, 727915, 759370
+ * Please refer to file 'xil_errata.h' for errata
+ * description.
+ * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ * cache APIs were corresponding to only Layer 1 cache
+ * memories. New APIs were now added and the existing cache
+ * related APIs were changed to provide a uniform interface
+ * to flush/invalidate/enable/disable the complete cache
+ * system which includes both L1 and L2 caches. The changes
+ * for these were done in:
+ * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ * files.
+ * Four new files were added for supporting L2 cache. They are:
+ * microblaze_flush_cache_ext.S-> Flushes L2 cache
+ * microblaze_flush_cache_ext_range.S -> Flushes a range of
+ * memory in L2 cache.
+ * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ * microblaze_invalidate_cache_ext_range -> Invalidates a
+ * range of memory in L2 cache.
+ * These changes are done to implement PR #697214.
+ * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ * fix the CR #706464. L2 cache disabling happens independent
+ * of L1 data cache disable operation. Changes are done in the
+ * same file in cache handling APIs to do a L2 cache sync
+ * (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
+ * interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ * sync operation. This fixes the CR# 716781.
+ * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
+ * for armcc toolchain.
+ * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ * fix issues related to NEON context saving. The assembly
+ * routines for IRQ and FIQ handling are modified.
+ * Deprecated the older BSP (3.10a).
+ * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ * various potential issues. Made changes in the function
+ * Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ * in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ * L2 cache sync operation and to fix issues around complete
+ * L2 cache flush/invalidation by ways.
+ * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ * to fix linking issues with armcc/DS-5. Modified the armcc
+ * makefile to fix issues.
+ * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ * src\cortexa9\armcc\) to fix CR#767251
+ * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ * Few cache lines were missed to invalidate when unaligned address
+ * invalidation was accommodated in Xil_DCacheInvalidateRange.
+ * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ * stack memory (which contains return address) was invalidated. So
+ * stack memory is flushed first and then L1D cache is invalidated.
+ * This is done to fix CR #763829
+ * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ * mblaze_nt_types.h file and replace uint32_t with u32 in the
+ * profile_hist.c to fix the above CR.
+ * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * instead of libxil.a and added prototypes for
+ * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ * mb_interface.h
+ * 4.1 hk 04/18/14 Add sleep function.
+ * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ * some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
+ * CR#794205
+ * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ * common/xil_testcache.c
+ * Fix for CR#764881.
+ * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ * output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
+ * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ * cortexa9/armcc/boot.s. Added default exception handlers for data
+ * abort and prefetch abort using handlers called
+ * DataAbortHandler and PrefetchAbortHandler respectively in
+ * cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
+ * issue of improper linking of translation_table.s
+ * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
+ * in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp 07/21/14 Corrected reset value of event counter in function
+ * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
+ * containing type def u32 defined in xil_types.g to resolve issue of
+ * CR#805869
+ * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ * it is not possible to generate timer in nanosecond due to limited
+ * cpu frequency
+ * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
+ * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ * removed function definition of XSmc_NorInit and XSmc_NorInit from
+ * cortexa9/smc.h
+ * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ * cache_ext_range declarations in mb_interface.h CR#783821.
+ * Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
+ * cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
+ * armcc/translation_table.s and iccarm/translation_table.s
+ * to properly defined reserved entries according to address map for
+ * fixing CR#820146
+ * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
+ * and cortexa9/armcc/translation_table.s to resolve compilation
+ * error for solving CR#822897
+ * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
+ * MISRA-C:2012 compliance.
+ * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
+ * adding src/common/xplatform_info.*s
+ * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
+ * removed incorrect initialization of TLB lockdown register to fix
+ * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ * and iccarm/boot.s
+ * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ * for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ * of L2Cache is done later.
+ * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ * taking long time to fix CR#853097. L2CacheSync is added into
+ * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ * Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ * instead of just System Stack
+ * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS and also take the compiler and archiver as specified
+ * in settings instead of hardcoding it.
+ * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
+ * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ * accordingly generate the translation table
+ * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS to fix a bug introduced during new version creation
+ * of BSP.
+ * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ * functionalities are avoided for the OpenAMP slave application(when
+ * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ * cache for its operation. Also file operations such as read, write,
+ * close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ * defined for BSP) because XilOpenAMP library contains own file operation.
+ * The xil-crt0.S file is modified for not initializing global timer for
+ * OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ * definition for dsb, isb and dmb to fix the compilation error when used
+ * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ * R5 deadlock for errata 780125
+ * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ * 32 bit BSP in the initialization
+ * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API
+ * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
+ * required for MISRA-C:2012 Compliance.
+ * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ * in cortexa9/xil_mmu.h
+ * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
+ * checking the current executing platform
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ * to initialize global constructor for C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ * C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ * translation_table.S to update the translation table according to proper
+ * address map
+ * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
+ * address map
+ * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ * equivalent to vector table base address
+ * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ * as per the toolchain update
+ * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
+ * for Cortex-A53 32bit mode
+ * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ * and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ * instead take it from xparameters.h to properly configure the timestamp
+ * clock frequency
+ * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
+ * new instructions for MB address extension feature
+ * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
+ * system monitor.
+ * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ * use set of assembly instructions to provide required delay to fix
+ * CR#913249.
+ * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ * _exit with exit. We should not be directly calling _exit and should
+ * always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
+ * registers, banked registers for various modes and enabled
+ * the cache ECC check before enabling the fault log for lock step mode
+ * Also modified the cortexr5/gcc/Makefile to support floating point
+ * registers initialization in boot code.
+ * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ * logic in case of lock-step mode when fault log is enabled to fix
+ * CR#938281
+ * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ * header file instrinsics.h which contains assembly instructions
+ * definitions which can be used by C
+ * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ * proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ * interrupts when sleep/usleep is being executed using assembly
+ * instructions to fix CR#913249.
+ * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ * instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ * value and compare it with previous value to detect the overflow
+ * to fix CR#940209.
+ * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ * the fault log to avoid intervention for lock-step mode and cortexr5/
+ * _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ * to fix CR#947335
+ *****************************************************************************************/
--- /dev/null
+LIBSOURCES = *.c *.S\r
+PROFILE_ARCH_OBJS = profile_mcount_mb.o\r
+LIBS = standalone_libs\r
--- /dev/null
+/* The errno variable is stored in the reentrancy structure. This
+ function returns its address for use by the macro errno defined in
+ errno.h. */
+
+#include <errno.h>
+#include <reent.h>
+#include "xil_types.h"
+sint32 * __errno (void);
+
+sint32 *
+__errno (void)
+{
+ return &_REENT->_errno;
+}
--- /dev/null
+#include <stdio.h>
+#include "xil_types.h"
+sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg);
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ * We don't have a filesystem, so we do nothing.
+ */
+sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg)
+{
+ (void) fd;
+ (void) cmd;
+ (void) arg;
+ return 0;
+}
--- /dev/null
+#ifndef FSL_H
+#define FSL_H
+
+#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Extended FSL macros. These now replace all of the previous FSL macros */
+#define FSL_DEFAULT
+#define FSL_NONBLOCKING n
+#define FSL_EXCEPTION e
+#define FSL_CONTROL c
+#define FSL_ATOMIC a
+
+#define FSL_NONBLOCKING_EXCEPTION ne
+#define FSL_NONBLOCKING_CONTROL nc
+#define FSL_NONBLOCKING_ATOMIC na
+#define FSL_EXCEPTION_CONTROL ec
+#define FSL_EXCEPTION_ATOMIC ea
+#define FSL_CONTROL_ATOMIC ca
+
+#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
+#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
+#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
+#define FSL_EXCEPTION_CONTROL_ATOMIC eca
+
+#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
+
+#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
+#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
+
+#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
+#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
+
+#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
+#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
+
+#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
+#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* FSL_H */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+ * Microblaze HW Exception Handler
+ * - Non self-modifying exception handler for the following exception conditions
+ * - Unalignment
+ * - Instruction bus error
+ * - Data bus error
+ * - Illegal instruction opcode
+ * - Divide-by-zero
+ * - Stack protection violation
+ *******************************************************************************/
+
+#include "microblaze_exceptions_g.h"
+#include "xparameters.h"
+
+/* Helpful Macros */
+#define EX_HANDLER_STACK_SIZ (4*21)
+#define RMSR_OFFSET (20 * 4)
+#define R17_OFFSET (0)
+#define REG_OFFSET(regnum) (4 * (regnum + 1))
+#define NUM_TO_REG(num) r ## num
+
+#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum)
+#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
+
+#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
+#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
+
+/* Uses r5 */
+#define PUSH_MSR \
+ mfs r5, rmsr; \
+ swi r5, r1, RMSR_OFFSET;
+
+#define PUSH_MSR_AND_ENABLE_EXC \
+ mfs r5, rmsr; \
+ swi r5, r1, RMSR_OFFSET; \
+ ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
+ mts rmsr, r5;
+
+/* Uses r5 */
+#define POP_MSR \
+ lwi r5, r1, RMSR_OFFSET; \
+ mts rmsr, r5;
+
+/* Push r17 */
+#define PUSH_R17 swi r17, r1, R17_OFFSET
+/* Pop r17 */
+#define POP_R17 lwi r17, r1, R17_OFFSET
+
+#define LWREG_NOP \
+ bri ex_handler_unhandled; \
+ nop;
+
+#define SWREG_NOP \
+ bri ex_handler_unhandled; \
+ nop;
+
+/* r3 is the source */
+#define R3_TO_LWREG_V(regnum) \
+ R3_TO_STACK (regnum); \
+ bri ex_handler_done;
+
+/* r3 is the source */
+#define R3_TO_LWREG(regnum) \
+ or NUM_TO_REG (regnum), r0, r3; \
+ bri ex_handler_done;
+
+/* r3 is the target */
+#define SWREG_TO_R3_V(regnum) \
+ R3_FROM_STACK (regnum); \
+ bri ex_sw_tail;
+
+/* r3 is the target */
+#define SWREG_TO_R3(regnum) \
+ or r3, r0, NUM_TO_REG (regnum); \
+ bri ex_sw_tail;
+
+/* regnum is the source */
+#define FP_EX_OPB_SAVE(regnum) \
+ swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
+ nop; \
+ bri handle_fp_ex_opa;
+
+/* regnum is the source */
+#define FP_EX_OPB_SAVE_V(regnum) \
+ R3_FROM_STACK (regnum); \
+ swi r3, r0, mb_fpex_op_b; \
+ bri handle_fp_ex_opa;
+
+/* regnum is the source */
+#define FP_EX_OPA_SAVE(regnum) \
+ swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
+ nop; \
+ bri handle_fp_ex_done;
+
+/* regnum is the source */
+#define FP_EX_OPA_SAVE_V(regnum) \
+ R3_FROM_STACK (regnum); \
+ swi r3, r0, mb_fpex_op_a; \
+ bri handle_fp_ex_done;
+
+#define FP_EX_UNHANDLED \
+ bri fp_ex_unhandled; \
+ nop; \
+ nop;
+
+/* ESR masks */
+#define ESR_EXC_MASK 0x0000001F
+#define ESR_REG_MASK 0x000003E0
+#define ESR_LW_SW_MASK 0x00000400
+#define ESR_WORD_MASK 0x00000800
+#define ESR_DS_MASK 0x00001000
+
+/* Extern declarations */
+.extern XNullHandler
+
+
+#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
+
+/*
+ * hw_exception_handler - Handler for unaligned exceptions
+ * Exception handler notes:
+ * - Does not handle exceptions other than unaligned exceptions
+ * - Does not handle exceptions during load into r17, r1, r0.
+ * - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
+ *
+ * Relevant register structures
+ *
+ * EAR - |----|----|----|----|----|----|----|----|
+ * - < ## 32 bit faulting address ## >
+ *
+ * ESR - |----|----|----|----|----| - | - |-----|-----|
+ * - W S REG EXC
+ *
+ *
+ * STACK FRAME STRUCTURE
+ * ---------------------
+ *
+ * +-------------+ + 0
+ * | r17 |
+ * +-------------+ + 4
+ * | Args for |
+ * | next func |
+ * +-------------+ + 8
+ * | r1 |
+ * | . |
+ * | . |
+ * | . |
+ * | . |
+ * | r18 |
+ * +-------------+ + 80
+ * | MSR |
+ * +-------------+ + 84
+ * | . |
+ * | . |
+ */
+
+
+.global _hw_exception_handler
+.section .text
+.align 2
+.ent _hw_exception_handler
+.type _hw_exception_handler, @function
+_hw_exception_handler:
+
+#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
+ /* Immediately halt for stack protection violation exception without using any stack */
+ swi r3, r0, mb_sp_save_r3; /* Save temporary register */
+ mfs r3, resr; /* Extract ESR[DS] */
+ andi r3, r3, ESR_EXC_MASK;
+ xori r3, r3, 0x7; /* Check for stack protection violation */
+ bnei r3, ex_handler_not_sp_violation;
+ex_handler_sp_violation:
+ bri 0; /* Halt here if stack protection violation */
+ex_handler_not_sp_violation:
+ lwi r3, r0, mb_sp_save_r3; /* Restore temporary register */
+#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
+
+ addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
+ PUSH_REG(3);
+ PUSH_REG(4);
+ PUSH_REG(5);
+ PUSH_REG(6);
+#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
+ mfs r6, resr;
+ andi r6, r6, ESR_DS_MASK;
+ beqi r6, ex_handler_no_ds;
+ mfs r17, rbtr;
+ex_handler_no_ds:
+#endif
+ PUSH_R17;
+ PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
+
+ mfs r3, resr;
+ andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
+#ifndef NO_UNALIGNED_EXCEPTIONS
+ xori r6, r5, 1; /* 00001 = Unaligned Exception */
+ bnei r6, handle_ex_regular;
+
+ la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
+ lwi r4, r4, 8;
+ la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
+ xor r6, r4, r6; /* the default exception handler */
+ beqi r6, handle_unaligned_ex ;
+
+handle_ex_regular:
+#endif /* ! NO_UNALIGNED_EXCEPTIONS */
+
+#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
+ xori r6, r5, 6; /* 00110 = FPU exception */
+ beqi r6, handle_fp_ex; /* Go and decode the FP exception */
+#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
+
+handle_other_ex: /* Handle Other exceptions here */
+ ori r6, r0, 20;
+ cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
+ blei r6, ex_handler_unhandled;
+
+ ori r6, r0, 7;
+ cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
+ bgti r6, handle_other_ex_tail;
+ ori r5, r0, 0x7;
+
+handle_other_ex_tail:
+ PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
+ PUSH_REG(8);
+ PUSH_REG(9);
+ PUSH_REG(10);
+ PUSH_REG(11);
+ PUSH_REG(12);
+ PUSH_REG(15);
+ PUSH_REG(18);
+
+ la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
+ addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */
+ addk r7, r7, r7;
+ addk r7, r7, r7;
+ addk r7, r7, r4; /* Get pointer to exception vector */
+ lwi r5, r7, 4; /* Load argument to exception handler from table */
+ lw r7, r7, r0; /* Load vector itself here */
+
+ brald r15, r7; /* Branch to handler */
+ nop;
+
+ POP_REG(7); /* Restore other volatiles */
+ POP_REG(8);
+ POP_REG(9);
+ POP_REG(10);
+ POP_REG(11);
+ POP_REG(12);
+ POP_REG(15);
+ POP_REG(18);
+
+ bri ex_handler_done; /* Complete exception handling */
+
+#ifndef NO_UNALIGNED_EXCEPTIONS
+handle_unaligned_ex:
+ andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
+ srl r6, r6; /* r6 >> 5 */
+ srl r6, r6;
+ srl r6, r6;
+ srl r6, r6;
+ srl r6, r6;
+ sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
+ mfs r4, rear;
+ andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
+ bnei r6, ex_sw;
+ex_lw:
+ andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
+ beqi r6, ex_lhw;
+ lbui r5, r4, 0; /* Exception address in r4 */
+ sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
+ lbui r5, r4, 1;
+ sbi r5, r0, ex_tmp_data_loc_1;
+ lbui r5, r4, 2;
+ sbi r5, r0, ex_tmp_data_loc_2;
+ lbui r5, r4, 3;
+ sbi r5, r0, ex_tmp_data_loc_3;
+ lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
+ bri ex_lw_tail;
+ex_lhw:
+ lbui r5, r4, 0; /* Exception address in r4 */
+ sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
+ lbui r5, r4, 1;
+ sbi r5, r0, ex_tmp_data_loc_1;
+ lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
+ex_lw_tail:
+ lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
+ la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
+ addk r5, r5, r5;
+ addk r5, r5, r5;
+ addk r5, r5, r5;
+ addk r5, r5, r6;
+ bra r5;
+ex_lw_end: /* Exception handling of load word, ends */
+ex_sw:
+ lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
+ la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
+ add r5, r5, r5;
+ add r5, r5, r5;
+ add r5, r5, r5;
+ add r5, r5, r6;
+ bra r5;
+ex_sw_tail:
+ mfs r6, resr;
+ andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
+ beqi r6, ex_shw;
+ swi r3, r0, ex_tmp_data_loc_0;
+ lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
+ sbi r3, r4, 0;
+ lbui r3, r0, ex_tmp_data_loc_1;
+ sbi r3, r4, 1;
+ lbui r3, r0, ex_tmp_data_loc_2;
+ sbi r3, r4, 2;
+ lbui r3, r0, ex_tmp_data_loc_3;
+ sbi r3, r4, 3;
+ bri ex_handler_done;
+ex_shw:
+ swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
+
+#ifdef __LITTLE_ENDIAN__
+ lbui r3, r0, ex_tmp_data_loc_0;
+#else
+ lbui r3, r0, ex_tmp_data_loc_2;
+#endif
+ sbi r3, r4, 0;
+#ifdef __LITTLE_ENDIAN__
+ lbui r3, r0, ex_tmp_data_loc_1;
+#else
+ lbui r3, r0, ex_tmp_data_loc_3;
+#endif
+ sbi r3, r4, 1;
+ex_sw_end: /* Exception handling of store word, ends. */
+ bri ex_handler_done;
+#endif /* !NO_UNALIGNED_EXCEPTIONS */
+
+#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
+handle_fp_ex:
+ addik r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */
+ lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */
+
+handle_fp_ex_opb:
+ la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ andi r3, r4, 0x1F;
+ add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
+ add r3, r3, r3;
+ add r5, r3, r3;
+ add r5, r5, r3;
+ add r5, r5, r6;
+ bra r5;
+
+handle_fp_ex_opa:
+ la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ srl r4, r4;
+ andi r3, r4, 0x1F;
+ add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
+ add r3, r3, r3;
+ add r5, r3, r3;
+ add r5, r5, r3;
+ add r5, r5, r6;
+ bra r5;
+
+handle_fp_ex_done:
+ ori r5, r0, 6; /* Set exception number back to 6 */
+ bri handle_other_ex_tail;
+
+fp_ex_unhandled:
+ bri 0;
+#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
+
+ex_handler_done:
+ POP_R17;
+ POP_MSR;
+ POP_REG(3);
+ POP_REG(4);
+ POP_REG(5);
+ POP_REG(6);
+
+ rted r17, 0
+ addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
+ex_handler_unhandled:
+ bri 0 /* UNHANDLED. TRAP HERE */
+.end _hw_exception_handler
+
+#ifndef NO_UNALIGNED_EXCEPTIONS
+
+/*
+ * hw_exception_handler Jump Table
+ * - Contains code snippets for each register that caused the unaligned exception.
+ * - Hence exception handler is NOT self-modifying
+ * - Separate table for load exceptions and store exceptions.
+ * - Each table is of size: (8 * 32) = 256 bytes
+ */
+
+.section .text
+.align 4
+lw_table:
+lw_r0: R3_TO_LWREG (0);
+lw_r1: LWREG_NOP;
+lw_r2: R3_TO_LWREG (2);
+lw_r3: R3_TO_LWREG_V (3);
+lw_r4: R3_TO_LWREG_V (4);
+lw_r5: R3_TO_LWREG_V (5);
+lw_r6: R3_TO_LWREG_V (6);
+lw_r7: R3_TO_LWREG (7);
+lw_r8: R3_TO_LWREG (8);
+lw_r9: R3_TO_LWREG (9);
+lw_r10: R3_TO_LWREG (10);
+lw_r11: R3_TO_LWREG (11);
+lw_r12: R3_TO_LWREG (12);
+lw_r13: R3_TO_LWREG (13);
+lw_r14: R3_TO_LWREG (14);
+lw_r15: R3_TO_LWREG (15);
+lw_r16: R3_TO_LWREG (16);
+lw_r17: LWREG_NOP;
+lw_r18: R3_TO_LWREG (18);
+lw_r19: R3_TO_LWREG (19);
+lw_r20: R3_TO_LWREG (20);
+lw_r21: R3_TO_LWREG (21);
+lw_r22: R3_TO_LWREG (22);
+lw_r23: R3_TO_LWREG (23);
+lw_r24: R3_TO_LWREG (24);
+lw_r25: R3_TO_LWREG (25);
+lw_r26: R3_TO_LWREG (26);
+lw_r27: R3_TO_LWREG (27);
+lw_r28: R3_TO_LWREG (28);
+lw_r29: R3_TO_LWREG (29);
+lw_r30: R3_TO_LWREG (30);
+lw_r31: R3_TO_LWREG (31);
+
+sw_table:
+sw_r0: SWREG_TO_R3 (0);
+sw_r1: SWREG_NOP;
+sw_r2: SWREG_TO_R3 (2);
+sw_r3: SWREG_TO_R3_V (3);
+sw_r4: SWREG_TO_R3_V (4);
+sw_r5: SWREG_TO_R3_V (5);
+sw_r6: SWREG_TO_R3_V (6);
+sw_r7: SWREG_TO_R3 (7);
+sw_r8: SWREG_TO_R3 (8);
+sw_r9: SWREG_TO_R3 (9);
+sw_r10: SWREG_TO_R3 (10);
+sw_r11: SWREG_TO_R3 (11);
+sw_r12: SWREG_TO_R3 (12);
+sw_r13: SWREG_TO_R3 (13);
+sw_r14: SWREG_TO_R3 (14);
+sw_r15: SWREG_TO_R3 (15);
+sw_r16: SWREG_TO_R3 (16);
+sw_r17: SWREG_NOP;
+sw_r18: SWREG_TO_R3 (18);
+sw_r19: SWREG_TO_R3 (19);
+sw_r20: SWREG_TO_R3 (20);
+sw_r21: SWREG_TO_R3 (21);
+sw_r22: SWREG_TO_R3 (22);
+sw_r23: SWREG_TO_R3 (23);
+sw_r24: SWREG_TO_R3 (24);
+sw_r25: SWREG_TO_R3 (25);
+sw_r26: SWREG_TO_R3 (26);
+sw_r27: SWREG_TO_R3 (27);
+sw_r28: SWREG_TO_R3 (28);
+sw_r29: SWREG_TO_R3 (29);
+sw_r30: SWREG_TO_R3 (30);
+sw_r31: SWREG_TO_R3 (31);
+
+/* Temporary data structures used in the handler */
+.section .data
+.align 2
+ex_tmp_data_loc_0:
+ .byte 0
+ex_tmp_data_loc_1:
+ .byte 0
+ex_tmp_data_loc_2:
+ .byte 0
+ex_tmp_data_loc_3:
+ .byte 0
+ex_reg_op:
+ .byte 0
+
+#endif /* ! NO_UNALIGNED_EXCEPTIONS */
+
+#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
+/*
+ * FP exception decode jump table.
+ * - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
+ * - Hence exception handler is NOT self-modifying
+ * - Separate table for opA and opB
+ * - Each table is of size: (12 * 32) = 384 bytes
+ */
+
+.section .text
+.align 4
+fp_table_opa:
+opa_r0: FP_EX_OPA_SAVE (0);
+opa_r1: FP_EX_UNHANDLED;
+opa_r2: FP_EX_OPA_SAVE (2);
+opa_r3: FP_EX_OPA_SAVE_V (3);
+opa_r4: FP_EX_OPA_SAVE_V (4);
+opa_r5: FP_EX_OPA_SAVE_V (5);
+opa_r6: FP_EX_OPA_SAVE_V (6);
+opa_r7: FP_EX_OPA_SAVE (7);
+opa_r8: FP_EX_OPA_SAVE (8);
+opa_r9: FP_EX_OPA_SAVE (9);
+opa_r10: FP_EX_OPA_SAVE (10);
+opa_r11: FP_EX_OPA_SAVE (11);
+opa_r12: FP_EX_OPA_SAVE (12);
+opa_r13: FP_EX_OPA_SAVE (13);
+opa_r14: FP_EX_UNHANDLED;
+opa_r15: FP_EX_UNHANDLED;
+opa_r16: FP_EX_UNHANDLED;
+opa_r17: FP_EX_UNHANDLED;
+opa_r18: FP_EX_OPA_SAVE (18);
+opa_r19: FP_EX_OPA_SAVE (19);
+opa_r20: FP_EX_OPA_SAVE (20);
+opa_r21: FP_EX_OPA_SAVE (21);
+opa_r22: FP_EX_OPA_SAVE (22);
+opa_r23: FP_EX_OPA_SAVE (23);
+opa_r24: FP_EX_OPA_SAVE (24);
+opa_r25: FP_EX_OPA_SAVE (25);
+opa_r26: FP_EX_OPA_SAVE (26);
+opa_r27: FP_EX_OPA_SAVE (27);
+opa_r28: FP_EX_OPA_SAVE (28);
+opa_r29: FP_EX_OPA_SAVE (29);
+opa_r30: FP_EX_OPA_SAVE (30);
+opa_r31: FP_EX_OPA_SAVE (31);
+
+fp_table_opb:
+opb_r0: FP_EX_OPB_SAVE (0);
+opb_r1: FP_EX_UNHANDLED;
+opb_r2: FP_EX_OPB_SAVE (2);
+opb_r3: FP_EX_OPB_SAVE_V (3);
+opb_r4: FP_EX_OPB_SAVE_V (4);
+opb_r5: FP_EX_OPB_SAVE_V (5);
+opb_r6: FP_EX_OPB_SAVE_V (6);
+opb_r7: FP_EX_OPB_SAVE (7);
+opb_r8: FP_EX_OPB_SAVE (8);
+opb_r9: FP_EX_OPB_SAVE (9);
+opb_r10: FP_EX_OPB_SAVE (10);
+opb_r11: FP_EX_OPB_SAVE (11);
+opb_r12: FP_EX_OPB_SAVE (12);
+opb_r13: FP_EX_OPB_SAVE (13);
+opb_r14: FP_EX_UNHANDLED;
+opb_r15: FP_EX_UNHANDLED;
+opb_r16: FP_EX_UNHANDLED;
+opb_r17: FP_EX_UNHANDLED;
+opb_r18: FP_EX_OPB_SAVE (18);
+opb_r19: FP_EX_OPB_SAVE (19);
+opb_r20: FP_EX_OPB_SAVE (20);
+opb_r21: FP_EX_OPB_SAVE (21);
+opb_r22: FP_EX_OPB_SAVE (22);
+opb_r23: FP_EX_OPB_SAVE (23);
+opb_r24: FP_EX_OPB_SAVE (24);
+opb_r25: FP_EX_OPB_SAVE (25);
+opb_r26: FP_EX_OPB_SAVE (26);
+opb_r27: FP_EX_OPB_SAVE (27);
+opb_r28: FP_EX_OPB_SAVE (28);
+opb_r29: FP_EX_OPB_SAVE (29);
+opb_r30: FP_EX_OPB_SAVE (30);
+opb_r31: FP_EX_OPB_SAVE (31);
+
+#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
+
+#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
+/* This is where we store the opA and opB of the last excepting FP instruction */
+.section .data
+.align 2
+.global mb_fpex_op_a
+.global mb_fpex_op_b
+mb_fpex_op_a:
+ .long 0
+mb_fpex_op_b:
+ .long 0
+#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
+
+#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
+/* This is where we store the register used to check which exception occurred */
+ .section .data
+ .align 2
+mb_sp_save_r3:
+ .long 0
+#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
+
+/* The exception vector table */
+.section .data
+.align 2
+.global MB_ExceptionVectorTable
+MB_ExceptionVectorTable:
+ .long XNullHandler
+ .long 0 /* -- FSL Exception -- */
+ .long XNullHandler
+ .long 1 /* -- Unaligned Access Exception -- */
+ .long XNullHandler
+ .long 2 /* -- Illegal Opcode Exception -- */
+ .long XNullHandler
+ .long 3 /* -- Instruction Bus Exception -- */
+ .long XNullHandler
+ .long 4 /* -- Data Bus Exception -- */
+ .long XNullHandler
+ .long 5 /* -- Div-by-0 Exception -- */
+ .long XNullHandler
+ .long 6 /* -- FPU Exception -- */
+ .long XNullHandler
+ .long 7 /* -- MMU Exceptions -- */
+
+#else /* Dummy exception handler, in case exceptions are not present in the processor */
+
+.global _hw_exception_handler
+.section .text
+.align 2
+.ent _hw_exception_handler
+_hw_exception_handler:
+ bri 0;
+.end _hw_exception_handler
+
+#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
--- /dev/null
+#include "xparameters.h"\r
+#include "xuartlite_l.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+char inbyte(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif \r
+\r
+char inbyte(void) {\r
+ return XUartLite_RecvByte(STDIN_BASEADDRESS);\r
+}\r
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef _MICROBLAZE_INTERFACE_H_
+#define _MICROBLAZE_INTERFACE_H_
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
+extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
+extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
+extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
+extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
+extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
+extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
+extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
+extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
+extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
+
+extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
+extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
+extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
+extern void microblaze_invalidate_icache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the icache */
+extern void microblaze_invalidate_dcache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the dcache */
+extern void microblaze_flush_dcache_range(u32 cacheaddr, u32 len); /* Flush a part of the dcache */
+extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
+extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
+extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
+extern void microblaze_flush_cache_ext_range(u32 cacheaddr,
+ u32 len); /* Flush cache ext range */
+extern void microblaze_invalidate_cache_ext_range(u32 cacheaddr,
+ u32 len); /* Invalidate cache ext range */
+
+/* Deprecated */
+extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated));
+extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated));
+extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated));
+extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated));
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+/* FSL Access Macros */
+
+/* Blocking Data Read and Write to FSL no. id */
+#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
+#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Non-blocking Data Read and Write to FSL no. id */
+#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
+#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Blocking Control Read and Write to FSL no. id */
+#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
+#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Non-blocking Control Read and Write to FSL no. id */
+#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
+#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Polling versions of FSL access macros. This makes the FSL access interruptible */
+#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ : "=d" (val) :: "r18")
+
+#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ :: "d" (val) : "r18")
+
+#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ : "=d" (val) :: "r18")
+
+#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
+ "addic\tr18,r0,0\n\t" \
+ "bnei\tr18,1b\n" \
+ :: "d" (val) : "r18")
+/* FSL valid and error check macros. */
+#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
+#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
+ "andi\t%0,%0,0x10" : "=d" (error))
+
+/* Pseudo assembler instructions */
+#define clz(v) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
+ ); \
+ _rval; \
+ })
+
+#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
+#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
+
+#define mb_swapb(v) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
+ ); \
+ _rval; \
+ })
+
+#define mb_swaph(v) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
+ ); \
+ _rval; \
+ })
+
+#define mfgpr(rn) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfmsr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rmsr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfear() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rear\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfeare() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfse\t%0,rear\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfesr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,resr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mffsr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rfsr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfpvr(rn) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfpvre(rn) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfbtr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rbtr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfedr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,redr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfpid() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rpid\n" : "=d"(_rval)\
+ ); \
+ _rval; \
+ })
+
+#define mfzpr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rzpr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mftlbx() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rtlbx\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mftlblo() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rtlblo\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mftlbhi() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rtlbhi\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfslr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rslr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mfshr() ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "mfs\t%0,rshr\n" : "=d"(_rval) \
+ ); \
+ _rval; \
+ })
+
+#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
+ "or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
+ ); \
+ })
+
+#define mtmsr(v) ({ __asm__ __volatile__ ( \
+ "mts\trmsr,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+
+#define mtfsr(v) ({ __asm__ __volatile__ ( \
+ "mts\trfsr,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mtpid(v) ({ __asm__ __volatile__ ( \
+ "mts\trpid,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mtzpr(v) ({ __asm__ __volatile__ ( \
+ "mts\trzpr,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mttlbx(v) ({ __asm__ __volatile__ ( \
+ "mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mttlblo(v) ({ __asm__ __volatile__ ( \
+ "mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mttlbhi(v) ({ __asm__ __volatile__ ( \
+ "mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mttlbsx(v) ({ __asm__ __volatile__ ( \
+ "mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mtslr(v) ({ __asm__ __volatile__ ( \
+ "mts\trslr,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define mtshr(v) ({ __asm__ __volatile__ ( \
+ "mts\trshr,%0\n\tnop\n" :: "d" (v) \
+ ); \
+ })
+
+#define lwx(address) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+ ); \
+ _rval; \
+ })
+
+#define lwr(address) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+ ); \
+ _rval; \
+ })
+
+
+#define lwea(lladdr) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
+ ); \
+ _rval; \
+ })
+
+#define lhur(address) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+ ); \
+ _rval; \
+ })
+
+#define lhuea(lladdr) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
+ ); \
+ _rval; \
+ })
+
+#define lbur(address) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+ ); \
+ _rval; \
+ })
+
+#define lbuea(lladdr) ({ u32 _rval; \
+ __asm__ __volatile__ ( \
+ "lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
+ ); \
+ _rval; \
+ })
+
+#define swx(address, data) ({ __asm__ __volatile__ ( \
+ "swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+ ); \
+ })
+
+#define swr(address, data) ({ __asm__ __volatile__ ( \
+ "swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+ ); \
+ })
+
+#define swea(lladdr, data) ({ __asm__ __volatile__ ( \
+ "swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
+ ); \
+ })
+
+#define shr(address, data) ({ __asm__ __volatile__ ( \
+ "shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+ ); \
+ })
+
+#define shea(lladdr, data) ({ __asm__ __volatile__ ( \
+ "shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
+ ); \
+ })
+
+#define sbr(address, data) ({ __asm__ __volatile__ ( \
+ "sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+ ); \
+ })
+
+#define sbea(lladdr, data) ({ __asm__ __volatile__ ( \
+ "sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
+ ); \
+ })
+
+#define microblaze_getfpex_operand_a() ({ \
+ extern u32 mb_fpex_op_a; \
+ mb_fpex_op_a; \
+ })
+
+#define microblaze_getfpex_operand_b() ({ \
+ extern u32 mb_fpex_op_b; \
+ mb_fpex_op_b; \
+ })
+
+/* Deprecated MicroBlaze FSL macros */
+#define microblaze_bread_datafsl(val, id) getfsl(val,id)
+#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
+#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
+#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
+#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
+#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
+#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
+#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _MICROBLAZE_INTERFACE_H_
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+* File : microblaze_disable_dcache.s
+* Date : 2002, March 20.
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Disable the L1 dcache on the microblaze.
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_disable_dcache
+ .ent microblaze_disable_dcache
+ .align 2
+microblaze_disable_dcache:
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+
+#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
+ addik r1, r1, -4
+ swi r15, r1, 0
+ brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
+ nop
+ lwi r15, r1, 0
+ addi r1, r1, 4
+#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
+ rtsd r15, 8
+ msrclr r0, 0x80
+
+#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
+
+ addik r1, r1, -4
+
+#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
+ swi r15, r1, 0
+ brlid r15, microblaze_flush_dcache
+ nop
+#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
+ mfs r11, rmsr
+ andi r11, r11, ~(0x80)
+ mts rmsr, r11
+
+#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
+ lwi r15, r1, 0
+#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
+
+ rtsd r15, 8
+ addi r1, r1, 4
+
+#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ .end microblaze_disable_dcache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* Disable exceptions on microblaze.
+*
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_disable_exceptions
+ .ent microblaze_disable_exceptions
+ .align 2
+microblaze_disable_exceptions:
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+ rtsd r15, 8
+ msrclr r0, 0x100
+#else
+ mfs r4, rmsr;
+ andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
+ mts rmsr, r4;
+ rtsd r15, 8;
+ nop;
+#endif
+.end microblaze_disable_exceptions
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* File : microblaze_disable_icache.s
+* Date : 2002, March 20.
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Disable L1 icache on the microblaze.
+*
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_disable_icache
+ .ent microblaze_disable_icache
+ .align 2
+microblaze_disable_icache:
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+ rtsd r15, 8
+ msrclr r0, 0x20
+#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ #Read the MSR register
+ mfs r8, rmsr
+ #Clear the icache enable bit
+ andi r8, r8, ~(0x20)
+ #Save the MSR register
+ mts rmsr, r8
+ #Return
+ rtsd r15, 8
+ nop
+#endif
+ .end microblaze_disable_icache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* File : microblaze_disable_interrupts.s
+* Date : 2002, March 20.
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Disable interrupts on the microblaze.
+*
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_disable_interrupts
+ .ent microblaze_disable_interrupts
+ .align 2
+microblaze_disable_interrupts:
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+ rtsd r15, 8
+ msrclr r0, 0x2
+#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ #Read the MSR register
+ mfs r12, rmsr
+ #Clear the interrupt enable bit
+ andi r12, r12, ~(0x2)
+ #Save the MSR register
+ mts rmsr, r12
+ #Return
+ rtsd r15, 8
+ nop
+#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ .end microblaze_disable_interrupts
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* File : microblaze_enable_dcache.s
+* Date : 2002, March 20.
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Enable L1 dcache on the microblaze.
+*
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_enable_dcache
+ .ent microblaze_enable_dcache
+ .align 2
+microblaze_enable_dcache:
+
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+ rtsd r15, 8
+ msrset r0, 0x80
+#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ #Read the MSR register
+ mfs r8, rmsr
+ #Set the interrupt enable bit
+ ori r8, r8, 0x80
+ #Save the MSR register
+ mts rmsr, r8
+ #Return
+ rtsd r15, 8
+ nop
+#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ .end microblaze_enable_dcache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* Enable exceptions on microblaze.
+*
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_enable_exceptions
+ .ent microblaze_enable_exceptions
+ .align 2
+microblaze_enable_exceptions:
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+ rtsd r15, 8;
+ msrset r0, 0x100
+#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ mfs r4, rmsr;
+ ori r4, r4, 0x100; /* Turn ON the EE bit */
+ mts rmsr, r4;
+ rtsd r15, 8;
+ nop;
+#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+.end microblaze_enable_exceptions
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* File : microblaze_enable_icache.s
+* Date : 2002, March 20.
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Enable icache on the microblaze.
+*
+*
+******************************************************************************/
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_enable_icache
+ .ent microblaze_enable_icache
+ .align 2
+microblaze_enable_icache:
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+ rtsd r15, 8
+ msrset r0, 0x20
+#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ #Read the MSR register
+ mfs r8, rmsr
+ #Set the interrupt enable bit
+ ori r8, r8, 0x20
+ #Save the MSR register
+ mts rmsr, r8
+ #Return
+ rtsd r15, 8
+ nop
+#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ .end microblaze_enable_icache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* File : microblaze_enable_interrupts.s
+* Date : 2002, March 20.
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Enable interrupts on the microblaze.
+*
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+ .text
+ .globl microblaze_enable_interrupts
+ .ent microblaze_enable_interrupts
+ .align 2
+microblaze_enable_interrupts:
+#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
+ rtsd r15, 8
+ msrset r0, 0x2
+#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ #Read the MSR register
+ mfs r12, rmsr
+ #Set the interrupt enable bit
+ ori r12, r12, 0x2
+ #Save the MSR register
+ mts rmsr, r12
+ #Return
+ rtsd r15, 8
+ nop
+#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
+ .end microblaze_enable_interrupts
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file microblaze_exception_handler.c
+*
+* This file contains exception handler registration routines for
+* the MicroBlaze processor.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Date Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 06/24/04 First release
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "microblaze_exceptions_i.h"
+#include "microblaze_exceptions_g.h"
+
+#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
+/****************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* Registers an exception handler for the MicroBlaze. The
+* argument provided in this call as the DataPtr is used as the argument
+* for the handler when it is called.
+*
+* @param ExceptionId is the id of the exception to register this handler
+* for.
+* @param Top level handler.
+* @param DataPtr is a reference to data that will be passed to the handler
+* when it gets called.
+* @return None.
+*
+* @note
+*
+* None.
+*
+****************************************************************************/
+void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr)
+{
+ MB_ExceptionVectorTable[ExceptionId].Handler = Handler;
+ MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr;
+}
+
+#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
--- /dev/null
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Exception Handling Header for MicroBlaze Processor\r
+*\r
+*******************************************************************/\r
+\r
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file microblaze_exceptions_i.h
+*
+* This header file contains defines for structures used by the microblaze
+* hardware exception handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Date Changes
+* ----- -------- -----------------------------------------------
+* 1.00a 06/24/04 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
+#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+ Xil_ExceptionHandler Handler;
+ void *CallBackRef;
+} MB_ExceptionVectorTableEntry;
+
+/* Exception IDs */
+#define XEXC_ID_FSL 0U
+#define XEXC_ID_UNALIGNED_ACCESS 1U
+#define XEXC_ID_ILLEGAL_OPCODE 2U
+#define XEXC_ID_M_AXI_I_EXCEPTION 3U
+#define XEXC_ID_IPLB_EXCEPTION 3U
+#define XEXC_ID_M_AXI_D_EXCEPTION 4U
+#define XEXC_ID_DPLB_EXCEPTION 4U
+#define XEXC_ID_DIV_BY_ZERO 5U
+#define XEXC_ID_FPU 6U
+#define XEXC_ID_STACK_VIOLATION 7U
+#define XEXC_ID_MMU 7U
+
+void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_flush_cache_ext()
+*
+* Flush the entire L2 Cache
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
+
+ .text
+ .globl microblaze_flush_cache_ext
+ .ent microblaze_flush_cache_ext
+ .align 2
+
+microblaze_flush_cache_ext:
+
+#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
+ addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
+
+ addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+
+Loop_start:
+ wdc.ext.flush r5, r6
+ bgtid r6,Loop_start
+ addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+#endif
+ rtsd r15, 8
+ nop
+ .end microblaze_flush_cache_ext
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
+*
+*Flush a L2 Cache range
+*
+*Parameters:
+* 'cacheaddr' - address in the L2 cache where the flush begins
+* 'len ' - length (in bytes) worth of L2 cache to be flushed
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
+
+ .text
+ .globl microblaze_flush_cache_ext_range
+ .ent microblaze_flush_cache_ext_range
+ .align 2
+
+microblaze_flush_cache_ext_range:
+#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
+ beqi r6, Loop_done
+
+ addik r6, r6, -1
+ add r6, r5, r6
+
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+ andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+
+ rsubk r6, r5, r6
+Loop_start:
+ wdc.ext.flush r5, r6
+ bneid r6, Loop_start
+ addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+
+Loop_done:
+#endif
+ rtsd r15, 8
+ nop
+
+ .end microblaze_flush_cache_ext_range
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+*
+* microblaze_flush_dcache()
+*
+* Flush the L1 DCache
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
+#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
+#endif
+
+ .text
+ .globl microblaze_flush_dcache
+ .ent microblaze_flush_dcache
+ .align 2
+
+microblaze_flush_dcache:
+ addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
+ addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
+
+L_start:
+ wdc.flush r5, r0 /* Flush the Cache */
+
+ cmpu r18, r5, r6 /* Are we at the end? */
+ blei r18, L_done
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+
+L_done:
+ rtsd r15, 8 /* Return */
+ nop
+ .end microblaze_flush_dcache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len)
+*
+* Flush a L1 DCache range
+*
+* Parameters:
+* 'cacheaddr' - address in the Dcache where the flush begins
+* 'len ' - length (in bytes) worth of Dcache to be flushed
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
+#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#define MB_HAS_WRITEBACK_SET 0
+#else
+#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#endif
+
+ .text
+ .globl microblaze_flush_dcache_range
+ .ent microblaze_flush_dcache_range
+ .align 2
+
+microblaze_flush_dcache_range:
+
+#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
+ mfs r9, rmsr
+ andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
+ mts rmsr, r10
+#endif
+
+ beqi r6, L_done /* Skip loop if size is zero */
+
+ add r6, r5, r6 /* Compute end address */
+ addik r6, r6, -1
+
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
+ andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
+
+#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
+
+L_start:
+ cmpu r18, r5, r6 /* Are we at the end? */
+ blti r18, L_done
+
+ wdc r5, r0 /* Invalidate the cache line */
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+#else
+ rsubk r6, r5, r6
+ /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
+L_start:
+ wdc.flush r5, r6 /* Flush the cache line */
+ bneid r6, L_start
+ addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
+
+#endif
+
+L_done:
+ rtsd r15, 8
+#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
+ mts rmsr, r9
+#else
+ nop
+#endif
+ .end microblaze_flush_dcache_range
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len)
+*
+* Invalidate dcache on the microblaze
+*
+* Parameters:
+* 'cache_start' - address in the Dcache where invalidation begins
+* 'cache_len' - length (in bytes) worth of Dcache to be invalidated
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
+#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
+#endif
+
+ .text
+ .globl microblaze_init_dcache_range
+ .ent microblaze_init_dcache_range
+ .align 2
+
+microblaze_init_dcache_range:
+
+ mfs r9, rmsr /* Disable Dcache and interrupts before invalidating */
+ andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
+ mts rmsr, r10
+
+ andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
+
+ add r6, r5, r6 /* Compute end */
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
+
+L_start:
+ wdc r5, r0 /* Invalidate the Cache (delay slot) */
+
+ cmpu r18, r5, r6 /* Are we at the end ? */
+ blei r18, L_done
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+
+L_done:
+ rtsd r15, 8 /* Return */
+ mts rmsr, r9
+ .end microblaze_init_dcache_range
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+*
+* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len)
+*
+* Invalidate icache on the microblaze
+*
+* Parameters:
+* 'cache_start' - address in the Icache where invalidation begins
+* 'cache_len' - length (in bytes) worth of Icache to be invalidated
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
+#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
+#endif
+
+ .text
+ .globl microblaze_init_icache_range
+ .ent microblaze_init_icache_range
+ .align 2
+
+microblaze_init_icache_range:
+
+ mfs r9, rmsr /* Disable Icache and interrupts before invalidating */
+ andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
+ mts rmsr, r10
+
+ andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
+
+ add r6, r5, r6 /* Compute end */
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
+
+L_start:
+ wic r5, r0 /* Invalidate the Cache (delay slot) */
+
+ cmpu r18, r5, r6 /* Are we at the end ? */
+ blei r18, L_done
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+
+L_done:
+ rtsd r15, 8 /* Return */
+ mts rmsr, r9
+ .end microblaze_init_icache_range
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file microblaze_interrupt_handler.c
+*
+* This file contains the standard interrupt handler for the MicroBlaze processor.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Date Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 10/03/03 First release
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "microblaze_interrupts_i.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void __interrupt_handler (void) __attribute__ ((interrupt_handler));
+void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr);
+
+/************************** Variable Definitions *****************************/
+
+extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
+/*****************************************************************************/
+/**
+*
+* This function is the standard interrupt handler used by the MicroBlaze processor.
+* It saves all volatile registers, calls the users top level interrupt handler.
+* When this returns, it restores all registers, and returns using a rtid instruction.
+*
+* @param
+*
+* None
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void __interrupt_handler(void)
+{
+ /* The compiler saves all volatiles and the MSR */
+ (void)MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
+ /* The compiler restores all volatiles and MSR, and returns from interrupt */
+}
+
+/****************************************************************************/
+/*****************************************************************************/
+/**
+*
+* Registers a top-level interrupt handler for the MicroBlaze. The
+* argument provided in this call as the DataPtr is used as the argument
+* for the handler when it is called.
+*
+* @param Top level handler.
+* @param DataPtr is a reference to data that will be passed to the handler
+* when it gets called.
+
+* @return None.
+*
+* @note
+*
+* None.
+*
+****************************************************************************/
+void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
+{
+ MB_InterruptVectorTable.Handler = Handler;
+ MB_InterruptVectorTable.CallBackRef = DataPtr;
+}
--- /dev/null
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Interrupt Handler Table for MicroBlaze Processor\r
+*\r
+*******************************************************************/\r
+\r
+#include "microblaze_interrupts_i.h"\r
+#include "xparameters.h"\r
+\r
+\r
+extern void XNullHandler (void *);\r
+\r
+/*\r
+* The interrupt handler table for microblaze processor\r
+*/\r
+\r
+MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =\r
+{\r
+{ XNullHandler,\r
+ (void*) XNULL}\r
+};\r
+\r
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file microblaze_interrupts_i.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* High-level driver functions are defined in xintc.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Date Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 10/03/03 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
+#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+ XInterruptHandler Handler;
+ void *CallBackRef;
+} MB_InterruptVectorTableEntry;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_invalidate_cache_ext()
+*
+*Invalidate the entire L2 Cache
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
+
+ .text
+ .globl microblaze_invalidate_cache_ext
+ .ent microblaze_invalidate_cache_ext
+ .align 2
+
+microblaze_invalidate_cache_ext:
+
+#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
+ addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
+
+ addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+
+Loop_start:
+ wdc.ext.clear r5, r6
+ bgtid r6,Loop_start
+ addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+#endif
+ rtsd r15, 8
+ nop
+
+ .end microblaze_invalidate_cache_ext
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
+*
+*Invalidate an L2 cache range
+*
+*Parameters:
+* 'cacheaddr' - address in the L2 cache where invalidation begins
+* 'len ' - length (in bytes) worth of Dcache to be invalidated
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
+
+ .text
+ .globl microblaze_invalidate_cache_ext_range
+ .ent microblaze_invalidate_cache_ext_range
+ .align 2
+
+microblaze_invalidate_cache_ext_range:
+#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
+ beqi r6, Loop_done
+
+ add r6, r5, r6
+ addik r6, r6, -1
+
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+ andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+
+ rsubk r6, r5, r6
+
+Loop_start:
+ wdc.ext.clear r5, r6
+ bneid r6, Loop_start
+ addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
+
+Loop_done:
+#endif
+ rtsd r15, 8
+ nop
+
+ .end microblaze_invalidate_cache_ext_range
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_invalidate_dcache()
+*
+* Invalidate the entire L1 DCache
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
+#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#endif
+
+ .text
+ .globl microblaze_invalidate_dcache
+ .ent microblaze_invalidate_dcache
+ .align 2
+
+microblaze_invalidate_dcache:
+
+#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
+ mfs r9, rmsr
+ andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
+ mts rmsr, r10
+#endif
+ addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
+ addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
+
+L_start:
+ wdc r5, r0 /* Invalidate the Cache */
+
+ cmpu r18, r5, r6 /* Are we at the end? */
+ blei r18, L_done
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+
+L_done:
+ rtsd r15, 8 /* Return */
+#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
+ mts rmsr, r9
+#else
+ nop
+#endif
+
+ .end microblaze_invalidate_dcache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+*
+* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
+*
+* Invalidate a Dcache range
+*
+* Parameters:
+* 'cacheaddr' - address in the Dcache where invalidation begins
+* 'len ' - length (in bytes) worth of Dcache to be invalidated
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
+#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#define MB_HAS_WRITEBACK_SET 0
+#else
+#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#endif
+
+ .text
+ .globl microblaze_invalidate_dcache_range
+ .ent microblaze_invalidate_dcache_range
+ .align 2
+
+microblaze_invalidate_dcache_range:
+
+
+#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
+ mfs r9, rmsr
+ andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
+ mts rmsr, r10
+#endif
+
+ beqi r6, L_done /* Skip loop if size is zero */
+
+ add r6, r5, r6 /* Compute end address */
+ addik r6, r6, -1
+
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
+ andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
+
+#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
+
+L_start:
+ cmpu r18, r5, r6 /* Are we at the end? */
+ blti r18, L_done
+
+ wdc r5, r0
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+#else
+
+ rsubk r6, r5, r6
+ /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
+L_start:
+ wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
+ bneid r6, L_start
+ addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
+
+#endif
+
+L_done:
+ rtsd r15, 8
+#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
+ mts rmsr, r9
+#else
+ nop
+#endif
+ .end microblaze_invalidate_dcache_range
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+*
+* microblaze_invalidate_icache()
+*
+* Invalidate the entire ICache
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
+#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#endif
+
+ .text
+ .globl microblaze_invalidate_icache
+ .ent microblaze_invalidate_icache
+ .align 2
+
+microblaze_invalidate_icache:
+
+#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
+ mfs r9, rmsr
+ andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
+ mts rmsr, r10
+#endif
+ addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
+ addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
+L_start:
+ wic r5, r0 /* Invalidate the Cache */
+
+ cmpu r18, r5, r6 /* Are we at the end? */
+ blei r18, L_done
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+
+L_done:
+ rtsd r15, 8 /* Return */
+
+#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
+ mts rmsr, r9
+#else
+ nop
+#endif
+ .end microblaze_invalidate_icache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+*
+* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
+*
+* Invalidate an ICache range
+*
+* Parameters:
+* 'cacheaddr' - address in the Icache where invalidation begins
+* 'len' - length (in bytes) worth of Icache to be invalidated
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
+#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
+
+#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
+#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#endif
+
+ .text
+ .globl microblaze_invalidate_icache_range
+ .ent microblaze_invalidate_icache_range
+ .align 2
+
+microblaze_invalidate_icache_range:
+
+#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
+ mfs r9, rmsr
+ andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
+ mts rmsr, r10
+#endif
+
+ beqi r6, L_done /* Skip loop if size is zero */
+
+ add r6, r5, r6 /* Compute end address */
+ addik r6, r6, -1
+
+ andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
+ andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
+
+L_start:
+ cmpu r18, r5, r6 /* Are we at the end? */
+ blti r18, L_done
+
+ wic r5, r0 /* Invalidate the cache line */
+
+ brid L_start /* Branch to the beginning of the loop */
+ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
+
+L_done:
+ rtsd r15, 8 /* Return */
+#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
+ mts rmsr, r9
+#else
+ nop
+#endif
+ .end microblaze_invalidate_icache_range
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* microblaze_scrub ()
+*
+* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
+* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
+* of an uncorrectable error when fault tolerance support is enabled.
+*
+* This routine assumes that the processor is in privileged mode when it is
+* called, if the MMU is enabled.
+*
+* Call this routine regularly from a timer interrupt.
+*
+* Parameters:
+* None
+*
+*
+*******************************************************************************/
+
+#include "xparameters.h"
+
+/* Define if fault tolerance is used */
+#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
+ #if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
+ #define FAULT_TOLERANT
+ #endif
+#endif
+
+/* Define if LMB is used and can be scrubbed */
+#if defined(XPAR_MICROBLAZE_D_LMB) && \
+ defined(XPAR_DLMB_CNTLR_BASEADDR) && \
+ defined(XPAR_DLMB_CNTLR_HIGHADDR)
+ #if XPAR_MICROBLAZE_D_LMB == 1
+ #define HAS_SCRUBBABLE_LMB
+ #define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
+ #endif
+#endif
+
+/* Set default cache line lengths */
+#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
+ #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
+#endif
+
+#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
+ #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
+#endif
+
+/* Define if internal Data Cache BRAMs are used */
+#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
+ #if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
+ #define HAS_BRAM_DCACHE
+ #define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
+ #define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
+ #endif
+#endif
+
+/* Define if internal Instruction Cache BRAMs are used */
+#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
+ #if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
+ #define HAS_BRAM_ICACHE
+ #define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
+ #define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
+ #endif
+#endif
+
+/* Define if internal MMU UTLB BRAM is used */
+#ifdef XPAR_MICROBLAZE_USE_MMU
+ #if XPAR_MICROBLAZE_USE_MMU > 1
+ #define HAS_BRAM_MMU_UTLB
+ #endif
+#endif
+
+/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
+#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
+ defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
+ #if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
+ #if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
+ XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
+ #define HAS_BRAM_BRANCH_TARGET_CACHE
+ #ifdef HAS_BRAM_DCACHE
+ #define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
+ #else
+ #define BTC_MASK_D 256
+ #endif
+ #ifdef HAS_BRAM_ICACHE
+ #define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
+ #else
+ #define BTC_MASK_I 256
+ #endif
+ #if BTC_MASK_D > BTC_MASK_I
+ #define BTC_MASK BTC_MASK_D
+ #else
+ #define BTC_MASK BTC_MASK_I
+ #endif
+ #endif
+ #endif
+#endif
+
+/* Define index offsets to persistent data used by this routine */
+#define DLMB_INDEX_OFFSET 0
+#define DCACHE_INDEX_OFFSET 4
+#define ICACHE_INDEX_OFFSET 8
+#define MMU_INDEX_OFFSET 12
+#define BTC_CALL_COUNT_OFFSET 16
+
+ .text
+ .globl microblaze_scrub
+ .ent microblaze_scrub
+ .align 2
+
+microblaze_scrub:
+#ifdef FAULT_TOLERANT
+ la r6, r0, L_persistent_data /* Get pointer to data */
+
+#ifdef HAS_SCRUBBABLE_LMB
+L_dlmb:
+ lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
+ lw r7, r5, r0 /* Load and store */
+ sw r7, r5, r0
+ addik r5, r5, 4 /* Increment and save dlmb index */
+ andi r5, r5, DLMB_MASK
+ swi r5, r6, DLMB_INDEX_OFFSET
+#endif /* HAS_SCRUBBABLE_LMB */
+
+#ifdef HAS_BRAM_DCACHE
+L_dcache:
+ lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
+ wdc r5, r0 /* Invalidate data cache line */
+ addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
+ andi r5, r5, DCACHE_MASK
+ swi r5, r6, DCACHE_INDEX_OFFSET
+#endif /* HAS_BRAM_DCACHE */
+
+#ifdef HAS_BRAM_ICACHE
+L_icache:
+ lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
+ wic r5, r0 /* Invalidate data cache line */
+ addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
+ andi r5, r5, ICACHE_MASK
+ swi r5, r6, ICACHE_INDEX_OFFSET
+#endif /* HAS_BRAM_ICACHE */
+
+#ifdef HAS_BRAM_MMU_UTLB
+L_mmu:
+ lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
+ mts rtlbx, r5 /* Access next entry in UTLB */
+ mts rtlbhi, r0 /* Clear the UTLB entry */
+
+ addik r5, r5, 1 /* Increment and save entry index */
+ andi r5, r5, 0x3F
+ swi r5, r6, MMU_INDEX_OFFSET
+#endif /* HAS_BRAM_MMU_UTLB */
+
+#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
+L_btc:
+ lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
+ addik r5, r5, 1 /* Increment and save call count */
+ andi r5, r5, BTC_MASK
+ swi r5, r6, BTC_CALL_COUNT_OFFSET
+
+ bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
+ bri 4 /* Clear branch target cache */
+L_skip_btc_scrub:
+#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
+
+#endif /* FAULT_TOLERANT */
+L_done:
+ rtsd r15, 8 /* Return */
+ nop
+ .end microblaze_scrub
+
+ /* Persistent data used by this routine */
+ .data
+ .align 2
+L_persistent_data:
+ .long 0 /* dlmb index */
+ .long 0 /* dcache index */
+ .long 0 /* icache index */
+ .long 0 /* mmu entry index */
+ .long 0 /* btc call count */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file microblaze_sleep.c
+*
+* Contains implementation of microblaze sleep function.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.1 hk 04/18/14 Add sleep function.
+*
+* </pre>
+*
+* @note
+*
+* This file may contain architecture-dependent code.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "microblaze_sleep.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+
+/*****************************************************************************/
+/**
+*
+* Provides delay for requested duration.
+*
+* @param Delay time in milliseconds.
+*
+* @return None.
+*
+* @note Instruction cache should be enabled for this to work.
+*
+******************************************************************************/
+void MB_Sleep(u32 MilliSeconds)
+{
+ if (((mfmsr() & 0x20U) == 0U)) {
+ /*
+ * Instruction cache not enabled.
+ * Delay will be much higher than expected.
+ */
+ }
+
+ asm volatile ("\n"
+ "1: \n\t"
+ "addik r7, r0, %0 \n\t"
+ "2: \n\t"
+ "addik r7, r7, -1 \n\t"
+ "bneid r7, 2b \n\t"
+ "or r0, r0, r0 \n\t"
+ "bneid %1, 1b \n\t"
+ "addik %1, %1, -1 \n\t"
+ :: "i"(ITERS_PER_MSEC), "d" (MilliSeconds));
+
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file microblaze_sleep.h
+*
+* Contains microblaze sleep function API.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.1 asa 04/18/14 Add sleep function - first release.
+*
+* </pre>
+*
+* @note
+*
+* This file may contain architecture-dependent items.
+*
+******************************************************************************/
+
+#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */
+#define MICROBLAZE_SLEEP_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "mb_interface.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ITERS_PER_MSEC ((XPAR_CPU_CORE_CLOCK_FREQ_HZ / 1000) / 6)
+
+/************************** Function Prototypes ******************************/
+
+void MB_Sleep(u32 MilliSeconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+*
+* File : microblaze_update_dcache.s
+* Date : 2003, September 24
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Update dcache on the microblaze.
+* Takes in three parameters
+* r5 : Cache Tag Line
+* r6 : Cache Data
+* r7 : Lock/Valid information
+* Bit 30 is Lock [ 1 indicates locked ]
+* Bit 31 is Valid [ 1 indicates valid ]
+*
+* --------------------------------------------------------------
+* | Lock | Valid | Effect
+* --------------------------------------------------------------
+* | 0 | 0 | Invalidate Cache
+* | 0 | 1 | Valid, but unlocked cacheline
+* | 1 | 0 | Invalidate Cache, No effect of lock
+* | 1 | 1 | Valid cache. Locked to a
+* | | | particular addrees
+* --------------------------------------------------------------
+*
+*
+**********************************************************************************/
+#include "xparameters.h"
+
+#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
+#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
+#endif
+
+ .text
+ .globl microblaze_update_dcache
+ .ent microblaze_update_dcache
+ .align 2
+microblaze_update_dcache:
+
+#if XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1
+
+/* Read the MSR register into a temp register */
+ mfs r18, rmsr
+
+/* Clear the dcache enable bit to disable the cache
+ Register r10,r18 are volatile registers and hence do not need to be saved before use */
+ andi r10, r18, ~128
+ mts rmsr, r10
+
+/* Update the lock and valid info */
+ andi r5, r5, 0xfffffffc
+ or r5, r5, r7
+
+/* Update dcache */
+ wdc r5, r6
+
+/* Return */
+ rtsd r15, 8
+ mts rmsr, r18
+
+#else
+
+ /* The only valid usage of this routine for larger cache line lengths is to invalidate a data cache line
+ So call microblaze_init_dcache_range appropriately to do the job */
+
+ brid microblaze_init_dcache_range
+ addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
+
+ /* We don't have a return instruction here. This is tail call optimization :) */
+
+#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */
+
+ .end microblaze_update_dcache
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* File : microblaze_update_icache.s
+* Date : 2003, September 24
+* Company: Xilinx
+* Group : Emerging Software Technologies
+*
+* Summary:
+* Update icache on the microblaze.
+* Takes in three parameters
+* r5 : Cache Tag Line
+* r6 : Cache Data
+* r7 : Lock/Valid information
+* Bit 30 is Lock [ 1 indicates locked ]
+* Bit 31 is Valid [ 1 indicates valid ]
+*
+* --------------------------------------------------------------
+* | Lock | Valid | Effect
+* --------------------------------------------------------------
+* | 0 | 0 | Invalidate Cache
+* | 0 | 1 | Valid, but unlocked cacheline
+* | 1 | 0 | Invalidate Cache, No effect of lock
+* | 1 | 1 | Valid cache. Locked to a
+* | | | particular addrees
+* --------------------------------------------------------------
+*
+*
+**********************************************************************************/
+#include "xparameters.h"
+
+#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
+#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
+#endif
+
+ .text
+ .globl microblaze_update_icache
+ .ent microblaze_update_icache
+ .align 2
+microblaze_update_icache:
+
+#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
+
+/* Read the MSR register into a temp register */
+ mfs r18, rmsr
+
+/* Clear the icache enable bit to disable the cache
+ Register r10,r18 are volatile registers and hence do not need to be saved before use */
+ andi r10, r18, ~32
+ mts rmsr, r10
+
+/* Update the lock and valid info */
+ andi r5, r5, 0xfffffffc
+ or r5, r5, r7
+
+/* Update icache */
+ wic r5, r6
+
+/* Return */
+ rtsd r15, 8
+ mts rmsr, r18
+
+#else
+
+ /* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line
+ So call microblaze_init_icache_range appropriately to do the job */
+
+ brid microblaze_init_icache_range
+ addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
+
+ /* We don't have a return instruction here. This is tail call optimization :) */
+
+#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
+
+ .end microblaze_update_icache
--- /dev/null
+#include "xparameters.h"\r
+#include "xuartlite_l.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+void outbyte(char c); \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif \r
+\r
+void outbyte(char c) {\r
+ XUartLite_SendByte(STDOUT_BASEADDRESS, c);\r
+}\r
--- /dev/null
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+ while (*ptr != (char8)0) {
+ outbyte (*ptr);
+ *ptr++;
+ }
+#else
+(void)ptr;
+#endif
+}
--- /dev/null
+###############################################################################
+#
+# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# Makefile for profiler
+#
+#######################################################################
+
+# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
+include ../config.make
+
+AS=mb-as
+COMPILER = mb-gcc
+ARCHIVER = mb-ar
+CP = cp
+COMPILER_FLAGS=-O2
+EXTRA_COMPILER_FLAGS=
+LIB = libxil.a
+DUMMYLIB = libxilprofile.a
+
+CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
+
+RELEASEDIR = ../../../../lib
+INCLUDEDIR = ../../../../include
+INCLUDES = -I./. -I${INCLUDEDIR}
+
+OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
+DUMMYOBJ = dummy.o
+INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
+
+libs : reallibs dummylibs
+
+reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
+ $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
+
+dummylibs : $(DUMMYOBJ)
+ $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
+
+%.o:%.c
+ $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+%.o:%.S
+ $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+include:
+ $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+void _profile_clean( void );
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+ Xil_ExceptionDisable();
+ disable_timer();
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_init.c:
+* Initialize the Profiling Structures.
+*
+******************************************************************************/
+
+#include "profile.h"
+
+/* XMD Initializes the following Global Variables Value during Program
+ * Download with appropriate values. */
+
+#ifdef PROC_MICROBLAZE
+
+extern s32 microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern s32 powerpc405_init(void);
+
+#else
+
+extern s32 cortexa9_init(void);
+
+#endif
+
+s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
+
+u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
+u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
+u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
+u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
+
+/* Structure for Storing the Profiling Data */
+struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
+s32 n_gmon_sections = 1;
+
+/* This is the initialization code, which is called from the crtinit. */
+
+void _profile_init( void )
+{
+/* print("Gmon Init called....\r\n") */
+/* putnum(n_gmon_sections) , print("\r\n") */
+/* if( _gmonparam == 0xffffffff ) */
+/* printf("Gmonparam is NULL !!\r\n") */
+/* for( i = 0, i < n_gmon_sections, i++ )[ */
+/* putnum( _gmonparam[i].lowpc) , print("\t") */
+/* putnum( _gmonparam[i].highpc) , print("\r\n") */
+/* putnum( _gmonparam[i].textsize ), print("\r\n") */
+/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
+/* ] */
+
+#ifdef PROC_MICROBLAZE
+ (void)microblaze_init();
+#elif defined PROC_PPC
+ powerpc405_init();
+#else
+ (void)cortexa9_init();
+#endif
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.c:
+* Timer related functions
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+/* extern u32 timer_clk_ticks, */
+
+#ifdef PROC_PPC405
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_pit_init( void );
+#endif
+s32 powerpc405_init()
+#endif /* PROC_CORTEXA9 */
+
+#ifdef PROC_PPC440
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void );
+#endif
+s32 powerpc405_init(void);
+#endif /* PROC_PPC440 */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void );
+#endif
+
+#ifdef PROC_MICROBLAZE
+s32 microblaze_init(void);
+#endif /* PROC_MICROBLAZE */
+
+#ifdef PROC_CORTEXA9
+s32 scu_timer_init( void );
+s32 cortexa9_init(void);
+#endif /* PROC_CORTEXA9 */
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC405
+
+
+/*--------------------------------------------------------------------
+* PowerPC PIT Timer Init.
+* Defined only if PIT Timer is used for Profiling
+*
+*-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set PIT Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_PITSetInterval( timer_clk_ticks ) ;
+ XTime_PITEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------
+* PowerPC Timer Initialization functions.
+* For PowerPC, PIT and opb_timer can be used for Profiling. This
+* is selected by the user in standalone BSP
+*
+*-------------------------------------------------------------------- */
+s32 powerpc405_init()
+{
+ Xil_ExceptionInit() ;
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+ * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC */
+
+
+
+/*--------------------------------------------------------------------
+ * PowerPC440 Target - Timer related functions
+ * -------------------------------------------------------------------- */
+#ifdef PROC_PPC440
+
+
+/*--------------------------------------------------------------------
+ * PowerPC DEC Timer Init.
+ * Defined only if DEC Timer is used for Profiling
+ *
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set DEC Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_DECSetInterval( timer_clk_ticks ) ;
+ XTime_DECEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Timer Initialization functions.
+ * For PowerPC, DEC and opb_timer can be used for Profiling. This
+ * is selected by the user in standalone BSP
+ *
+ *-------------------------------------------------------------------- */
+s32 powerpc405_init(void)
+{
+ Xil_ExceptionInit();
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+ * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC440 */
+
+/* --------------------------------------------------------------------
+ * opb_timer Initialization for PowerPC and MicroBlaze. This function
+ * is not needed if DEC timer is used in PowerPC
+ *
+ *-------------------------------------------------------------------- */
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting */
+ XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
+
+ /* reset the timers, and clear interrupts */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
+ (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
+
+ /* start the timers */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
+ | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for MicroBlaze Target.
+ * For MicroBlaze, opb_timer is used. The opb_timer can be directly
+ * connected to MicroBlaze or connected through Interrupt Controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 microblaze_init(void)
+{
+ /* Register profile_intr_handler
+ * 1. If timer is connected to Interrupt Controller, register the handler
+ * to Interrupt Controllers vector table.
+ * 2. If timer is directly connected to MicroBlaze, register the handler
+ * as Interrupt handler */
+ Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL) ;
+#endif
+
+ /* Initialize the timer with Timer Ticks */
+ (void)opb_timer_init() ;
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+ XIntc_MasterEnable((u32)INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+#endif
+
+#endif
+
+ Xil_ExceptionEnable();
+
+ return 0;
+
+}
+
+#endif /* PROC_MICROBLAZE */
+
+
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for Cortex A9 Target.
+ * The scu private timer is connected to the Scu GIC controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 scu_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting
+ * scu timer runs at half the cpu clock */
+ XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
+
+ /* clear any pending interrupts */
+ XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
+
+ /* enable interrupts, auto-reload mode and start the timer */
+ XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ return 0;
+}
+
+s32 cortexa9_init(void)
+{
+
+ Xil_ExceptionInit();
+
+ XScuGic_DeviceInitialize(0);
+
+ /*
+ * Connect the interrupt controller interrupt handler to the hardware
+ * interrupt handling logic in the processor.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+ NULL);
+
+ /*
+ * Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device.
+ */
+ XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+ PROFILE_TIMER_INTR_ID,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL);
+
+ /*
+ * Enable the interrupt for scu timer.
+ */
+ XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+ /*
+ * Enable interrupts in the Processor.
+ */
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+ /*
+ * Initialize the timer with Timer Ticks
+ */
+ (void)scu_timer_init() ;
+
+ Xil_ExceptionEnable();
+
+ return 0;
+}
+
+#endif /* PROC_CORTEXA9 */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+* Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+# define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+# define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+ ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
+ (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
+ ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+ (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
+ ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ * 1. XTime_PITDisableInterrupt() ;
+ * 2. Store the remaining timer clk tick
+ * 3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
+ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
+ mtspr(XREG_SPR_PIT, 0); \
+ }
+#else
+#define disable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ * 1. Load the remaining timer clk ticks
+ * 2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
+ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+ }
+#else
+#define enable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 1. Load the timer clk ticks
+ * 2. Enable AutoReload and Interrupt
+ * 3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack() \
+ { \
+ u32 val; \
+ mtspr(XREG_SPR_PIT, timer_clk_ticks); \
+ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+ }
+#else
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
+ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
+ }
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(Addr); \
+ tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+ u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+ OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ OutAddr += (u32)XTC_TCSR_OFFSET; \
+ ProfIo_Out32(OutAddr, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = (u32)ProfIo_In32(Addr); \
+ tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
+ ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
+ }
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+{ \
+ Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+ (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+ .globl dummy_f
+
+#ifdef PROC_MICROBLAZE
+ .text
+ .align 2
+ .ent dummy_f
+
+dummy_f:
+ nop
+
+ .end dummy_f
+#endif
+
+#ifdef PROC_PPC
+ .section .text
+ .align 2
+ .type dummy_f@function
+
+dummy_f:
+ b dummy_f
+
+#endif
+
+#ifdef PROC_CORTEXA9
+ .section .text
+ .align 2
+ .type dummy_f, %function
+
+dummy_f:
+ b dummy_f
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char byte;
+typedef short half;
+typedef int word;
+typedef unsigned char ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int uword;
+typedef ubyte boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef PROFILE_H
+#define PROFILE_H 1
+
+#include <stdio.h>
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define HISTCOUNTER u16
+
+struct tostruct {
+ u32 selfpc;
+ s32 count;
+ s16 link;
+ u16 pad;
+};
+
+struct fromstruct {
+ u32 frompc ;
+ s16 link ;
+ u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y) (((x)/(y))*(y))
+#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+ s32 state;
+
+ /* Histogram Information */
+ u16 *kcount; /* No. of bins in histogram */
+ u32 kcountsize; /* Histogram samples */
+
+ /* Call-graph Information */
+ struct fromstruct *froms;
+ u32 fromssize;
+ struct tostruct *tos;
+ u32 tossize;
+
+ /* Initialization I/Ps */
+ u32 lowpc;
+ u32 highpc;
+ u32 textsize;
+ /* u32 cg_froms, */
+ /* u32 cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define GMON_PROF_ON 0
+#define GMON_PROF_BUSY 1
+#define GMON_PROF_ERROR 2
+#define GMON_PROF_OFF 3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define GPROF_STATE 0 /* int: profiling enabling variable */
+#define GPROF_COUNT 1 /* struct: profile tick count buffer */
+#define GPROF_FROMS 2 /* struct: from location hash bucket */
+#define GPROF_TOS 3 /* struct: destination/count structure */
+#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PROFILE_H */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount fucntion is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
+#endif
+
+/*extern struct gmonparam *_gmonparam, */
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
+{
+ s32 index = 0 ;
+
+ while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == cgtable_size ) {
+ return -1 ;
+ } else {
+ return index ;
+ }
+}
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
+{
+ s32 index = 0 ;
+ s32 Status;
+
+ while( (index < fromssize) && (froms[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == fromssize ) {
+ Status = -1 ;
+ } else {
+ Status = index ;
+ }
+ return Status;
+}
+#endif /* PROFILE_NO_FUNCPTR */
+
+
+void mcount( u32 frompc, u32 selfpc )
+{
+ register struct gmonparam *p = NULL;
+ register s32 toindex, fromindex;
+ s32 j;
+
+ disable_timer();
+
+ /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
+ * check that frompcindex is a reasonable pc value.
+ * for example: signal catchers get called from the stack,
+ * not from text space. too bad.
+ */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+ p = &_gmonparam[j];
+ break;
+ }
+ }
+ if( j == n_gmon_sections ) {
+ goto done;
+ }
+
+#ifdef PROFILE_NO_FUNCPTR
+ fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = p->cgtable_size ;
+ p->cgtable_size++ ;
+ p->cgtable[fromindex].frompc = frompc ;
+ p->cgtable[fromindex].selfpc = selfpc ;
+ p->cgtable[fromindex].count = 1 ;
+ goto done ;
+ }
+ p->cgtable[fromindex].count++ ;
+#else
+ fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = (s32)p->fromssize ;
+ p->fromssize++ ;
+ /*if( fromindex >= N_FROMS ) {
+ * print("Error : From PC table overflow\r\n")
+ * goto overflow
+ *}*/
+ p->froms[fromindex].frompc = frompc ;
+ p->froms[fromindex].link = -1 ;
+ }else {
+ toindex = ((s32)(p->froms[fromindex].link));
+ while(toindex != -1) {
+ toindex = (((s32)p->tossize) - toindex)-1 ;
+ if( p->tos[toindex].selfpc == selfpc ) {
+ p->tos[toindex].count++ ;
+ goto done ;
+ }
+ toindex = ((s32)(p->tos[toindex].link)) ;
+ }
+ }
+
+ /*if( toindex == -1 ) { */
+ p->tos-- ;
+ p->tossize++ ;
+ /* if( toindex >= N_TOS ) {
+ * print("Error : To PC table overflow\r\n")
+ * goto overflow
+ *} */
+ p->tos[0].selfpc = selfpc ;
+ p->tos[0].count = 1 ;
+ p->tos[0].link = p->froms[fromindex].link ;
+ p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
+#endif
+
+ done:
+ p->state = GMON_PROF_ON;
+ goto enable_timer_label ;
+ /* overflow: */
+ /*p->state = GMON_PROF_ERROR */
+ enable_timer_label:
+ enable_timer();
+ return ;
+}
+
+
+#endif /* PROFILE_NO_GRAPH */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#define BINSIZE 4U
+#define SAMPLE_FREQ_HZ 100000U
+#define TIMER_CLK_TICKS 1000U
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000U
+#define PROFILE_TIMER_INTR_ID 0U
+
+#define TIMER_CONNECT_INTC
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h"
+
+extern u32 binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+ s32 j;
+
+#ifdef PROC_MICROBLAZE
+ asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+ prof_pc = mfspr(SPR_SRR0);
+#else
+ /* for cortexa9, lr is saved in asm interrupt handler */
+#endif
+ /* print("PC: "), putnum(prof_pc), print("\r\n"), */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
+ _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
+ break;
+ }
+ }
+ /* Ack the Timer Interrupt */
+ timer_ack();
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
+
+.globl __gnu_mcount_nc
+.type __gnu_mcount_nc, %function
+
+__gnu_mcount_nc:
+ push {r0, r1, r2, r3, lr}
+ subs r1, lr, #0 /* callee - current lr */
+ ldr r0, [sp, #20] /* caller - at the top of the stack */
+ bl mcount /* when __gnu_mcount_nc is called */
+ pop {r0, r1, r2, r3, ip, lr}
+ bx ip
+
+ .end __gnu_mcount_nc
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+ .globl _mcount
+ .text
+ .align 2
+ .ent _mcount
+
+ #ifndef PROFILE_NO_GRAPH
+
+_mcount:
+ addi r1, r1, -48
+ swi r11, r1, 44
+ swi r12, r1, 40
+ swi r5, r1, 36
+ swi r6, r1, 32
+ swi r7, r1, 28
+ swi r8, r1, 24
+ swi r9, r1, 20
+ swi r10, r1, 16
+ swi r15, r1, 12
+ add r5, r0, r15
+ brlid r15, mcount
+ add r6, r0, r16
+
+ lwi r11, r1, 44
+ lwi r12, r1, 40
+ lwi r5, r1, 36
+ lwi r6, r1, 32
+ lwi r7, r1, 28
+ lwi r8, r1, 24
+ lwi r9, r1, 20
+ lwi r10, r1, 16
+ lwi r15, r1, 12
+ rtsd r15, 4
+ addi r1, r1, 48
+
+ #endif /* PROFILE_NO_GRAPH */
+
+ .end _mcount
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+ .globl _mcount
+
+ #define _MCOUNT_STACK_FRAME 48
+ .section .text
+ .align 2
+ .type _mcount@function
+
+
+_mcount:
+ stwu 1, -_MCOUNT_STACK_FRAME(1)
+ stw 3, 8(1)
+ stw 4, 12(1)
+ stw 5, 16(1)
+ stw 6, 20(1)
+ stw 7, 24(1)
+ stw 8, 28(1)
+ stw 9, 32(1)
+ stw 10, 36(1)
+ stw 11, 40(1)
+ stw 12, 44(1)
+ mflr 4
+ stw 4, (_MCOUNT_STACK_FRAME+4)(1)
+ lwz 3, (_MCOUNT_STACK_FRAME)(1)
+ lwz 3, 4(3)
+ bl mcount
+ lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
+ mtlr 4
+ lwz 12, 44(1)
+ lwz 11, 40(1)
+ lwz 10, 36(1)
+ lwz 9, 32(1)
+ lwz 8, 28(1)
+ lwz 7, 24(1)
+ lwz 6, 20(1)
+ lwz 5, 16(1)
+ lwz 4, 12(1)
+ lwz 3, 8(1)
+ addi 1,1, _MCOUNT_STACK_FRAME
+ blr
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file pvr.c
+*
+* This header file contains defines for structures used by the microblaze
+* PVR routines
+*
+******************************************************************************/
+#include "xparameters.h"
+#include "pvr.h"
+#include <string.h>
+
+/* Definitions */
+int microblaze_get_pvr (pvr_t *pvr)
+{
+ if (!pvr)
+ return -1;
+
+ bzero ((void*)pvr, sizeof (pvr_t));
+
+#ifdef MICROBLAZE_PVR_NONE
+ return -1;
+#else
+ getpvr (0, pvr->pvr[0]);
+#endif /* MICROBLAZE_PVR_NONE */
+
+#ifdef MICROBLAZE_PVR_FULL
+ getpvr (1, pvr->pvr[1]);
+ getpvr (2, pvr->pvr[2]);
+ getpvr (3, pvr->pvr[3]);
+
+ getpvr (4, pvr->pvr[4]);
+ getpvr (5, pvr->pvr[5]);
+ getpvr (6, pvr->pvr[6]);
+ getpvr (7, pvr->pvr[7]);
+
+ getpvr (8, pvr->pvr[8]);
+ getpvr (9, pvr->pvr[9]);
+ getpvr (10, pvr->pvr[10]);
+ getpvr (11, pvr->pvr[11]);
+
+/* getpvr (12, pvr->pvr[12]); */
+/* getpvr (13, pvr->pvr[13]); */
+/* getpvr (14, pvr->pvr[14]); */
+/* getpvr (15, pvr->pvr[15]); */
+
+#endif /* MICROBLAZE_PVR_FULL */
+
+ return 0;
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file pvr.h
+*
+* This header file contains defines for structures used by the microblaze
+* PVR routines
+*
+******************************************************************************/
+
+#ifndef _PVR_H
+#define _PVR_H
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "mb_interface.h"
+#include "bspconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Defs */
+typedef struct pvr_s {
+#ifdef MICROBLAZE_PVR_FULL
+ unsigned int pvr[16];
+#else
+ unsigned int pvr[1];
+#endif
+} pvr_t;
+
+
+#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
+
+/* Basic PVR mask */
+#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000
+#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000
+#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000
+#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000
+#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000
+#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000
+#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000
+#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000
+#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000
+#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000
+#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000
+#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000
+#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000
+#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00
+#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF
+
+/* User 2 PVR mask */
+#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF
+
+/* Configuration PVR masks */
+#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000
+#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000
+#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000
+#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000
+#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000
+#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000
+#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
+#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
+#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000
+#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000
+#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
+#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000
+#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000
+#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000
+#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000
+#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000
+#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000
+#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800
+#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200
+#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400
+#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040
+#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020
+#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010
+#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008
+#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004
+#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100
+#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080
+#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002
+#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001
+#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000
+
+/* Debug and exception PVR masks */
+#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000
+#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
+#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
+#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
+#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380
+#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007
+
+/* ICache config PVR masks */
+#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000
+#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
+#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
+#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
+#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
+#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000
+#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000
+#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00
+#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300
+#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
+#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040
+
+/* DCache config PVR masks */
+#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000
+#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
+#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
+#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
+#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
+#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000
+#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000
+#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000
+#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00
+#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
+#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040
+
+/* ICache base address PVR mask */
+#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
+
+/* ICache high address PVR mask */
+#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
+
+/* DCache base address PVR mask */
+#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
+
+/* DCache high address PVR mask */
+#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
+
+/* Target family PVR mask */
+#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000
+
+/* MSR Reset value PVR mask */
+#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF
+
+/* MMU value PVR mask */
+#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000
+#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000
+#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000
+#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000
+#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000
+#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000
+
+/* PVR access macros */
+#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
+#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
+#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
+#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
+#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
+#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
+#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
+#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
+#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
+#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
+#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
+#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
+#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
+#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
+
+#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
+
+#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
+#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
+#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
+#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
+#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
+#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
+#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
+#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
+#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
+#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
+#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
+#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
+#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
+#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
+#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
+#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
+#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
+#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
+
+#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
+#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
+#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
+#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
+#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
+#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
+
+#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
+#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
+#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
+#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
+#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
+#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
+#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
+#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
+#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
+#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
+
+#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
+#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
+#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
+#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
+#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
+#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
+#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
+#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
+#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
+#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
+
+#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
+#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
+
+#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
+#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
+
+#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
+
+#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
+
+#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
+#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
+#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
+#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
+#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
+#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
+
+/* Protos */
+int microblaze_get_pvr (pvr_t *pvr);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _PVR_H */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+
+#endif /* end of protection macro */
--- /dev/null
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implemention MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 Initial release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+/*s32 Xil_AssertWait = 1*/
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implement assert. Currently, it calls a user-defined callback function
+* if one has been set. Then, it potentially enters an infinite loop depending
+* on the value of the Xil_AssertWait variable.
+*
+* @param file is the name of the filename of the source
+* @param line is the linenumber within File
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+ s32 Xil_AssertWait = 1;
+ /* if the callback has been set then invoke it */
+ if (Xil_AssertCallbackRoutine != 0) {
+ (*Xil_AssertCallbackRoutine)(File, Line);
+ }
+
+ /* if specified, wait indefinitely such that the assert will show up
+ * in testing
+ */
+ while (Xil_AssertWait != 0) {
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Set up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param routine is the callback to be invoked when an assert is taken
+*
+* @return None.
+*
+* @note This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+ Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param NullParameter is an arbitrary void pointer and not used.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void *) NullParameter;
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param Expression is the expression to evaluate. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
+* so that asserts which fail allow execution to continue.
+*
+* @param Expression is the expression to evaluate. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* This contains implementation of cache related driver functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00 hbm 07/28/09 Initial release
+* 3.10 asa 05/04/13 This version of MicroBlaze BSP adds support for system
+* cache/L2 cache. Existing APIs in this file are modified
+* to add support for L2 cache.
+* These changes are done for implementing PR #697214.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xil_cache.h"
+
+
+/****************************************************************************/
+/**
+*
+* Disable the data cache.
+*
+* @param None
+*
+* @return None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+ Xil_DCacheFlush();
+ Xil_DCacheInvalidate();
+ Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+*
+* Disable the instruction cache.
+*
+* @param None
+*
+* @return None.
+*
+* @note
+*
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+ Xil_ICacheInvalidate();
+ Xil_L1ICacheDisable();
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* This header file contains cache related driver functions (or macros)
+* that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* The functions in this header file can be used across all Xilinx supported
+* processors.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00 hbm 07/28/09 Initial release
+* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
+* the correct cache flush routines are used based on
+* whether the write-back or write-through caches are
+* used (cr #630532).
+* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
+* cache/L2 cache. The existing/old APIs/macros in this
+* file are renamed to imply that they deal with L1 cache.
+* New macros/APIs are added to address similar features for
+* L2 cache. Users can include this file in their application
+* to use the various cache related APIs. These changes are
+* done for implementing PR #697214.
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#if defined XENV_VXWORKS
+/* VxWorks environment */
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#else
+/* standalone environment */
+
+#include "mb_interface.h"
+#include "xil_types.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/**
+*
+* Invalidate the entire L1 data cache. If the cacheline is modified (dirty),
+* the modified contents are lost.
+*
+* @param None.
+*
+* @return None.
+*
+* @note
+*
+* Processor must be in real mode.
+****************************************************************************/
+#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
+
+/****************************************************************************/
+/**
+*
+* Invalidate the entire L2 data cache. If the cacheline is modified (dirty),
+* the modified contents are lost.
+*
+* @param None.
+*
+* @return None.
+*
+* @note
+*
+* Processor must be in real mode.
+****************************************************************************/
+#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
+
+/****************************************************************************/
+/**
+*
+* Invalidate the L1 data cache for the given address range.
+* If the bytes specified by the address (Addr) are cached by the L1 data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost.
+*
+* @param Addr is address of ragne to be invalidated.
+* @param Len is the length in bytes to be invalidated.
+*
+* @return None.
+*
+* @note
+*
+* Processor must be in real mode.
+****************************************************************************/
+#define Xil_L1DCacheInvalidateRange(Addr, Len) \
+ microblaze_invalidate_dcache_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+*
+* Invalidate the L1 data cache for the given address range.
+* If the bytes specified by the address (Addr) are cached by the L1 data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost.
+*
+* @param Addr is address of ragne to be invalidated.
+* @param Len is the length in bytes to be invalidated.
+*
+* @return None.
+*
+* @note
+*
+* Processor must be in real mode.
+****************************************************************************/
+#define Xil_L2CacheInvalidateRange(Addr, Len) \
+ microblaze_invalidate_cache_ext_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+* Flush the L1 data cache for the given address range.
+* If the bytes specified by the address (Addr) are cached by the data cache,
+* and is modified (dirty), the cacheline will be written to system memory.
+* The cacheline will also be invalidated.
+*
+* @param Addr is the starting address of the range to be flushed.
+* @param Len is the length in byte to be flushed.
+*
+* @return None.
+*
+****************************************************************************/
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define Xil_L1DCacheFlushRange(Addr, Len) \
+ microblaze_flush_dcache_range((Addr), (Len))
+#else
+# define Xil_L1DCacheFlushRange(Addr, Len) \
+ microblaze_invalidate_dcache_range((Addr), (Len))
+#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
+
+/****************************************************************************/
+/**
+* Flush the L2 data cache for the given address range.
+* If the bytes specified by the address (Addr) are cached by the data cache,
+* and is modified (dirty), the cacheline will be written to system memory.
+* The cacheline will also be invalidated.
+*
+* @param Addr is the starting address of the range to be flushed.
+* @param Len is the length in byte to be flushed.
+*
+* @return None.
+*
+****************************************************************************/
+#define Xil_L2CacheFlushRange(Addr, Len) \
+ microblaze_flush_cache_ext_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be
+* written to system memory. The entire data cache will be invalidated.
+*
+* @return None.
+*
+* @note
+*
+****************************************************************************/
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define Xil_L1DCacheFlush() microblaze_flush_dcache()
+#else
+# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
+#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
+
+/****************************************************************************/
+/**
+* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be
+* written to system memory. The entire data cache will be invalidated.
+*
+* @return None.
+*
+* @note
+*
+****************************************************************************/
+#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
+
+/****************************************************************************/
+/**
+*
+* Invalidate the instruction cache for the given address range.
+*
+* @param Addr is address of ragne to be invalidated.
+* @param Len is the length in bytes to be invalidated.
+*
+* @return None.
+*
+****************************************************************************/
+#define Xil_L1ICacheInvalidateRange(Addr, Len) \
+ microblaze_invalidate_icache_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+*
+* Invalidate the entire instruction cache.
+*
+* @param None
+*
+* @return None.
+*
+****************************************************************************/
+#define Xil_L1ICacheInvalidate() \
+ microblaze_invalidate_icache()
+
+
+/****************************************************************************/
+/**
+*
+* Enable the L1 data cache.
+*
+* @return None.
+*
+* @note This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1DCacheEnable() \
+ microblaze_enable_dcache()
+
+/****************************************************************************/
+/**
+*
+* Disable the L1 data cache.
+*
+* @return None.
+*
+* @note This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1DCacheDisable() \
+ microblaze_disable_dcache()
+
+/****************************************************************************/
+/**
+*
+* Enable the instruction cache.
+*
+* @return None.
+*
+* @note This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1ICacheEnable() \
+ microblaze_enable_icache()
+
+/****************************************************************************/
+/**
+*
+* Disable the L1 Instruction cache.
+*
+* @return None.
+*
+* @note This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1ICacheDisable() \
+ microblaze_disable_icache()
+
+/****************************************************************************/
+/**
+*
+* Enable the data cache.
+*
+* @param None
+*
+* @return None.
+*
+****************************************************************************/
+#define Xil_DCacheEnable() Xil_L1DCacheEnable()
+
+/****************************************************************************/
+/**
+*
+* Enable the instruction cache.
+*
+* @param None
+*
+* @return None.
+*
+* @note
+*
+*
+****************************************************************************/
+#define Xil_ICacheEnable() Xil_L1ICacheEnable()
+
+/****************************************************************************
+*
+* Invalidate the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#define Xil_DCacheInvalidate() \
+ Xil_L2CacheInvalidate(); \
+ Xil_L1DCacheInvalidate();
+
+
+/****************************************************************************
+*
+* Invalidate the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param Start address of ragne to be invalidated.
+* @param Length of range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ Xil_L2CacheInvalidateRange((Addr), (Len)); \
+ Xil_L1DCacheInvalidateRange((Addr), (Len));
+
+
+/****************************************************************************
+*
+* Flush the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#define Xil_DCacheFlush() \
+ Xil_L2CacheFlush(); \
+ Xil_L1DCacheFlush();
+
+/****************************************************************************
+* Flush the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the written to system memory first before the
+* before the line is invalidated.
+*
+* @param Start address of range to be flushed.
+* @param Length of range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#define Xil_DCacheFlushRange(Addr, Len) \
+ Xil_L2CacheFlushRange((Addr), (Len)); \
+ Xil_L1DCacheFlushRange((Addr), (Len));
+
+
+/****************************************************************************
+*
+* Invalidate the entire instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#define Xil_ICacheInvalidate() \
+ Xil_L2CacheInvalidate(); \
+ Xil_L1ICacheInvalidate();
+
+
+/****************************************************************************
+*
+* Invalidate the instruction cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param Start address of ragne to be invalidated.
+* @param Length of range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ Xil_L2CacheInvalidateRange((Addr), (Len)); \
+ Xil_L1ICacheInvalidateRange((Addr), (Len));
+
+void Xil_DCacheDisable(void);
+void Xil_ICacheDisable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains implementation of exception related driver functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00 hbm 07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+#include "xil_exception.h"
+
+#include "microblaze_exceptions_g.h"
+#include "microblaze_interrupts_i.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void microblaze_enable_exceptions(void);
+extern void microblaze_disable_exceptions(void);
+extern void microblaze_enable_interrupts(void);
+extern void microblaze_disable_interrupts(void);
+
+/**
+* Currently HAL is an augmented part of standalone BSP, so the old definition
+* of MB_ExceptionVectorTableEntry is used here.
+*/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *CallBackRef;
+} MB_ExceptionVectorTableEntry;
+
+/*typedef struct {
+ Xil_ExceptionHandler Handler,
+ void *CallBackRef,
+} MB_InterruptVectorTableEntry, */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/************************** Variable Definitions *****************************/
+extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT];
+extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
+
+/**
+ *
+ * This function is a stub handler that is the default handler that gets called
+ * if the application has not setup a handler for a specific exception. The
+ * function interface has to match the interface specified for a handler even
+ * though none of the arguments are used.
+ *
+ * @param Data is unused by this function.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ *
+ * None.
+ *
+ *****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+ (void *) Data;
+}
+
+/****************************************************************************/
+/**
+*
+* Initialize exception handling for the processor. The exception vector table
+* is setup with the stub handler for all exceptions.
+*
+* @param None.
+*
+* @return None.
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+ /*
+ * there is no need to setup the exception table here
+ */
+
+}
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_ExceptionEnable(void)
+{
+#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
+ microblaze_enable_exceptions();
+#endif
+ microblaze_enable_interrupts();
+}
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_ExceptionDisable(void)
+{
+#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
+ microblaze_disable_exceptions();
+#endif
+ microblaze_disable_interrupts();
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the exception source and the
+* associated handler that is to run when the exception is recognized. The
+* argument provided in this call as the DataPtr is used as the argument
+* for the handler when it is called.
+*
+* @param Id contains the ID of the exception source and should
+* be XIL_EXCEPTION_INT or be in the range of 0 to XIL_EXCEPTION_LAST.
+* See xil_mach_exception.h for further information.
+* @param Handler to the handler for that exception.
+* @param Data is a reference to data that will be passed to the handler
+* when it gets called.
+*
+* @return None.
+*
+* @note
+*
+* None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Id, Xil_ExceptionHandler Handler,
+ void *Data)
+{
+ if (Id == XIL_EXCEPTION_ID_INT) {
+ MB_InterruptVectorTable.Handler = Handler;
+ MB_InterruptVectorTable.CallBackRef = Data;
+ }
+ else {
+#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
+ MB_ExceptionVectorTable[Id].Handler = Handler;
+ MB_ExceptionVectorTable[Id].CallBackRef = Data;
+#endif
+ }
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Removes the handler for a specific exception Id. The stub handler is then
+* registered for this exception Id.
+*
+* @param Id contains the ID of the exception source and should
+* be XIL_EXCEPTION_INT or in the range of 0 to XIL_EXCEPTION_LAST.
+* See xexception_l.h for further information.
+*
+* @return None.
+*
+* @note
+*
+* None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Id)
+{
+ if (Id == XIL_EXCEPTION_ID_INT) {
+ MB_InterruptVectorTable.Handler = Xil_ExceptionNullHandler;
+ MB_InterruptVectorTable.CallBackRef = NULL;
+ }
+ else {
+
+#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
+ MB_ExceptionVectorTable[Id].Handler =
+ Xil_ExceptionNullHandler;
+ MB_ExceptionVectorTable[Id].CallBackRef = NULL;
+#endif
+ }
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains exception related driver functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00 hbm 07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * These constants are specific to Microblaze processor.
+ */
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#define XIL_EXCEPTION_ID_FSL 0U
+#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U
+#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U
+#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U
+#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U
+#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U
+#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U
+#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U
+#define XIL_EXCEPTION_ID_FPU 6U
+#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U
+#define XIL_EXCEPTION_ID_MMU 7U
+#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
+ */
+#define XIL_EXCEPTION_ID_INT 16U /**
+ * exception ID for interrupt
+ */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *Data);
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Id);
+
+extern void Xil_ExceptionInit(void);
+extern void Xil_ExceptionEnable(void);
+extern void Xil_ExceptionDisable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped architectures. These functions
+* encapsulate generic CPU I/O requirements.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a hbm 07/28/09 Initial release
+* 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s
+* 5.4 sk 01/14/16 Changed xil_io() and xil_out() functions to static inline
+* functions.
+*
+* </pre>
+*
+* @note
+*
+* This file may contain architecture-dependent code.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/***************** Macros (Inline Functions) and Functions Definitions *******/
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param Data contains the value to be converted.
+*
+* @return converted value.
+*
+* @note None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param Data contains the value to be converted.
+*
+* @return converted value.
+*
+* @note None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFFU);
+ HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+ /* swap the half words before returning the value */
+
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a little-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the byte-swapped value
+* read from that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address with the
+* proper endianness. The return value has the same endianness
+* as that of the processor, i.e. if the processor is big-engian,
+* the return value is the byte-swapped value read from the
+* address.
+*
+*
+* @note None.
+*
+******************************************************************************/
+#ifndef __LITTLE_ENDIAN__
+u16 Xil_In16LE(UINTPTR Addr)
+#else
+u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 Value;
+
+ /* get the data then swap it */
+ Value = Xil_In16(Addr);
+
+ return Xil_EndianSwap16(Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a little-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the byte-swapped value
+* read from that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address with the
+* proper endianness. The return value has the same endianness
+* as that of the processor, i.e. if the processor is big-engian,
+* the return value is the byte-swapped value read from the
+* address.
+*
+* @note None.
+*
+******************************************************************************/
+#ifndef __LITTLE_ENDIAN__
+u32 Xil_In32LE(UINTPTR Addr)
+#else
+u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 InValue;
+
+ /* get the data then swap it */
+ InValue = Xil_In32(Addr);
+ return Xil_EndianSwap32(InValue);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a little-endian output operation for a 16-bit memory location by
+* writing the specified value to the the specified address. The value is
+* byte-swapped before being written.
+*
+* @param Addr contains the address to perform the output operation at.
+* @param Value contains the value to be output at the specified address.
+* The value has the same endianness as that of the processor.
+* If the processor is big-endian, the byte-swapped value is
+* written to the address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#ifndef __LITTLE_ENDIAN__
+void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#else
+void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ u16 OutValue;
+
+ /* swap the data then output it */
+ OutValue = Xil_EndianSwap16(Value);
+
+ Xil_Out16(Addr, OutValue);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a little-endian output operation for a 32-bit memory location
+* by writing the specified value to the the specified address. The value is
+* byte-swapped before being written.
+*
+* @param Addr contains the address at which the output operation at.
+* @param Value contains the value to be output at the specified address.
+* The value has the same endianness as that of the processor.
+* If the processor is big-endian, the byte-swapped value is
+* written to the address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#ifndef __LITTLE_ENDIAN__
+void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#else
+void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ u32 OutValue;
+
+ /* swap the data then output it */
+ OutValue = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, OutValue);
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a hbm 07/28/09 Initial release
+* 3.00a hbm 07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s
+* 3.03a sdm 08/18/11 Added INST_SYNC and DATA_SYNC macros.
+* 3.07a asa 08/31/12 Added xil_printf.h include
+* 5.4 sk 01/14/16 Changed xil_io() and xil_out() functions to static inline
+* functions.
+*
+* </pre>
+*
+* @note
+*
+* This file may contain architecture-dependent items.
+*
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "mb_interface.h"
+#include "xil_printf.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Function Prototypes ****************************/
+
+static inline u8 Xil_In8(UINTPTR Addr);
+static inline u16 Xil_In16(UINTPTR Addr);
+static inline u32 Xil_In32(UINTPTR Addr);
+
+static inline void Xil_Out8(UINTPTR Addr, u8 Value);
+static inline void Xil_Out16(UINTPTR Addr, u16 Value);
+static inline void Xil_Out32(UINTPTR Addr, u32 Value);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Perform an input operation for an 8-bit memory location by reading from the
+* specified address and returning the value read from that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+static inline u8 Xil_In8(UINTPTR Addr) {
+ return *(volatile u8 *)Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform an input operation for a 16-bit memory location by reading from the
+* specified address and returning the value read from that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+static inline u16 Xil_In16(UINTPTR Addr) {
+ return *(volatile u16 *)Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+static inline u32 Xil_In32(UINTPTR Addr) {
+ return *(volatile u32 *)Addr;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform an output operation for an 8-bit memory location by writing the
+* specified value to the specified address.
+*
+* @param Addr contains the address to perform the output operation at.
+* @param value contains the value to be output at the specified address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static inline void Xil_Out8(UINTPTR Addr, u8 Value) {
+ volatile u8 *LocalAddr = (u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform an output operation for a 16-bit memory location by writing the
+* specified value to the specified address.
+*
+* @param Addr contains the address to perform the output operation at.
+* @param value contains the value to be output at the specified address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static inline void Xil_Out16(UINTPTR Addr, u16 Value) {
+ volatile u16 *LocalAddr = (u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform an output operation for a 32-bit memory location by writing the
+* specified value to the specified address.
+*
+* @param addr contains the address to perform the output operation at.
+* @param value contains the value to be output at the specified address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static inline void Xil_Out32(UINTPTR Addr, u32 Value) {
+ volatile u32 *LocalAddr = (u32 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined __GNUC__
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+#else
+# define INST_SYNC
+# define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*
+ * The following macros allow optimized I/O operations for memory mapped I/O.
+ * It should be noted that macros cannot be used if synchronization of the I/O
+ * operation is needed as it will likely break some code.
+ */
+
+
+
+extern u16 Xil_EndianSwap16(u16 Data);
+extern u32 Xil_EndianSwap32(u32 Data);
+
+#ifndef __LITTLE_ENDIAN__
+extern u16 Xil_In16LE(UINTPTR Addr);
+extern u32 Xil_In32LE(UINTPTR Addr);
+extern void Xil_Out16LE(UINTPTR Addr, u16 Value);
+extern void Xil_Out32LE(UINTPTR Addr, u32 Value);
+
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the value read from
+* that address.
+*
+* @param addr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address with the
+* proper endianness. The return value has the same endianness
+* as that of the processor, i.e. if the processor is
+* little-engian, the return value is the byte-swapped value read
+* from the address.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_In16BE(Addr) Xil_In16((Addr))
+
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the value read from
+* that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The value read from the specified input address with the
+* proper endianness. The return value has the same endianness
+* as that of the processor, i.e. if the processor is
+* little-engian, the return value is the byte-swapped value read
+* from the address.
+*
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_In32BE(Addr) Xil_In32((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified value to the specified address.
+*
+* @param Addr contains the address to perform the output operation at.
+* @param Value contains the value to be output at the specified address.
+* The value has the same endianness as that of the processor.
+* If the processor is little-endian, the byte-swapped value is
+* written to the address.
+*
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Out16BE(Addr, Value) Xil_Out16((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified value to the specified address.
+*
+* @param Addr contains the address to perform the output operation at.
+* @param Value contains the value to be output at the specified address.
+* The value has the same endianness as that of the processor.
+* If the processor is little-endian, the byte-swapped value is
+* written to the address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Out32BE(Addr, Value) Xil_Out32((Addr), (Value))
+
+#define Xil_Htonl(Data) (Data)
+#define Xil_Htons(Data) (Data)
+#define Xil_Ntohl(Data) (Data)
+#define Xil_Ntohs(Data) (Data)
+
+#else
+
+extern u16 Xil_In16BE(UINTPTR Addr);
+extern u32 Xil_In32BE(UINTPTR Addr);
+extern void Xil_Out16BE(UINTPTR Addr, u16 Value);
+extern void Xil_Out32BE(UINTPTR Addr, u32 Value);
+
+#define Xil_In16LE(Addr) Xil_In16((Addr))
+#define Xil_In32LE(Addr) Xil_In32((Addr))
+#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
+#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
+
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param Data the 32-bit number to be converted.
+*
+* @return The converted 32-bit number in network byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param Data the 16-bit number to be converted.
+*
+* @return The converted 16-bit number in network byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param Value the 32-bit number to be converted.
+*
+* @return The converted 32-bit number in host byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param Value the 16-bit number to be converted.
+*
+* @return The converted 16-bit number in host byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in
+* slcr reset functional blcok.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release
+* 5.4 pkp 16/11/15 Change the description for XOcm_Remap function
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XDdr_ResetHw(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert and deassert the ddr softreset bit */
+ RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
+ RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+ RegVal |= XDDRPS_CTRL_RESET_MASK;
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* to postbootrom state.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XOcm_Remap(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Map the ocm region to postbootrom state */
+ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+ RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
+ Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+*
+* @param BaseAddress of the interface
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+ u32 RegVal;
+
+ /* Clear the interuupts */
+ RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+ RegVal |= XSMC_MEMC_CLR_CONFIG_MASK;
+ Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+ /* Clear the idle counter registers */
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
+ /* Update the ecc registers with reset values */
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
+ XSMC_ECC_MEMCFG1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+ XSMC_ECC_MEMCMD1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
+ XSMC_ECC_MEMCMD2_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues(void)
+{
+ u32 i;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Update all the MIO registers with reset values */
+ for (i=0U; i<=1U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+ for (; i<=8U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_02_RESET_VAL);
+ }
+ for (; i<=53U ;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues(void)
+{
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+
+ /* update the pll control registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
+ /* update the pll config registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
+ /* update the clock control registers with reset values */
+ Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Disable the level shifters */
+ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
+ Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal |= XSLCR_OCM_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from
+* the slcr
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal |= XSLCR_GEM_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal &= (u32)(~XSLCR_GEM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal |= XSLCR_USB_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal |= XSLCR_QSPI_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal |= XSLCR_SPI_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal |= XSLCR_I2C_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal |= XSLCR_UART_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr
+* registers
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal |= XSLCR_CAN_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal |= XSLCR_SMC_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal |= XSLCR_DMAC_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from
+* the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal |= XSLCR_GPIO_RST_CTRL_VAL;
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x0000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x00000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
--- /dev/null
+/*---------------------------------------------------*/
+/* Modified from : */
+/* Public Domain version of printf */
+/* Rud Merriam, Compsult, Inc. Houston, Tx. */
+/* For Embedded Systems Programming, 1991 */
+/* */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+ s32 len;
+ s32 num1;
+ s32 num2;
+ char8 pad_character;
+ s32 do_padding;
+ s32 left_flag;
+ s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/* */
+/* This routine puts pad characters into the output */
+/* buffer. */
+/* */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+ s32 i;
+
+ if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+ i=(par->len);
+ for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( par->pad_character);
+#endif
+ }
+ }
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a string to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+static void outs(const charptr lp, struct params_s *par)
+{
+ charptr LocalPtr;
+ LocalPtr = lp;
+ /* pad on left if needed */
+ if(LocalPtr != NULL) {
+ par->len = (s32)strlen( LocalPtr);
+ }
+ padding( !(par->left_flag), par);
+
+ /* Move string to the buffer */
+ while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+ (par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*LocalPtr);
+ LocalPtr += 1;
+#endif
+}
+
+ /* Pad on right if needed */
+ /* CR 439175 - elided next stmt. Seemed bogus. */
+ /* par->len = strlen( lp) */
+ padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a number to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+ charptr cp;
+ s32 negative;
+ s32 i;
+ char8 outbuf[32];
+ const char8 digits[] = "0123456789ABCDEF";
+ u32 num;
+ for(i = 0; i<32; i++) {
+ outbuf[i] = '0';
+ }
+
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = n;
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = 0;
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( outbuf[i] );
+ i--;
+#endif
+}
+ padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine gets a number from the format */
+/* string. */
+/* */
+static s32 getnum( charptr* linep)
+{
+ s32 n;
+ s32 ResultIsDigit = 0;
+ charptr cptr;
+ n = 0;
+ cptr = *linep;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ while (ResultIsDigit != 0) {
+ if(cptr != NULL){
+ n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+ cptr += 1;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ }
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ *linep = ((charptr )(cptr));
+ return(n);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine operates just like a printf/sprintf */
+/* routine. It outputs a set of data under the */
+/* control of a formatting string. Not all of the */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded */
+/* systems work. Primarily the floating point */
+/* routines are omitted. Other formats could be */
+/* added easily by following the examples shown for */
+/* the supported formats. */
+/* */
+
+/* void esp_printf( const func_ptr f_ptr,
+ const charptr ctrl1, ...) */
+void xil_printf( const char8 *ctrl1, ...)
+{
+ s32 Check;
+ s32 long_flag;
+ s32 dot_flag;
+
+ params_t par;
+
+ char8 ch;
+ va_list argp;
+ char8 *ctrl = (char8 *)ctrl1;
+
+ va_start( argp, ctrl1);
+
+ while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+ /* move format string chars to buffer until a */
+ /* format control is found. */
+ if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*ctrl);
+ ctrl += 1;
+#endif
+ continue;
+ }
+
+ /* initialize all the flags for this format. */
+ dot_flag = 0;
+ long_flag = 0;
+ par.unsigned_flag = 0;
+ par.left_flag = 0;
+ par.do_padding = 0;
+ par.pad_character = ' ';
+ par.num2=32767;
+ par.num1=0;
+ par.len=0;
+
+ try_next:
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ if(ctrl != NULL) {
+ ch = *ctrl;
+ }
+ else {
+ ch = *ctrl;
+ }
+
+ if (isdigit((s32)ch) != 0) {
+ if (dot_flag != 0) {
+ par.num2 = getnum(&ctrl);
+ }
+ else {
+ if (ch == '0') {
+ par.pad_character = '0';
+ }
+ if(ctrl != NULL) {
+ par.num1 = getnum(&ctrl);
+ }
+ par.do_padding = 1;
+ }
+ if(ctrl != NULL) {
+ ctrl -= 1;
+ }
+ goto try_next;
+ }
+
+ switch (tolower((s32)ch)) {
+ case '%':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( '%');
+#endif
+ Check = 1;
+ break;
+
+ case '-':
+ par.left_flag = 1;
+ Check = 0;
+ break;
+
+ case '.':
+ dot_flag = 1;
+ Check = 0;
+ break;
+
+ case 'l':
+ long_flag = 1;
+ Check = 0;
+ break;
+
+ case 'u':
+ par.unsigned_flag = 1;
+ /* fall through */
+ case 'i':
+ case 'd':
+ if ((long_flag != 0) || (ch == 'D')) {
+ outnum( va_arg(argp, s32), 10L, &par);
+ }
+ else {
+ outnum( va_arg(argp, s32), 10L, &par);
+ }
+ Check = 1;
+ break;
+ case 'p':
+ case 'X':
+ case 'x':
+ par.unsigned_flag = 1;
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ Check = 1;
+ break;
+
+ case 's':
+ outs( va_arg( argp, char *), &par);
+ Check = 1;
+ break;
+
+ case 'c':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( va_arg( argp, s32));
+#endif
+ Check = 1;
+ break;
+
+ case '\\':
+ switch (*ctrl) {
+ case 'a':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x07));
+#endif
+ break;
+ case 'h':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x08));
+#endif
+ break;
+ case 'r':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+#endif
+ break;
+ case 'n':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+ outbyte( ((char8)0x0A));
+#endif
+ break;
+ default:
+#ifdef STDOUT_BASEADDRESS
+ outbyte( *ctrl);
+#endif
+ break;
+ }
+ ctrl += 1;
+ Check = 0;
+ break;
+
+ default:
+ Check = 1;
+ break;
+ }
+ if(Check == 1) {
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ continue;
+ }
+ goto try_next;
+ }
+ va_end( argp);
+}
+
+/*---------------------------------------------------*/
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef XIL_PRINTF_H
+#define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print(const char8 *ptr);
+void outbyte(char c);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
+* cache line.
+* </pre>
+*
+* @note
+*
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+/**
+* Perform DCache range related API test such as Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange. This test function writes a constant value
+* to the Data array, flushes the range, writes a new value, then invalidates
+* the corresponding range.
+*
+* @return
+*
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheRange(void)
+{
+ s32 Index;
+ s32 Status = 0;
+ u32 CtrlReg;
+ INTPTR Value;
+
+ xil_printf("-- Cache Range Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A00505;
+
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" flush range done\r\n");
+
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A00505) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush worked\r\n");
+ }
+ else {
+ xil_printf("Error: flush dcache range not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0C505;
+
+
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" invalidate dcache range done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0A05;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A0A05) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+
+ if (!Status) {
+ xil_printf(" Invalidate worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache range not working\r\n");
+ }
+ xil_printf("-- Cache Range Test Complete --\r\n");
+ return Status;
+
+}
+
+/**
+* Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value, then invalidates
+* the DCache.
+*
+* @return
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheAll(void)
+{
+ s32 Index;
+ s32 Status;
+ INTPTR Value;
+ u32 CtrlReg;
+
+ xil_printf("-- Cache All Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50500A0A;
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlush();
+ xil_printf(" flush all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+
+ if (Value != 0x50500A0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Flush dcache all not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x505FFA0A;
+
+ Xil_DCacheFlush();
+
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidate();
+
+ xil_printf(" invalidate all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50CFA0A;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0x50CFA0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Invalidate all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache all not working\r\n");
+ }
+
+ xil_printf("-- DCache all Test Complete --\n\r");
+
+ return Status;
+}
+
+
+/**
+* Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*
+* - 0 is returned for a pass
+* The function will hang if it fails.
+*/
+s32 Xil_TestICacheRange(void)
+{
+
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+ xil_printf("-- Invalidate icache range done --\r\n");
+
+ return 0;
+}
+
+/**
+* Perform Xil_ICacheInvalidate().
+*
+* @return
+*
+* - 0 is returned for a pass
+* The function will hang if it fails.
+*/
+s32 Xil_TestICacheAll(void)
+{
+ Xil_ICacheInvalidate();
+ xil_printf("-- Invalidate icache all done --\r\n");
+ return 0;
+}
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* This file contains utility functions to test cache.
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param Data is the 16-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+ return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param Data is the 32-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+ u16 Lo16;
+ u16 Hi16;
+
+ u16 Swap16Lo;
+ u16 Swap16Hi;
+
+ Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+ Lo16 = (u16)(Data & 0x0000FFFFU);
+
+ Swap16Lo = Swap16(Lo16);
+ Swap16Hi = Swap16(Hi16);
+
+ return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide register IO test where the register is
+* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
+* values.
+*
+* @param Addr is a pointer to the region of memory to be tested.
+* @param Length is the Length of the block.
+* @param Value is the constant used for writting the memory.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+ u8 ValueIn;
+ s32 Index;
+ s32 Status = 0;
+
+ for (Index = 0; Index < Length; Index++) {
+ Xil_Out8((INTPTR)Addr, Value);
+
+ ValueIn = Xil_In8((INTPTR)Addr);
+
+ if ((Value != ValueIn) && (Status == 0)) {
+ Status = -1;
+ break;
+ }
+ }
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide register IO test. Each location is tested
+* by sequentially writing a 16-bit wide register, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function performs the following
+* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
+* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
+* read-in value before comparing is controlled by the 5th argument.
+*
+* @param Addr is a pointer to the region of memory to be tested.
+* @param Length is the Length of the block.
+* @param Value is the constant used for writting the memory.
+* @param Kind is the test kind. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+ u16 *TempAddr16;
+ u16 ValueIn = 0U;
+ s32 Index;
+ TempAddr16 = Addr;
+ Xil_AssertNonvoid(TempAddr16 != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out16LE((INTPTR)TempAddr16, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out16BE((INTPTR)TempAddr16, Value);
+ break;
+ default:
+ Xil_Out16((INTPTR)TempAddr16, Value);
+ break;
+ }
+
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out16((INTPTR)TempAddr16, Value);
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+ break;
+ default:
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+ break;
+ }
+
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr16 += sizeof(u16);
+ }
+ return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide register IO test. Each location is tested
+* by sequentially writing a 32-bit wide regsiter, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function perform the following
+* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
+* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
+* before comparing is controlled by the 5th argument.
+*
+* @param Addr is a pointer to the region of memory to be tested.
+* @param Length is the Length of the block.
+* @param Value is the constant used for writting the memory.
+* @param Kind is the test kind. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+ u32 *TempAddr;
+ u32 ValueIn = 0U;
+ s32 Index;
+ TempAddr = Addr;
+ Xil_AssertNonvoid(TempAddr != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out32LE((INTPTR)TempAddr, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out32BE((INTPTR)TempAddr, Value);
+ break;
+ default:
+ Xil_Out32((INTPTR)TempAddr, Value);
+ break;
+ }
+
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out32((INTPTR)TempAddr, Value);
+
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In32LE((INTPTR)TempAddr);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In32BE((INTPTR)TempAddr);
+ break;
+ default:
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+ break;
+ }
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr += sizeof(u32);
+ }
+ return 0;
+}
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.h
+*
+* This file contains utility functions to teach endian related memory
+* IO functions.
+*
+* <b>Memory test description</b>
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide memory test.
+*
+* @param Addr is a pointer to the region of memory to be tested.
+* @param Words is the length of the block.
+* @param Pattern is the constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest is the test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+*
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u32 Val;
+ u32 FirtVal;
+ u32 WordMem32;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ *(Addr+I) = Val;
+ Val++;
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (1U << j);
+
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u32) RotateLeft(Val, 32U);
+ }
+
+ /*
+ * Restore the reference 'val' to the
+ * initial value
+ */
+ Val = 1U << j;
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = (u32)RotateLeft(Val, 32U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible
+ * initial test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = ~(1U << j);
+
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+
+ Val = ~(1U << j);
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* Read the location */
+ WordMem32 = *(Addr+I);
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+
+ if ((WordMem32 ^ Val) != 0x00000000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u32)0) {
+ Val = 0xDEADBEEFU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide memory test.
+*
+* @param Addr is a pointer to the region of memory to be tested.
+* @param Words is the length of the block.
+* @param Pattern is the constant used for the constant Pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest is the test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u16 Val;
+ u16 FirtVal;
+ u16 WordMem16;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * selectthe proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (u16)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u16)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones
+ * test to test for bad
+ * data bits
+ */
+
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u16) (~((INTPTR)(&Addr[I])));
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ Val = (u16) (~((INTPTR) (&Addr[I])));
+ if ((WordMem16 ^ Val) != 0x0000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+ if (Pattern == (u16)0) {
+ Val = 0xDEADU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide memory test.
+*
+* @param Addr is a pointer to the region of memory to be tested.
+* @param Words is the length of the block.
+* @param Pattern is the constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest is the test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u8 Val;
+ u8 FirtVal;
+ u8 WordMem8;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * select the proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+ Val = (u8)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u8)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test to test
+ * for bad data bits
+ */
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ if ((WordMem8 ^ Val) != 0x00U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u8)0) {
+ Val = 0xA5U;
+ }
+ else {
+ Val = Pattern;
+ }
+ /*
+ * Fill the memory with fixed Pattern
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the left one bit position
+*
+* @param Input is value to be rotated to the left
+* @param Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting unsigned long value of the rotate left
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+ u32 Msb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+ /*
+ * set the Width of the Input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ Msb = LocalInput & MsbMask;
+
+ ReturnVal = LocalInput << 1U;
+
+ if (Msb != 0x00000000U) {
+ ReturnVal = ReturnVal | (u32)0x00000001;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the right one bit position
+*
+* @param Input is value to be rotated to the right
+* @param Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting u32 value of the rotate right
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+ u32 Lsb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << 1U) - 1U;
+
+ /*
+ * set the width of the input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ ReturnVal = LocalInput >> 1U;
+
+ Lsb = LocalInput & 0x00000001U;
+
+ if (Lsb != 0x00000000U) {
+ ReturnVal = ReturnVal | MsbMask;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+*
+* This file contains utility functions to test memory.
+*
+* <b>Memory test description</b>
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* <pre>
+* XIL_TESTMEM_ALLMEMTESTS:
+* Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+* Incrementing Value Test.
+* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+* incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+* Walking Ones Test.
+* This test uses a walking '1' as the test value for memory.
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+*
+* XIL_TESTMEM_WALKZEROS:
+* Walking Zero's Test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+* Inverse Address Test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+* Fixed Pattern Test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+* </pre>
+*
+* <i>WARNING</i>
+*
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+*
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+* @note None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+* @note None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/**
+ * xbasic_types.h does not typedef s* or u64
+ */
+
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * UPPER_32_BITS - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * LOWER_32_BITS - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00 pkp 12/15/14 Initial release
+* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
+* mode
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about platform
+*
+* @param None.
+*
+* @return The information about platform defined in xplatform_info.h
+*
+* @note None.
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+ u32 reg;
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+ return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+ return XPLAT_MICROBLAZE;
+#else
+ return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about zynq ultrascale MP platform
+*
+* @param None.
+*
+* @return The information about zynq ultrascale MP platform defined in
+* xplatform_info.h
+*
+* @note None.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+ u32 reg;
+ reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+ return reg;
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about PS Silicon version
+*
+* @param None.
+*
+* @return The information about PS Silicon version.
+*
+* @note None.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info()
+{
+ u32 reg;
+ reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+ & XPS_VERSION_INFO_MASK);
+ return reg;
+}
+#endif
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* This file contains definitions for various platforms available
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes. Status codes have their
+* own data type called int. These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /* an error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /* an error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /* the device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /* there was no data available */
+#define XST_REGISTER_ERROR 14L /* a register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /* the device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
+#define XST_NO_CALLBACK 18L /* a callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /* device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /* device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /* device is busy */
+#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /* used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /* used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /* driver defined error */
+#define XST_RECV_ERROR 27L /* generic receive error */
+#define XST_SEND_ERROR 28L /* generic transmit error */
+#define XST_NOT_ENABLED 29L /* a requested service is not
+ available because it has not
+ been enabled */
+
+/***************** Utility Component statuses 401 - 500 *********************/
+
+#define XST_MEMTEST_FAILED 401L /* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
+ * empty and full simultaneously
+ */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
+ error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
+#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
+ * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
+#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /* Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /* Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /* Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /* Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
+ */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+++ /dev/null
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-OUTS = *.o
-
-LIBSOURCES=*.c
-INCLUDEFILES=*.h
-
-libs:
- echo "Compiling tmrctr"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OUTS}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr.c
-*
-* Contains required functions for the XTmrCtr driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/16/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.05a adk 15/05/13 Fixed the CR:693066
-* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
-* XTmrCtr instance structure.
-* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
-* the XTmrCtr_Start function.
-* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
-* There will be no Initialization done in the
-* XTmrCtr_Initialize if both the timers have already started and
-* the XST_DEVICE_IS_STARTED Status is returned.
-* Removed the logic in the XTmrCtr_Initialize function
-* which was checking the Register Value to know whether
-* a timer has started or not.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xtmrctr.h"
-#include "xtmrctr_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific timer/counter instance/driver. Initialize fields of
-* the XTmrCtr structure, then reset the timer/counter.If a timer is already
-* running then it is not initialized.
-*
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param DeviceId is the unique id of the device controlled by this
-* XTmrCtr component. Passing in a device id associates the
-* generic XTmrCtr component to a specific device, as chosen by
-* the caller or application developer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_DEVICE_IS_STARTED if the device has already been started
-* - XST_DEVICE_NOT_FOUND if the device doesn't exist
-*
-* @note None.
-*
-******************************************************************************/
-int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId)
-{
- XTmrCtr_Config *TmrCtrConfigPtr;
- int TmrCtrNumber;
- int TmrCtrLowIndex = 0;
- int TmrCtrHighIndex = XTC_DEVICE_TIMER_COUNT;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
-
- /*
- * If both the timers have already started, disallow the initialize and
- * return a status indicating it is started. This allows the user to stop
- * the device and reinitialize, but prevents a user from inadvertently
- * initializing.
- * In case one of the timers has not started then that particular timer
- * will be initialized
- */
- if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED) &&
- (InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) {
- return XST_DEVICE_IS_STARTED;
- }
-
-
- /*
- * Ensure that only the timer which is NOT started can be initialized
- */
- if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED)) {
- TmrCtrLowIndex = 1;
- } else if ((InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) {
- TmrCtrHighIndex = 1;
- } else {
- InstancePtr->IsStartedTmrCtr0 = 0;
- InstancePtr->IsStartedTmrCtr1 = 0;
- }
-
-
-
- /*
- * Lookup the device configuration in the temporary CROM table. Use this
- * configuration info down below when initializing this component.
- */
- TmrCtrConfigPtr = XTmrCtr_LookupConfig(DeviceId);
-
- if (TmrCtrConfigPtr == (XTmrCtr_Config *) NULL) {
- return XST_DEVICE_NOT_FOUND;
- }
-
- /*
- * Set some default values, including setting the callback
- * handlers to stubs.
- */
- InstancePtr->BaseAddress = TmrCtrConfigPtr->BaseAddress;
- InstancePtr->Handler = NULL;
- InstancePtr->CallBackRef = NULL;
-
- /*
- * Clear the statistics for this driver
- */
- InstancePtr->Stats.Interrupts = 0;
-
- /* Initialize the registers of each timer/counter in the device */
-
- for (TmrCtrNumber = TmrCtrLowIndex; TmrCtrNumber < TmrCtrHighIndex;
- TmrCtrNumber++) {
-
- /*
- * Set the Compare register to 0
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TLR_OFFSET, 0);
- /*
- * Reset the timer and the interrupt, the reset bit will need to
- * be cleared after this
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
- /*
- * Set the control/status register to complete initialization by
- * clearing the reset bit which was just set
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, 0);
- }
-
- /*
- * Indicate the instance is ready to use, successfully initialized
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Starts the specified timer counter of the device such that it starts running.
-* The timer counter is reset before it is started and the reset value is
-* loaded into the timer counter.
-*
-* If interrupt mode is specified in the options, it is necessary for the caller
-* to connect the interrupt handler of the timer/counter to the interrupt source,
-* typically an interrupt controller, and enable the interrupt within the
-* interrupt controller.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 ControlStatusReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the current register contents such that only the necessary bits
- * of the register are modified in the following operations
- */
- ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Reset the timer counter such that it reloads from the compare
- * register and the interrupt is cleared simultaneously, the interrupt
- * can only be cleared after reset such that the interrupt condition is
- * cleared
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- XTC_CSR_LOAD_MASK);
-
-
-
- /*
- * Indicate that the timer is started before enabling it
- */
- if (TmrCtrNumber == 0) {
- InstancePtr->IsStartedTmrCtr0 = XIL_COMPONENT_IS_STARTED;
- } else {
- InstancePtr->IsStartedTmrCtr1 = XIL_COMPONENT_IS_STARTED;
- }
-
-
- /*
- * Remove the reset condition such that the timer counter starts running
- * with the value loaded from the compare register
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg | XTC_CSR_ENABLE_TMR_MASK);
-}
-
-/*****************************************************************************/
-/**
-*
-* Stops the timer counter by disabling it.
-*
-* It is the callers' responsibility to disconnect the interrupt handler of the
-* timer_counter from the interrupt source, typically an interrupt controller,
-* and disable the interrupt within the interrupt controller.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 ControlStatusReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the current register contents
- */
- ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Disable the timer counter such that it's not running
- */
- ControlStatusReg &= ~(XTC_CSR_ENABLE_TMR_MASK);
-
- /*
- * Write out the updated value to the actual register.
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, ControlStatusReg);
-
- /*
- * Indicate that the timer is stopped
- */
- if (TmrCtrNumber == 0) {
- InstancePtr->IsStartedTmrCtr0 = 0;
- } else {
- InstancePtr->IsStartedTmrCtr1 = 0;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the current value of the specified timer counter. The timer counter
-* may be either incrementing or decrementing based upon the current mode of
-* operation.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The current value for the timer counter.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCR_OFFSET);
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the reset value for the specified timer counter. This is the value
-* that is loaded into the timer counter when it is reset. This value is also
-* loaded when the timer counter is started.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param ResetValue contains the value to be used to reset the timer
-* counter.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
- u32 ResetValue)
-{
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TLR_OFFSET, ResetValue);
-}
-
-/*****************************************************************************/
-/**
-*
-* Returns the timer counter value that was captured the last time the external
-* capture input was asserted.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The current capture value for the indicated timer counter.
-*
-* @note None.
-*
-*******************************************************************************/
-u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TLR_OFFSET);
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the specified timer counter of the device. A reset causes the timer
-* counter to set it's value to the reset value.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 CounterControlReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read current contents of the register so it won't be destroyed
- */
- CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Reset the timer by toggling the reset bit in the register
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- CounterControlReg | XTC_CSR_LOAD_MASK);
-
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, CounterControlReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* Checks if the specified timer counter of the device has expired. In capture
-* mode, expired is defined as a capture occurred. In compare mode, expired is
-* defined as the timer counter rolled over/under for up/down counting.
-*
-* When interrupts are enabled, the expiration causes an interrupt. This function
-* is typically used to poll a timer counter to determine when it has expired.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return TRUE if the timer has expired, and FALSE otherwise.
-*
-* @note None.
-*
-******************************************************************************/
-int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 CounterControlReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check if timer is expired
- */
- CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
-
- return ((CounterControlReg & XTC_CSR_INT_OCCURED_MASK) ==
- XTC_CSR_INT_OCCURED_MASK);
-}
-
-/*****************************************************************************
-*
-* Looks up the device configuration based on the unique device ID. The table
-* TmrCtrConfigTable contains the configuration info for each device in the
-* system.
-*
-* @param DeviceId is the unique device ID to search for in the config
-* table.
-*
-* @return A pointer to the configuration that matches the given device ID,
-* or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId)
-{
- XTmrCtr_Config *CfgPtr = NULL;
- int Index;
-
- for (Index = 0; Index < XPAR_XTMRCTR_NUM_INSTANCES; Index++) {
- if (XTmrCtr_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XTmrCtr_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr.h
-*
-* The Xilinx timer/counter component. This component supports the Xilinx
-* timer/counter. More detailed description of the driver operation can
-* be found in the xtmrctr.c file.
-*
-* The Xilinx timer/counter supports the following features:
-* - Polled mode.
-* - Interrupt driven mode
-* - enabling and disabling specific timers
-* - PWM operation
-* - Cascade Operation (This is to be used for getting a 64 bit timer and this
-* feature is present in the latest versions of the axi_timer IP)
-*
-* The driver does not currently support the PWM operation of the device.
-*
-* The timer counter operates in 2 primary modes, compare and capture. In
-* either mode, the timer counter may count up or down, with up being the
-* default.
-*
-* Compare mode is typically used for creating a single time period or multiple
-* repeating time periods in the auto reload mode, such as a periodic interrupt.
-* When started, the timer counter loads an initial value, referred to as the
-* compare value, into the timer counter and starts counting down or up. The
-* timer counter expires when it rolls over/under depending upon the mode of
-* counting. An external compare output signal may be configured such that a
-* pulse is generated with this signal when it hits the compare value.
-*
-* Capture mode is typically used for measuring the time period between
-* external events. This mode uses an external capture input signal to cause
-* the value of the timer counter to be captured. When started, the timer
-* counter loads an initial value, referred to as the compare value,
-
-* The timer can be configured to either cause an interrupt when the count
-* reaches the compare value in compare mode or latch the current count
-* value in the capture register when an external input is asserted
-* in capture mode. The external capture input can be enabled/disabled using the
-* XTmrCtr_SetOptions function. While in compare mode, it is also possible to
-* drive an external output when the compare value is reached in the count
-* register The external compare output can be enabled/disabled using the
-* XTmrCtr_SetOptions function.
-*
-* <b>Interrupts</b>
-*
-* It is the responsibility of the application to connect the interrupt
-* handler of the timer/counter to the interrupt source. The interrupt
-* handler function, XTmrCtr_InterruptHandler, is visible such that the user
-* can connect it to the interrupt source. Note that this interrupt handler
-* does not provide interrupt context save and restore processing, the user
-* must perform this processing.
-*
-* The driver services interrupts and passes timeouts to the upper layer
-* software through callback functions. The upper layer software must register
-* its callback functions during initialization. The driver requires callback
-* functions for timers.
-*
-* @note
-* The default settings for the timers are:
-* - Interrupt generation disabled
-* - Count up mode
-* - Compare mode
-* - Hold counter (will not reload the timer)
-* - External compare output disabled
-* - External capture input disabled
-* - Pulse width modulation disabled
-* - Timer disabled, waits for Start function to be called
-* <br><br>
-* A timer counter device may contain multiple timer counters. The symbol
-* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device.
-* The device currently contains 2 timer counters.
-* <br><br>
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/16/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.10b mta 03/21/07 Updated to new coding style.
-* 1.11a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-* for naming consistency (CR 559142).
-* 2.02a sdm 09/28/10 Updated the driver tcl to generate the xparameters
-* for the timer clock frequency (CR 572679).
-* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further
-* processing for CR 584557.
-* 2.04a sdm 07/12/11 Added support for cascade mode operation.
-* The cascade mode of operation is present in the latest
-* versions of the axi_timer IP. Please check the HW
-* Datasheet to see whether this feature is present in the
-* version of the IP that you are using.
-* 2.05a adk 15/05/13 Fixed the CR:693066
-* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
-* XTmrCtr instance structure.
-* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
-* the XTmrCtr_Start function.
-* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
-* There will be no Initialization done in the
-* XTmrCtr_Initialize if both the timers have already started and
-* the XST_DEVICE_IS_STARTED Status is returned.
-* Removed the logic in the XTmrCtr_Initialize function
-* which was checking the Register Value to know whether
-* a timer has started or not.
-* 3.0 adk 19/12/13 Updated as per the New Tcl API's
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_H /* prevent circular inclusions */
-#define XTMRCTR_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xtmrctr_l.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name Configuration options
- * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions()
- * @{
- */
-/**
- * Used to configure the timer counter device.
- * <pre>
- * XTC_CASCADE_MODE_OPTION Enables the Cascade Mode only valid for TCSRO.
- * XTC_ENABLE_ALL_OPTION Enables all timer counters at once.
- * XTC_DOWN_COUNT_OPTION Configures the timer counter to count down from
- * start value, the default is to count up.
- * XTC_CAPTURE_MODE_OPTION Configures the timer to capture the timer
- * counter value when the external capture line is
- * asserted. The default mode is compare mode.
- * XTC_INT_MODE_OPTION Enables the timer counter interrupt output.
- * XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer counter to
- * reload from the compare value. The default mode
- * causes the timer counter to hold when the
- * compare value is hit.
- * In capture mode, configures the timer counter to
- * not hold the previous capture value if a new
- * event occurs. The default mode cause the timer
- * counter to hold the capture value until
- * recognized.
- * XTC_EXT_COMPARE_OPTION Enables the external compare output signal.
- * </pre>
- */
-#define XTC_CASCADE_MODE_OPTION 0x00000080UL
-#define XTC_ENABLE_ALL_OPTION 0x00000040UL
-#define XTC_DOWN_COUNT_OPTION 0x00000020UL
-#define XTC_CAPTURE_MODE_OPTION 0x00000010UL
-#define XTC_INT_MODE_OPTION 0x00000008UL
-#define XTC_AUTO_RELOAD_OPTION 0x00000004UL
-#define XTC_EXT_COMPARE_OPTION 0x00000002UL
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress;/**< Register base address */
-} XTmrCtr_Config;
-
-/**
- * Signature for the callback function.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions, and passed back to the
- * upper layer when the callback is invoked. Its type is
- * unimportant to the driver, so it is a void pointer.
- * @param TmrCtrNumber is the number of the timer/counter within the
- * device. The device typically contains at least two
- * timer/counters. The timer number is a zero based number with a
- * range of 0 to (XTC_DEVICE_TIMER_COUNT - 1).
- */
-typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber);
-
-
-/**
- * Timer/Counter statistics
- */
-typedef struct {
- u32 Interrupts; /**< The number of interrupts that have occurred */
-} XTmrCtrStats;
-
-/**
- * The XTmrCtr driver instance data. The user is required to allocate a
- * variable of this type for every timer/counter device in the system. A
- * pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XTmrCtrStats Stats; /**< Component Statistics */
- u32 BaseAddress; /**< Base address of registers */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStartedTmrCtr0; /**< Is Timer Counter 0 started */
- u32 IsStartedTmrCtr1; /**< Is Timer Counter 1 started */
-
- XTmrCtr_Handler Handler; /**< Callback function */
- void *CallBackRef; /**< Callback reference for handler */
-} XTmrCtr;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions, in file xtmrctr.c
- */
-int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId);
-void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
- u32 ResetValue);
-u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId);
-
-/*
- * Functions for options, in file xtmrctr_options.c
- */
-void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options);
-u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/*
- * Functions for statistics, in file xtmrctr_stats.c
- */
-void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr);
-void XTmrCtr_ClearStats(XTmrCtr * InstancePtr);
-
-/*
- * Functions for self-test, in file xtmrctr_selftest.c
- */
-int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
-
-/*
- * Functions for interrupts, in file xtmrctr_intr.c
- */
-void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
- void *CallBackRef);
-void XTmrCtr_InterruptHandler(void *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Driver configuration\r
-*\r
-*******************************************************************/\r
-\r
-#include "xparameters.h"\r
-#include "xtmrctr.h"\r
-\r
-/*\r
-* The configuration table for devices\r
-*/\r
-\r
-XTmrCtr_Config XTmrCtr_ConfigTable[] =\r
-{\r
- {\r
- XPAR_AXI_TIMER_0_DEVICE_ID,\r
- XPAR_AXI_TIMER_0_BASEADDR\r
- }\r
-};\r
-\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_i.h
-*
-* This file contains data which is shared between files internal to the
-* XTmrCtr component. It is intended for internal use only.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 _m is removed from all the macro definitions.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_I_H /* prevent circular inclusions */
-#define XTMRCTR_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-extern XTmrCtr_Config XTmrCtr_ConfigTable[];
-
-extern u8 XTmrCtr_Offsets[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_intr.c
-*
-* Contains interrupt-related functions for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further
-* processing for CR 584557.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr.h"
-
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Sets the timer callback function, which the driver calls when the specified
-* timer times out.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance .
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note
-*
-* The handler is called within interrupt context so the function that is
-* called should either be short or pass the more extensive processing off
-* to another task to allow the interrupt to return and normal processing
-* to continue.
-*
-******************************************************************************/
-void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
- void *CallBackRef)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = FuncPtr;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* Interrupt Service Routine (ISR) for the driver. This function only performs
-* processing for the device and does not save and restore the interrupt context.
-*
-* @param InstancePtr contains a pointer to the timer/counter instance for
-* the interrupt.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_InterruptHandler(void *InstancePtr)
-{
- XTmrCtr *TmrCtrPtr = NULL;
- u8 TmrCtrNumber;
- u32 ControlStatusReg;
-
- /*
- * Verify that each of the inputs are valid.
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Convert the non-typed pointer to an timer/counter instance pointer
- * such that there is access to the timer/counter
- */
- TmrCtrPtr = (XTmrCtr *) InstancePtr;
-
- /*
- * Loop thru each timer counter in the device and call the callback
- * function for each timer which has caused an interrupt
- */
- for (TmrCtrNumber = 0;
- TmrCtrNumber < XTC_DEVICE_TIMER_COUNT; TmrCtrNumber++) {
-
- ControlStatusReg = XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET);
- /*
- * Check if interrupt is enabled
- */
- if (ControlStatusReg & XTC_CSR_ENABLE_INT_MASK) {
-
- /*
- * Check if timer expired and interrupt occured
- */
- if (ControlStatusReg & XTC_CSR_INT_OCCURED_MASK) {
- /*
- * Increment statistics for the number of
- * interrupts and call the callback to handle
- * any application specific processing
- */
- TmrCtrPtr->Stats.Interrupts++;
- TmrCtrPtr->Handler(TmrCtrPtr->CallBackRef,
- TmrCtrNumber);
- /*
- * Read the new Control/Status Register content.
- */
- ControlStatusReg =
- XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET);
- /*
- * If in compare mode and a single shot rather
- * than auto reload mode then disable the timer
- * and reset it such so that the interrupt can
- * be acknowledged, this should be only temporary
- * till the hardware is fixed
- */
- if (((ControlStatusReg &
- XTC_CSR_AUTO_RELOAD_MASK) == 0) &&
- ((ControlStatusReg &
- XTC_CSR_CAPTURE_MODE_MASK)== 0)) {
- /*
- * Disable the timer counter and
- * reset it such that the timer
- * counter is loaded with the
- * reset value allowing the
- * interrupt to be acknowledged
- */
- ControlStatusReg &=
- ~XTC_CSR_ENABLE_TMR_MASK;
-
- XTmrCtr_WriteReg(
- TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg |
- XTC_CSR_LOAD_MASK);
-
- /*
- * Clear the reset condition,
- * the reset bit must be
- * manually cleared by a 2nd write
- * to the register
- */
- XTmrCtr_WriteReg(
- TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg);
- }
-
- /*
- * Acknowledge the interrupt by clearing the
- * interrupt bit in the timer control status
- * register, this is done after calling the
- * handler so the application could call
- * IsExpired, the interrupt is cleared by
- * writing a 1 to the interrupt bit of the
- * register without changing any of the other
- * bits
- */
- XTmrCtr_WriteReg(TmrCtrPtr->BaseAddress,
- TmrCtrNumber,
- XTC_TCSR_OFFSET,
- ControlStatusReg |
- XTC_CSR_INT_OCCURED_MASK);
- }
- }
- }
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_l.c
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 04/24/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's
-* </pre>
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr_l.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/* The following table contains the offset from the base address of a timer
- * counter device for each timer counter. A single device may contain multiple
- * timer counters and the functions specify which one to operate on.
- */
-u8 XTmrCtr_Offsets[] = { 0, XTC_TIMER_COUNTER_OFFSET };
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* High-level driver functions are defined in xtmrctr.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 04/24/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
-* for naming consistency (CR 559142).
-* 2.04a sdm 07/12/11 Added the CASC mode bit in the TCSRO register for the
-* cascade mode operation.
-* The cascade mode of operation is present in the latest
-* versions of the axi_timer IP. Please check the HW
-* Datasheet to see whether this feature is present in the
-* version of the IP that you are using.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XTMRCTR_L_H /* prevent circular inclusions */
-#define XTMRCTR_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * Defines the number of timer counters within a single hardware device. This
- * number is not currently parameterized in the hardware but may be in the
- * future.
- */
-#define XTC_DEVICE_TIMER_COUNT 2
-
-/* Each timer counter consumes 16 bytes of address space */
-
-#define XTC_TIMER_COUNTER_OFFSET 16
-
-/** @name Register Offset Definitions
- * Register offsets within a timer counter, there are multiple
- * timer counters within a single device
- * @{
- */
-
-#define XTC_TCSR_OFFSET 0 /**< Control/Status register */
-#define XTC_TLR_OFFSET 4 /**< Load register */
-#define XTC_TCR_OFFSET 8 /**< Timer counter register */
-
-/* @} */
-
-/** @name Control Status Register Bit Definitions
- * Control Status Register bit masks
- * Used to configure the timer counter device.
- * @{
- */
-
-#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */
-#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer
- counters */
-#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width
- Modulation */
-#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an
- interrupt has occured.
- If set and '1' is
- written to this bit
- position, bit is
- cleared. */
-#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the
- specific timer */
-#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt
- output. */
-#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using
- the load value provided
- earlier in the Load
- Register,
- XTC_TLR_OFFSET. */
-#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode,
- configures
- the timer counter to
- reload from the
- Load Register. The
- default mode
- causes the timer counter
- to hold when the compare
- value is hit. In capture
- mode, configures the
- timer counter to not
- hold the previous
- capture value if a new
- event occurs. The
- default mode cause the
- timer counter to hold
- the capture value until
- recognized. */
-#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the
- external input
- to the timer counter. */
-#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the
- external generate output
- for the timer. */
-#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer
- counter to count down
- from start value, the
- default is to count
- up.*/
-#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to
- capture the timer
- counter value when the
- external capture line is
- asserted. The default
- mode is compare mode.*/
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-extern u8 XTmrCtr_Offsets[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Read one of the timer counter registers.
-*
-* @param BaseAddress contains the base address of the timer counter
-* device.
-* @param TmrCtrNumber contains the specific timer counter within the
-* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegOffset contains the offset from the 1st register of the timer
-* counter to select the specific register of the timer counter.
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
- unsigned RegOffset);
-******************************************************************************/
-#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (RegOffset))
-
-#ifndef XTimerCtr_ReadReg
-#define XTimerCtr_ReadReg XTmrCtr_ReadReg
-#endif
-
-/*****************************************************************************/
-/**
-* Write a specified value to a register of a timer counter.
-*
-* @param BaseAddress is the base address of the timer counter device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegOffset contain the offset from the 1st register of the timer
-* counter to select the specific register of the timer counter.
-* @param ValueToWrite is the 32 bit value to be written to the register.
-*
-* @note C-Style signature:
-* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
-* unsigned RegOffset, u32 ValueToWrite);
-******************************************************************************/
-#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (RegOffset)), (ValueToWrite))
-
-/****************************************************************************/
-/**
-*
-* Set the Control Status Register of a timer counter to the specified value.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegisterValue is the 32 bit value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
-* u8 TmrCtrNumber,u32 RegisterValue);
-*****************************************************************************/
-#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the Control Status Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
-* u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Get the Timer Counter Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
-* u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
-
-/****************************************************************************/
-/**
-*
-* Set the Load Register of a timer counter to the specified value.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param RegisterValue is the 32 bit value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
-* u32 RegisterValue);
-*****************************************************************************/
-#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the Load Register of a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return The value read from the register, a 32 bit value.
-*
-* @note C-Style signature:
-* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \
-XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable a timer counter such that it starts running.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
- XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable a timer counter such that it stops running.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device,
-* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
- XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
-
-/****************************************************************************/
-/**
-*
-* Enable the interrupt for a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the interrupt for a timer counter.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK))
-
-/****************************************************************************/
-/**
-*
-* Cause the timer counter to load it's Timer Counter Register with the value
-* in the Load Register.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
- u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \
- XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
- XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Determine if a timer counter event has occurred. Events are defined to be
-* when a capture has occurred or the counter has roller over.
-*
-* @param BaseAddress is the base address of the device.
-* @param TmrCtrNumber is the specific timer counter within the device, a
-* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @note C-Style signature:
-* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
-*****************************************************************************/
-#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \
- ((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \
- XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \
- XTC_CSR_INT_OCCURED_MASK)
-
-/************************** Function Prototypes ******************************/
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_options.c
-*
-* Contains configuration options functions for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* 2.04a sdm 07/12/11 Added support for the cascade mode operation.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr.h"
-#include "xtmrctr_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/*
- * The following data type maps an option to a register mask such that getting
- * and setting the options may be table driven.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
-} Mapping;
-
-/*
- * Create the table which contains options which are to be processed to get/set
- * the options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-static Mapping OptionsTable[] = {
- {XTC_CASCADE_MODE_OPTION, XTC_CSR_CASC_MASK},
- {XTC_ENABLE_ALL_OPTION, XTC_CSR_ENABLE_ALL_MASK},
- {XTC_DOWN_COUNT_OPTION, XTC_CSR_DOWN_COUNT_MASK},
- {XTC_CAPTURE_MODE_OPTION, XTC_CSR_CAPTURE_MODE_MASK |
- XTC_CSR_EXT_CAPTURE_MASK},
- {XTC_INT_MODE_OPTION, XTC_CSR_ENABLE_INT_MASK},
- {XTC_AUTO_RELOAD_OPTION, XTC_CSR_AUTO_RELOAD_MASK},
- {XTC_EXT_COMPARE_OPTION, XTC_CSR_EXT_GENERATE_MASK}
-};
-
-/* Create a constant for the number of entries in the table */
-
-#define XTC_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
-
-/*****************************************************************************/
-/**
-*
-* Enables the specified options for the specified timer counter. This function
-* sets the options without regard to the current options of the driver. To
-* prevent a loss of the current options, the user should call
-* XTmrCtr_GetOptions() prior to this function and modify the retrieved options
-* to pass into this function to prevent loss of the current options.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-* @param Options contains the desired options to be set or cleared.
-* Setting the option to '1' enables the option, clearing the to
-* '0' disables the option. The options are bit masks such that
-* multiple options may be set or cleared. The options are
-* described in xtmrctr.h.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options)
-{
- u32 CounterControlReg = 0;
- u32 Index;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop through the Options table, turning the enable on or off
- * depending on whether the bit is set in the incoming Options flag.
- */
-
- for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
- if (Options & OptionsTable[Index].Option) {
-
- /*
- * Turn the option on
- */
- CounterControlReg |= OptionsTable[Index].Mask;
- }
- else {
- /*
- * Turn the option off
- */
- CounterControlReg &= ~OptionsTable[Index].Mask;
- }
- }
-
- /*
- * Write out the updated value to the actual register
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, CounterControlReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the options for the specified timer counter.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return
-*
-* The currently set options. An option which is set to a '1' is enabled and
-* set to a '0' is disabled. The options are bit masks such that multiple
-* options may be set or cleared. The options are described in xtmrctr.h.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
-
- u32 Options = 0;
- u32 CounterControlReg;
- u32 Index;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the current contents of the control status register to allow
- * the current options to be determined
- */
- CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCSR_OFFSET);
- /*
- * Loop through the Options table, turning the enable on or off
- * depending on whether the bit is set in the current register settings.
- */
- for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) {
- if (CounterControlReg & OptionsTable[Index].Mask) {
- Options |= OptionsTable[Index].Option; /* turn it on */
- }
- else {
- Options &= ~OptionsTable[Index].Option; /* turn it off */
- }
- }
-
- return Options;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_selftest.c
-*
-* Contains diagnostic/self-test functions for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release
-* 1.10b mta 03/21/07 Updated to new coding style
-* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro
-* definitions.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-#include "xtmrctr.h"
-#include "xtmrctr_i.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device. This test verifies that the specified
-* timer counter of the device can be enabled and increments.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param TmrCtrNumber is the timer counter of the device to operate on.
-* Each device may contain multiple timer counters. The timer
-* number is a zero based number with a range of
-* 0 - (XTC_DEVICE_TIMER_COUNT - 1).
-*
-* @return
-* - XST_SUCCESS if self-test was successful
-* - XST_FAILURE if the timer is not incrementing.
-*
-* @note
-*
-* This is a destructive test using the provided timer. The current settings
-* of the timer are returned to the initialized values and all settings at the
-* time this function is called are overwritten.
-*
-******************************************************************************/
-int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber)
-{
- u32 TimerCount1 = 0;
- u32 TimerCount2 = 0;
- u16 Count = 0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Set the Capture register to 0
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TLR_OFFSET, 0);
-
- /*
- * Reset the timer and the interrupt
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
-
- /*
- * Set the control/status register to enable timer
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, XTC_CSR_ENABLE_TMR_MASK);
-
- /*
- * Read the timer
- */
- TimerCount1 = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCR_OFFSET);
- /*
- * Make sure timer is incrementing if the Count rolls over to zero
- * and the timer still has not incremented an error is returned
- */
-
- do {
- TimerCount2 = XTmrCtr_ReadReg(InstancePtr->BaseAddress,
- TmrCtrNumber, XTC_TCR_OFFSET);
- Count++;
- }
- while ((TimerCount1 == TimerCount2) && (Count != 0));
-
- /*
- * Reset the timer and the interrupt
- */
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET,
- XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
-
- /*
- * Set the control/status register to 0 to complete initialization
- * this disables the timer completely and allows it to be used again
- */
-
- XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber,
- XTC_TCSR_OFFSET, 0);
-
- if (TimerCount1 == TimerCount2) {
- return XST_FAILURE;
- }
- else {
- return XST_SUCCESS;
- }
-}
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xtmrctr_stats.c
-*
-* Contains function to get and clear statistics for the XTmrCtr component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 02/06/02 First release.
-* 1.10b mta 03/21/07 Updated for new coding style.
-* 2.00a ktn 10/30/09 Updated to use HAL API's.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xtmrctr.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Get a copy of the XTmrCtrStats structure, which contains the current
-* statistics for this driver.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-* @param StatsPtr is a pointer to a XTmrCtrStats structure which will get
-* a copy of current statistics.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(StatsPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- StatsPtr->Interrupts = InstancePtr->Stats.Interrupts;
-}
-
-/*****************************************************************************/
-/**
-*
-* Clear the XTmrCtrStats structure for this driver.
-*
-* @param InstancePtr is a pointer to the XTmrCtr instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XTmrCtr_ClearStats(XTmrCtr * InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Stats.Interrupts = 0;
-}
+++ /dev/null
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-LEVEL=0
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-
-OUTS = *.o
-
-libs:
- echo "Compiling uartlite"
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
- $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
- make clean
-
-include:
- ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -rf ${OUTS}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite.c
-*
-* Contains required functions for the XUartLite driver. See the xuartlite.h
-* header file for more details on this driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/31/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.00b rmm 05/13/03 Fixed diab compiler warnings relating to asserts
-* 1.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
-* CfgInitialize() take a pointer to a config structure
-* instead of a device id. Moved Initialize() into
-* xgpio_sinit.c, and had Initialize() call CfgInitialize()
-* after it retrieved the config structure using the device
-* id. Removed include of xparameters.h along with any
-* dependencies on xparameters.h and the _g.c config table.
-* 1.01a wsy 05/08/06 fix CR220811 and CR224103.
-* 1.12a mta 03/31/07 Updated to new coding conventions
-* 1.13a sv 01/21/08 Updated driver to support access through DCR bus
-* 1.14a sdm 09/26/08 Updated code to avoid race condition in
-* XUartLite_SendBuffer
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
-* renamed to remove _m from the name. XUartLite_mClearStats
-* macro is removed and XUartLite_ClearStats function should
-* be used in its place.
-* 2.00a hvm 08/11/11 Removed the SetOptions related information in the
-* Recv and RecvBuffer function header notes section.
-* CR620849.
-* 2.01a adk 18/04/13 Updated the code to avoid unused variable
-* warnings when compiling with the -Wextra -Wall flags
-* In the file xuartlite.c. CR:704999.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartlite.h"
-#include "xuartlite_i.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static void StubHandler(void *CallBackRef, unsigned int ByteCount);
-
-/****************************************************************************/
-/**
-*
-* Initialize a XUartLite instance. The receive and transmit FIFOs of the
-* UART are not flushed, so the user may want to flush them. The hardware
-* device does not have any way to disable the receiver such that any valid
-* data may be present in the receive FIFO. This function disables the UART
-* interrupt. The baudrate and format of the data are fixed in the hardware
-* at hardware build time.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-* @param Config is a reference to a structure containing information
-* about a specific UART Lite device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config. This function can initialize multiple
-* instance objects with the use of multiple calls giving different
-* Config information on each call.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* Config->BaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS if everything starts up as expected.
-*
-* @note The Config pointer argument is not used by this function,
-* but is provided to keep the function signature consistent
-* with other drivers.
-*
-*****************************************************************************/
-int XUartLite_CfgInitialize(XUartLite *InstancePtr, XUartLite_Config *Config,
- u32 EffectiveAddr)
-{
- (void) Config;
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Set some default values, including setting the callback
- * handlers to stubs.
- */
- InstancePtr->SendBuffer.NextBytePtr = NULL;
- InstancePtr->SendBuffer.RemainingBytes = 0;
- InstancePtr->SendBuffer.RequestedBytes = 0;
-
- InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
- InstancePtr->ReceiveBuffer.RemainingBytes = 0;
- InstancePtr->ReceiveBuffer.RequestedBytes = 0;
-
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
- InstancePtr->RegBaseAddress = ((EffectiveAddr >> 2)) & 0xFFF;
-#else
- InstancePtr->RegBaseAddress = EffectiveAddr;
-#endif
-
- InstancePtr->RecvHandler = StubHandler;
- InstancePtr->SendHandler = StubHandler;
-
- /* Write to the control register to disable the interrupts, don't
- * reset the FIFOs are the user may want the data that's present
- */
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, 0);
-
- /*
- * Clear the statistics for this driver
- */
- XUartLite_ClearStats(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sends the specified buffer of data using the UART in either
-* polled or interrupt driven modes. This function is non-blocking such that it
-* will return before the data has been sent by the UART. If the UART is busy
-* sending data, it will return and indicate zero bytes were sent.
-*
-* In a polled mode, this function will only send as much data as the UART can
-* buffer in the FIFO. The application may need to call it repeatedly to
-* send a buffer.
-*
-* In interrupt mode, this function will start sending the specified buffer and
-* then the interrupt handler of the driver will continue sending data until the
-* buffer has been sent. A callback function, as specified by the application,
-* will be called to indicate the completion of sending the buffer.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-* @param DataBufferPtr is pointer to a buffer of data to be sent.
-* @param NumBytes contains the number of bytes to be sent. A value of
-* zero will stop a previous send operation that is in progress
-* in interrupt mode. Any data that was already put into the
-* transmit FIFO will be sent.
-*
-* @return The number of bytes actually sent.
-*
-* @note The number of bytes is not asserted so that this function may
-* be called with a value of zero to stop an operation that is
-* already in progress.
-*
-******************************************************************************/
-unsigned int XUartLite_Send(XUartLite *InstancePtr, u8 *DataBufferPtr,
- unsigned int NumBytes)
-{
- unsigned int BytesSent;
- u32 StatusRegister;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(DataBufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(((signed)NumBytes) >= 0);
-
- /*
- * Enter a critical region by disabling the UART interrupts to allow
- * this call to stop a previous operation that may be interrupt driven.
- */
- StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
-
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, 0);
-
- /*
- * Setup the specified buffer to be sent by setting the instance
- * variables so it can be sent with polled or interrupt mode
- */
- InstancePtr->SendBuffer.RequestedBytes = NumBytes;
- InstancePtr->SendBuffer.RemainingBytes = NumBytes;
- InstancePtr->SendBuffer.NextBytePtr = DataBufferPtr;
-
- /*
- * Restore the interrupt enable register to it's previous value such
- * that the critical region is exited.
- * This is done here to minimize the amount of time the interrupt is
- * disabled since there is only one interrupt and the receive could
- * be filling up while interrupts are blocked.
- */
-
- StatusRegister &= XUL_CR_ENABLE_INTR;
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, StatusRegister);
-
- /*
- * Send the buffer using the UART and return the number of bytes sent
- */
- BytesSent = XUartLite_SendBuffer(InstancePtr);
-
- return BytesSent;
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function will attempt to receive a specified number of bytes of data
-* from the UART and store it into the specified buffer. This function is
-* designed for either polled or interrupt driven modes. It is non-blocking
-* such that it will return if no data has already received by the UART.
-*
-* In a polled mode, this function will only receive as much data as the UART
-* can buffer in the FIFO. The application may need to call it repeatedly to
-* receive a buffer. Polled mode is the default mode of operation for the driver.
-*
-* In interrupt mode, this function will start receiving and then the interrupt
-* handler of the driver will continue receiving data until the buffer has been
-* received. A callback function, as specified by the application, will be called
-* to indicate the completion of receiving the buffer or when any receive errors
-* or timeouts occur.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-* @param DataBufferPtr is pointer to buffer for data to be received into.
-* @param NumBytes is the number of bytes to be received. A value of zero
-* will stop a previous receive operation that is in progress in
-* interrupt mode.
-*
-* @return The number of bytes received.
-*
-* @note The number of bytes is not asserted so that this function
-* may be called with a value of zero to stop an operation
-* that is already in progress.
-*
-*****************************************************************************/
-unsigned int XUartLite_Recv(XUartLite *InstancePtr, u8 *DataBufferPtr,
- unsigned int NumBytes)
-{
- unsigned int ReceivedCount;
- u32 StatusRegister;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(DataBufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(((signed)NumBytes) >= 0);
-
- /*
- * Enter a critical region by disabling all the UART interrupts to allow
- * this call to stop a previous operation that may be interrupt driven
- */
- StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, 0);
-
- /*
- * Setup the specified buffer to be received by setting the instance
- * variables so it can be received with polled or interrupt mode
- */
- InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
- InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
- InstancePtr->ReceiveBuffer.NextBytePtr = DataBufferPtr;
-
- /*
- * Restore the interrupt enable register to it's previous value such
- * that the critical region is exited
- */
- StatusRegister &= XUL_CR_ENABLE_INTR;
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, StatusRegister);
-
- /*
- * Receive the data from the UART and return the number of bytes
- * received
- * This is done here to minimize the amount of time the interrupt is
- * disabled since there is only one interrupt and the transmit could
- * be emptying out while interrupts are blocked.
- */
- ReceivedCount = XUartLite_ReceiveBuffer(InstancePtr);
-
- return ReceivedCount;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function resets the FIFOs, both transmit and receive, of the UART such
-* that they are emptied. Since the UART does not have any way to disable it
-* from receiving data, it may be necessary for the application to reset the
-* FIFOs to get rid of any unwanted data.
-*
-* @param InstancePtr is a pointer to the XUartLite instance .
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartLite_ResetFifos(XUartLite *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the status register 1st such that the next write to the control
- * register won't destroy the state of the interrupt enable bit
- */
- Register = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
- XUL_STATUS_REG_OFFSET);
-
- /*
- * Mask off the interrupt enable bit to maintain it's state.
- */
- Register &= XUL_SR_INTR_ENABLED;
-
- /*
- * Write to the control register to reset both FIFOs, these bits are
- * self-clearing such that there's no need to clear them
- */
- XUartLite_WriteReg(InstancePtr->RegBaseAddress, XUL_CONTROL_REG_OFFSET,
- Register | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function determines if the specified UART is sending data. If the
-* transmitter register is not empty, it is sending data.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return A value of TRUE if the UART is sending data, otherwise FALSE.
-*
-* @note None.
-*
-*****************************************************************************/
-int XUartLite_IsSending(XUartLite *InstancePtr)
-{
- u32 StatusRegister;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Read the status register to determine if the transmitter is empty
- */
- StatusRegister = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
- XUL_STATUS_REG_OFFSET);
-
- /*
- * If the transmitter is not empty then indicate that the UART is still
- * sending some data
- */
- return ((StatusRegister & XUL_SR_TX_FIFO_EMPTY) == 0);
-}
-
-
-/****************************************************************************
-*
-* This function provides a stub handler such that if the application does not
-* define a handler but enables interrupts, this function will be called.
-*
-* @param CallBackRef has no purpose but is necessary to match the
-* interface for a handler.
-* @param ByteCount has no purpose but is necessary to match the
-* interface for a handler.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void StubHandler(void *CallBackRef, unsigned int ByteCount)
-{
- (void) CallBackRef;
- (void) ByteCount;
- /*
- * Assert occurs always since this is a stub and should never be called
- */
- Xil_AssertVoidAlways();
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function sends a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is designed to be
-* an internal function for the XUartLite component such that it may be called
-* from a shell function that sets up the buffer or from an interrupt handler.
-*
-* This function sends the specified buffer of data to the UART in either
-* polled or interrupt driven modes. This function is non-blocking such that
-* it will return before the data has been sent by the UART.
-*
-* In a polled mode, this function will only send as much data as the UART can
-* buffer, either in the transmitter or in the FIFO if present and enabled.
-* The application may need to call it repeatedly to send a buffer.
-*
-* In interrupt mode, this function will start sending the specified buffer and
-* then the interrupt handler of the driver will continue until the buffer
-* has been sent. A callback function, as specified by the application, will
-* be called to indicate the completion of sending the buffer.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return NumBytes is the number of bytes actually sent (put into the
-* UART transmitter and/or FIFO).
-*
-* @note None.
-*
-*****************************************************************************/
-unsigned int XUartLite_SendBuffer(XUartLite *InstancePtr)
-{
- unsigned int SentCount = 0;
- u8 StatusRegister;
- u8 IntrEnableStatus;
-
- /*
- * Read the status register to determine if the transmitter is full
- */
- StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
-
- /*
- * Enter a critical region by disabling all the UART interrupts to allow
- * this call to stop a previous operation that may be interrupt driven
- */
- StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, 0);
-
- /*
- * Save the status register contents to restore the interrupt enable
- * register to it's previous value when that the critical region is
- * exited
- */
- IntrEnableStatus = StatusRegister;
-
- /*
- * Fill the FIFO from the the buffer that was specified
- */
-
- while (((StatusRegister & XUL_SR_TX_FIFO_FULL) == 0) &&
- (SentCount < InstancePtr->SendBuffer.RemainingBytes)) {
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_TX_FIFO_OFFSET,
- InstancePtr->SendBuffer.NextBytePtr[
- SentCount]);
-
- SentCount++;
-
- StatusRegister =
- XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
-
- }
-
- /*
- * Update the buffer to reflect the bytes that were sent from it
- */
- InstancePtr->SendBuffer.NextBytePtr += SentCount;
- InstancePtr->SendBuffer.RemainingBytes -= SentCount;
-
- /*
- * Increment associated counters
- */
- InstancePtr->Stats.CharactersTransmitted += SentCount;
-
- /*
- * Restore the interrupt enable register to it's previous value such
- * that the critical region is exited
- */
- IntrEnableStatus &= XUL_CR_ENABLE_INTR;
- XUartLite_WriteReg(InstancePtr->RegBaseAddress, XUL_CONTROL_REG_OFFSET,
- IntrEnableStatus);
-
- /*
- * Return the number of bytes that were sent, althought they really were
- * only put into the FIFO, not completely sent yet
- */
- return SentCount;
-}
-
-/****************************************************************************/
-/**
-*
-* This function receives a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is designed to be
-* an internal function for the XUartLite component such that it may be called
-* from a shell function that sets up the buffer or from an interrupt handler.
-*
-* This function will attempt to receive a specified number of bytes of data
-* from the UART and store it into the specified buffer. This function is
-* designed for either polled or interrupt driven modes. It is non-blocking
-* such that it will return if there is no data has already received by the
-* UART.
-*
-* In a polled mode, this function will only receive as much data as the UART
-* can buffer, either in the receiver or in the FIFO if present and enabled.
-* The application may need to call it repeatedly to receive a buffer. Polled
-* mode is the default mode of operation for the driver.
-*
-* In interrupt mode, this function will start receiving and then the interrupt
-* handler of the driver will continue until the buffer has been received. A
-* callback function, as specified by the application, will be called to indicate
-* the completion of receiving the buffer or when any receive errors or timeouts
-* occur.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return The number of bytes received.
-*
-* @note None.
-*
-*****************************************************************************/
-unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr)
-{
- u8 StatusRegister;
- unsigned int ReceivedCount = 0;
-
- /*
- * Loop until there is not more data buffered by the UART or the
- * specified number of bytes is received
- */
-
- while (ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes) {
- /*
- * Read the Status Register to determine if there is any data in
- * the receiver/FIFO
- */
- StatusRegister =
- XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
-
- /*
- * If there is data ready to be removed, then put the next byte
- * received into the specified buffer and update the stats to
- * reflect any receive errors for the byte
- */
- if (StatusRegister & XUL_SR_RX_FIFO_VALID_DATA) {
- InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount++]=
- XUartLite_ReadReg(InstancePtr->RegBaseAddress,
- XUL_RX_FIFO_OFFSET);
-
- XUartLite_UpdateStats(InstancePtr, StatusRegister);
- }
-
- /*
- * There's no more data buffered, so exit such that this
- * function does not block waiting for data
- */
- else {
- break;
- }
- }
-
- /*
- * Enter a critical region by disabling all the UART interrupts to allow
- * this call to stop a previous operation that may be interrupt driven
- */
- StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, 0);
-
- /*
- * Update the receive buffer to reflect the number of bytes that was
- * received
- */
- InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
- InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
-
- /*
- * Increment associated counters in the statistics
- */
- InstancePtr->Stats.CharactersReceived += ReceivedCount;
-
- /*
- * Restore the interrupt enable register to it's previous value such
- * that the critical region is exited
- */
- StatusRegister &= XUL_CR_ENABLE_INTR;
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, StatusRegister);
-
- return ReceivedCount;
-}
-
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite.h
-*
-* This component contains the implementation of the XUartLite component which is
-* the driver for the Xilinx UART Lite device. This UART is a minimal hardware
-* implementation with minimal features. Most of the features, including baud
-* rate, parity, and number of data bits are only configurable when the hardware
-* device is built, rather than at run time by software.
-*
-* The device has 16 byte transmit and receive FIFOs and supports interrupts.
-* The device does not have any way to disable the receiver such that the
-* receive FIFO may contain unwanted data. The FIFOs are not flushed when the
-* driver is initialized, but a function is provided to allow the user to
-* reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated when the transmit FIFO
-* transitions from having data to being empty or when any data is contained in
-* the receive FIFO.
-*
-* In order to use interrupts, it's necessary for the user to connect the driver
-* interrupt handler, XUartLite_InterruptHandler, to the interrupt system of the
-* application. This function does not save and restore the processor context
-* such that the user must provide it. Send and receive handlers may be set for
-* the driver such that the handlers are called when transmit and receive
-* interrupts occur. The handlers are called from interrupt context and are
-* designed to allow application specific processing to be performed.
-*
-* The functions, XUartLite_Send and XUartLite_Recv, are provided in the driver
-* to allow data to be sent and received. They are designed to be used in
-* polled or interrupt modes.
-*
-* The driver provides a status for each received byte indicating any parity
-* frame or overrun error. The driver provides statistics which allow visibility
-* into these errors.
-*
-* <b>Initialization & Configuration</b>
-*
-* The XUartLite_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XUartLite_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XUartLite_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* <b>RTOS Independence</b>
-*
-* This driver is intended to be RTOS and processor independent. It works
-* with physical addresses only. Any needs for dynamic memory management,
-* threads or thread mutual exclusion, virtual memory, or cache control must
-* be satisfied by the layer above this driver.
-*
-* @note
-*
-* The driver is partitioned such that a minimal implementation may be used.
-* More features require additional files to be linked in.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/31/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 1.02a rpm 02/14/07 Added check for outstanding transmission before
-* calling the send callback (avoids extraneous
-* callback invocations) in interrupt service routine.
-* 1.12a mta 03/31/07 Updated to new coding conventions
-* 1.13a sv 01/21/08 Updated driver to support access through DCR bus
-* 1.14a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 1.14a sdm 09/26/08 Updated code to avoid race condition in
-* XUartLite_SendBuffer
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
-* renamed to remove _m from the name. XUartLite_mClearStats
-* macro is removed and XUartLite_ClearStats function should
-* be used in its place.
-* 2.01a adk 18/04/13 Updated the code to avoid unused variable
-* warnings when compiling with the -Wextra -Wall flags
-* In the file xuartlite.c. CR:704999.
-* Added notes for CR 710483 that the XUL_FIFO_SIZE is not
-* used in the driver. This is the size of the FIFO for
-* Transmit/Receive FIFOs which cannot be changed.
-* 3.0 adk 17/12/13 Fixed CR:741186,761863 Changes are made in the file
-* xuartlite_selftest.c
-* 3.0 adk 19/12/13 Update the driver as per new TCL API's
-*
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTLITE_H /* prevent circular inclusions */
-#define XUARTLITE_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * Callback function. The first argument is a callback reference passed in by
- * the upper layer when setting the callback functions, and passed back to the
- * upper layer when the callback is invoked.
- * The second argument is the ByteCount which is the number of bytes that
- * actually moved from/to the buffer provided in the _Send/_Receive call.
- */
-typedef void (*XUartLite_Handler)(void *CallBackRef, unsigned int ByteCount);
-
-/**
- * Statistics for the XUartLite driver
- */
-typedef struct {
- u32 TransmitInterrupts; /**< Number of transmit interrupts */
- u32 ReceiveInterrupts; /**< Number of receive interrupts */
- u32 CharactersTransmitted; /**< Number of characters transmitted */
- u32 CharactersReceived; /**< Number of characters received */
- u32 ReceiveOverrunErrors; /**< Number of receive overruns */
- u32 ReceiveParityErrors; /**< Number of receive parity errors */
- u32 ReceiveFramingErrors; /**< Number of receive framing errors */
-} XUartLite_Stats;
-
-/**
- * The following data type is used to manage the buffers that are handled
- * when sending and receiving data in the interrupt mode. It is intended
- * for internal use only.
- */
-typedef struct {
- u8 *NextBytePtr;
- unsigned int RequestedBytes;
- unsigned int RemainingBytes;
-} XUartLite_Buffer;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 RegBaseAddr; /**< Register base address */
- u32 BaudRate; /**< Fixed baud rate */
- u8 UseParity; /**< Parity generator enabled when TRUE */
- u8 ParityOdd; /**< Parity generated is odd when TRUE, even
- when FALSE */
- u8 DataBits; /**< Fixed data bits */
-} XUartLite_Config;
-
-/**
- * The XUartLite driver instance data. The user is required to allocate a
- * variable of this type for every UART Lite device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUartLite_Stats Stats; /* Component Statistics */
- u32 RegBaseAddress; /* Base address of registers */
- u32 IsReady; /* Device is initialized and ready */
-
- XUartLite_Buffer SendBuffer;
- XUartLite_Buffer ReceiveBuffer;
-
- XUartLite_Handler RecvHandler;
- void *RecvCallBackRef; /* Callback ref for recv handler */
- XUartLite_Handler SendHandler;
- void *SendCallBackRef; /* Callback ref for send handler */
-} XUartLite;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xuartlite_sinit.c
- */
-int XUartLite_Initialize(XUartLite *InstancePtr, u16 DeviceId);
-XUartLite_Config *XUartLite_LookupConfig(u16 DeviceId);
-
-/*
- * Required functions, in file xuart.c
- */
-int XUartLite_CfgInitialize(XUartLite *InstancePtr,
- XUartLite_Config *Config,
- u32 EffectiveAddr);
-
-void XUartLite_ResetFifos(XUartLite *InstancePtr);
-
-unsigned int XUartLite_Send(XUartLite *InstancePtr, u8 *DataBufferPtr,
- unsigned int NumBytes);
-unsigned int XUartLite_Recv(XUartLite *InstancePtr, u8 *DataBufferPtr,
- unsigned int NumBytes);
-
-int XUartLite_IsSending(XUartLite *InstancePtr);
-
-/*
- * Functions for statistics, in file xuartlite_stats.c
- */
-void XUartLite_GetStats(XUartLite *InstancePtr, XUartLite_Stats *StatsPtr);
-void XUartLite_ClearStats(XUartLite *InstancePtr);
-
-/*
- * Functions for self-test, in file xuartlite_selftest.c
- */
-int XUartLite_SelfTest(XUartLite *InstancePtr);
-
-/*
- * Functions for interrupts, in file xuartlite_intr.c
- */
-void XUartLite_EnableInterrupt(XUartLite *InstancePtr);
-void XUartLite_DisableInterrupt(XUartLite *InstancePtr);
-
-void XUartLite_SetRecvHandler(XUartLite *InstancePtr, XUartLite_Handler FuncPtr,
- void *CallBackRef);
-void XUartLite_SetSendHandler(XUartLite *InstancePtr, XUartLite_Handler FuncPtr,
- void *CallBackRef);
-
-void XUartLite_InterruptHandler(XUartLite *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
+++ /dev/null
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Driver configuration\r
-*\r
-*******************************************************************/\r
-\r
-#include "xparameters.h"\r
-#include "xuartlite.h"\r
-\r
-/*\r
-* The configuration table for devices\r
-*/\r
-\r
-XUartLite_Config XUartLite_ConfigTable[] =\r
-{\r
- {\r
- XPAR_AXI_UARTLITE_0_DEVICE_ID,\r
- XPAR_AXI_UARTLITE_0_BASEADDR,\r
- XPAR_AXI_UARTLITE_0_BAUDRATE,\r
- XPAR_AXI_UARTLITE_0_USE_PARITY,\r
- XPAR_AXI_UARTLITE_0_ODD_PARITY,\r
- XPAR_AXI_UARTLITE_0_DATA_BITS\r
- }\r
-};\r
-\r
-\r
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_i.h
-*
-* Contains data which is shared between the files of the XUartLite component.
-* It is intended for internal use only.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/31/01 First release
-* 1.00b jhl 02/21/02 Reparitioned the driver for smaller files
-* 1.00b rpm 04/24/02 Moved register definitions to xuartlite_l.h and
-* updated macro naming convention
-* 2.00a ktn 10/20/09 The macros have been renamed to remove _m from
-* the name. XUartLite_mClearStats macro is removed and
-* XUartLite_ClearStats function should be used in its place.
-
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTLITE_I_H /* prevent circular inclusions */
-#define XUARTLITE_I_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xuartlite.h"
-#include "xuartlite_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************
-*
-* Update the statistics of the instance.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-* @param StatusRegister contains the contents of the UART status
-* register to update the statistics with.
-*
-* @return None.
-*
-* @note
-*
-* Signature: void XUartLite_UpdateStats(XUartLite *InstancePtr,
-* u32 StatusRegister)
-*
-*****************************************************************************/
-#define XUartLite_UpdateStats(InstancePtr, StatusRegister) \
-{ \
- if ((StatusRegister) & XUL_SR_OVERRUN_ERROR) \
- { \
- (InstancePtr)->Stats.ReceiveOverrunErrors++; \
- } \
- if ((StatusRegister) & XUL_SR_PARITY_ERROR) \
- { \
- (InstancePtr)->Stats.ReceiveParityErrors++; \
- } \
- if ((StatusRegister) & XUL_SR_FRAMING_ERROR) \
- { \
- (InstancePtr)->Stats.ReceiveFramingErrors++; \
- } \
-}
-
-/************************** Variable Definitions ****************************/
-
-/* the configuration table */
-extern XUartLite_Config XUartLite_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-unsigned int XUartLite_SendBuffer(XUartLite *InstancePtr);
-unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_intr.c
-*
-* This file contains interrupt-related functions for the UART Lite component
-* (XUartLite).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/31/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 1.02a rpm 02/14/07 Added check for outstanding transmission before
-* calling the send callback (avoids extraneous
-* callback invocations)
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
-* renamed to remove _m from the name.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartlite.h"
-#include "xuartlite_i.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-static void ReceiveDataHandler(XUartLite *InstancePtr);
-static void SendDataHandler(XUartLite *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-typedef void (*Handler)(XUartLite *InstancePtr);
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs in the driver. The purpose of the handler is to allow application
-* specific processing to be performed.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-* @param FuncPtr is the pointer to the callback function.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-*
-* @return None.
-*
-* @note There is no assert on the CallBackRef since the driver doesn't
-* know what it is (nor should it)
-*
-*****************************************************************************/
-void XUartLite_SetRecvHandler(XUartLite *InstancePtr,
- XUartLite_Handler FuncPtr, void *CallBackRef)
-{
- /*
- * Assert validates the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->RecvHandler = FuncPtr;
- InstancePtr->RecvCallBackRef = CallBackRef;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs in the driver. The purpose of the handler is to allow application
-* specific processing to be performed.
-*
-* @param InstancePtr is a pointer to the XUartLite instance .
-* @param FuncPtr is the pointer to the callback function.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-*
-* @return None.
-*
-* @note There is no assert on the CallBackRef since the driver doesn't
-* know what it is (nor should it)
-*
-*****************************************************************************/
-void XUartLite_SetSendHandler(XUartLite *InstancePtr,
- XUartLite_Handler FuncPtr, void *CallBackRef)
-{
- /*
- * Assert validates the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->SendHandler = FuncPtr;
- InstancePtr->SendCallBackRef = CallBackRef;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is the interrupt handler for the UART lite driver.
-* It must be connected to an interrupt system by the user such that it is
-* called when an interrupt for any UART lite occurs. This function
-* does not save or restore the processor context such that the user must
-* ensure this occurs.
-*
-* @param InstancePtr contains a pointer to the instance of the UART that
-* the interrupt is for.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUartLite_InterruptHandler(XUartLite *InstancePtr)
-{
- u32 IsrStatus;
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Read the status register to determine which, coulb be both
- * interrupt is active
- */
- IsrStatus = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
- XUL_STATUS_REG_OFFSET);
-
- if ((IsrStatus & (XUL_SR_RX_FIFO_FULL |
- XUL_SR_RX_FIFO_VALID_DATA)) != 0) {
- ReceiveDataHandler(InstancePtr);
- }
-
- if (((IsrStatus & XUL_SR_TX_FIFO_EMPTY) != 0) &&
- (InstancePtr->SendBuffer.RequestedBytes > 0)) {
- SendDataHandler(InstancePtr);
- }
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data is received, either a single
-* byte when FIFOs are not enabled, or multiple bytes with the FIFO.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveDataHandler(XUartLite *InstancePtr)
-{
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) {
- XUartLite_ReceiveBuffer(InstancePtr);
- }
-
- /*
- * If the last byte of a message was received then call the application
- * handler, this code should not use an else from the previous check of
- * the number of bytes to receive because the call to receive the buffer
- * updates the bytes to receive
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes == 0) {
- InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef,
- InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes);
- }
-
- /*
- * Update the receive stats to reflect the receive interrupt
- */
- InstancePtr->Stats.ReceiveInterrupts++;
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data has been sent, the transmit
-* FIFO is empty (transmitter holding register).
-*
-* @param InstancePtr is a pointer to the XUartLite instance .
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void SendDataHandler(XUartLite *InstancePtr)
-{
- /*
- * If there are not bytes to be sent from the specified buffer,
- * call the callback function
- */
- if (InstancePtr->SendBuffer.RemainingBytes == 0) {
- int SaveReq;
-
- /*
- * Save and zero the requested bytes since transmission
- * is complete
- */
- SaveReq = InstancePtr->SendBuffer.RequestedBytes;
- InstancePtr->SendBuffer.RequestedBytes = 0;
-
- /*
- * Call the application handler to indicate
- * the data has been sent
- */
- InstancePtr->SendHandler(InstancePtr->SendCallBackRef, SaveReq);
- }
- /*
- * Otherwise there is still more data to send in the specified buffer
- * so go ahead and send it
- */
- else {
- XUartLite_SendBuffer(InstancePtr);
- }
-
- /*
- * Update the transmit stats to reflect the transmit interrupt
- */
- InstancePtr->Stats.TransmitInterrupts++;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function disables the UART interrupt. After calling this function,
-* data may still be received by the UART but no interrupt will be generated
-* since the hardware device has no way to disable the receiver.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartLite_DisableInterrupt(XUartLite *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write to the control register to disable the interrupts, the only
- * other bits in this register are the FIFO reset bits such that
- * writing them to zero will not affect them.
- */
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, 0);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function enables the UART interrupt such that an interrupt will occur
-* when data is received or data has been transmitted. The device contains
-* 16 byte receive and transmit FIFOs such that an interrupt is generated
-* anytime there is data in the receive FIFO and when the transmit FIFO
-* transitions from not empty to empty.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartLite_EnableInterrupt(XUartLite *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write to the control register to enable the interrupts, the only
- * other bits in this register are the FIFO reset bits such that
- * writing them to zero will not affect them.
- */
- XUartLite_WriteReg(InstancePtr->RegBaseAddress,
- XUL_CONTROL_REG_OFFSET, XUL_CR_ENABLE_INTR);
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_l.c
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 04/25/02 First release
-* 1.12a rpm 07/16/07 Fixed arg type for RecvByte
-* 2.00a ktn 10/20/09 The macros have been renamed to remove _m from the name.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xuartlite_l.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This functions sends a single byte using the UART. It is blocking in that it
-* waits for the transmitter to become non-full before it writes the byte to
-* the transmit register.
-*
-* @param BaseAddress is the base address of the device
-* @param Data is the byte of data to send
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUartLite_SendByte(u32 BaseAddress, u8 Data)
-{
- while (XUartLite_IsTransmitFull(BaseAddress));
-
- XUartLite_WriteReg(BaseAddress, XUL_TX_FIFO_OFFSET, Data);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This functions receives a single byte using the UART. It is blocking in that
-* it waits for the receiver to become non-empty before it reads from the
-* receive register.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return The byte of data received.
-*
-* @note None.
-*
-******************************************************************************/
-u8 XUartLite_RecvByte(u32 BaseAddress)
-{
- while (XUartLite_IsReceiveEmpty(BaseAddress));
-
- return (u8)XUartLite_ReadReg(BaseAddress, XUL_RX_FIFO_OFFSET);
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. High-level driver functions
-* are defined in xuartlite.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b rpm 04/25/02 First release
-* 1.00b rpm 07/07/03 Removed references to XUartLite_GetControlReg macro
-* since the control register is write-only
-* 1.12a mta 03/21/07 Updated to new coding style
-* 1.13a sv 01/21/08 Updated driver to support access through DCR bus
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
-* renamed to remove _m from the name.
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XUARTLITE_L_H /* prevent circular inclusions */
-#define XUARTLITE_L_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/*
- * XPAR_XUARTLITE_USE_DCR_BRIDGE has to be set to 1 if the UartLite device is
- * accessed through a DCR bus connected to a bridge.
- */
-#define XPAR_XUARTLITE_USE_DCR_BRIDGE 0
-
-#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
-#include "xio_dcr.h"
-#endif
-
-
-/************************** Constant Definitions ****************************/
-
-/* UART Lite register offsets */
-
-#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
-#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
-#define XUL_TX_FIFO_OFFSET 1 /* transmit FIFO, write only */
-#define XUL_STATUS_REG_OFFSET 2 /* status register, read only */
-#define XUL_CONTROL_REG_OFFSET 3 /* control reg, write only */
-
-#else
-
-#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
-#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
-#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */
-#define XUL_CONTROL_REG_OFFSET 12 /* control reg, write only */
-
-#endif
-
-/* Control Register bit positions */
-
-#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */
-#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */
-#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */
-
-/* Status Register bit positions */
-
-#define XUL_SR_PARITY_ERROR 0x80
-#define XUL_SR_FRAMING_ERROR 0x40
-#define XUL_SR_OVERRUN_ERROR 0x20
-#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */
-#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
-#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */
-#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
-#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
-
-/* The following constant specifies the size of the Transmit/Receive FIFOs.
- * The FIFO size is fixed to 16 in the Uartlite IP and the size is not
- * configurable. This constant is not used in the driver.
- */
-#define XUL_FIFO_SIZE 16
-
-/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
- * per instance basis
- */
-#define XUL_STOP_BITS 1
-
-/* Parity definitions
- */
-#define XUL_PARITY_NONE 0
-#define XUL_PARITY_ODD 1
-#define XUL_PARITY_EVEN 2
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/*
- * Define the appropriate I/O access method to memory mapped I/O or DCR.
- */
-#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
-
-#define XUartLite_In32 XIo_DcrIn
-#define XUartLite_Out32 XIo_DcrOut
-
-#else
-
-#define XUartLite_In32 Xil_In32
-#define XUartLite_Out32 Xil_Out32
-
-#endif
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a UartLite register. A 32 bit write is performed.
-*
-* @param BaseAddress is the base address of the UartLite device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUartLite_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-****************************************************************************/
-#define XUartLite_WriteReg(BaseAddress, RegOffset, Data) \
- XUartLite_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a UartLite register. A 32 bit read is performed.
-*
-* @param BaseAddress is the base address of the UartLite device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XUartLite_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XUartLite_ReadReg(BaseAddress, RegOffset) \
- XUartLite_In32((BaseAddress) + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the control register. Use the XUL_CR_* constants defined
-* above to create the bit-mask to be written to the register.
-*
-* @param BaseAddress is the base address of the device
-* @param Mask is the 32-bit value to write to the control register
-*
-* @return None.
-*
-* @note C-style Signature:
-* void XUartLite_SetControlReg(u32 BaseAddress, u32 Mask);
-*
-*****************************************************************************/
-#define XUartLite_SetControlReg(BaseAddress, Mask) \
- XUartLite_WriteReg((BaseAddress), XUL_CONTROL_REG_OFFSET, (Mask))
-
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the status register. Use the XUL_SR_* constants defined
-* above to interpret the bit-mask returned.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return A 32-bit value representing the contents of the status register.
-*
-* @note C-style Signature:
-* u32 XUartLite_GetStatusReg(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XUartLite_GetStatusReg(BaseAddress) \
- XUartLite_ReadReg((BaseAddress), XUL_STATUS_REG_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the receiver has data.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return TRUE if the receiver is empty, FALSE if there is data present.
-*
-* @note C-style Signature:
-* int XUartLite_IsReceiveEmpty(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XUartLite_IsReceiveEmpty(BaseAddress) \
- ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
- XUL_SR_RX_FIFO_VALID_DATA)
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the transmitter is full.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return TRUE if the transmitter is full, FALSE otherwise.
-*
-* @note C-style Signature:
-* int XUartLite_IsTransmitFull(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XUartLite_IsTransmitFull(BaseAddress) \
- ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
- XUL_SR_TX_FIFO_FULL)
-
-
-/****************************************************************************/
-/**
-*
-* Check to see if the interrupt is enabled.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return TRUE if the interrupt is enabled, FALSE otherwise.
-*
-* @note C-style Signature:
-* int XUartLite_IsIntrEnabled(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XUartLite_IsIntrEnabled(BaseAddress) \
- ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \
- XUL_SR_INTR_ENABLED)
-
-
-/****************************************************************************/
-/**
-*
-* Enable the device interrupt. We cannot read the control register, so we
-* just write the enable interrupt bit and clear all others. Since the only
-* other ones are the FIFO reset bits, this works without side effects.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return None.
-*
-* @note C-style Signature:
-* void XUartLite_EnableIntr(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XUartLite_EnableIntr(BaseAddress) \
- XUartLite_SetControlReg((BaseAddress), XUL_CR_ENABLE_INTR)
-
-
-/****************************************************************************/
-/**
-*
-* Disable the device interrupt. We cannot read the control register, so we
-* just clear all bits. Since the only other ones are the FIFO reset bits,
-* this works without side effects.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return None.
-*
-* @note C-style Signature:
-* void XUartLite_DisableIntr(u32 BaseAddress);
-*
-*****************************************************************************/
-#define XUartLite_DisableIntr(BaseAddress) \
- XUartLite_SetControlReg((BaseAddress), 0)
-
-/************************** Function Prototypes *****************************/
-
-void XUartLite_SendByte(u32 BaseAddress, u8 Data);
-u8 XUartLite_RecvByte(u32 BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_selftest.c
-*
-* This file contains the self-test functions for the UART Lite component
-* (XUartLite).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/31/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
-* renamed to remove _m from the name.
-* 3.0 adk 17/12/13 Fixed CR:741186,761863 Reset the FIFO's before reading
-* the status register We don't know the status of the Status
-* Register in case of if there is more than one uartlite IP
-* instance in the h/w design.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartlite.h"
-#include "xuartlite_i.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-*
-* Runs a self-test on the device hardware. Since there is no way to perform a
-* loopback in the hardware, this test can only check the state of the status
-* register to verify it is correct. This test assumes that the hardware
-* device is still in its reset state, but has been initialized with the
-* Initialize function.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return
-* - XST_SUCCESS if the self-test was successful.
-* - XST_FAILURE if the self-test failed, the status register
-* value was not correct
-*
-* @note None.
-*
-******************************************************************************/
-int XUartLite_SelfTest(XUartLite *InstancePtr)
-{
- u32 StatusRegister;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Reset the FIFO's before reading the status register.
- * It is likely that the Uartlite IP may not always have an
- * empty Tx and Rx FIFO when a selftest is performed if more than one
- * uartlite instance is present in the h/w design.
- */
- XUartLite_ResetFifos(InstancePtr);
-
- /*
- * Read the Status register value to check if it is the correct value
- * after a reset
- */
- StatusRegister = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
- XUL_STATUS_REG_OFFSET);
-
- /*
- * If the status register is any other value other than
- * XUL_SR_TX_FIFO_EMPTY then the test is a failure since this is
- * the not the value after reset
- */
- if (StatusRegister != XUL_SR_TX_FIFO_EMPTY) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_sinit.c
-*
-* The implementation of the XUartLite component's static initialzation
-* functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.01a jvb 10/13/05 First release
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xuartlite_i.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************
-*
-* Looks up the device configuration based on the unique device ID. The table
-* UartliteConfigTable contains the configuration info for each device in the
-* system.
-*
-* @param DeviceId is the unique device ID to match on.
-*
-* @return A pointer to the configuration data for the device, or
-* NULL if no match was found.
-*
-* @note None.
-*
-******************************************************************************/
-XUartLite_Config *XUartLite_LookupConfig(u16 DeviceId)
-{
- XUartLite_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index=0; Index < XPAR_XUARTLITE_NUM_INSTANCES; Index++) {
- if (XUartLite_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XUartLite_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-/****************************************************************************/
-/**
-*
-* Initialize a XUartLite instance. The receive and transmit FIFOs of the
-* UART are not flushed, so the user may want to flush them. The hardware
-* device does not have any way to disable the receiver such that any valid
-* data may be present in the receive FIFO. This function disables the UART
-* interrupt. The baudrate and format of the data are fixed in the hardware
-* at hardware build time.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-* @param DeviceId is the unique id of the device controlled by this
-* XUartLite instance. Passing in a device id associates the
-* generic XUartLite instance to a specific device, as chosen by
-* the caller or application developer.
-*
-* @return
-* - XST_SUCCESS if everything starts up as expected.
-* - XST_DEVICE_NOT_FOUND if the device is not found in the
-* configuration table.
-*
-* @note None.
-*
-*****************************************************************************/
-int XUartLite_Initialize(XUartLite *InstancePtr, u16 DeviceId)
-{
- XUartLite_Config *ConfigPtr;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Lookup the device configuration in the configuration table. Use this
- * configuration info when initializing this component.
- */
- ConfigPtr = XUartLite_LookupConfig(DeviceId);
-
- if (ConfigPtr == (XUartLite_Config *)NULL) {
- return XST_DEVICE_NOT_FOUND;
- }
- return XUartLite_CfgInitialize(InstancePtr, ConfigPtr,
- ConfigPtr->RegBaseAddr);
-}
-
+++ /dev/null
-/******************************************************************************
-*
-* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xuartlite_stats.c
-*
-* This file contains the statistics functions for the UART Lite component
-* (XUartLite).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 08/31/01 First release
-* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
-* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
-* XUartLite_mClearStats macro is removed.
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xuartlite.h"
-#include "xuartlite_i.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-*
-* Returns a snapshot of the current statistics in the structure specified.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-* @param StatsPtr is a pointer to a XUartLiteStats structure to where the
-* statistics are to be copied.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartLite_GetStats(XUartLite *InstancePtr, XUartLite_Stats *StatsPtr)
-{
- /*
- * Assert validates the input arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(StatsPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Copy the stats from the instance to the specified stats */
-
- StatsPtr->TransmitInterrupts = InstancePtr->Stats.TransmitInterrupts;
- StatsPtr->ReceiveInterrupts = InstancePtr->Stats.ReceiveInterrupts;
- StatsPtr->CharactersTransmitted =
- InstancePtr->Stats.CharactersTransmitted;
- StatsPtr->CharactersReceived = InstancePtr->Stats.CharactersReceived;
- StatsPtr->ReceiveOverrunErrors =
- InstancePtr->Stats.ReceiveOverrunErrors;
- StatsPtr->ReceiveFramingErrors =
- InstancePtr->Stats.ReceiveFramingErrors;
- StatsPtr->ReceiveParityErrors = InstancePtr->Stats.ReceiveParityErrors;
-}
-
-/****************************************************************************/
-/**
-*
-* This function zeros the statistics for the given instance.
-*
-* @param InstancePtr is a pointer to the XUartLite instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartLite_ClearStats(XUartLite *InstancePtr)
-{
- /*
- * Assert validates the input arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Stats.TransmitInterrupts = 0;
- InstancePtr->Stats.ReceiveInterrupts = 0;
- InstancePtr->Stats.CharactersTransmitted = 0;
- InstancePtr->Stats.CharactersReceived = 0;
- InstancePtr->Stats.ReceiveOverrunErrors = 0;
- InstancePtr->Stats.ReceiveFramingErrors = 0;
- InstancePtr->Stats.ReceiveParityErrors = 0;
-
-}
-
--- /dev/null
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+LEVEL=0
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+
+OUTS = *.o
+
+libs:
+ echo "Compiling uartlite"
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
+
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite.c
+* @addtogroup uartlite_v3_1
+* @{
+*
+* Contains required functions for the XUartLite driver. See the xuartlite.h
+* header file for more details on this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 08/31/01 First release
+* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
+* 1.00b rmm 05/13/03 Fixed diab compiler warnings relating to asserts
+* 1.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
+* CfgInitialize() take a pointer to a config structure
+* instead of a device id. Moved Initialize() into
+* xgpio_sinit.c, and had Initialize() call CfgInitialize()
+* after it retrieved the config structure using the device
+* id. Removed include of xparameters.h along with any
+* dependencies on xparameters.h and the _g.c config table.
+* 1.01a wsy 05/08/06 fix CR220811 and CR224103.
+* 1.12a mta 03/31/07 Updated to new coding conventions
+* 1.13a sv 01/21/08 Updated driver to support access through DCR bus
+* 1.14a sdm 09/26/08 Updated code to avoid race condition in
+* XUartLite_SendBuffer
+* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
+* renamed to remove _m from the name. XUartLite_mClearStats
+* macro is removed and XUartLite_ClearStats function should
+* be used in its place.
+* 2.00a hvm 08/11/11 Removed the SetOptions related information in the
+* Recv and RecvBuffer function header notes section.
+* CR620849.
+* 2.01a adk 18/04/13 Updated the code to avoid unused variable
+* warnings when compiling with the -Wextra -Wall flags
+* In the file xuartlite.c. CR:704999.
+* 3.1 nsk 21/07/15 Updated XUartLite_ReceiveBuffer function to update the
+* receive data into user buffer in critical region.
+* CR#865787.
+* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XUartLite_CfgInitialize API.
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartlite.h"
+#include "xuartlite_i.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static void StubHandler(void *CallBackRef, unsigned int ByteCount);
+
+/****************************************************************************/
+/**
+*
+* Initialize a XUartLite instance. The receive and transmit FIFOs of the
+* UART are not flushed, so the user may want to flush them. The hardware
+* device does not have any way to disable the receiver such that any valid
+* data may be present in the receive FIFO. This function disables the UART
+* interrupt. The baudrate and format of the data are fixed in the hardware
+* at hardware build time.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+* @param Config is a reference to a structure containing information
+* about a specific UART Lite device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config. This function can initialize multiple
+* instance objects with the use of multiple calls giving different
+* Config information on each call.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* Config->BaseAddress for this parameters, passing the physical
+* address instead.
+*
+* @return
+* - XST_SUCCESS if everything starts up as expected.
+*
+* @note The Config pointer argument is not used by this function,
+* but is provided to keep the function signature consistent
+* with other drivers.
+*
+*****************************************************************************/
+int XUartLite_CfgInitialize(XUartLite *InstancePtr, XUartLite_Config *Config,
+ UINTPTR EffectiveAddr)
+{
+ (void) Config;
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Set some default values, including setting the callback
+ * handlers to stubs.
+ */
+ InstancePtr->SendBuffer.NextBytePtr = NULL;
+ InstancePtr->SendBuffer.RemainingBytes = 0;
+ InstancePtr->SendBuffer.RequestedBytes = 0;
+
+ InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+ InstancePtr->ReceiveBuffer.RemainingBytes = 0;
+ InstancePtr->ReceiveBuffer.RequestedBytes = 0;
+
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
+ InstancePtr->RegBaseAddress = ((EffectiveAddr >> 2)) & 0xFFF;
+#else
+ InstancePtr->RegBaseAddress = EffectiveAddr;
+#endif
+
+ InstancePtr->RecvHandler = StubHandler;
+ InstancePtr->SendHandler = StubHandler;
+
+ /* Write to the control register to disable the interrupts, don't
+ * reset the FIFOs are the user may want the data that's present
+ */
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, 0);
+
+ /*
+ * Clear the statistics for this driver
+ */
+ XUartLite_ClearStats(InstancePtr);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer of data using the UART in either
+* polled or interrupt driven modes. This function is non-blocking such that it
+* will return before the data has been sent by the UART. If the UART is busy
+* sending data, it will return and indicate zero bytes were sent.
+*
+* In a polled mode, this function will only send as much data as the UART can
+* buffer in the FIFO. The application may need to call it repeatedly to
+* send a buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer and
+* then the interrupt handler of the driver will continue sending data until the
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending the buffer.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+* @param DataBufferPtr is pointer to a buffer of data to be sent.
+* @param NumBytes contains the number of bytes to be sent. A value of
+* zero will stop a previous send operation that is in progress
+* in interrupt mode. Any data that was already put into the
+* transmit FIFO will be sent.
+*
+* @return The number of bytes actually sent.
+*
+* @note The number of bytes is not asserted so that this function may
+* be called with a value of zero to stop an operation that is
+* already in progress.
+*
+******************************************************************************/
+unsigned int XUartLite_Send(XUartLite *InstancePtr, u8 *DataBufferPtr,
+ unsigned int NumBytes)
+{
+ unsigned int BytesSent;
+ u32 StatusRegister;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(DataBufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(((signed)NumBytes) >= 0);
+
+ /*
+ * Enter a critical region by disabling the UART interrupts to allow
+ * this call to stop a previous operation that may be interrupt driven.
+ */
+ StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
+
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, 0);
+
+ /*
+ * Setup the specified buffer to be sent by setting the instance
+ * variables so it can be sent with polled or interrupt mode
+ */
+ InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+ InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+ InstancePtr->SendBuffer.NextBytePtr = DataBufferPtr;
+
+ /*
+ * Restore the interrupt enable register to it's previous value such
+ * that the critical region is exited.
+ * This is done here to minimize the amount of time the interrupt is
+ * disabled since there is only one interrupt and the receive could
+ * be filling up while interrupts are blocked.
+ */
+
+ StatusRegister &= XUL_CR_ENABLE_INTR;
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, StatusRegister);
+
+ /*
+ * Send the buffer using the UART and return the number of bytes sent
+ */
+ BytesSent = XUartLite_SendBuffer(InstancePtr);
+
+ return BytesSent;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function will attempt to receive a specified number of bytes of data
+* from the UART and store it into the specified buffer. This function is
+* designed for either polled or interrupt driven modes. It is non-blocking
+* such that it will return if no data has already received by the UART.
+*
+* In a polled mode, this function will only receive as much data as the UART
+* can buffer in the FIFO. The application may need to call it repeatedly to
+* receive a buffer. Polled mode is the default mode of operation for the driver.
+*
+* In interrupt mode, this function will start receiving and then the interrupt
+* handler of the driver will continue receiving data until the buffer has been
+* received. A callback function, as specified by the application, will be called
+* to indicate the completion of receiving the buffer or when any receive errors
+* or timeouts occur.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+* @param DataBufferPtr is pointer to buffer for data to be received into.
+* @param NumBytes is the number of bytes to be received. A value of zero
+* will stop a previous receive operation that is in progress in
+* interrupt mode.
+*
+* @return The number of bytes received.
+*
+* @note The number of bytes is not asserted so that this function
+* may be called with a value of zero to stop an operation
+* that is already in progress.
+*
+*****************************************************************************/
+unsigned int XUartLite_Recv(XUartLite *InstancePtr, u8 *DataBufferPtr,
+ unsigned int NumBytes)
+{
+ unsigned int ReceivedCount;
+ u32 StatusRegister;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(DataBufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(((signed)NumBytes) >= 0);
+
+ /*
+ * Enter a critical region by disabling all the UART interrupts to allow
+ * this call to stop a previous operation that may be interrupt driven
+ */
+ StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, 0);
+
+ /*
+ * Setup the specified buffer to be received by setting the instance
+ * variables so it can be received with polled or interrupt mode
+ */
+ InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.NextBytePtr = DataBufferPtr;
+
+ /*
+ * Restore the interrupt enable register to it's previous value such
+ * that the critical region is exited
+ */
+ StatusRegister &= XUL_CR_ENABLE_INTR;
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, StatusRegister);
+
+ /*
+ * Receive the data from the UART and return the number of bytes
+ * received
+ * This is done here to minimize the amount of time the interrupt is
+ * disabled since there is only one interrupt and the transmit could
+ * be emptying out while interrupts are blocked.
+ */
+ ReceivedCount = XUartLite_ReceiveBuffer(InstancePtr);
+
+ return ReceivedCount;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets the FIFOs, both transmit and receive, of the UART such
+* that they are emptied. Since the UART does not have any way to disable it
+* from receiving data, it may be necessary for the application to reset the
+* FIFOs to get rid of any unwanted data.
+*
+* @param InstancePtr is a pointer to the XUartLite instance .
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartLite_ResetFifos(XUartLite *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the status register 1st such that the next write to the control
+ * register won't destroy the state of the interrupt enable bit
+ */
+ Register = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
+ XUL_STATUS_REG_OFFSET);
+
+ /*
+ * Mask off the interrupt enable bit to maintain it's state.
+ */
+ Register &= XUL_SR_INTR_ENABLED;
+
+ /*
+ * Write to the control register to reset both FIFOs, these bits are
+ * self-clearing such that there's no need to clear them
+ */
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress, XUL_CONTROL_REG_OFFSET,
+ Register | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data. If the
+* transmitter register is not empty, it is sending data.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return A value of TRUE if the UART is sending data, otherwise FALSE.
+*
+* @note None.
+*
+*****************************************************************************/
+int XUartLite_IsSending(XUartLite *InstancePtr)
+{
+ u32 StatusRegister;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Read the status register to determine if the transmitter is empty
+ */
+ StatusRegister = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
+ XUL_STATUS_REG_OFFSET);
+
+ /*
+ * If the transmitter is not empty then indicate that the UART is still
+ * sending some data
+ */
+ return ((StatusRegister & XUL_SR_TX_FIFO_EMPTY) == 0);
+}
+
+
+/****************************************************************************
+*
+* This function provides a stub handler such that if the application does not
+* define a handler but enables interrupts, this function will be called.
+*
+* @param CallBackRef has no purpose but is necessary to match the
+* interface for a handler.
+* @param ByteCount has no purpose but is necessary to match the
+* interface for a handler.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void StubHandler(void *CallBackRef, unsigned int ByteCount)
+{
+ (void) CallBackRef;
+ (void) ByteCount;
+ /*
+ * Assert occurs always since this is a stub and should never be called
+ */
+ Xil_AssertVoidAlways();
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is designed to be
+* an internal function for the XUartLite component such that it may be called
+* from a shell function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer of data to the UART in either
+* polled or interrupt driven modes. This function is non-blocking such that
+* it will return before the data has been sent by the UART.
+*
+* In a polled mode, this function will only send as much data as the UART can
+* buffer, either in the transmitter or in the FIFO if present and enabled.
+* The application may need to call it repeatedly to send a buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer and
+* then the interrupt handler of the driver will continue until the buffer
+* has been sent. A callback function, as specified by the application, will
+* be called to indicate the completion of sending the buffer.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return NumBytes is the number of bytes actually sent (put into the
+* UART transmitter and/or FIFO).
+*
+* @note None.
+*
+*****************************************************************************/
+unsigned int XUartLite_SendBuffer(XUartLite *InstancePtr)
+{
+ unsigned int SentCount = 0;
+ u8 StatusRegister;
+ u8 IntrEnableStatus;
+
+ /*
+ * Read the status register to determine if the transmitter is full
+ */
+ StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
+
+ /*
+ * Enter a critical region by disabling all the UART interrupts to allow
+ * this call to stop a previous operation that may be interrupt driven
+ */
+ StatusRegister = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, 0);
+
+ /*
+ * Save the status register contents to restore the interrupt enable
+ * register to it's previous value when that the critical region is
+ * exited
+ */
+ IntrEnableStatus = StatusRegister;
+
+ /*
+ * Fill the FIFO from the the buffer that was specified
+ */
+
+ while (((StatusRegister & XUL_SR_TX_FIFO_FULL) == 0) &&
+ (SentCount < InstancePtr->SendBuffer.RemainingBytes)) {
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_TX_FIFO_OFFSET,
+ InstancePtr->SendBuffer.NextBytePtr[
+ SentCount]);
+
+ SentCount++;
+
+ StatusRegister =
+ XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
+
+ }
+
+ /*
+ * Update the buffer to reflect the bytes that were sent from it
+ */
+ InstancePtr->SendBuffer.NextBytePtr += SentCount;
+ InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+ /*
+ * Increment associated counters
+ */
+ InstancePtr->Stats.CharactersTransmitted += SentCount;
+
+ /*
+ * Restore the interrupt enable register to it's previous value such
+ * that the critical region is exited
+ */
+ IntrEnableStatus &= XUL_CR_ENABLE_INTR;
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress, XUL_CONTROL_REG_OFFSET,
+ IntrEnableStatus);
+
+ /*
+ * Return the number of bytes that were sent, althought they really were
+ * only put into the FIFO, not completely sent yet
+ */
+ return SentCount;
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is designed to be
+* an internal function for the XUartLite component such that it may be called
+* from a shell function that sets up the buffer or from an interrupt handler.
+*
+* This function will attempt to receive a specified number of bytes of data
+* from the UART and store it into the specified buffer. This function is
+* designed for either polled or interrupt driven modes. It is non-blocking
+* such that it will return if there is no data has already received by the
+* UART.
+*
+* In a polled mode, this function will only receive as much data as the UART
+* can buffer, either in the receiver or in the FIFO if present and enabled.
+* The application may need to call it repeatedly to receive a buffer. Polled
+* mode is the default mode of operation for the driver.
+*
+* In interrupt mode, this function will start receiving and then the interrupt
+* handler of the driver will continue until the buffer has been received. A
+* callback function, as specified by the application, will be called to indicate
+* the completion of receiving the buffer or when any receive errors or timeouts
+* occur.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return The number of bytes received.
+*
+* @note None.
+*
+*****************************************************************************/
+unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr)
+{
+ u8 StatusRegister;
+ u8 StatusRegisterVal;
+ unsigned int ReceivedCount = 0;
+
+ /*
+ * Enter a critical region by disabling all the UART interrupts to allow
+ * this call to stop a previous operation that may be interrupt driven
+ */
+ StatusRegisterVal = XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, 0);
+ /*
+ * Loop until there is not more data buffered by the UART or the
+ * specified number of bytes is received
+ */
+
+ while (ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes) {
+ /*
+ * Read the Status Register to determine if there is any data in
+ * the receiver/FIFO
+ */
+ StatusRegister =
+ XUartLite_GetStatusReg(InstancePtr->RegBaseAddress);
+
+ /*
+ * If there is data ready to be removed, then put the next byte
+ * received into the specified buffer and update the stats to
+ * reflect any receive errors for the byte
+ */
+ if (StatusRegister & XUL_SR_RX_FIFO_VALID_DATA) {
+ InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount++]=
+ XUartLite_ReadReg(InstancePtr->RegBaseAddress,
+ XUL_RX_FIFO_OFFSET);
+
+ XUartLite_UpdateStats(InstancePtr, StatusRegister);
+ }
+
+ /*
+ * There's no more data buffered, so exit such that this
+ * function does not block waiting for data
+ */
+ else {
+ break;
+ }
+ }
+
+ /*
+ * Update the receive buffer to reflect the number of bytes that was
+ * received
+ */
+ InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+ InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+ /*
+ * Increment associated counters in the statistics
+ */
+ InstancePtr->Stats.CharactersReceived += ReceivedCount;
+
+ /*
+ * Restore the interrupt enable register to it's previous value such
+ * that the critical region is exited
+ */
+ StatusRegisterVal &= XUL_CR_ENABLE_INTR;
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, StatusRegisterVal);
+
+ return ReceivedCount;
+}
+
+
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite.h
+* @addtogroup uartlite_v3_1
+* @{
+* @details
+*
+* This component contains the implementation of the XUartLite component which is
+* the driver for the Xilinx UART Lite device. This UART is a minimal hardware
+* implementation with minimal features. Most of the features, including baud
+* rate, parity, and number of data bits are only configurable when the hardware
+* device is built, rather than at run time by software.
+*
+* The device has 16 byte transmit and receive FIFOs and supports interrupts.
+* The device does not have any way to disable the receiver such that the
+* receive FIFO may contain unwanted data. The FIFOs are not flushed when the
+* driver is initialized, but a function is provided to allow the user to
+* reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated when the transmit FIFO
+* transitions from having data to being empty or when any data is contained in
+* the receive FIFO.
+*
+* In order to use interrupts, it's necessary for the user to connect the driver
+* interrupt handler, XUartLite_InterruptHandler, to the interrupt system of the
+* application. This function does not save and restore the processor context
+* such that the user must provide it. Send and receive handlers may be set for
+* the driver such that the handlers are called when transmit and receive
+* interrupts occur. The handlers are called from interrupt context and are
+* designed to allow application specific processing to be performed.
+*
+* The functions, XUartLite_Send and XUartLite_Recv, are provided in the driver
+* to allow data to be sent and received. They are designed to be used in
+* polled or interrupt modes.
+*
+* The driver provides a status for each received byte indicating any parity
+* frame or overrun error. The driver provides statistics which allow visibility
+* into these errors.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XUartLite_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in one
+* of the following ways:
+*
+* - XUartLite_Initialize(InstancePtr, DeviceId) - The driver looks up its own
+* configuration structure created by the tool-chain based on an ID provided
+* by the tool-chain.
+*
+* - XUartLite_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent. It works
+* with physical addresses only. Any needs for dynamic memory management,
+* threads or thread mutual exclusion, virtual memory, or cache control must
+* be satisfied by the layer above this driver.
+*
+* @note
+*
+* The driver is partitioned such that a minimal implementation may be used.
+* More features require additional files to be linked in.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 08/31/01 First release
+* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
+* 1.01a jvb 12/14/05 I separated dependency on the static config table and
+* xparameters.h from the driver initialization by moving
+* _Initialize and _LookupConfig to _sinit.c. I also added
+* the new _CfgInitialize routine.
+* 1.02a rpm 02/14/07 Added check for outstanding transmission before
+* calling the send callback (avoids extraneous
+* callback invocations) in interrupt service routine.
+* 1.12a mta 03/31/07 Updated to new coding conventions
+* 1.13a sv 01/21/08 Updated driver to support access through DCR bus
+* 1.14a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
+* file
+* 1.14a sdm 09/26/08 Updated code to avoid race condition in
+* XUartLite_SendBuffer
+* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
+* renamed to remove _m from the name. XUartLite_mClearStats
+* macro is removed and XUartLite_ClearStats function should
+* be used in its place.
+* 2.01a adk 18/04/13 Updated the code to avoid unused variable
+* warnings when compiling with the -Wextra -Wall flags
+* In the file xuartlite.c. CR:704999.
+* Added notes for CR 710483 that the XUL_FIFO_SIZE is not
+* used in the driver. This is the size of the FIFO for
+* Transmit/Receive FIFOs which cannot be changed.
+* 3.0 adk 17/12/13 Fixed CR:741186,761863 Changes are made in the file
+* xuartlite_selftest.c
+* 3.0 adk 19/12/13 Update the driver as per new TCL API's
+* 3.1 nsk 21/07/15 Updated XUartLite_ReceiveBuffer function in xuartlite.c
+* to update the receive data into user buffer in critical
+* region.CR#865787.
+* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XUartLite_CfgInitialize API.
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTLITE_H /* prevent circular inclusions */
+#define XUARTLITE_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * Callback function. The first argument is a callback reference passed in by
+ * the upper layer when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+ * The second argument is the ByteCount which is the number of bytes that
+ * actually moved from/to the buffer provided in the _Send/_Receive call.
+ */
+typedef void (*XUartLite_Handler)(void *CallBackRef, unsigned int ByteCount);
+
+/**
+ * Statistics for the XUartLite driver
+ */
+typedef struct {
+ u32 TransmitInterrupts; /**< Number of transmit interrupts */
+ u32 ReceiveInterrupts; /**< Number of receive interrupts */
+ u32 CharactersTransmitted; /**< Number of characters transmitted */
+ u32 CharactersReceived; /**< Number of characters received */
+ u32 ReceiveOverrunErrors; /**< Number of receive overruns */
+ u32 ReceiveParityErrors; /**< Number of receive parity errors */
+ u32 ReceiveFramingErrors; /**< Number of receive framing errors */
+} XUartLite_Stats;
+
+/**
+ * The following data type is used to manage the buffers that are handled
+ * when sending and receiving data in the interrupt mode. It is intended
+ * for internal use only.
+ */
+typedef struct {
+ u8 *NextBytePtr;
+ unsigned int RequestedBytes;
+ unsigned int RemainingBytes;
+} XUartLite_Buffer;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR RegBaseAddr; /**< Register base address */
+ u32 BaudRate; /**< Fixed baud rate */
+ u8 UseParity; /**< Parity generator enabled when TRUE */
+ u8 ParityOdd; /**< Parity generated is odd when TRUE, even
+ when FALSE */
+ u8 DataBits; /**< Fixed data bits */
+} XUartLite_Config;
+
+/**
+ * The XUartLite driver instance data. The user is required to allocate a
+ * variable of this type for every UART Lite device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XUartLite_Stats Stats; /* Component Statistics */
+ UINTPTR RegBaseAddress; /* Base address of registers */
+ u32 IsReady; /* Device is initialized and ready */
+
+ XUartLite_Buffer SendBuffer;
+ XUartLite_Buffer ReceiveBuffer;
+
+ XUartLite_Handler RecvHandler;
+ void *RecvCallBackRef; /* Callback ref for recv handler */
+ XUartLite_Handler SendHandler;
+ void *SendCallBackRef; /* Callback ref for send handler */
+} XUartLite;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xuartlite_sinit.c
+ */
+int XUartLite_Initialize(XUartLite *InstancePtr, u16 DeviceId);
+XUartLite_Config *XUartLite_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in file xuart.c
+ */
+int XUartLite_CfgInitialize(XUartLite *InstancePtr,
+ XUartLite_Config *Config,
+ UINTPTR EffectiveAddr);
+
+void XUartLite_ResetFifos(XUartLite *InstancePtr);
+
+unsigned int XUartLite_Send(XUartLite *InstancePtr, u8 *DataBufferPtr,
+ unsigned int NumBytes);
+unsigned int XUartLite_Recv(XUartLite *InstancePtr, u8 *DataBufferPtr,
+ unsigned int NumBytes);
+
+int XUartLite_IsSending(XUartLite *InstancePtr);
+
+/*
+ * Functions for statistics, in file xuartlite_stats.c
+ */
+void XUartLite_GetStats(XUartLite *InstancePtr, XUartLite_Stats *StatsPtr);
+void XUartLite_ClearStats(XUartLite *InstancePtr);
+
+/*
+ * Functions for self-test, in file xuartlite_selftest.c
+ */
+int XUartLite_SelfTest(XUartLite *InstancePtr);
+
+/*
+ * Functions for interrupts, in file xuartlite_intr.c
+ */
+void XUartLite_EnableInterrupt(XUartLite *InstancePtr);
+void XUartLite_DisableInterrupt(XUartLite *InstancePtr);
+
+void XUartLite_SetRecvHandler(XUartLite *InstancePtr, XUartLite_Handler FuncPtr,
+ void *CallBackRef);
+void XUartLite_SetSendHandler(XUartLite *InstancePtr, XUartLite_Handler FuncPtr,
+ void *CallBackRef);
+
+void XUartLite_InterruptHandler(XUartLite *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
+/** @} */
--- /dev/null
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Driver configuration\r
+*\r
+*******************************************************************/\r
+\r
+#include "xparameters.h"\r
+#include "xuartlite.h"\r
+\r
+/*\r
+* The configuration table for devices\r
+*/\r
+\r
+XUartLite_Config XUartLite_ConfigTable[] =\r
+{\r
+ {\r
+ XPAR_AXI_UARTLITE_0_DEVICE_ID,\r
+ XPAR_AXI_UARTLITE_0_BASEADDR,\r
+ XPAR_AXI_UARTLITE_0_BAUDRATE,\r
+ XPAR_AXI_UARTLITE_0_USE_PARITY,\r
+ XPAR_AXI_UARTLITE_0_ODD_PARITY,\r
+ XPAR_AXI_UARTLITE_0_DATA_BITS\r
+ }\r
+};\r
+\r
+\r
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_i.h
+* @addtogroup uartlite_v3_1
+* @{
+*
+* Contains data which is shared between the files of the XUartLite component.
+* It is intended for internal use only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 08/31/01 First release
+* 1.00b jhl 02/21/02 Reparitioned the driver for smaller files
+* 1.00b rpm 04/24/02 Moved register definitions to xuartlite_l.h and
+* updated macro naming convention
+* 2.00a ktn 10/20/09 The macros have been renamed to remove _m from
+* the name. XUartLite_mClearStats macro is removed and
+* XUartLite_ClearStats function should be used in its place.
+
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTLITE_I_H /* prevent circular inclusions */
+#define XUARTLITE_I_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xuartlite.h"
+#include "xuartlite_l.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************
+*
+* Update the statistics of the instance.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+* @param StatusRegister contains the contents of the UART status
+* register to update the statistics with.
+*
+* @return None.
+*
+* @note
+*
+* Signature: void XUartLite_UpdateStats(XUartLite *InstancePtr,
+* u32 StatusRegister)
+*
+*****************************************************************************/
+#define XUartLite_UpdateStats(InstancePtr, StatusRegister) \
+{ \
+ if ((StatusRegister) & XUL_SR_OVERRUN_ERROR) \
+ { \
+ (InstancePtr)->Stats.ReceiveOverrunErrors++; \
+ } \
+ if ((StatusRegister) & XUL_SR_PARITY_ERROR) \
+ { \
+ (InstancePtr)->Stats.ReceiveParityErrors++; \
+ } \
+ if ((StatusRegister) & XUL_SR_FRAMING_ERROR) \
+ { \
+ (InstancePtr)->Stats.ReceiveFramingErrors++; \
+ } \
+}
+
+/************************** Variable Definitions ****************************/
+
+/* the configuration table */
+extern XUartLite_Config XUartLite_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+unsigned int XUartLite_SendBuffer(XUartLite *InstancePtr);
+unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_intr.c
+* @addtogroup uartlite_v3_1
+* @{
+*
+* This file contains interrupt-related functions for the UART Lite component
+* (XUartLite).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 08/31/01 First release
+* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
+* 1.02a rpm 02/14/07 Added check for outstanding transmission before
+* calling the send callback (avoids extraneous
+* callback invocations)
+* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
+* renamed to remove _m from the name.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartlite.h"
+#include "xuartlite_i.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartLite *InstancePtr);
+static void SendDataHandler(XUartLite *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartLite *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs in the driver. The purpose of the handler is to allow application
+* specific processing to be performed.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+* @param FuncPtr is the pointer to the callback function.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+*
+* @return None.
+*
+* @note There is no assert on the CallBackRef since the driver doesn't
+* know what it is (nor should it)
+*
+*****************************************************************************/
+void XUartLite_SetRecvHandler(XUartLite *InstancePtr,
+ XUartLite_Handler FuncPtr, void *CallBackRef)
+{
+ /*
+ * Assert validates the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->RecvHandler = FuncPtr;
+ InstancePtr->RecvCallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs in the driver. The purpose of the handler is to allow application
+* specific processing to be performed.
+*
+* @param InstancePtr is a pointer to the XUartLite instance .
+* @param FuncPtr is the pointer to the callback function.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+*
+* @return None.
+*
+* @note There is no assert on the CallBackRef since the driver doesn't
+* know what it is (nor should it)
+*
+*****************************************************************************/
+void XUartLite_SetSendHandler(XUartLite *InstancePtr,
+ XUartLite_Handler FuncPtr, void *CallBackRef)
+{
+ /*
+ * Assert validates the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->SendHandler = FuncPtr;
+ InstancePtr->SendCallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the UART lite driver.
+* It must be connected to an interrupt system by the user such that it is
+* called when an interrupt for any UART lite occurs. This function
+* does not save or restore the processor context such that the user must
+* ensure this occurs.
+*
+* @param InstancePtr contains a pointer to the instance of the UART that
+* the interrupt is for.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUartLite_InterruptHandler(XUartLite *InstancePtr)
+{
+ u32 IsrStatus;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Read the status register to determine which, coulb be both
+ * interrupt is active
+ */
+ IsrStatus = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
+ XUL_STATUS_REG_OFFSET);
+
+ if ((IsrStatus & (XUL_SR_RX_FIFO_FULL |
+ XUL_SR_RX_FIFO_VALID_DATA)) != 0) {
+ ReceiveDataHandler(InstancePtr);
+ }
+
+ if (((IsrStatus & XUL_SR_TX_FIFO_EMPTY) != 0) &&
+ (InstancePtr->SendBuffer.RequestedBytes > 0)) {
+ SendDataHandler(InstancePtr);
+ }
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is received, either a single
+* byte when FIFOs are not enabled, or multiple bytes with the FIFO.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartLite *InstancePtr)
+{
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) {
+ XUartLite_ReceiveBuffer(InstancePtr);
+ }
+
+ /*
+ * If the last byte of a message was received then call the application
+ * handler, this code should not use an else from the previous check of
+ * the number of bytes to receive because the call to receive the buffer
+ * updates the bytes to receive
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes == 0) {
+ InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef,
+ InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes);
+ }
+
+ /*
+ * Update the receive stats to reflect the receive interrupt
+ */
+ InstancePtr->Stats.ReceiveInterrupts++;
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param InstancePtr is a pointer to the XUartLite instance .
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartLite *InstancePtr)
+{
+ /*
+ * If there are not bytes to be sent from the specified buffer,
+ * call the callback function
+ */
+ if (InstancePtr->SendBuffer.RemainingBytes == 0) {
+ int SaveReq;
+
+ /*
+ * Save and zero the requested bytes since transmission
+ * is complete
+ */
+ SaveReq = InstancePtr->SendBuffer.RequestedBytes;
+ InstancePtr->SendBuffer.RequestedBytes = 0;
+
+ /*
+ * Call the application handler to indicate
+ * the data has been sent
+ */
+ InstancePtr->SendHandler(InstancePtr->SendCallBackRef, SaveReq);
+ }
+ /*
+ * Otherwise there is still more data to send in the specified buffer
+ * so go ahead and send it
+ */
+ else {
+ XUartLite_SendBuffer(InstancePtr);
+ }
+
+ /*
+ * Update the transmit stats to reflect the transmit interrupt
+ */
+ InstancePtr->Stats.TransmitInterrupts++;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function disables the UART interrupt. After calling this function,
+* data may still be received by the UART but no interrupt will be generated
+* since the hardware device has no way to disable the receiver.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartLite_DisableInterrupt(XUartLite *InstancePtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write to the control register to disable the interrupts, the only
+ * other bits in this register are the FIFO reset bits such that
+ * writing them to zero will not affect them.
+ */
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, 0);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables the UART interrupt such that an interrupt will occur
+* when data is received or data has been transmitted. The device contains
+* 16 byte receive and transmit FIFOs such that an interrupt is generated
+* anytime there is data in the receive FIFO and when the transmit FIFO
+* transitions from not empty to empty.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartLite_EnableInterrupt(XUartLite *InstancePtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write to the control register to enable the interrupts, the only
+ * other bits in this register are the FIFO reset bits such that
+ * writing them to zero will not affect them.
+ */
+ XUartLite_WriteReg(InstancePtr->RegBaseAddress,
+ XUL_CONTROL_REG_OFFSET, XUL_CR_ENABLE_INTR);
+}
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_l.c
+* @addtogroup uartlite_v3_1
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device. The user should refer to the hardware device specification for more
+* details of the device operation.
+
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm 04/25/02 First release
+* 1.12a rpm 07/16/07 Fixed arg type for RecvByte
+* 2.00a ktn 10/20/09 The macros have been renamed to remove _m from the name.
+* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototypes of XUartLite_SendByte,
+* XUartLite_RecvByte APIs.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xuartlite_l.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the UART. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param BaseAddress is the base address of the device
+* @param Data is the byte of data to send
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data)
+{
+ while (XUartLite_IsTransmitFull(BaseAddress));
+
+ XUartLite_WriteReg(BaseAddress, XUL_TX_FIFO_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the UART. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return The byte of data received.
+*
+* @note None.
+*
+******************************************************************************/
+u8 XUartLite_RecvByte(UINTPTR BaseAddress)
+{
+ while (XUartLite_IsReceiveEmpty(BaseAddress));
+
+ return (u8)XUartLite_ReadReg(BaseAddress, XUL_RX_FIFO_OFFSET);
+}
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_l.h
+* @addtogroup uartlite_v3_1
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device. High-level driver functions
+* are defined in xuartlite.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b rpm 04/25/02 First release
+* 1.00b rpm 07/07/03 Removed references to XUartLite_GetControlReg macro
+* since the control register is write-only
+* 1.12a mta 03/21/07 Updated to new coding style
+* 1.13a sv 01/21/08 Updated driver to support access through DCR bus
+* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
+* renamed to remove _m from the name.
+* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototypes of XUartLite_SendByte,
+* XUartLite_RecvByte APIs.
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTLITE_L_H /* prevent circular inclusions */
+#define XUARTLITE_L_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/*
+ * XPAR_XUARTLITE_USE_DCR_BRIDGE has to be set to 1 if the UartLite device is
+ * accessed through a DCR bus connected to a bridge.
+ */
+#define XPAR_XUARTLITE_USE_DCR_BRIDGE 0
+
+#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
+#include "xio_dcr.h"
+#endif
+
+
+/************************** Constant Definitions ****************************/
+
+/* UART Lite register offsets */
+
+#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
+#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
+#define XUL_TX_FIFO_OFFSET 1 /* transmit FIFO, write only */
+#define XUL_STATUS_REG_OFFSET 2 /* status register, read only */
+#define XUL_CONTROL_REG_OFFSET 3 /* control reg, write only */
+
+#else
+
+#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
+#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
+#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */
+#define XUL_CONTROL_REG_OFFSET 12 /* control reg, write only */
+
+#endif
+
+/* Control Register bit positions */
+
+#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */
+#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */
+#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */
+
+/* Status Register bit positions */
+
+#define XUL_SR_PARITY_ERROR 0x80
+#define XUL_SR_FRAMING_ERROR 0x40
+#define XUL_SR_OVERRUN_ERROR 0x20
+#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */
+#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
+#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */
+#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
+#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
+
+/* The following constant specifies the size of the Transmit/Receive FIFOs.
+ * The FIFO size is fixed to 16 in the Uartlite IP and the size is not
+ * configurable. This constant is not used in the driver.
+ */
+#define XUL_FIFO_SIZE 16
+
+/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
+ * per instance basis
+ */
+#define XUL_STOP_BITS 1
+
+/* Parity definitions
+ */
+#define XUL_PARITY_NONE 0
+#define XUL_PARITY_ODD 1
+#define XUL_PARITY_EVEN 2
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/*
+ * Define the appropriate I/O access method to memory mapped I/O or DCR.
+ */
+#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
+
+#define XUartLite_In32 XIo_DcrIn
+#define XUartLite_Out32 XIo_DcrOut
+
+#else
+
+#define XUartLite_In32 Xil_In32
+#define XUartLite_Out32 Xil_Out32
+
+#endif
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a UartLite register. A 32 bit write is performed.
+*
+* @param BaseAddress is the base address of the UartLite device.
+* @param RegOffset is the register offset from the base to write to.
+* @param Data is the data written to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUartLite_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+****************************************************************************/
+#define XUartLite_WriteReg(BaseAddress, RegOffset, Data) \
+ XUartLite_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a UartLite register. A 32 bit read is performed.
+*
+* @param BaseAddress is the base address of the UartLite device.
+* @param RegOffset is the register offset from the base to read from.
+*
+* @return Data read from the register.
+*
+* @note C-style signature:
+* u32 XUartLite_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XUartLite_ReadReg(BaseAddress, RegOffset) \
+ XUartLite_In32((BaseAddress) + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the control register. Use the XUL_CR_* constants defined
+* above to create the bit-mask to be written to the register.
+*
+* @param BaseAddress is the base address of the device
+* @param Mask is the 32-bit value to write to the control register
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XUartLite_SetControlReg(u32 BaseAddress, u32 Mask);
+*
+*****************************************************************************/
+#define XUartLite_SetControlReg(BaseAddress, Mask) \
+ XUartLite_WriteReg((BaseAddress), XUL_CONTROL_REG_OFFSET, (Mask))
+
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the status register. Use the XUL_SR_* constants defined
+* above to interpret the bit-mask returned.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return A 32-bit value representing the contents of the status register.
+*
+* @note C-style Signature:
+* u32 XUartLite_GetStatusReg(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XUartLite_GetStatusReg(BaseAddress) \
+ XUartLite_ReadReg((BaseAddress), XUL_STATUS_REG_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the receiver has data.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return TRUE if the receiver is empty, FALSE if there is data present.
+*
+* @note C-style Signature:
+* int XUartLite_IsReceiveEmpty(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XUartLite_IsReceiveEmpty(BaseAddress) \
+ ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
+ XUL_SR_RX_FIFO_VALID_DATA)
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the transmitter is full.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return TRUE if the transmitter is full, FALSE otherwise.
+*
+* @note C-style Signature:
+* int XUartLite_IsTransmitFull(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XUartLite_IsTransmitFull(BaseAddress) \
+ ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
+ XUL_SR_TX_FIFO_FULL)
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the interrupt is enabled.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return TRUE if the interrupt is enabled, FALSE otherwise.
+*
+* @note C-style Signature:
+* int XUartLite_IsIntrEnabled(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XUartLite_IsIntrEnabled(BaseAddress) \
+ ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \
+ XUL_SR_INTR_ENABLED)
+
+
+/****************************************************************************/
+/**
+*
+* Enable the device interrupt. We cannot read the control register, so we
+* just write the enable interrupt bit and clear all others. Since the only
+* other ones are the FIFO reset bits, this works without side effects.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XUartLite_EnableIntr(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XUartLite_EnableIntr(BaseAddress) \
+ XUartLite_SetControlReg((BaseAddress), XUL_CR_ENABLE_INTR)
+
+
+/****************************************************************************/
+/**
+*
+* Disable the device interrupt. We cannot read the control register, so we
+* just clear all bits. Since the only other ones are the FIFO reset bits,
+* this works without side effects.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XUartLite_DisableIntr(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XUartLite_DisableIntr(BaseAddress) \
+ XUartLite_SetControlReg((BaseAddress), 0)
+
+/************************** Function Prototypes *****************************/
+
+void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data);
+u8 XUartLite_RecvByte(UINTPTR BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_selftest.c
+* @addtogroup uartlite_v3_1
+* @{
+*
+* This file contains the self-test functions for the UART Lite component
+* (XUartLite).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 08/31/01 First release
+* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
+* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
+* renamed to remove _m from the name.
+* 3.0 adk 17/12/13 Fixed CR:741186,761863 Reset the FIFO's before reading
+* the status register We don't know the status of the Status
+* Register in case of if there is more than one uartlite IP
+* instance in the h/w design.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartlite.h"
+#include "xuartlite_i.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Runs a self-test on the device hardware. Since there is no way to perform a
+* loopback in the hardware, this test can only check the state of the status
+* register to verify it is correct. This test assumes that the hardware
+* device is still in its reset state, but has been initialized with the
+* Initialize function.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return
+* - XST_SUCCESS if the self-test was successful.
+* - XST_FAILURE if the self-test failed, the status register
+* value was not correct
+*
+* @note None.
+*
+******************************************************************************/
+int XUartLite_SelfTest(XUartLite *InstancePtr)
+{
+ u32 StatusRegister;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Reset the FIFO's before reading the status register.
+ * It is likely that the Uartlite IP may not always have an
+ * empty Tx and Rx FIFO when a selftest is performed if more than one
+ * uartlite instance is present in the h/w design.
+ */
+ XUartLite_ResetFifos(InstancePtr);
+
+ /*
+ * Read the Status register value to check if it is the correct value
+ * after a reset
+ */
+ StatusRegister = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
+ XUL_STATUS_REG_OFFSET);
+
+ /*
+ * If the status register is any other value other than
+ * XUL_SR_TX_FIFO_EMPTY then the test is a failure since this is
+ * the not the value after reset
+ */
+ if (StatusRegister != XUL_SR_TX_FIFO_EMPTY) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_sinit.c
+* @addtogroup uartlite_v3_1
+* @{
+*
+* The implementation of the XUartLite component's static initialzation
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.01a jvb 10/13/05 First release
+* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartlite_i.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************
+*
+* Looks up the device configuration based on the unique device ID. The table
+* UartliteConfigTable contains the configuration info for each device in the
+* system.
+*
+* @param DeviceId is the unique device ID to match on.
+*
+* @return A pointer to the configuration data for the device, or
+* NULL if no match was found.
+*
+* @note None.
+*
+******************************************************************************/
+XUartLite_Config *XUartLite_LookupConfig(u16 DeviceId)
+{
+ XUartLite_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index=0; Index < XPAR_XUARTLITE_NUM_INSTANCES; Index++) {
+ if (XUartLite_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XUartLite_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+
+/****************************************************************************/
+/**
+*
+* Initialize a XUartLite instance. The receive and transmit FIFOs of the
+* UART are not flushed, so the user may want to flush them. The hardware
+* device does not have any way to disable the receiver such that any valid
+* data may be present in the receive FIFO. This function disables the UART
+* interrupt. The baudrate and format of the data are fixed in the hardware
+* at hardware build time.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+* @param DeviceId is the unique id of the device controlled by this
+* XUartLite instance. Passing in a device id associates the
+* generic XUartLite instance to a specific device, as chosen by
+* the caller or application developer.
+*
+* @return
+* - XST_SUCCESS if everything starts up as expected.
+* - XST_DEVICE_NOT_FOUND if the device is not found in the
+* configuration table.
+*
+* @note None.
+*
+*****************************************************************************/
+int XUartLite_Initialize(XUartLite *InstancePtr, u16 DeviceId)
+{
+ XUartLite_Config *ConfigPtr;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Lookup the device configuration in the configuration table. Use this
+ * configuration info when initializing this component.
+ */
+ ConfigPtr = XUartLite_LookupConfig(DeviceId);
+
+ if (ConfigPtr == (XUartLite_Config *)NULL) {
+ return XST_DEVICE_NOT_FOUND;
+ }
+ return XUartLite_CfgInitialize(InstancePtr, ConfigPtr,
+ ConfigPtr->RegBaseAddr);
+}
+
+/** @} */
--- /dev/null
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_stats.c
+* @addtogroup uartlite_v3_1
+* @{
+*
+* This file contains the statistics functions for the UART Lite component
+* (XUartLite).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 08/31/01 First release
+* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
+* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs.
+* XUartLite_mClearStats macro is removed.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xuartlite.h"
+#include "xuartlite_i.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Returns a snapshot of the current statistics in the structure specified.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+* @param StatsPtr is a pointer to a XUartLiteStats structure to where the
+* statistics are to be copied.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartLite_GetStats(XUartLite *InstancePtr, XUartLite_Stats *StatsPtr)
+{
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(StatsPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Copy the stats from the instance to the specified stats */
+
+ StatsPtr->TransmitInterrupts = InstancePtr->Stats.TransmitInterrupts;
+ StatsPtr->ReceiveInterrupts = InstancePtr->Stats.ReceiveInterrupts;
+ StatsPtr->CharactersTransmitted =
+ InstancePtr->Stats.CharactersTransmitted;
+ StatsPtr->CharactersReceived = InstancePtr->Stats.CharactersReceived;
+ StatsPtr->ReceiveOverrunErrors =
+ InstancePtr->Stats.ReceiveOverrunErrors;
+ StatsPtr->ReceiveFramingErrors =
+ InstancePtr->Stats.ReceiveFramingErrors;
+ StatsPtr->ReceiveParityErrors = InstancePtr->Stats.ReceiveParityErrors;
+}
+
+/****************************************************************************/
+/**
+*
+* This function zeros the statistics for the given instance.
+*
+* @param InstancePtr is a pointer to the XUartLite instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartLite_ClearStats(XUartLite *InstancePtr)
+{
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Stats.TransmitInterrupts = 0;
+ InstancePtr->Stats.ReceiveInterrupts = 0;
+ InstancePtr->Stats.CharactersTransmitted = 0;
+ InstancePtr->Stats.CharactersReceived = 0;
+ InstancePtr->Stats.ReceiveOverrunErrors = 0;
+ InstancePtr->Stats.ReceiveFramingErrors = 0;
+ InstancePtr->Stats.ReceiveParityErrors = 0;
+
+}
+
+/** @} */
\r
- PARAMETER NAME = C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\MicroBlaze_Kintex7_EthernetLite\BSP\system.mss\r
-\r
PARAMETER VERSION = 2.2.0\r
\r
\r
BEGIN OS\r
PARAMETER OS_NAME = standalone\r
- PARAMETER OS_VER = 4.2\r
+ PARAMETER OS_VER = 5.4\r
PARAMETER PROC_INSTANCE = microblaze_0\r
+ PARAMETER microblaze_exceptions = true\r
+ PARAMETER stdin = axi_uartlite_0\r
+ PARAMETER stdout = axi_uartlite_0\r
END\r
\r
\r
BEGIN PROCESSOR\r
PARAMETER DRIVER_NAME = cpu\r
- PARAMETER DRIVER_VER = 2.2\r
+ PARAMETER DRIVER_VER = 2.4\r
PARAMETER HW_INSTANCE = microblaze_0\r
END\r
\r
\r
BEGIN DRIVER\r
PARAMETER DRIVER_NAME = emaclite\r
- PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER DRIVER_VER = 4.2\r
PARAMETER HW_INSTANCE = axi_ethernetlite_0\r
END\r
\r
BEGIN DRIVER\r
PARAMETER DRIVER_NAME = gpio\r
- PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER DRIVER_VER = 4.1\r
PARAMETER HW_INSTANCE = axi_gpio_0\r
END\r
\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = intc\r
- PARAMETER DRIVER_VER = 3.2\r
- PARAMETER HW_INSTANCE = axi_intc_0\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = tmrctr\r
- PARAMETER DRIVER_VER = 3.0\r
- PARAMETER HW_INSTANCE = axi_timer_0\r
-END\r
-\r
BEGIN DRIVER\r
PARAMETER DRIVER_NAME = uartlite\r
- PARAMETER DRIVER_VER = 3.0\r
+ PARAMETER DRIVER_VER = 3.2\r
PARAMETER HW_INSTANCE = axi_uartlite_0\r
END\r
\r
BEGIN DRIVER\r
PARAMETER DRIVER_NAME = bram\r
- PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER DRIVER_VER = 4.1\r
PARAMETER HW_INSTANCE = microblaze_0_local_memory_dlmb_bram_if_cntlr\r
END\r
\r
BEGIN DRIVER\r
PARAMETER DRIVER_NAME = bram\r
- PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER DRIVER_VER = 4.1\r
PARAMETER HW_INSTANCE = microblaze_0_local_memory_ilmb_bram_if_cntlr\r
END\r
\r
<?xml version="1.0" encoding="UTF-8"?>\r
<projectDescription>\r
<name>Hardware</name>\r
- <comment>Created by SDK v2014.4</comment>\r
+ <comment>Created by SDK v2016.1</comment>\r
<projects>\r
</projects>\r
<buildSpec>\r
</natures>\r
<filteredResources>\r
<filter>\r
- <id>1421760060412</id>\r
+ <id>1462808401190</id>\r
<name></name>\r
<type>6</type>\r
<matcher>\r
</matcher>\r
</filter>\r
<filter>\r
- <id>1421760060422</id>\r
+ <id>1462808401200</id>\r
<name></name>\r
<type>6</type>\r
<matcher>\r
</matcher>\r
</filter>\r
<filter>\r
- <id>1421760060432</id>\r
+ <id>1462808401200</id>\r
<name></name>\r
<type>6</type>\r
<matcher>\r
<arguments>1.0-name-matches-false-false-*.hwh</arguments>\r
</matcher>\r
</filter>\r
- <filter>\r
- <id>1421760060432</id>\r
- <name></name>\r
- <type>6</type>\r
- <matcher>\r
- <id>org.eclipse.ui.ide.multiFilter</id>\r
- <arguments>1.0-name-matches-false-false-*.bit</arguments>\r
- </matcher>\r
- </filter>\r
- <filter>\r
- <id>1421760060442</id>\r
- <name></name>\r
- <type>6</type>\r
- <matcher>\r
- <id>org.eclipse.ui.ide.multiFilter</id>\r
- <arguments>1.0-name-matches-false-false-*.bmm</arguments>\r
- </matcher>\r
- </filter>\r
- <filter>\r
- <id>1421760060442</id>\r
- <name></name>\r
- <type>6</type>\r
- <matcher>\r
- <id>org.eclipse.ui.ide.multiFilter</id>\r
- <arguments>1.0-name-matches-false-false-*.mmi</arguments>\r
- </matcher>\r
- </filter>\r
</filteredResources>\r
</projectDescription>\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Jan 20 12:53:16 2015" VIVADOVERSION="2014.4">
-
- <SYSTEMINFO ARCH="kintex7" BOARD="xilinx.com:kc705:part0:1.1" DEVICE="7k325t" NAME="base_microblaze_design_imp" PACKAGE="ffg900" SPEEDGRADE="-2"/>
-
- <EXTERNALPORTS>
- <PORT DIR="I" NAME="rs232_uart_rxd" SIGIS="undef"/>
- <PORT DIR="O" NAME="rs232_uart_txd" SIGIS="undef"/>
- <PORT DIR="O" LEFT="7" NAME="led_8bits_tri_o" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="I" NAME="mii_col" SIGIS="undef"/>
- <PORT DIR="I" NAME="mii_crs" SIGIS="undef"/>
- <PORT DIR="O" NAME="mii_rst_n" SIGIS="undef"/>
- <PORT DIR="I" NAME="mii_rx_clk" SIGIS="undef"/>
- <PORT DIR="I" NAME="mii_rx_dv" SIGIS="undef"/>
- <PORT DIR="I" NAME="mii_rx_er" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="mii_rxd" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="I" NAME="mii_tx_clk" SIGIS="undef"/>
- <PORT DIR="O" NAME="mii_tx_en" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="mii_txd" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="mdio_mdc_mdc" SIGIS="undef"/>
- <PORT DIR="I" NAME="mdio_mdc_mdio_i" SIGIS="undef"/>
- <PORT DIR="O" NAME="mdio_mdc_mdio_o" SIGIS="undef"/>
- <PORT DIR="O" NAME="mdio_mdc_mdio_t" SIGIS="undef"/>
- <PORT DIR="IO" LEFT="63" NAME="ddr3_sdram_dq" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="IO" LEFT="7" NAME="ddr3_sdram_dqs_p" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="IO" LEFT="7" NAME="ddr3_sdram_dqs_n" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="13" NAME="ddr3_sdram_addr" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="2" NAME="ddr3_sdram_ba" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_sdram_ras_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_sdram_cas_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_sdram_we_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_sdram_reset_n" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_ck_p" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_ck_n" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_cke" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_cs_n" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="7" NAME="ddr3_sdram_dm" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_odt" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="I" NAME="sys_diff_clock_clk_p" SIGIS="undef"/>
- <PORT DIR="I" NAME="sys_diff_clock_clk_n" SIGIS="undef"/>
- <PORT DIR="I" NAME="reset" SIGIS="rst" SIGNAME="External_Ports_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="sys_rst"/>
- </CONNECTIONS>
- </PORT>
- </EXTERNALPORTS>
-
- <MODULES>
- <MODULE FULLNAME="/axi_ethernetlite_0" HWVERSION="3.0" INSTANCE="axi_ethernetlite_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite" VLNV="xilinx.com:ip:axi_ethernetlite:3.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_ethernetlite;v=v3_0;d=pg135-axi-ethernetlite.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_INSTANCE" VALUE="axi_ethernetlite_inst"/>
- <PARAMETER NAME="C_S_AXI_ACLK_PERIOD_PS" VALUE="10000"/>
- <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="13"/>
- <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_ID_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
- <PARAMETER NAME="C_INCLUDE_MDIO" VALUE="1"/>
- <PARAMETER NAME="C_INCLUDE_INTERNAL_LOOPBACK" VALUE="0"/>
- <PARAMETER NAME="C_INCLUDE_GLOBAL_BUFFERS" VALUE="1"/>
- <PARAMETER NAME="C_DUPLEX" VALUE="1"/>
- <PARAMETER NAME="C_TX_PING_PONG" VALUE="1"/>
- <PARAMETER NAME="C_RX_PING_PONG" VALUE="1"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_ethernetlite_0_0"/>
- <PARAMETER NAME="AXI_ACLK_FREQ_MHZ" VALUE="100"/>
- <PARAMETER NAME="Enable_Constraints" VALUE="1"/>
- <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
- <PARAMETER NAME="MII_BOARD_INTERFACE" VALUE="mii"/>
- <PARAMETER NAME="MDIO_BOARD_INTERFACE" VALUE="mdio_mdc"/>
- <PARAMETER NAME="C_USE_INTERNAL" VALUE="0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x40E00000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0x40E0FFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="ip2intc_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_ethernetlite_0_ip2intc_irpt">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="12" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="12" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="phy_tx_clk" SIGIS="undef"/>
- <PORT DIR="I" NAME="phy_rx_clk" SIGIS="undef"/>
- <PORT DIR="I" NAME="phy_crs" SIGIS="undef"/>
- <PORT DIR="I" NAME="phy_dv" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="phy_rx_data" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="I" NAME="phy_col" SIGIS="undef"/>
- <PORT DIR="I" NAME="phy_rx_er" SIGIS="undef"/>
- <PORT DIR="O" NAME="phy_rst_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="phy_tx_en" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="phy_tx_data" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="I" NAME="phy_mdio_i" SIGIS="undef"/>
- <PORT DIR="O" NAME="phy_mdio_o" SIGIS="undef"/>
- <PORT DIR="O" NAME="phy_mdio_t" SIGIS="undef"/>
- <PORT DIR="O" NAME="phy_mdc" SIGIS="undef"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M04_AXI" NAME="S_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="s_axi_araddr"/>
- <PORTMAP PHYSICAL="s_axi_arready"/>
- <PORTMAP PHYSICAL="s_axi_arvalid"/>
- <PORTMAP PHYSICAL="s_axi_awaddr"/>
- <PORTMAP PHYSICAL="s_axi_awready"/>
- <PORTMAP PHYSICAL="s_axi_awvalid"/>
- <PORTMAP PHYSICAL="s_axi_bready"/>
- <PORTMAP PHYSICAL="s_axi_bresp"/>
- <PORTMAP PHYSICAL="s_axi_bvalid"/>
- <PORTMAP PHYSICAL="s_axi_rdata"/>
- <PORTMAP PHYSICAL="s_axi_rready"/>
- <PORTMAP PHYSICAL="s_axi_rresp"/>
- <PORTMAP PHYSICAL="s_axi_rvalid"/>
- <PORTMAP PHYSICAL="s_axi_wdata"/>
- <PORTMAP PHYSICAL="s_axi_wready"/>
- <PORTMAP PHYSICAL="s_axi_wstrb"/>
- <PORTMAP PHYSICAL="s_axi_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_ethernetlite_0_MII" NAME="MII" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="phy_col"/>
- <PORTMAP PHYSICAL="phy_crs"/>
- <PORTMAP PHYSICAL="phy_rst_n"/>
- <PORTMAP PHYSICAL="phy_rx_clk"/>
- <PORTMAP PHYSICAL="phy_dv"/>
- <PORTMAP PHYSICAL="phy_rx_er"/>
- <PORTMAP PHYSICAL="phy_rx_data"/>
- <PORTMAP PHYSICAL="phy_tx_clk"/>
- <PORTMAP PHYSICAL="phy_tx_en"/>
- <PORTMAP PHYSICAL="phy_tx_data"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_ethernetlite_0_MDIO" NAME="MDIO" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="phy_mdc"/>
- <PORTMAP PHYSICAL="phy_mdio_i"/>
- <PORTMAP PHYSICAL="phy_mdio_o"/>
- <PORTMAP PHYSICAL="phy_mdio_t"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="2"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
- <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_GPIO_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C_GPIO2_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_ALL_INPUTS" VALUE="0"/>
- <PARAMETER NAME="C_ALL_INPUTS_2" VALUE="0"/>
- <PARAMETER NAME="C_ALL_OUTPUTS" VALUE="1"/>
- <PARAMETER NAME="C_ALL_OUTPUTS_2" VALUE="0"/>
- <PARAMETER NAME="C_INTERRUPT_PRESENT" VALUE="0"/>
- <PARAMETER NAME="C_DOUT_DEFAULT" VALUE="0x00000000"/>
- <PARAMETER NAME="C_TRI_DEFAULT" VALUE="0xFFFFFFFF"/>
- <PARAMETER NAME="C_IS_DUAL" VALUE="0"/>
- <PARAMETER NAME="C_DOUT_DEFAULT_2" VALUE="0x00000000"/>
- <PARAMETER NAME="C_TRI_DEFAULT_2" VALUE="0xFFFFFFFF"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_gpio_0_0"/>
- <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
- <PARAMETER NAME="GPIO_BOARD_INTERFACE" VALUE="led_8bits"/>
- <PARAMETER NAME="GPIO2_BOARD_INTERFACE" VALUE="Custom"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x40000000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0x4000FFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="7" NAME="gpio_io_o" RIGHT="0" SIGIS="undef"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M01_AXI" NAME="S_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="s_axi_araddr"/>
- <PORTMAP PHYSICAL="s_axi_arready"/>
- <PORTMAP PHYSICAL="s_axi_arvalid"/>
- <PORTMAP PHYSICAL="s_axi_awaddr"/>
- <PORTMAP PHYSICAL="s_axi_awready"/>
- <PORTMAP PHYSICAL="s_axi_awvalid"/>
- <PORTMAP PHYSICAL="s_axi_bready"/>
- <PORTMAP PHYSICAL="s_axi_bresp"/>
- <PORTMAP PHYSICAL="s_axi_bvalid"/>
- <PORTMAP PHYSICAL="s_axi_rdata"/>
- <PORTMAP PHYSICAL="s_axi_rready"/>
- <PORTMAP PHYSICAL="s_axi_rresp"/>
- <PORTMAP PHYSICAL="s_axi_rvalid"/>
- <PORTMAP PHYSICAL="s_axi_wdata"/>
- <PORTMAP PHYSICAL="s_axi_wready"/>
- <PORTMAP PHYSICAL="s_axi_wstrb"/>
- <PORTMAP PHYSICAL="s_axi_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_gpio_0_GPIO" NAME="GPIO" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="gpio_io_o"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/axi_intc_0" HWVERSION="4.1" INSTANCE="axi_intc_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc" VLNV="xilinx.com:ip:axi_intc:4.1">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_intc;v=v4_1;d=pg099-axi-intc.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_INSTANCE" VALUE="axi_intc_inst"/>
- <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
- <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_NUM_INTR_INPUTS" VALUE="3"/>
- <PARAMETER NAME="C_NUM_SW_INTR" VALUE="0"/>
- <PARAMETER NAME="C_KIND_OF_INTR" VALUE="0xfffffffe"/>
- <PARAMETER NAME="C_KIND_OF_EDGE" VALUE="0xffffffff"/>
- <PARAMETER NAME="C_KIND_OF_LVL" VALUE="0xffffffff"/>
- <PARAMETER NAME="C_ASYNC_INTR" VALUE="0xFFFFFFF8"/>
- <PARAMETER NAME="C_NUM_SYNC_FF" VALUE="2"/>
- <PARAMETER NAME="C_IVAR_RESET_VALUE" VALUE="0x00000010"/>
- <PARAMETER NAME="C_ENABLE_ASYNC" VALUE="0"/>
- <PARAMETER NAME="C_HAS_IPR" VALUE="1"/>
- <PARAMETER NAME="C_HAS_SIE" VALUE="1"/>
- <PARAMETER NAME="C_HAS_CIE" VALUE="1"/>
- <PARAMETER NAME="C_HAS_IVR" VALUE="1"/>
- <PARAMETER NAME="C_HAS_ILR" VALUE="0"/>
- <PARAMETER NAME="C_IRQ_IS_LEVEL" VALUE="1"/>
- <PARAMETER NAME="C_IRQ_ACTIVE" VALUE="0x1"/>
- <PARAMETER NAME="C_DISABLE_SYNCHRONIZERS" VALUE="1"/>
- <PARAMETER NAME="C_MB_CLK_NOT_CONNECTED" VALUE="1"/>
- <PARAMETER NAME="C_HAS_FAST" VALUE="0"/>
- <PARAMETER NAME="C_EN_CASCADE_MODE" VALUE="0"/>
- <PARAMETER NAME="C_CASCADE_MASTER" VALUE="0"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_intc_0_0"/>
- <PARAMETER NAME="Sense_of_IRQ_Level_Type" VALUE="Active_High"/>
- <PARAMETER NAME="Sense_of_IRQ_Edge_Type" VALUE="Rising"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="EDK_SPECIAL" VALUE="INTR_CTRL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x41200000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0x4120FFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="intr" RIGHT="0" SENSITIVITY="EDGE_RISING:EDGE_RISING:LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_ethernetlite_0_ip2intc_irpt & axi_uartlite_0_interrupt & axi_timer_0_interrupt">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="ip2intc_irpt"/>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="interrupt"/>
- <CONNECTION INSTANCE="axi_timer_0" PORT="interrupt"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="irq" SIGIS="undef" SIGNAME="axi_intc_0_irq">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Interrupt"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M03_AXI" NAME="s_axi" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="s_axi_araddr"/>
- <PORTMAP PHYSICAL="s_axi_arready"/>
- <PORTMAP PHYSICAL="s_axi_arvalid"/>
- <PORTMAP PHYSICAL="s_axi_awaddr"/>
- <PORTMAP PHYSICAL="s_axi_awready"/>
- <PORTMAP PHYSICAL="s_axi_awvalid"/>
- <PORTMAP PHYSICAL="s_axi_bready"/>
- <PORTMAP PHYSICAL="s_axi_bresp"/>
- <PORTMAP PHYSICAL="s_axi_bvalid"/>
- <PORTMAP PHYSICAL="s_axi_rdata"/>
- <PORTMAP PHYSICAL="s_axi_rready"/>
- <PORTMAP PHYSICAL="s_axi_rresp"/>
- <PORTMAP PHYSICAL="s_axi_rvalid"/>
- <PORTMAP PHYSICAL="s_axi_wdata"/>
- <PORTMAP PHYSICAL="s_axi_wready"/>
- <PORTMAP PHYSICAL="s_axi_wstrb"/>
- <PORTMAP PHYSICAL="s_axi_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="interrupt" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="irq"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
- <SOURCE INSTANCE="axi_timer_0" PRIORITY="0" SIGNAME="axi_timer_0_interrupt"/>
- <SOURCE INSTANCE="axi_uartlite_0" PRIORITY="1" SIGNAME="axi_uartlite_0_interrupt"/>
- <SOURCE INSTANCE="axi_ethernetlite_0" PRIORITY="2" SIGNAME="axi_ethernetlite_0_ip2intc_irpt"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE FULLNAME="/axi_mem_intercon" HWVERSION="2.1" INSTANCE="axi_mem_intercon" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="NUM_SI" VALUE="2"/>
- <PARAMETER NAME="NUM_MI" VALUE="1"/>
- <PARAMETER NAME="STRATEGY" VALUE="0"/>
- <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
- <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
- <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
- <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
- <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
- <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
- <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
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- <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M00_SECURE" VALUE="0"/>
- <PARAMETER NAME="M01_SECURE" VALUE="0"/>
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- <PARAMETER NAME="M25_SECURE" VALUE="0"/>
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- <PARAMETER NAME="M27_SECURE" VALUE="0"/>
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- <PARAMETER NAME="M33_SECURE" VALUE="0"/>
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- <PARAMETER NAME="M37_SECURE" VALUE="0"/>
- <PARAMETER NAME="M38_SECURE" VALUE="0"/>
- <PARAMETER NAME="M39_SECURE" VALUE="0"/>
- <PARAMETER NAME="M40_SECURE" VALUE="0"/>
- <PARAMETER NAME="M41_SECURE" VALUE="0"/>
- <PARAMETER NAME="M42_SECURE" VALUE="0"/>
- <PARAMETER NAME="M43_SECURE" VALUE="0"/>
- <PARAMETER NAME="M44_SECURE" VALUE="0"/>
- <PARAMETER NAME="M45_SECURE" VALUE="0"/>
- <PARAMETER NAME="M46_SECURE" VALUE="0"/>
- <PARAMETER NAME="M47_SECURE" VALUE="0"/>
- <PARAMETER NAME="M48_SECURE" VALUE="0"/>
- <PARAMETER NAME="M49_SECURE" VALUE="0"/>
- <PARAMETER NAME="M50_SECURE" VALUE="0"/>
- <PARAMETER NAME="M51_SECURE" VALUE="0"/>
- <PARAMETER NAME="M52_SECURE" VALUE="0"/>
- <PARAMETER NAME="M53_SECURE" VALUE="0"/>
- <PARAMETER NAME="M54_SECURE" VALUE="0"/>
- <PARAMETER NAME="M55_SECURE" VALUE="0"/>
- <PARAMETER NAME="M56_SECURE" VALUE="0"/>
- <PARAMETER NAME="M57_SECURE" VALUE="0"/>
- <PARAMETER NAME="M58_SECURE" VALUE="0"/>
- <PARAMETER NAME="M59_SECURE" VALUE="0"/>
- <PARAMETER NAME="M60_SECURE" VALUE="0"/>
- <PARAMETER NAME="M61_SECURE" VALUE="0"/>
- <PARAMETER NAME="M62_SECURE" VALUE="0"/>
- <PARAMETER NAME="M63_SECURE" VALUE="0"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_mem_intercon_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="interconnect_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S01_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARBURST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARCACHE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARLEN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARLOCK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARQOS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARSIZE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWBURST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWCACHE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWLEN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWLOCK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWQOS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWSIZE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RLAST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WLAST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WSTRB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="7" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="7" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S01_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARBURST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARCACHE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S01_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARLEN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARLOCK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARQOS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARSIZE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWBURST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWCACHE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWLEN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWLOCK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWQOS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWSIZE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="S01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RLAST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WLAST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WSTRB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WVALID"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DC" NAME="S00_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="S00_AXI_araddr"/>
- <PORTMAP PHYSICAL="S00_AXI_arburst"/>
- <PORTMAP PHYSICAL="S00_AXI_arcache"/>
- <PORTMAP PHYSICAL="S00_AXI_arid"/>
- <PORTMAP PHYSICAL="S00_AXI_arlen"/>
- <PORTMAP PHYSICAL="S00_AXI_arlock"/>
- <PORTMAP PHYSICAL="S00_AXI_arprot"/>
- <PORTMAP PHYSICAL="S00_AXI_arqos"/>
- <PORTMAP PHYSICAL="S00_AXI_arready"/>
- <PORTMAP PHYSICAL="S00_AXI_arsize"/>
- <PORTMAP PHYSICAL="S00_AXI_arvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_awaddr"/>
- <PORTMAP PHYSICAL="S00_AXI_awburst"/>
- <PORTMAP PHYSICAL="S00_AXI_awcache"/>
- <PORTMAP PHYSICAL="S00_AXI_awid"/>
- <PORTMAP PHYSICAL="S00_AXI_awlen"/>
- <PORTMAP PHYSICAL="S00_AXI_awlock"/>
- <PORTMAP PHYSICAL="S00_AXI_awprot"/>
- <PORTMAP PHYSICAL="S00_AXI_awqos"/>
- <PORTMAP PHYSICAL="S00_AXI_awready"/>
- <PORTMAP PHYSICAL="S00_AXI_awsize"/>
- <PORTMAP PHYSICAL="S00_AXI_awvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_bid"/>
- <PORTMAP PHYSICAL="S00_AXI_bready"/>
- <PORTMAP PHYSICAL="S00_AXI_bresp"/>
- <PORTMAP PHYSICAL="S00_AXI_bvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_rdata"/>
- <PORTMAP PHYSICAL="S00_AXI_rid"/>
- <PORTMAP PHYSICAL="S00_AXI_rlast"/>
- <PORTMAP PHYSICAL="S00_AXI_rready"/>
- <PORTMAP PHYSICAL="S00_AXI_rresp"/>
- <PORTMAP PHYSICAL="S00_AXI_rvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_wdata"/>
- <PORTMAP PHYSICAL="S00_AXI_wlast"/>
- <PORTMAP PHYSICAL="S00_AXI_wready"/>
- <PORTMAP PHYSICAL="S00_AXI_wstrb"/>
- <PORTMAP PHYSICAL="S00_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" NAME="M00_AXI" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M00_AXI_awid"/>
- <PORTMAP PHYSICAL="M00_AXI_awaddr"/>
- <PORTMAP PHYSICAL="M00_AXI_awlen"/>
- <PORTMAP PHYSICAL="M00_AXI_awsize"/>
- <PORTMAP PHYSICAL="M00_AXI_awburst"/>
- <PORTMAP PHYSICAL="M00_AXI_awlock"/>
- <PORTMAP PHYSICAL="M00_AXI_awcache"/>
- <PORTMAP PHYSICAL="M00_AXI_awprot"/>
- <PORTMAP PHYSICAL="M00_AXI_awqos"/>
- <PORTMAP PHYSICAL="M00_AXI_awvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_awready"/>
- <PORTMAP PHYSICAL="M00_AXI_wdata"/>
- <PORTMAP PHYSICAL="M00_AXI_wstrb"/>
- <PORTMAP PHYSICAL="M00_AXI_wlast"/>
- <PORTMAP PHYSICAL="M00_AXI_wvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_wready"/>
- <PORTMAP PHYSICAL="M00_AXI_bready"/>
- <PORTMAP PHYSICAL="M00_AXI_bid"/>
- <PORTMAP PHYSICAL="M00_AXI_bresp"/>
- <PORTMAP PHYSICAL="M00_AXI_bvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_arid"/>
- <PORTMAP PHYSICAL="M00_AXI_araddr"/>
- <PORTMAP PHYSICAL="M00_AXI_arlen"/>
- <PORTMAP PHYSICAL="M00_AXI_arsize"/>
- <PORTMAP PHYSICAL="M00_AXI_arburst"/>
- <PORTMAP PHYSICAL="M00_AXI_arlock"/>
- <PORTMAP PHYSICAL="M00_AXI_arcache"/>
- <PORTMAP PHYSICAL="M00_AXI_arprot"/>
- <PORTMAP PHYSICAL="M00_AXI_arqos"/>
- <PORTMAP PHYSICAL="M00_AXI_arvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_arready"/>
- <PORTMAP PHYSICAL="M00_AXI_rready"/>
- <PORTMAP PHYSICAL="M00_AXI_rid"/>
- <PORTMAP PHYSICAL="M00_AXI_rdata"/>
- <PORTMAP PHYSICAL="M00_AXI_rresp"/>
- <PORTMAP PHYSICAL="M00_AXI_rlast"/>
- <PORTMAP PHYSICAL="M00_AXI_rvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_IC" NAME="S01_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="S01_AXI_araddr"/>
- <PORTMAP PHYSICAL="S01_AXI_arburst"/>
- <PORTMAP PHYSICAL="S01_AXI_arcache"/>
- <PORTMAP PHYSICAL="S01_AXI_arid"/>
- <PORTMAP PHYSICAL="S01_AXI_arlen"/>
- <PORTMAP PHYSICAL="S01_AXI_arlock"/>
- <PORTMAP PHYSICAL="S01_AXI_arprot"/>
- <PORTMAP PHYSICAL="S01_AXI_arqos"/>
- <PORTMAP PHYSICAL="S01_AXI_arready"/>
- <PORTMAP PHYSICAL="S01_AXI_arsize"/>
- <PORTMAP PHYSICAL="S01_AXI_arvalid"/>
- <PORTMAP PHYSICAL="S01_AXI_awaddr"/>
- <PORTMAP PHYSICAL="S01_AXI_awburst"/>
- <PORTMAP PHYSICAL="S01_AXI_awcache"/>
- <PORTMAP PHYSICAL="S01_AXI_awid"/>
- <PORTMAP PHYSICAL="S01_AXI_awlen"/>
- <PORTMAP PHYSICAL="S01_AXI_awlock"/>
- <PORTMAP PHYSICAL="S01_AXI_awprot"/>
- <PORTMAP PHYSICAL="S01_AXI_awqos"/>
- <PORTMAP PHYSICAL="S01_AXI_awready"/>
- <PORTMAP PHYSICAL="S01_AXI_awsize"/>
- <PORTMAP PHYSICAL="S01_AXI_awvalid"/>
- <PORTMAP PHYSICAL="S01_AXI_bid"/>
- <PORTMAP PHYSICAL="S01_AXI_bready"/>
- <PORTMAP PHYSICAL="S01_AXI_bresp"/>
- <PORTMAP PHYSICAL="S01_AXI_bvalid"/>
- <PORTMAP PHYSICAL="S01_AXI_rdata"/>
- <PORTMAP PHYSICAL="S01_AXI_rid"/>
- <PORTMAP PHYSICAL="S01_AXI_rlast"/>
- <PORTMAP PHYSICAL="S01_AXI_rready"/>
- <PORTMAP PHYSICAL="S01_AXI_rresp"/>
- <PORTMAP PHYSICAL="S01_AXI_rvalid"/>
- <PORTMAP PHYSICAL="S01_AXI_wdata"/>
- <PORTMAP PHYSICAL="S01_AXI_wlast"/>
- <PORTMAP PHYSICAL="S01_AXI_wready"/>
- <PORTMAP PHYSICAL="S01_AXI_wstrb"/>
- <PORTMAP PHYSICAL="S01_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/axi_timer_0" HWVERSION="2.0" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_timer" VLNV="xilinx.com:ip:axi_timer:2.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v2_0;d=pg079-axi-timer.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_COUNT_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_ONE_TIMER_ONLY" VALUE="0"/>
- <PARAMETER NAME="C_TRIG0_ASSERT" VALUE=""1""/>
- <PARAMETER NAME="C_TRIG1_ASSERT" VALUE=""1""/>
- <PARAMETER NAME="C_GEN0_ASSERT" VALUE=""1""/>
- <PARAMETER NAME="C_GEN1_ASSERT" VALUE=""1""/>
- <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="5"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_timer_0_0"/>
- <PARAMETER NAME="TRIG0_ASSERT" VALUE="Active_High"/>
- <PARAMETER NAME="TRIG1_ASSERT" VALUE="Active_High"/>
- <PARAMETER NAME="GEN0_ASSERT" VALUE="Active_High"/>
- <PARAMETER NAME="GEN1_ASSERT" VALUE="Active_High"/>
- <PARAMETER NAME="COUNT_WIDTH" VALUE="32"/>
- <PARAMETER NAME="mode_64bit" VALUE="0"/>
- <PARAMETER NAME="enable_timer2" VALUE="1"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x41C00000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0x41C0FFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" NAME="capturetrig0" SIGIS="undef"/>
- <PORT DIR="I" NAME="capturetrig1" SIGIS="undef"/>
- <PORT DIR="O" NAME="generateout0" SIGIS="undef"/>
- <PORT DIR="O" NAME="generateout1" SIGIS="undef"/>
- <PORT DIR="O" NAME="pwm0" SIGIS="undef"/>
- <PORT DIR="O" NAME="interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_interrupt">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="freeze" SIGIS="undef"/>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="4" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="4" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M02_AXI" NAME="S_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="s_axi_araddr"/>
- <PORTMAP PHYSICAL="s_axi_arready"/>
- <PORTMAP PHYSICAL="s_axi_arvalid"/>
- <PORTMAP PHYSICAL="s_axi_awaddr"/>
- <PORTMAP PHYSICAL="s_axi_awready"/>
- <PORTMAP PHYSICAL="s_axi_awvalid"/>
- <PORTMAP PHYSICAL="s_axi_bready"/>
- <PORTMAP PHYSICAL="s_axi_bresp"/>
- <PORTMAP PHYSICAL="s_axi_bvalid"/>
- <PORTMAP PHYSICAL="s_axi_rdata"/>
- <PORTMAP PHYSICAL="s_axi_rready"/>
- <PORTMAP PHYSICAL="s_axi_rresp"/>
- <PORTMAP PHYSICAL="s_axi_rvalid"/>
- <PORTMAP PHYSICAL="s_axi_wdata"/>
- <PORTMAP PHYSICAL="s_axi_wready"/>
- <PORTMAP PHYSICAL="s_axi_wstrb"/>
- <PORTMAP PHYSICAL="s_axi_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="0"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE FULLNAME="/axi_uartlite_0" HWVERSION="2.0" INSTANCE="axi_uartlite_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite" VLNV="xilinx.com:ip:axi_uartlite:2.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_uartlite;v=v2_0;d=pg142-axi-uartlite.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
- <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_BAUDRATE" VALUE="115200"/>
- <PARAMETER NAME="C_DATA_BITS" VALUE="8"/>
- <PARAMETER NAME="C_USE_PARITY" VALUE="0"/>
- <PARAMETER NAME="C_ODD_PARITY" VALUE="0"/>
- <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ_d" VALUE="100"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_uartlite_0_0"/>
- <PARAMETER NAME="PARITY" VALUE="No_Parity"/>
- <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
- <PARAMETER NAME="UARTLITE_BOARD_INTERFACE" VALUE="rs232_uart"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x40600000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0x4060FFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_uartlite_0_interrupt">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="rx" SIGIS="undef"/>
- <PORT DIR="O" NAME="tx" SIGIS="undef"/>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M00_AXI" NAME="S_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="s_axi_araddr"/>
- <PORTMAP PHYSICAL="s_axi_arready"/>
- <PORTMAP PHYSICAL="s_axi_arvalid"/>
- <PORTMAP PHYSICAL="s_axi_awaddr"/>
- <PORTMAP PHYSICAL="s_axi_awready"/>
- <PORTMAP PHYSICAL="s_axi_awvalid"/>
- <PORTMAP PHYSICAL="s_axi_bready"/>
- <PORTMAP PHYSICAL="s_axi_bresp"/>
- <PORTMAP PHYSICAL="s_axi_bvalid"/>
- <PORTMAP PHYSICAL="s_axi_rdata"/>
- <PORTMAP PHYSICAL="s_axi_rready"/>
- <PORTMAP PHYSICAL="s_axi_rresp"/>
- <PORTMAP PHYSICAL="s_axi_rvalid"/>
- <PORTMAP PHYSICAL="s_axi_wdata"/>
- <PORTMAP PHYSICAL="s_axi_wready"/>
- <PORTMAP PHYSICAL="s_axi_wstrb"/>
- <PORTMAP PHYSICAL="s_axi_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_uartlite_0_UART" NAME="UART" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="rx"/>
- <PORTMAP PHYSICAL="tx"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="1"/>
- </INTERRUPTINFO>
- </MODULE>
- <MODULE FULLNAME="/mdm_1" HWVERSION="3.2" INSTANCE="mdm_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="DEBUG" MODTYPE="mdm" VLNV="xilinx.com:ip:mdm:3.2">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=mdm;v=v3_2;d=pg115-mdm.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_JTAG_CHAIN" VALUE="2"/>
- <PARAMETER NAME="C_USE_BSCAN" VALUE="0"/>
- <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
- <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
- <PARAMETER NAME="C_MB_DBG_PORTS" VALUE="1"/>
- <PARAMETER NAME="C_USE_UART" VALUE="0"/>
- <PARAMETER NAME="C_DBG_REG_ACCESS" VALUE="0"/>
- <PARAMETER NAME="C_DBG_MEM_ACCESS" VALUE="0"/>
- <PARAMETER NAME="C_USE_CROSS_TRIGGER" VALUE="0"/>
- <PARAMETER NAME="C_TRACE_OUTPUT" VALUE="0"/>
- <PARAMETER NAME="C_TRACE_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_TRACE_CLK_FREQ_HZ" VALUE="200000000"/>
- <PARAMETER NAME="C_TRACE_CLK_OUT_PHASE" VALUE="90"/>
- <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
- <PARAMETER NAME="C_M_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_THREAD_ID_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
- <PARAMETER NAME="C_M_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXIS_ID_WIDTH" VALUE="7"/>
- <PARAMETER NAME="C_XMTC" VALUE="0"/>
- <PARAMETER NAME="C_BRK" VALUE="0"/>
- <PARAMETER NAME="C_TRIG_IN_PORTS" VALUE="1"/>
- <PARAMETER NAME="C_TRIG_OUT_PORTS" VALUE="1"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_mdm_1_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="O" NAME="Debug_SYS_Rst" SIGIS="rst" SIGNAME="mdm_1_Debug_SYS_Rst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="mb_debug_sys_rst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Dbg_Clk_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Clk_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Dbg_TDI_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDI_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDI"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Dbg_TDO_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDO_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDO"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGIS="undef" SIGNAME="mdm_1_Dbg_Reg_En_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Reg_En"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Dbg_Capture_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Capture_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Capture"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Dbg_Shift_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Shift_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Shift"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Dbg_Update_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Update_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Update"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Dbg_Rst_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Rst_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Debug_Rst"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="mdm_1_MBDEBUG_0" NAME="MBDEBUG_0" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="Dbg_Capture_0"/>
- <PORTMAP PHYSICAL="Dbg_Clk_0"/>
- <PORTMAP PHYSICAL="Dbg_Reg_En_0"/>
- <PORTMAP PHYSICAL="Dbg_Rst_0"/>
- <PORTMAP PHYSICAL="Dbg_Shift_0"/>
- <PORTMAP PHYSICAL="Dbg_TDI_0"/>
- <PORTMAP PHYSICAL="Dbg_TDO_0"/>
- <PORTMAP PHYSICAL="Dbg_Update_0"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP/>
- <PERIPHERALS>
- <PERIPHERAL INSTANCE="microblaze_0"/>
- </PERIPHERALS>
- </MODULE>
- <MODULE FULLNAME="/microblaze_0" HWVERSION="9.4" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" IS_ENABLE="1" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="microblaze" VLNV="xilinx.com:ip:microblaze:9.4">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/rdoc?v=2014.3;d=ug984-vivado-microblaze-ref.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_SCO" VALUE="0"/>
- <PARAMETER NAME="C_FREQ" VALUE="100000000"/>
- <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
- <PARAMETER NAME="C_NUM_SYNC_FF_CLK" VALUE="2"/>
- <PARAMETER NAME="C_NUM_SYNC_FF_CLK_IRQ" VALUE="1"/>
- <PARAMETER NAME="C_NUM_SYNC_FF_CLK_DEBUG" VALUE="2"/>
- <PARAMETER NAME="C_NUM_SYNC_FF_DBG_CLK" VALUE="1"/>
- <PARAMETER NAME="C_FAULT_TOLERANT" VALUE="0"/>
- <PARAMETER NAME="C_ECC_USE_CE_EXCEPTION" VALUE="0"/>
- <PARAMETER NAME="C_LOCKSTEP_SLAVE" VALUE="0"/>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
- <PARAMETER NAME="C_INSTANCE" VALUE="base_microblaze_design_microblaze_0_0"/>
- <PARAMETER NAME="C_AVOID_PRIMITIVES" VALUE="0"/>
- <PARAMETER NAME="C_AREA_OPTIMIZED" VALUE="0"/>
- <PARAMETER NAME="C_OPTIMIZATION" VALUE="0"/>
- <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
- <PARAMETER NAME="C_BASE_VECTORS" VALUE="0x00000000"/>
- <PARAMETER NAME="C_M_AXI_DP_THREAD_ID_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_DP_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_DP_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" VALUE="0"/>
- <PARAMETER NAME="C_M_AXI_D_BUS_EXCEPTION" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_IP_THREAD_ID_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_IP_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_IP_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_I_BUS_EXCEPTION" VALUE="1"/>
- <PARAMETER NAME="C_D_LMB" VALUE="1"/>
- <PARAMETER NAME="C_D_AXI" VALUE="1"/>
- <PARAMETER NAME="C_I_LMB" VALUE="1"/>
- <PARAMETER NAME="C_I_AXI" VALUE="0"/>
- <PARAMETER NAME="C_USE_MSR_INSTR" VALUE="1"/>
- <PARAMETER NAME="C_USE_PCMP_INSTR" VALUE="1"/>
- <PARAMETER NAME="C_USE_BARREL" VALUE="1"/>
- <PARAMETER NAME="C_USE_DIV" VALUE="1"/>
- <PARAMETER NAME="C_USE_HW_MUL" VALUE="2"/>
- <PARAMETER NAME="C_USE_FPU" VALUE="2"/>
- <PARAMETER NAME="C_USE_REORDER_INSTR" VALUE="1"/>
- <PARAMETER NAME="C_UNALIGNED_EXCEPTIONS" VALUE="1"/>
- <PARAMETER NAME="C_ILL_OPCODE_EXCEPTION" VALUE="1"/>
- <PARAMETER NAME="C_DIV_ZERO_EXCEPTION" VALUE="1"/>
- <PARAMETER NAME="C_FPU_EXCEPTION" VALUE="1"/>
- <PARAMETER NAME="C_FSL_LINKS" VALUE="0"/>
- <PARAMETER NAME="C_USE_EXTENDED_FSL_INSTR" VALUE="0"/>
- <PARAMETER NAME="C_FSL_EXCEPTION" VALUE="0"/>
- <PARAMETER NAME="C_USE_STACK_PROTECTION" VALUE="1"/>
- <PARAMETER NAME="C_USE_INTERRUPT" VALUE="1"/>
- <PARAMETER NAME="C_USE_EXT_BRK" VALUE="0"/>
- <PARAMETER NAME="C_USE_EXT_NM_BRK" VALUE="0"/>
- <PARAMETER NAME="C_USE_MMU" VALUE="0"/>
- <PARAMETER NAME="C_MMU_DTLB_SIZE" VALUE="4"/>
- <PARAMETER NAME="C_MMU_ITLB_SIZE" VALUE="2"/>
- <PARAMETER NAME="C_MMU_TLB_ACCESS" VALUE="3"/>
- <PARAMETER NAME="C_MMU_ZONES" VALUE="2"/>
- <PARAMETER NAME="C_MMU_PRIVILEGED_INSTR" VALUE="0"/>
- <PARAMETER NAME="C_USE_BRANCH_TARGET_CACHE" VALUE="1"/>
- <PARAMETER NAME="C_BRANCH_TARGET_CACHE_SIZE" VALUE="0"/>
- <PARAMETER NAME="C_PC_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_PVR" VALUE="0"/>
- <PARAMETER NAME="C_PVR_USER1" VALUE="0x00"/>
- <PARAMETER NAME="C_PVR_USER2" VALUE="0x00000000"/>
- <PARAMETER NAME="C_DYNAMIC_BUS_SIZING" VALUE="0"/>
- <PARAMETER NAME="C_RESET_MSR" VALUE="0x00000000"/>
- <PARAMETER NAME="C_OPCODE_0x0_ILLEGAL" VALUE="1"/>
- <PARAMETER NAME="C_DEBUG_ENABLED" VALUE="1"/>
- <PARAMETER NAME="C_NUMBER_OF_PC_BRK" VALUE="8"/>
- <PARAMETER NAME="C_NUMBER_OF_RD_ADDR_BRK" VALUE="2"/>
- <PARAMETER NAME="C_NUMBER_OF_WR_ADDR_BRK" VALUE="2"/>
- <PARAMETER NAME="C_DEBUG_EVENT_COUNTERS" VALUE="5"/>
- <PARAMETER NAME="C_DEBUG_LATENCY_COUNTERS" VALUE="1"/>
- <PARAMETER NAME="C_DEBUG_COUNTER_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_DEBUG_TRACE_SIZE" VALUE="8192"/>
- <PARAMETER NAME="C_DEBUG_EXTERNAL_TRACE" VALUE="0"/>
- <PARAMETER NAME="C_DEBUG_PROFILE_SIZE" VALUE="0"/>
- <PARAMETER NAME="C_INTERRUPT_IS_EDGE" VALUE="0"/>
- <PARAMETER NAME="C_EDGE_IS_POSITIVE" VALUE="1"/>
- <PARAMETER NAME="C_ASYNC_INTERRUPT" VALUE="1"/>
- <PARAMETER NAME="C_M0_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S0_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M1_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S1_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M2_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S2_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M3_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S3_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M4_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S4_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M5_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S5_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M6_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S6_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M7_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S7_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M8_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S8_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M9_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S9_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M10_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S10_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M11_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S11_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M12_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S12_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M13_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S13_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M14_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S14_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M15_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S15_AXIS_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_ICACHE_BASEADDR" VALUE="0x80000000"/>
- <PARAMETER NAME="C_ICACHE_HIGHADDR" VALUE="0xbfffffff"/>
- <PARAMETER NAME="C_USE_ICACHE" VALUE="1"/>
- <PARAMETER NAME="C_ALLOW_ICACHE_WR" VALUE="1"/>
- <PARAMETER NAME="C_ADDR_TAG_BITS" VALUE="15"/>
- <PARAMETER NAME="C_CACHE_BYTE_SIZE" VALUE="32768"/>
- <PARAMETER NAME="C_ICACHE_LINE_LEN" VALUE="8"/>
- <PARAMETER NAME="C_ICACHE_ALWAYS_USED" VALUE="1"/>
- <PARAMETER NAME="C_ICACHE_STREAMS" VALUE="1"/>
- <PARAMETER NAME="C_ICACHE_VICTIMS" VALUE="8"/>
- <PARAMETER NAME="C_ICACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
- <PARAMETER NAME="C_ICACHE_DATA_WIDTH" VALUE="0"/>
- <PARAMETER NAME="C_M_AXI_IC_THREAD_ID_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_IC_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_IC_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_IC_USER_VALUE" VALUE="31"/>
- <PARAMETER NAME="C_M_AXI_IC_AWUSER_WIDTH" VALUE="5"/>
- <PARAMETER NAME="C_M_AXI_IC_ARUSER_WIDTH" VALUE="5"/>
- <PARAMETER NAME="C_M_AXI_IC_WUSER_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_IC_RUSER_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_IC_BUSER_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_DCACHE_BASEADDR" VALUE="0x80000000"/>
- <PARAMETER NAME="C_DCACHE_HIGHADDR" VALUE="0xbfffffff"/>
- <PARAMETER NAME="C_USE_DCACHE" VALUE="1"/>
- <PARAMETER NAME="C_ALLOW_DCACHE_WR" VALUE="1"/>
- <PARAMETER NAME="C_DCACHE_ADDR_TAG" VALUE="15"/>
- <PARAMETER NAME="C_DCACHE_BYTE_SIZE" VALUE="32768"/>
- <PARAMETER NAME="C_DCACHE_LINE_LEN" VALUE="8"/>
- <PARAMETER NAME="C_DCACHE_ALWAYS_USED" VALUE="1"/>
- <PARAMETER NAME="C_DCACHE_USE_WRITEBACK" VALUE="1"/>
- <PARAMETER NAME="C_DCACHE_VICTIMS" VALUE="8"/>
- <PARAMETER NAME="C_DCACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
- <PARAMETER NAME="C_DCACHE_DATA_WIDTH" VALUE="0"/>
- <PARAMETER NAME="C_M_AXI_DC_THREAD_ID_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_DC_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_DC_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" VALUE="0"/>
- <PARAMETER NAME="C_M_AXI_DC_USER_VALUE" VALUE="31"/>
- <PARAMETER NAME="C_M_AXI_DC_AWUSER_WIDTH" VALUE="5"/>
- <PARAMETER NAME="C_M_AXI_DC_ARUSER_WIDTH" VALUE="5"/>
- <PARAMETER NAME="C_M_AXI_DC_WUSER_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_DC_RUSER_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_M_AXI_DC_BUSER_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_TRACE" VALUE="1"/>
- <PARAMETER NAME="C_LOCKSTEP_SELECT" VALUE="0"/>
- <PARAMETER NAME="C_ENABLE_DISCRETE_PORTS" VALUE="0"/>
- <PARAMETER NAME="C_M_AXI_DC_USER_SIGNALS" VALUE="0"/>
- <PARAMETER NAME="C_M_AXI_IC_USER_SIGNALS" VALUE="0"/>
- <PARAMETER NAME="G_TEMPLATE_LIST" VALUE="2"/>
- <PARAMETER NAME="G_USE_EXCEPTIONS" VALUE="1"/>
- <PARAMETER NAME="C_M0_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S0_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M1_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S1_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M2_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S2_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M3_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S3_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M4_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S4_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M5_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S5_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M6_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S6_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M7_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S7_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M8_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S8_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M9_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S9_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M10_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S10_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M11_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S11_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M12_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S12_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M13_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S13_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M14_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S14_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_M15_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="C_S15_AXIS_PROTOCOL" VALUE="GENERIC"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_microblaze_0_0"/>
- <PARAMETER NAME="C_ENDIANNESS" VALUE="1"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PROCESSOR"/>
- <PARAMETER NAME="EDK_SPECIAL" VALUE="microblaze"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Reset" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_mb_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="mb_reset"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Interrupt" SIGIS="INTERRUPT" SIGNAME="axi_intc_0_irq">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="irq"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Interrupt_Address" RIGHT="31" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Interrupt_Ack" RIGHT="1" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Instr_Addr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr_Addr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_ABus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Instr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ReadDBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="IFetch" SIGIS="undef" SIGNAME="microblaze_0_IFetch">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_ReadStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="I_AS" SIGIS="undef" SIGNAME="microblaze_0_I_AS">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_AddrStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="IReady" SIGIS="undef" SIGNAME="microblaze_0_IReady">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Ready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="IWAIT" SIGIS="undef" SIGNAME="microblaze_0_IWAIT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Wait"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="ICE" SIGIS="undef" SIGNAME="microblaze_0_ICE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_CE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="IUE" SIGIS="undef" SIGNAME="microblaze_0_IUE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_UE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="Data_Addr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Addr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_ABus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Data_Read" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Read">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ReadDBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="Data_Write" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Write">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_DBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="D_AS" SIGIS="undef" SIGNAME="microblaze_0_D_AS">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_AddrStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Read_Strobe" SIGIS="undef" SIGNAME="microblaze_0_Read_Strobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_ReadStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Write_Strobe" SIGIS="undef" SIGNAME="microblaze_0_Write_Strobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_WriteStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="DReady" SIGIS="undef" SIGNAME="microblaze_0_DReady">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Ready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="DWait" SIGIS="undef" SIGNAME="microblaze_0_DWait">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Wait"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="DCE" SIGIS="undef" SIGNAME="microblaze_0_DCE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_CE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="DUE" SIGIS="undef" SIGNAME="microblaze_0_DUE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_UE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="Byte_Enable" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_Byte_Enable">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_BE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWPROT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DP_AWVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DP_AWREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WSTRB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DP_WVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DP_WREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DP_BVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DP_BREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARPROT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DP_ARVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DP_ARREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DP_RVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DP_RREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Dbg_Clk" SIGIS="undef" SIGNAME="mdm_1_Dbg_Clk_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Clk_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Dbg_TDI" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDI_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_TDI_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Dbg_TDO" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDO_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_TDO_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Dbg_Reg_En" RIGHT="7" SIGIS="undef" SIGNAME="mdm_1_Dbg_Reg_En_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Reg_En_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Dbg_Shift" SIGIS="undef" SIGNAME="mdm_1_Dbg_Shift_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Shift_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Dbg_Capture" SIGIS="undef" SIGNAME="mdm_1_Dbg_Capture_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Capture_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Dbg_Update" SIGIS="undef" SIGNAME="mdm_1_Dbg_Update_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Update_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="Debug_Rst" SIGIS="undef" SIGNAME="mdm_1_Dbg_Rst_0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Rst_0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="Trace_Instruction" RIGHT="31" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Valid_Instr" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_PC" RIGHT="31" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Reg_Write" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_PID_Reg" RIGHT="7" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Exception_Taken" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Jump_Taken" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Delay_Slot" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_Data_Address" RIGHT="31" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Data_Access" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Data_Read" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Data_Write" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_DCache_Req" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_DCache_Hit" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_DCache_Rdy" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_DCache_Read" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_ICache_Req" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_ICache_Hit" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_ICache_Rdy" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_OF_PipeRun" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_EX_PipeRun" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_MEM_PipeRun" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_MB_Halted" SIGIS="undef"/>
- <PORT DIR="O" NAME="Trace_Jump_Hit" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M_AXI_IC_AWID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_AWLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_AWVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_IC_AWREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_WLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_WVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_IC_WREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M_AXI_IC_BID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_IC_BVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_BREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M_AXI_IC_ARID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_ARLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_ARVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_IC_ARREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M_AXI_IC_RID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_IC_RLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_IC_RVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_IC_RREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M_AXI_DC_AWID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_AWLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_AWVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DC_AWREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_WLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_WVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DC_WREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M_AXI_DC_BID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DC_BVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_BREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M_AXI_DC_ARID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_ARLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_ARVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DC_ARREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M_AXI_DC_RID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DC_RLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AXI_DC_RVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M_AXI_DC_RREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="INTERRUPT" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP PHYSICAL="Interrupt_Ack"/>
- <PORTMAP PHYSICAL="Interrupt_Address"/>
- <PORTMAP PHYSICAL="Interrupt"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_DLMB" NAME="DLMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="Data_Addr"/>
- <PORTMAP PHYSICAL="D_AS"/>
- <PORTMAP PHYSICAL="Byte_Enable"/>
- <PORTMAP PHYSICAL="DCE"/>
- <PORTMAP PHYSICAL="Data_Read"/>
- <PORTMAP PHYSICAL="Read_Strobe"/>
- <PORTMAP PHYSICAL="DReady"/>
- <PORTMAP PHYSICAL="DUE"/>
- <PORTMAP PHYSICAL="DWait"/>
- <PORTMAP PHYSICAL="Data_Write"/>
- <PORTMAP PHYSICAL="Write_Strobe"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_ILMB" NAME="ILMB" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="Instr_Addr"/>
- <PORTMAP PHYSICAL="I_AS"/>
- <PORTMAP PHYSICAL="ICE"/>
- <PORTMAP PHYSICAL="Instr"/>
- <PORTMAP PHYSICAL="IFetch"/>
- <PORTMAP PHYSICAL="IReady"/>
- <PORTMAP PHYSICAL="IUE"/>
- <PORTMAP PHYSICAL="IWAIT"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" NAME="M_AXI_DP" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M_AXI_DP_ARADDR"/>
- <PORTMAP PHYSICAL="M_AXI_DP_ARPROT"/>
- <PORTMAP PHYSICAL="M_AXI_DP_ARREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DP_ARVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DP_AWADDR"/>
- <PORTMAP PHYSICAL="M_AXI_DP_AWPROT"/>
- <PORTMAP PHYSICAL="M_AXI_DP_AWREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DP_AWVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DP_BREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DP_BRESP"/>
- <PORTMAP PHYSICAL="M_AXI_DP_BVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DP_RDATA"/>
- <PORTMAP PHYSICAL="M_AXI_DP_RREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DP_RRESP"/>
- <PORTMAP PHYSICAL="M_AXI_DP_RVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DP_WDATA"/>
- <PORTMAP PHYSICAL="M_AXI_DP_WREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DP_WSTRB"/>
- <PORTMAP PHYSICAL="M_AXI_DP_WVALID"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DC" NAME="M_AXI_DC" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M_AXI_DC_ARADDR"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARBURST"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARCACHE"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARLEN"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARLOCK"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARPROT"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARQOS"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARSIZE"/>
- <PORTMAP PHYSICAL="M_AXI_DC_ARVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWADDR"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWBURST"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWCACHE"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWLEN"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWLOCK"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWPROT"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWQOS"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWSIZE"/>
- <PORTMAP PHYSICAL="M_AXI_DC_AWVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_BID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_BREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DC_BRESP"/>
- <PORTMAP PHYSICAL="M_AXI_DC_BVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_RDATA"/>
- <PORTMAP PHYSICAL="M_AXI_DC_RID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_RLAST"/>
- <PORTMAP PHYSICAL="M_AXI_DC_RREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DC_RRESP"/>
- <PORTMAP PHYSICAL="M_AXI_DC_RVALID"/>
- <PORTMAP PHYSICAL="M_AXI_DC_WDATA"/>
- <PORTMAP PHYSICAL="M_AXI_DC_WLAST"/>
- <PORTMAP PHYSICAL="M_AXI_DC_WREADY"/>
- <PORTMAP PHYSICAL="M_AXI_DC_WSTRB"/>
- <PORTMAP PHYSICAL="M_AXI_DC_WVALID"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_IC" NAME="M_AXI_IC" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M_AXI_IC_ARADDR"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARBURST"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARCACHE"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARLEN"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARLOCK"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARPROT"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARQOS"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARREADY"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARSIZE"/>
- <PORTMAP PHYSICAL="M_AXI_IC_ARVALID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWADDR"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWBURST"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWCACHE"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWLEN"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWLOCK"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWPROT"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWQOS"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWREADY"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWSIZE"/>
- <PORTMAP PHYSICAL="M_AXI_IC_AWVALID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_BID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_BREADY"/>
- <PORTMAP PHYSICAL="M_AXI_IC_BRESP"/>
- <PORTMAP PHYSICAL="M_AXI_IC_BVALID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_RDATA"/>
- <PORTMAP PHYSICAL="M_AXI_IC_RID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_RLAST"/>
- <PORTMAP PHYSICAL="M_AXI_IC_RREADY"/>
- <PORTMAP PHYSICAL="M_AXI_IC_RRESP"/>
- <PORTMAP PHYSICAL="M_AXI_IC_RVALID"/>
- <PORTMAP PHYSICAL="M_AXI_IC_WDATA"/>
- <PORTMAP PHYSICAL="M_AXI_IC_WLAST"/>
- <PORTMAP PHYSICAL="M_AXI_IC_WREADY"/>
- <PORTMAP PHYSICAL="M_AXI_IC_WSTRB"/>
- <PORTMAP PHYSICAL="M_AXI_IC_WVALID"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="mdm_1_MBDEBUG_0" NAME="DEBUG" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP PHYSICAL="Dbg_Capture"/>
- <PORTMAP PHYSICAL="Dbg_Clk"/>
- <PORTMAP PHYSICAL="Dbg_Reg_En"/>
- <PORTMAP PHYSICAL="Debug_Rst"/>
- <PORTMAP PHYSICAL="Dbg_Shift"/>
- <PORTMAP PHYSICAL="Dbg_TDI"/>
- <PORTMAP PHYSICAL="Dbg_TDO"/>
- <PORTMAP PHYSICAL="Dbg_Update"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" NAME="TRACE" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="Trace_Data_Access"/>
- <PORTMAP PHYSICAL="Trace_Data_Address"/>
- <PORTMAP PHYSICAL="Trace_Data_Byte_Enable"/>
- <PORTMAP PHYSICAL="Trace_Data_Read"/>
- <PORTMAP PHYSICAL="Trace_Data_Write"/>
- <PORTMAP PHYSICAL="Trace_Data_Write_Value"/>
- <PORTMAP PHYSICAL="Trace_DCache_Hit"/>
- <PORTMAP PHYSICAL="Trace_DCache_Rdy"/>
- <PORTMAP PHYSICAL="Trace_DCache_Read"/>
- <PORTMAP PHYSICAL="Trace_DCache_Req"/>
- <PORTMAP PHYSICAL="Trace_Delay_Slot"/>
- <PORTMAP PHYSICAL="Trace_EX_PipeRun"/>
- <PORTMAP PHYSICAL="Trace_Exception_Kind"/>
- <PORTMAP PHYSICAL="Trace_Exception_Taken"/>
- <PORTMAP PHYSICAL="Trace_ICache_Hit"/>
- <PORTMAP PHYSICAL="Trace_ICache_Rdy"/>
- <PORTMAP PHYSICAL="Trace_ICache_Req"/>
- <PORTMAP PHYSICAL="Trace_Instruction"/>
- <PORTMAP PHYSICAL="Trace_Jump_Hit"/>
- <PORTMAP PHYSICAL="Trace_Jump_Taken"/>
- <PORTMAP PHYSICAL="Trace_MB_Halted"/>
- <PORTMAP PHYSICAL="Trace_MEM_PipeRun"/>
- <PORTMAP PHYSICAL="Trace_MSR_Reg"/>
- <PORTMAP PHYSICAL="Trace_New_Reg_Value"/>
- <PORTMAP PHYSICAL="Trace_OF_PipeRun"/>
- <PORTMAP PHYSICAL="Trace_PC"/>
- <PORTMAP PHYSICAL="Trace_PID_Reg"/>
- <PORTMAP PHYSICAL="Trace_Reg_Addr"/>
- <PORTMAP PHYSICAL="Trace_Reg_Write"/>
- <PORTMAP PHYSICAL="Trace_Valid_Instr"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- <MEMORYMAP>
- <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="MEMORY"/>
- <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" MEMTYPE="MEMORY"/>
- <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000FFFF" INSTANCE="axi_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
- <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060FFFF" INSTANCE="axi_uartlite_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
- <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40E00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40E0FFFF" INSTANCE="axi_ethernetlite_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
- <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120FFFF" INSTANCE="axi_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
- <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41C00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41C0FFFF" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
- <MEMRANGE ADDRESSBLOCK="memaddr" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xBFFFFFFF" INSTANCE="mig_7series_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="MEMORY"/>
- <MEMRANGE ADDRESSBLOCK="memaddr" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xBFFFFFFF" INSTANCE="mig_7series_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" MEMTYPE="MEMORY"/>
- </MEMORYMAP>
- <PERIPHERALS>
- <PERIPHERAL INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr"/>
- <PERIPHERAL INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr"/>
- <PERIPHERAL INSTANCE="axi_gpio_0"/>
- <PERIPHERAL INSTANCE="axi_uartlite_0"/>
- <PERIPHERAL INSTANCE="axi_ethernetlite_0"/>
- <PERIPHERAL INSTANCE="axi_intc_0"/>
- <PERIPHERAL INSTANCE="axi_timer_0"/>
- <PERIPHERAL INSTANCE="mig_7series_0"/>
- </PERIPHERALS>
- </MODULE>
- <MODULE FULLNAME="/microblaze_0_axi_periph" HWVERSION="2.1" INSTANCE="microblaze_0_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="NUM_SI" VALUE="1"/>
- <PARAMETER NAME="NUM_MI" VALUE="5"/>
- <PARAMETER NAME="STRATEGY" VALUE="0"/>
- <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
- <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
- <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
- <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
- <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
- <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
- <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
- <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
- <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
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- <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
- <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
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- <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
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- <PARAMETER NAME="M46_SECURE" VALUE="0"/>
- <PARAMETER NAME="M47_SECURE" VALUE="0"/>
- <PARAMETER NAME="M48_SECURE" VALUE="0"/>
- <PARAMETER NAME="M49_SECURE" VALUE="0"/>
- <PARAMETER NAME="M50_SECURE" VALUE="0"/>
- <PARAMETER NAME="M51_SECURE" VALUE="0"/>
- <PARAMETER NAME="M52_SECURE" VALUE="0"/>
- <PARAMETER NAME="M53_SECURE" VALUE="0"/>
- <PARAMETER NAME="M54_SECURE" VALUE="0"/>
- <PARAMETER NAME="M55_SECURE" VALUE="0"/>
- <PARAMETER NAME="M56_SECURE" VALUE="0"/>
- <PARAMETER NAME="M57_SECURE" VALUE="0"/>
- <PARAMETER NAME="M58_SECURE" VALUE="0"/>
- <PARAMETER NAME="M59_SECURE" VALUE="0"/>
- <PARAMETER NAME="M60_SECURE" VALUE="0"/>
- <PARAMETER NAME="M61_SECURE" VALUE="0"/>
- <PARAMETER NAME="M62_SECURE" VALUE="0"/>
- <PARAMETER NAME="M63_SECURE" VALUE="0"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_microblaze_0_axi_periph_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="interconnect_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M02_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M03_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M03_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M04_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M04_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARPROT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWPROT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WSTRB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WSTRB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="8" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="8" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="4" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M02_AXI_arready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_arvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="4" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M02_AXI_awready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_awvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_bready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M02_AXI_bvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_rready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M02_AXI_rvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M02_AXI_wready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_wvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="8" NAME="M03_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M03_AXI_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M03_AXI_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="8" NAME="M03_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M03_AXI_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M03_AXI_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M03_AXI_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M03_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M03_AXI_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M03_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M03_AXI_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M03_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M03_AXI_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M03_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M03_AXI_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M03_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M03_AXI_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="12" NAME="M04_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M04_AXI_arready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M04_AXI_arvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="12" NAME="M04_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M04_AXI_awready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M04_AXI_awvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M04_AXI_bready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M04_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M04_AXI_bvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M04_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M04_AXI_rready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M04_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M04_AXI_rvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M04_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M04_AXI_wready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M04_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M04_AXI_wvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wvalid"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" NAME="S00_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="S00_AXI_araddr"/>
- <PORTMAP PHYSICAL="S00_AXI_arprot"/>
- <PORTMAP PHYSICAL="S00_AXI_arready"/>
- <PORTMAP PHYSICAL="S00_AXI_arvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_awaddr"/>
- <PORTMAP PHYSICAL="S00_AXI_awprot"/>
- <PORTMAP PHYSICAL="S00_AXI_awready"/>
- <PORTMAP PHYSICAL="S00_AXI_awvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_bready"/>
- <PORTMAP PHYSICAL="S00_AXI_bresp"/>
- <PORTMAP PHYSICAL="S00_AXI_bvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_rdata"/>
- <PORTMAP PHYSICAL="S00_AXI_rready"/>
- <PORTMAP PHYSICAL="S00_AXI_rresp"/>
- <PORTMAP PHYSICAL="S00_AXI_rvalid"/>
- <PORTMAP PHYSICAL="S00_AXI_wdata"/>
- <PORTMAP PHYSICAL="S00_AXI_wready"/>
- <PORTMAP PHYSICAL="S00_AXI_wstrb"/>
- <PORTMAP PHYSICAL="S00_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M00_AXI" NAME="M00_AXI" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M00_AXI_araddr"/>
- <PORTMAP PHYSICAL="M00_AXI_arready"/>
- <PORTMAP PHYSICAL="M00_AXI_arvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_awaddr"/>
- <PORTMAP PHYSICAL="M00_AXI_awready"/>
- <PORTMAP PHYSICAL="M00_AXI_awvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_bready"/>
- <PORTMAP PHYSICAL="M00_AXI_bresp"/>
- <PORTMAP PHYSICAL="M00_AXI_bvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_rdata"/>
- <PORTMAP PHYSICAL="M00_AXI_rready"/>
- <PORTMAP PHYSICAL="M00_AXI_rresp"/>
- <PORTMAP PHYSICAL="M00_AXI_rvalid"/>
- <PORTMAP PHYSICAL="M00_AXI_wdata"/>
- <PORTMAP PHYSICAL="M00_AXI_wready"/>
- <PORTMAP PHYSICAL="M00_AXI_wstrb"/>
- <PORTMAP PHYSICAL="M00_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M01_AXI" NAME="M01_AXI" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M01_AXI_araddr"/>
- <PORTMAP PHYSICAL="M01_AXI_arready"/>
- <PORTMAP PHYSICAL="M01_AXI_arvalid"/>
- <PORTMAP PHYSICAL="M01_AXI_awaddr"/>
- <PORTMAP PHYSICAL="M01_AXI_awready"/>
- <PORTMAP PHYSICAL="M01_AXI_awvalid"/>
- <PORTMAP PHYSICAL="M01_AXI_bready"/>
- <PORTMAP PHYSICAL="M01_AXI_bresp"/>
- <PORTMAP PHYSICAL="M01_AXI_bvalid"/>
- <PORTMAP PHYSICAL="M01_AXI_rdata"/>
- <PORTMAP PHYSICAL="M01_AXI_rready"/>
- <PORTMAP PHYSICAL="M01_AXI_rresp"/>
- <PORTMAP PHYSICAL="M01_AXI_rvalid"/>
- <PORTMAP PHYSICAL="M01_AXI_wdata"/>
- <PORTMAP PHYSICAL="M01_AXI_wready"/>
- <PORTMAP PHYSICAL="M01_AXI_wstrb"/>
- <PORTMAP PHYSICAL="M01_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M02_AXI" NAME="M02_AXI" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M02_AXI_araddr"/>
- <PORTMAP PHYSICAL="M02_AXI_arready"/>
- <PORTMAP PHYSICAL="M02_AXI_arvalid"/>
- <PORTMAP PHYSICAL="M02_AXI_awaddr"/>
- <PORTMAP PHYSICAL="M02_AXI_awready"/>
- <PORTMAP PHYSICAL="M02_AXI_awvalid"/>
- <PORTMAP PHYSICAL="M02_AXI_bready"/>
- <PORTMAP PHYSICAL="M02_AXI_bresp"/>
- <PORTMAP PHYSICAL="M02_AXI_bvalid"/>
- <PORTMAP PHYSICAL="M02_AXI_rdata"/>
- <PORTMAP PHYSICAL="M02_AXI_rready"/>
- <PORTMAP PHYSICAL="M02_AXI_rresp"/>
- <PORTMAP PHYSICAL="M02_AXI_rvalid"/>
- <PORTMAP PHYSICAL="M02_AXI_wdata"/>
- <PORTMAP PHYSICAL="M02_AXI_wready"/>
- <PORTMAP PHYSICAL="M02_AXI_wstrb"/>
- <PORTMAP PHYSICAL="M02_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M03_AXI" NAME="M03_AXI" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M03_AXI_araddr"/>
- <PORTMAP PHYSICAL="M03_AXI_arready"/>
- <PORTMAP PHYSICAL="M03_AXI_arvalid"/>
- <PORTMAP PHYSICAL="M03_AXI_awaddr"/>
- <PORTMAP PHYSICAL="M03_AXI_awready"/>
- <PORTMAP PHYSICAL="M03_AXI_awvalid"/>
- <PORTMAP PHYSICAL="M03_AXI_bready"/>
- <PORTMAP PHYSICAL="M03_AXI_bresp"/>
- <PORTMAP PHYSICAL="M03_AXI_bvalid"/>
- <PORTMAP PHYSICAL="M03_AXI_rdata"/>
- <PORTMAP PHYSICAL="M03_AXI_rready"/>
- <PORTMAP PHYSICAL="M03_AXI_rresp"/>
- <PORTMAP PHYSICAL="M03_AXI_rvalid"/>
- <PORTMAP PHYSICAL="M03_AXI_wdata"/>
- <PORTMAP PHYSICAL="M03_AXI_wready"/>
- <PORTMAP PHYSICAL="M03_AXI_wstrb"/>
- <PORTMAP PHYSICAL="M03_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M04_AXI" NAME="M04_AXI" TYPE="MASTER">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M04_AXI_araddr"/>
- <PORTMAP PHYSICAL="M04_AXI_arready"/>
- <PORTMAP PHYSICAL="M04_AXI_arvalid"/>
- <PORTMAP PHYSICAL="M04_AXI_awaddr"/>
- <PORTMAP PHYSICAL="M04_AXI_awready"/>
- <PORTMAP PHYSICAL="M04_AXI_awvalid"/>
- <PORTMAP PHYSICAL="M04_AXI_bready"/>
- <PORTMAP PHYSICAL="M04_AXI_bresp"/>
- <PORTMAP PHYSICAL="M04_AXI_bvalid"/>
- <PORTMAP PHYSICAL="M04_AXI_rdata"/>
- <PORTMAP PHYSICAL="M04_AXI_rready"/>
- <PORTMAP PHYSICAL="M04_AXI_rresp"/>
- <PORTMAP PHYSICAL="M04_AXI_rvalid"/>
- <PORTMAP PHYSICAL="M04_AXI_wdata"/>
- <PORTMAP PHYSICAL="M04_AXI_wready"/>
- <PORTMAP PHYSICAL="M04_AXI_wstrb"/>
- <PORTMAP PHYSICAL="M04_AXI_wvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/microblaze_0_local_memory/dlmb_bram_if_cntlr" HWVERSION="4.0" INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
- <PARAMETER NAME="C_MASK" VALUE="0xc0000000"/>
- <PARAMETER NAME="C_MASK1" VALUE="0x00800000"/>
- <PARAMETER NAME="C_MASK2" VALUE="0x00800000"/>
- <PARAMETER NAME="C_MASK3" VALUE="0x00800000"/>
- <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_ECC" VALUE="0"/>
- <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
- <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
- <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
- <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
- <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
- <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
- <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
- <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
- <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
- <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
- <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_dlmb_bram_if_cntlr_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0x0003FFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ABus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ABus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteDBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_WriteDBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_AddrStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_AddrStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ReadStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ReadStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_WriteStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_BE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_BE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_DBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_DBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Ready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_Ready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Wait">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_Wait"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_UE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_UE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_CE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_CE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Rst_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="rsta"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Clk_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="clka"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Addr_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="addra"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_EN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="ena"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_WEN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="wea"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Dout_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="dina"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Din_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="douta"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_v10_LMB_Sl_0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="LMB_ABus"/>
- <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP PHYSICAL="LMB_BE"/>
- <PORTMAP PHYSICAL="Sl_CE"/>
- <PORTMAP PHYSICAL="Sl_DBus"/>
- <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP PHYSICAL="Sl_Ready"/>
- <PORTMAP PHYSICAL="Sl_UE"/>
- <PORTMAP PHYSICAL="Sl_Wait"/>
- <PORTMAP PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP PHYSICAL="BRAM_Dout_A"/>
- <PORTMAP PHYSICAL="BRAM_Din_A"/>
- <PORTMAP PHYSICAL="BRAM_EN_A"/>
- <PORTMAP PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP PHYSICAL="BRAM_WEN_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/microblaze_0_local_memory/dlmb_v10" HWVERSION="3.0" INSTANCE="microblaze_0_local_memory_dlmb_v10" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
- <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_dlmb_v10_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="SYS_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_Rst" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Addr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Data_Addr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_Read_Strobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Read_Strobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_Write_Strobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Write_Strobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_D_AS">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="D_AS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Write">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Data_Write"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_Byte_Enable">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Byte_Enable"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_DBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_DBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Ready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_Ready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Wait">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_Wait"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_UE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_UE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_CE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_CE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ABus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_ABus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ReadStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_ReadStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_WriteStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_AddrStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_AddrStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Read">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Data_Read"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteDBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_WriteDBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="microblaze_0_DReady">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="DReady"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="microblaze_0_DWait">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="DWait"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="microblaze_0_DUE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="DUE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="microblaze_0_DCE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="DCE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_BE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_BE"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_v10_LMB_Sl_0" NAME="LMB_Sl_0" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="LMB_ABus"/>
- <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP PHYSICAL="LMB_BE"/>
- <PORTMAP PHYSICAL="Sl_CE"/>
- <PORTMAP PHYSICAL="Sl_DBus"/>
- <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP PHYSICAL="Sl_Ready"/>
- <PORTMAP PHYSICAL="LMB_Rst"/>
- <PORTMAP PHYSICAL="Sl_UE"/>
- <PORTMAP PHYSICAL="Sl_Wait"/>
- <PORTMAP PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_DLMB" NAME="LMB_M" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M_ABus"/>
- <PORTMAP PHYSICAL="M_AddrStrobe"/>
- <PORTMAP PHYSICAL="M_BE"/>
- <PORTMAP PHYSICAL="LMB_CE"/>
- <PORTMAP PHYSICAL="LMB_ReadDBus"/>
- <PORTMAP PHYSICAL="M_ReadStrobe"/>
- <PORTMAP PHYSICAL="LMB_Ready"/>
- <PORTMAP PHYSICAL="LMB_Rst"/>
- <PORTMAP PHYSICAL="LMB_UE"/>
- <PORTMAP PHYSICAL="LMB_Wait"/>
- <PORTMAP PHYSICAL="M_DBus"/>
- <PORTMAP PHYSICAL="M_WriteStrobe"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/microblaze_0_local_memory/ilmb_bram_if_cntlr" HWVERSION="4.0" INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
- <PARAMETER NAME="C_MASK" VALUE="0x80000000"/>
- <PARAMETER NAME="C_MASK1" VALUE="0x00800000"/>
- <PARAMETER NAME="C_MASK2" VALUE="0x00800000"/>
- <PARAMETER NAME="C_MASK3" VALUE="0x00800000"/>
- <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_ECC" VALUE="0"/>
- <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
- <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
- <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
- <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
- <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
- <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
- <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
- <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
- <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
- <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
- <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_ilmb_bram_if_cntlr_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0x0003FFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ABus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ABus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteDBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_WriteDBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_AddrStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_AddrStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ReadStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ReadStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_WriteStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_BE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_BE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_DBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_DBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Ready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_Ready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Wait">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_Wait"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_UE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_UE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_CE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_CE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Rst_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="rstb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Clk_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="clkb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Addr_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="addrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_EN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="enb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_WEN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="web"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Dout_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="dinb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Din_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="doutb"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_v10_LMB_Sl_0" NAME="SLMB" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="LMB_ABus"/>
- <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP PHYSICAL="LMB_BE"/>
- <PORTMAP PHYSICAL="Sl_CE"/>
- <PORTMAP PHYSICAL="Sl_DBus"/>
- <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP PHYSICAL="Sl_Ready"/>
- <PORTMAP PHYSICAL="Sl_UE"/>
- <PORTMAP PHYSICAL="Sl_Wait"/>
- <PORTMAP PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="BRAM_Addr_A"/>
- <PORTMAP PHYSICAL="BRAM_Clk_A"/>
- <PORTMAP PHYSICAL="BRAM_Dout_A"/>
- <PORTMAP PHYSICAL="BRAM_Din_A"/>
- <PORTMAP PHYSICAL="BRAM_EN_A"/>
- <PORTMAP PHYSICAL="BRAM_Rst_A"/>
- <PORTMAP PHYSICAL="BRAM_WEN_A"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/microblaze_0_local_memory/ilmb_v10" HWVERSION="3.0" INSTANCE="microblaze_0_local_memory_ilmb_v10" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
- <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
- <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_ilmb_v10_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="SYS_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_Rst" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr_Addr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Instr_Addr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_IFetch">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="IFetch"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M_WriteStrobe" SIGIS="undef"/>
- <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_I_AS">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="I_AS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M_DBus" RIGHT="31" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M_BE" RIGHT="3" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_DBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_DBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Ready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_Ready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Wait">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_Wait"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_UE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_UE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_CE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_CE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ABus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_ABus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ReadStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_ReadStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_WriteStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_AddrStrobe">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_AddrStrobe"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Instr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteDBus">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_WriteDBus"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="microblaze_0_IReady">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="IReady"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="microblaze_0_IWAIT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="IWAIT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="microblaze_0_IUE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="IUE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="microblaze_0_ICE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="ICE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_BE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_BE"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_v10_LMB_Sl_0" NAME="LMB_Sl_0" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="LMB_ABus"/>
- <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
- <PORTMAP PHYSICAL="LMB_BE"/>
- <PORTMAP PHYSICAL="Sl_CE"/>
- <PORTMAP PHYSICAL="Sl_DBus"/>
- <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
- <PORTMAP PHYSICAL="Sl_Ready"/>
- <PORTMAP PHYSICAL="LMB_Rst"/>
- <PORTMAP PHYSICAL="Sl_UE"/>
- <PORTMAP PHYSICAL="Sl_Wait"/>
- <PORTMAP PHYSICAL="LMB_WriteDBus"/>
- <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_ILMB" NAME="LMB_M" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="M_ABus"/>
- <PORTMAP PHYSICAL="M_AddrStrobe"/>
- <PORTMAP PHYSICAL="M_BE"/>
- <PORTMAP PHYSICAL="LMB_CE"/>
- <PORTMAP PHYSICAL="LMB_ReadDBus"/>
- <PORTMAP PHYSICAL="M_ReadStrobe"/>
- <PORTMAP PHYSICAL="LMB_Ready"/>
- <PORTMAP PHYSICAL="LMB_Rst"/>
- <PORTMAP PHYSICAL="LMB_UE"/>
- <PORTMAP PHYSICAL="LMB_Wait"/>
- <PORTMAP PHYSICAL="M_DBus"/>
- <PORTMAP PHYSICAL="M_WriteStrobe"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/microblaze_0_local_memory/lmb_bram" HWVERSION="8.2" INSTANCE="microblaze_0_local_memory_lmb_bram" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY" MODTYPE="blk_mem_gen" VLNV="xilinx.com:ip:blk_mem_gen:8.2">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=blk_mem_gen;v=v8_2;d=pg058-blk-mem-gen.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_ELABORATION_DIR" VALUE="./"/>
- <PARAMETER NAME="C_INTERFACE_TYPE" VALUE="0"/>
- <PARAMETER NAME="C_AXI_TYPE" VALUE="1"/>
- <PARAMETER NAME="C_AXI_SLAVE_TYPE" VALUE="0"/>
- <PARAMETER NAME="C_USE_BRAM_BLOCK" VALUE="1"/>
- <PARAMETER NAME="C_ENABLE_32BIT_ADDRESS" VALUE="1"/>
- <PARAMETER NAME="C_CTRL_ECC_ALGO" VALUE="NONE"/>
- <PARAMETER NAME="C_HAS_AXI_ID" VALUE="0"/>
- <PARAMETER NAME="C_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C_MEM_TYPE" VALUE="2"/>
- <PARAMETER NAME="C_BYTE_SIZE" VALUE="8"/>
- <PARAMETER NAME="C_ALGORITHM" VALUE="1"/>
- <PARAMETER NAME="C_PRIM_TYPE" VALUE="1"/>
- <PARAMETER NAME="C_LOAD_INIT_FILE" VALUE="0"/>
- <PARAMETER NAME="C_INIT_FILE_NAME" VALUE="no_coe_file_loaded"/>
- <PARAMETER NAME="C_INIT_FILE" VALUE="base_microblaze_design_lmb_bram_0.mem"/>
- <PARAMETER NAME="C_USE_DEFAULT_DATA" VALUE="0"/>
- <PARAMETER NAME="C_DEFAULT_DATA" VALUE="0"/>
- <PARAMETER NAME="C_HAS_RSTA" VALUE="1"/>
- <PARAMETER NAME="C_RST_PRIORITY_A" VALUE="CE"/>
- <PARAMETER NAME="C_RSTRAM_A" VALUE="0"/>
- <PARAMETER NAME="C_INITA_VAL" VALUE="0"/>
- <PARAMETER NAME="C_HAS_ENA" VALUE="1"/>
- <PARAMETER NAME="C_HAS_REGCEA" VALUE="0"/>
- <PARAMETER NAME="C_USE_BYTE_WEA" VALUE="1"/>
- <PARAMETER NAME="C_WEA_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C_WRITE_MODE_A" VALUE="WRITE_FIRST"/>
- <PARAMETER NAME="C_WRITE_WIDTH_A" VALUE="32"/>
- <PARAMETER NAME="C_READ_WIDTH_A" VALUE="32"/>
- <PARAMETER NAME="C_WRITE_DEPTH_A" VALUE="65536"/>
- <PARAMETER NAME="C_READ_DEPTH_A" VALUE="65536"/>
- <PARAMETER NAME="C_ADDRA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_HAS_RSTB" VALUE="1"/>
- <PARAMETER NAME="C_RST_PRIORITY_B" VALUE="CE"/>
- <PARAMETER NAME="C_RSTRAM_B" VALUE="0"/>
- <PARAMETER NAME="C_INITB_VAL" VALUE="0"/>
- <PARAMETER NAME="C_HAS_ENB" VALUE="1"/>
- <PARAMETER NAME="C_HAS_REGCEB" VALUE="0"/>
- <PARAMETER NAME="C_USE_BYTE_WEB" VALUE="1"/>
- <PARAMETER NAME="C_WEB_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C_WRITE_MODE_B" VALUE="WRITE_FIRST"/>
- <PARAMETER NAME="C_WRITE_WIDTH_B" VALUE="32"/>
- <PARAMETER NAME="C_READ_WIDTH_B" VALUE="32"/>
- <PARAMETER NAME="C_WRITE_DEPTH_B" VALUE="65536"/>
- <PARAMETER NAME="C_READ_DEPTH_B" VALUE="65536"/>
- <PARAMETER NAME="C_ADDRB_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_A" VALUE="0"/>
- <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_B" VALUE="0"/>
- <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_A" VALUE="0"/>
- <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_B" VALUE="0"/>
- <PARAMETER NAME="C_MUX_PIPELINE_STAGES" VALUE="0"/>
- <PARAMETER NAME="C_HAS_SOFTECC_INPUT_REGS_A" VALUE="0"/>
- <PARAMETER NAME="C_HAS_SOFTECC_OUTPUT_REGS_B" VALUE="0"/>
- <PARAMETER NAME="C_USE_SOFTECC" VALUE="0"/>
- <PARAMETER NAME="C_USE_ECC" VALUE="0"/>
- <PARAMETER NAME="C_EN_ECC_PIPE" VALUE="0"/>
- <PARAMETER NAME="C_HAS_INJECTERR" VALUE="0"/>
- <PARAMETER NAME="C_SIM_COLLISION_CHECK" VALUE="ALL"/>
- <PARAMETER NAME="C_COMMON_CLK" VALUE="0"/>
- <PARAMETER NAME="C_DISABLE_WARN_BHV_COLL" VALUE="0"/>
- <PARAMETER NAME="C_EN_SLEEP_PIN" VALUE="0"/>
- <PARAMETER NAME="C_DISABLE_WARN_BHV_RANGE" VALUE="0"/>
- <PARAMETER NAME="C_COUNT_36K_BRAM" VALUE="64"/>
- <PARAMETER NAME="C_COUNT_18K_BRAM" VALUE="0"/>
- <PARAMETER NAME="C_EST_POWER_SUMMARY" VALUE="Estimated Power for IP : 20.388004 mW"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_lmb_bram_0"/>
- <PARAMETER NAME="Interface_Type" VALUE="Native"/>
- <PARAMETER NAME="AXI_Type" VALUE="AXI4_Full"/>
- <PARAMETER NAME="AXI_Slave_Type" VALUE="Memory_Slave"/>
- <PARAMETER NAME="Use_AXI_ID" VALUE="false"/>
- <PARAMETER NAME="AXI_ID_Width" VALUE="4"/>
- <PARAMETER NAME="Memory_Type" VALUE="True_Dual_Port_RAM"/>
- <PARAMETER NAME="Enable_32bit_Address" VALUE="true"/>
- <PARAMETER NAME="ecctype" VALUE="No_ECC"/>
- <PARAMETER NAME="ECC" VALUE="false"/>
- <PARAMETER NAME="softecc" VALUE="false"/>
- <PARAMETER NAME="EN_SLEEP_PIN" VALUE="false"/>
- <PARAMETER NAME="EN_ECC_PIPE" VALUE="false"/>
- <PARAMETER NAME="Use_Error_Injection_Pins" VALUE="false"/>
- <PARAMETER NAME="Error_Injection_Type" VALUE="Single_Bit_Error_Injection"/>
- <PARAMETER NAME="Use_Byte_Write_Enable" VALUE="true"/>
- <PARAMETER NAME="Byte_Size" VALUE="8"/>
- <PARAMETER NAME="Algorithm" VALUE="Minimum_Area"/>
- <PARAMETER NAME="Primitive" VALUE="8kx2"/>
- <PARAMETER NAME="Assume_Synchronous_Clk" VALUE="false"/>
- <PARAMETER NAME="Write_Width_A" VALUE="32"/>
- <PARAMETER NAME="Write_Depth_A" VALUE="65536"/>
- <PARAMETER NAME="Read_Width_A" VALUE="32"/>
- <PARAMETER NAME="Operating_Mode_A" VALUE="WRITE_FIRST"/>
- <PARAMETER NAME="Enable_A" VALUE="Use_ENA_Pin"/>
- <PARAMETER NAME="Write_Width_B" VALUE="32"/>
- <PARAMETER NAME="Read_Width_B" VALUE="32"/>
- <PARAMETER NAME="Operating_Mode_B" VALUE="WRITE_FIRST"/>
- <PARAMETER NAME="Enable_B" VALUE="Use_ENB_Pin"/>
- <PARAMETER NAME="Register_PortA_Output_of_Memory_Primitives" VALUE="false"/>
- <PARAMETER NAME="Register_PortA_Output_of_Memory_Core" VALUE="false"/>
- <PARAMETER NAME="Use_REGCEA_Pin" VALUE="false"/>
- <PARAMETER NAME="Register_PortB_Output_of_Memory_Primitives" VALUE="false"/>
- <PARAMETER NAME="Register_PortB_Output_of_Memory_Core" VALUE="false"/>
- <PARAMETER NAME="Use_REGCEB_Pin" VALUE="false"/>
- <PARAMETER NAME="register_porta_input_of_softecc" VALUE="false"/>
- <PARAMETER NAME="register_portb_output_of_softecc" VALUE="false"/>
- <PARAMETER NAME="Pipeline_Stages" VALUE="0"/>
- <PARAMETER NAME="Load_Init_File" VALUE="false"/>
- <PARAMETER NAME="Coe_File" VALUE="no_coe_file_loaded"/>
- <PARAMETER NAME="Fill_Remaining_Memory_Locations" VALUE="false"/>
- <PARAMETER NAME="Remaining_Memory_Locations" VALUE="0"/>
- <PARAMETER NAME="Use_RSTA_Pin" VALUE="true"/>
- <PARAMETER NAME="Reset_Memory_Latch_A" VALUE="false"/>
- <PARAMETER NAME="Reset_Priority_A" VALUE="CE"/>
- <PARAMETER NAME="Output_Reset_Value_A" VALUE="0"/>
- <PARAMETER NAME="Use_RSTB_Pin" VALUE="true"/>
- <PARAMETER NAME="Reset_Memory_Latch_B" VALUE="false"/>
- <PARAMETER NAME="Reset_Priority_B" VALUE="CE"/>
- <PARAMETER NAME="Output_Reset_Value_B" VALUE="0"/>
- <PARAMETER NAME="Reset_Type" VALUE="SYNC"/>
- <PARAMETER NAME="Additional_Inputs_for_Power_Estimation" VALUE="false"/>
- <PARAMETER NAME="Port_A_Clock" VALUE="100"/>
- <PARAMETER NAME="Port_A_Write_Rate" VALUE="50"/>
- <PARAMETER NAME="Port_B_Clock" VALUE="100"/>
- <PARAMETER NAME="Port_B_Write_Rate" VALUE="50"/>
- <PARAMETER NAME="Port_A_Enable_Rate" VALUE="100"/>
- <PARAMETER NAME="Port_B_Enable_Rate" VALUE="100"/>
- <PARAMETER NAME="Collision_Warnings" VALUE="ALL"/>
- <PARAMETER NAME="Disable_Collision_Warnings" VALUE="false"/>
- <PARAMETER NAME="Disable_Out_of_Range_Warnings" VALUE="false"/>
- <PARAMETER NAME="use_bram_block" VALUE="BRAM_Controller"/>
- <PARAMETER NAME="MEM_FILE" VALUE="base_microblaze_design_lmb_bram_0.mem"/>
- <PARAMETER NAME="CTRL_ECC_ALGO" VALUE="NONE"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" NAME="clka" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Clk_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Clk_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="rsta" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Rst_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Rst_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="ena" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_EN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_EN_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="wea" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_WEN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_WEN_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="addra" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Addr_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Addr_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="dina" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Dout_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Dout_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="douta" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Din_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Din_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="clkb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Clk_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Clk_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="rstb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Rst_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Rst_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="enb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_EN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_EN_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="web" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_WEN_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_WEN_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="addrb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Addr_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Addr_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="dinb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Dout_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Dout_A"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="doutb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Din_A">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Din_A"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORTA" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP PHYSICAL="addra"/>
- <PORTMAP PHYSICAL="clka"/>
- <PORTMAP PHYSICAL="dina"/>
- <PORTMAP PHYSICAL="douta"/>
- <PORTMAP PHYSICAL="ena"/>
- <PORTMAP PHYSICAL="rsta"/>
- <PORTMAP PHYSICAL="wea"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORTB" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP PHYSICAL="addrb"/>
- <PORTMAP PHYSICAL="clkb"/>
- <PORTMAP PHYSICAL="dinb"/>
- <PORTMAP PHYSICAL="doutb"/>
- <PORTMAP PHYSICAL="enb"/>
- <PORTMAP PHYSICAL="rstb"/>
- <PORTMAP PHYSICAL="web"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/mig_7series_0" HWVERSION="2.3" INSTANCE="mig_7series_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="mig_7series" VLNV="xilinx.com:ip:mig_7series:2.3">
- <DOCUMENTS/>
- <PARAMETERS>
- <PARAMETER NAME="NoOfControllers" VALUE="1"/>
- <PARAMETER NAME="COMBINED_INTERFACE" VALUE="0"/>
- <PARAMETER NAME="REFCLK_TYPE" VALUE="NONE"/>
- <PARAMETER NAME="MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="TEMP_MON_CONTROL" VALUE="INTERNAL"/>
- <PARAMETER NAME="POLARITY" VALUE="ACTIVE_HIGH"/>
- <PARAMETER NAME="IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="USE_AXI" VALUE="1"/>
- <PARAMETER NAME="ECC" VALUE="OFF"/>
- <PARAMETER NAME="DDR3_DQ_WIDTH" VALUE="64"/>
- <PARAMETER NAME="DDR3_DQS_WIDTH" VALUE="8"/>
- <PARAMETER NAME="DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="DDR3_DM_WIDTH" VALUE="8"/>
- <PARAMETER NAME="DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="DDR3_DQS_CNT_WIDTH" VALUE="3"/>
- <PARAMETER NAME="DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="DDR3_ADDR_WIDTH" VALUE="28"/>
- <PARAMETER NAME="DDR3_nCK_PER_CLK" VALUE="4"/>
- <PARAMETER NAME="DDR3_DATA_WIDTH" VALUE="64"/>
- <PARAMETER NAME="DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
- <PARAMETER NAME="PHASE" VALUE="0.000"/>
- <PARAMETER NAME="UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="MMCM_VCO" VALUE="800"/>
- <PARAMETER NAME="MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C_S_AXI_ID_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C_S_AXI_MEM_SIZE" VALUE="1073741824"/>
- <PARAMETER NAME="QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C0_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C0_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C0_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C0_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C0_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C0_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C0_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C0_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C0_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C0_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C0_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C0_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C0_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C0_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C0_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C0_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C0_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C0_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C0_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C0_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C0_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C0_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C0_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C0_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C0_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C0_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C0_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C0_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C0_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C0_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C0_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C0_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C0_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C0_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C0_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C0_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C0_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C0_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C0_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C0_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C0_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C0_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C0_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C0_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C0_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C0_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C0_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C0_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C0_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C0_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C0_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C0_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C0_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C0_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C0_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C0_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C0_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C0_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C0_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C0_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C0_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="C1_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C1_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C1_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C1_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C1_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C1_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C1_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C1_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C1_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C1_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C1_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C1_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C1_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C1_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C1_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C1_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C1_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C1_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C1_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C1_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C1_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C1_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C1_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C1_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C1_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C1_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C1_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C1_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C1_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C1_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C1_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C1_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C1_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C1_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C1_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C1_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C1_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C1_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C1_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C1_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C1_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C1_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C1_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C1_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C1_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C1_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C1_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C1_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C1_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C1_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C1_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C1_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C1_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C1_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C1_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C1_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C1_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C1_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C1_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C1_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C1_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="C2_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C2_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C2_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C2_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C2_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C2_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C2_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C2_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C2_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C2_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C2_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C2_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C2_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C2_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C2_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C2_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C2_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C2_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C2_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C2_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C2_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C2_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C2_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C2_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C2_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C2_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C2_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C2_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C2_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C2_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C2_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C2_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C2_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C2_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C2_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C2_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C2_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C2_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C2_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C2_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C2_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C2_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C2_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C2_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C2_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C2_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C2_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C2_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C2_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C2_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C2_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C2_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C2_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C2_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C2_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C2_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C2_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C2_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C2_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C2_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="C3_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C3_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C3_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C3_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C3_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C3_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C3_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C3_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C3_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C3_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C3_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C3_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C3_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C3_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C3_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C3_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C3_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C3_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C3_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C3_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C3_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C3_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C3_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C3_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C3_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C3_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C3_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C3_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C3_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C3_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C3_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C3_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C3_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C3_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C3_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C3_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C3_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C3_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C3_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C3_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C3_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C3_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C3_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C3_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C3_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C3_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C3_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C3_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C3_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C3_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C3_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C3_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C3_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C3_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C3_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C3_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C3_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C3_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C3_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C3_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="C4_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C4_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C4_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C4_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C4_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C4_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C4_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C4_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C4_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C4_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C4_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C4_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C4_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C4_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C4_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C4_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C4_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C4_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C4_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C4_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C4_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C4_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C4_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C4_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C4_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C4_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C4_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C4_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C4_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C4_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C4_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C4_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C4_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C4_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C4_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C4_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C4_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C4_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C4_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C4_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C4_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C4_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C4_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C4_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C4_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C4_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C4_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C4_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C4_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C4_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C4_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C4_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C4_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C4_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C4_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C4_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C4_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C4_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C4_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C4_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C4_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="C5_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C5_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C5_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C5_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C5_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C5_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C5_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C5_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C5_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C5_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C5_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C5_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C5_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C5_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C5_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C5_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C5_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C5_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C5_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C5_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C5_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C5_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C5_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C5_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C5_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C5_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C5_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C5_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C5_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C5_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C5_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C5_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C5_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C5_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C5_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C5_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C5_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C5_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C5_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C5_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C5_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C5_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C5_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C5_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C5_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C5_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C5_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C5_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C5_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C5_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C5_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C5_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C5_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C5_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C5_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C5_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C5_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C5_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C5_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C5_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C5_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="C6_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C6_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C6_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C6_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C6_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C6_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C6_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C6_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C6_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C6_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C6_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C6_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C6_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C6_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C6_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C6_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C6_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C6_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C6_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C6_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C6_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C6_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C6_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C6_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C6_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C6_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C6_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C6_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C6_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C6_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C6_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C6_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C6_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C6_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C6_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C6_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C6_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C6_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C6_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C6_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C6_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C6_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C6_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C6_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C6_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C6_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C6_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C6_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C6_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C6_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C6_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C6_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C6_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C6_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C6_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C6_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C6_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C6_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C6_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C6_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C6_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="C7_MEM_TYPE" VALUE="DDR3"/>
- <PARAMETER NAME="C7_IS_CLK_SHARED" VALUE="FALSE"/>
- <PARAMETER NAME="C7_SYSCLK_TYPE" VALUE="DIFF"/>
- <PARAMETER NAME="C7_USE_AXI" VALUE="0"/>
- <PARAMETER NAME="C7_ECC" VALUE="OFF"/>
- <PARAMETER NAME="C7_DDR3_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_DDR3_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C7_DDR3_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C7_DDR3_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C7_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR3_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C7_DDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_DDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C7_DDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C7_DDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_ODT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C7_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C7_LPDDR2_DQ_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_LPDDR2_DQS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_ROW_WIDTH" VALUE="14"/>
- <PARAMETER NAME="C7_LPDDR2_BANK_WIDTH" VALUE="3"/>
- <PARAMETER NAME="C7_LPDDR2_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_CKE_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_CS_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_nCS_PER_RANK" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_USE_CS_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_USE_DM_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_USE_ODT_PORT" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_REG_CTRL" VALUE="OFF"/>
- <PARAMETER NAME="C7_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C7_DQS_CNT_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C7_DDRX_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_DDRX_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C7_DDRX_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_DDR3_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_DDR3_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C7_DDR3_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_DDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_DDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C7_DDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_LPDDR2_ADDR_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_LPDDR2_nCK_PER_CLK" VALUE="2"/>
- <PARAMETER NAME="C7_LPDDR2_DATA_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_FREQ_HZ" VALUE="100.0"/>
- <PARAMETER NAME="C7_PHASE" VALUE="0.000"/>
- <PARAMETER NAME="C7_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
- <PARAMETER NAME="C7_MMCM_VCO" VALUE="1200.0"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT1_FREQ" VALUE="10"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT2_FREQ" VALUE="10"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT3_FREQ" VALUE="10"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT4_FREQ" VALUE="10"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C7_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
- <PARAMETER NAME="C7_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C7_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C7_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C7_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C7_C_S_AXI_ID_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C7_C_S_AXI_DATA_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C7_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
- <PARAMETER NAME="C7_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
- <PARAMETER NAME="C7_QDRIIP_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C7_QDRIIP_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C7_QDRIIP_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C7_QDRIIP_BW_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C7_QDRIIP_BURST_LEN" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C7_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C7_RLDII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_RLDII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C7_RLDII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C7_RLDIII_NUM_DEVICES" VALUE="1"/>
- <PARAMETER NAME="C7_RLDIII_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C7_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C7_RLDIII_QK_WIDTH" VALUE="8"/>
- <PARAMETER NAME="C7_RLDIII_CK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDIII_DK_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDIII_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDIII_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C7_RLDIII_QVLD_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDIII_DEBUG_PORT" VALUE="OFF"/>
- <PARAMETER NAME="C7_RLDX_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C7_RLDX_DATA_WIDTH" VALUE="18"/>
- <PARAMETER NAME="C7_RLDX_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C7_RLDX_BANK_WIDTH" VALUE="2"/>
- <PARAMETER NAME="C7_RLDX_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C7_RLDX_DM_WIDTH" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C7_RLDII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C7_RLDII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C7_RLDIII_CMD_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C7_RLDIII_ADDR_WIDTH" VALUE="29"/>
- <PARAMETER NAME="C7_RLDIII_nCK_PER_CLK" VALUE="1"/>
- <PARAMETER NAME="C7_POLARITY" VALUE="ACTIVE_LOW"/>
- <PARAMETER NAME="XML_INPUT_FILE" VALUE="board.prj"/>
- <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="reset"/>
- <PARAMETER NAME="MIG_DONT_TOUCH_PARAM" VALUE="Custom"/>
- <PARAMETER NAME="BOARD_MIG_PARAM" VALUE="ddr3_sdram"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_mig_7series_0_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- <PARAMETER NAME="EDK_SPECIAL" VALUE="MEMORY_CTRL"/>
- <PARAMETER NAME="C_BASEADDR" VALUE="0x80000000"/>
- <PARAMETER NAME="C_HIGHADDR" VALUE="0xBFFFFFFF"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" NAME="sys_rst" SIGIS="rst" SIGNAME="External_Ports_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="External_Ports" PORT="reset"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" LEFT="63" NAME="ddr3_dq" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="IO" LEFT="7" NAME="ddr3_dqs_p" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="IO" LEFT="7" NAME="ddr3_dqs_n" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="13" NAME="ddr3_addr" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="2" NAME="ddr3_ba" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_ras_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_cas_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_we_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="ddr3_reset_n" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_ck_p" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_ck_n" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_cke" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_cs_n" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="7" NAME="ddr3_dm" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="ddr3_odt" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="ui_clk_sync_rst" SIGIS="rst" SIGNAME="mig_7series_0_ui_clk_sync_rst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="ext_reset_in"/>
- </CONNECTIONS>
- </PORT>
- <PORT CLKFREQUENCY="100000000" DIR="O" NAME="ui_clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Clk"/>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Clk"/>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_Clk"/>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Clk"/>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_Clk"/>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="slowest_sync_clk"/>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aclk"/>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aclk"/>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aclk"/>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_aclk"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_ACLK"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="ACLK"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_ACLK"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_ACLK"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_ACLK"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_ACLK"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_ACLK"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ACLK"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="ACLK"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ACLK"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ACLK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="s_axi_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="s_axi_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="s_axi_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="s_axi_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_awlock" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wstrb"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="s_axi_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="s_axi_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="s_axi_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="s_axi_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="s_axi_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_arlock" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlock"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axi_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arqos"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="s_axi_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="mmcm_locked" SIGIS="undef" SIGNAME="mig_7series_0_mmcm_locked">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="dcm_locked"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="sys_clk_p" SIGIS="undef"/>
- <PORT DIR="I" NAME="sys_clk_n" SIGIS="undef"/>
- <PORT DIR="O" NAME="init_calib_complete" SIGIS="undef"/>
- <PORT DIR="I" NAME="aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="mig_7series_0_DDR3" NAME="DDR3" TYPE="INITIATOR">
- <PORTMAPS>
- <PORTMAP PHYSICAL="ddr3_dq"/>
- <PORTMAP PHYSICAL="ddr3_dqs_p"/>
- <PORTMAP PHYSICAL="ddr3_dqs_n"/>
- <PORTMAP PHYSICAL="ddr3_addr"/>
- <PORTMAP PHYSICAL="ddr3_ba"/>
- <PORTMAP PHYSICAL="ddr3_ras_n"/>
- <PORTMAP PHYSICAL="ddr3_cas_n"/>
- <PORTMAP PHYSICAL="ddr3_we_n"/>
- <PORTMAP PHYSICAL="ddr3_reset_n"/>
- <PORTMAP PHYSICAL="ddr3_ck_p"/>
- <PORTMAP PHYSICAL="ddr3_ck_n"/>
- <PORTMAP PHYSICAL="ddr3_cke"/>
- <PORTMAP PHYSICAL="ddr3_cs_n"/>
- <PORTMAP PHYSICAL="ddr3_dm"/>
- <PORTMAP PHYSICAL="ddr3_odt"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" NAME="S_AXI" TYPE="SLAVE">
- <PORTMAPS>
- <PORTMAP PHYSICAL="s_axi_awid"/>
- <PORTMAP PHYSICAL="s_axi_awaddr"/>
- <PORTMAP PHYSICAL="s_axi_awlen"/>
- <PORTMAP PHYSICAL="s_axi_awsize"/>
- <PORTMAP PHYSICAL="s_axi_awburst"/>
- <PORTMAP PHYSICAL="s_axi_awlock"/>
- <PORTMAP PHYSICAL="s_axi_awcache"/>
- <PORTMAP PHYSICAL="s_axi_awprot"/>
- <PORTMAP PHYSICAL="s_axi_awqos"/>
- <PORTMAP PHYSICAL="s_axi_awvalid"/>
- <PORTMAP PHYSICAL="s_axi_awready"/>
- <PORTMAP PHYSICAL="s_axi_wdata"/>
- <PORTMAP PHYSICAL="s_axi_wstrb"/>
- <PORTMAP PHYSICAL="s_axi_wlast"/>
- <PORTMAP PHYSICAL="s_axi_wvalid"/>
- <PORTMAP PHYSICAL="s_axi_wready"/>
- <PORTMAP PHYSICAL="s_axi_bready"/>
- <PORTMAP PHYSICAL="s_axi_bid"/>
- <PORTMAP PHYSICAL="s_axi_bresp"/>
- <PORTMAP PHYSICAL="s_axi_bvalid"/>
- <PORTMAP PHYSICAL="s_axi_arid"/>
- <PORTMAP PHYSICAL="s_axi_araddr"/>
- <PORTMAP PHYSICAL="s_axi_arlen"/>
- <PORTMAP PHYSICAL="s_axi_arsize"/>
- <PORTMAP PHYSICAL="s_axi_arburst"/>
- <PORTMAP PHYSICAL="s_axi_arlock"/>
- <PORTMAP PHYSICAL="s_axi_arcache"/>
- <PORTMAP PHYSICAL="s_axi_arprot"/>
- <PORTMAP PHYSICAL="s_axi_arqos"/>
- <PORTMAP PHYSICAL="s_axi_arvalid"/>
- <PORTMAP PHYSICAL="s_axi_arready"/>
- <PORTMAP PHYSICAL="s_axi_rready"/>
- <PORTMAP PHYSICAL="s_axi_rid"/>
- <PORTMAP PHYSICAL="s_axi_rdata"/>
- <PORTMAP PHYSICAL="s_axi_rresp"/>
- <PORTMAP PHYSICAL="s_axi_rlast"/>
- <PORTMAP PHYSICAL="s_axi_rvalid"/>
- </PORTMAPS>
- </BUSINTERFACE>
- <BUSINTERFACE BUSNAME="External_Interface_sys_diff_clock" NAME="SYS_CLK" TYPE="TARGET">
- <PORTMAPS>
- <PORTMAP PHYSICAL="sys_clk_p"/>
- <PORTMAP PHYSICAL="sys_clk_n"/>
- </PORTMAPS>
- </BUSINTERFACE>
- </BUSINTERFACES>
- </MODULE>
- <MODULE FULLNAME="/rst_clk_wiz_1_100M" HWVERSION="5.0" INSTANCE="rst_clk_wiz_1_100M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
- <DOCUMENTS>
- <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
- </DOCUMENTS>
- <PARAMETERS>
- <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
- <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
- <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
- <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
- <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
- <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
- <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
- <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
- <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_rst_clk_wiz_1_100M_0"/>
- <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
- <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
- </PARAMETERS>
- <PORTS>
- <PORT CLKFREQUENCY="100000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="ext_reset_in" SIGIS="rst" SIGNAME="mig_7series_0_ui_clk_sync_rst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk_sync_rst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="aux_reset_in" SIGIS="rst"/>
- <PORT DIR="I" NAME="mb_debug_sys_rst" SIGIS="rst" SIGNAME="mdm_1_Debug_SYS_Rst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mdm_1" PORT="Debug_SYS_Rst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="dcm_locked" SIGIS="undef" SIGNAME="mig_7series_0_mmcm_locked">
- <CONNECTIONS>
- <CONNECTION INSTANCE="mig_7series_0" PORT="mmcm_locked"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="mb_reset" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_mb_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="Reset"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="SYS_Rst"/>
- <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_Rst"/>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="SYS_Rst"/>
- <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_Rst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="peripheral_reset" RIGHT="0" SIGIS="rst"/>
- <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="ARESETN"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="ARESETN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_aresetn"/>
- <CONNECTION INSTANCE="mig_7series_0" PORT="aresetn"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_ARESETN"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_ARESETN"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_ARESETN"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_ARESETN"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_ARESETN"/>
- <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_ARESETN"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ARESETN"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ARESETN"/>
- <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ARESETN"/>
- </CONNECTIONS>
- </PORT>
- </PORTS>
- <BUSINTERFACES/>
- </MODULE>
- </MODULES>
-
- <REPOSITORIES/>
-
-</EDKSYSTEM>
+++ /dev/null
-\r
-################################################################\r
-# This is a generated script based on design: base_microblaze_design\r
-#\r
-# Though there are limitations about the generated script,\r
-# the main purpose of this utility is to make learning\r
-# IP Integrator Tcl commands easier.\r
-################################################################\r
-\r
-################################################################\r
-# Check if script is running in correct Vivado version.\r
-################################################################\r
-set scripts_vivado_version 2014.4\r
-set current_vivado_version [version -short]\r
-\r
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {\r
- puts ""\r
- puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."\r
-\r
- return 1\r
-}\r
-\r
-################################################################\r
-# START\r
-################################################################\r
-\r
-# To test this script, run the following commands from Vivado Tcl console:\r
-# source base_microblaze_design_script.tcl\r
-\r
-# If you do not already have a project created,\r
-# you can create a project using the following command:\r
-# create_project project_1 myproj -part xc7k325tffg900-2\r
-# set_property BOARD_PART xilinx.com:kc705:part0:1.1 [current_project]\r
-\r
-\r
-# CHANGE DESIGN NAME HERE\r
-set design_name base_microblaze_design\r
-\r
-# If you do not already have an existing IP Integrator design open,\r
-# you can create a design using the following command:\r
-# create_bd_design $design_name\r
-\r
-# CHECKING IF PROJECT EXISTS\r
-if { [get_projects -quiet] eq "" } {\r
- puts "ERROR: Please open or create a project!"\r
- return 1\r
-}\r
-\r
-\r
-# Creating design if needed\r
-set errMsg ""\r
-set nRet 0\r
-\r
-set cur_design [current_bd_design -quiet]\r
-set list_cells [get_bd_cells -quiet]\r
-\r
-if { ${design_name} eq "" } {\r
- # USE CASES:\r
- # 1) Design_name not set\r
-\r
- set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."\r
- set nRet 1\r
-\r
-} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {\r
- # USE CASES:\r
- # 2): Current design opened AND is empty AND names same.\r
- # 3): Current design opened AND is empty AND names diff; design_name NOT in project.\r
- # 4): Current design opened AND is empty AND names diff; design_name exists in project.\r
-\r
- if { $cur_design ne $design_name } {\r
- puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."\r
- set design_name [get_property NAME $cur_design]\r
- }\r
- puts "INFO: Constructing design in IPI design <$cur_design>..."\r
-\r
-} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {\r
- # USE CASES:\r
- # 5) Current design opened AND has components AND same names.\r
-\r
- set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."\r
- set nRet 1\r
-} elseif { [get_files -quiet ${design_name}.bd] ne "" } {\r
- # USE CASES: \r
- # 6) Current opened design, has components, but diff names, design_name exists in project.\r
- # 7) No opened design, design_name exists in project.\r
-\r
- set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."\r
- set nRet 2\r
-\r
-} else {\r
- # USE CASES:\r
- # 8) No opened design, design_name not in project.\r
- # 9) Current opened design, has components, but diff names, design_name not in project.\r
-\r
- puts "INFO: Currently there is no design <$design_name> in project, so creating one..."\r
-\r
- create_bd_design $design_name\r
-\r
- puts "INFO: Making design <$design_name> as current_bd_design."\r
- current_bd_design $design_name\r
-\r
-}\r
-\r
-puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."\r
-\r
-if { $nRet != 0 } {\r
- puts $errMsg\r
- return $nRet\r
-}\r
-\r
-##################################################################\r
-# DESIGN PROCs\r
-##################################################################\r
-\r
-\r
-# Hierarchical cell: microblaze_0_local_memory\r
-proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {\r
-\r
- if { $parentCell eq "" || $nameHier eq "" } {\r
- puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"\r
- return\r
- }\r
-\r
- # Get object for parentCell\r
- set parentObj [get_bd_cells $parentCell]\r
- if { $parentObj == "" } {\r
- puts "ERROR: Unable to find parent cell <$parentCell>!"\r
- return\r
- }\r
-\r
- # Make sure parentObj is hier blk\r
- set parentType [get_property TYPE $parentObj]\r
- if { $parentType ne "hier" } {\r
- puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."\r
- return\r
- }\r
-\r
- # Save current instance; Restore later\r
- set oldCurInst [current_bd_instance .]\r
-\r
- # Set parent object as current\r
- current_bd_instance $parentObj\r
-\r
- # Create cell and set as current instance\r
- set hier_obj [create_bd_cell -type hier $nameHier]\r
- current_bd_instance $hier_obj\r
-\r
- # Create interface pins\r
- create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB\r
- create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB\r
-\r
- # Create pins\r
- create_bd_pin -dir I -type clk LMB_Clk\r
- create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst\r
-\r
- # Create instance: dlmb_bram_if_cntlr, and set properties\r
- set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]\r
- set_property -dict [ list CONFIG.C_ECC {0} ] $dlmb_bram_if_cntlr\r
-\r
- # Create instance: dlmb_v10, and set properties\r
- set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]\r
-\r
- # Create instance: ilmb_bram_if_cntlr, and set properties\r
- set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]\r
- set_property -dict [ list CONFIG.C_ECC {0} ] $ilmb_bram_if_cntlr\r
-\r
- # Create instance: ilmb_v10, and set properties\r
- set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]\r
-\r
- # Create instance: lmb_bram, and set properties\r
- set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 lmb_bram ]\r
- set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller} ] $lmb_bram\r
-\r
- # Create interface connections\r
- connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]\r
- connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]\r
- connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]\r
- connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]\r
- connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]\r
- connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]\r
-\r
- # Create port connections\r
- connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]\r
- connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]\r
- \r
- # Restore current instance\r
- current_bd_instance $oldCurInst\r
-}\r
-\r
-\r
-# Procedure to create entire design; Provide argument to make\r
-# procedure reusable. If parentCell is "", will use root.\r
-proc create_root_design { parentCell } {\r
-\r
- if { $parentCell eq "" } {\r
- set parentCell [get_bd_cells /]\r
- }\r
-\r
- # Get object for parentCell\r
- set parentObj [get_bd_cells $parentCell]\r
- if { $parentObj == "" } {\r
- puts "ERROR: Unable to find parent cell <$parentCell>!"\r
- return\r
- }\r
-\r
- # Make sure parentObj is hier blk\r
- set parentType [get_property TYPE $parentObj]\r
- if { $parentType ne "hier" } {\r
- puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."\r
- return\r
- }\r
-\r
- # Save current instance; Restore later\r
- set oldCurInst [current_bd_instance .]\r
-\r
- # Set parent object as current\r
- current_bd_instance $parentObj\r
-\r
-\r
- # Create interface ports\r
- set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ]\r
- set led_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_8bits ]\r
- set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ]\r
- set mii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii ]\r
- set rs232_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart ]\r
- set sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]\r
-\r
- # Create ports\r
- set reset [ create_bd_port -dir I -type rst reset ]\r
- set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $reset\r
-\r
- # Create instance: axi_ethernetlite_0, and set properties\r
- set axi_ethernetlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:3.0 axi_ethernetlite_0 ]\r
- set_property -dict [ list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} CONFIG.MII_BOARD_INTERFACE {mii} CONFIG.USE_BOARD_FLOW {true} ] $axi_ethernetlite_0\r
-\r
- # Create instance: axi_gpio_0, and set properties\r
- set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]\r
- set_property -dict [ list CONFIG.GPIO_BOARD_INTERFACE {led_8bits} CONFIG.USE_BOARD_FLOW {true} ] $axi_gpio_0\r
-\r
- # Create instance: axi_intc_0, and set properties\r
- set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]\r
-\r
- # Create instance: axi_mem_intercon, and set properties\r
- set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]\r
- set_property -dict [ list CONFIG.NUM_MI {1} CONFIG.NUM_SI {2} ] $axi_mem_intercon\r
-\r
- # Create instance: axi_timer_0, and set properties\r
- set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]\r
-\r
- # Create instance: axi_uartlite_0, and set properties\r
- set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]\r
- set_property -dict [ list CONFIG.C_BAUDRATE {115200} CONFIG.UARTLITE_BOARD_INTERFACE {rs232_uart} CONFIG.USE_BOARD_FLOW {true} ] $axi_uartlite_0\r
-\r
- # Create instance: mdm_1, and set properties\r
- set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]\r
-\r
- # Create instance: microblaze_0, and set properties\r
- set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.4 microblaze_0 ]\r
- set_property -dict [ list CONFIG.C_CACHE_BYTE_SIZE {32768} \\r
-CONFIG.C_DCACHE_BYTE_SIZE {32768} CONFIG.C_DCACHE_LINE_LEN {8} \\r
-CONFIG.C_DCACHE_USE_WRITEBACK {1} CONFIG.C_DCACHE_VICTIMS {8} \\r
-CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_DIV_ZERO_EXCEPTION {1} \\r
-CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} \\r
-CONFIG.C_FPU_EXCEPTION {1} CONFIG.C_ICACHE_LINE_LEN {8} \\r
-CONFIG.C_ICACHE_STREAMS {1} CONFIG.C_ICACHE_VICTIMS {8} \\r
-CONFIG.C_ILL_OPCODE_EXCEPTION {1} CONFIG.C_I_LMB {1} \\r
-CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \\r
-CONFIG.C_NUMBER_OF_PC_BRK {8} CONFIG.C_NUMBER_OF_RD_ADDR_BRK {2} \\r
-CONFIG.C_NUMBER_OF_WR_ADDR_BRK {2} CONFIG.C_OPCODE_0x0_ILLEGAL {1} \\r
-CONFIG.C_TRACE {1} CONFIG.C_UNALIGNED_EXCEPTIONS {1} \\r
-CONFIG.C_USE_BARREL {1} CONFIG.C_USE_BRANCH_TARGET_CACHE {1} \\r
-CONFIG.C_USE_DCACHE {1} CONFIG.C_USE_DIV {1} \\r
-CONFIG.C_USE_FPU {2} CONFIG.C_USE_HW_MUL {2} \\r
-CONFIG.C_USE_ICACHE {1} CONFIG.C_USE_MSR_INSTR {1} \\r
-CONFIG.C_USE_PCMP_INSTR {1} CONFIG.C_USE_REORDER_INSTR {1} \\r
-CONFIG.C_USE_STACK_PROTECTION {1} CONFIG.G_TEMPLATE_LIST {2} \\r
-CONFIG.G_USE_EXCEPTIONS {1} ] $microblaze_0\r
-\r
- # Create instance: microblaze_0_axi_periph, and set properties\r
- set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]\r
- set_property -dict [ list CONFIG.NUM_MI {5} CONFIG.NUM_SI {1} ] $microblaze_0_axi_periph\r
-\r
- # Create instance: microblaze_0_local_memory\r
- create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory\r
-\r
- # Create instance: mig_7series_0, and set properties\r
- set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 mig_7series_0 ]\r
- set_property -dict [ list CONFIG.BOARD_MIG_PARAM {ddr3_sdram} CONFIG.RESET_BOARD_INTERFACE {reset} ] $mig_7series_0\r
-\r
- # Create instance: rst_clk_wiz_1_100M, and set properties\r
- set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]\r
- set_property -dict [ list CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.USE_BOARD_FLOW {true} ] $rst_clk_wiz_1_100M\r
-\r
- # Create instance: xlconcat_0, and set properties\r
- set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]\r
- set_property -dict [ list CONFIG.NUM_PORTS {3} ] $xlconcat_0\r
-\r
- # Create interface connections\r
- connect_bd_intf_net -intf_net SYS_CLK_1 [get_bd_intf_ports sys_diff_clock] [get_bd_intf_pins mig_7series_0/SYS_CLK]\r
- connect_bd_intf_net -intf_net axi_ethernetlite_0_MDIO [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernetlite_0/MDIO]\r
- connect_bd_intf_net -intf_net axi_ethernetlite_0_MII [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernetlite_0/MII]\r
- connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports led_8bits] [get_bd_intf_pins axi_gpio_0/GPIO]\r
- connect_bd_intf_net -intf_net axi_intc_0_interrupt [get_bd_intf_pins axi_intc_0/interrupt] [get_bd_intf_pins microblaze_0/INTERRUPT]\r
- connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]\r
- connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports rs232_uart] [get_bd_intf_pins axi_uartlite_0/UART]\r
- connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC]\r
- connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]\r
- connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC]\r
- connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]\r
- connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]\r
- connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]\r
- connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI]\r
- connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_ethernetlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI]\r
- connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]\r
- connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]\r
- connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]\r
- connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3]\r
-\r
- # Create port connections\r
- connect_bd_net -net axi_ethernetlite_0_ip2intc_irpt [get_bd_pins axi_ethernetlite_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In2]\r
- connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In0]\r
- connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In1]\r
- connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst]\r
- connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_ethernetlite_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]\r
- connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked]\r
- connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]\r
- connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins mig_7series_0/sys_rst]\r
- connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset]\r
- connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]\r
- connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]\r
- connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_ethernetlite_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]\r
- connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout]\r
-\r
- # Create address segments\r
- create_bd_addr_seg -range 0x10000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_ethernetlite_0/S_AXI/Reg] SEG_axi_ethernetlite_0_Reg\r
- create_bd_addr_seg -range 0x10000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg\r
- create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_intc_0/s_axi/Reg] SEG_axi_intc_0_Reg\r
- create_bd_addr_seg -range 0x10000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg\r
- create_bd_addr_seg -range 0x10000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg\r
- create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem\r
- create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem\r
- create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr\r
- create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr\r
- \r
-\r
- # Restore current instance\r
- current_bd_instance $oldCurInst\r
-\r
- save_bd_design\r
-}\r
-# End of create_root_design()\r
-\r
-\r
-##################################################################\r
-# MAIN FLOW\r
-##################################################################\r
-\r
-create_root_design ""\r
-\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>\r
-<MemInfo Version="1" Minor="0">\r
- <Processor Endianness="Little" InstPath="base_microblaze_design_i/microblaze_0">\r
- <AddressSpace Name="base_microblaze_design_i_microblaze_0.base_microblaze_design_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="262143">\r
- <BusBlock>\r
- <BitLane MemType="RAMB32" Placement="X1Y4">\r
- <DataWidth MSB="7" LSB="7"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y8">\r
- <DataWidth MSB="6" LSB="6"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X0Y8">\r
- <DataWidth MSB="5" LSB="5"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y0">\r
- <DataWidth MSB="4" LSB="4"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y12">\r
- <DataWidth MSB="3" LSB="3"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y5">\r
- <DataWidth MSB="2" LSB="2"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y17">\r
- <DataWidth MSB="1" LSB="1"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y6">\r
- <DataWidth MSB="0" LSB="0"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y1">\r
- <DataWidth MSB="15" LSB="15"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y3">\r
- <DataWidth MSB="14" LSB="14"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y7">\r
- <DataWidth MSB="13" LSB="13"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y2">\r
- <DataWidth MSB="12" LSB="12"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y13">\r
- <DataWidth MSB="11" LSB="11"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y13">\r
- <DataWidth MSB="10" LSB="10"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y0">\r
- <DataWidth MSB="9" LSB="9"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y2">\r
- <DataWidth MSB="8" LSB="8"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y8">\r
- <DataWidth MSB="23" LSB="23"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y7">\r
- <DataWidth MSB="22" LSB="22"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y10">\r
- <DataWidth MSB="21" LSB="21"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y7">\r
- <DataWidth MSB="20" LSB="20"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y11">\r
- <DataWidth MSB="19" LSB="19"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y0">\r
- <DataWidth MSB="18" LSB="18"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y11">\r
- <DataWidth MSB="17" LSB="17"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y2">\r
- <DataWidth MSB="16" LSB="16"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y6">\r
- <DataWidth MSB="31" LSB="31"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y9">\r
- <DataWidth MSB="30" LSB="30"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y15">\r
- <DataWidth MSB="29" LSB="29"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y3">\r
- <DataWidth MSB="28" LSB="28"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y15">\r
- <DataWidth MSB="27" LSB="27"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y13">\r
- <DataWidth MSB="26" LSB="26"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y9">\r
- <DataWidth MSB="25" LSB="25"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y5">\r
- <DataWidth MSB="24" LSB="24"/>\r
- <AddressRange Begin="0" End="32767"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- </BusBlock>\r
- <BusBlock>\r
- <BitLane MemType="RAMB32" Placement="X1Y5">\r
- <DataWidth MSB="7" LSB="7"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y9">\r
- <DataWidth MSB="6" LSB="6"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X0Y9">\r
- <DataWidth MSB="5" LSB="5"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y1">\r
- <DataWidth MSB="4" LSB="4"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y13">\r
- <DataWidth MSB="3" LSB="3"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y6">\r
- <DataWidth MSB="2" LSB="2"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y18">\r
- <DataWidth MSB="1" LSB="1"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y7">\r
- <DataWidth MSB="0" LSB="0"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y2">\r
- <DataWidth MSB="15" LSB="15"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y4">\r
- <DataWidth MSB="14" LSB="14"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y8">\r
- <DataWidth MSB="13" LSB="13"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y3">\r
- <DataWidth MSB="12" LSB="12"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y14">\r
- <DataWidth MSB="11" LSB="11"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y14">\r
- <DataWidth MSB="10" LSB="10"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y1">\r
- <DataWidth MSB="9" LSB="9"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y3">\r
- <DataWidth MSB="8" LSB="8"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y9">\r
- <DataWidth MSB="23" LSB="23"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y8">\r
- <DataWidth MSB="22" LSB="22"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y11">\r
- <DataWidth MSB="21" LSB="21"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y8">\r
- <DataWidth MSB="20" LSB="20"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y12">\r
- <DataWidth MSB="19" LSB="19"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y1">\r
- <DataWidth MSB="18" LSB="18"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y12">\r
- <DataWidth MSB="17" LSB="17"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y3">\r
- <DataWidth MSB="16" LSB="16"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X1Y7">\r
- <DataWidth MSB="31" LSB="31"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X2Y10">\r
- <DataWidth MSB="30" LSB="30"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X4Y16">\r
- <DataWidth MSB="29" LSB="29"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y4">\r
- <DataWidth MSB="28" LSB="28"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X3Y16">\r
- <DataWidth MSB="27" LSB="27"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X5Y14">\r
- <DataWidth MSB="26" LSB="26"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y10">\r
- <DataWidth MSB="25" LSB="25"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- <BitLane MemType="RAMB32" Placement="X6Y6">\r
- <DataWidth MSB="24" LSB="24"/>\r
- <AddressRange Begin="32768" End="65535"/>\r
- <Parity ON="false" NumBits="0"/>\r
- </BitLane>\r
- </BusBlock>\r
- </AddressSpace>\r
- </Processor>\r
- <Config>\r
- <Option Name="Part" Val="xc7k325tffg900-2"/>\r
- </Config>\r
-</MemInfo>\r
+++ /dev/null
-<?xml version="1.0"?>\r
-<Project Version="1" Minor="0">\r
- <BUILD_NUMBER Name="1071353"/>\r
- <FULL_BUILD Name="SW Build 1071353 on Tue Nov 18 18:29:27 MST 2014"/>\r
- <MODE Name="Post-Bitstream"/>\r
- <SYSTEMINFO BOARD="xilinx.com:kc705:part0:1.1" ARCH="kintex7" PACKAGE="ffg900" DEVICE="7k325t" SPEED="-2" LUT="" FF="" BRAM="" DSP=""/>\r
- <HIERARCHY Name="base_microblaze_design_i"/>\r
- <File Type="HW_HANDOFF" Name="base_microblaze_design.hwh" ModTime="1421754940"/>\r
- <File Type="BIT" Name="base_microblaze_design_wrapper.bit" ModTime="1421759776"/>\r
- <File Type="BMM" Name="base_microblaze_design_wrapper.mmi" ModTime="1421759676"/>\r
- <File Type="BD_TCL" Name="base_microblaze_design_bd.tcl" ModTime="1421754940"/>\r
- <USEDRESOURCES LUT="" FF="" BRAM="" DSP=""/>\r
-</Project>\r
-\r
projects / freertos / commitdiff