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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup gpio_v4_1
39 * This header file contains identifiers and driver functions (or
40 * macros) that can be used to access the device. The user should refer to the
41 * hardware device specification for more details of the device operation.
43 * The macros that are available in this file use a multiply to calculate the
44 * addresses of registers. The user can control whether that multiply is done
45 * at run time or at compile time. A constant passed as the channel parameter
46 * will cause the multiply to be done at compile time. A variable passed as the
47 * channel parameter will cause it to occur at run time.
50 * MODIFICATION HISTORY:
52 * Ver Who Date Changes
53 * ----- ---- -------- -----------------------------------------------
54 * 1.00a jhl 04/24/02 First release of low level driver
55 * 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
56 * change required the functions to be changed such that
57 * the interface is not compatible with previous versions.
58 * See the examples in the example directory for macros
59 * to help compile an application that was designed for
60 * previous versions of the driver. The interrupt registers
61 * are accessible using the ReadReg and WriteReg macros and
62 * a channel parameter was added to the other macros.
63 * 2.11a mta 03/21/07 Updated to new coding style
64 * 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
65 * 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
66 * XGpio_mReadReg to XGpio_ReadReg.
67 * Removed the macros XGpio_mSetDataDirection,
68 * XGpio_mGetDataReg and XGpio_mSetDataReg. Users
69 * should use XGpio_WriteReg/XGpio_ReadReg to achieve the
71 * 4.1 lks 11/18/15 Removed support for DCR bridge
74 ******************************************************************************/
76 #ifndef XGPIO_L_H /* prevent circular inclusions */
77 #define XGPIO_L_H /* by using protection macros */
83 /***************************** Include Files *********************************/
85 #include "xil_types.h"
86 #include "xil_assert.h"
90 /************************** Constant Definitions *****************************/
94 * Register offsets for this device.
97 #define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
98 #define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
99 #define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
100 #define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
102 #define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
103 #define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
104 #define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
108 /* The following constant describes the offset of each channels data and
109 * tristate register from the base address.
111 #define XGPIO_CHAN_OFFSET 8
113 /** @name Interrupt Status and Enable Register bitmaps and masks
115 * Bit definitions for the interrupt status register and interrupt enable
119 #define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
120 #define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
121 #define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
125 /** @name Global Interrupt Enable Register bitmaps and masks
127 * Bit definitions for the Global Interrupt Enable register
130 #define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000
135 /**************************** Type Definitions *******************************/
138 /***************** Macros (Inline Functions) Definitions *********************/
140 #define XGpio_In32 Xil_In32
141 #define XGpio_Out32 Xil_Out32
144 /****************************************************************************/
147 * Write a value to a GPIO register. A 32 bit write is performed. If the
148 * GPIO core is implemented in a smaller width, only the least significant data
151 * @param BaseAddress is the base address of the GPIO device.
152 * @param RegOffset is the register offset from the base to write to.
153 * @param Data is the data written to the register.
157 * @note C-style signature:
158 * void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
160 ****************************************************************************/
161 #define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
162 XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
164 /****************************************************************************/
167 * Read a value from a GPIO register. A 32 bit read is performed. If the
168 * GPIO core is implemented in a smaller width, only the least
169 * significant data is read from the register. The most significant data
172 * @param BaseAddress is the base address of the GPIO device.
173 * @param RegOffset is the register offset from the base to read from.
175 * @return Data read from the register.
177 * @note C-style signature:
178 * u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
180 ****************************************************************************/
181 #define XGpio_ReadReg(BaseAddress, RegOffset) \
182 XGpio_In32((BaseAddress) + (RegOffset))
184 /************************** Function Prototypes ******************************/
186 /************************** Variable Definitions *****************************/
192 #endif /* end of protection macro */