1 /******************************************************************************
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29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
35 * @file xil_misc_reset.c
37 * This file contains the implementation of the reset sequence for various
38 * zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
39 * sequence provided to the interfaces is based on the provision in
40 * slcr reset functional blcok.
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- ---- -------- -------------------------------------------------------
47 * 1.00b kpc 03/07/13 First release
48 * 5.4 pkp 16/11/15 Change the description for XOcm_Remap function
51 ******************************************************************************/
54 /***************************** Include Files *********************************/
55 #include "xil_misc_psreset_api.h"
57 /************************** Constant Definitions *****************************/
60 /**************************** Type Definitions *******************************/
63 /***************** Macros (Inline Functions) Definitions *********************/
66 /************************** Function Prototypes ******************************/
69 /*****************************************************************************/
71 * This function contains the implementation for ddr reset.
79 ******************************************************************************/
80 void XDdr_ResetHw(void)
84 /* Unlock the slcr register access lock */
85 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
86 /* Assert and deassert the ddr softreset bit */
87 RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
88 RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
89 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
90 RegVal |= XDDRPS_CTRL_RESET_MASK;
91 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
95 /*****************************************************************************/
97 * This function contains the implementation for remapping the ocm memory region
98 * to postbootrom state.
106 ******************************************************************************/
107 void XOcm_Remap(void)
111 /* Unlock the slcr register access lock */
112 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
113 /* Map the ocm region to postbootrom state */
114 RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
115 RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
116 Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
119 /*****************************************************************************/
121 * This function contains the implementation for SMC reset sequence
123 * @param BaseAddress of the interface
129 ******************************************************************************/
130 void XSmc_ResetHw(u32 BaseAddress)
134 /* Clear the interuupts */
135 RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
136 RegVal |= XSMC_MEMC_CLR_CONFIG_MASK;
137 Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
138 /* Clear the idle counter registers */
139 Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
140 Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
141 /* Update the ecc registers with reset values */
142 Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
143 XSMC_ECC_MEMCFG1_RESET_VAL);
144 Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
145 XSMC_ECC_MEMCMD1_RESET_VAL);
146 Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
147 XSMC_ECC_MEMCMD2_RESET_VAL);
151 /*****************************************************************************/
153 * This function contains the implementation for updating the slcr mio registers
161 ******************************************************************************/
162 void XSlcr_MioWriteResetValues(void)
166 /* Unlock the slcr register access lock */
167 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
168 /* Update all the MIO registers with reset values */
169 for (i=0U; i<=1U;i++)
171 Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
172 XSLCR_MIO_PIN_00_RESET_VAL);
176 Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
177 XSLCR_MIO_PIN_02_RESET_VAL);
181 Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
182 XSLCR_MIO_PIN_00_RESET_VAL);
188 /*****************************************************************************/
190 * This function contains the implementation for updating the slcr pll registers
198 ******************************************************************************/
199 void XSlcr_PllWriteResetValues(void)
202 /* Unlock the slcr register access lock */
203 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
205 /* update the pll control registers with reset values */
206 Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
207 Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
208 Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
209 /* update the pll config registers with reset values */
210 Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
211 Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
212 Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
213 /* update the clock control registers with reset values */
214 Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
215 Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
218 /*****************************************************************************/
220 * This function contains the implementation for disabling the level shifters
228 ******************************************************************************/
229 void XSlcr_DisableLevelShifters(void)
232 /* Unlock the slcr register access lock */
233 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
234 /* Disable the level shifters */
235 RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
236 RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
237 Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
240 /*****************************************************************************/
242 * This function contains the implementation for OCM software reset from the
251 ******************************************************************************/
252 void XSlcr_OcmReset(void)
255 /* Unlock the slcr register access lock */
256 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
257 /* Assert the reset */
258 RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
259 RegVal |= XSLCR_OCM_RST_CTRL_VAL;
260 Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
261 /* Release the reset */
262 RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
263 RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
264 Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
267 /*****************************************************************************/
269 * This function contains the implementation for Ethernet software reset from
277 ******************************************************************************/
278 void XSlcr_EmacPsReset(void)
281 /* Unlock the slcr register access lock */
282 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
283 /* Assert the reset */
284 RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
285 RegVal |= XSLCR_GEM_RST_CTRL_VAL;
286 Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
287 /* Release the reset */
288 RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
289 RegVal &= (u32)(~XSLCR_GEM_RST_CTRL_VAL);
290 Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
293 /*****************************************************************************/
295 * This function contains the implementation for USB software reset from the
304 ******************************************************************************/
305 void XSlcr_UsbPsReset(void)
308 /* Unlock the slcr register access lock */
309 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
310 /* Assert the reset */
311 RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
312 RegVal |= XSLCR_USB_RST_CTRL_VAL;
313 Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
314 /* Release the reset */
315 RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
316 RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
317 Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
319 /*****************************************************************************/
321 * This function contains the implementation for QSPI software reset from the
330 ******************************************************************************/
331 void XSlcr_QspiPsReset(void)
334 /* Unlock the slcr register access lock */
335 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
336 /* Assert the reset */
337 RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
338 RegVal |= XSLCR_QSPI_RST_CTRL_VAL;
339 Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
340 /* Release the reset */
341 RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
342 RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
343 Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
345 /*****************************************************************************/
347 * This function contains the implementation for SPI software reset from the
356 ******************************************************************************/
357 void XSlcr_SpiPsReset(void)
360 /* Unlock the slcr register access lock */
361 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
362 /* Assert the reset */
363 RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
364 RegVal |= XSLCR_SPI_RST_CTRL_VAL;
365 Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
366 /* Release the reset */
367 RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
368 RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
369 Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
371 /*****************************************************************************/
373 * This function contains the implementation for i2c software reset from the slcr
381 ******************************************************************************/
382 void XSlcr_I2cPsReset(void)
385 /* Unlock the slcr register access lock */
386 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
387 /* Assert the reset */
388 RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
389 RegVal |= XSLCR_I2C_RST_CTRL_VAL;
390 Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
391 /* Release the reset */
392 RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
393 RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
394 Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
396 /*****************************************************************************/
398 * This function contains the implementation for UART software reset from the
407 ******************************************************************************/
408 void XSlcr_UartPsReset(void)
411 /* Unlock the slcr register access lock */
412 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
413 /* Assert the reset */
414 RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
415 RegVal |= XSLCR_UART_RST_CTRL_VAL;
416 Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
417 /* Release the reset */
418 RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
419 RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
420 Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
422 /*****************************************************************************/
424 * This function contains the implementation for CAN software reset from slcr
433 ******************************************************************************/
434 void XSlcr_CanPsReset(void)
437 /* Unlock the slcr register access lock */
438 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
439 /* Assert the reset */
440 RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
441 RegVal |= XSLCR_CAN_RST_CTRL_VAL;
442 Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
443 /* Release the reset */
444 RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
445 RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
446 Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
448 /*****************************************************************************/
450 * This function contains the implementation for SMC software reset from the slcr
458 ******************************************************************************/
459 void XSlcr_SmcPsReset(void)
462 /* Unlock the slcr register access lock */
463 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
464 /* Assert the reset */
465 RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
466 RegVal |= XSLCR_SMC_RST_CTRL_VAL;
467 Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
468 /* Release the reset */
469 RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
470 RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
471 Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
473 /*****************************************************************************/
475 * This function contains the implementation for DMA controller software reset
484 ******************************************************************************/
485 void XSlcr_DmaPsReset(void)
488 /* Unlock the slcr register access lock */
489 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
490 /* Assert the reset */
491 RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
492 RegVal |= XSLCR_DMAC_RST_CTRL_VAL;
493 Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
494 /* Release the reset */
495 RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
496 RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
497 Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
499 /*****************************************************************************/
501 * This function contains the implementation for Gpio AMBA software reset from
510 ******************************************************************************/
511 void XSlcr_GpioPsReset(void)
514 /* Unlock the slcr register access lock */
515 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
516 /* Assert the reset */
517 RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
518 RegVal |= XSLCR_GPIO_RST_CTRL_VAL;
519 Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
520 /* Release the reset */
521 RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
522 RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
523 Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);