1 Disassembly Listing for PIC32MEC14xx_RTOSDemo
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3 C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/dist/default/debug/PIC32MEC14xx_RTOSDemo.X.debug.elf
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6 --- c:/e/dev/freertos/workingcopy/freertos/source/timers.c --------------------------------------------
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8 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
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9 3: All rights reserved
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11 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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13 7: This file is part of the FreeRTOS distribution.
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15 9: FreeRTOS is free software; you can redistribute it and/or modify it under
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16 10: the terms of the GNU General Public License (version 2) as published by the
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17 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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19 13: ***************************************************************************
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20 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
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21 15: >>! distribute a combined work that includes FreeRTOS without being !<<
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22 16: >>! obliged to provide the source code for proprietary components !<<
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23 17: >>! outside of the FreeRTOS kernel. !<<
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24 18: ***************************************************************************
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26 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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27 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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28 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
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29 23: link: http://www.freertos.org/a00114.html
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31 25: ***************************************************************************
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33 27: * FreeRTOS provides completely free yet professionally developed, *
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34 28: * robust, strictly quality controlled, supported, and cross *
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35 29: * platform software that is more than just the market leader, it *
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36 30: * is the industry's de facto standard. *
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38 32: * Help yourself get started quickly while simultaneously helping *
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39 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
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40 34: * tutorial book, reference manual, or both: *
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41 35: * http://www.FreeRTOS.org/Documentation *
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43 37: ***************************************************************************
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45 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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46 40: the FAQ page "My application does not run, what could be wrong?". Have you
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47 41: defined configASSERT()?
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49 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
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50 44: embedded software for free we request you assist our global community by
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51 45: participating in the support forum.
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53 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
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54 48: be as productive as possible as early as possible. Now you can receive
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55 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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56 50: Ltd, and the world's leading authority on the world's leading RTOS.
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58 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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59 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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60 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
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62 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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63 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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65 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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66 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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67 61: licenses offer ticketed support, indemnification and commercial middleware.
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69 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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70 64: engineered and independently SIL3 certified version for use in safety and
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71 65: mission critical applications that require provable dependability.
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73 67: 1 tab == 4 spaces!
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76 70: /* Standard includes. */
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77 71: #include <stdlib.h>
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79 73: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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80 74: all the API functions to use the MPU wrappers. That should only be done when
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81 75: task.h is included from an application file. */
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82 76: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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84 78: #include "FreeRTOS.h"
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85 79: #include "task.h"
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86 80: #include "queue.h"
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87 81: #include "timers.h"
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89 83: #if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
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90 84: #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
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93 87: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the
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94 88: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
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95 89: header files above, but not in this file, in order to generate the correct
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96 90: privileged Vs unprivileged linkage and placement. */
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97 91: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
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100 94: /* This entire source file will be skipped if the application is not configured
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101 95: to include software timer functionality. This #if is closed at the very bottom
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102 96: of this file. If you want to include software timer functionality then ensure
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103 97: configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
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104 98: #if ( configUSE_TIMERS == 1 )
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106 100: /* Misc definitions. */
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107 101: #define tmrNO_DELAY ( TickType_t ) 0U
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109 103: /* The definition of the timers themselves. */
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110 104: typedef struct tmrTimerControl
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112 106: const char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
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113 107: ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */
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114 108: TickType_t xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
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115 109: UBaseType_t uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one-shot timer. */
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116 110: void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */
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117 111: TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */
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118 112: #if( configUSE_TRACE_FACILITY == 1 )
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119 113: UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */
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123 117: /* The old xTIMER name is maintained above then typedefed to the new Timer_t
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124 118: name below to enable the use of older kernel aware debuggers. */
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125 119: typedef xTIMER Timer_t;
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127 121: /* The definition of messages that can be sent and received on the timer queue.
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128 122: Two types of message can be queued - messages that manipulate a software timer,
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129 123: and messages that request the execution of a non-timer related callback. The
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130 124: two message types are defined in two separate structures, xTimerParametersType
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131 125: and xCallbackParametersType respectively. */
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132 126: typedef struct tmrTimerParameters
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134 128: TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
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135 129: Timer_t * pxTimer; /*<< The timer to which the command will be applied. */
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136 130: } TimerParameter_t;
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139 133: typedef struct tmrCallbackParameters
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141 135: PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
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142 136: void *pvParameter1; /* << The value that will be used as the callback functions first parameter. */
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143 137: uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */
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144 138: } CallbackParameters_t;
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146 140: /* The structure that contains the two message types, along with an identifier
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147 141: that is used to determine which message type is valid. */
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148 142: typedef struct tmrTimerQueueMessage
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150 144: BaseType_t xMessageID; /*<< The command being sent to the timer service task. */
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153 147: TimerParameter_t xTimerParameters;
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155 149: /* Don't include xCallbackParameters if it is not going to be used as
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156 150: it makes the structure (and therefore the timer queue) larger. */
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157 151: #if ( INCLUDE_xTimerPendFunctionCall == 1 )
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158 152: CallbackParameters_t xCallbackParameters;
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159 153: #endif /* INCLUDE_xTimerPendFunctionCall */
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161 155: } DaemonTaskMessage_t;
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163 157: /*lint -e956 A manual analysis and inspection has been used to determine which
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164 158: static variables must be declared volatile. */
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166 160: /* The list in which active timers are stored. Timers are referenced in expire
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167 161: time order, with the nearest expiry time at the front of the list. Only the
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168 162: timer service task is allowed to access these lists. */
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169 163: PRIVILEGED_DATA static List_t xActiveTimerList1;
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170 164: PRIVILEGED_DATA static List_t xActiveTimerList2;
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171 165: PRIVILEGED_DATA static List_t *pxCurrentTimerList;
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172 166: PRIVILEGED_DATA static List_t *pxOverflowTimerList;
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174 168: /* A queue that is used to send commands to the timer service task. */
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175 169: PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
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177 171: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
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179 173: PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
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183 177: /*lint +e956 */
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185 179: /*-----------------------------------------------------------*/
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188 182: * Initialise the infrastructure used by the timer service task if it has not
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189 183: * been initialised already.
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191 185: static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
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194 188: * The timer service task (daemon). Timer functionality is controlled by this
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195 189: * task. Other tasks communicate with the timer service task using the
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196 190: * xTimerQueue queue.
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198 192: static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
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201 195: * Called by the timer service task to interpret and process a command it
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202 196: * received on the timer queue.
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204 198: static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
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207 201: * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
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208 202: * depending on if the expire time causes a timer counter overflow.
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210 204: static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
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213 207: * An active timer has reached its expire time. Reload the timer if it is an
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214 208: * auto reload timer, then call its callback.
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216 210: static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
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219 213: * The tick count has overflowed. Switch the timer lists after ensuring the
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220 214: * current timer list does not still reference some timers.
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222 216: static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
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225 219: * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
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226 220: * if a tick count overflow occurred since prvSampleTimeNow() was last called.
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228 222: static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
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231 225: * If the timer list contains any active timers then return the expire time of
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232 226: * the timer that will expire first and set *pxListWasEmpty to false. If the
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233 227: * timer list does not contain any timers then return 0 and set *pxListWasEmpty
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236 230: static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
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239 233: * If a timer has expired, process it. Otherwise, block the timer service task
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240 234: * until either a timer does expire or a command is received.
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242 236: static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
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244 238: /*-----------------------------------------------------------*/
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246 240: BaseType_t xTimerCreateTimerTask( void )
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248 BFD07A6C 4FE9 ADDIU SP, SP, -48
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249 BFD07A6E CBEB SW RA, 44(SP)
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250 BFD07A70 CBCA SW S8, 40(SP)
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251 BFD07A72 0FDD MOVE S8, SP
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252 242: BaseType_t xReturn = pdFAIL;
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253 BFD07A74 0020F81E SW ZERO, 32(S8)
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255 244: /* This function is called when the scheduler is started if
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256 245: configUSE_TIMERS is set to 1. Check that the infrastructure used by the
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257 246: timer service task has been created/initialised. If timers have already
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258 247: been created then the initialisation will already have been performed. */
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259 248: prvCheckForValidListAndQueue();
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260 BFD07A78 35F477E8 JALS prvCheckForValidListAndQueue
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261 BFD07A7A 0C0035F4 LHU T7, 3072(S4)
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264 250: if( xTimerQueue != NULL )
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265 BFD07A7E 8068FC5C LW V0, -32664(GP)
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266 BFD07A82 001540E2 BEQZC V0, 0xBFD07AB0
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268 252: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
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270 254: /* Create the timer task, storing its handle in xTimerTaskHandle so
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271 255: it can be returned by the xTimerGetTimerDaemonTaskHandle() function. */
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272 256: xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, &xTimerTaskHandle );
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276 260: /* Create the timer task without storing its handle. */
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277 261: xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, NULL);
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278 BFD07A86 ED02 LI V0, 2
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279 BFD07A88 C844 SW V0, 16(SP)
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280 BFD07A8A C805 SW ZERO, 20(SP)
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281 BFD07A8C C806 SW ZERO, 24(SP)
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282 BFD07A8E C807 SW ZERO, 28(SP)
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283 BFD07A90 BFD141A2 LUI V0, 0xBFD1
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284 BFD07A92 3082BFD1 LDC1 F30, 12418(S1)
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285 BFD07A94 97393082 ADDIU A0, V0, -26823
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286 BFD07A96 41A29739 BEQ T9, T9, 0xBFD0FDDE
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287 BFD07A98 BFD141A2 LUI V0, 0xBFD1
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288 BFD07A9A 30A2BFD1 LDC1 F30, 12450(S1)
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289 BFD07A9C 9AE030A2 ADDIU A1, V0, -25888
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290 BFD07A9E 30C09AE0 SWC1 F23, 12480(ZERO)
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291 BFD07AA0 017C30C0 ADDIU A2, ZERO, 380
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292 BFD07AA4 0CE0 MOVE A3, ZERO
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293 BFD07AA6 0A9A77E8 JALS xTaskGenericCreate
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294 BFD07AA8 0A9A LBU A1, 10(S1)
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296 BFD07AAC 0020F85E SW V0, 32(S8)
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302 267: mtCOVERAGE_TEST_MARKER();
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305 270: configASSERT( xReturn );
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306 BFD07AB0 0020FC5E LW V0, 32(S8)
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307 BFD07AB4 000940A2 BNEZC V0, 0xBFD07ACA
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308 BFD07AB8 BFD141A2 LUI V0, 0xBFD1
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309 BFD07ABA 3082BFD1 LDC1 F30, 12418(S1)
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310 BFD07ABC 9AE83082 ADDIU A0, V0, -25880
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311 BFD07ABE 30A09AE8 SWC1 F23, 12448(T0)
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312 BFD07AC0 010E30A0 ADDIU A1, ZERO, 270
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313 BFD07AC4 4B7E77E8 JALS vAssertCalled
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314 BFD07AC6 4B7E LW K1, 120(SP)
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316 271: return xReturn;
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317 BFD07ACA 0020FC5E LW V0, 32(S8)
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319 BFD07ACE 0FBE MOVE SP, S8
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320 BFD07AD0 4BEB LW RA, 44(SP)
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321 BFD07AD2 4BCA LW S8, 40(SP)
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322 BFD07AD4 4C19 ADDIU SP, SP, 48
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323 BFD07AD6 459F JR16 RA
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325 273: /*-----------------------------------------------------------*/
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327 275: TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
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329 BFD061D8 4FF1 ADDIU SP, SP, -32
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330 BFD061DA CBE7 SW RA, 28(SP)
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331 BFD061DC CBC6 SW S8, 24(SP)
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332 BFD061DE 0FDD MOVE S8, SP
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333 BFD061E0 0020F89E SW A0, 32(S8)
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334 BFD061E4 0024F8BE SW A1, 36(S8)
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335 BFD061E8 0028F8DE SW A2, 40(S8)
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336 BFD061EC 002CF8FE SW A3, 44(S8)
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337 277: Timer_t *pxNewTimer;
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339 279: /* Allocate the timer structure. */
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340 280: if( xTimerPeriodInTicks == ( TickType_t ) 0U )
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341 BFD061F0 0024FC5E LW V0, 36(S8)
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342 BFD061F4 000440A2 BNEZC V0, 0xBFD06200
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344 282: pxNewTimer = NULL;
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345 BFD061F8 0010F81E SW ZERO, 16(S8)
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346 BFD061FC CC2E B 0xBFD0625A
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351 286: pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
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352 BFD06200 EE28 LI A0, 40
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353 BFD06202 111677E8 JALS pvPortMalloc
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354 BFD06204 0C001116 ADDI T0, S6, 3072
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356 BFD06208 0010F85E SW V0, 16(S8)
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357 287: if( pxNewTimer != NULL )
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358 BFD0620C 0010FC5E LW V0, 16(S8)
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359 BFD06210 002340E2 BEQZC V0, 0xBFD0625A
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361 289: /* Ensure the infrastructure used by the timer service task has been
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362 290: created/initialised. */
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363 291: prvCheckForValidListAndQueue();
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364 BFD06214 35F477E8 JALS prvCheckForValidListAndQueue
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365 BFD06216 0C0035F4 LHU T7, 3072(S4)
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368 293: /* Initialise the timer structure members using the function parameters. */
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369 294: pxNewTimer->pcTimerName = pcTimerName;
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370 BFD0621A 0010FC5E LW V0, 16(S8)
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371 BFD0621E 0020FC7E LW V1, 32(S8)
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372 BFD06222 E9A0 SW V1, 0(V0)
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373 295: pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
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374 BFD06224 0010FC5E LW V0, 16(S8)
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375 BFD06228 0024FC7E LW V1, 36(S8)
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376 BFD0622C E9A6 SW V1, 24(V0)
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377 296: pxNewTimer->uxAutoReload = uxAutoReload;
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378 BFD0622E 0010FC5E LW V0, 16(S8)
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379 BFD06232 0028FC7E LW V1, 40(S8)
\r
380 BFD06236 E9A7 SW V1, 28(V0)
\r
381 297: pxNewTimer->pvTimerID = pvTimerID;
\r
382 BFD06238 0010FC5E LW V0, 16(S8)
\r
383 BFD0623C 002CFC7E LW V1, 44(S8)
\r
384 BFD06240 E9A8 SW V1, 32(V0)
\r
385 298: pxNewTimer->pxCallbackFunction = pxCallbackFunction;
\r
386 BFD06242 0010FC5E LW V0, 16(S8)
\r
387 BFD06246 0030FC7E LW V1, 48(S8)
\r
388 BFD0624A E9A9 SW V1, 36(V0)
\r
389 299: vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
\r
390 BFD0624C 0010FC5E LW V0, 16(S8)
\r
391 BFD06250 6D22 ADDIU V0, V0, 4
\r
392 BFD06252 0C82 MOVE A0, V0
\r
393 BFD06254 4EE677E8 JALS vListInitialiseItem
\r
394 BFD06256 4EE6 ADDIU S7, S7, 3
\r
397 301: traceTIMER_CREATE( pxNewTimer );
\r
401 305: traceTIMER_CREATE_FAILED();
\r
405 309: /* 0 is not a valid value for xTimerPeriodInTicks. */
\r
406 310: configASSERT( ( xTimerPeriodInTicks > 0 ) );
\r
407 BFD0625A 0024FC5E LW V0, 36(S8)
\r
408 BFD0625E 000940A2 BNEZC V0, 0xBFD06274
\r
409 BFD06262 BFD141A2 LUI V0, 0xBFD1
\r
410 BFD06264 3082BFD1 LDC1 F30, 12418(S1)
\r
411 BFD06266 9AE83082 ADDIU A0, V0, -25880
\r
412 BFD06268 30A09AE8 SWC1 F23, 12448(T0)
\r
413 BFD0626A 013630A0 ADDIU A1, ZERO, 310
\r
414 BFD0626E 4B7E77E8 JALS vAssertCalled
\r
415 BFD06270 4B7E LW K1, 120(SP)
\r
418 312: return ( TimerHandle_t ) pxNewTimer;
\r
419 BFD06274 0010FC5E LW V0, 16(S8)
\r
421 BFD06278 0FBE MOVE SP, S8
\r
422 BFD0627A 4BE7 LW RA, 28(SP)
\r
423 BFD0627C 4BC6 LW S8, 24(SP)
\r
424 BFD0627E 4C11 ADDIU SP, SP, 32
\r
425 BFD06280 459F JR16 RA
\r
427 314: /*-----------------------------------------------------------*/
\r
429 316: BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
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431 BFD05A1C 4FE9 ADDIU SP, SP, -48
\r
432 BFD05A1E CBEB SW RA, 44(SP)
\r
433 BFD05A20 CBCA SW S8, 40(SP)
\r
434 BFD05A22 0FDD MOVE S8, SP
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435 BFD05A24 0030F89E SW A0, 48(S8)
\r
436 BFD05A28 0034F8BE SW A1, 52(S8)
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437 BFD05A2C 0038F8DE SW A2, 56(S8)
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438 BFD05A30 003CF8FE SW A3, 60(S8)
\r
439 318: BaseType_t xReturn = pdFAIL;
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440 BFD05A34 0010F81E SW ZERO, 16(S8)
\r
441 319: DaemonTaskMessage_t xMessage;
\r
443 321: /* Send a message to the timer service task to perform a particular action
\r
444 322: on a particular timer definition. */
\r
445 323: if( xTimerQueue != NULL )
\r
446 BFD05A38 8068FC5C LW V0, -32664(GP)
\r
447 BFD05A3C 004740E2 BEQZC V0, 0xBFD05ACE
\r
449 325: /* Send a command to the timer service task to start the xTimer timer. */
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450 326: xMessage.xMessageID = xCommandID;
\r
451 BFD05A40 0034FC5E LW V0, 52(S8)
\r
452 BFD05A44 0014F85E SW V0, 20(S8)
\r
453 327: xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
\r
454 BFD05A48 0038FC5E LW V0, 56(S8)
\r
455 BFD05A4C 0018F85E SW V0, 24(S8)
\r
456 328: xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
\r
457 BFD05A50 0030FC5E LW V0, 48(S8)
\r
458 BFD05A54 001CF85E SW V0, 28(S8)
\r
460 330: if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
\r
461 BFD05A58 0034FC5E LW V0, 52(S8)
\r
462 BFD05A5C 00069042 SLTI V0, V0, 6
\r
463 BFD05A60 002740E2 BEQZC V0, 0xBFD05AB2
\r
465 332: if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
\r
466 BFD05A64 4A8E77E8 JALS xTaskGetSchedulerState
\r
467 BFD05A66 4A8E LW S4, 56(SP)
\r
469 BFD05A6A 0C62 MOVE V1, V0
\r
470 BFD05A6C ED02 LI V0, 2
\r
471 BFD05A6E 0011B443 BNE V1, V0, 0xBFD05A94
\r
472 BFD05A70 0C000011 SLL ZERO, S1, 1
\r
475 334: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
\r
476 BFD05A74 8068FC7C LW V1, -32664(GP)
\r
477 BFD05A78 0014305E ADDIU V0, S8, 20
\r
478 BFD05A7C 0C83 MOVE A0, V1
\r
479 BFD05A7E 0CA2 MOVE A1, V0
\r
480 BFD05A80 0040FCDE LW A2, 64(S8)
\r
481 BFD05A84 0CE0 MOVE A3, ZERO
\r
482 BFD05A86 06A277E8 JALS xQueueGenericSend
\r
483 BFD05A88 06A2 ADDU A1, S1, V0
\r
485 BFD05A8C 0010F85E SW V0, 16(S8)
\r
486 BFD05A90 CC1E B 0xBFD05ACE
\r
491 338: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
\r
492 BFD05A94 8068FC7C LW V1, -32664(GP)
\r
493 BFD05A98 0014305E ADDIU V0, S8, 20
\r
494 BFD05A9C 0C83 MOVE A0, V1
\r
495 BFD05A9E 0CA2 MOVE A1, V0
\r
496 BFD05AA0 0CC0 MOVE A2, ZERO
\r
497 BFD05AA2 0CE0 MOVE A3, ZERO
\r
498 BFD05AA4 06A277E8 JALS xQueueGenericSend
\r
499 BFD05AA6 06A2 ADDU A1, S1, V0
\r
501 BFD05AAA 0010F85E SW V0, 16(S8)
\r
502 BFD05AAE CC0F B 0xBFD05ACE
\r
508 343: xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
\r
509 BFD05AB2 8068FC7C LW V1, -32664(GP)
\r
510 BFD05AB6 0014305E ADDIU V0, S8, 20
\r
511 BFD05ABA 0C83 MOVE A0, V1
\r
512 BFD05ABC 0CA2 MOVE A1, V0
\r
513 BFD05ABE 003CFCDE LW A2, 60(S8)
\r
514 BFD05AC2 0CE0 MOVE A3, ZERO
\r
515 BFD05AC4 11EA77E8 JALS xQueueGenericSendFromISR
\r
516 BFD05AC6 0C0011EA ADDI T7, T2, 3072
\r
518 BFD05ACA 0010F85E SW V0, 16(S8)
\r
521 346: traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
\r
525 350: mtCOVERAGE_TEST_MARKER();
\r
528 353: return xReturn;
\r
529 BFD05ACE 0010FC5E LW V0, 16(S8)
\r
531 BFD05AD2 0FBE MOVE SP, S8
\r
532 BFD05AD4 4BEB LW RA, 44(SP)
\r
533 BFD05AD6 4BCA LW S8, 40(SP)
\r
534 BFD05AD8 4C19 ADDIU SP, SP, 48
\r
535 BFD05ADA 459F JR16 RA
\r
537 355: /*-----------------------------------------------------------*/
\r
539 357: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
\r
541 359: TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
\r
543 361: /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
\r
544 362: started, then xTimerTaskHandle will be NULL. */
\r
545 363: configASSERT( ( xTimerTaskHandle != NULL ) );
\r
546 364: return xTimerTaskHandle;
\r
550 368: /*-----------------------------------------------------------*/
\r
552 370: const char * pcTimerGetTimerName( TimerHandle_t xTimer )
\r
554 BFD09B04 4FF9 ADDIU SP, SP, -16
\r
555 BFD09B06 CBC3 SW S8, 12(SP)
\r
556 BFD09B08 0FDD MOVE S8, SP
\r
557 BFD09B0A 0010F89E SW A0, 16(S8)
\r
558 372: Timer_t *pxTimer = ( Timer_t * ) xTimer;
\r
559 BFD09B0E 0010FC5E LW V0, 16(S8)
\r
560 BFD09B12 0000F85E SW V0, 0(S8)
\r
562 374: return pxTimer->pcTimerName;
\r
563 BFD09B16 0000FC5E LW V0, 0(S8)
\r
564 BFD09B1A 6920 LW V0, 0(V0)
\r
566 BFD09B1C 0FBE MOVE SP, S8
\r
567 BFD09B1E 4BC3 LW S8, 12(SP)
\r
568 BFD09B20 4C09 ADDIU SP, SP, 16
\r
569 BFD09B22 459F JR16 RA
\r
571 376: /*-----------------------------------------------------------*/
\r
573 378: static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
\r
575 BFD05F24 4FED ADDIU SP, SP, -40
\r
576 BFD05F26 CBE9 SW RA, 36(SP)
\r
577 BFD05F28 CBC8 SW S8, 32(SP)
\r
578 BFD05F2A 0FDD MOVE S8, SP
\r
579 BFD05F2C 0028F89E SW A0, 40(S8)
\r
580 BFD05F30 002CF8BE SW A1, 44(S8)
\r
581 380: BaseType_t xResult;
\r
582 381: Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
\r
583 BFD05F34 8060FC5C LW V0, -32672(GP)
\r
584 BFD05F38 6923 LW V0, 12(V0)
\r
585 BFD05F3A 6923 LW V0, 12(V0)
\r
586 BFD05F3C 0018F85E SW V0, 24(S8)
\r
588 383: /* Remove the timer from the list of active timers. A check has already
\r
589 384: been performed to ensure the list is not empty. */
\r
590 385: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
\r
591 BFD05F40 0018FC5E LW V0, 24(S8)
\r
592 BFD05F44 6D22 ADDIU V0, V0, 4
\r
593 BFD05F46 0C82 MOVE A0, V0
\r
594 BFD05F48 00C877E8 JALS uxListRemove
\r
595 BFD05F4A 0C0000C8 SLL A2, T0, 1
\r
597 386: traceTIMER_EXPIRED( pxTimer );
\r
599 388: /* If the timer is an auto reload timer then calculate the next
\r
600 389: expiry time and re-insert the timer in the list of active timers. */
\r
601 390: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
\r
602 BFD05F4E 0018FC5E LW V0, 24(S8)
\r
603 BFD05F52 69A7 LW V1, 28(V0)
\r
604 BFD05F54 ED01 LI V0, 1
\r
605 BFD05F56 002FB443 BNE V1, V0, 0xBFD05FB8
\r
606 BFD05F58 0C00002F SLL AT, T7, 1
\r
609 392: /* The timer is inserted into a list using a time relative to anything
\r
610 393: other than the current time. It will therefore be inserted into the
\r
611 394: correct list relative to the time this task thinks it is now. */
\r
612 395: if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )
\r
613 BFD05F5C 0018FC5E LW V0, 24(S8)
\r
614 BFD05F60 69A6 LW V1, 24(V0)
\r
615 BFD05F62 0028FC5E LW V0, 40(S8)
\r
616 BFD05F66 0526 ADDU V0, V1, V0
\r
617 BFD05F68 0018FC9E LW A0, 24(S8)
\r
618 BFD05F6C 0CA2 MOVE A1, V0
\r
619 BFD05F6E 002CFCDE LW A2, 44(S8)
\r
620 BFD05F72 0028FCFE LW A3, 40(S8)
\r
621 BFD05F76 2BE477E8 JALS prvInsertTimerInActiveList
\r
622 BFD05F78 2BE4 LHU A3, 8(A2)
\r
624 BFD05F7C 0C62 MOVE V1, V0
\r
625 BFD05F7E ED01 LI V0, 1
\r
626 BFD05F80 001AB443 BNE V1, V0, 0xBFD05FB8
\r
627 BFD05F82 0C00001A SLL ZERO, K0, 1
\r
630 397: /* The timer expired before it was added to the active timer
\r
631 398: list. Reload it now. */
\r
632 399: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
\r
633 BFD05F86 C804 SW ZERO, 16(SP)
\r
634 BFD05F88 0018FC9E LW A0, 24(S8)
\r
635 BFD05F8C 0CA0 MOVE A1, ZERO
\r
636 BFD05F8E 0028FCDE LW A2, 40(S8)
\r
637 BFD05F92 0CE0 MOVE A3, ZERO
\r
638 BFD05F94 2D0E77E8 JALS xTimerGenericCommand
\r
639 BFD05F96 2D0E ANDI V0, S0, 0x8000
\r
641 BFD05F9A 001CF85E SW V0, 28(S8)
\r
642 400: configASSERT( xResult );
\r
643 BFD05F9E 001CFC5E LW V0, 28(S8)
\r
644 BFD05FA2 000940A2 BNEZC V0, 0xBFD05FB8
\r
645 BFD05FA6 BFD141A2 LUI V0, 0xBFD1
\r
646 BFD05FA8 3082BFD1 LDC1 F30, 12418(S1)
\r
647 BFD05FAA 9AE83082 ADDIU A0, V0, -25880
\r
648 BFD05FAC 30A09AE8 SWC1 F23, 12448(T0)
\r
649 BFD05FAE 019030A0 ADDIU A1, ZERO, 400
\r
650 BFD05FB2 4B7E77E8 JALS vAssertCalled
\r
651 BFD05FB4 4B7E LW K1, 120(SP)
\r
653 401: ( void ) xResult;
\r
657 405: mtCOVERAGE_TEST_MARKER();
\r
662 410: mtCOVERAGE_TEST_MARKER();
\r
665 413: /* Call the timer callback. */
\r
666 414: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
\r
667 BFD05FB8 0018FC5E LW V0, 24(S8)
\r
668 BFD05FBC 6929 LW V0, 36(V0)
\r
669 BFD05FBE 0018FC9E LW A0, 24(S8)
\r
670 BFD05FC2 45E2 JALRS16 V0
\r
673 BFD05FC6 0FBE MOVE SP, S8
\r
674 BFD05FC8 4BE9 LW RA, 36(SP)
\r
675 BFD05FCA 4BC8 LW S8, 32(SP)
\r
676 BFD05FCC 4C15 ADDIU SP, SP, 40
\r
677 BFD05FCE 459F JR16 RA
\r
679 416: /*-----------------------------------------------------------*/
\r
681 418: static void prvTimerTask( void *pvParameters )
\r
683 BFD09738 4FF1 ADDIU SP, SP, -32
\r
684 BFD0973A CBE7 SW RA, 28(SP)
\r
685 BFD0973C CBC6 SW S8, 24(SP)
\r
686 BFD0973E 0FDD MOVE S8, SP
\r
687 BFD09740 0020F89E SW A0, 32(S8)
\r
688 420: TickType_t xNextExpireTime;
\r
689 421: BaseType_t xListWasEmpty;
\r
691 423: /* Just to avoid compiler warnings. */
\r
692 424: ( void ) pvParameters;
\r
696 428: /* Query the timers list to see if it contains any timers, and if so,
\r
697 429: obtain the time at which the next timer will expire. */
\r
698 430: xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
\r
699 BFD09744 0014305E ADDIU V0, S8, 20
\r
700 BFD09748 0C82 MOVE A0, V0
\r
701 BFD0974A 47EE77E8 JALS prvGetNextExpireTime
\r
703 BFD09750 0010F85E SW V0, 16(S8)
\r
705 432: /* If a timer has expired, process it. Otherwise, block this task
\r
706 433: until either a timer does expire, or a command is received. */
\r
707 434: prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
\r
708 BFD09754 0014FC5E LW V0, 20(S8)
\r
709 BFD09758 0010FC9E LW A0, 16(S8)
\r
710 BFD0975C 0CA2 MOVE A1, V0
\r
711 BFD0975E 2D7077E8 JALS prvProcessTimerOrBlockTask
\r
712 BFD09760 2D70 ANDI V0, A3, 0x80
\r
715 436: /* Empty the command queue. */
\r
716 437: prvProcessReceivedCommands();
\r
717 BFD09764 0B9A77E8 JALS prvProcessReceivedCommands
\r
718 BFD09766 0B9A LBU A3, 10(S1)
\r
721 BFD0976A CFEC B 0xBFD09744
\r
724 440: /*-----------------------------------------------------------*/
\r
726 442: static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty )
\r
728 BFD05AE0 4FED ADDIU SP, SP, -40
\r
729 BFD05AE2 CBE9 SW RA, 36(SP)
\r
730 BFD05AE4 CBC8 SW S8, 32(SP)
\r
731 BFD05AE6 0FDD MOVE S8, SP
\r
732 BFD05AE8 0028F89E SW A0, 40(S8)
\r
733 BFD05AEC 002CF8BE SW A1, 44(S8)
\r
734 444: TickType_t xTimeNow;
\r
735 445: BaseType_t xTimerListsWereSwitched;
\r
737 447: vTaskSuspendAll();
\r
738 BFD05AF0 4EF477E8 JALS vTaskSuspendAll
\r
739 BFD05AF2 4EF4 ADDIU S7, S7, -6
\r
742 449: /* Obtain the time now to make an assessment as to whether the timer
\r
743 450: has expired or not. If obtaining the time causes the lists to switch
\r
744 451: then don't process this timer as any timers that remained in the list
\r
745 452: when the lists were switched will have been processed within the
\r
746 453: prvSampleTimeNow() function. */
\r
747 454: xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
\r
748 BFD05AF6 0018305E ADDIU V0, S8, 24
\r
749 BFD05AFA 0C82 MOVE A0, V0
\r
750 BFD05AFC 42A877E8 JALS prvSampleTimeNow
\r
751 BFD05AFE 0C0042A8 BC2T 2, 0xBFD07302
\r
753 BFD05B02 0010F85E SW V0, 16(S8)
\r
754 455: if( xTimerListsWereSwitched == pdFALSE )
\r
755 BFD05B06 0018FC5E LW V0, 24(S8)
\r
756 BFD05B0A 003D40A2 BNEZC V0, 0xBFD05B88
\r
758 457: /* The tick count has not overflowed, has the timer expired? */
\r
759 458: if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
\r
760 BFD05B0E 002CFC5E LW V0, 44(S8)
\r
761 BFD05B12 001440A2 BNEZC V0, 0xBFD05B3E
\r
762 BFD05B16 0028FC7E LW V1, 40(S8)
\r
763 BFD05B1A 0010FC5E LW V0, 16(S8)
\r
764 BFD05B1E 13900062 SLTU V0, V0, V1
\r
765 BFD05B20 40A21390 ADDI GP, S0, 16546
\r
766 BFD05B22 000C40A2 BNEZC V0, 0xBFD05B3E
\r
768 460: ( void ) xTaskResumeAll();
\r
769 BFD05B26 158E77E8 JALS xTaskResumeAll
\r
770 BFD05B28 0C00158E LBU T4, 3072(T6)
\r
772 461: prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
\r
773 BFD05B2C 0028FC9E LW A0, 40(S8)
\r
774 BFD05B30 0010FCBE LW A1, 16(S8)
\r
775 BFD05B34 2F9277E8 JALS prvProcessExpiredTimer
\r
776 BFD05B36 2F92 ANDI A3, S1, 0x2
\r
778 BFD05B3A CC2C B 0xBFD05B94
\r
783 465: /* The tick count has not overflowed, and the next expire
\r
784 466: time has not been reached yet. This task should therefore
\r
785 467: block to wait for the next expire time or a command to be
\r
786 468: received - whichever comes first. The following line cannot
\r
787 469: be reached unless xNextExpireTime > xTimeNow, except in the
\r
788 470: case when the current timer list is empty. */
\r
789 471: vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
\r
790 BFD05B3E 8068FC7C LW V1, -32664(GP)
\r
791 BFD05B42 0028FC9E LW A0, 40(S8)
\r
792 BFD05B46 0010FC5E LW V0, 16(S8)
\r
793 BFD05B4A 0529 SUBU V0, A0, V0
\r
794 BFD05B4C 0C83 MOVE A0, V1
\r
795 BFD05B4E 0CA2 MOVE A1, V0
\r
796 BFD05B50 002CFCDE LW A2, 44(S8)
\r
797 BFD05B54 349477E8 JALS vQueueWaitForMessageRestricted
\r
798 BFD05B56 0C003494 LHU A0, 3072(S4)
\r
801 473: if( xTaskResumeAll() == pdFALSE )
\r
802 BFD05B5A 158E77E8 JALS xTaskResumeAll
\r
803 BFD05B5C 0C00158E LBU T4, 3072(T6)
\r
805 BFD05B60 001740A2 BNEZC V0, 0xBFD05B92
\r
807 475: /* Yield to wait for either a command to arrive, or the
\r
808 476: block time to expire. If a command arrived between the
\r
809 477: critical section being exited and this yield then the yield
\r
810 478: will not cause the task to block. */
\r
811 479: portYIELD_WITHIN_API();
\r
812 BFD05B64 4E7677E8 JALS ulPortGetCP0Cause
\r
813 BFD05B66 4E76 ADDIU S3, S3, -5
\r
815 BFD05B6A 0014F85E SW V0, 20(S8)
\r
816 BFD05B6E 0014FC5E LW V0, 20(S8)
\r
817 BFD05B72 01005042 ORI V0, V0, 256
\r
818 BFD05B76 0014F85E SW V0, 20(S8)
\r
819 BFD05B7A 0014FC9E LW A0, 20(S8)
\r
820 BFD05B7E 4E8677E8 JALS vPortSetCP0Cause
\r
821 BFD05B80 4E86 ADDIU S4, S4, 3
\r
823 BFD05B84 CC07 B 0xBFD05B94
\r
829 483: mtCOVERAGE_TEST_MARKER();
\r
835 489: ( void ) xTaskResumeAll();
\r
836 BFD05B88 158E77E8 JALS xTaskResumeAll
\r
837 BFD05B8A 0C00158E LBU T4, 3072(T6)
\r
839 BFD05B8E CC02 B 0xBFD05B94
\r
844 BFD05B94 0FBE MOVE SP, S8
\r
845 BFD05B96 4BE9 LW RA, 36(SP)
\r
846 BFD05B98 4BC8 LW S8, 32(SP)
\r
847 BFD05B9A 4C15 ADDIU SP, SP, 40
\r
848 BFD05B9C 459F JR16 RA
\r
850 493: /*-----------------------------------------------------------*/
\r
852 495: static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
\r
854 BFD08FDC 4FF9 ADDIU SP, SP, -16
\r
855 BFD08FDE CBC3 SW S8, 12(SP)
\r
856 BFD08FE0 0FDD MOVE S8, SP
\r
857 BFD08FE2 0010F89E SW A0, 16(S8)
\r
858 497: TickType_t xNextExpireTime;
\r
860 499: /* Timers are listed in expiry time order, with the head of the list
\r
861 500: referencing the task that will expire first. Obtain the time at which
\r
862 501: the timer with the nearest expiry time will expire. If there are no
\r
863 502: active timers then just set the next expire time to 0. That will cause
\r
864 503: this task to unblock when the tick count overflows, at which point the
\r
865 504: timer lists will be switched and the next expiry time can be
\r
866 505: re-assessed. */
\r
867 506: *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
\r
868 BFD08FE6 8060FC5C LW V0, -32672(GP)
\r
869 BFD08FEA 6920 LW V0, 0(V0)
\r
870 BFD08FEC 0001B062 SLTIU V1, V0, 1
\r
871 BFD08FF0 0010FC5E LW V0, 16(S8)
\r
872 BFD08FF4 E9A0 SW V1, 0(V0)
\r
873 507: if( *pxListWasEmpty == pdFALSE )
\r
874 BFD08FF6 0010FC5E LW V0, 16(S8)
\r
875 BFD08FFA 6920 LW V0, 0(V0)
\r
876 BFD08FFC 000840A2 BNEZC V0, 0xBFD09010
\r
878 509: xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
\r
879 BFD09000 8060FC5C LW V0, -32672(GP)
\r
880 BFD09004 6923 LW V0, 12(V0)
\r
881 BFD09006 6920 LW V0, 0(V0)
\r
882 BFD09008 0000F85E SW V0, 0(S8)
\r
883 BFD0900C CC03 B 0xBFD09014
\r
888 513: /* Ensure the task unblocks when the tick count rolls over. */
\r
889 514: xNextExpireTime = ( TickType_t ) 0U;
\r
890 BFD09010 0000F81E SW ZERO, 0(S8)
\r
893 517: return xNextExpireTime;
\r
894 BFD09014 0000FC5E LW V0, 0(S8)
\r
896 BFD09018 0FBE MOVE SP, S8
\r
897 BFD0901A 4BC3 LW S8, 12(SP)
\r
898 BFD0901C 4C09 ADDIU SP, SP, 16
\r
899 BFD0901E 459F JR16 RA
\r
901 519: /*-----------------------------------------------------------*/
\r
903 521: static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
\r
905 BFD08550 4FF1 ADDIU SP, SP, -32
\r
906 BFD08552 CBE7 SW RA, 28(SP)
\r
907 BFD08554 CBC6 SW S8, 24(SP)
\r
908 BFD08556 0FDD MOVE S8, SP
\r
909 BFD08558 0020F89E SW A0, 32(S8)
\r
910 523: TickType_t xTimeNow;
\r
911 524: PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
\r
913 526: xTimeNow = xTaskGetTickCount();
\r
914 BFD0855C 4CCA77E8 JALS xTaskGetTickCount
\r
915 BFD0855E 4CCA ADDIU A2, A2, 5
\r
917 BFD08562 0010F85E SW V0, 16(S8)
\r
919 528: if( xTimeNow < xLastTime )
\r
920 BFD08566 806CFC5C LW V0, -32660(GP)
\r
921 BFD0856A 0010FC7E LW V1, 16(S8)
\r
922 BFD0856E 13900043 SLTU V0, V1, V0
\r
923 BFD08570 40E21390 ADDI GP, S0, 16610
\r
924 BFD08572 000940E2 BEQZC V0, 0xBFD08588
\r
926 530: prvSwitchTimerLists();
\r
927 BFD08576 1F7877E8 JALS prvSwitchTimerLists
\r
928 BFD08578 0C001F78 LB K1, 3072(T8)
\r
930 531: *pxTimerListsWereSwitched = pdTRUE;
\r
931 BFD0857C 0020FC5E LW V0, 32(S8)
\r
932 BFD08580 ED81 LI V1, 1
\r
933 BFD08582 E9A0 SW V1, 0(V0)
\r
934 BFD08584 CC04 B 0xBFD0858E
\r
939 535: *pxTimerListsWereSwitched = pdFALSE;
\r
940 BFD08588 0020FC5E LW V0, 32(S8)
\r
941 BFD0858C E820 SW S0, 0(V0)
\r
944 538: xLastTime = xTimeNow;
\r
945 BFD0858E 0010FC5E LW V0, 16(S8)
\r
946 BFD08592 806CF85C SW V0, -32660(GP)
\r
948 540: return xTimeNow;
\r
949 BFD08596 0010FC5E LW V0, 16(S8)
\r
951 BFD0859A 0FBE MOVE SP, S8
\r
952 BFD0859C 4BE7 LW RA, 28(SP)
\r
953 BFD0859E 4BC6 LW S8, 24(SP)
\r
954 BFD085A0 4C11 ADDIU SP, SP, 32
\r
955 BFD085A2 459F JR16 RA
\r
957 542: /*-----------------------------------------------------------*/
\r
959 544: static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
\r
961 BFD057C8 4FF1 ADDIU SP, SP, -32
\r
962 BFD057CA CBE7 SW RA, 28(SP)
\r
963 BFD057CC CBC6 SW S8, 24(SP)
\r
964 BFD057CE 0FDD MOVE S8, SP
\r
965 BFD057D0 0020F89E SW A0, 32(S8)
\r
966 BFD057D4 0024F8BE SW A1, 36(S8)
\r
967 BFD057D8 0028F8DE SW A2, 40(S8)
\r
968 BFD057DC 002CF8FE SW A3, 44(S8)
\r
969 546: BaseType_t xProcessTimerNow = pdFALSE;
\r
970 BFD057E0 0010F81E SW ZERO, 16(S8)
\r
972 548: listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
\r
973 BFD057E4 0020FC5E LW V0, 32(S8)
\r
974 BFD057E8 0024FC7E LW V1, 36(S8)
\r
975 BFD057EC E9A1 SW V1, 4(V0)
\r
976 549: listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
\r
977 BFD057EE 0020FC5E LW V0, 32(S8)
\r
978 BFD057F2 0020FC7E LW V1, 32(S8)
\r
979 BFD057F6 E9A4 SW V1, 16(V0)
\r
981 551: if( xNextExpiryTime <= xTimeNow )
\r
982 BFD057F8 0024FC7E LW V1, 36(S8)
\r
983 BFD057FC 0028FC5E LW V0, 40(S8)
\r
984 BFD05800 13900062 SLTU V0, V0, V1
\r
985 BFD05802 40A21390 ADDI GP, S0, 16546
\r
986 BFD05804 001D40A2 BNEZC V0, 0xBFD05842
\r
988 553: /* Has the expiry time elapsed between the command to start/reset a
\r
989 554: timer was issued, and the time the command was processed? */
\r
990 555: if( ( xTimeNow - xCommandTime ) >= pxTimer->xTimerPeriodInTicks )
\r
991 BFD05808 0028FC7E LW V1, 40(S8)
\r
992 BFD0580C 002CFC5E LW V0, 44(S8)
\r
993 BFD05810 05A7 SUBU V1, V1, V0
\r
994 BFD05812 0020FC5E LW V0, 32(S8)
\r
995 BFD05816 6926 LW V0, 24(V0)
\r
996 BFD05818 13900043 SLTU V0, V1, V0
\r
997 BFD0581A 40A21390 ADDI GP, S0, 16546
\r
998 BFD0581C 000540A2 BNEZC V0, 0xBFD0582A
\r
1000 557: /* The time between a command being issued and the command being
\r
1001 558: processed actually exceeds the timers period. */
\r
1002 559: xProcessTimerNow = pdTRUE;
\r
1003 BFD05820 ED01 LI V0, 1
\r
1004 BFD05822 0010F85E SW V0, 16(S8)
\r
1005 BFD05824 CC2C0010 EXT ZERO, S0, 16, 26
\r
1006 BFD05826 CC2C B 0xBFD05880
\r
1011 563: vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
\r
1012 BFD0582A 8064FC7C LW V1, -32668(GP)
\r
1013 BFD0582E 0020FC5E LW V0, 32(S8)
\r
1014 BFD05832 6D22 ADDIU V0, V0, 4
\r
1015 BFD05834 0C83 MOVE A0, V1
\r
1016 BFD05836 0CA2 MOVE A1, V0
\r
1017 BFD05838 304077E8 JALS vListInsert
\r
1018 BFD0583A 0C003040 ADDIU V0, ZERO, 3072
\r
1020 BFD0583E CC20 B 0xBFD05880
\r
1026 568: if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
\r
1027 BFD05842 0028FC7E LW V1, 40(S8)
\r
1028 BFD05846 002CFC5E LW V0, 44(S8)
\r
1029 BFD0584A 13900043 SLTU V0, V1, V0
\r
1030 BFD0584C 40E21390 ADDI GP, S0, 16610
\r
1031 BFD0584E 000D40E2 BEQZC V0, 0xBFD0586C
\r
1032 BFD05852 0024FC7E LW V1, 36(S8)
\r
1033 BFD05856 002CFC5E LW V0, 44(S8)
\r
1034 BFD0585A 13900043 SLTU V0, V1, V0
\r
1035 BFD0585C 40A21390 ADDI GP, S0, 16546
\r
1036 BFD0585E 000540A2 BNEZC V0, 0xBFD0586C
\r
1038 570: /* If, since the command was issued, the tick count has overflowed
\r
1039 571: but the expiry time has not, then the timer must have already passed
\r
1040 572: its expiry time and should be processed immediately. */
\r
1041 573: xProcessTimerNow = pdTRUE;
\r
1042 BFD05862 ED01 LI V0, 1
\r
1043 BFD05864 0010F85E SW V0, 16(S8)
\r
1044 BFD05868 CC0B B 0xBFD05880
\r
1049 577: vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
\r
1050 BFD0586C 8060FC7C LW V1, -32672(GP)
\r
1051 BFD05870 0020FC5E LW V0, 32(S8)
\r
1052 BFD05874 6D22 ADDIU V0, V0, 4
\r
1053 BFD05876 0C83 MOVE A0, V1
\r
1054 BFD05878 0CA2 MOVE A1, V0
\r
1055 BFD0587A 304077E8 JALS vListInsert
\r
1056 BFD0587C 0C003040 ADDIU V0, ZERO, 3072
\r
1061 581: return xProcessTimerNow;
\r
1062 BFD05880 0010FC5E LW V0, 16(S8)
\r
1064 BFD05884 0FBE MOVE SP, S8
\r
1065 BFD05886 4BE7 LW RA, 28(SP)
\r
1066 BFD05888 4BC6 LW S8, 24(SP)
\r
1067 BFD0588A 4C11 ADDIU SP, SP, 32
\r
1068 BFD0588C 459F JR16 RA
\r
1070 583: /*-----------------------------------------------------------*/
\r
1072 585: static void prvProcessReceivedCommands( void )
\r
1074 BFD01734 4FDD ADDIU SP, SP, -72
\r
1075 BFD01736 CBF1 SW RA, 68(SP)
\r
1076 BFD01738 CBD0 SW S8, 64(SP)
\r
1077 BFD0173A 0FDD MOVE S8, SP
\r
1078 587: DaemonTaskMessage_t xMessage;
\r
1079 588: Timer_t *pxTimer;
\r
1080 589: BaseType_t xTimerListsWereSwitched, xResult;
\r
1081 590: TickType_t xTimeNow;
\r
1083 592: while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
\r
1084 BFD0173C CCE0 B 0xBFD018FE
\r
1086 BFD018FE 8068FC7C LW V1, -32664(GP)
\r
1087 BFD01902 0028305E ADDIU V0, S8, 40
\r
1088 BFD01906 0C83 MOVE A0, V1
\r
1089 BFD01908 0CA2 MOVE A1, V0
\r
1090 BFD0190A 0CC0 MOVE A2, ZERO
\r
1091 BFD0190C 0CE0 MOVE A3, ZERO
\r
1092 BFD0190E 081E77E8 JALS xQueueGenericReceive
\r
1093 BFD01910 081E LBU S0, 14(S1)
\r
1095 BFD01914 FF1440A2 BNEZC V0, 0xBFD01740
\r
1096 BFD01916 0FBEFF14 LW T8, 4030(S4)
\r
1098 594: #if ( INCLUDE_xTimerPendFunctionCall == 1 )
\r
1100 596: /* Negative commands are pended function calls rather than timer
\r
1102 598: if( xMessage.xMessageID < ( BaseType_t ) 0 )
\r
1103 BFD01740 0028FC5E LW V0, 40(S8)
\r
1104 BFD01744 001F4042 BGEZ V0, 0xBFD01786
\r
1105 BFD01746 0C00001F SLL ZERO, RA, 1
\r
1108 600: const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
\r
1109 BFD0174A 0028305E ADDIU V0, S8, 40
\r
1110 BFD0174E 6D22 ADDIU V0, V0, 4
\r
1111 BFD01750 0018F85E SW V0, 24(S8)
\r
1113 602: /* The timer uses the xCallbackParameters member to request a
\r
1114 603: callback be executed. Check the callback is not NULL. */
\r
1115 604: configASSERT( pxCallback );
\r
1116 BFD01754 0018FC5E LW V0, 24(S8)
\r
1117 BFD01758 000940A2 BNEZC V0, 0xBFD0176E
\r
1118 BFD0175C BFD141A2 LUI V0, 0xBFD1
\r
1119 BFD0175E 3082BFD1 LDC1 F30, 12418(S1)
\r
1120 BFD01760 9AE83082 ADDIU A0, V0, -25880
\r
1121 BFD01762 30A09AE8 SWC1 F23, 12448(T0)
\r
1122 BFD01764 025C30A0 ADDIU A1, ZERO, 604
\r
1123 BFD01768 4B7E77E8 JALS vAssertCalled
\r
1124 BFD0176A 4B7E LW K1, 120(SP)
\r
1127 606: /* Call the function. */
\r
1128 607: pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
\r
1129 BFD0176E 0018FC5E LW V0, 24(S8)
\r
1130 BFD01772 6920 LW V0, 0(V0)
\r
1131 BFD01774 0018FC7E LW V1, 24(S8)
\r
1132 BFD01778 6A31 LW A0, 4(V1)
\r
1133 BFD0177A 0018FC7E LW V1, 24(S8)
\r
1134 BFD0177E 69B2 LW V1, 8(V1)
\r
1135 BFD01780 0CA3 MOVE A1, V1
\r
1136 BFD01782 45E2 JALRS16 V0
\r
1141 611: mtCOVERAGE_TEST_MARKER();
\r
1144 614: #endif /* INCLUDE_xTimerPendFunctionCall */
\r
1146 616: /* Commands that are positive are timer commands rather than pended
\r
1147 617: function calls. */
\r
1148 618: if( xMessage.xMessageID >= ( BaseType_t ) 0 )
\r
1149 BFD01786 0028FC5E LW V0, 40(S8)
\r
1150 BFD0178A 00B84002 BLTZ V0, 0xBFD018FE
\r
1151 BFD0178C 0C0000B8 SLL A1, T8, 1
\r
1154 620: /* The messages uses the xTimerParameters member to work on a
\r
1155 621: software timer. */
\r
1156 622: pxTimer = xMessage.u.xTimerParameters.pxTimer;
\r
1157 BFD01790 0030FC5E LW V0, 48(S8)
\r
1158 BFD01794 001CF85E SW V0, 28(S8)
\r
1160 624: if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
\r
1161 BFD01798 001CFC5E LW V0, 28(S8)
\r
1162 BFD0179C 6925 LW V0, 20(V0)
\r
1163 BFD0179E 000740E2 BEQZC V0, 0xBFD017B0
\r
1165 626: /* The timer is in a list, remove it. */
\r
1166 627: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
\r
1167 BFD017A2 001CFC5E LW V0, 28(S8)
\r
1168 BFD017A6 6D22 ADDIU V0, V0, 4
\r
1169 BFD017A8 0C82 MOVE A0, V0
\r
1170 BFD017AA 00C877E8 JALS uxListRemove
\r
1171 BFD017AC 0C0000C8 SLL A2, T0, 1
\r
1176 631: mtCOVERAGE_TEST_MARKER();
\r
1179 634: traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
\r
1181 636: /* In this case the xTimerListsWereSwitched parameter is not used, but
\r
1182 637: it must be present in the function call. prvSampleTimeNow() must be
\r
1183 638: called after the message is received from xTimerQueue so there is no
\r
1184 639: possibility of a higher priority task adding a message to the message
\r
1185 640: queue with a time that is ahead of the timer daemon task (because it
\r
1186 641: pre-empted the timer daemon task after the xTimeNow value was set). */
\r
1187 642: xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
\r
1188 BFD017B0 0038305E ADDIU V0, S8, 56
\r
1189 BFD017B4 0C82 MOVE A0, V0
\r
1190 BFD017B6 42A877E8 JALS prvSampleTimeNow
\r
1191 BFD017B8 0C0042A8 BC2T 2, 0xBFD02FBC
\r
1193 BFD017BC 0020F85E SW V0, 32(S8)
\r
1195 644: switch( xMessage.xMessageID )
\r
1196 BFD017C0 0028FC5E LW V0, 40(S8)
\r
1197 BFD017C4 000AB062 SLTIU V1, V0, 10
\r
1198 BFD017C8 008C40E3 BEQZC V1, 0xBFD018E4
\r
1199 BFD017CC 25A4 SLL V1, V0, 2
\r
1200 BFD017CE BFD041A2 LUI V0, 0xBFD0
\r
1201 BFD017D0 3042BFD0 LDC1 F30, 12354(S0)
\r
1202 BFD017D2 17DC3042 ADDIU V0, V0, 6108
\r
1203 BFD017D4 052617DC LBU S8, 1318(GP)
\r
1204 BFD017D6 0526 ADDU V0, V1, V0
\r
1205 BFD017D8 6920 LW V0, 0(V0)
\r
1206 BFD017DA 45A2 JRC V0
\r
1207 BFD017DC BFD01805 SB ZERO, -16432(A1)
\r
1208 BFD017DE 1805BFD0 LDC1 F30, 6149(S0)
\r
1209 BFD017E0 BFD01805 SB ZERO, -16432(A1)
\r
1210 BFD017E2 1805BFD0 LDC1 F30, 6149(S0)
\r
1211 BFD017E4 BFD01805 SB ZERO, -16432(A1)
\r
1212 BFD017E6 18EBBFD0 LDC1 F30, 6379(S0)
\r
1213 BFD017E8 BFD018EB SB A3, -16432(T3)
\r
1214 BFD017EA 188DBFD0 LDC1 F30, 6285(S0)
\r
1215 BFD017EC BFD0188D SB A0, -16432(T5)
\r
1216 BFD017EE 18D7BFD0 LDC1 F30, 6359(S0)
\r
1217 BFD017F0 BFD018D7 SB A2, -16432(S7)
\r
1218 BFD017F2 1805BFD0 LDC1 F30, 6149(S0)
\r
1219 BFD017F4 BFD01805 SB ZERO, -16432(A1)
\r
1220 BFD017F6 1805BFD0 LDC1 F30, 6149(S0)
\r
1221 BFD017F8 BFD01805 SB ZERO, -16432(A1)
\r
1222 BFD017FA 18EBBFD0 LDC1 F30, 6379(S0)
\r
1223 BFD017FC BFD018EB SB A3, -16432(T3)
\r
1224 BFD017FE 188DBFD0 LDC1 F30, 6285(S0)
\r
1225 BFD01800 BFD0188D SB A0, -16432(T5)
\r
1226 BFD01802 FC7EBFD0 LDC1 F30, -898(S0)
\r
1228 646: case tmrCOMMAND_START :
\r
1229 647: case tmrCOMMAND_START_FROM_ISR :
\r
1230 648: case tmrCOMMAND_RESET :
\r
1231 649: case tmrCOMMAND_RESET_FROM_ISR :
\r
1232 650: case tmrCOMMAND_START_DONT_TRACE :
\r
1233 651: /* Start or restart a timer. */
\r
1234 652: if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) == pdTRUE )
\r
1235 BFD01804 002CFC7E LW V1, 44(S8)
\r
1236 BFD01808 001CFC5E LW V0, 28(S8)
\r
1237 BFD0180C 6926 LW V0, 24(V0)
\r
1238 BFD0180E 05A6 ADDU V1, V1, V0
\r
1239 BFD01810 002CFC5E LW V0, 44(S8)
\r
1240 BFD01814 001CFC9E LW A0, 28(S8)
\r
1241 BFD01818 0CA3 MOVE A1, V1
\r
1242 BFD0181A 0020FCDE LW A2, 32(S8)
\r
1243 BFD0181E 0CE2 MOVE A3, V0
\r
1244 BFD01820 2BE477E8 JALS prvInsertTimerInActiveList
\r
1245 BFD01822 2BE4 LHU A3, 8(A2)
\r
1247 BFD01826 0C62 MOVE V1, V0
\r
1248 BFD01828 ED01 LI V0, 1
\r
1249 BFD0182A 0061B443 BNE V1, V0, 0xBFD018F0
\r
1250 BFD0182C 0C000061 SLL V1, AT, 1
\r
1253 654: /* The timer expired before it was added to the active
\r
1254 655: timer list. Process it now. */
\r
1255 656: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
\r
1256 BFD01830 001CFC5E LW V0, 28(S8)
\r
1257 BFD01834 6929 LW V0, 36(V0)
\r
1258 BFD01836 001CFC9E LW A0, 28(S8)
\r
1259 BFD0183A 45E2 JALRS16 V0
\r
1261 657: traceTIMER_EXPIRED( pxTimer );
\r
1263 659: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
\r
1264 BFD0183E 001CFC5E LW V0, 28(S8)
\r
1265 BFD01842 69A7 LW V1, 28(V0)
\r
1266 BFD01844 ED01 LI V0, 1
\r
1267 BFD01846 0056B443 BNE V1, V0, 0xBFD018F6
\r
1268 BFD01848 0C000056 SLL V0, S6, 1
\r
1271 661: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
\r
1272 BFD0184C 002CFC7E LW V1, 44(S8)
\r
1273 BFD01850 001CFC5E LW V0, 28(S8)
\r
1274 BFD01854 6926 LW V0, 24(V0)
\r
1275 BFD01856 0526 ADDU V0, V1, V0
\r
1276 BFD01858 C804 SW ZERO, 16(SP)
\r
1277 BFD0185A 001CFC9E LW A0, 28(S8)
\r
1278 BFD0185E 0CA0 MOVE A1, ZERO
\r
1279 BFD01860 0CC2 MOVE A2, V0
\r
1280 BFD01862 0CE0 MOVE A3, ZERO
\r
1281 BFD01864 2D0E77E8 JALS xTimerGenericCommand
\r
1282 BFD01866 2D0E ANDI V0, S0, 0x8000
\r
1284 BFD0186A 0024F85E SW V0, 36(S8)
\r
1285 662: configASSERT( xResult );
\r
1286 BFD0186E 0024FC5E LW V0, 36(S8)
\r
1287 BFD01872 004340A2 BNEZC V0, 0xBFD018FC
\r
1288 BFD01876 BFD141A2 LUI V0, 0xBFD1
\r
1289 BFD01878 3082BFD1 LDC1 F30, 12418(S1)
\r
1290 BFD0187A 9AE83082 ADDIU A0, V0, -25880
\r
1291 BFD0187C 30A09AE8 SWC1 F23, 12448(T0)
\r
1292 BFD0187E 029630A0 ADDIU A1, ZERO, 662
\r
1293 BFD01882 4B7E77E8 JALS vAssertCalled
\r
1294 BFD01884 4B7E LW K1, 120(SP)
\r
1296 663: ( void ) xResult;
\r
1300 667: mtCOVERAGE_TEST_MARKER();
\r
1305 672: mtCOVERAGE_TEST_MARKER();
\r
1308 BFD01888 CC3A B 0xBFD018FE
\r
1311 BFD018F2 CC05 B 0xBFD018FE
\r
1314 BFD018F8 CC02 B 0xBFD018FE
\r
1318 676: case tmrCOMMAND_STOP :
\r
1319 677: case tmrCOMMAND_STOP_FROM_ISR :
\r
1320 678: /* The timer has already been removed from the active list.
\r
1321 679: There is nothing to do here. */
\r
1324 BFD018EC CC08 B 0xBFD018FE
\r
1327 682: case tmrCOMMAND_CHANGE_PERIOD :
\r
1328 683: case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
\r
1329 684: pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
\r
1330 BFD0188C 002CFC7E LW V1, 44(S8)
\r
1331 BFD01890 001CFC5E LW V0, 28(S8)
\r
1332 BFD01894 E9A6 SW V1, 24(V0)
\r
1333 685: configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
\r
1334 BFD01896 001CFC5E LW V0, 28(S8)
\r
1335 BFD0189A 6926 LW V0, 24(V0)
\r
1336 BFD0189C 000940A2 BNEZC V0, 0xBFD018B2
\r
1337 BFD018A0 BFD141A2 LUI V0, 0xBFD1
\r
1338 BFD018A2 3082BFD1 LDC1 F30, 12418(S1)
\r
1339 BFD018A4 9AE83082 ADDIU A0, V0, -25880
\r
1340 BFD018A6 30A09AE8 SWC1 F23, 12448(T0)
\r
1341 BFD018A8 02AD30A0 ADDIU A1, ZERO, 685
\r
1342 BFD018AC 4B7E77E8 JALS vAssertCalled
\r
1343 BFD018AE 4B7E LW K1, 120(SP)
\r
1346 687: /* The new period does not really have a reference, and can be
\r
1347 688: longer or shorter than the old one. The command time is
\r
1348 689: therefore set to the current time, and as the period cannot be
\r
1349 690: zero the next expiry time can only be in the future, meaning
\r
1350 691: (unlike for the xTimerStart() case above) there is no fail case
\r
1351 692: that needs to be handled here. */
\r
1352 693: ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
\r
1353 BFD018B2 001CFC5E LW V0, 28(S8)
\r
1354 BFD018B6 69A6 LW V1, 24(V0)
\r
1355 BFD018B8 0020FC5E LW V0, 32(S8)
\r
1356 BFD018BC 0526 ADDU V0, V1, V0
\r
1357 BFD018BE 001CFC9E LW A0, 28(S8)
\r
1358 BFD018C2 0CA2 MOVE A1, V0
\r
1359 BFD018C4 0020FCDE LW A2, 32(S8)
\r
1360 BFD018C8 0020FCFE LW A3, 32(S8)
\r
1361 BFD018CC 2BE477E8 JALS prvInsertTimerInActiveList
\r
1362 BFD018CE 2BE4 LHU A3, 8(A2)
\r
1365 BFD018D2 CC15 B 0xBFD018FE
\r
1368 696: case tmrCOMMAND_DELETE :
\r
1369 697: /* The timer has already been removed from the active list,
\r
1370 698: just free up the memory. */
\r
1371 699: vPortFree( pxTimer );
\r
1372 BFD018D6 001CFC9E LW A0, 28(S8)
\r
1373 BFD018DA 2FEA77E8 JALS vPortFree
\r
1374 BFD018DC 2FEA ANDI A3, A2, 0x20
\r
1377 BFD018E0 CC0E B 0xBFD018FE
\r
1381 703: /* Don't expect to get here. */
\r
1384 BFD018E6 CC0B B 0xBFD018FE
\r
1390 BFD01918 0FBE MOVE SP, S8
\r
1391 BFD0191A 4BF1 LW RA, 68(SP)
\r
1392 BFD0191C 4BD0 LW S8, 64(SP)
\r
1393 BFD0191E 4C25 ADDIU SP, SP, 72
\r
1394 BFD01920 459F JR16 RA
\r
1396 709: /*-----------------------------------------------------------*/
\r
1398 711: static void prvSwitchTimerLists( void )
\r
1400 BFD03EF0 4FE5 ADDIU SP, SP, -56
\r
1401 BFD03EF2 CBED SW RA, 52(SP)
\r
1402 BFD03EF4 CBCC SW S8, 48(SP)
\r
1403 BFD03EF6 0FDD MOVE S8, SP
\r
1404 713: TickType_t xNextExpireTime, xReloadTime;
\r
1405 714: List_t *pxTemp;
\r
1406 715: Timer_t *pxTimer;
\r
1407 716: BaseType_t xResult;
\r
1409 718: /* The tick count has overflowed. The timer lists must be switched.
\r
1410 719: If there are any timers still referenced from the current timer list
\r
1411 720: then they must have expired and should be processed before the lists
\r
1412 721: are switched. */
\r
1413 722: while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
\r
1414 BFD03EF8 CC61 B 0xBFD03FBC
\r
1416 BFD03FBC 8060FC5C LW V0, -32672(GP)
\r
1417 BFD03FC0 6920 LW V0, 0(V0)
\r
1418 BFD03FC2 FF9B40A2 BNEZC V0, 0xBFD03EFC
\r
1419 BFD03FC4 FC5CFF9B LW GP, -932(K1)
\r
1421 724: xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
\r
1422 BFD03EFC 8060FC5C LW V0, -32672(GP)
\r
1423 BFD03F00 6923 LW V0, 12(V0)
\r
1424 BFD03F02 6920 LW V0, 0(V0)
\r
1425 BFD03F04 0018F85E SW V0, 24(S8)
\r
1427 726: /* Remove the timer from the list. */
\r
1428 727: pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
\r
1429 BFD03F08 8060FC5C LW V0, -32672(GP)
\r
1430 BFD03F0C 6923 LW V0, 12(V0)
\r
1431 BFD03F0E 6923 LW V0, 12(V0)
\r
1432 BFD03F10 001CF85E SW V0, 28(S8)
\r
1433 728: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
\r
1434 BFD03F14 001CFC5E LW V0, 28(S8)
\r
1435 BFD03F18 6D22 ADDIU V0, V0, 4
\r
1436 BFD03F1A 0C82 MOVE A0, V0
\r
1437 BFD03F1C 00C877E8 JALS uxListRemove
\r
1438 BFD03F1E 0C0000C8 SLL A2, T0, 1
\r
1440 729: traceTIMER_EXPIRED( pxTimer );
\r
1442 731: /* Execute its callback, then send a command to restart the timer if
\r
1443 732: it is an auto-reload timer. It cannot be restarted here as the lists
\r
1444 733: have not yet been switched. */
\r
1445 734: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
\r
1446 BFD03F22 001CFC5E LW V0, 28(S8)
\r
1447 BFD03F26 6929 LW V0, 36(V0)
\r
1448 BFD03F28 001CFC9E LW A0, 28(S8)
\r
1449 BFD03F2C 45E2 JALRS16 V0
\r
1452 736: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
\r
1453 BFD03F30 001CFC5E LW V0, 28(S8)
\r
1454 BFD03F34 69A7 LW V1, 28(V0)
\r
1455 BFD03F36 ED01 LI V0, 1
\r
1456 BFD03F38 0040B443 BNE V1, V0, 0xBFD03FBC
\r
1457 BFD03F3A 0C000040 SLL V0, ZERO, 1
\r
1460 738: /* Calculate the reload value, and if the reload value results in
\r
1461 739: the timer going into the same timer list then it has already expired
\r
1462 740: and the timer should be re-inserted into the current list so it is
\r
1463 741: processed again within this loop. Otherwise a command should be sent
\r
1464 742: to restart the timer to ensure it is only inserted into a list after
\r
1465 743: the lists have been swapped. */
\r
1466 744: xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
\r
1467 BFD03F3E 001CFC5E LW V0, 28(S8)
\r
1468 BFD03F42 69A6 LW V1, 24(V0)
\r
1469 BFD03F44 0018FC5E LW V0, 24(S8)
\r
1470 BFD03F48 0526 ADDU V0, V1, V0
\r
1471 BFD03F4A 0020F85E SW V0, 32(S8)
\r
1472 745: if( xReloadTime > xNextExpireTime )
\r
1473 BFD03F4E 0020FC7E LW V1, 32(S8)
\r
1474 BFD03F52 0018FC5E LW V0, 24(S8)
\r
1475 BFD03F56 13900062 SLTU V0, V0, V1
\r
1476 BFD03F58 40E21390 ADDI GP, S0, 16610
\r
1477 BFD03F5A 001640E2 BEQZC V0, 0xBFD03F8A
\r
1479 747: listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
\r
1480 BFD03F5E 001CFC5E LW V0, 28(S8)
\r
1481 BFD03F62 0020FC7E LW V1, 32(S8)
\r
1482 BFD03F66 E9A1 SW V1, 4(V0)
\r
1483 748: listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
\r
1484 BFD03F68 001CFC5E LW V0, 28(S8)
\r
1485 BFD03F6C 001CFC7E LW V1, 28(S8)
\r
1486 BFD03F70 E9A4 SW V1, 16(V0)
\r
1487 749: vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
\r
1488 BFD03F72 8060FC7C LW V1, -32672(GP)
\r
1489 BFD03F76 001CFC5E LW V0, 28(S8)
\r
1490 BFD03F7A 6D22 ADDIU V0, V0, 4
\r
1491 BFD03F7C 0C83 MOVE A0, V1
\r
1492 BFD03F7E 0CA2 MOVE A1, V0
\r
1493 BFD03F80 304077E8 JALS vListInsert
\r
1494 BFD03F82 0C003040 ADDIU V0, ZERO, 3072
\r
1496 BFD03F86 CC1A B 0xBFD03FBC
\r
1501 753: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
\r
1502 BFD03F8A C804 SW ZERO, 16(SP)
\r
1503 BFD03F8C 001CFC9E LW A0, 28(S8)
\r
1504 BFD03F90 0CA0 MOVE A1, ZERO
\r
1505 BFD03F92 0018FCDE LW A2, 24(S8)
\r
1506 BFD03F96 0CE0 MOVE A3, ZERO
\r
1507 BFD03F98 2D0E77E8 JALS xTimerGenericCommand
\r
1508 BFD03F9A 2D0E ANDI V0, S0, 0x8000
\r
1510 BFD03F9E 0024F85E SW V0, 36(S8)
\r
1511 754: configASSERT( xResult );
\r
1512 BFD03FA2 0024FC5E LW V0, 36(S8)
\r
1513 BFD03FA6 000940A2 BNEZC V0, 0xBFD03FBC
\r
1514 BFD03FAA BFD141A2 LUI V0, 0xBFD1
\r
1515 BFD03FAC 3082BFD1 LDC1 F30, 12418(S1)
\r
1516 BFD03FAE 9AE83082 ADDIU A0, V0, -25880
\r
1517 BFD03FB0 30A09AE8 SWC1 F23, 12448(T0)
\r
1518 BFD03FB2 02F230A0 ADDIU A1, ZERO, 754
\r
1519 BFD03FB6 4B7E77E8 JALS vAssertCalled
\r
1520 BFD03FB8 4B7E LW K1, 120(SP)
\r
1522 755: ( void ) xResult;
\r
1527 760: mtCOVERAGE_TEST_MARKER();
\r
1531 764: pxTemp = pxCurrentTimerList;
\r
1532 BFD03FC6 8060FC5C LW V0, -32672(GP)
\r
1533 BFD03FCA 0028F85E SW V0, 40(S8)
\r
1534 765: pxCurrentTimerList = pxOverflowTimerList;
\r
1535 BFD03FCE 8064FC5C LW V0, -32668(GP)
\r
1536 BFD03FD2 8060F85C SW V0, -32672(GP)
\r
1537 766: pxOverflowTimerList = pxTemp;
\r
1538 BFD03FD6 0028FC5E LW V0, 40(S8)
\r
1539 BFD03FDA 8064F85C SW V0, -32668(GP)
\r
1541 BFD03FDE 0FBE MOVE SP, S8
\r
1542 BFD03FE0 4BED LW RA, 52(SP)
\r
1543 BFD03FE2 4BCC LW S8, 48(SP)
\r
1544 BFD03FE4 4C1D ADDIU SP, SP, 56
\r
1545 BFD03FE6 459F JR16 RA
\r
1547 768: /*-----------------------------------------------------------*/
\r
1549 770: static void prvCheckForValidListAndQueue( void )
\r
1551 BFD06BE8 4FF5 ADDIU SP, SP, -24
\r
1552 BFD06BEA CBE5 SW RA, 20(SP)
\r
1553 BFD06BEC CBC4 SW S8, 16(SP)
\r
1554 BFD06BEE 0FDD MOVE S8, SP
\r
1555 772: /* Check that the list from which active timers are referenced, and the
\r
1556 773: queue used to communicate with the timer service, have been
\r
1557 774: initialised. */
\r
1558 775: taskENTER_CRITICAL();
\r
1559 BFD06BF0 33B877E8 JALS vTaskEnterCritical
\r
1560 BFD06BF2 0C0033B8 ADDIU SP, T8, 3072
\r
1563 777: if( xTimerQueue == NULL )
\r
1564 BFD06BF6 8068FC5C LW V0, -32664(GP)
\r
1565 BFD06BFA 002F40A2 BNEZC V0, 0xBFD06C5C
\r
1567 779: vListInitialise( &xActiveTimerList1 );
\r
1568 BFD06BFE BFD241A2 LUI V0, 0xBFD2
\r
1569 BFD06C00 3082BFD2 LDC1 F30, 12418(S2)
\r
1570 BFD06C02 B9483082 ADDIU A0, V0, -18104
\r
1571 BFD06C04 77E8B948 SDC1 F10, 30696(T0)
\r
1572 BFD06C06 457077E8 JALS vListInitialise
\r
1573 BFD06C08 4570 SWM16 0x3, 0(SP)
\r
1575 780: vListInitialise( &xActiveTimerList2 );
\r
1576 BFD06C0C BFD241A2 LUI V0, 0xBFD2
\r
1577 BFD06C0E 3082BFD2 LDC1 F30, 12418(S2)
\r
1578 BFD06C10 B95C3082 ADDIU A0, V0, -18084
\r
1579 BFD06C12 77E8B95C SDC1 F10, 30696(GP)
\r
1580 BFD06C14 457077E8 JALS vListInitialise
\r
1581 BFD06C16 4570 SWM16 0x3, 0(SP)
\r
1583 781: pxCurrentTimerList = &xActiveTimerList1;
\r
1584 BFD06C1A BFD241A2 LUI V0, 0xBFD2
\r
1585 BFD06C1C 3042BFD2 LDC1 F30, 12354(S2)
\r
1586 BFD06C1E B9483042 ADDIU V0, V0, -18104
\r
1587 BFD06C20 F85CB948 SDC1 F10, -1956(T0)
\r
1588 BFD06C22 8060F85C SW V0, -32672(GP)
\r
1589 782: pxOverflowTimerList = &xActiveTimerList2;
\r
1590 BFD06C26 BFD241A2 LUI V0, 0xBFD2
\r
1591 BFD06C28 3042BFD2 LDC1 F30, 12354(S2)
\r
1592 BFD06C2A B95C3042 ADDIU V0, V0, -18084
\r
1593 BFD06C2C F85CB95C SDC1 F10, -1956(GP)
\r
1594 BFD06C2E 8064F85C SW V0, -32668(GP)
\r
1595 783: xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
\r
1596 BFD06C32 EE05 LI A0, 5
\r
1597 BFD06C34 EE90 LI A1, 16
\r
1598 BFD06C36 0CC0 MOVE A2, ZERO
\r
1599 BFD06C38 1EFA77E8 JALS xQueueGenericCreate
\r
1600 BFD06C3A 0C001EFA LB S7, 3072(K0)
\r
1602 BFD06C3E 8068F85C SW V0, -32664(GP)
\r
1603 784: configASSERT( xTimerQueue );
\r
1604 BFD06C42 8068FC5C LW V0, -32664(GP)
\r
1605 BFD06C46 000940A2 BNEZC V0, 0xBFD06C5C
\r
1606 BFD06C4A BFD141A2 LUI V0, 0xBFD1
\r
1607 BFD06C4C 3082BFD1 LDC1 F30, 12418(S1)
\r
1608 BFD06C4E 9AE83082 ADDIU A0, V0, -25880
\r
1609 BFD06C50 30A09AE8 SWC1 F23, 12448(T0)
\r
1610 BFD06C52 031030A0 ADDIU A1, ZERO, 784
\r
1611 BFD06C56 4B7E77E8 JALS vAssertCalled
\r
1612 BFD06C58 4B7E LW K1, 120(SP)
\r
1615 786: #if ( configQUEUE_REGISTRY_SIZE > 0 )
\r
1617 788: if( xTimerQueue != NULL )
\r
1619 790: vQueueAddToRegistry( xTimerQueue, "TmrQ" );
\r
1623 794: mtCOVERAGE_TEST_MARKER();
\r
1626 797: #endif /* configQUEUE_REGISTRY_SIZE */
\r
1630 801: mtCOVERAGE_TEST_MARKER();
\r
1633 804: taskEXIT_CRITICAL();
\r
1634 BFD06C5C 40AA77E8 JALS vTaskExitCritical
\r
1635 BFD06C5E 0C0040AA BNEZC T2, 0xBFD08462
\r
1638 BFD06C62 0FBE MOVE SP, S8
\r
1639 BFD06C64 4BE5 LW RA, 20(SP)
\r
1640 BFD06C66 4BC4 LW S8, 16(SP)
\r
1641 BFD06C68 4C0D ADDIU SP, SP, 24
\r
1642 BFD06C6A 459F JR16 RA
\r
1644 806: /*-----------------------------------------------------------*/
\r
1646 808: BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
\r
1648 BFD093E0 4FF1 ADDIU SP, SP, -32
\r
1649 BFD093E2 CBE7 SW RA, 28(SP)
\r
1650 BFD093E4 CBC6 SW S8, 24(SP)
\r
1651 BFD093E6 0FDD MOVE S8, SP
\r
1652 BFD093E8 0020F89E SW A0, 32(S8)
\r
1653 810: BaseType_t xTimerIsInActiveList;
\r
1654 811: Timer_t *pxTimer = ( Timer_t * ) xTimer;
\r
1655 BFD093EC 0020FC5E LW V0, 32(S8)
\r
1656 BFD093F0 0010F85E SW V0, 16(S8)
\r
1658 813: /* Is the timer in the list of active timers? */
\r
1659 814: taskENTER_CRITICAL();
\r
1660 BFD093F4 33B877E8 JALS vTaskEnterCritical
\r
1661 BFD093F6 0C0033B8 ADDIU SP, T8, 3072
\r
1664 816: /* Checking to see if it is in the NULL list in effect checks to see if
\r
1665 817: it is referenced from either the current or the overflow timer lists in
\r
1666 818: one go, but the logic has to be reversed, hence the '!'. */
\r
1667 819: xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );
\r
1668 BFD093FA 0010FC5E LW V0, 16(S8)
\r
1669 BFD093FE 6925 LW V0, 20(V0)
\r
1670 BFD09400 13900040 SLTU V0, ZERO, V0
\r
1671 BFD09402 F85E1390 ADDI GP, S0, -1954
\r
1672 BFD09404 0014F85E SW V0, 20(S8)
\r
1674 821: taskEXIT_CRITICAL();
\r
1675 BFD09408 40AA77E8 JALS vTaskExitCritical
\r
1676 BFD0940A 0C0040AA BNEZC T2, 0xBFD0AC0E
\r
1679 823: return xTimerIsInActiveList;
\r
1680 BFD0940E 0014FC5E LW V0, 20(S8)
\r
1681 824: } /*lint !e818 Can't be pointer to const due to the typedef. */
\r
1682 BFD09412 0FBE MOVE SP, S8
\r
1683 BFD09414 4BE7 LW RA, 28(SP)
\r
1684 BFD09416 4BC6 LW S8, 24(SP)
\r
1685 BFD09418 4C11 ADDIU SP, SP, 32
\r
1686 BFD0941A 459F JR16 RA
\r
1688 825: /*-----------------------------------------------------------*/
\r
1690 827: void *pvTimerGetTimerID( const TimerHandle_t xTimer )
\r
1692 BFD0875C 4FF1 ADDIU SP, SP, -32
\r
1693 BFD0875E CBE7 SW RA, 28(SP)
\r
1694 BFD08760 CBC6 SW S8, 24(SP)
\r
1695 BFD08762 0FDD MOVE S8, SP
\r
1696 BFD08764 0020F89E SW A0, 32(S8)
\r
1697 829: Timer_t * const pxTimer = ( Timer_t * ) xTimer;
\r
1698 BFD08768 0020FC5E LW V0, 32(S8)
\r
1699 BFD0876C 0010F85E SW V0, 16(S8)
\r
1700 830: void *pvReturn;
\r
1702 832: configASSERT( xTimer );
\r
1703 BFD08770 0020FC5E LW V0, 32(S8)
\r
1704 BFD08774 000940A2 BNEZC V0, 0xBFD0878A
\r
1705 BFD08778 BFD141A2 LUI V0, 0xBFD1
\r
1706 BFD0877A 3082BFD1 LDC1 F30, 12418(S1)
\r
1707 BFD0877C 9AE83082 ADDIU A0, V0, -25880
\r
1708 BFD0877E 30A09AE8 SWC1 F23, 12448(T0)
\r
1709 BFD08780 034030A0 ADDIU A1, ZERO, 832
\r
1710 BFD08784 4B7E77E8 JALS vAssertCalled
\r
1711 BFD08786 4B7E LW K1, 120(SP)
\r
1714 834: taskENTER_CRITICAL();
\r
1715 BFD0878A 33B877E8 JALS vTaskEnterCritical
\r
1716 BFD0878C 0C0033B8 ADDIU SP, T8, 3072
\r
1719 836: pvReturn = pxTimer->pvTimerID;
\r
1720 BFD08790 0010FC5E LW V0, 16(S8)
\r
1721 BFD08794 6928 LW V0, 32(V0)
\r
1722 BFD08796 0014F85E SW V0, 20(S8)
\r
1724 838: taskEXIT_CRITICAL();
\r
1725 BFD0879A 40AA77E8 JALS vTaskExitCritical
\r
1726 BFD0879C 0C0040AA BNEZC T2, 0xBFD09FA0
\r
1729 840: return pvReturn;
\r
1730 BFD087A0 0014FC5E LW V0, 20(S8)
\r
1732 BFD087A4 0FBE MOVE SP, S8
\r
1733 BFD087A6 4BE7 LW RA, 28(SP)
\r
1734 BFD087A8 4BC6 LW S8, 24(SP)
\r
1735 BFD087AA 4C11 ADDIU SP, SP, 32
\r
1736 BFD087AC 459F JR16 RA
\r
1738 842: /*-----------------------------------------------------------*/
\r
1740 844: void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
\r
1742 BFD087B0 4FF1 ADDIU SP, SP, -32
\r
1743 BFD087B2 CBE7 SW RA, 28(SP)
\r
1744 BFD087B4 CBC6 SW S8, 24(SP)
\r
1745 BFD087B6 0FDD MOVE S8, SP
\r
1746 BFD087B8 0020F89E SW A0, 32(S8)
\r
1747 BFD087BC 0024F8BE SW A1, 36(S8)
\r
1748 846: Timer_t * const pxTimer = ( Timer_t * ) xTimer;
\r
1749 BFD087C0 0020FC5E LW V0, 32(S8)
\r
1750 BFD087C4 0010F85E SW V0, 16(S8)
\r
1752 848: configASSERT( xTimer );
\r
1753 BFD087C8 0020FC5E LW V0, 32(S8)
\r
1754 BFD087CC 000940A2 BNEZC V0, 0xBFD087E2
\r
1755 BFD087D0 BFD141A2 LUI V0, 0xBFD1
\r
1756 BFD087D2 3082BFD1 LDC1 F30, 12418(S1)
\r
1757 BFD087D4 9AE83082 ADDIU A0, V0, -25880
\r
1758 BFD087D6 30A09AE8 SWC1 F23, 12448(T0)
\r
1759 BFD087D8 035030A0 ADDIU A1, ZERO, 848
\r
1760 BFD087DC 4B7E77E8 JALS vAssertCalled
\r
1761 BFD087DE 4B7E LW K1, 120(SP)
\r
1764 850: taskENTER_CRITICAL();
\r
1765 BFD087E2 33B877E8 JALS vTaskEnterCritical
\r
1766 BFD087E4 0C0033B8 ADDIU SP, T8, 3072
\r
1769 852: pxTimer->pvTimerID = pvNewID;
\r
1770 BFD087E8 0010FC5E LW V0, 16(S8)
\r
1771 BFD087EC 0024FC7E LW V1, 36(S8)
\r
1772 BFD087F0 E9A8 SW V1, 32(V0)
\r
1774 854: taskEXIT_CRITICAL();
\r
1775 BFD087F2 40AA77E8 JALS vTaskExitCritical
\r
1776 BFD087F4 0C0040AA BNEZC T2, 0xBFD09FF8
\r
1779 BFD087F8 0FBE MOVE SP, S8
\r
1780 BFD087FA 4BE7 LW RA, 28(SP)
\r
1781 BFD087FC 4BC6 LW S8, 24(SP)
\r
1782 BFD087FE 4C11 ADDIU SP, SP, 32
\r
1783 BFD08800 459F JR16 RA
\r
1785 856: /*-----------------------------------------------------------*/
\r
1787 858: #if( INCLUDE_xTimerPendFunctionCall == 1 )
\r
1789 860: BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
\r
1791 BFD07F64 4FE9 ADDIU SP, SP, -48
\r
1792 BFD07F66 CBEB SW RA, 44(SP)
\r
1793 BFD07F68 CBCA SW S8, 40(SP)
\r
1794 BFD07F6A 0FDD MOVE S8, SP
\r
1795 BFD07F6C 0030F89E SW A0, 48(S8)
\r
1796 BFD07F70 0034F8BE SW A1, 52(S8)
\r
1797 BFD07F74 0038F8DE SW A2, 56(S8)
\r
1798 BFD07F78 003CF8FE SW A3, 60(S8)
\r
1799 BFD07F7A 3040003C SRL AT, GP, 6
\r
1800 862: DaemonTaskMessage_t xMessage;
\r
1801 863: BaseType_t xReturn;
\r
1803 865: /* Complete the message with the function parameters and post it to the
\r
1804 866: daemon task. */
\r
1805 867: xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
\r
1806 BFD07F7C FFFE3040 ADDIU V0, ZERO, -2
\r
1807 BFD07F7E F85EFFFE LW RA, -1954(S8)
\r
1808 BFD07F80 0014F85E SW V0, 20(S8)
\r
1809 868: xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
\r
1810 BFD07F84 0030FC5E LW V0, 48(S8)
\r
1811 BFD07F88 0018F85E SW V0, 24(S8)
\r
1812 869: xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
\r
1813 BFD07F8C 0034FC5E LW V0, 52(S8)
\r
1814 BFD07F90 001CF85E SW V0, 28(S8)
\r
1815 870: xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
\r
1816 BFD07F94 0038FC5E LW V0, 56(S8)
\r
1817 BFD07F98 0020F85E SW V0, 32(S8)
\r
1819 872: xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
\r
1820 BFD07F9C 8068FC7C LW V1, -32664(GP)
\r
1821 BFD07FA0 0014305E ADDIU V0, S8, 20
\r
1822 BFD07FA4 0C83 MOVE A0, V1
\r
1823 BFD07FA6 0CA2 MOVE A1, V0
\r
1824 BFD07FA8 003CFCDE LW A2, 60(S8)
\r
1825 BFD07FAC 0CE0 MOVE A3, ZERO
\r
1826 BFD07FAE 11EA77E8 JALS xQueueGenericSendFromISR
\r
1827 BFD07FB0 0C0011EA ADDI T7, T2, 3072
\r
1829 BFD07FB4 0010F85E SW V0, 16(S8)
\r
1831 874: tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
\r
1833 876: return xReturn;
\r
1834 BFD07FB8 0010FC5E LW V0, 16(S8)
\r
1836 BFD07FBC 0FBE MOVE SP, S8
\r
1837 BFD07FBE 4BEB LW RA, 44(SP)
\r
1838 BFD07FC0 4BCA LW S8, 40(SP)
\r
1839 BFD07FC2 4C19 ADDIU SP, SP, 48
\r
1840 BFD07FC4 459F JR16 RA
\r
1843 879: #endif /* INCLUDE_xTimerPendFunctionCall */
\r
1844 880: /*-----------------------------------------------------------*/
\r
1846 882: #if( INCLUDE_xTimerPendFunctionCall == 1 )
\r
1848 884: BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
\r
1850 BFD06D70 4FE9 ADDIU SP, SP, -48
\r
1851 BFD06D72 CBEB SW RA, 44(SP)
\r
1852 BFD06D74 CBCA SW S8, 40(SP)
\r
1853 BFD06D76 0FDD MOVE S8, SP
\r
1854 BFD06D78 0030F89E SW A0, 48(S8)
\r
1855 BFD06D7C 0034F8BE SW A1, 52(S8)
\r
1856 BFD06D80 0038F8DE SW A2, 56(S8)
\r
1857 BFD06D84 003CF8FE SW A3, 60(S8)
\r
1858 886: DaemonTaskMessage_t xMessage;
\r
1859 887: BaseType_t xReturn;
\r
1861 889: /* This function can only be called after a timer has been created or
\r
1862 890: after the scheduler has been started because, until then, the timer
\r
1863 891: queue does not exist. */
\r
1864 892: configASSERT( xTimerQueue );
\r
1865 BFD06D88 8068FC5C LW V0, -32664(GP)
\r
1866 BFD06D8C 000940A2 BNEZC V0, 0xBFD06DA2
\r
1867 BFD06D90 BFD141A2 LUI V0, 0xBFD1
\r
1868 BFD06D92 3082BFD1 LDC1 F30, 12418(S1)
\r
1869 BFD06D94 9AE83082 ADDIU A0, V0, -25880
\r
1870 BFD06D96 30A09AE8 SWC1 F23, 12448(T0)
\r
1871 BFD06D98 037C30A0 ADDIU A1, ZERO, 892
\r
1872 BFD06D9C 4B7E77E8 JALS vAssertCalled
\r
1873 BFD06D9E 4B7E LW K1, 120(SP)
\r
1876 894: /* Complete the message with the function parameters and post it to the
\r
1877 895: daemon task. */
\r
1878 896: xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
\r
1879 BFD06DA2 ED7F LI V0, -1
\r
1880 BFD06DA4 0014F85E SW V0, 20(S8)
\r
1881 897: xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
\r
1882 BFD06DA8 0030FC5E LW V0, 48(S8)
\r
1883 BFD06DAC 0018F85E SW V0, 24(S8)
\r
1884 898: xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
\r
1885 BFD06DB0 0034FC5E LW V0, 52(S8)
\r
1886 BFD06DB4 001CF85E SW V0, 28(S8)
\r
1887 899: xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
\r
1888 BFD06DB8 0038FC5E LW V0, 56(S8)
\r
1889 BFD06DBC 0020F85E SW V0, 32(S8)
\r
1891 901: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
\r
1892 BFD06DC0 8068FC7C LW V1, -32664(GP)
\r
1893 BFD06DC4 0014305E ADDIU V0, S8, 20
\r
1894 BFD06DC8 0C83 MOVE A0, V1
\r
1895 BFD06DCA 0CA2 MOVE A1, V0
\r
1896 BFD06DCC 003CFCDE LW A2, 60(S8)
\r
1897 BFD06DD0 0CE0 MOVE A3, ZERO
\r
1898 BFD06DD2 06A277E8 JALS xQueueGenericSend
\r
1899 BFD06DD4 06A2 ADDU A1, S1, V0
\r
1901 BFD06DD8 0010F85E SW V0, 16(S8)
\r
1903 903: tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
\r
1905 905: return xReturn;
\r
1906 BFD06DDC 0010FC5E LW V0, 16(S8)
\r
1908 BFD06DE0 0FBE MOVE SP, S8
\r
1909 BFD06DE2 4BEB LW RA, 44(SP)
\r
1910 BFD06DE4 4BCA LW S8, 40(SP)
\r
1911 BFD06DE6 4C19 ADDIU SP, SP, 48
\r
1912 BFD06DE8 459F JR16 RA
\r
1915 908: #endif /* INCLUDE_xTimerPendFunctionCall */
\r
1916 909: /*-----------------------------------------------------------*/
\r
1918 911: /* This entire source file will be skipped if the application is not configured
\r
1919 912: to include software timer functionality. If you want to include software timer
\r
1920 913: functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
\r
1921 914: #endif /* configUSE_TIMERS == 1 */
\r
1925 --- c:/e/dev/freertos/workingcopy/freertos/source/tasks.c ---------------------------------------------
\r
1927 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
1928 3: All rights reserved
\r
1930 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
1932 7: This file is part of the FreeRTOS distribution.
\r
1934 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
1935 10: the terms of the GNU General Public License (version 2) as published by the
\r
1936 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
1938 13: ***************************************************************************
\r
1939 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
1940 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
1941 16: >>! obliged to provide the source code for proprietary components !<<
\r
1942 17: >>! outside of the FreeRTOS kernel. !<<
\r
1943 18: ***************************************************************************
\r
1945 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
1946 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
1947 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
1948 23: link: http://www.freertos.org/a00114.html
\r
1950 25: ***************************************************************************
\r
1952 27: * FreeRTOS provides completely free yet professionally developed, *
\r
1953 28: * robust, strictly quality controlled, supported, and cross *
\r
1954 29: * platform software that is more than just the market leader, it *
\r
1955 30: * is the industry's de facto standard. *
\r
1957 32: * Help yourself get started quickly while simultaneously helping *
\r
1958 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
1959 34: * tutorial book, reference manual, or both: *
\r
1960 35: * http://www.FreeRTOS.org/Documentation *
\r
1962 37: ***************************************************************************
\r
1964 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
1965 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
1966 41: defined configASSERT()?
\r
1968 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
1969 44: embedded software for free we request you assist our global community by
\r
1970 45: participating in the support forum.
\r
1972 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
1973 48: be as productive as possible as early as possible. Now you can receive
\r
1974 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
1975 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
1977 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
1978 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
1979 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
1981 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
1982 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
1984 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
1985 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
1986 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
1988 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
1989 64: engineered and independently SIL3 certified version for use in safety and
\r
1990 65: mission critical applications that require provable dependability.
\r
1992 67: 1 tab == 4 spaces!
\r
1995 70: /* Standard includes. */
\r
1996 71: #include <stdlib.h>
\r
1997 72: #include <string.h>
\r
1999 74: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
\r
2000 75: all the API functions to use the MPU wrappers. That should only be done when
\r
2001 76: task.h is included from an application file. */
\r
2002 77: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
\r
2004 79: /* FreeRTOS includes. */
\r
2005 80: #include "FreeRTOS.h"
\r
2006 81: #include "task.h"
\r
2007 82: #include "timers.h"
\r
2008 83: #include "StackMacros.h"
\r
2010 85: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the
\r
2011 86: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
\r
2012 87: header files above, but not in this file, in order to generate the correct
\r
2013 88: privileged Vs unprivileged linkage and placement. */
\r
2014 89: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
\r
2016 91: /* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
\r
2017 92: functions but without including stdio.h here. */
\r
2018 93: #if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
\r
2019 94: /* At the bottom of this file are two optional functions that can be used
\r
2020 95: to generate human readable text from the raw data generated by the
\r
2021 96: uxTaskGetSystemState() function. Note the formatting functions are provided
\r
2022 97: for convenience only, and are NOT considered part of the kernel. */
\r
2023 98: #include <stdio.h>
\r
2024 99: #endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
\r
2026 101: /* Sanity check the configuration. */
\r
2027 102: #if( configUSE_TICKLESS_IDLE != 0 )
\r
2028 103: #if( INCLUDE_vTaskSuspend != 1 )
\r
2029 104: #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
\r
2030 105: #endif /* INCLUDE_vTaskSuspend */
\r
2031 106: #endif /* configUSE_TICKLESS_IDLE */
\r
2034 109: * Defines the size, in words, of the stack allocated to the idle task.
\r
2036 111: #define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE
\r
2038 113: #if( configUSE_PREEMPTION == 0 )
\r
2039 114: /* If the cooperative scheduler is being used then a yield should not be
\r
2040 115: performed just because a higher priority task has been woken. */
\r
2041 116: #define taskYIELD_IF_USING_PREEMPTION()
\r
2043 118: #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
\r
2046 121: /* Value that can be assigned to the eNotifyState member of the TCB. */
\r
2049 124: eNotWaitingNotification = 0,
\r
2050 125: eWaitingNotification,
\r
2052 127: } eNotifyValue;
\r
2055 130: * Task control block. A task control block (TCB) is allocated for each task,
\r
2056 131: * and stores task state information, including a pointer to the task's context
\r
2057 132: * (the task's run time environment, including register values)
\r
2059 134: typedef struct tskTaskControlBlock
\r
2061 136: volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
\r
2063 138: #if ( portUSING_MPU_WRAPPERS == 1 )
\r
2064 139: xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
\r
2065 140: BaseType_t xUsingStaticallyAllocatedStack; /* Set to pdTRUE if the stack is a statically allocated array, and pdFALSE if the stack is dynamically allocated. */
\r
2068 143: ListItem_t xGenericListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
\r
2069 144: ListItem_t xEventListItem; /*< Used to reference a task from an event list. */
\r
2070 145: UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */
\r
2071 146: StackType_t *pxStack; /*< Points to the start of the stack. */
\r
2072 147: char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
\r
2074 149: #if ( portSTACK_GROWTH > 0 )
\r
2075 150: StackType_t *pxEndOfStack; /*< Points to the end of the stack on architectures where the stack grows up from low memory. */
\r
2078 153: #if ( portCRITICAL_NESTING_IN_TCB == 1 )
\r
2079 154: UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
\r
2082 157: #if ( configUSE_TRACE_FACILITY == 1 )
\r
2083 158: UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */
\r
2084 159: UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
\r
2087 162: #if ( configUSE_MUTEXES == 1 )
\r
2088 163: UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
\r
2089 164: UBaseType_t uxMutexesHeld;
\r
2092 167: #if ( configUSE_APPLICATION_TASK_TAG == 1 )
\r
2093 168: TaskHookFunction_t pxTaskTag;
\r
2096 171: #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
\r
2097 172: void *pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
\r
2100 175: #if ( configGENERATE_RUN_TIME_STATS == 1 )
\r
2101 176: uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
\r
2104 179: #if ( configUSE_NEWLIB_REENTRANT == 1 )
\r
2105 180: /* Allocate a Newlib reent structure that is specific to this task.
\r
2106 181: Note Newlib support has been included by popular demand, but is not
\r
2107 182: used by the FreeRTOS maintainers themselves. FreeRTOS is not
\r
2108 183: responsible for resulting newlib operation. User must be familiar with
\r
2109 184: newlib and must provide system-wide implementations of the necessary
\r
2110 185: stubs. Be warned that (at the time of writing) the current newlib design
\r
2111 186: implements a system-wide malloc() that must be provided with locks. */
\r
2112 187: struct _reent xNewLib_reent;
\r
2115 190: #if ( configUSE_TASK_NOTIFICATIONS == 1 )
\r
2116 191: volatile uint32_t ulNotifiedValue;
\r
2117 192: volatile eNotifyValue eNotifyState;
\r
2122 197: /* The old tskTCB name is maintained above then typedefed to the new TCB_t name
\r
2123 198: below to enable the use of older kernel aware debuggers. */
\r
2124 199: typedef tskTCB TCB_t;
\r
2127 202: * Some kernel aware debuggers require the data the debugger needs access to to
\r
2128 203: * be global, rather than file scope.
\r
2130 205: #ifdef portREMOVE_STATIC_QUALIFIER
\r
2131 206: #define static
\r
2134 209: /*lint -e956 A manual analysis and inspection has been used to determine which
\r
2135 210: static variables must be declared volatile. */
\r
2137 212: PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
\r
2139 214: /* Lists for ready and blocked tasks. --------------------*/
\r
2140 215: PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
\r
2141 216: PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */
\r
2142 217: PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
\r
2143 218: PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */
\r
2144 219: PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
\r
2145 220: PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */
\r
2147 222: #if ( INCLUDE_vTaskDelete == 1 )
\r
2149 224: PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */
\r
2150 225: PRIVILEGED_DATA static volatile UBaseType_t uxTasksDeleted = ( UBaseType_t ) 0U;
\r
2154 229: #if ( INCLUDE_vTaskSuspend == 1 )
\r
2156 231: PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */
\r
2160 235: #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
\r
2162 237: PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */
\r
2166 241: /* Other file private variables. --------------------------------*/
\r
2167 242: PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
\r
2168 243: PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) 0U;
\r
2169 244: PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
\r
2170 245: PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
\r
2171 246: PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0U;
\r
2172 247: PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
\r
2173 248: PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
\r
2174 249: PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
\r
2175 250: PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY; before the scheduler starts. */
\r
2177 252: /* Context switches are held pending while the scheduler is suspended. Also,
\r
2178 253: interrupts must not manipulate the xGenericListItem of a TCB, or any of the
\r
2179 254: lists the xGenericListItem can be referenced from, if the scheduler is suspended.
\r
2180 255: If an interrupt needs to unblock a task while the scheduler is suspended then it
\r
2181 256: moves the task's event list item into the xPendingReadyList, ready for the
\r
2182 257: kernel to move the task from the pending ready list into the real ready list
\r
2183 258: when the scheduler is unsuspended. The pending ready list itself can only be
\r
2184 259: accessed from a critical section. */
\r
2185 260: PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE;
\r
2187 262: #if ( configGENERATE_RUN_TIME_STATS == 1 )
\r
2189 264: PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */
\r
2190 265: PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */
\r
2194 269: /*lint +e956 */
\r
2196 271: /* Debugging and trace facilities private variables and macros. ------------*/
\r
2199 274: * The value used to fill the stack of a task when the task is created. This
\r
2200 275: * is used purely for checking the high water mark for tasks.
\r
2202 277: #define tskSTACK_FILL_BYTE ( 0xa5U )
\r
2205 280: * Macros used by vListTask to indicate which state a task is in.
\r
2207 282: #define tskBLOCKED_CHAR ( 'B' )
\r
2208 283: #define tskREADY_CHAR ( 'R' )
\r
2209 284: #define tskDELETED_CHAR ( 'D' )
\r
2210 285: #define tskSUSPENDED_CHAR ( 'S' )
\r
2212 287: /*-----------------------------------------------------------*/
\r
2214 289: #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
\r
2216 291: /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
\r
2217 292: performed in a generic way that is not optimised to any particular
\r
2218 293: microcontroller architecture. */
\r
2220 295: /* uxTopReadyPriority holds the priority of the highest priority ready
\r
2221 296: state task. */
\r
2222 297: #define taskRECORD_READY_PRIORITY( uxPriority ) \
\r
2224 299: if( ( uxPriority ) > uxTopReadyPriority ) \
\r
2226 301: uxTopReadyPriority = ( uxPriority ); \
\r
2228 303: } /* taskRECORD_READY_PRIORITY */
\r
2230 305: /*-----------------------------------------------------------*/
\r
2232 307: #define taskSELECT_HIGHEST_PRIORITY_TASK() \
\r
2234 309: /* Find the highest priority queue that contains ready tasks. */ \
\r
2235 310: while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) \
\r
2237 312: configASSERT( uxTopReadyPriority ); \
\r
2238 313: --uxTopReadyPriority; \
\r
2241 316: /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
\r
2242 317: the same priority get an equal share of the processor time. */ \
\r
2243 318: listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); \
\r
2244 319: } /* taskSELECT_HIGHEST_PRIORITY_TASK */
\r
2246 321: /*-----------------------------------------------------------*/
\r
2248 323: /* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
\r
2249 324: they are only required when a port optimised method of task selection is
\r
2250 325: being used. */
\r
2251 326: #define taskRESET_READY_PRIORITY( uxPriority )
\r
2252 327: #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
\r
2254 329: #else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
\r
2256 331: /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
\r
2257 332: performed in a way that is tailored to the particular microcontroller
\r
2258 333: architecture being used. */
\r
2260 335: /* A port optimised version is provided. Call the port defined macros. */
\r
2261 336: #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
\r
2263 338: /*-----------------------------------------------------------*/
\r
2265 340: #define taskSELECT_HIGHEST_PRIORITY_TASK() \
\r
2267 342: UBaseType_t uxTopPriority; \
\r
2269 344: /* Find the highest priority queue that contains ready tasks. */ \
\r
2270 345: portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \
\r
2271 346: configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
\r
2272 347: listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
\r
2273 348: } /* taskSELECT_HIGHEST_PRIORITY_TASK() */
\r
2275 350: /*-----------------------------------------------------------*/
\r
2277 352: /* A port optimised version is provided, call it only if the TCB being reset
\r
2278 353: is being referenced from a ready list. If it is referenced from a delayed
\r
2279 354: or suspended list then it won't be in a ready list. */
\r
2280 355: #define taskRESET_READY_PRIORITY( uxPriority ) \
\r
2282 357: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \
\r
2284 359: portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \
\r
2288 363: #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
\r
2290 365: /*-----------------------------------------------------------*/
\r
2292 367: /* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
\r
2293 368: count overflows. */
\r
2294 369: #define taskSWITCH_DELAYED_LISTS() \
\r
2296 371: List_t *pxTemp; \
\r
2298 373: /* The delayed tasks list should be empty when the lists are switched. */ \
\r
2299 374: configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \
\r
2301 376: pxTemp = pxDelayedTaskList; \
\r
2302 377: pxDelayedTaskList = pxOverflowDelayedTaskList; \
\r
2303 378: pxOverflowDelayedTaskList = pxTemp; \
\r
2304 379: xNumOfOverflows++; \
\r
2305 380: prvResetNextTaskUnblockTime(); \
\r
2308 383: /*-----------------------------------------------------------*/
\r
2311 386: * Place the task represented by pxTCB into the appropriate ready list for
\r
2312 387: * the task. It is inserted at the end of the list.
\r
2314 389: #define prvAddTaskToReadyList( pxTCB ) \
\r
2315 390: traceMOVED_TASK_TO_READY_STATE( pxTCB ); \
\r
2316 391: taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \
\r
2317 392: vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )
\r
2318 393: /*-----------------------------------------------------------*/
\r
2321 396: * Several functions take an TaskHandle_t parameter that can optionally be NULL,
\r
2322 397: * where NULL is used to indicate that the handle of the currently executing
\r
2323 398: * task should be used in place of the parameter. This macro simply checks to
\r
2324 399: * see if the parameter is NULL and returns a pointer to the appropriate TCB.
\r
2326 401: #define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
\r
2328 403: /* The item value of the event list item is normally used to hold the priority
\r
2329 404: of the task to which it belongs (coded to allow it to be held in reverse
\r
2330 405: priority order). However, it is occasionally borrowed for other purposes. It
\r
2331 406: is important its value is not updated due to a task priority change while it is
\r
2332 407: being used for another purpose. The following bit definition is used to inform
\r
2333 408: the scheduler that the value should not be changed - in which case it is the
\r
2334 409: responsibility of whichever module is using the value to ensure it gets set back
\r
2335 410: to its original value when it is released. */
\r
2336 411: #if configUSE_16_BIT_TICKS == 1
\r
2337 412: #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U
\r
2339 414: #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL
\r
2342 417: /* Callback function prototypes. --------------------------*/
\r
2343 418: #if configCHECK_FOR_STACK_OVERFLOW > 0
\r
2344 419: extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
\r
2347 422: #if configUSE_TICK_HOOK > 0
\r
2348 423: extern void vApplicationTickHook( void );
\r
2351 426: /* File private functions. --------------------------------*/
\r
2354 429: * Utility to ready a TCB for a given task. Mainly just copies the parameters
\r
2355 430: * into the TCB structure.
\r
2357 432: static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
\r
2360 435: * Utility task that simply returns pdTRUE if the task referenced by xTask is
\r
2361 436: * currently in the Suspended state, or pdFALSE if the task referenced by xTask
\r
2362 437: * is in any other state.
\r
2364 439: #if ( INCLUDE_vTaskSuspend == 1 )
\r
2365 440: static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
\r
2366 441: #endif /* INCLUDE_vTaskSuspend */
\r
2369 444: * Utility to ready all the lists used by the scheduler. This is called
\r
2370 445: * automatically upon the creation of the first task.
\r
2372 447: static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
\r
2375 450: * The idle task, which as all tasks is implemented as a never ending loop.
\r
2376 451: * The idle task is automatically created and added to the ready lists upon
\r
2377 452: * creation of the first user task.
\r
2379 454: * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
\r
2380 455: * language extensions. The equivalent prototype for this function is:
\r
2382 457: * void prvIdleTask( void *pvParameters );
\r
2385 460: static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
\r
2388 463: * Utility to free all memory allocated by the scheduler to hold a TCB,
\r
2389 464: * including the stack pointed to by the TCB.
\r
2391 466: * This does not free memory allocated by the task itself (i.e. memory
\r
2392 467: * allocated by calls to pvPortMalloc from within the tasks application code).
\r
2394 469: #if ( INCLUDE_vTaskDelete == 1 )
\r
2396 471: static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
\r
2401 476: * Used only by the idle task. This checks to see if anything has been placed
\r
2402 477: * in the list of tasks waiting to be deleted. If so the task is cleaned up
\r
2403 478: * and its TCB deleted.
\r
2405 480: static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
\r
2408 483: * The currently executing task is entering the Blocked state. Add the task to
\r
2409 484: * either the current or the overflow delayed task list.
\r
2411 486: static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake ) PRIVILEGED_FUNCTION;
\r
2414 489: * Allocates memory from the heap for a TCB and associated stack. Checks the
\r
2415 490: * allocation was successful.
\r
2417 492: static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer ) PRIVILEGED_FUNCTION;
\r
2420 495: * Fills an TaskStatus_t structure with information on each task that is
\r
2421 496: * referenced from the pxList list (which may be a ready list, a delayed list,
\r
2422 497: * a suspended list, etc.).
\r
2424 499: * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
\r
2425 500: * NORMAL APPLICATION CODE.
\r
2427 502: #if ( configUSE_TRACE_FACILITY == 1 )
\r
2429 504: static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
\r
2434 509: * When a task is created, the stack of the task is filled with a known value.
\r
2435 510: * This function determines the 'high water mark' of the task stack by
\r
2436 511: * determining how much of the stack remains at the original preset value.
\r
2438 513: #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
\r
2440 515: static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
\r
2445 520: * Return the amount of time, in ticks, that will pass before the kernel will
\r
2446 521: * next move a task from the Blocked state to the Running state.
\r
2448 523: * This conditional compilation should use inequality to 0, not equality to 1.
\r
2449 524: * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
\r
2450 525: * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
\r
2451 526: * set to a value other than 1.
\r
2453 528: #if ( configUSE_TICKLESS_IDLE != 0 )
\r
2455 530: static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
\r
2460 535: * Set xNextTaskUnblockTime to the time at which the next Blocked state task
\r
2461 536: * will exit the Blocked state.
\r
2463 538: static void prvResetNextTaskUnblockTime( void );
\r
2465 540: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
\r
2468 543: * Helper function used to pad task names with spaces when printing out
\r
2469 544: * human readable tables of task information.
\r
2471 546: static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName );
\r
2474 549: /*-----------------------------------------------------------*/
\r
2476 551: BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
\r
2478 BFD01534 4FE9 ADDIU SP, SP, -48
\r
2479 BFD01536 CBEB SW RA, 44(SP)
\r
2480 BFD01538 CBCA SW S8, 40(SP)
\r
2481 BFD0153A 0FDD MOVE S8, SP
\r
2482 BFD0153C 0030F89E SW A0, 48(S8)
\r
2483 BFD01540 0034F8BE SW A1, 52(S8)
\r
2484 BFD01544 0C46 MOVE V0, A2
\r
2485 BFD01546 003CF8FE SW A3, 60(S8)
\r
2486 BFD0154A 0038385E SH V0, 56(S8)
\r
2487 553: BaseType_t xReturn;
\r
2488 554: TCB_t * pxNewTCB;
\r
2489 555: StackType_t *pxTopOfStack;
\r
2491 557: configASSERT( pxTaskCode );
\r
2492 BFD0154E 0030FC5E LW V0, 48(S8)
\r
2493 BFD01552 000940A2 BNEZC V0, 0xBFD01568
\r
2494 BFD01556 BFD141A2 LUI V0, 0xBFD1
\r
2495 BFD01558 3082BFD1 LDC1 F30, 12418(S1)
\r
2496 BFD0155A 98103082 ADDIU A0, V0, -26608
\r
2497 BFD0155C 30A09810 SWC1 F0, 12448(S0)
\r
2498 BFD0155E 022D30A0 ADDIU A1, ZERO, 557
\r
2499 BFD01562 4B7E77E8 JALS vAssertCalled
\r
2500 BFD01564 4B7E LW K1, 120(SP)
\r
2502 558: configASSERT( ( ( uxPriority & ( UBaseType_t ) ( ~portPRIVILEGE_BIT ) ) < ( UBaseType_t ) configMAX_PRIORITIES ) );
\r
2503 BFD01568 0040FC5E LW V0, 64(S8)
\r
2504 BFD0156C 0005B042 SLTIU V0, V0, 5
\r
2505 BFD01570 000940A2 BNEZC V0, 0xBFD01586
\r
2506 BFD01574 BFD141A2 LUI V0, 0xBFD1
\r
2507 BFD01576 3082BFD1 LDC1 F30, 12418(S1)
\r
2508 BFD01578 98103082 ADDIU A0, V0, -26608
\r
2509 BFD0157A 30A09810 SWC1 F0, 12448(S0)
\r
2510 BFD0157C 022E30A0 ADDIU A1, ZERO, 558
\r
2511 BFD01580 4B7E77E8 JALS vAssertCalled
\r
2512 BFD01582 4B7E LW K1, 120(SP)
\r
2515 560: /* Allocate the memory required by the TCB and stack for the new task,
\r
2516 561: checking that the allocation was successful. */
\r
2517 562: pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );
\r
2518 BFD01586 0038345E LHU V0, 56(S8)
\r
2519 BFD0158A 0C82 MOVE A0, V0
\r
2520 BFD0158C 0048FCBE LW A1, 72(S8)
\r
2521 BFD01590 319477E8 JALS prvAllocateTCBAndStack
\r
2522 BFD01592 0C003194 ADDIU T4, S4, 3072
\r
2524 BFD01596 001CF85E SW V0, 28(S8)
\r
2526 564: if( pxNewTCB != NULL )
\r
2527 BFD0159A 001CFC5E LW V0, 28(S8)
\r
2528 BFD0159E 009A40E2 BEQZC V0, 0xBFD016D6
\r
2530 566: #if( portUSING_MPU_WRAPPERS == 1 )
\r
2531 567: /* Should the task be created in privileged mode? */
\r
2532 568: BaseType_t xRunPrivileged;
\r
2533 569: if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
\r
2535 571: xRunPrivileged = pdTRUE;
\r
2539 575: xRunPrivileged = pdFALSE;
\r
2541 577: uxPriority &= ~portPRIVILEGE_BIT;
\r
2543 579: if( puxStackBuffer != NULL )
\r
2545 581: /* The application provided its own stack. Note this so no
\r
2546 582: attempt is made to delete the stack should that task be
\r
2548 584: pxNewTCB->xUsingStaticallyAllocatedStack = pdTRUE;
\r
2552 588: /* The stack was allocated dynamically. Note this so it can be
\r
2553 589: deleted again if the task is deleted. */
\r
2554 590: pxNewTCB->xUsingStaticallyAllocatedStack = pdFALSE;
\r
2556 592: #endif /* portUSING_MPU_WRAPPERS == 1 */
\r
2558 594: /* Calculate the top of stack address. This depends on whether the
\r
2559 595: stack grows from high memory to low (as per the 80x86) or vice versa.
\r
2560 596: portSTACK_GROWTH is used to make the result positive or negative as
\r
2561 597: required by the port. */
\r
2562 598: #if( portSTACK_GROWTH < 0 )
\r
2564 600: pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( uint16_t ) 1 );
\r
2565 BFD015A2 001CFC5E LW V0, 28(S8)
\r
2566 BFD015A4 69AC001C EXT ZERO, GP, 6, 14
\r
2567 BFD015A6 69AC LW V1, 48(V0)
\r
2568 BFD015A8 0038345E LHU V0, 56(S8)
\r
2569 BFD015AC 6D2E ADDIU V0, V0, -1
\r
2570 BFD015AE 2524 SLL V0, V0, 2
\r
2571 BFD015B0 0526 ADDU V0, V1, V0
\r
2572 BFD015B2 0020F85E SW V0, 32(S8)
\r
2573 601: pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */
\r
2574 BFD015B6 0020FC7E LW V1, 32(S8)
\r
2575 BFD015B8 30400020 SRL AT, ZERO, 6
\r
2576 BFD015BA FFF83040 ADDIU V0, ZERO, -8
\r
2577 BFD015BC 4493FFF8 LW RA, 17555(T8)
\r
2578 BFD015BE 4493 AND16 V0, V1
\r
2579 BFD015C0 0020F85E SW V0, 32(S8)
\r
2581 603: /* Check the alignment of the calculated top of stack is correct. */
\r
2582 604: configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
\r
2583 BFD015C4 0020FC5E LW V0, 32(S8)
\r
2584 BFD015C8 2D25 ANDI V0, V0, 0x7
\r
2585 BFD015CA 000940E2 BEQZC V0, 0xBFD015E0
\r
2586 BFD015CE BFD141A2 LUI V0, 0xBFD1
\r
2587 BFD015D0 3082BFD1 LDC1 F30, 12418(S1)
\r
2588 BFD015D2 98103082 ADDIU A0, V0, -26608
\r
2589 BFD015D4 30A09810 SWC1 F0, 12448(S0)
\r
2590 BFD015D6 025C30A0 ADDIU A1, ZERO, 604
\r
2591 BFD015DA 4B7E77E8 JALS vAssertCalled
\r
2592 BFD015DC 4B7E LW K1, 120(SP)
\r
2595 606: #else /* portSTACK_GROWTH */
\r
2597 608: pxTopOfStack = pxNewTCB->pxStack;
\r
2599 610: /* Check the alignment of the stack buffer is correct. */
\r
2600 611: configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
\r
2602 613: /* If we want to use stack checking on architectures that use
\r
2603 614: a positive stack growth direction then we also need to store the
\r
2604 615: other extreme of the stack space. */
\r
2605 616: pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );
\r
2607 618: #endif /* portSTACK_GROWTH */
\r
2609 620: /* Setup the newly allocated TCB with the initial state of the task. */
\r
2610 621: prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );
\r
2611 BFD015E0 0038345E LHU V0, 56(S8)
\r
2612 BFD015E4 C844 SW V0, 16(SP)
\r
2613 BFD015E6 001CFC9E LW A0, 28(S8)
\r
2614 BFD015EA 0034FCBE LW A1, 52(S8)
\r
2615 BFD015EE 0040FCDE LW A2, 64(S8)
\r
2616 BFD015F2 004CFCFE LW A3, 76(S8)
\r
2617 BFD015F6 1E7477E8 JALS prvInitialiseTCBVariables
\r
2618 BFD015F8 0C001E74 LB S3, 3072(S4)
\r
2621 623: /* Initialize the TCB stack to look as if the task was already running,
\r
2622 624: but had been interrupted by the scheduler. The return address is set
\r
2623 625: to the start of the task function. Once the stack has been initialised
\r
2624 626: the top of stack variable is updated. */
\r
2625 627: #if( portUSING_MPU_WRAPPERS == 1 )
\r
2627 629: pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
\r
2629 631: #else /* portUSING_MPU_WRAPPERS */
\r
2631 633: pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
\r
2632 BFD015FC 0020FC9E LW A0, 32(S8)
\r
2633 BFD01600 0030FCBE LW A1, 48(S8)
\r
2634 BFD01604 003CFCDE LW A2, 60(S8)
\r
2635 BFD01608 2B1877E8 JALS pxPortInitialiseStack
\r
2636 BFD0160A 2B18 LHU A2, 16(S1)
\r
2638 BFD0160E 0C62 MOVE V1, V0
\r
2639 BFD01610 001CFC5E LW V0, 28(S8)
\r
2640 BFD01614 E9A0 SW V1, 0(V0)
\r
2642 635: #endif /* portUSING_MPU_WRAPPERS */
\r
2644 637: if( ( void * ) pxCreatedTask != NULL )
\r
2645 BFD01616 0044FC5E LW V0, 68(S8)
\r
2646 BFD0161A 000540E2 BEQZC V0, 0xBFD01628
\r
2648 639: /* Pass the TCB out - in an anonymous way. The calling function/
\r
2649 640: task can use this as a handle to delete the task later if
\r
2651 642: *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
\r
2652 BFD0161E 0044FC5E LW V0, 68(S8)
\r
2653 BFD01622 001CFC7E LW V1, 28(S8)
\r
2654 BFD01626 E9A0 SW V1, 0(V0)
\r
2658 646: mtCOVERAGE_TEST_MARKER();
\r
2661 649: /* Ensure interrupts don't access the task lists while they are being
\r
2663 651: taskENTER_CRITICAL();
\r
2664 BFD01628 33B877E8 JALS vTaskEnterCritical
\r
2665 BFD0162A 0C0033B8 ADDIU SP, T8, 3072
\r
2668 653: uxCurrentNumberOfTasks++;
\r
2669 BFD0162E 8038FC5C LW V0, -32712(GP)
\r
2670 BFD01632 6D20 ADDIU V0, V0, 1
\r
2671 BFD01634 8038F85C SW V0, -32712(GP)
\r
2672 654: if( pxCurrentTCB == NULL )
\r
2673 BFD01638 8030FC5C LW V0, -32720(GP)
\r
2674 BFD0163C 000F40A2 BNEZC V0, 0xBFD0165E
\r
2676 656: /* There are no other tasks, or all the other tasks are in
\r
2677 657: the suspended state - make this the current task. */
\r
2678 658: pxCurrentTCB = pxNewTCB;
\r
2679 BFD01640 001CFC5E LW V0, 28(S8)
\r
2680 BFD01644 8030F85C SW V0, -32720(GP)
\r
2682 660: if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
\r
2683 BFD01648 8038FC7C LW V1, -32712(GP)
\r
2684 BFD0164C ED01 LI V0, 1
\r
2685 BFD0164E 0017B443 BNE V1, V0, 0xBFD01680
\r
2686 BFD01650 0C000017 SLL ZERO, S7, 1
\r
2689 662: /* This is the first task to be created so do the preliminary
\r
2690 663: initialisation required. We will not recover if this call
\r
2691 664: fails, but we will report the failure. */
\r
2692 665: prvInitialiseTaskLists();
\r
2693 BFD01654 309677E8 JALS prvInitialiseTaskLists
\r
2694 BFD01656 0C003096 ADDIU A0, S6, 3072
\r
2696 BFD0165A CC12 B 0xBFD01680
\r
2701 669: mtCOVERAGE_TEST_MARKER();
\r
2706 674: /* If the scheduler is not already running, make this task the
\r
2707 675: current task if it is the highest priority task to be created
\r
2709 677: if( xSchedulerRunning == pdFALSE )
\r
2710 BFD0165E 8044FC5C LW V0, -32700(GP)
\r
2711 BFD01662 000D40A2 BNEZC V0, 0xBFD01680
\r
2713 679: if( pxCurrentTCB->uxPriority <= uxPriority )
\r
2714 BFD01666 8030FC5C LW V0, -32720(GP)
\r
2715 BFD0166A 69AB LW V1, 44(V0)
\r
2716 BFD0166C 0040FC5E LW V0, 64(S8)
\r
2717 BFD01670 13900062 SLTU V0, V0, V1
\r
2718 BFD01672 40A21390 ADDI GP, S0, 16546
\r
2719 BFD01674 000440A2 BNEZC V0, 0xBFD01680
\r
2721 681: pxCurrentTCB = pxNewTCB;
\r
2722 BFD01678 001CFC5E LW V0, 28(S8)
\r
2723 BFD0167C 8030F85C SW V0, -32720(GP)
\r
2727 685: mtCOVERAGE_TEST_MARKER();
\r
2732 690: mtCOVERAGE_TEST_MARKER();
\r
2736 694: uxTaskNumber++;
\r
2737 BFD01680 8054FC5C LW V0, -32684(GP)
\r
2738 BFD01684 6D20 ADDIU V0, V0, 1
\r
2739 BFD01686 8054F85C SW V0, -32684(GP)
\r
2741 696: #if ( configUSE_TRACE_FACILITY == 1 )
\r
2743 698: /* Add a counter into the TCB for tracing only. */
\r
2744 699: pxNewTCB->uxTCBNumber = uxTaskNumber;
\r
2746 701: #endif /* configUSE_TRACE_FACILITY */
\r
2747 702: traceTASK_CREATE( pxNewTCB );
\r
2749 704: prvAddTaskToReadyList( pxNewTCB );
\r
2750 BFD0168A 001CFC5E LW V0, 28(S8)
\r
2751 BFD0168E 692B LW V0, 44(V0)
\r
2752 BFD01690 ED81 LI V1, 1
\r
2753 BFD01692 18100062 SLLV V1, V0, V1
\r
2754 BFD01694 FC5C1810 SB ZERO, -932(S0)
\r
2755 BFD01696 8040FC5C LW V0, -32704(GP)
\r
2756 BFD0169A 44D3 OR16 V0, V1
\r
2757 BFD0169C 8040F85C SW V0, -32704(GP)
\r
2758 BFD016A0 001CFC5E LW V0, 28(S8)
\r
2759 BFD016A4 692B LW V0, 44(V0)
\r
2760 BFD016A6 2524 SLL V0, V0, 2
\r
2761 BFD016A8 25A4 SLL V1, V0, 2
\r
2762 BFD016AA 05B4 ADDU V1, V0, V1
\r
2763 BFD016AC BFD241A2 LUI V0, 0xBFD2
\r
2764 BFD016AE 3042BFD2 LDC1 F30, 12354(S2)
\r
2765 BFD016B0 806C3042 ADDIU V0, V0, -32660
\r
2766 BFD016B4 05A6 ADDU V1, V1, V0
\r
2767 BFD016B6 001CFC5E LW V0, 28(S8)
\r
2768 BFD016BA 6D22 ADDIU V0, V0, 4
\r
2769 BFD016BC 0C83 MOVE A0, V1
\r
2770 BFD016BE 0CA2 MOVE A1, V0
\r
2771 BFD016C0 3E4A77E8 JALS vListInsertEnd
\r
2772 BFD016C2 0C003E4A LH S2, 3072(T2)
\r
2775 706: xReturn = pdPASS;
\r
2776 BFD016C6 ED01 LI V0, 1
\r
2777 BFD016C8 0018F85E SW V0, 24(S8)
\r
2778 707: portSETUP_TCB( pxNewTCB );
\r
2780 709: taskEXIT_CRITICAL();
\r
2781 BFD016CC 40AA77E8 JALS vTaskExitCritical
\r
2782 BFD016CE 0C0040AA BNEZC T2, 0xBFD02ED2
\r
2784 BFD016D2 CC04 B 0xBFD016DC
\r
2789 713: xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
\r
2790 BFD016D6 ED7F LI V0, -1
\r
2791 BFD016D8 0018F85E SW V0, 24(S8)
\r
2792 714: traceTASK_CREATE_FAILED();
\r
2795 717: if( xReturn == pdPASS )
\r
2796 BFD016DC 0018FC7E LW V1, 24(S8)
\r
2797 BFD016E0 ED01 LI V0, 1
\r
2798 BFD016E2 001EB443 BNE V1, V0, 0xBFD01722
\r
2799 BFD016E4 0C00001E SLL ZERO, S8, 1
\r
2802 719: if( xSchedulerRunning != pdFALSE )
\r
2803 BFD016E8 8044FC5C LW V0, -32700(GP)
\r
2804 BFD016EC 001940E2 BEQZC V0, 0xBFD01722
\r
2806 721: /* If the created task is of a higher priority than the current task
\r
2807 722: then it should run now. */
\r
2808 723: if( pxCurrentTCB->uxPriority < uxPriority )
\r
2809 BFD016F0 8030FC5C LW V0, -32720(GP)
\r
2810 BFD016F4 69AB LW V1, 44(V0)
\r
2811 BFD016F6 0040FC5E LW V0, 64(S8)
\r
2812 BFD016FA 13900043 SLTU V0, V1, V0
\r
2813 BFD016FC 40E21390 ADDI GP, S0, 16610
\r
2814 BFD016FE 001040E2 BEQZC V0, 0xBFD01722
\r
2816 725: taskYIELD_IF_USING_PREEMPTION();
\r
2817 BFD01702 4E5677E8 JALS ulPortGetCP0Cause
\r
2818 BFD01704 4E56 ADDIU S2, S2, -5
\r
2820 BFD01708 0024F85E SW V0, 36(S8)
\r
2821 BFD0170C 0024FC5E LW V0, 36(S8)
\r
2822 BFD01710 01005042 ORI V0, V0, 256
\r
2823 BFD01714 0024F85E SW V0, 36(S8)
\r
2824 BFD01718 0024FC9E LW A0, 36(S8)
\r
2825 BFD0171C 4E6677E8 JALS vPortSetCP0Cause
\r
2826 BFD0171E 4E66 ADDIU S3, S3, 3
\r
2831 729: mtCOVERAGE_TEST_MARKER();
\r
2836 734: mtCOVERAGE_TEST_MARKER();
\r
2840 738: return xReturn;
\r
2841 BFD01722 0018FC5E LW V0, 24(S8)
\r
2843 BFD01726 0FBE MOVE SP, S8
\r
2844 BFD01728 4BEB LW RA, 44(SP)
\r
2845 BFD0172A 4BCA LW S8, 40(SP)
\r
2846 BFD0172C 4C19 ADDIU SP, SP, 48
\r
2847 BFD0172E 459F JR16 RA
\r
2849 740: /*-----------------------------------------------------------*/
\r
2851 742: #if ( INCLUDE_vTaskDelete == 1 )
\r
2853 744: void vTaskDelete( TaskHandle_t xTaskToDelete )
\r
2855 BFD033F4 4FF1 ADDIU SP, SP, -32
\r
2856 BFD033F6 CBE7 SW RA, 28(SP)
\r
2857 BFD033F8 CBC6 SW S8, 24(SP)
\r
2858 BFD033FA 0FDD MOVE S8, SP
\r
2859 BFD033FC 0020F89E SW A0, 32(S8)
\r
2860 746: TCB_t *pxTCB;
\r
2862 748: taskENTER_CRITICAL();
\r
2863 BFD03400 33B877E8 JALS vTaskEnterCritical
\r
2864 BFD03402 0C0033B8 ADDIU SP, T8, 3072
\r
2867 750: /* If null is passed in here then it is the calling task that is
\r
2868 751: being deleted. */
\r
2869 752: pxTCB = prvGetTCBFromHandle( xTaskToDelete );
\r
2870 BFD03406 0020FC5E LW V0, 32(S8)
\r
2871 BFD0340A 000440A2 BNEZC V0, 0xBFD03416
\r
2872 BFD0340E 8030FC5C LW V0, -32720(GP)
\r
2873 BFD03412 CC03 B 0xBFD0341A
\r
2875 BFD03416 0020FC5E LW V0, 32(S8)
\r
2876 BFD0341A 0010F85E SW V0, 16(S8)
\r
2878 754: /* Remove task from the ready list and place in the termination list.
\r
2879 755: This will stop the task from be scheduled. The idle task will check
\r
2880 756: the termination list and free up any memory allocated by the
\r
2881 757: scheduler for the TCB and stack. */
\r
2882 758: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
2883 BFD0341E 0010FC5E LW V0, 16(S8)
\r
2884 BFD03422 6D22 ADDIU V0, V0, 4
\r
2885 BFD03424 0C82 MOVE A0, V0
\r
2886 BFD03426 00C877E8 JALS uxListRemove
\r
2887 BFD03428 0C0000C8 SLL A2, T0, 1
\r
2889 BFD0342C 001A40A2 BNEZC V0, 0xBFD03464
\r
2891 760: taskRESET_READY_PRIORITY( pxTCB->uxPriority );
\r
2892 BFD03430 0010FC5E LW V0, 16(S8)
\r
2893 BFD03434 692B LW V0, 44(V0)
\r
2894 BFD03436 2524 SLL V0, V0, 2
\r
2895 BFD03438 25A4 SLL V1, V0, 2
\r
2896 BFD0343A 05B4 ADDU V1, V0, V1
\r
2897 BFD0343C BFD241A2 LUI V0, 0xBFD2
\r
2898 BFD0343E 3042BFD2 LDC1 F30, 12354(S2)
\r
2899 BFD03440 806C3042 ADDIU V0, V0, -32660
\r
2900 BFD03444 0526 ADDU V0, V1, V0
\r
2901 BFD03446 6920 LW V0, 0(V0)
\r
2902 BFD03448 000C40A2 BNEZC V0, 0xBFD03464
\r
2903 BFD0344C 0010FC5E LW V0, 16(S8)
\r
2904 BFD03450 692B LW V0, 44(V0)
\r
2905 BFD03452 ED81 LI V1, 1
\r
2906 BFD03454 10100062 SLLV V0, V0, V1
\r
2907 BFD03456 441A1010 ADDI ZERO, S0, 17434
\r
2908 BFD03458 441A NOT16 V1, V0
\r
2909 BFD0345A 8040FC5C LW V0, -32704(GP)
\r
2910 BFD0345E 4493 AND16 V0, V1
\r
2911 BFD03460 8040F85C SW V0, -32704(GP)
\r
2915 764: mtCOVERAGE_TEST_MARKER();
\r
2918 767: /* Is the task waiting on an event also? */
\r
2919 768: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
\r
2920 BFD03464 0010FC5E LW V0, 16(S8)
\r
2921 BFD03468 692A LW V0, 40(V0)
\r
2922 BFD0346A 000740E2 BEQZC V0, 0xBFD0347C
\r
2924 770: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
\r
2925 BFD0346E 0010FC5E LW V0, 16(S8)
\r
2926 BFD03470 6D2C0010 EXT ZERO, S0, 20, 14
\r
2927 BFD03472 6D2C ADDIU V0, V0, 24
\r
2928 BFD03474 0C82 MOVE A0, V0
\r
2929 BFD03476 00C877E8 JALS uxListRemove
\r
2930 BFD03478 0C0000C8 SLL A2, T0, 1
\r
2935 774: mtCOVERAGE_TEST_MARKER();
\r
2938 777: vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );
\r
2939 BFD0347C 0010FC5E LW V0, 16(S8)
\r
2940 BFD03480 6D22 ADDIU V0, V0, 4
\r
2941 BFD03482 BFD241A3 LUI V1, 0xBFD2
\r
2942 BFD03484 3083BFD2 LDC1 F30, 12419(S2)
\r
2943 BFD03486 810C3083 ADDIU A0, V1, -32500
\r
2944 BFD0348A 0CA2 MOVE A1, V0
\r
2945 BFD0348C 3E4A77E8 JALS vListInsertEnd
\r
2946 BFD0348E 0C003E4A LH S2, 3072(T2)
\r
2949 779: /* Increment the ucTasksDeleted variable so the idle task knows
\r
2950 780: there is a task that has been deleted and that it should therefore
\r
2951 781: check the xTasksWaitingTermination list. */
\r
2952 782: ++uxTasksDeleted;
\r
2953 BFD03492 8034FC5C LW V0, -32716(GP)
\r
2954 BFD03496 6D20 ADDIU V0, V0, 1
\r
2955 BFD03498 8034F85C SW V0, -32716(GP)
\r
2957 784: /* Increment the uxTaskNumberVariable also so kernel aware debuggers
\r
2958 785: can detect that the task lists need re-generating. */
\r
2959 786: uxTaskNumber++;
\r
2960 BFD0349C 8054FC5C LW V0, -32684(GP)
\r
2961 BFD034A0 6D20 ADDIU V0, V0, 1
\r
2962 BFD034A2 8054F85C SW V0, -32684(GP)
\r
2964 788: traceTASK_DELETE( pxTCB );
\r
2966 790: taskEXIT_CRITICAL();
\r
2967 BFD034A6 40AA77E8 JALS vTaskExitCritical
\r
2968 BFD034A8 0C0040AA BNEZC T2, 0xBFD04CAC
\r
2971 792: /* Force a reschedule if it is the currently running task that has just
\r
2972 793: been deleted. */
\r
2973 794: if( xSchedulerRunning != pdFALSE )
\r
2974 BFD034AC 8044FC5C LW V0, -32700(GP)
\r
2975 BFD034B0 002F40E2 BEQZC V0, 0xBFD03512
\r
2977 796: if( pxTCB == pxCurrentTCB )
\r
2978 BFD034B4 8030FC5C LW V0, -32720(GP)
\r
2979 BFD034B8 0010FC7E LW V1, 16(S8)
\r
2980 BFD034BC 0020B443 BNE V1, V0, 0xBFD03500
\r
2981 BFD034BE 0C000020 SLL AT, ZERO, 1
\r
2984 798: configASSERT( uxSchedulerSuspended == 0 );
\r
2985 BFD034C2 805CFC5C LW V0, -32676(GP)
\r
2986 BFD034C6 000940E2 BEQZC V0, 0xBFD034DC
\r
2987 BFD034CA BFD141A2 LUI V0, 0xBFD1
\r
2988 BFD034CC 3082BFD1 LDC1 F30, 12418(S1)
\r
2989 BFD034CE 98103082 ADDIU A0, V0, -26608
\r
2990 BFD034D0 30A09810 SWC1 F0, 12448(S0)
\r
2991 BFD034D2 031E30A0 ADDIU A1, ZERO, 798
\r
2992 BFD034D6 4B7E77E8 JALS vAssertCalled
\r
2993 BFD034D8 4B7E LW K1, 120(SP)
\r
2996 800: /* The pre-delete hook is primarily for the Windows simulator,
\r
2997 801: in which Windows specific clean up operations are performed,
\r
2998 802: after which it is not possible to yield away from this task -
\r
2999 803: hence xYieldPending is used to latch that a context switch is
\r
3001 805: portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
\r
3002 806: portYIELD_WITHIN_API();
\r
3003 BFD034DC 4E5677E8 JALS ulPortGetCP0Cause
\r
3004 BFD034DE 4E56 ADDIU S2, S2, -5
\r
3006 BFD034E2 0014F85E SW V0, 20(S8)
\r
3007 BFD034E6 0014FC5E LW V0, 20(S8)
\r
3008 BFD034EA 01005042 ORI V0, V0, 256
\r
3009 BFD034EE 0014F85E SW V0, 20(S8)
\r
3010 BFD034F2 0014FC9E LW A0, 20(S8)
\r
3011 BFD034F6 4E6677E8 JALS vPortSetCP0Cause
\r
3012 BFD034F8 4E66 ADDIU S3, S3, 3
\r
3014 BFD034FC CC0A B 0xBFD03512
\r
3019 810: /* Reset the next expected unblock time in case it referred to
\r
3020 811: the task that has just been deleted. */
\r
3021 812: taskENTER_CRITICAL();
\r
3022 BFD03500 33B877E8 JALS vTaskEnterCritical
\r
3023 BFD03502 0C0033B8 ADDIU SP, T8, 3072
\r
3026 814: prvResetNextTaskUnblockTime();
\r
3027 BFD03506 47CA77E8 JALS prvResetNextTaskUnblockTime
\r
3030 816: taskEXIT_CRITICAL();
\r
3031 BFD0350C 40AA77E8 JALS vTaskExitCritical
\r
3032 BFD0350E 0C0040AA BNEZC T2, 0xBFD04D12
\r
3037 BFD03512 0FBE MOVE SP, S8
\r
3038 BFD03514 4BE7 LW RA, 28(SP)
\r
3039 BFD03516 4BC6 LW S8, 24(SP)
\r
3040 BFD03518 4C11 ADDIU SP, SP, 32
\r
3041 BFD0351A 459F JR16 RA
\r
3044 821: #endif /* INCLUDE_vTaskDelete */
\r
3045 822: /*-----------------------------------------------------------*/
\r
3047 824: #if ( INCLUDE_vTaskDelayUntil == 1 )
\r
3049 826: void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
\r
3051 BFD00008 4FE9 ADDIU SP, SP, -48
\r
3052 BFD0000A CBEB SW RA, 44(SP)
\r
3053 BFD0000C CBCA SW S8, 40(SP)
\r
3054 BFD0000E 0FDD MOVE S8, SP
\r
3055 BFD00010 0030F89E SW A0, 48(S8)
\r
3056 BFD00014 0034F8BE SW A1, 52(S8)
\r
3057 828: TickType_t xTimeToWake;
\r
3058 829: BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
\r
3059 BFD00018 0010F81E SW ZERO, 16(S8)
\r
3061 831: configASSERT( pxPreviousWakeTime );
\r
3062 BFD0001C 0030FC5E LW V0, 48(S8)
\r
3063 BFD00020 000940A2 BNEZC V0, 0xBFD00036
\r
3064 BFD00024 BFD141A2 LUI V0, 0xBFD1
\r
3065 BFD00026 3082BFD1 LDC1 F30, 12418(S1)
\r
3066 BFD00028 98103082 ADDIU A0, V0, -26608
\r
3067 BFD0002A 30A09810 SWC1 F0, 12448(S0)
\r
3068 BFD0002C 033F30A0 ADDIU A1, ZERO, 831
\r
3069 BFD00030 4B7E77E8 JALS vAssertCalled
\r
3070 BFD00032 4B7E LW K1, 120(SP)
\r
3072 832: configASSERT( ( xTimeIncrement > 0U ) );
\r
3073 BFD00036 0034FC5E LW V0, 52(S8)
\r
3074 BFD0003A 000940A2 BNEZC V0, 0xBFD00050
\r
3075 BFD0003E BFD141A2 LUI V0, 0xBFD1
\r
3076 BFD00040 3082BFD1 LDC1 F30, 12418(S1)
\r
3077 BFD00042 98103082 ADDIU A0, V0, -26608
\r
3078 BFD00044 30A09810 SWC1 F0, 12448(S0)
\r
3079 BFD00046 034030A0 ADDIU A1, ZERO, 832
\r
3080 BFD0004A 4B7E77E8 JALS vAssertCalled
\r
3081 BFD0004C 4B7E LW K1, 120(SP)
\r
3083 833: configASSERT( uxSchedulerSuspended == 0 );
\r
3084 BFD00050 805CFC5C LW V0, -32676(GP)
\r
3085 BFD00054 000940E2 BEQZC V0, 0xBFD0006A
\r
3086 BFD00058 BFD141A2 LUI V0, 0xBFD1
\r
3087 BFD0005A 3082BFD1 LDC1 F30, 12418(S1)
\r
3088 BFD0005C 98103082 ADDIU A0, V0, -26608
\r
3089 BFD0005E 30A09810 SWC1 F0, 12448(S0)
\r
3090 BFD00060 034130A0 ADDIU A1, ZERO, 833
\r
3091 BFD00064 4B7E77E8 JALS vAssertCalled
\r
3092 BFD00066 4B7E LW K1, 120(SP)
\r
3095 835: vTaskSuspendAll();
\r
3096 BFD0006A 4EF477E8 JALS vTaskSuspendAll
\r
3097 BFD0006C 4EF4 ADDIU S7, S7, -6
\r
3100 837: /* Minor optimisation. The tick count cannot change in this
\r
3102 839: const TickType_t xConstTickCount = xTickCount;
\r
3103 BFD00070 803CFC5C LW V0, -32708(GP)
\r
3104 BFD00074 0014F85E SW V0, 20(S8)
\r
3106 841: /* Generate the tick time at which the task wants to wake. */
\r
3107 842: xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
\r
3108 BFD00078 0030FC5E LW V0, 48(S8)
\r
3109 BFD0007C 69A0 LW V1, 0(V0)
\r
3110 BFD0007E 0034FC5E LW V0, 52(S8)
\r
3111 BFD00082 0526 ADDU V0, V1, V0
\r
3112 BFD00084 0018F85E SW V0, 24(S8)
\r
3114 844: if( xConstTickCount < *pxPreviousWakeTime )
\r
3115 BFD00088 0030FC5E LW V0, 48(S8)
\r
3116 BFD0008C 69A0 LW V1, 0(V0)
\r
3117 BFD0008E 0014FC5E LW V0, 20(S8)
\r
3118 BFD00092 13900062 SLTU V0, V0, V1
\r
3119 BFD00094 40E21390 ADDI GP, S0, 16610
\r
3120 BFD00096 001640E2 BEQZC V0, 0xBFD000C6
\r
3122 846: /* The tick count has overflowed since this function was
\r
3123 847: lasted called. In this case the only time we should ever
\r
3124 848: actually delay is if the wake time has also overflowed,
\r
3125 849: and the wake time is greater than the tick time. When this
\r
3126 850: is the case it is as if neither time had overflowed. */
\r
3127 851: if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
\r
3128 BFD0009A 0030FC5E LW V0, 48(S8)
\r
3129 BFD0009E 69A0 LW V1, 0(V0)
\r
3130 BFD000A0 0018FC5E LW V0, 24(S8)
\r
3131 BFD000A4 13900062 SLTU V0, V0, V1
\r
3132 BFD000A6 40E21390 ADDI GP, S0, 16610
\r
3133 BFD000A8 002140E2 BEQZC V0, 0xBFD000EE
\r
3134 BFD000AC 0018FC7E LW V1, 24(S8)
\r
3135 BFD000B0 0014FC5E LW V0, 20(S8)
\r
3136 BFD000B4 13900062 SLTU V0, V0, V1
\r
3137 BFD000B6 40E21390 ADDI GP, S0, 16610
\r
3138 BFD000B8 001940E2 BEQZC V0, 0xBFD000EE
\r
3140 853: xShouldDelay = pdTRUE;
\r
3141 BFD000BC ED01 LI V0, 1
\r
3142 BFD000BE 0010F85E SW V0, 16(S8)
\r
3143 BFD000C2 CC15 B 0xBFD000EE
\r
3148 857: mtCOVERAGE_TEST_MARKER();
\r
3153 862: /* The tick time has not overflowed. In this case we will
\r
3154 863: delay if either the wake time has overflowed, and/or the
\r
3155 864: tick time is less than the wake time. */
\r
3156 865: if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
\r
3157 BFD000C6 0030FC5E LW V0, 48(S8)
\r
3158 BFD000CA 69A0 LW V1, 0(V0)
\r
3159 BFD000CC 0018FC5E LW V0, 24(S8)
\r
3160 BFD000D0 13900062 SLTU V0, V0, V1
\r
3161 BFD000D2 40A21390 ADDI GP, S0, 16546
\r
3162 BFD000D4 000840A2 BNEZC V0, 0xBFD000E8
\r
3163 BFD000D8 0018FC7E LW V1, 24(S8)
\r
3164 BFD000DC 0014FC5E LW V0, 20(S8)
\r
3165 BFD000E0 13900062 SLTU V0, V0, V1
\r
3166 BFD000E2 40E21390 ADDI GP, S0, 16610
\r
3167 BFD000E4 000340E2 BEQZC V0, 0xBFD000EE
\r
3169 867: xShouldDelay = pdTRUE;
\r
3170 BFD000E8 ED01 LI V0, 1
\r
3171 BFD000EA 0010F85E SW V0, 16(S8)
\r
3175 871: mtCOVERAGE_TEST_MARKER();
\r
3179 875: /* Update the wake time ready for the next call. */
\r
3180 876: *pxPreviousWakeTime = xTimeToWake;
\r
3181 BFD000EE 0030FC5E LW V0, 48(S8)
\r
3182 BFD000F2 0018FC7E LW V1, 24(S8)
\r
3183 BFD000F6 E9A0 SW V1, 0(V0)
\r
3185 878: if( xShouldDelay != pdFALSE )
\r
3186 BFD000F8 0010FC5E LW V0, 16(S8)
\r
3187 BFD000FC 001A40E2 BEQZC V0, 0xBFD00134
\r
3189 880: traceTASK_DELAY_UNTIL();
\r
3191 882: /* Remove the task from the ready list before adding it to the
\r
3192 883: blocked list as the same list item is used for both lists. */
\r
3193 884: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
3194 BFD00100 8030FC5C LW V0, -32720(GP)
\r
3195 BFD00104 6D22 ADDIU V0, V0, 4
\r
3196 BFD00106 0C82 MOVE A0, V0
\r
3197 BFD00108 00C877E8 JALS uxListRemove
\r
3198 BFD0010A 0C0000C8 SLL A2, T0, 1
\r
3200 BFD0010E 000C40A2 BNEZC V0, 0xBFD0012A
\r
3202 886: /* The current task must be in a ready list, so there is
\r
3203 887: no need to check, and the port reset macro can be called
\r
3205 889: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
\r
3206 BFD00112 8030FC5C LW V0, -32720(GP)
\r
3207 BFD00116 692B LW V0, 44(V0)
\r
3208 BFD00118 ED81 LI V1, 1
\r
3209 BFD0011A 10100062 SLLV V0, V0, V1
\r
3210 BFD0011C 441A1010 ADDI ZERO, S0, 17434
\r
3211 BFD0011E 441A NOT16 V1, V0
\r
3212 BFD00120 8040FC5C LW V0, -32704(GP)
\r
3213 BFD00124 4493 AND16 V0, V1
\r
3214 BFD00126 8040F85C SW V0, -32704(GP)
\r
3218 893: mtCOVERAGE_TEST_MARKER();
\r
3221 896: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
3222 BFD0012A 0018FC9E LW A0, 24(S8)
\r
3223 BFD0012E 373477E8 JALS prvAddCurrentTaskToDelayedList
\r
3224 BFD00130 0C003734 LHU T9, 3072(S4)
\r
3229 900: mtCOVERAGE_TEST_MARKER();
\r
3232 903: xAlreadyYielded = xTaskResumeAll();
\r
3233 BFD00134 158E77E8 JALS xTaskResumeAll
\r
3234 BFD00136 0C00158E LBU T4, 3072(T6)
\r
3236 BFD0013A 001CF85E SW V0, 28(S8)
\r
3238 905: /* Force a reschedule if xTaskResumeAll has not already done so, we may
\r
3239 906: have put ourselves to sleep. */
\r
3240 907: if( xAlreadyYielded == pdFALSE )
\r
3241 BFD0013E 001CFC5E LW V0, 28(S8)
\r
3242 BFD00142 001040A2 BNEZC V0, 0xBFD00166
\r
3244 909: portYIELD_WITHIN_API();
\r
3245 BFD00146 4E5677E8 JALS ulPortGetCP0Cause
\r
3246 BFD00148 4E56 ADDIU S2, S2, -5
\r
3248 BFD0014C 0020F85E SW V0, 32(S8)
\r
3249 BFD00150 0020FC5E LW V0, 32(S8)
\r
3250 BFD00154 01005042 ORI V0, V0, 256
\r
3251 BFD00158 0020F85E SW V0, 32(S8)
\r
3252 BFD0015C 0020FC9E LW A0, 32(S8)
\r
3253 BFD00160 4E6677E8 JALS vPortSetCP0Cause
\r
3254 BFD00162 4E66 ADDIU S3, S3, 3
\r
3259 913: mtCOVERAGE_TEST_MARKER();
\r
3262 BFD00166 0FBE MOVE SP, S8
\r
3263 BFD00168 4BEB LW RA, 44(SP)
\r
3264 BFD0016A 4BCA LW S8, 40(SP)
\r
3265 BFD0016C 4C19 ADDIU SP, SP, 48
\r
3266 BFD0016E 459F JR16 RA
\r
3269 917: #endif /* INCLUDE_vTaskDelayUntil */
\r
3270 918: /*-----------------------------------------------------------*/
\r
3272 920: #if ( INCLUDE_vTaskDelay == 1 )
\r
3274 922: void vTaskDelay( const TickType_t xTicksToDelay )
\r
3276 BFD05BA0 4FED ADDIU SP, SP, -40
\r
3277 BFD05BA2 CBE9 SW RA, 36(SP)
\r
3278 BFD05BA4 CBC8 SW S8, 32(SP)
\r
3279 BFD05BA6 0FDD MOVE S8, SP
\r
3280 BFD05BA8 0028F89E SW A0, 40(S8)
\r
3281 924: TickType_t xTimeToWake;
\r
3282 925: BaseType_t xAlreadyYielded = pdFALSE;
\r
3283 BFD05BAC 0010F81E SW ZERO, 16(S8)
\r
3286 928: /* A delay time of zero just forces a reschedule. */
\r
3287 929: if( xTicksToDelay > ( TickType_t ) 0U )
\r
3288 BFD05BB0 0028FC5E LW V0, 40(S8)
\r
3289 BFD05BB4 003640E2 BEQZC V0, 0xBFD05C24
\r
3291 931: configASSERT( uxSchedulerSuspended == 0 );
\r
3292 BFD05BB8 805CFC5C LW V0, -32676(GP)
\r
3293 BFD05BBC 000940E2 BEQZC V0, 0xBFD05BD2
\r
3294 BFD05BC0 BFD141A2 LUI V0, 0xBFD1
\r
3295 BFD05BC2 3082BFD1 LDC1 F30, 12418(S1)
\r
3296 BFD05BC4 98103082 ADDIU A0, V0, -26608
\r
3297 BFD05BC6 30A09810 SWC1 F0, 12448(S0)
\r
3298 BFD05BC8 03A330A0 ADDIU A1, ZERO, 931
\r
3299 BFD05BCC 4B7E77E8 JALS vAssertCalled
\r
3300 BFD05BCE 4B7E LW K1, 120(SP)
\r
3302 932: vTaskSuspendAll();
\r
3303 BFD05BD2 4EF477E8 JALS vTaskSuspendAll
\r
3304 BFD05BD4 4EF4 ADDIU S7, S7, -6
\r
3307 934: traceTASK_DELAY();
\r
3309 936: /* A task that is removed from the event list while the
\r
3310 937: scheduler is suspended will not get placed in the ready
\r
3311 938: list or removed from the blocked list until the scheduler
\r
3314 941: This task cannot be in an event list as it is the currently
\r
3315 942: executing task. */
\r
3317 944: /* Calculate the time to wake - this may overflow but this is
\r
3318 945: not a problem. */
\r
3319 946: xTimeToWake = xTickCount + xTicksToDelay;
\r
3320 BFD05BD8 803CFC7C LW V1, -32708(GP)
\r
3321 BFD05BDC 0028FC5E LW V0, 40(S8)
\r
3322 BFD05BE0 0526 ADDU V0, V1, V0
\r
3323 BFD05BE2 0014F85E SW V0, 20(S8)
\r
3325 948: /* We must remove ourselves from the ready list before adding
\r
3326 949: ourselves to the blocked list as the same list item is used for
\r
3327 950: both lists. */
\r
3328 951: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
3329 BFD05BE6 8030FC5C LW V0, -32720(GP)
\r
3330 BFD05BEA 6D22 ADDIU V0, V0, 4
\r
3331 BFD05BEC 0C82 MOVE A0, V0
\r
3332 BFD05BEE 00C877E8 JALS uxListRemove
\r
3333 BFD05BF0 0C0000C8 SLL A2, T0, 1
\r
3335 BFD05BF4 000C40A2 BNEZC V0, 0xBFD05C10
\r
3337 953: /* The current task must be in a ready list, so there is
\r
3338 954: no need to check, and the port reset macro can be called
\r
3340 956: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
\r
3341 BFD05BF8 8030FC5C LW V0, -32720(GP)
\r
3342 BFD05BFC 692B LW V0, 44(V0)
\r
3343 BFD05BFE ED81 LI V1, 1
\r
3344 BFD05C00 10100062 SLLV V0, V0, V1
\r
3345 BFD05C02 441A1010 ADDI ZERO, S0, 17434
\r
3346 BFD05C04 441A NOT16 V1, V0
\r
3347 BFD05C06 8040FC5C LW V0, -32704(GP)
\r
3348 BFD05C0A 4493 AND16 V0, V1
\r
3349 BFD05C0C 8040F85C SW V0, -32704(GP)
\r
3353 960: mtCOVERAGE_TEST_MARKER();
\r
3355 962: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
3356 BFD05C10 0014FC9E LW A0, 20(S8)
\r
3357 BFD05C14 373477E8 JALS prvAddCurrentTaskToDelayedList
\r
3358 BFD05C16 0C003734 LHU T9, 3072(S4)
\r
3361 964: xAlreadyYielded = xTaskResumeAll();
\r
3362 BFD05C1A 158E77E8 JALS xTaskResumeAll
\r
3363 BFD05C1C 0C00158E LBU T4, 3072(T6)
\r
3365 BFD05C20 0010F85E SW V0, 16(S8)
\r
3369 968: mtCOVERAGE_TEST_MARKER();
\r
3372 971: /* Force a reschedule if xTaskResumeAll has not already done so, we may
\r
3373 972: have put ourselves to sleep. */
\r
3374 973: if( xAlreadyYielded == pdFALSE )
\r
3375 BFD05C24 0010FC5E LW V0, 16(S8)
\r
3376 BFD05C28 001040A2 BNEZC V0, 0xBFD05C4C
\r
3378 975: portYIELD_WITHIN_API();
\r
3379 BFD05C2C 4E5677E8 JALS ulPortGetCP0Cause
\r
3380 BFD05C2E 4E56 ADDIU S2, S2, -5
\r
3382 BFD05C32 0018F85E SW V0, 24(S8)
\r
3383 BFD05C36 0018FC5E LW V0, 24(S8)
\r
3384 BFD05C3A 01005042 ORI V0, V0, 256
\r
3385 BFD05C3E 0018F85E SW V0, 24(S8)
\r
3386 BFD05C42 0018FC9E LW A0, 24(S8)
\r
3387 BFD05C46 4E6677E8 JALS vPortSetCP0Cause
\r
3388 BFD05C48 4E66 ADDIU S3, S3, 3
\r
3393 979: mtCOVERAGE_TEST_MARKER();
\r
3396 BFD05C4C 0FBE MOVE SP, S8
\r
3397 BFD05C4E 4BE9 LW RA, 36(SP)
\r
3398 BFD05C50 4BC8 LW S8, 32(SP)
\r
3399 BFD05C52 4C15 ADDIU SP, SP, 40
\r
3400 BFD05C54 459F JR16 RA
\r
3403 983: #endif /* INCLUDE_vTaskDelay */
\r
3404 984: /*-----------------------------------------------------------*/
\r
3406 986: #if ( INCLUDE_eTaskGetState == 1 )
\r
3408 988: eTaskState eTaskGetState( TaskHandle_t xTask )
\r
3410 BFD04494 4FED ADDIU SP, SP, -40
\r
3411 BFD04496 CBE9 SW RA, 36(SP)
\r
3412 BFD04498 CBC8 SW S8, 32(SP)
\r
3413 BFD0449A 0FDD MOVE S8, SP
\r
3414 BFD0449C 0028F89E SW A0, 40(S8)
\r
3415 990: eTaskState eReturn;
\r
3416 991: List_t *pxStateList;
\r
3417 992: const TCB_t * const pxTCB = ( TCB_t * ) xTask;
\r
3418 BFD044A0 0028FC5E LW V0, 40(S8)
\r
3419 BFD044A4 0014F85E SW V0, 20(S8)
\r
3421 994: configASSERT( pxTCB );
\r
3422 BFD044A8 0014FC5E LW V0, 20(S8)
\r
3423 BFD044AC 000940A2 BNEZC V0, 0xBFD044C2
\r
3424 BFD044B0 BFD141A2 LUI V0, 0xBFD1
\r
3425 BFD044B2 3082BFD1 LDC1 F30, 12418(S1)
\r
3426 BFD044B4 98103082 ADDIU A0, V0, -26608
\r
3427 BFD044B6 30A09810 SWC1 F0, 12448(S0)
\r
3428 BFD044B8 03E230A0 ADDIU A1, ZERO, 994
\r
3429 BFD044BC 4B7E77E8 JALS vAssertCalled
\r
3430 BFD044BE 4B7E LW K1, 120(SP)
\r
3433 996: if( pxTCB == pxCurrentTCB )
\r
3434 BFD044C2 8030FC5C LW V0, -32720(GP)
\r
3435 BFD044C6 0014FC7E LW V1, 20(S8)
\r
3436 BFD044CA 0005B443 BNE V1, V0, 0xBFD044D8
\r
3437 BFD044CC 0C000005 SLL ZERO, A1, 1
\r
3440 998: /* The task calling this function is querying its own state. */
\r
3441 999: eReturn = eRunning;
\r
3442 BFD044D0 0010F81E SW ZERO, 16(S8)
\r
3443 BFD044D4 CC48 B 0xBFD04566
\r
3448 1003: taskENTER_CRITICAL();
\r
3449 BFD044D8 33B877E8 JALS vTaskEnterCritical
\r
3450 BFD044DA 0C0033B8 ADDIU SP, T8, 3072
\r
3453 1005: pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xGenericListItem ) );
\r
3454 BFD044DE 0014FC5E LW V0, 20(S8)
\r
3455 BFD044E2 6925 LW V0, 20(V0)
\r
3456 BFD044E4 0018F85E SW V0, 24(S8)
\r
3458 1007: taskEXIT_CRITICAL();
\r
3459 BFD044E8 40AA77E8 JALS vTaskExitCritical
\r
3460 BFD044EA 0C0040AA BNEZC T2, 0xBFD05CEE
\r
3463 1009: if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
\r
3464 BFD044EE 8074FC5C LW V0, -32652(GP)
\r
3465 BFD044F2 0018FC7E LW V1, 24(S8)
\r
3466 BFD044F6 00089443 BEQ V1, V0, 0xBFD0450A
\r
3467 BFD044F8 0C000008 SLL ZERO, T0, 1
\r
3469 BFD044FC 8078FC5C LW V0, -32648(GP)
\r
3470 BFD04500 0018FC7E LW V1, 24(S8)
\r
3471 BFD04504 0006B443 BNE V1, V0, 0xBFD04514
\r
3472 BFD04506 0C000006 SLL ZERO, A2, 1
\r
3475 1011: /* The task being queried is referenced from one of the Blocked
\r
3477 1013: eReturn = eBlocked;
\r
3478 BFD0450A ED02 LI V0, 2
\r
3479 BFD0450C 0010F85E SW V0, 16(S8)
\r
3480 BFD04510 CC2A B 0xBFD04566
\r
3484 1016: #if ( INCLUDE_vTaskSuspend == 1 )
\r
3485 1017: else if( pxStateList == &xSuspendedTaskList )
\r
3486 BFD04514 0018FC7E LW V1, 24(S8)
\r
3487 BFD04518 BFD241A2 LUI V0, 0xBFD2
\r
3488 BFD0451A 3042BFD2 LDC1 F30, 12354(S2)
\r
3489 BFD0451C 80E43042 ADDIU V0, V0, -32540
\r
3490 BFD04520 0010B443 BNE V1, V0, 0xBFD04544
\r
3491 BFD04522 0C000010 SLL ZERO, S0, 1
\r
3494 1019: /* The task being queried is referenced from the suspended
\r
3495 1020: list. Is it genuinely suspended or is it block
\r
3496 1021: indefinitely? */
\r
3497 1022: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
\r
3498 BFD04526 0014FC5E LW V0, 20(S8)
\r
3499 BFD0452A 692A LW V0, 40(V0)
\r
3500 BFD0452C 000540A2 BNEZC V0, 0xBFD0453A
\r
3502 1024: eReturn = eSuspended;
\r
3503 BFD04530 ED03 LI V0, 3
\r
3504 BFD04532 0010F85E SW V0, 16(S8)
\r
3505 BFD04536 CC17 B 0xBFD04566
\r
3510 1028: eReturn = eBlocked;
\r
3511 BFD0453A ED02 LI V0, 2
\r
3512 BFD0453C 0010F85E SW V0, 16(S8)
\r
3513 BFD04540 CC12 B 0xBFD04566
\r
3519 1033: #if ( INCLUDE_vTaskDelete == 1 )
\r
3520 1034: else if( pxStateList == &xTasksWaitingTermination )
\r
3521 BFD04544 0018FC7E LW V1, 24(S8)
\r
3522 BFD04548 BFD241A2 LUI V0, 0xBFD2
\r
3523 BFD0454A 3042BFD2 LDC1 F30, 12354(S2)
\r
3524 BFD0454C 810C3042 ADDIU V0, V0, -32500
\r
3525 BFD04550 0006B443 BNE V1, V0, 0xBFD04560
\r
3526 BFD04552 0C000006 SLL ZERO, A2, 1
\r
3529 1036: /* The task being queried is referenced from the deleted
\r
3530 1037: tasks list. */
\r
3531 1038: eReturn = eDeleted;
\r
3532 BFD04556 ED04 LI V0, 4
\r
3533 BFD04558 0010F85E SW V0, 16(S8)
\r
3534 BFD0455C CC04 B 0xBFD04566
\r
3539 1042: else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
\r
3541 1044: /* If the task is not in any other state, it must be in the
\r
3542 1045: Ready (including pending ready) state. */
\r
3543 1046: eReturn = eReady;
\r
3544 BFD04560 ED01 LI V0, 1
\r
3545 BFD04562 0010F85E SW V0, 16(S8)
\r
3549 1050: return eReturn;
\r
3550 BFD04566 0010FC5E LW V0, 16(S8)
\r
3551 1051: } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
\r
3552 BFD0456A 0FBE MOVE SP, S8
\r
3553 BFD0456C 4BE9 LW RA, 36(SP)
\r
3554 BFD0456E 4BC8 LW S8, 32(SP)
\r
3555 BFD04570 4C15 ADDIU SP, SP, 40
\r
3556 BFD04572 459F JR16 RA
\r
3559 1053: #endif /* INCLUDE_eTaskGetState */
\r
3560 1054: /*-----------------------------------------------------------*/
\r
3562 1056: #if ( INCLUDE_uxTaskPriorityGet == 1 )
\r
3564 1058: UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
\r
3566 BFD08B78 4FF1 ADDIU SP, SP, -32
\r
3567 BFD08B7A CBE7 SW RA, 28(SP)
\r
3568 BFD08B7C CBC6 SW S8, 24(SP)
\r
3569 BFD08B7E 0FDD MOVE S8, SP
\r
3570 BFD08B80 0020F89E SW A0, 32(S8)
\r
3571 1060: TCB_t *pxTCB;
\r
3572 1061: UBaseType_t uxReturn;
\r
3574 1063: taskENTER_CRITICAL();
\r
3575 BFD08B84 33B877E8 JALS vTaskEnterCritical
\r
3576 BFD08B86 0C0033B8 ADDIU SP, T8, 3072
\r
3579 1065: /* If null is passed in here then we are changing the
\r
3580 1066: priority of the calling function. */
\r
3581 1067: pxTCB = prvGetTCBFromHandle( xTask );
\r
3582 BFD08B8A 0020FC5E LW V0, 32(S8)
\r
3583 BFD08B8E 000440A2 BNEZC V0, 0xBFD08B9A
\r
3584 BFD08B92 8030FC5C LW V0, -32720(GP)
\r
3585 BFD08B96 CC03 B 0xBFD08B9E
\r
3587 BFD08B9A 0020FC5E LW V0, 32(S8)
\r
3588 BFD08B9E 0010F85E SW V0, 16(S8)
\r
3589 1068: uxReturn = pxTCB->uxPriority;
\r
3590 BFD08BA2 0010FC5E LW V0, 16(S8)
\r
3591 BFD08BA6 692B LW V0, 44(V0)
\r
3592 BFD08BA8 0014F85E SW V0, 20(S8)
\r
3594 1070: taskEXIT_CRITICAL();
\r
3595 BFD08BAC 40AA77E8 JALS vTaskExitCritical
\r
3596 BFD08BAE 0C0040AA BNEZC T2, 0xBFD0A3B2
\r
3599 1072: return uxReturn;
\r
3600 BFD08BB2 0014FC5E LW V0, 20(S8)
\r
3602 BFD08BB6 0FBE MOVE SP, S8
\r
3603 BFD08BB8 4BE7 LW RA, 28(SP)
\r
3604 BFD08BBA 4BC6 LW S8, 24(SP)
\r
3605 BFD08BBC 4C11 ADDIU SP, SP, 32
\r
3606 BFD08BBE 459F JR16 RA
\r
3609 1075: #endif /* INCLUDE_uxTaskPriorityGet */
\r
3610 1076: /*-----------------------------------------------------------*/
\r
3612 1078: #if ( INCLUDE_uxTaskPriorityGet == 1 )
\r
3614 1080: UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )
\r
3616 BFD08708 4FED ADDIU SP, SP, -40
\r
3617 BFD0870A CBE9 SW RA, 36(SP)
\r
3618 BFD0870C CBC8 SW S8, 32(SP)
\r
3619 BFD0870E 0FDD MOVE S8, SP
\r
3620 BFD08710 0028F89E SW A0, 40(S8)
\r
3621 1082: TCB_t *pxTCB;
\r
3622 1083: UBaseType_t uxReturn, uxSavedInterruptState;
\r
3624 1085: /* RTOS ports that support interrupt nesting have the concept of a
\r
3625 1086: maximum system call (or maximum API call) interrupt priority.
\r
3626 1087: Interrupts that are above the maximum system call priority are keep
\r
3627 1088: permanently enabled, even when the RTOS kernel is in a critical section,
\r
3628 1089: but cannot make any calls to FreeRTOS API functions. If configASSERT()
\r
3629 1090: is defined in FreeRTOSConfig.h then
\r
3630 1091: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
3631 1092: failure if a FreeRTOS API function is called from an interrupt that has
\r
3632 1093: been assigned a priority above the configured maximum system call
\r
3633 1094: priority. Only FreeRTOS functions that end in FromISR can be called
\r
3634 1095: from interrupts that have been assigned a priority at or (logically)
\r
3635 1096: below the maximum system call interrupt priority. FreeRTOS maintains a
\r
3636 1097: separate interrupt safe API to ensure interrupt entry is as fast and as
\r
3637 1098: simple as possible. More information (albeit Cortex-M specific) is
\r
3638 1099: provided on the following link:
\r
3639 1100: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
3640 1101: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
3642 1103: uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
\r
3643 BFD08714 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
3645 BFD0871A 0010F85E SW V0, 16(S8)
\r
3647 1105: /* If null is passed in here then it is the priority of the calling
\r
3648 1106: task that is being queried. */
\r
3649 1107: pxTCB = prvGetTCBFromHandle( xTask );
\r
3650 BFD0871E 0028FC5E LW V0, 40(S8)
\r
3651 BFD08722 000440A2 BNEZC V0, 0xBFD0872E
\r
3652 BFD08726 8030FC5C LW V0, -32720(GP)
\r
3653 BFD0872A CC03 B 0xBFD08732
\r
3655 BFD0872E 0028FC5E LW V0, 40(S8)
\r
3656 BFD08732 0014F85E SW V0, 20(S8)
\r
3657 1108: uxReturn = pxTCB->uxPriority;
\r
3658 BFD08736 0014FC5E LW V0, 20(S8)
\r
3659 BFD0873A 692B LW V0, 44(V0)
\r
3660 BFD0873C 0018F85E SW V0, 24(S8)
\r
3662 1110: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
\r
3663 BFD08740 0010FC9E LW A0, 16(S8)
\r
3664 BFD08744 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
3665 BFD08746 4D5E ADDIU T2, T2, -1
\r
3668 1112: return uxReturn;
\r
3669 BFD0874A 0018FC5E LW V0, 24(S8)
\r
3671 BFD0874E 0FBE MOVE SP, S8
\r
3672 BFD08750 4BE9 LW RA, 36(SP)
\r
3673 BFD08752 4BC8 LW S8, 32(SP)
\r
3674 BFD08754 4C15 ADDIU SP, SP, 40
\r
3675 BFD08756 459F JR16 RA
\r
3678 1115: #endif /* INCLUDE_uxTaskPriorityGet */
\r
3679 1116: /*-----------------------------------------------------------*/
\r
3681 1118: #if ( INCLUDE_vTaskPrioritySet == 1 )
\r
3683 1120: void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
\r
3685 BFD01924 4FE9 ADDIU SP, SP, -48
\r
3686 BFD01926 CBEB SW RA, 44(SP)
\r
3687 BFD01928 CBCA SW S8, 40(SP)
\r
3688 BFD0192A 0FDD MOVE S8, SP
\r
3689 BFD0192C 0030F89E SW A0, 48(S8)
\r
3690 BFD01930 0034F8BE SW A1, 52(S8)
\r
3691 1122: TCB_t *pxTCB;
\r
3692 1123: UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
\r
3693 1124: BaseType_t xYieldRequired = pdFALSE;
\r
3694 BFD01934 0010F81E SW ZERO, 16(S8)
\r
3696 1126: configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
\r
3697 BFD01938 0034FC5E LW V0, 52(S8)
\r
3698 BFD0193C 0005B042 SLTIU V0, V0, 5
\r
3699 BFD01940 000940A2 BNEZC V0, 0xBFD01956
\r
3700 BFD01944 BFD141A2 LUI V0, 0xBFD1
\r
3701 BFD01946 3082BFD1 LDC1 F30, 12418(S1)
\r
3702 BFD01948 98103082 ADDIU A0, V0, -26608
\r
3703 BFD0194A 30A09810 SWC1 F0, 12448(S0)
\r
3704 BFD0194C 046630A0 ADDIU A1, ZERO, 1126
\r
3705 BFD0194E 0466 ADDU S0, V1, A2
\r
3706 BFD01950 4B7E77E8 JALS vAssertCalled
\r
3707 BFD01952 4B7E LW K1, 120(SP)
\r
3710 1128: /* Ensure the new priority is valid. */
\r
3711 1129: if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
\r
3712 BFD01956 0034FC5E LW V0, 52(S8)
\r
3713 BFD0195A 0005B042 SLTIU V0, V0, 5
\r
3714 BFD0195E 000340A2 BNEZC V0, 0xBFD01968
\r
3716 1131: uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
\r
3717 BFD01962 ED04 LI V0, 4
\r
3718 BFD01964 0034F85E SW V0, 52(S8)
\r
3722 1135: mtCOVERAGE_TEST_MARKER();
\r
3725 1138: taskENTER_CRITICAL();
\r
3726 BFD01968 33B877E8 JALS vTaskEnterCritical
\r
3727 BFD0196A 0C0033B8 ADDIU SP, T8, 3072
\r
3730 1140: /* If null is passed in here then it is the priority of the calling
\r
3731 1141: task that is being changed. */
\r
3732 1142: pxTCB = prvGetTCBFromHandle( xTask );
\r
3733 BFD0196E 0030FC5E LW V0, 48(S8)
\r
3734 BFD01972 000440A2 BNEZC V0, 0xBFD0197E
\r
3735 BFD01976 8030FC5C LW V0, -32720(GP)
\r
3736 BFD0197A CC03 B 0xBFD01982
\r
3738 BFD0197E 0030FC5E LW V0, 48(S8)
\r
3739 BFD01982 0014F85E SW V0, 20(S8)
\r
3741 1144: traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
\r
3743 1146: #if ( configUSE_MUTEXES == 1 )
\r
3745 1148: uxCurrentBasePriority = pxTCB->uxBasePriority;
\r
3746 BFD01986 0014FC5E LW V0, 20(S8)
\r
3747 BFD0198A 0040FC42 LW V0, 64(V0)
\r
3748 BFD0198E 0018F85E SW V0, 24(S8)
\r
3752 1152: uxCurrentBasePriority = pxTCB->uxPriority;
\r
3756 1156: if( uxCurrentBasePriority != uxNewPriority )
\r
3757 BFD01992 0018FC7E LW V1, 24(S8)
\r
3758 BFD01996 0034FC5E LW V0, 52(S8)
\r
3759 BFD0199A 00AD9443 BEQ V1, V0, 0xBFD01AF8
\r
3760 BFD0199C 0C0000AD SLL A1, T5, 1
\r
3763 1158: /* The priority change may have readied a task of higher
\r
3764 1159: priority than the calling task. */
\r
3765 1160: if( uxNewPriority > uxCurrentBasePriority )
\r
3766 BFD019A0 0034FC7E LW V1, 52(S8)
\r
3767 BFD019A4 0018FC5E LW V0, 24(S8)
\r
3768 BFD019A8 13900062 SLTU V0, V0, V1
\r
3769 BFD019AA 40E21390 ADDI GP, S0, 16610
\r
3770 BFD019AC 001540E2 BEQZC V0, 0xBFD019DA
\r
3772 1162: if( pxTCB != pxCurrentTCB )
\r
3773 BFD019B0 8030FC5C LW V0, -32720(GP)
\r
3774 BFD019B4 0014FC7E LW V1, 20(S8)
\r
3775 BFD019B8 00199443 BEQ V1, V0, 0xBFD019EE
\r
3776 BFD019BA 0C000019 SLL ZERO, T9, 1
\r
3779 1164: /* The priority of a task other than the currently
\r
3780 1165: running task is being raised. Is the priority being
\r
3781 1166: raised above that of the running task? */
\r
3782 1167: if( uxNewPriority >= pxCurrentTCB->uxPriority )
\r
3783 BFD019BE 8030FC5C LW V0, -32720(GP)
\r
3784 BFD019C2 69AB LW V1, 44(V0)
\r
3785 BFD019C4 0034FC5E LW V0, 52(S8)
\r
3786 BFD019C8 13900062 SLTU V0, V0, V1
\r
3787 BFD019CA 40A21390 ADDI GP, S0, 16546
\r
3788 BFD019CC 000F40A2 BNEZC V0, 0xBFD019EE
\r
3790 1169: xYieldRequired = pdTRUE;
\r
3791 BFD019D0 ED01 LI V0, 1
\r
3792 BFD019D2 0010F85E SW V0, 16(S8)
\r
3793 BFD019D6 CC0B B 0xBFD019EE
\r
3798 1173: mtCOVERAGE_TEST_MARKER();
\r
3803 1178: /* The priority of the running task is being raised,
\r
3804 1179: but the running task must already be the highest
\r
3805 1180: priority task able to run so no yield is required. */
\r
3808 1183: else if( pxTCB == pxCurrentTCB )
\r
3809 BFD019DA 8030FC5C LW V0, -32720(GP)
\r
3810 BFD019DE 0014FC7E LW V1, 20(S8)
\r
3811 BFD019E2 0004B443 BNE V1, V0, 0xBFD019EE
\r
3812 BFD019E4 0C000004 SLL ZERO, A0, 1
\r
3815 1185: /* Setting the priority of the running task down means
\r
3816 1186: there may now be another task of higher priority that
\r
3817 1187: is ready to execute. */
\r
3818 1188: xYieldRequired = pdTRUE;
\r
3819 BFD019E8 ED01 LI V0, 1
\r
3820 BFD019EA 0010F85E SW V0, 16(S8)
\r
3824 1192: /* Setting the priority of any other task down does not
\r
3825 1193: require a yield as the running task must be above the
\r
3826 1194: new priority of the task being modified. */
\r
3829 1197: /* Remember the ready list the task might be referenced from
\r
3830 1198: before its uxPriority member is changed so the
\r
3831 1199: taskRESET_READY_PRIORITY() macro can function correctly. */
\r
3832 1200: uxPriorityUsedOnEntry = pxTCB->uxPriority;
\r
3833 BFD019EE 0014FC5E LW V0, 20(S8)
\r
3834 BFD019F2 692B LW V0, 44(V0)
\r
3835 BFD019F4 001CF85E SW V0, 28(S8)
\r
3837 1202: #if ( configUSE_MUTEXES == 1 )
\r
3839 1204: /* Only change the priority being used if the task is not
\r
3840 1205: currently using an inherited priority. */
\r
3841 1206: if( pxTCB->uxBasePriority == pxTCB->uxPriority )
\r
3842 BFD019F8 0014FC5E LW V0, 20(S8)
\r
3843 BFD019FC 0040FC62 LW V1, 64(V0)
\r
3844 BFD01A00 0014FC5E LW V0, 20(S8)
\r
3845 BFD01A04 692B LW V0, 44(V0)
\r
3846 BFD01A06 0006B443 BNE V1, V0, 0xBFD01A16
\r
3847 BFD01A08 0C000006 SLL ZERO, A2, 1
\r
3850 1208: pxTCB->uxPriority = uxNewPriority;
\r
3851 BFD01A0C 0014FC5E LW V0, 20(S8)
\r
3852 BFD01A10 0034FC7E LW V1, 52(S8)
\r
3853 BFD01A14 E9AB SW V1, 44(V0)
\r
3857 1212: mtCOVERAGE_TEST_MARKER();
\r
3860 1215: /* The base priority gets set whatever. */
\r
3861 1216: pxTCB->uxBasePriority = uxNewPriority;
\r
3862 BFD01A16 0014FC5E LW V0, 20(S8)
\r
3863 BFD01A1A 0034FC7E LW V1, 52(S8)
\r
3864 BFD01A1E 0040F862 SW V1, 64(V0)
\r
3868 1220: pxTCB->uxPriority = uxNewPriority;
\r
3872 1224: /* Only reset the event list item value if the value is not
\r
3873 1225: being used for anything else. */
\r
3874 1226: if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
\r
3875 BFD01A22 0014FC5E LW V0, 20(S8)
\r
3876 BFD01A26 6926 LW V0, 24(V0)
\r
3877 BFD01A28 00084002 BLTZ V0, 0xBFD01A3C
\r
3878 BFD01A2A 0C000008 SLL ZERO, T0, 1
\r
3881 1228: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
3882 BFD01A2E ED85 LI V1, 5
\r
3883 BFD01A30 0034FC5E LW V0, 52(S8)
\r
3884 BFD01A34 05A7 SUBU V1, V1, V0
\r
3885 BFD01A36 0014FC5E LW V0, 20(S8)
\r
3886 BFD01A3A E9A6 SW V1, 24(V0)
\r
3890 1232: mtCOVERAGE_TEST_MARKER();
\r
3893 1235: /* If the task is in the blocked or suspended list we need do
\r
3894 1236: nothing more than change it's priority variable. However, if
\r
3895 1237: the task is in a ready list it needs to be removed and placed
\r
3896 1238: in the list appropriate to its new priority. */
\r
3897 1239: if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )
\r
3898 BFD01A3C 0014FC5E LW V0, 20(S8)
\r
3899 BFD01A3E 69A50014 LWX T5, 0(S4)
\r
3900 BFD01A40 69A5 LW V1, 20(V0)
\r
3901 BFD01A42 001CFC5E LW V0, 28(S8)
\r
3902 BFD01A46 2524 SLL V0, V0, 2
\r
3903 BFD01A48 2624 SLL A0, V0, 2
\r
3904 BFD01A4A 0644 ADDU A0, V0, A0
\r
3905 BFD01A4C BFD241A2 LUI V0, 0xBFD2
\r
3906 BFD01A4E 3042BFD2 LDC1 F30, 12354(S2)
\r
3907 BFD01A50 806C3042 ADDIU V0, V0, -32660
\r
3908 BFD01A54 0528 ADDU V0, A0, V0
\r
3909 BFD01A56 0004B443 BNE V1, V0, 0xBFD01A62
\r
3910 BFD01A58 0C000004 SLL ZERO, A0, 1
\r
3912 BFD01A5C ED01 LI V0, 1
\r
3913 BFD01A5E CC02 B 0xBFD01A64
\r
3915 BFD01A62 0C40 MOVE V0, ZERO
\r
3916 BFD01A64 003240E2 BEQZC V0, 0xBFD01ACC
\r
3918 1241: /* The task is currently in its ready list - remove before adding
\r
3919 1242: it to it's new ready list. As we are in a critical section we
\r
3920 1243: can do this even if the scheduler is suspended. */
\r
3921 1244: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
3922 BFD01A68 0014FC5E LW V0, 20(S8)
\r
3923 BFD01A6C 6D22 ADDIU V0, V0, 4
\r
3924 BFD01A6E 0C82 MOVE A0, V0
\r
3925 BFD01A70 00C877E8 JALS uxListRemove
\r
3926 BFD01A72 0C0000C8 SLL A2, T0, 1
\r
3928 BFD01A76 000B40A2 BNEZC V0, 0xBFD01A90
\r
3930 1246: /* It is known that the task is in its ready list so
\r
3931 1247: there is no need to check again and the port level
\r
3932 1248: reset macro can be called directly. */
\r
3933 1249: portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
\r
3934 BFD01A7A 001CFC5E LW V0, 28(S8)
\r
3935 BFD01A7E ED81 LI V1, 1
\r
3936 BFD01A80 10100062 SLLV V0, V0, V1
\r
3937 BFD01A82 441A1010 ADDI ZERO, S0, 17434
\r
3938 BFD01A84 441A NOT16 V1, V0
\r
3939 BFD01A86 8040FC5C LW V0, -32704(GP)
\r
3940 BFD01A8A 4493 AND16 V0, V1
\r
3941 BFD01A8C 8040F85C SW V0, -32704(GP)
\r
3945 1253: mtCOVERAGE_TEST_MARKER();
\r
3947 1255: prvAddTaskToReadyList( pxTCB );
\r
3948 BFD01A90 0014FC5E LW V0, 20(S8)
\r
3949 BFD01A94 692B LW V0, 44(V0)
\r
3950 BFD01A96 ED81 LI V1, 1
\r
3951 BFD01A98 18100062 SLLV V1, V0, V1
\r
3952 BFD01A9A FC5C1810 SB ZERO, -932(S0)
\r
3953 BFD01A9C 8040FC5C LW V0, -32704(GP)
\r
3954 BFD01AA0 44D3 OR16 V0, V1
\r
3955 BFD01AA2 8040F85C SW V0, -32704(GP)
\r
3956 BFD01AA6 0014FC5E LW V0, 20(S8)
\r
3957 BFD01AAA 692B LW V0, 44(V0)
\r
3958 BFD01AAC 2524 SLL V0, V0, 2
\r
3959 BFD01AAE 25A4 SLL V1, V0, 2
\r
3960 BFD01AB0 05B4 ADDU V1, V0, V1
\r
3961 BFD01AB2 BFD241A2 LUI V0, 0xBFD2
\r
3962 BFD01AB4 3042BFD2 LDC1 F30, 12354(S2)
\r
3963 BFD01AB6 806C3042 ADDIU V0, V0, -32660
\r
3964 BFD01ABA 05A6 ADDU V1, V1, V0
\r
3965 BFD01ABC 0014FC5E LW V0, 20(S8)
\r
3966 BFD01AC0 6D22 ADDIU V0, V0, 4
\r
3967 BFD01AC2 0C83 MOVE A0, V1
\r
3968 BFD01AC4 0CA2 MOVE A1, V0
\r
3969 BFD01AC6 3E4A77E8 JALS vListInsertEnd
\r
3970 BFD01AC8 0C003E4A LH S2, 3072(T2)
\r
3975 1259: mtCOVERAGE_TEST_MARKER();
\r
3978 1262: if( xYieldRequired == pdTRUE )
\r
3979 BFD01ACC 0010FC7E LW V1, 16(S8)
\r
3980 BFD01AD0 ED01 LI V0, 1
\r
3981 BFD01AD2 0011B443 BNE V1, V0, 0xBFD01AF8
\r
3982 BFD01AD4 0C000011 SLL ZERO, S1, 1
\r
3985 1264: taskYIELD_IF_USING_PREEMPTION();
\r
3986 BFD01AD8 4E5677E8 JALS ulPortGetCP0Cause
\r
3987 BFD01ADA 4E56 ADDIU S2, S2, -5
\r
3989 BFD01ADE 0020F85E SW V0, 32(S8)
\r
3990 BFD01AE2 0020FC5E LW V0, 32(S8)
\r
3991 BFD01AE6 01005042 ORI V0, V0, 256
\r
3992 BFD01AEA 0020F85E SW V0, 32(S8)
\r
3993 BFD01AEE 0020FC9E LW A0, 32(S8)
\r
3994 BFD01AF2 4E6677E8 JALS vPortSetCP0Cause
\r
3995 BFD01AF4 4E66 ADDIU S3, S3, 3
\r
4000 1268: mtCOVERAGE_TEST_MARKER();
\r
4003 1271: /* Remove compiler warning about unused variables when the port
\r
4004 1272: optimised task selection is not being used. */
\r
4005 1273: ( void ) uxPriorityUsedOnEntry;
\r
4008 1276: taskEXIT_CRITICAL();
\r
4009 BFD01AF8 40AA77E8 JALS vTaskExitCritical
\r
4010 BFD01AFA 0C0040AA BNEZC T2, 0xBFD032FE
\r
4013 BFD01AFE 0FBE MOVE SP, S8
\r
4014 BFD01B00 4BEB LW RA, 44(SP)
\r
4015 BFD01B02 4BCA LW S8, 40(SP)
\r
4016 BFD01B04 4C19 ADDIU SP, SP, 48
\r
4017 BFD01B06 459F JR16 RA
\r
4020 1279: #endif /* INCLUDE_vTaskPrioritySet */
\r
4021 1280: /*-----------------------------------------------------------*/
\r
4023 1282: #if ( INCLUDE_vTaskSuspend == 1 )
\r
4025 1284: void vTaskSuspend( TaskHandle_t xTaskToSuspend )
\r
4027 BFD0304C 4FF1 ADDIU SP, SP, -32
\r
4028 BFD0304E CBE7 SW RA, 28(SP)
\r
4029 BFD03050 CBC6 SW S8, 24(SP)
\r
4030 BFD03052 0FDD MOVE S8, SP
\r
4031 BFD03054 0020F89E SW A0, 32(S8)
\r
4032 1286: TCB_t *pxTCB;
\r
4034 1288: taskENTER_CRITICAL();
\r
4035 BFD03058 33B877E8 JALS vTaskEnterCritical
\r
4036 BFD0305A 0C0033B8 ADDIU SP, T8, 3072
\r
4039 1290: /* If null is passed in here then it is the running task that is
\r
4040 1291: being suspended. */
\r
4041 1292: pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
\r
4042 BFD0305E 0020FC5E LW V0, 32(S8)
\r
4043 BFD03062 000440A2 BNEZC V0, 0xBFD0306E
\r
4044 BFD03066 8030FC5C LW V0, -32720(GP)
\r
4045 BFD0306A CC03 B 0xBFD03072
\r
4047 BFD0306E 0020FC5E LW V0, 32(S8)
\r
4048 BFD03072 0010F85E SW V0, 16(S8)
\r
4050 1294: traceTASK_SUSPEND( pxTCB );
\r
4052 1296: /* Remove task from the ready/delayed list and place in the
\r
4053 1297: suspended list. */
\r
4054 1298: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
4055 BFD03076 0010FC5E LW V0, 16(S8)
\r
4056 BFD0307A 6D22 ADDIU V0, V0, 4
\r
4057 BFD0307C 0C82 MOVE A0, V0
\r
4058 BFD0307E 00C877E8 JALS uxListRemove
\r
4059 BFD03080 0C0000C8 SLL A2, T0, 1
\r
4061 BFD03084 001A40A2 BNEZC V0, 0xBFD030BC
\r
4063 1300: taskRESET_READY_PRIORITY( pxTCB->uxPriority );
\r
4064 BFD03088 0010FC5E LW V0, 16(S8)
\r
4065 BFD0308C 692B LW V0, 44(V0)
\r
4066 BFD0308E 2524 SLL V0, V0, 2
\r
4067 BFD03090 25A4 SLL V1, V0, 2
\r
4068 BFD03092 05B4 ADDU V1, V0, V1
\r
4069 BFD03094 BFD241A2 LUI V0, 0xBFD2
\r
4070 BFD03096 3042BFD2 LDC1 F30, 12354(S2)
\r
4071 BFD03098 806C3042 ADDIU V0, V0, -32660
\r
4072 BFD0309C 0526 ADDU V0, V1, V0
\r
4073 BFD0309E 6920 LW V0, 0(V0)
\r
4074 BFD030A0 000C40A2 BNEZC V0, 0xBFD030BC
\r
4075 BFD030A4 0010FC5E LW V0, 16(S8)
\r
4076 BFD030A8 692B LW V0, 44(V0)
\r
4077 BFD030AA ED81 LI V1, 1
\r
4078 BFD030AC 10100062 SLLV V0, V0, V1
\r
4079 BFD030AE 441A1010 ADDI ZERO, S0, 17434
\r
4080 BFD030B0 441A NOT16 V1, V0
\r
4081 BFD030B2 8040FC5C LW V0, -32704(GP)
\r
4082 BFD030B6 4493 AND16 V0, V1
\r
4083 BFD030B8 8040F85C SW V0, -32704(GP)
\r
4087 1304: mtCOVERAGE_TEST_MARKER();
\r
4090 1307: /* Is the task waiting on an event also? */
\r
4091 1308: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
\r
4092 BFD030BC 0010FC5E LW V0, 16(S8)
\r
4093 BFD030C0 692A LW V0, 40(V0)
\r
4094 BFD030C2 000740E2 BEQZC V0, 0xBFD030D4
\r
4096 1310: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
\r
4097 BFD030C6 0010FC5E LW V0, 16(S8)
\r
4098 BFD030C8 6D2C0010 EXT ZERO, S0, 20, 14
\r
4099 BFD030CA 6D2C ADDIU V0, V0, 24
\r
4100 BFD030CC 0C82 MOVE A0, V0
\r
4101 BFD030CE 00C877E8 JALS uxListRemove
\r
4102 BFD030D0 0C0000C8 SLL A2, T0, 1
\r
4107 1314: mtCOVERAGE_TEST_MARKER();
\r
4110 1317: vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );
\r
4111 BFD030D4 0010FC5E LW V0, 16(S8)
\r
4112 BFD030D8 6D22 ADDIU V0, V0, 4
\r
4113 BFD030DA BFD241A3 LUI V1, 0xBFD2
\r
4114 BFD030DC 3083BFD2 LDC1 F30, 12419(S2)
\r
4115 BFD030DE 80E43083 ADDIU A0, V1, -32540
\r
4116 BFD030E2 0CA2 MOVE A1, V0
\r
4117 BFD030E4 3E4A77E8 JALS vListInsertEnd
\r
4118 BFD030E6 0C003E4A LH S2, 3072(T2)
\r
4121 1319: taskEXIT_CRITICAL();
\r
4122 BFD030EA 40AA77E8 JALS vTaskExitCritical
\r
4123 BFD030EC 0C0040AA BNEZC T2, 0xBFD048F0
\r
4126 1321: if( pxTCB == pxCurrentTCB )
\r
4127 BFD030F0 8030FC5C LW V0, -32720(GP)
\r
4128 BFD030F4 0010FC7E LW V1, 16(S8)
\r
4129 BFD030F8 0036B443 BNE V1, V0, 0xBFD03168
\r
4130 BFD030FA 0C000036 SLL AT, S6, 1
\r
4133 1323: if( xSchedulerRunning != pdFALSE )
\r
4134 BFD030FE 8044FC5C LW V0, -32700(GP)
\r
4135 BFD03102 001F40E2 BEQZC V0, 0xBFD03144
\r
4137 1325: /* The current task has just been suspended. */
\r
4138 1326: configASSERT( uxSchedulerSuspended == 0 );
\r
4139 BFD03106 805CFC5C LW V0, -32676(GP)
\r
4140 BFD0310A 000940E2 BEQZC V0, 0xBFD03120
\r
4141 BFD0310E BFD141A2 LUI V0, 0xBFD1
\r
4142 BFD03110 3082BFD1 LDC1 F30, 12418(S1)
\r
4143 BFD03112 98103082 ADDIU A0, V0, -26608
\r
4144 BFD03114 30A09810 SWC1 F0, 12448(S0)
\r
4145 BFD03116 052E30A0 ADDIU A1, ZERO, 1326
\r
4146 BFD03118 052E ADDU V0, A3, V0
\r
4147 BFD0311A 4B7E77E8 JALS vAssertCalled
\r
4148 BFD0311C 4B7E LW K1, 120(SP)
\r
4150 1327: portYIELD_WITHIN_API();
\r
4151 BFD03120 4E5677E8 JALS ulPortGetCP0Cause
\r
4152 BFD03122 4E56 ADDIU S2, S2, -5
\r
4154 BFD03126 0014F85E SW V0, 20(S8)
\r
4155 BFD0312A 0014FC5E LW V0, 20(S8)
\r
4156 BFD0312E 01005042 ORI V0, V0, 256
\r
4157 BFD03132 0014F85E SW V0, 20(S8)
\r
4158 BFD03136 0014FC9E LW A0, 20(S8)
\r
4159 BFD0313A 4E6677E8 JALS vPortSetCP0Cause
\r
4160 BFD0313C 4E66 ADDIU S3, S3, 3
\r
4162 BFD03140 CC20 B 0xBFD03182
\r
4167 1331: /* The scheduler is not running, but the task that was pointed
\r
4168 1332: to by pxCurrentTCB has just been suspended and pxCurrentTCB
\r
4169 1333: must be adjusted to point to a different task. */
\r
4170 1334: if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
\r
4171 BFD03144 BFD241A2 LUI V0, 0xBFD2
\r
4172 BFD03146 FC62BFD2 LDC1 F30, -926(S2)
\r
4173 BFD03148 80E4FC62 LW V1, -32540(V0)
\r
4174 BFD0314C 8038FC5C LW V0, -32712(GP)
\r
4175 BFD03150 0005B443 BNE V1, V0, 0xBFD0315E
\r
4176 BFD03152 0C000005 SLL ZERO, A1, 1
\r
4179 1336: /* No other tasks are ready, so set pxCurrentTCB back to
\r
4180 1337: NULL so when the next task is created pxCurrentTCB will
\r
4181 1338: be set to point to it no matter what its relative priority
\r
4183 1340: pxCurrentTCB = NULL;
\r
4184 BFD03156 8030F81C SW ZERO, -32720(GP)
\r
4185 BFD0315A CC13 B 0xBFD03182
\r
4190 1344: vTaskSwitchContext();
\r
4191 BFD0315E 16DE77E8 JALS vTaskSwitchContext
\r
4192 BFD03160 0C0016DE LBU S6, 3072(S8)
\r
4194 BFD03164 CC0E B 0xBFD03182
\r
4201 1350: if( xSchedulerRunning != pdFALSE )
\r
4202 BFD03168 8044FC5C LW V0, -32700(GP)
\r
4203 BFD0316C 000940E2 BEQZC V0, 0xBFD03182
\r
4205 1352: /* A task other than the currently running task was suspended,
\r
4206 1353: reset the next expected unblock time in case it referred to the
\r
4207 1354: task that is now in the Suspended state. */
\r
4208 1355: taskENTER_CRITICAL();
\r
4209 BFD03170 33B877E8 JALS vTaskEnterCritical
\r
4210 BFD03172 0C0033B8 ADDIU SP, T8, 3072
\r
4213 1357: prvResetNextTaskUnblockTime();
\r
4214 BFD03176 47CA77E8 JALS prvResetNextTaskUnblockTime
\r
4217 1359: taskEXIT_CRITICAL();
\r
4218 BFD0317C 40AA77E8 JALS vTaskExitCritical
\r
4219 BFD0317E 0C0040AA BNEZC T2, 0xBFD04982
\r
4224 1363: mtCOVERAGE_TEST_MARKER();
\r
4228 BFD03182 0FBE MOVE SP, S8
\r
4229 BFD03184 4BE7 LW RA, 28(SP)
\r
4230 BFD03186 4BC6 LW S8, 24(SP)
\r
4231 BFD03188 4C11 ADDIU SP, SP, 32
\r
4232 BFD0318A 459F JR16 RA
\r
4235 1368: #endif /* INCLUDE_vTaskSuspend */
\r
4236 1369: /*-----------------------------------------------------------*/
\r
4238 1371: #if ( INCLUDE_vTaskSuspend == 1 )
\r
4240 1373: static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
\r
4242 BFD066DC 4FF1 ADDIU SP, SP, -32
\r
4243 BFD066DE CBE7 SW RA, 28(SP)
\r
4244 BFD066E0 CBC6 SW S8, 24(SP)
\r
4245 BFD066E2 0FDD MOVE S8, SP
\r
4246 BFD066E4 0020F89E SW A0, 32(S8)
\r
4247 1375: BaseType_t xReturn = pdFALSE;
\r
4248 BFD066E8 0010F81E SW ZERO, 16(S8)
\r
4249 1376: const TCB_t * const pxTCB = ( TCB_t * ) xTask;
\r
4250 BFD066EC 0020FC5E LW V0, 32(S8)
\r
4251 BFD066F0 0014F85E SW V0, 20(S8)
\r
4253 1378: /* Accesses xPendingReadyList so must be called from a critical
\r
4256 1381: /* It does not make sense to check if the calling task is suspended. */
\r
4257 1382: configASSERT( xTask );
\r
4258 BFD066F4 0020FC5E LW V0, 32(S8)
\r
4259 BFD066F8 000940A2 BNEZC V0, 0xBFD0670E
\r
4260 BFD066FC BFD141A2 LUI V0, 0xBFD1
\r
4261 BFD066FE 3082BFD1 LDC1 F30, 12418(S1)
\r
4262 BFD06700 98103082 ADDIU A0, V0, -26608
\r
4263 BFD06702 30A09810 SWC1 F0, 12448(S0)
\r
4264 BFD06704 056630A0 ADDIU A1, ZERO, 1382
\r
4265 BFD06706 0566 ADDU V0, V1, A2
\r
4266 BFD06708 4B7E77E8 JALS vAssertCalled
\r
4267 BFD0670A 4B7E LW K1, 120(SP)
\r
4270 1384: /* Is the task being resumed actually in the suspended list? */
\r
4271 1385: if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )
\r
4272 BFD0670E 0014FC5E LW V0, 20(S8)
\r
4273 BFD06710 69A50014 LWX T5, 0(S4)
\r
4274 BFD06712 69A5 LW V1, 20(V0)
\r
4275 BFD06714 BFD241A2 LUI V0, 0xBFD2
\r
4276 BFD06716 3042BFD2 LDC1 F30, 12354(S2)
\r
4277 BFD06718 80E43042 ADDIU V0, V0, -32540
\r
4278 BFD0671C 0004B443 BNE V1, V0, 0xBFD06728
\r
4279 BFD0671E 0C000004 SLL ZERO, A0, 1
\r
4281 BFD06722 ED01 LI V0, 1
\r
4282 BFD06724 CC02 B 0xBFD0672A
\r
4284 BFD06728 0C40 MOVE V0, ZERO
\r
4285 BFD0672A 001840E2 BEQZC V0, 0xBFD0675E
\r
4287 1387: /* Has the task already been resumed from within an ISR? */
\r
4288 1388: if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
\r
4289 BFD0672E 0014FC5E LW V0, 20(S8)
\r
4290 BFD06732 69AA LW V1, 40(V0)
\r
4291 BFD06734 BFD241A2 LUI V0, 0xBFD2
\r
4292 BFD06736 3042BFD2 LDC1 F30, 12354(S2)
\r
4293 BFD06738 80D03042 ADDIU V0, V0, -32560
\r
4294 BFD0673C 000F9443 BEQ V1, V0, 0xBFD0675E
\r
4295 BFD0673E 0C00000F SLL ZERO, T7, 1
\r
4298 1390: /* Is it in the suspended list because it is in the Suspended
\r
4299 1391: state, or because is is blocked with no timeout? */
\r
4300 1392: if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
\r
4301 BFD06742 0014FC5E LW V0, 20(S8)
\r
4302 BFD06746 692A LW V0, 40(V0)
\r
4303 BFD06748 000340A2 BNEZC V0, 0xBFD06752
\r
4304 BFD0674C ED01 LI V0, 1
\r
4305 BFD0674E CC02 B 0xBFD06754
\r
4307 BFD06752 0C40 MOVE V0, ZERO
\r
4308 BFD06754 000340E2 BEQZC V0, 0xBFD0675E
\r
4310 1394: xReturn = pdTRUE;
\r
4311 BFD06758 ED01 LI V0, 1
\r
4312 BFD0675A 0010F85E SW V0, 16(S8)
\r
4316 1398: mtCOVERAGE_TEST_MARKER();
\r
4321 1403: mtCOVERAGE_TEST_MARKER();
\r
4326 1408: mtCOVERAGE_TEST_MARKER();
\r
4329 1411: return xReturn;
\r
4330 BFD0675E 0010FC5E LW V0, 16(S8)
\r
4331 1412: } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
\r
4332 BFD06762 0FBE MOVE SP, S8
\r
4333 BFD06764 4BE7 LW RA, 28(SP)
\r
4334 BFD06766 4BC6 LW S8, 24(SP)
\r
4335 BFD06768 4C11 ADDIU SP, SP, 32
\r
4336 BFD0676A 459F JR16 RA
\r
4339 1414: #endif /* INCLUDE_vTaskSuspend */
\r
4340 1415: /*-----------------------------------------------------------*/
\r
4342 1417: #if ( INCLUDE_vTaskSuspend == 1 )
\r
4344 1419: void vTaskResume( TaskHandle_t xTaskToResume )
\r
4346 BFD040E4 4FF1 ADDIU SP, SP, -32
\r
4347 BFD040E6 CBE7 SW RA, 28(SP)
\r
4348 BFD040E8 CBC6 SW S8, 24(SP)
\r
4349 BFD040EA 0FDD MOVE S8, SP
\r
4350 BFD040EC 0020F89E SW A0, 32(S8)
\r
4351 1421: TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
\r
4352 BFD040F0 0020FC5E LW V0, 32(S8)
\r
4353 BFD040F4 0010F85E SW V0, 16(S8)
\r
4355 1423: /* It does not make sense to resume the calling task. */
\r
4356 1424: configASSERT( xTaskToResume );
\r
4357 BFD040F8 0020FC5E LW V0, 32(S8)
\r
4358 BFD040FC 000940A2 BNEZC V0, 0xBFD04112
\r
4359 BFD04100 BFD141A2 LUI V0, 0xBFD1
\r
4360 BFD04102 3082BFD1 LDC1 F30, 12418(S1)
\r
4361 BFD04104 98103082 ADDIU A0, V0, -26608
\r
4362 BFD04106 30A09810 SWC1 F0, 12448(S0)
\r
4363 BFD04108 059030A0 ADDIU A1, ZERO, 1424
\r
4364 BFD0410A 0590 ADDU V1, S0, S1
\r
4365 BFD0410C 4B7E77E8 JALS vAssertCalled
\r
4366 BFD0410E 4B7E LW K1, 120(SP)
\r
4369 1426: /* The parameter cannot be NULL as it is impossible to resume the
\r
4370 1427: currently executing task. */
\r
4371 1428: if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
\r
4372 BFD04112 0010FC5E LW V0, 16(S8)
\r
4373 BFD04116 005640E2 BEQZC V0, 0xBFD041C6
\r
4374 BFD0411A 8030FC5C LW V0, -32720(GP)
\r
4375 BFD0411E 0010FC7E LW V1, 16(S8)
\r
4376 BFD04122 00509443 BEQ V1, V0, 0xBFD041C6
\r
4377 BFD04124 0C000050 SLL V0, S0, 1
\r
4380 1430: taskENTER_CRITICAL();
\r
4381 BFD04128 33B877E8 JALS vTaskEnterCritical
\r
4382 BFD0412A 0C0033B8 ADDIU SP, T8, 3072
\r
4385 1432: if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )
\r
4386 BFD0412E 0010FC9E LW A0, 16(S8)
\r
4387 BFD04132 336E77E8 JALS prvTaskIsTaskSuspended
\r
4388 BFD04134 0C00336E ADDIU K1, T6, 3072
\r
4390 BFD04138 0C62 MOVE V1, V0
\r
4391 BFD0413A ED01 LI V0, 1
\r
4392 BFD0413C 0040B443 BNE V1, V0, 0xBFD041C0
\r
4393 BFD0413E 0C000040 SLL V0, ZERO, 1
\r
4396 1434: traceTASK_RESUME( pxTCB );
\r
4398 1436: /* As we are in a critical section we can access the ready
\r
4399 1437: lists even if the scheduler is suspended. */
\r
4400 1438: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
4401 BFD04142 0010FC5E LW V0, 16(S8)
\r
4402 BFD04146 6D22 ADDIU V0, V0, 4
\r
4403 BFD04148 0C82 MOVE A0, V0
\r
4404 BFD0414A 00C877E8 JALS uxListRemove
\r
4405 BFD0414C 0C0000C8 SLL A2, T0, 1
\r
4407 1439: prvAddTaskToReadyList( pxTCB );
\r
4408 BFD04150 0010FC5E LW V0, 16(S8)
\r
4409 BFD04154 692B LW V0, 44(V0)
\r
4410 BFD04156 ED81 LI V1, 1
\r
4411 BFD04158 18100062 SLLV V1, V0, V1
\r
4412 BFD0415A FC5C1810 SB ZERO, -932(S0)
\r
4413 BFD0415C 8040FC5C LW V0, -32704(GP)
\r
4414 BFD04160 44D3 OR16 V0, V1
\r
4415 BFD04162 8040F85C SW V0, -32704(GP)
\r
4416 BFD04166 0010FC5E LW V0, 16(S8)
\r
4417 BFD0416A 692B LW V0, 44(V0)
\r
4418 BFD0416C 2524 SLL V0, V0, 2
\r
4419 BFD0416E 25A4 SLL V1, V0, 2
\r
4420 BFD04170 05B4 ADDU V1, V0, V1
\r
4421 BFD04172 BFD241A2 LUI V0, 0xBFD2
\r
4422 BFD04174 3042BFD2 LDC1 F30, 12354(S2)
\r
4423 BFD04176 806C3042 ADDIU V0, V0, -32660
\r
4424 BFD0417A 05A6 ADDU V1, V1, V0
\r
4425 BFD0417C 0010FC5E LW V0, 16(S8)
\r
4426 BFD04180 6D22 ADDIU V0, V0, 4
\r
4427 BFD04182 0C83 MOVE A0, V1
\r
4428 BFD04184 0CA2 MOVE A1, V0
\r
4429 BFD04186 3E4A77E8 JALS vListInsertEnd
\r
4430 BFD04188 0C003E4A LH S2, 3072(T2)
\r
4433 1441: /* We may have just resumed a higher priority task. */
\r
4434 1442: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
\r
4435 BFD0418C 0010FC5E LW V0, 16(S8)
\r
4436 BFD04190 69AB LW V1, 44(V0)
\r
4437 BFD04192 8030FC5C LW V0, -32720(GP)
\r
4438 BFD04196 692B LW V0, 44(V0)
\r
4439 BFD04198 13900043 SLTU V0, V1, V0
\r
4440 BFD0419A 40A21390 ADDI GP, S0, 16546
\r
4441 BFD0419C 001040A2 BNEZC V0, 0xBFD041C0
\r
4443 1444: /* This yield may not cause the task just resumed to run,
\r
4444 1445: but will leave the lists in the correct state for the
\r
4445 1446: next yield. */
\r
4446 1447: taskYIELD_IF_USING_PREEMPTION();
\r
4447 BFD041A0 4E5677E8 JALS ulPortGetCP0Cause
\r
4448 BFD041A2 4E56 ADDIU S2, S2, -5
\r
4450 BFD041A6 0014F85E SW V0, 20(S8)
\r
4451 BFD041AA 0014FC5E LW V0, 20(S8)
\r
4452 BFD041AE 01005042 ORI V0, V0, 256
\r
4453 BFD041B2 0014F85E SW V0, 20(S8)
\r
4454 BFD041B6 0014FC9E LW A0, 20(S8)
\r
4455 BFD041BA 4E6677E8 JALS vPortSetCP0Cause
\r
4456 BFD041BC 4E66 ADDIU S3, S3, 3
\r
4461 1451: mtCOVERAGE_TEST_MARKER();
\r
4466 1456: mtCOVERAGE_TEST_MARKER();
\r
4469 1459: taskEXIT_CRITICAL();
\r
4470 BFD041C0 40AA77E8 JALS vTaskExitCritical
\r
4471 BFD041C2 0C0040AA BNEZC T2, 0xBFD059C6
\r
4476 1463: mtCOVERAGE_TEST_MARKER();
\r
4479 BFD041C6 0FBE MOVE SP, S8
\r
4480 BFD041C8 4BE7 LW RA, 28(SP)
\r
4481 BFD041CA 4BC6 LW S8, 24(SP)
\r
4482 BFD041CC 4C11 ADDIU SP, SP, 32
\r
4483 BFD041CE 459F JR16 RA
\r
4486 1467: #endif /* INCLUDE_vTaskSuspend */
\r
4488 1469: /*-----------------------------------------------------------*/
\r
4490 1471: #if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
\r
4492 1473: BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
\r
4494 BFD041D4 4FED ADDIU SP, SP, -40
\r
4495 BFD041D6 CBE9 SW RA, 36(SP)
\r
4496 BFD041D8 CBC8 SW S8, 32(SP)
\r
4497 BFD041DA 0FDD MOVE S8, SP
\r
4498 BFD041DC 0028F89E SW A0, 40(S8)
\r
4499 1475: BaseType_t xYieldRequired = pdFALSE;
\r
4500 BFD041E0 0010F81E SW ZERO, 16(S8)
\r
4501 1476: TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
\r
4502 BFD041E4 0028FC5E LW V0, 40(S8)
\r
4503 BFD041E8 0014F85E SW V0, 20(S8)
\r
4504 1477: UBaseType_t uxSavedInterruptStatus;
\r
4506 1479: configASSERT( xTaskToResume );
\r
4507 BFD041EC 0028FC5E LW V0, 40(S8)
\r
4508 BFD041F0 000940A2 BNEZC V0, 0xBFD04206
\r
4509 BFD041F4 BFD141A2 LUI V0, 0xBFD1
\r
4510 BFD041F6 3082BFD1 LDC1 F30, 12418(S1)
\r
4511 BFD041F8 98103082 ADDIU A0, V0, -26608
\r
4512 BFD041FA 30A09810 SWC1 F0, 12448(S0)
\r
4513 BFD041FC 05C730A0 ADDIU A1, ZERO, 1479
\r
4514 BFD041FE 05C7 SUBU V1, V1, A0
\r
4515 BFD04200 4B7E77E8 JALS vAssertCalled
\r
4516 BFD04202 4B7E LW K1, 120(SP)
\r
4519 1481: /* RTOS ports that support interrupt nesting have the concept of a
\r
4520 1482: maximum system call (or maximum API call) interrupt priority.
\r
4521 1483: Interrupts that are above the maximum system call priority are keep
\r
4522 1484: permanently enabled, even when the RTOS kernel is in a critical section,
\r
4523 1485: but cannot make any calls to FreeRTOS API functions. If configASSERT()
\r
4524 1486: is defined in FreeRTOSConfig.h then
\r
4525 1487: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
4526 1488: failure if a FreeRTOS API function is called from an interrupt that has
\r
4527 1489: been assigned a priority above the configured maximum system call
\r
4528 1490: priority. Only FreeRTOS functions that end in FromISR can be called
\r
4529 1491: from interrupts that have been assigned a priority at or (logically)
\r
4530 1492: below the maximum system call interrupt priority. FreeRTOS maintains a
\r
4531 1493: separate interrupt safe API to ensure interrupt entry is as fast and as
\r
4532 1494: simple as possible. More information (albeit Cortex-M specific) is
\r
4533 1495: provided on the following link:
\r
4534 1496: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
4535 1497: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
4537 1499: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
4538 BFD04206 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
4540 BFD0420C 0018F85E SW V0, 24(S8)
\r
4542 1501: if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )
\r
4543 BFD04210 0014FC9E LW A0, 20(S8)
\r
4544 BFD04214 336E77E8 JALS prvTaskIsTaskSuspended
\r
4545 BFD04216 0C00336E ADDIU K1, T6, 3072
\r
4547 BFD0421A 0C62 MOVE V1, V0
\r
4548 BFD0421C ED01 LI V0, 1
\r
4549 BFD0421E 0044B443 BNE V1, V0, 0xBFD042AA
\r
4550 BFD04220 0C000044 SLL V0, A0, 1
\r
4553 1503: traceTASK_RESUME_FROM_ISR( pxTCB );
\r
4555 1505: /* Check the ready lists can be accessed. */
\r
4556 1506: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
\r
4557 BFD04224 805CFC5C LW V0, -32676(GP)
\r
4558 BFD04228 003440A2 BNEZC V0, 0xBFD04294
\r
4560 1508: /* Ready lists can be accessed so move the task from the
\r
4561 1509: suspended list to the ready list directly. */
\r
4562 1510: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
\r
4563 BFD0422C 0014FC5E LW V0, 20(S8)
\r
4564 BFD04230 69AB LW V1, 44(V0)
\r
4565 BFD04232 8030FC5C LW V0, -32720(GP)
\r
4566 BFD04236 692B LW V0, 44(V0)
\r
4567 BFD04238 13900043 SLTU V0, V1, V0
\r
4568 BFD0423A 40A21390 ADDI GP, S0, 16546
\r
4569 BFD0423C 000340A2 BNEZC V0, 0xBFD04246
\r
4571 1512: xYieldRequired = pdTRUE;
\r
4572 BFD04240 ED01 LI V0, 1
\r
4573 BFD04242 0010F85E SW V0, 16(S8)
\r
4577 1516: mtCOVERAGE_TEST_MARKER();
\r
4580 1519: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
4581 BFD04246 0014FC5E LW V0, 20(S8)
\r
4582 BFD0424A 6D22 ADDIU V0, V0, 4
\r
4583 BFD0424C 0C82 MOVE A0, V0
\r
4584 BFD0424E 00C877E8 JALS uxListRemove
\r
4585 BFD04250 0C0000C8 SLL A2, T0, 1
\r
4587 1520: prvAddTaskToReadyList( pxTCB );
\r
4588 BFD04254 0014FC5E LW V0, 20(S8)
\r
4589 BFD04258 692B LW V0, 44(V0)
\r
4590 BFD0425A ED81 LI V1, 1
\r
4591 BFD0425C 18100062 SLLV V1, V0, V1
\r
4592 BFD0425E FC5C1810 SB ZERO, -932(S0)
\r
4593 BFD04260 8040FC5C LW V0, -32704(GP)
\r
4594 BFD04264 44D3 OR16 V0, V1
\r
4595 BFD04266 8040F85C SW V0, -32704(GP)
\r
4596 BFD0426A 0014FC5E LW V0, 20(S8)
\r
4597 BFD0426E 692B LW V0, 44(V0)
\r
4598 BFD04270 2524 SLL V0, V0, 2
\r
4599 BFD04272 25A4 SLL V1, V0, 2
\r
4600 BFD04274 05B4 ADDU V1, V0, V1
\r
4601 BFD04276 BFD241A2 LUI V0, 0xBFD2
\r
4602 BFD04278 3042BFD2 LDC1 F30, 12354(S2)
\r
4603 BFD0427A 806C3042 ADDIU V0, V0, -32660
\r
4604 BFD0427E 05A6 ADDU V1, V1, V0
\r
4605 BFD04280 0014FC5E LW V0, 20(S8)
\r
4606 BFD04284 6D22 ADDIU V0, V0, 4
\r
4607 BFD04286 0C83 MOVE A0, V1
\r
4608 BFD04288 0CA2 MOVE A1, V0
\r
4609 BFD0428A 3E4A77E8 JALS vListInsertEnd
\r
4610 BFD0428C 0C003E4A LH S2, 3072(T2)
\r
4612 BFD04290 CC0C B 0xBFD042AA
\r
4617 1524: /* The delayed or ready lists cannot be accessed so the task
\r
4618 1525: is held in the pending ready list until the scheduler is
\r
4619 1526: unsuspended. */
\r
4620 1527: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
\r
4621 BFD04294 0014FC5E LW V0, 20(S8)
\r
4622 BFD04296 6D2C0014 EXT ZERO, S4, 20, 14
\r
4623 BFD04298 6D2C ADDIU V0, V0, 24
\r
4624 BFD0429A BFD241A3 LUI V1, 0xBFD2
\r
4625 BFD0429C 3083BFD2 LDC1 F30, 12419(S2)
\r
4626 BFD0429E 80D03083 ADDIU A0, V1, -32560
\r
4627 BFD042A2 0CA2 MOVE A1, V0
\r
4628 BFD042A4 3E4A77E8 JALS vListInsertEnd
\r
4629 BFD042A6 0C003E4A LH S2, 3072(T2)
\r
4635 1532: mtCOVERAGE_TEST_MARKER();
\r
4638 1535: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
4639 BFD042AA 0018FC9E LW A0, 24(S8)
\r
4640 BFD042AE 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
4641 BFD042B0 4D5E ADDIU T2, T2, -1
\r
4644 1537: return xYieldRequired;
\r
4645 BFD042B4 0010FC5E LW V0, 16(S8)
\r
4647 BFD042B8 0FBE MOVE SP, S8
\r
4648 BFD042BA 4BE9 LW RA, 36(SP)
\r
4649 BFD042BC 4BC8 LW S8, 32(SP)
\r
4650 BFD042BE 4C15 ADDIU SP, SP, 40
\r
4651 BFD042C0 459F JR16 RA
\r
4654 1540: #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
\r
4655 1541: /*-----------------------------------------------------------*/
\r
4657 1543: void vTaskStartScheduler( void )
\r
4659 BFD04AC0 4FE9 ADDIU SP, SP, -48
\r
4660 BFD04AC2 CBEB SW RA, 44(SP)
\r
4661 BFD04AC4 CBCA SW S8, 40(SP)
\r
4662 BFD04AC6 0FDD MOVE S8, SP
\r
4663 1545: BaseType_t xReturn;
\r
4665 1547: /* Add the idle task at the lowest priority. */
\r
4666 1548: #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
\r
4668 1550: /* Create the idle task, storing its handle in xIdleTaskHandle so it can
\r
4669 1551: be returned by the xTaskGetIdleTaskHandle() function. */
\r
4670 1552: xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
\r
4674 1556: /* Create the idle task without storing its handle. */
\r
4675 1557: xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
\r
4676 BFD04AC8 C804 SW ZERO, 16(SP)
\r
4677 BFD04ACA C805 SW ZERO, 20(SP)
\r
4678 BFD04ACC C806 SW ZERO, 24(SP)
\r
4679 BFD04ACE C807 SW ZERO, 28(SP)
\r
4680 BFD04AD0 BFD141A2 LUI V0, 0xBFD1
\r
4681 BFD04AD2 3082BFD1 LDC1 F30, 12418(S1)
\r
4682 BFD04AD4 8BC53082 ADDIU A0, V0, -29755
\r
4683 BFD04AD6 8BC5 SB A3, 5(A0)
\r
4684 BFD04AD8 BFD141A2 LUI V0, 0xBFD1
\r
4685 BFD04ADA 30A2BFD1 LDC1 F30, 12450(S1)
\r
4686 BFD04ADC 982830A2 ADDIU A1, V0, -26584
\r
4687 BFD04ADE 30C09828 SWC1 F1, 12480(T0)
\r
4688 BFD04AE0 00BE30C0 ADDIU A2, ZERO, 190
\r
4689 BFD04AE4 0CE0 MOVE A3, ZERO
\r
4690 BFD04AE6 0A9A77E8 JALS xTaskGenericCreate
\r
4691 BFD04AE8 0A9A LBU A1, 10(S1)
\r
4693 BFD04AEC 0020F85E SW V0, 32(S8)
\r
4695 1559: #endif /* INCLUDE_xTaskGetIdleTaskHandle */
\r
4697 1561: #if ( configUSE_TIMERS == 1 )
\r
4699 1563: if( xReturn == pdPASS )
\r
4700 BFD04AF0 0020FC7E LW V1, 32(S8)
\r
4701 BFD04AF4 ED01 LI V0, 1
\r
4702 BFD04AF6 0006B443 BNE V1, V0, 0xBFD04B06
\r
4703 BFD04AF8 0C000006 SLL ZERO, A2, 1
\r
4706 1565: xReturn = xTimerCreateTimerTask();
\r
4707 BFD04AFC 3D3677E8 JALS xTimerCreateTimerTask
\r
4708 BFD04AFE 0C003D36 LH T1, 3072(S6)
\r
4710 BFD04B02 0020F85E SW V0, 32(S8)
\r
4714 1569: mtCOVERAGE_TEST_MARKER();
\r
4717 1572: #endif /* configUSE_TIMERS */
\r
4719 1574: if( xReturn == pdPASS )
\r
4720 BFD04B06 0020FC7E LW V1, 32(S8)
\r
4721 BFD04B0A ED01 LI V0, 1
\r
4722 BFD04B0C 0031B443 BNE V1, V0, 0xBFD04B72
\r
4723 BFD04B0E 0C000031 SLL AT, S1, 1
\r
4726 1576: /* Interrupts are turned off here, to ensure a tick does not occur
\r
4727 1577: before or during the call to xPortStartScheduler(). The stacks of
\r
4728 1578: the created tasks contain a status word with interrupts switched on
\r
4729 1579: so interrupts will automatically get re-enabled when the first task
\r
4730 1580: starts to run. */
\r
4731 1581: portDISABLE_INTERRUPTS();
\r
4732 BFD04B12 4E3677E8 JALS ulPortGetCP0Status
\r
4733 BFD04B14 4E36 ADDIU S1, S1, -5
\r
4735 BFD04B18 0024F85E SW V0, 36(S8)
\r
4736 BFD04B1C 0024FC7E LW V1, 36(S8)
\r
4737 BFD04B20 000141A2 LUI V0, 0x1
\r
4738 BFD04B24 FC005042 ORI V0, V0, -1024
\r
4739 BFD04B26 4493FC00 LW ZERO, 17555(ZERO)
\r
4740 BFD04B28 4493 AND16 V0, V1
\r
4741 BFD04B2A 50400042 SRL V0, V0, 10
\r
4742 BFD04B2C B0425040 ORI V0, ZERO, -20414
\r
4743 BFD04B2E 0003B042 SLTIU V0, V0, 3
\r
4744 BFD04B32 001140E2 BEQZC V0, 0xBFD04B58
\r
4745 BFD04B36 0024FC7E LW V1, 36(S8)
\r
4746 BFD04B3A FFFE41A2 LUI V0, 0xFFFE
\r
4747 BFD04B3C 5042FFFE LW RA, 20546(S8)
\r
4748 BFD04B3E 03FF5042 ORI V0, V0, 1023
\r
4749 BFD04B42 4493 AND16 V0, V1
\r
4750 BFD04B44 0024F85E SW V0, 36(S8)
\r
4751 BFD04B48 0024FC5E LW V0, 36(S8)
\r
4752 BFD04B4C 0C005042 ORI V0, V0, 3072
\r
4754 BFD04B50 0C82 MOVE A0, V0
\r
4755 BFD04B52 4E4677E8 JALS vPortSetCP0Status
\r
4756 BFD04B54 4E46 ADDIU S2, S2, 3
\r
4759 1583: #if ( configUSE_NEWLIB_REENTRANT == 1 )
\r
4761 1585: /* Switch Newlib's _impure_ptr variable to point to the _reent
\r
4762 1586: structure specific to the task that will run first. */
\r
4763 1587: _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
\r
4765 1589: #endif /* configUSE_NEWLIB_REENTRANT */
\r
4767 1591: xNextTaskUnblockTime = portMAX_DELAY;
\r
4768 BFD04B58 ED7F LI V0, -1
\r
4769 BFD04B5A 8058F85C SW V0, -32680(GP)
\r
4770 1592: xSchedulerRunning = pdTRUE;
\r
4771 BFD04B5E ED01 LI V0, 1
\r
4772 BFD04B60 8044F85C SW V0, -32700(GP)
\r
4773 1593: xTickCount = ( TickType_t ) 0U;
\r
4774 BFD04B64 803CF81C SW ZERO, -32708(GP)
\r
4776 1595: /* If configGENERATE_RUN_TIME_STATS is defined then the following
\r
4777 1596: macro must be defined to configure the timer/counter used to generate
\r
4778 1597: the run time counter time base. */
\r
4779 1598: portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
\r
4781 1600: /* Setting up the timer tick is hardware specific and thus in the
\r
4782 1601: portable interface. */
\r
4783 1602: if( xPortStartScheduler() != pdFALSE )
\r
4784 BFD04B68 344C77E8 JALS xPortStartScheduler
\r
4785 BFD04B6A 0C00344C LHU V0, 3072(T4)
\r
4787 BFD04B6E CC0E B 0xBFD04B8C
\r
4790 1604: /* Should not reach here as if the scheduler is running the
\r
4791 1605: function will not return. */
\r
4795 1609: /* Should only reach here if a task calls xTaskEndScheduler(). */
\r
4800 1614: /* This line will only be reached if the kernel could not be started,
\r
4801 1615: because there was not enough FreeRTOS heap to create the idle task
\r
4802 1616: or the timer task. */
\r
4803 1617: configASSERT( xReturn );
\r
4804 BFD04B72 0020FC5E LW V0, 32(S8)
\r
4805 BFD04B76 000940A2 BNEZC V0, 0xBFD04B8C
\r
4806 BFD04B7A BFD141A2 LUI V0, 0xBFD1
\r
4807 BFD04B7C 3082BFD1 LDC1 F30, 12418(S1)
\r
4808 BFD04B7E 98103082 ADDIU A0, V0, -26608
\r
4809 BFD04B80 30A09810 SWC1 F0, 12448(S0)
\r
4810 BFD04B82 065130A0 ADDIU A1, ZERO, 1617
\r
4811 BFD04B84 0651 SUBU A0, S0, A1
\r
4812 BFD04B86 4B7E77E8 JALS vAssertCalled
\r
4813 BFD04B88 4B7E LW K1, 120(SP)
\r
4817 BFD04B8C 0FBE MOVE SP, S8
\r
4818 BFD04B8E 4BEB LW RA, 44(SP)
\r
4819 BFD04B90 4BCA LW S8, 40(SP)
\r
4820 BFD04B92 4C19 ADDIU SP, SP, 48
\r
4821 BFD04B94 459F JR16 RA
\r
4823 1620: /*-----------------------------------------------------------*/
\r
4825 1622: void vTaskEndScheduler( void )
\r
4827 BFD07F00 4FF1 ADDIU SP, SP, -32
\r
4828 BFD07F02 CBE7 SW RA, 28(SP)
\r
4829 BFD07F04 CBC6 SW S8, 24(SP)
\r
4830 BFD07F06 0FDD MOVE S8, SP
\r
4831 1624: /* Stop the scheduler interrupts and call the portable scheduler end
\r
4832 1625: routine so the original ISRs can be restored if necessary. The port
\r
4833 1626: layer must ensure interrupts enable bit is left in the correct state. */
\r
4834 1627: portDISABLE_INTERRUPTS();
\r
4835 BFD07F08 4E3677E8 JALS ulPortGetCP0Status
\r
4836 BFD07F0A 4E36 ADDIU S1, S1, -5
\r
4838 BFD07F0E 0010F85E SW V0, 16(S8)
\r
4839 BFD07F12 0010FC7E LW V1, 16(S8)
\r
4840 BFD07F16 000141A2 LUI V0, 0x1
\r
4841 BFD07F1A FC005042 ORI V0, V0, -1024
\r
4842 BFD07F1C 4493FC00 LW ZERO, 17555(ZERO)
\r
4843 BFD07F1E 4493 AND16 V0, V1
\r
4844 BFD07F20 50400042 SRL V0, V0, 10
\r
4845 BFD07F22 B0425040 ORI V0, ZERO, -20414
\r
4846 BFD07F24 0003B042 SLTIU V0, V0, 3
\r
4847 BFD07F28 001140E2 BEQZC V0, 0xBFD07F4E
\r
4848 BFD07F2C 0010FC7E LW V1, 16(S8)
\r
4849 BFD07F30 FFFE41A2 LUI V0, 0xFFFE
\r
4850 BFD07F32 5042FFFE LW RA, 20546(S8)
\r
4851 BFD07F34 03FF5042 ORI V0, V0, 1023
\r
4852 BFD07F38 4493 AND16 V0, V1
\r
4853 BFD07F3A 0010F85E SW V0, 16(S8)
\r
4854 BFD07F3E 0010FC5E LW V0, 16(S8)
\r
4855 BFD07F42 0C005042 ORI V0, V0, 3072
\r
4857 BFD07F46 0C82 MOVE A0, V0
\r
4858 BFD07F48 4E4677E8 JALS vPortSetCP0Status
\r
4859 BFD07F4A 4E46 ADDIU S2, S2, 3
\r
4861 1628: xSchedulerRunning = pdFALSE;
\r
4862 BFD07F4E 8044F81C SW ZERO, -32700(GP)
\r
4863 1629: vPortEndScheduler();
\r
4864 BFD07F52 4BD477E8 JALS vPortEndScheduler
\r
4865 BFD07F54 4BD4 LW S8, 80(SP)
\r
4868 BFD07F58 0FBE MOVE SP, S8
\r
4869 BFD07F5A 4BE7 LW RA, 28(SP)
\r
4870 BFD07F5C 4BC6 LW S8, 24(SP)
\r
4871 BFD07F5E 4C11 ADDIU SP, SP, 32
\r
4872 BFD07F60 459F JR16 RA
\r
4874 1631: /*----------------------------------------------------------*/
\r
4876 1633: void vTaskSuspendAll( void )
\r
4878 BFD09DE8 4FB0 ADDIU SP, SP, -8
\r
4879 BFD09DEA CBC1 SW S8, 4(SP)
\r
4880 BFD09DEC 0FDD MOVE S8, SP
\r
4881 1635: /* A critical section is not required as the variable is of type
\r
4882 1636: BaseType_t. Please read Richard Barry's reply in the following link to a
\r
4883 1637: post in the FreeRTOS support forum before reporting this as a bug! -
\r
4884 1638: http://goo.gl/wu4acr */
\r
4885 1639: ++uxSchedulerSuspended;
\r
4886 BFD09DEE 805CFC5C LW V0, -32676(GP)
\r
4887 BFD09DF2 6D20 ADDIU V0, V0, 1
\r
4888 BFD09DF4 805CF85C SW V0, -32676(GP)
\r
4890 BFD09DF8 0FBE MOVE SP, S8
\r
4891 BFD09DFA 4BC1 LW S8, 4(SP)
\r
4892 BFD09DFC 4C05 ADDIU SP, SP, 8
\r
4893 BFD09DFE 459F JR16 RA
\r
4895 1641: /*----------------------------------------------------------*/
\r
4897 1643: #if ( configUSE_TICKLESS_IDLE != 0 )
\r
4899 1645: static TickType_t prvGetExpectedIdleTime( void )
\r
4901 1647: TickType_t xReturn;
\r
4903 1649: if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
\r
4905 1651: xReturn = 0;
\r
4907 1653: else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
\r
4909 1655: /* There are other idle priority tasks in the ready state. If
\r
4910 1656: time slicing is used then the very next tick interrupt must be
\r
4911 1657: processed. */
\r
4912 1658: xReturn = 0;
\r
4916 1662: xReturn = xNextTaskUnblockTime - xTickCount;
\r
4919 1665: return xReturn;
\r
4922 1668: #endif /* configUSE_TICKLESS_IDLE */
\r
4923 1669: /*----------------------------------------------------------*/
\r
4925 1671: BaseType_t xTaskResumeAll( void )
\r
4927 BFD02B1C 4FED ADDIU SP, SP, -40
\r
4928 BFD02B1E CBE9 SW RA, 36(SP)
\r
4929 BFD02B20 CBC8 SW S8, 32(SP)
\r
4930 BFD02B22 0FDD MOVE S8, SP
\r
4931 1673: TCB_t *pxTCB;
\r
4932 1674: BaseType_t xAlreadyYielded = pdFALSE;
\r
4933 BFD02B24 0010F81E SW ZERO, 16(S8)
\r
4935 1676: /* If uxSchedulerSuspended is zero then this function does not match a
\r
4936 1677: previous call to vTaskSuspendAll(). */
\r
4937 1678: configASSERT( uxSchedulerSuspended );
\r
4938 BFD02B28 805CFC5C LW V0, -32676(GP)
\r
4939 BFD02B2C 000940A2 BNEZC V0, 0xBFD02B42
\r
4940 BFD02B30 BFD141A2 LUI V0, 0xBFD1
\r
4941 BFD02B32 3082BFD1 LDC1 F30, 12418(S1)
\r
4942 BFD02B34 98103082 ADDIU A0, V0, -26608
\r
4943 BFD02B36 30A09810 SWC1 F0, 12448(S0)
\r
4944 BFD02B38 068E30A0 ADDIU A1, ZERO, 1678
\r
4945 BFD02B3A 068E ADDU A1, A3, S0
\r
4946 BFD02B3C 4B7E77E8 JALS vAssertCalled
\r
4947 BFD02B3E 4B7E LW K1, 120(SP)
\r
4950 1680: /* It is possible that an ISR caused a task to be removed from an event
\r
4951 1681: list while the scheduler was suspended. If this was the case then the
\r
4952 1682: removed task will have been added to the xPendingReadyList. Once the
\r
4953 1683: scheduler has been resumed it is safe to move all the pending ready
\r
4954 1684: tasks from this list into their appropriate ready list. */
\r
4955 1685: taskENTER_CRITICAL();
\r
4956 BFD02B42 33B877E8 JALS vTaskEnterCritical
\r
4957 BFD02B44 0C0033B8 ADDIU SP, T8, 3072
\r
4960 1687: --uxSchedulerSuspended;
\r
4961 BFD02B48 805CFC5C LW V0, -32676(GP)
\r
4962 BFD02B4C 6D2E ADDIU V0, V0, -1
\r
4963 BFD02B4E 805CF85C SW V0, -32676(GP)
\r
4965 1689: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
\r
4966 BFD02B52 805CFC5C LW V0, -32676(GP)
\r
4967 BFD02B56 007D40A2 BNEZC V0, 0xBFD02C54
\r
4969 1691: if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
\r
4970 BFD02B5A 8038FC5C LW V0, -32712(GP)
\r
4971 BFD02B5E 007940E2 BEQZC V0, 0xBFD02C54
\r
4973 1693: /* Move any readied tasks from the pending list into the
\r
4974 1694: appropriate ready list. */
\r
4975 1695: while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
\r
4976 BFD02B62 CC42 B 0xBFD02BE8
\r
4978 BFD02BE8 BFD241A2 LUI V0, 0xBFD2
\r
4979 BFD02BEA FC42BFD2 LDC1 F30, -958(S2)
\r
4980 BFD02BEC 80D0FC42 LW V0, -32560(V0)
\r
4981 BFD02BF0 FFB940A2 BNEZC V0, 0xBFD02B66
\r
4982 BFD02BF2 FC5CFFB9 LW SP, -932(T9)
\r
4984 1697: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
\r
4985 BFD02B66 BFD241A2 LUI V0, 0xBFD2
\r
4986 BFD02B68 3042BFD2 LDC1 F30, 12354(S2)
\r
4987 BFD02B6A 80D03042 ADDIU V0, V0, -32560
\r
4988 BFD02B6E 6923 LW V0, 12(V0)
\r
4989 BFD02B70 6923 LW V0, 12(V0)
\r
4990 BFD02B72 0014F85E SW V0, 20(S8)
\r
4991 1698: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
\r
4992 BFD02B76 0014FC5E LW V0, 20(S8)
\r
4993 BFD02B78 6D2C0014 EXT ZERO, S4, 20, 14
\r
4994 BFD02B7A 6D2C ADDIU V0, V0, 24
\r
4995 BFD02B7C 0C82 MOVE A0, V0
\r
4996 BFD02B7E 00C877E8 JALS uxListRemove
\r
4997 BFD02B80 0C0000C8 SLL A2, T0, 1
\r
4999 1699: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
5000 BFD02B84 0014FC5E LW V0, 20(S8)
\r
5001 BFD02B88 6D22 ADDIU V0, V0, 4
\r
5002 BFD02B8A 0C82 MOVE A0, V0
\r
5003 BFD02B8C 00C877E8 JALS uxListRemove
\r
5004 BFD02B8E 0C0000C8 SLL A2, T0, 1
\r
5006 1700: prvAddTaskToReadyList( pxTCB );
\r
5007 BFD02B92 0014FC5E LW V0, 20(S8)
\r
5008 BFD02B96 692B LW V0, 44(V0)
\r
5009 BFD02B98 ED81 LI V1, 1
\r
5010 BFD02B9A 18100062 SLLV V1, V0, V1
\r
5011 BFD02B9C FC5C1810 SB ZERO, -932(S0)
\r
5012 BFD02B9E 8040FC5C LW V0, -32704(GP)
\r
5013 BFD02BA2 44D3 OR16 V0, V1
\r
5014 BFD02BA4 8040F85C SW V0, -32704(GP)
\r
5015 BFD02BA8 0014FC5E LW V0, 20(S8)
\r
5016 BFD02BAC 692B LW V0, 44(V0)
\r
5017 BFD02BAE 2524 SLL V0, V0, 2
\r
5018 BFD02BB0 25A4 SLL V1, V0, 2
\r
5019 BFD02BB2 05B4 ADDU V1, V0, V1
\r
5020 BFD02BB4 BFD241A2 LUI V0, 0xBFD2
\r
5021 BFD02BB6 3042BFD2 LDC1 F30, 12354(S2)
\r
5022 BFD02BB8 806C3042 ADDIU V0, V0, -32660
\r
5023 BFD02BBC 05A6 ADDU V1, V1, V0
\r
5024 BFD02BBE 0014FC5E LW V0, 20(S8)
\r
5025 BFD02BC2 6D22 ADDIU V0, V0, 4
\r
5026 BFD02BC4 0C83 MOVE A0, V1
\r
5027 BFD02BC6 0CA2 MOVE A1, V0
\r
5028 BFD02BC8 3E4A77E8 JALS vListInsertEnd
\r
5029 BFD02BCA 0C003E4A LH S2, 3072(T2)
\r
5032 1702: /* If the moved task has a priority higher than the current
\r
5033 1703: task then a yield must be performed. */
\r
5034 1704: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
\r
5035 BFD02BCE 0014FC5E LW V0, 20(S8)
\r
5036 BFD02BD2 69AB LW V1, 44(V0)
\r
5037 BFD02BD4 8030FC5C LW V0, -32720(GP)
\r
5038 BFD02BD8 692B LW V0, 44(V0)
\r
5039 BFD02BDA 13900043 SLTU V0, V1, V0
\r
5040 BFD02BDC 40A21390 ADDI GP, S0, 16546
\r
5041 BFD02BDE 000340A2 BNEZC V0, 0xBFD02BE8
\r
5043 1706: xYieldPending = pdTRUE;
\r
5044 BFD02BE2 ED01 LI V0, 1
\r
5045 BFD02BE4 804CF85C SW V0, -32692(GP)
\r
5049 1710: mtCOVERAGE_TEST_MARKER();
\r
5053 1714: /* If any ticks occurred while the scheduler was suspended then
\r
5054 1715: they should be processed now. This ensures the tick count does
\r
5055 1716: not slip, and that any delayed tasks are resumed at the correct
\r
5057 1718: if( uxPendedTicks > ( UBaseType_t ) 0U )
\r
5058 BFD02BF4 8048FC5C LW V0, -32696(GP)
\r
5059 BFD02BF8 001340E2 BEQZC V0, 0xBFD02C22
\r
5061 1720: while( uxPendedTicks > ( UBaseType_t ) 0U )
\r
5062 BFD02BFC CC0E B 0xBFD02C1A
\r
5064 BFD02C1A 8048FC5C LW V0, -32696(GP)
\r
5065 BFD02C1E FFEF40A2 BNEZC V0, 0xBFD02C00
\r
5066 BFD02C20 FC7CFFEF LW RA, -900(T7)
\r
5068 1722: if( xTaskIncrementTick() != pdFALSE )
\r
5069 BFD02C00 104077E8 JALS xTaskIncrementTick
\r
5070 BFD02C02 0C001040 ADDI V0, ZERO, 3072
\r
5072 BFD02C06 000340E2 BEQZC V0, 0xBFD02C10
\r
5074 1724: xYieldPending = pdTRUE;
\r
5075 BFD02C0A ED01 LI V0, 1
\r
5076 BFD02C0C 804CF85C SW V0, -32692(GP)
\r
5080 1728: mtCOVERAGE_TEST_MARKER();
\r
5082 1730: --uxPendedTicks;
\r
5083 BFD02C10 8048FC5C LW V0, -32696(GP)
\r
5084 BFD02C14 6D2E ADDIU V0, V0, -1
\r
5085 BFD02C16 8048F85C SW V0, -32696(GP)
\r
5090 1735: mtCOVERAGE_TEST_MARKER();
\r
5093 1738: if( xYieldPending == pdTRUE )
\r
5094 BFD02C22 804CFC7C LW V1, -32692(GP)
\r
5095 BFD02C26 ED01 LI V0, 1
\r
5096 BFD02C28 0014B443 BNE V1, V0, 0xBFD02C54
\r
5097 BFD02C2A 0C000014 SLL ZERO, S4, 1
\r
5100 1740: #if( configUSE_PREEMPTION != 0 )
\r
5102 1742: xAlreadyYielded = pdTRUE;
\r
5103 BFD02C2E ED01 LI V0, 1
\r
5104 BFD02C30 0010F85E SW V0, 16(S8)
\r
5107 1745: taskYIELD_IF_USING_PREEMPTION();
\r
5108 BFD02C34 4E5677E8 JALS ulPortGetCP0Cause
\r
5109 BFD02C36 4E56 ADDIU S2, S2, -5
\r
5111 BFD02C3A 0018F85E SW V0, 24(S8)
\r
5112 BFD02C3E 0018FC5E LW V0, 24(S8)
\r
5113 BFD02C42 01005042 ORI V0, V0, 256
\r
5114 BFD02C46 0018F85E SW V0, 24(S8)
\r
5115 BFD02C4A 0018FC9E LW A0, 24(S8)
\r
5116 BFD02C4E 4E6677E8 JALS vPortSetCP0Cause
\r
5117 BFD02C50 4E66 ADDIU S3, S3, 3
\r
5122 1749: mtCOVERAGE_TEST_MARKER();
\r
5128 1755: mtCOVERAGE_TEST_MARKER();
\r
5131 1758: taskEXIT_CRITICAL();
\r
5132 BFD02C54 40AA77E8 JALS vTaskExitCritical
\r
5133 BFD02C56 0C0040AA BNEZC T2, 0xBFD0445A
\r
5136 1760: return xAlreadyYielded;
\r
5137 BFD02C5A 0010FC5E LW V0, 16(S8)
\r
5139 BFD02C5E 0FBE MOVE SP, S8
\r
5140 BFD02C60 4BE9 LW RA, 36(SP)
\r
5141 BFD02C62 4BC8 LW S8, 32(SP)
\r
5142 BFD02C64 4C15 ADDIU SP, SP, 40
\r
5143 BFD02C66 459F JR16 RA
\r
5145 1762: /*-----------------------------------------------------------*/
\r
5147 1764: TickType_t xTaskGetTickCount( void )
\r
5149 BFD09994 4FF1 ADDIU SP, SP, -32
\r
5150 BFD09996 CBE7 SW RA, 28(SP)
\r
5151 BFD09998 CBC6 SW S8, 24(SP)
\r
5152 BFD0999A 0FDD MOVE S8, SP
\r
5153 1766: TickType_t xTicks;
\r
5155 1768: /* Critical section required if running on a 16 bit processor. */
\r
5156 1769: portTICK_TYPE_ENTER_CRITICAL();
\r
5157 BFD0999C 33B877E8 JALS vTaskEnterCritical
\r
5158 BFD0999E 0C0033B8 ADDIU SP, T8, 3072
\r
5161 1771: xTicks = xTickCount;
\r
5162 BFD099A2 803CFC5C LW V0, -32708(GP)
\r
5163 BFD099A6 0010F85E SW V0, 16(S8)
\r
5165 1773: portTICK_TYPE_EXIT_CRITICAL();
\r
5166 BFD099AA 40AA77E8 JALS vTaskExitCritical
\r
5167 BFD099AC 0C0040AA BNEZC T2, 0xBFD0B1B0
\r
5170 1775: return xTicks;
\r
5171 BFD099B0 0010FC5E LW V0, 16(S8)
\r
5173 BFD099B4 0FBE MOVE SP, S8
\r
5174 BFD099B6 4BE7 LW RA, 28(SP)
\r
5175 BFD099B8 4BC6 LW S8, 24(SP)
\r
5176 BFD099BA 4C11 ADDIU SP, SP, 32
\r
5177 BFD099BC 459F JR16 RA
\r
5179 1777: /*-----------------------------------------------------------*/
\r
5181 1779: TickType_t xTaskGetTickCountFromISR( void )
\r
5183 BFD09844 4FF1 ADDIU SP, SP, -32
\r
5184 BFD09846 CBE7 SW RA, 28(SP)
\r
5185 BFD09848 CBC6 SW S8, 24(SP)
\r
5186 BFD0984A 0FDD MOVE S8, SP
\r
5187 1781: TickType_t xReturn;
\r
5188 1782: UBaseType_t uxSavedInterruptStatus;
\r
5190 1784: /* RTOS ports that support interrupt nesting have the concept of a maximum
\r
5191 1785: system call (or maximum API call) interrupt priority. Interrupts that are
\r
5192 1786: above the maximum system call priority are kept permanently enabled, even
\r
5193 1787: when the RTOS kernel is in a critical section, but cannot make any calls to
\r
5194 1788: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
\r
5195 1789: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
5196 1790: failure if a FreeRTOS API function is called from an interrupt that has been
\r
5197 1791: assigned a priority above the configured maximum system call priority.
\r
5198 1792: Only FreeRTOS functions that end in FromISR can be called from interrupts
\r
5199 1793: that have been assigned a priority at or (logically) below the maximum
\r
5200 1794: system call interrupt priority. FreeRTOS maintains a separate interrupt
\r
5201 1795: safe API to ensure interrupt entry is as fast and as simple as possible.
\r
5202 1796: More information (albeit Cortex-M specific) is provided on the following
\r
5203 1797: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
5204 1798: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
5206 1800: uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
\r
5207 BFD0984C 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
5209 BFD09852 0010F85E SW V0, 16(S8)
\r
5211 1802: xReturn = xTickCount;
\r
5212 BFD09856 803CFC5C LW V0, -32708(GP)
\r
5213 BFD0985A 0014F85E SW V0, 20(S8)
\r
5215 1804: portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
5216 BFD0985E 0010FC9E LW A0, 16(S8)
\r
5217 BFD09862 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
5218 BFD09864 4D5E ADDIU T2, T2, -1
\r
5221 1806: return xReturn;
\r
5222 BFD09868 0014FC5E LW V0, 20(S8)
\r
5224 BFD0986C 0FBE MOVE SP, S8
\r
5225 BFD0986E 4BE7 LW RA, 28(SP)
\r
5226 BFD09870 4BC6 LW S8, 24(SP)
\r
5227 BFD09872 4C11 ADDIU SP, SP, 32
\r
5228 BFD09874 459F JR16 RA
\r
5230 1808: /*-----------------------------------------------------------*/
\r
5232 1810: UBaseType_t uxTaskGetNumberOfTasks( void )
\r
5234 BFD09E98 4FB0 ADDIU SP, SP, -8
\r
5235 BFD09E9A CBC1 SW S8, 4(SP)
\r
5236 BFD09E9C 0FDD MOVE S8, SP
\r
5237 1812: /* A critical section is not required because the variables are of type
\r
5238 1813: BaseType_t. */
\r
5239 1814: return uxCurrentNumberOfTasks;
\r
5240 BFD09E9E 8038FC5C LW V0, -32712(GP)
\r
5242 BFD09EA2 0FBE MOVE SP, S8
\r
5243 BFD09EA4 4BC1 LW S8, 4(SP)
\r
5244 BFD09EA6 4C05 ADDIU SP, SP, 8
\r
5245 BFD09EA8 459F JR16 RA
\r
5247 1816: /*-----------------------------------------------------------*/
\r
5249 1818: #if ( INCLUDE_pcTaskGetTaskName == 1 )
\r
5251 1820: char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
\r
5253 1822: TCB_t *pxTCB;
\r
5255 1824: /* If null is passed in here then the name of the calling task is being queried. */
\r
5256 1825: pxTCB = prvGetTCBFromHandle( xTaskToQuery );
\r
5257 1826: configASSERT( pxTCB );
\r
5258 1827: return &( pxTCB->pcTaskName[ 0 ] );
\r
5261 1830: #endif /* INCLUDE_pcTaskGetTaskName */
\r
5262 1831: /*-----------------------------------------------------------*/
\r
5264 1833: #if ( configUSE_TRACE_FACILITY == 1 )
\r
5266 1835: UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
\r
5268 1837: UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
\r
5270 1839: vTaskSuspendAll();
\r
5272 1841: /* Is there a space in the array for each task in the system? */
\r
5273 1842: if( uxArraySize >= uxCurrentNumberOfTasks )
\r
5275 1844: /* Fill in an TaskStatus_t structure with information on each
\r
5276 1845: task in the Ready state. */
\r
5280 1849: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
\r
5282 1851: } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
5284 1853: /* Fill in an TaskStatus_t structure with information on each
\r
5285 1854: task in the Blocked state. */
\r
5286 1855: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
\r
5287 1856: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
\r
5289 1858: #if( INCLUDE_vTaskDelete == 1 )
\r
5291 1860: /* Fill in an TaskStatus_t structure with information on
\r
5292 1861: each task that has been deleted but not yet cleaned up. */
\r
5293 1862: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
\r
5297 1866: #if ( INCLUDE_vTaskSuspend == 1 )
\r
5299 1868: /* Fill in an TaskStatus_t structure with information on
\r
5300 1869: each task in the Suspended state. */
\r
5301 1870: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
\r
5305 1874: #if ( configGENERATE_RUN_TIME_STATS == 1)
\r
5307 1876: if( pulTotalRunTime != NULL )
\r
5309 1878: #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
\r
5310 1879: portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
\r
5312 1881: *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
\r
5318 1887: if( pulTotalRunTime != NULL )
\r
5320 1889: *pulTotalRunTime = 0;
\r
5327 1896: mtCOVERAGE_TEST_MARKER();
\r
5330 1899: ( void ) xTaskResumeAll();
\r
5332 1901: return uxTask;
\r
5335 1904: #endif /* configUSE_TRACE_FACILITY */
\r
5336 1905: /*----------------------------------------------------------*/
\r
5338 1907: #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
\r
5340 1909: TaskHandle_t xTaskGetIdleTaskHandle( void )
\r
5342 1911: /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
\r
5343 1912: started, then xIdleTaskHandle will be NULL. */
\r
5344 1913: configASSERT( ( xIdleTaskHandle != NULL ) );
\r
5345 1914: return xIdleTaskHandle;
\r
5348 1917: #endif /* INCLUDE_xTaskGetIdleTaskHandle */
\r
5349 1918: /*----------------------------------------------------------*/
\r
5351 1920: /* This conditional compilation should use inequality to 0, not equality to 1.
\r
5352 1921: This is to ensure vTaskStepTick() is available when user defined low power mode
\r
5353 1922: implementations require configUSE_TICKLESS_IDLE to be set to a value other than
\r
5355 1924: #if ( configUSE_TICKLESS_IDLE != 0 )
\r
5357 1926: void vTaskStepTick( const TickType_t xTicksToJump )
\r
5359 1928: /* Correct the tick count value after a period during which the tick
\r
5360 1929: was suppressed. Note this does *not* call the tick hook function for
\r
5361 1930: each stepped tick. */
\r
5362 1931: configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
\r
5363 1932: xTickCount += xTicksToJump;
\r
5364 1933: traceINCREASE_TICK_COUNT( xTicksToJump );
\r
5367 1936: #endif /* configUSE_TICKLESS_IDLE */
\r
5368 1937: /*----------------------------------------------------------*/
\r
5370 1939: BaseType_t xTaskIncrementTick( void )
\r
5372 BFD02080 4FE9 ADDIU SP, SP, -48
\r
5373 BFD02082 CBEB SW RA, 44(SP)
\r
5374 BFD02084 CBCA SW S8, 40(SP)
\r
5375 BFD02086 0FDD MOVE S8, SP
\r
5376 1941: TCB_t * pxTCB;
\r
5377 1942: TickType_t xItemValue;
\r
5378 1943: BaseType_t xSwitchRequired = pdFALSE;
\r
5379 BFD02088 0010F81E SW ZERO, 16(S8)
\r
5381 1945: /* Called by the portable layer each time a tick interrupt occurs.
\r
5382 1946: Increments the tick then checks to see if the new tick value will cause any
\r
5383 1947: tasks to be unblocked. */
\r
5384 1948: traceTASK_INCREMENT_TICK( xTickCount );
\r
5385 1949: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
\r
5386 BFD0208C 805CFC5C LW V0, -32676(GP)
\r
5387 BFD02090 00B840A2 BNEZC V0, 0xBFD02204
\r
5389 1951: /* Increment the RTOS tick, switching the delayed and overflowed
\r
5390 1952: delayed lists if it wraps to 0. */
\r
5391 1953: ++xTickCount;
\r
5392 BFD02094 803CFC5C LW V0, -32708(GP)
\r
5393 BFD02098 6D20 ADDIU V0, V0, 1
\r
5394 BFD0209A 803CF85C SW V0, -32708(GP)
\r
5397 1956: /* Minor optimisation. The tick count cannot change in this
\r
5399 1958: const TickType_t xConstTickCount = xTickCount;
\r
5400 BFD0209E 803CFC5C LW V0, -32708(GP)
\r
5401 BFD020A2 0014F85E SW V0, 20(S8)
\r
5403 1960: if( xConstTickCount == ( TickType_t ) 0U )
\r
5404 BFD020A6 0014FC5E LW V0, 20(S8)
\r
5405 BFD020AA 002240A2 BNEZC V0, 0xBFD020F2
\r
5407 1962: taskSWITCH_DELAYED_LISTS();
\r
5408 BFD020AE 8074FC5C LW V0, -32652(GP)
\r
5409 BFD020B2 6920 LW V0, 0(V0)
\r
5410 BFD020B4 000940E2 BEQZC V0, 0xBFD020CA
\r
5411 BFD020B8 BFD141A2 LUI V0, 0xBFD1
\r
5412 BFD020BA 3082BFD1 LDC1 F30, 12418(S1)
\r
5413 BFD020BC 98103082 ADDIU A0, V0, -26608
\r
5414 BFD020BE 30A09810 SWC1 F0, 12448(S0)
\r
5415 BFD020C0 07AA30A0 ADDIU A1, ZERO, 1962
\r
5416 BFD020C2 07AA ADDU A3, A1, V0
\r
5417 BFD020C4 4B7E77E8 JALS vAssertCalled
\r
5418 BFD020C6 4B7E LW K1, 120(SP)
\r
5420 BFD020CA 8074FC5C LW V0, -32652(GP)
\r
5421 BFD020CE 0018F85E SW V0, 24(S8)
\r
5422 BFD020D2 8078FC5C LW V0, -32648(GP)
\r
5423 BFD020D6 8074F85C SW V0, -32652(GP)
\r
5424 BFD020DA 0018FC5E LW V0, 24(S8)
\r
5425 BFD020DE 8078F85C SW V0, -32648(GP)
\r
5426 BFD020E2 8050FC5C LW V0, -32688(GP)
\r
5427 BFD020E6 6D20 ADDIU V0, V0, 1
\r
5428 BFD020E8 8050F85C SW V0, -32688(GP)
\r
5429 BFD020EC 47CA77E8 JALS prvResetNextTaskUnblockTime
\r
5434 1966: mtCOVERAGE_TEST_MARKER();
\r
5437 1969: /* See if this tick has made a timeout expire. Tasks are stored in
\r
5438 1970: the queue in the order of their wake time - meaning once one task
\r
5439 1971: has been found whose block time has not expired there is no need to
\r
5440 1972: look any further down the list. */
\r
5441 1973: if( xConstTickCount >= xNextTaskUnblockTime )
\r
5442 BFD020F2 8058FC5C LW V0, -32680(GP)
\r
5443 BFD020F6 0014FC7E LW V1, 20(S8)
\r
5444 BFD020FA 13900043 SLTU V0, V1, V0
\r
5445 BFD020FC 40A21390 ADDI GP, S0, 16546
\r
5446 BFD020FE 006C40A2 BNEZC V0, 0xBFD021DA
\r
5447 BFD02102 CC02 B 0xBFD02108
\r
5452 1977: if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
\r
5453 BFD02108 8074FC5C LW V0, -32652(GP)
\r
5454 BFD0210C 6920 LW V0, 0(V0)
\r
5455 BFD0210E 000340A2 BNEZC V0, 0xBFD02118
\r
5456 BFD02112 ED01 LI V0, 1
\r
5457 BFD02114 CC02 B 0xBFD0211A
\r
5459 BFD02118 0C40 MOVE V0, ZERO
\r
5460 BFD0211A 000540E2 BEQZC V0, 0xBFD02128
\r
5462 1979: /* The delayed list is empty. Set xNextTaskUnblockTime
\r
5463 1980: to the maximum possible value so it is extremely
\r
5464 1981: unlikely that the
\r
5465 1982: if( xTickCount >= xNextTaskUnblockTime ) test will pass
\r
5466 1983: next time through. */
\r
5467 1984: xNextTaskUnblockTime = portMAX_DELAY;
\r
5468 BFD0211E ED7F LI V0, -1
\r
5469 BFD02120 8058F85C SW V0, -32680(GP)
\r
5471 BFD02124 CC5A B 0xBFD021DA
\r
5476 1989: /* The delayed list is not empty, get the value of the
\r
5477 1990: item at the head of the delayed list. This is the time
\r
5478 1991: at which the task at the head of the delayed list must
\r
5479 1992: be removed from the Blocked state. */
\r
5480 1993: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
\r
5481 BFD02128 8074FC5C LW V0, -32652(GP)
\r
5482 BFD0212C 6923 LW V0, 12(V0)
\r
5483 BFD0212E 6923 LW V0, 12(V0)
\r
5484 BFD02130 001CF85E SW V0, 28(S8)
\r
5485 1994: xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );
\r
5486 BFD02134 001CFC5E LW V0, 28(S8)
\r
5487 BFD02138 6921 LW V0, 4(V0)
\r
5488 BFD0213A 0020F85E SW V0, 32(S8)
\r
5490 1996: if( xConstTickCount < xItemValue )
\r
5491 BFD0213E 0014FC7E LW V1, 20(S8)
\r
5492 BFD02142 0020FC5E LW V0, 32(S8)
\r
5493 BFD02146 13900043 SLTU V0, V1, V0
\r
5494 BFD02148 40E21390 ADDI GP, S0, 16610
\r
5495 BFD0214A 000640E2 BEQZC V0, 0xBFD0215A
\r
5497 1998: /* It is not time to unblock this item yet, but the
\r
5498 1999: item value is the time at which the task at the head
\r
5499 2000: of the blocked list must be removed from the Blocked
\r
5500 2001: state - so record the item value in
\r
5501 2002: xNextTaskUnblockTime. */
\r
5502 2003: xNextTaskUnblockTime = xItemValue;
\r
5503 BFD0214E 0020FC5E LW V0, 32(S8)
\r
5504 BFD02152 8058F85C SW V0, -32680(GP)
\r
5506 BFD02156 CC41 B 0xBFD021DA
\r
5511 2008: mtCOVERAGE_TEST_MARKER();
\r
5514 2011: /* It is time to remove the item from the Blocked state. */
\r
5515 2012: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
5516 BFD0215A 001CFC5E LW V0, 28(S8)
\r
5517 BFD0215E 6D22 ADDIU V0, V0, 4
\r
5518 BFD02160 0C82 MOVE A0, V0
\r
5519 BFD02162 00C877E8 JALS uxListRemove
\r
5520 BFD02164 0C0000C8 SLL A2, T0, 1
\r
5523 2014: /* Is the task waiting on an event also? If so remove
\r
5524 2015: it from the event list. */
\r
5525 2016: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
\r
5526 BFD02168 001CFC5E LW V0, 28(S8)
\r
5527 BFD0216C 692A LW V0, 40(V0)
\r
5528 BFD0216E 000740E2 BEQZC V0, 0xBFD02180
\r
5530 2018: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
\r
5531 BFD02172 001CFC5E LW V0, 28(S8)
\r
5532 BFD02174 6D2C001C EXT ZERO, GP, 20, 14
\r
5533 BFD02176 6D2C ADDIU V0, V0, 24
\r
5534 BFD02178 0C82 MOVE A0, V0
\r
5535 BFD0217A 00C877E8 JALS uxListRemove
\r
5536 BFD0217C 0C0000C8 SLL A2, T0, 1
\r
5541 2022: mtCOVERAGE_TEST_MARKER();
\r
5544 2025: /* Place the unblocked task into the appropriate ready
\r
5546 2027: prvAddTaskToReadyList( pxTCB );
\r
5547 BFD02180 001CFC5E LW V0, 28(S8)
\r
5548 BFD02184 692B LW V0, 44(V0)
\r
5549 BFD02186 ED81 LI V1, 1
\r
5550 BFD02188 18100062 SLLV V1, V0, V1
\r
5551 BFD0218A FC5C1810 SB ZERO, -932(S0)
\r
5552 BFD0218C 8040FC5C LW V0, -32704(GP)
\r
5553 BFD02190 44D3 OR16 V0, V1
\r
5554 BFD02192 8040F85C SW V0, -32704(GP)
\r
5555 BFD02196 001CFC5E LW V0, 28(S8)
\r
5556 BFD0219A 692B LW V0, 44(V0)
\r
5557 BFD0219C 2524 SLL V0, V0, 2
\r
5558 BFD0219E 25A4 SLL V1, V0, 2
\r
5559 BFD021A0 05B4 ADDU V1, V0, V1
\r
5560 BFD021A2 BFD241A2 LUI V0, 0xBFD2
\r
5561 BFD021A4 3042BFD2 LDC1 F30, 12354(S2)
\r
5562 BFD021A6 806C3042 ADDIU V0, V0, -32660
\r
5563 BFD021AA 05A6 ADDU V1, V1, V0
\r
5564 BFD021AC 001CFC5E LW V0, 28(S8)
\r
5565 BFD021B0 6D22 ADDIU V0, V0, 4
\r
5566 BFD021B2 0C83 MOVE A0, V1
\r
5567 BFD021B4 0CA2 MOVE A1, V0
\r
5568 BFD021B6 3E4A77E8 JALS vListInsertEnd
\r
5569 BFD021B8 0C003E4A LH S2, 3072(T2)
\r
5572 2029: /* A task being unblocked cannot cause an immediate
\r
5573 2030: context switch if preemption is turned off. */
\r
5574 2031: #if ( configUSE_PREEMPTION == 1 )
\r
5576 2033: /* Preemption is on, but a context switch should
\r
5577 2034: only be performed if the unblocked task has a
\r
5578 2035: priority that is equal to or higher than the
\r
5579 2036: currently executing task. */
\r
5580 2037: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
\r
5581 BFD021BC 001CFC5E LW V0, 28(S8)
\r
5582 BFD021C0 69AB LW V1, 44(V0)
\r
5583 BFD021C2 8030FC5C LW V0, -32720(GP)
\r
5584 BFD021C6 692B LW V0, 44(V0)
\r
5585 BFD021C8 13900043 SLTU V0, V1, V0
\r
5586 BFD021CA 40A21390 ADDI GP, S0, 16546
\r
5587 BFD021CC FF9B40A2 BNEZC V0, 0xBFD02106
\r
5588 BFD021CE ED01FF9B LW GP, -4863(K1)
\r
5590 2039: xSwitchRequired = pdTRUE;
\r
5591 BFD021D0 ED01 LI V0, 1
\r
5592 BFD021D2 0010F85E SW V0, 16(S8)
\r
5596 2043: mtCOVERAGE_TEST_MARKER();
\r
5599 2046: #endif /* configUSE_PREEMPTION */
\r
5603 BFD021D6 CF98 B 0xBFD02108
\r
5608 2052: /* Tasks of equal priority to the currently running task will share
\r
5609 2053: processing time (time slice) if preemption is on, and the application
\r
5610 2054: writer has not explicitly turned time slicing off. */
\r
5611 2055: #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
\r
5613 2057: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
\r
5614 BFD021DA 8030FC5C LW V0, -32720(GP)
\r
5615 BFD021DE 692B LW V0, 44(V0)
\r
5616 BFD021E0 2524 SLL V0, V0, 2
\r
5617 BFD021E2 25A4 SLL V1, V0, 2
\r
5618 BFD021E4 05B4 ADDU V1, V0, V1
\r
5619 BFD021E6 BFD241A2 LUI V0, 0xBFD2
\r
5620 BFD021E8 3042BFD2 LDC1 F30, 12354(S2)
\r
5621 BFD021EA 806C3042 ADDIU V0, V0, -32660
\r
5622 BFD021EE 0526 ADDU V0, V1, V0
\r
5623 BFD021F0 6920 LW V0, 0(V0)
\r
5624 BFD021F2 0002B042 SLTIU V0, V0, 2
\r
5625 BFD021F6 000A40A2 BNEZC V0, 0xBFD0220E
\r
5627 2059: xSwitchRequired = pdTRUE;
\r
5628 BFD021FA ED01 LI V0, 1
\r
5629 BFD021FC 0010F85E SW V0, 16(S8)
\r
5630 BFD02200 CC06 B 0xBFD0220E
\r
5635 2063: mtCOVERAGE_TEST_MARKER();
\r
5638 2066: #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
\r
5640 2068: #if ( configUSE_TICK_HOOK == 1 )
\r
5642 2070: /* Guard against the tick hook being called when the pended tick
\r
5643 2071: count is being unwound (when the scheduler is being unlocked). */
\r
5644 2072: if( uxPendedTicks == ( UBaseType_t ) 0U )
\r
5646 2074: vApplicationTickHook();
\r
5650 2078: mtCOVERAGE_TEST_MARKER();
\r
5653 2081: #endif /* configUSE_TICK_HOOK */
\r
5657 2085: ++uxPendedTicks;
\r
5658 BFD02204 8048FC5C LW V0, -32696(GP)
\r
5659 BFD02208 6D20 ADDIU V0, V0, 1
\r
5660 BFD0220A 8048F85C SW V0, -32696(GP)
\r
5662 2087: /* The tick hook gets called at regular intervals, even if the
\r
5663 2088: scheduler is locked. */
\r
5664 2089: #if ( configUSE_TICK_HOOK == 1 )
\r
5666 2091: vApplicationTickHook();
\r
5671 2096: #if ( configUSE_PREEMPTION == 1 )
\r
5673 2098: if( xYieldPending != pdFALSE )
\r
5674 BFD0220E 804CFC5C LW V0, -32692(GP)
\r
5675 BFD02212 000340E2 BEQZC V0, 0xBFD0221C
\r
5677 2100: xSwitchRequired = pdTRUE;
\r
5678 BFD02216 ED01 LI V0, 1
\r
5679 BFD02218 0010F85E SW V0, 16(S8)
\r
5683 2104: mtCOVERAGE_TEST_MARKER();
\r
5686 2107: #endif /* configUSE_PREEMPTION */
\r
5688 2109: return xSwitchRequired;
\r
5689 BFD0221C 0010FC5E LW V0, 16(S8)
\r
5691 BFD02220 0FBE MOVE SP, S8
\r
5692 BFD02222 4BEB LW RA, 44(SP)
\r
5693 BFD02224 4BCA LW S8, 40(SP)
\r
5694 BFD02226 4C19 ADDIU SP, SP, 48
\r
5695 BFD02228 459F JR16 RA
\r
5697 2111: /*-----------------------------------------------------------*/
\r
5699 2113: #if ( configUSE_APPLICATION_TASK_TAG == 1 )
\r
5701 2115: void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
\r
5703 2117: TCB_t *xTCB;
\r
5705 2119: /* If xTask is NULL then it is the task hook of the calling task that is
\r
5706 2120: getting set. */
\r
5707 2121: if( xTask == NULL )
\r
5709 2123: xTCB = ( TCB_t * ) pxCurrentTCB;
\r
5713 2127: xTCB = ( TCB_t * ) xTask;
\r
5716 2130: /* Save the hook function in the TCB. A critical section is required as
\r
5717 2131: the value can be accessed from an interrupt. */
\r
5718 2132: taskENTER_CRITICAL();
\r
5719 2133: xTCB->pxTaskTag = pxHookFunction;
\r
5720 2134: taskEXIT_CRITICAL();
\r
5723 2137: #endif /* configUSE_APPLICATION_TASK_TAG */
\r
5724 2138: /*-----------------------------------------------------------*/
\r
5726 2140: #if ( configUSE_APPLICATION_TASK_TAG == 1 )
\r
5728 2142: TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
\r
5730 2144: TCB_t *xTCB;
\r
5731 2145: TaskHookFunction_t xReturn;
\r
5733 2147: /* If xTask is NULL then we are setting our own task hook. */
\r
5734 2148: if( xTask == NULL )
\r
5736 2150: xTCB = ( TCB_t * ) pxCurrentTCB;
\r
5740 2154: xTCB = ( TCB_t * ) xTask;
\r
5743 2157: /* Save the hook function in the TCB. A critical section is required as
\r
5744 2158: the value can be accessed from an interrupt. */
\r
5745 2159: taskENTER_CRITICAL();
\r
5747 2161: xReturn = xTCB->pxTaskTag;
\r
5749 2163: taskEXIT_CRITICAL();
\r
5751 2165: return xReturn;
\r
5754 2168: #endif /* configUSE_APPLICATION_TASK_TAG */
\r
5755 2169: /*-----------------------------------------------------------*/
\r
5757 2171: #if ( configUSE_APPLICATION_TASK_TAG == 1 )
\r
5759 2173: BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
\r
5761 2175: TCB_t *xTCB;
\r
5762 2176: BaseType_t xReturn;
\r
5764 2178: /* If xTask is NULL then we are calling our own task hook. */
\r
5765 2179: if( xTask == NULL )
\r
5767 2181: xTCB = ( TCB_t * ) pxCurrentTCB;
\r
5771 2185: xTCB = ( TCB_t * ) xTask;
\r
5774 2188: if( xTCB->pxTaskTag != NULL )
\r
5776 2190: xReturn = xTCB->pxTaskTag( pvParameter );
\r
5780 2194: xReturn = pdFAIL;
\r
5783 2197: return xReturn;
\r
5786 2200: #endif /* configUSE_APPLICATION_TASK_TAG */
\r
5787 2201: /*-----------------------------------------------------------*/
\r
5789 2203: void vTaskSwitchContext( void )
\r
5791 BFD02DBC 4FE5 ADDIU SP, SP, -56
\r
5792 BFD02DBE CBED SW RA, 52(SP)
\r
5793 BFD02DC0 CBCC SW S8, 48(SP)
\r
5794 BFD02DC2 0FDD MOVE S8, SP
\r
5795 2205: if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
\r
5796 BFD02DC4 805CFC5C LW V0, -32676(GP)
\r
5797 BFD02DC8 000540E2 BEQZC V0, 0xBFD02DD6
\r
5799 2207: /* The scheduler is currently suspended - do not allow a context
\r
5801 2209: xYieldPending = pdTRUE;
\r
5802 BFD02DCC ED01 LI V0, 1
\r
5803 BFD02DCE 804CF85C SW V0, -32692(GP)
\r
5804 BFD02DD2 CC91 B 0xBFD02EF6
\r
5809 2213: xYieldPending = pdFALSE;
\r
5810 BFD02DD6 804CF81C SW ZERO, -32692(GP)
\r
5811 2214: traceTASK_SWITCHED_OUT();
\r
5813 2216: #if ( configGENERATE_RUN_TIME_STATS == 1 )
\r
5815 2218: #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
\r
5816 2219: portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
\r
5818 2221: ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
\r
5821 2224: /* Add the amount of time the task has been running to the
\r
5822 2225: accumulated time so far. The time the task started running was
\r
5823 2226: stored in ulTaskSwitchedInTime. Note that there is no overflow
\r
5824 2227: protection here so count values are only valid until the timer
\r
5825 2228: overflows. The guard against negative values is to protect
\r
5826 2229: against suspect run time stat counter implementations - which
\r
5827 2230: are provided by the application, not the kernel. */
\r
5828 2231: if( ulTotalRunTime > ulTaskSwitchedInTime )
\r
5830 2233: pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
\r
5834 2237: mtCOVERAGE_TEST_MARKER();
\r
5836 2239: ulTaskSwitchedInTime = ulTotalRunTime;
\r
5838 2241: #endif /* configGENERATE_RUN_TIME_STATS */
\r
5840 2243: /* Check for stack overflow, if configured. */
\r
5841 2244: taskFIRST_CHECK_FOR_STACK_OVERFLOW();
\r
5842 BFD02DDA 8030FC5C LW V0, -32720(GP)
\r
5843 BFD02DDE 69A0 LW V1, 0(V0)
\r
5844 BFD02DE0 8030FC5C LW V0, -32720(GP)
\r
5845 BFD02DE4 692C LW V0, 48(V0)
\r
5846 BFD02DE6 13900062 SLTU V0, V0, V1
\r
5847 BFD02DE8 40A21390 ADDI GP, S0, 16546
\r
5848 BFD02DEA 000B40A2 BNEZC V0, 0xBFD02E04
\r
5849 BFD02DEE 8030FC7C LW V1, -32720(GP)
\r
5850 BFD02DF2 8030FC5C LW V0, -32720(GP)
\r
5851 BFD02DF6 00343042 ADDIU V0, V0, 52
\r
5852 BFD02DFA 0C83 MOVE A0, V1
\r
5853 BFD02DFC 0CA2 MOVE A1, V0
\r
5854 BFD02DFE 422277E8 JALS vApplicationStackOverflowHook
\r
5855 BFD02E00 0C004222 BLTZALS V0, 0xBFD04604
\r
5857 2245: taskSECOND_CHECK_FOR_STACK_OVERFLOW();
\r
5858 BFD02E04 BFD141A2 LUI V0, 0xBFD1
\r
5859 BFD02E06 FCC2BFD1 LDC1 F30, -830(S1)
\r
5860 BFD02E08 9830FCC2 LW A2, -26576(V0)
\r
5861 BFD02E0A 30629830 SWC1 F1, 12386(S0)
\r
5862 BFD02E0C 98303062 ADDIU V1, V0, -26576
\r
5863 BFD02E0E 6AB19830 SWC1 F1, 27313(S0)
\r
5864 BFD02E10 6AB1 LW A1, 4(V1)
\r
5865 BFD02E12 98303062 ADDIU V1, V0, -26576
\r
5866 BFD02E14 6A329830 SWC1 F1, 27186(S0)
\r
5867 BFD02E16 6A32 LW A0, 8(V1)
\r
5868 BFD02E18 98303062 ADDIU V1, V0, -26576
\r
5869 BFD02E1A 69B39830 SWC1 F1, 27059(S0)
\r
5870 BFD02E1C 69B3 LW V1, 12(V1)
\r
5871 BFD02E1E 98303042 ADDIU V0, V0, -26576
\r
5872 BFD02E20 69249830 SWC1 F1, 26916(S0)
\r
5873 BFD02E22 6924 LW V0, 16(V0)
\r
5874 BFD02E24 0018F8DE SW A2, 24(S8)
\r
5875 BFD02E28 001CF8BE SW A1, 28(S8)
\r
5876 BFD02E2C 0020F89E SW A0, 32(S8)
\r
5877 BFD02E30 0024F87E SW V1, 36(S8)
\r
5878 BFD02E34 0028F85E SW V0, 40(S8)
\r
5879 BFD02E38 8030FC5C LW V0, -32720(GP)
\r
5880 BFD02E3C 69AC LW V1, 48(V0)
\r
5881 BFD02E3E 0018305E ADDIU V0, S8, 24
\r
5882 BFD02E42 0C83 MOVE A0, V1
\r
5883 BFD02E44 0CA2 MOVE A1, V0
\r
5884 BFD02E46 EF14 LI A2, 20
\r
5885 BFD02E48 3DA677E8 JALS 0xBFD07B4C
\r
5886 BFD02E4A 0C003DA6 LH T5, 3072(A2)
\r
5888 BFD02E4E 000B40E2 BEQZC V0, 0xBFD02E68
\r
5889 BFD02E52 8030FC7C LW V1, -32720(GP)
\r
5890 BFD02E56 8030FC5C LW V0, -32720(GP)
\r
5891 BFD02E5A 00343042 ADDIU V0, V0, 52
\r
5892 BFD02E5E 0C83 MOVE A0, V1
\r
5893 BFD02E60 0CA2 MOVE A1, V0
\r
5894 BFD02E62 422277E8 JALS vApplicationStackOverflowHook
\r
5895 BFD02E64 0C004222 BLTZALS V0, 0xBFD04668
\r
5898 2247: /* Select a new task to run using either the generic C or port
\r
5899 2248: optimised asm code. */
\r
5900 2249: taskSELECT_HIGHEST_PRIORITY_TASK();
\r
5901 BFD02E68 8040FC5C LW V0, -32704(GP)
\r
5902 BFD02E6C 5B3C0042 CLZ V0, V0
\r
5903 BFD02E70 ED9F LI V1, 31
\r
5904 BFD02E72 0527 SUBU V0, V1, V0
\r
5905 BFD02E74 0010F85E SW V0, 16(S8)
\r
5906 BFD02E78 0010FC5E LW V0, 16(S8)
\r
5907 BFD02E7C 2524 SLL V0, V0, 2
\r
5908 BFD02E7E 25A4 SLL V1, V0, 2
\r
5909 BFD02E80 05B4 ADDU V1, V0, V1
\r
5910 BFD02E82 BFD241A2 LUI V0, 0xBFD2
\r
5911 BFD02E84 3042BFD2 LDC1 F30, 12354(S2)
\r
5912 BFD02E86 806C3042 ADDIU V0, V0, -32660
\r
5913 BFD02E8A 0526 ADDU V0, V1, V0
\r
5914 BFD02E8C 6920 LW V0, 0(V0)
\r
5915 BFD02E8E 000940A2 BNEZC V0, 0xBFD02EA4
\r
5916 BFD02E92 BFD141A2 LUI V0, 0xBFD1
\r
5917 BFD02E94 3082BFD1 LDC1 F30, 12418(S1)
\r
5918 BFD02E96 98103082 ADDIU A0, V0, -26608
\r
5919 BFD02E98 30A09810 SWC1 F0, 12448(S0)
\r
5920 BFD02E9A 08C930A0 ADDIU A1, ZERO, 2249
\r
5921 BFD02E9C 08C9 LBU S1, 9(A0)
\r
5922 BFD02E9E 4B7E77E8 JALS vAssertCalled
\r
5923 BFD02EA0 4B7E LW K1, 120(SP)
\r
5925 BFD02EA4 0010FC5E LW V0, 16(S8)
\r
5926 BFD02EA8 2524 SLL V0, V0, 2
\r
5927 BFD02EAA 25A4 SLL V1, V0, 2
\r
5928 BFD02EAC 05B4 ADDU V1, V0, V1
\r
5929 BFD02EAE BFD241A2 LUI V0, 0xBFD2
\r
5930 BFD02EB0 3042BFD2 LDC1 F30, 12354(S2)
\r
5931 BFD02EB2 806C3042 ADDIU V0, V0, -32660
\r
5932 BFD02EB6 0526 ADDU V0, V1, V0
\r
5933 BFD02EB8 0014F85E SW V0, 20(S8)
\r
5934 BFD02EBC 0014FC5E LW V0, 20(S8)
\r
5935 BFD02EC0 6921 LW V0, 4(V0)
\r
5936 BFD02EC2 69A1 LW V1, 4(V0)
\r
5937 BFD02EC4 0014FC5E LW V0, 20(S8)
\r
5938 BFD02EC8 E9A1 SW V1, 4(V0)
\r
5939 BFD02ECA 0014FC5E LW V0, 20(S8)
\r
5940 BFD02ECE 69A1 LW V1, 4(V0)
\r
5941 BFD02ED0 0014FC5E LW V0, 20(S8)
\r
5942 BFD02ED4 6D24 ADDIU V0, V0, 8
\r
5943 BFD02ED6 0008B443 BNE V1, V0, 0xBFD02EEA
\r
5944 BFD02ED8 0C000008 SLL ZERO, T0, 1
\r
5946 BFD02EDC 0014FC5E LW V0, 20(S8)
\r
5947 BFD02EE0 6921 LW V0, 4(V0)
\r
5948 BFD02EE2 69A1 LW V1, 4(V0)
\r
5949 BFD02EE4 0014FC5E LW V0, 20(S8)
\r
5950 BFD02EE8 E9A1 SW V1, 4(V0)
\r
5951 BFD02EEA 0014FC5E LW V0, 20(S8)
\r
5952 BFD02EEE 6921 LW V0, 4(V0)
\r
5953 BFD02EF0 6923 LW V0, 12(V0)
\r
5954 BFD02EF2 8030F85C SW V0, -32720(GP)
\r
5955 2250: traceTASK_SWITCHED_IN();
\r
5957 2252: #if ( configUSE_NEWLIB_REENTRANT == 1 )
\r
5959 2254: /* Switch Newlib's _impure_ptr variable to point to the _reent
\r
5960 2255: structure specific to this task. */
\r
5961 2256: _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
\r
5963 2258: #endif /* configUSE_NEWLIB_REENTRANT */
\r
5966 BFD02EF6 0FBE MOVE SP, S8
\r
5967 BFD02EF8 4BED LW RA, 52(SP)
\r
5968 BFD02EFA 4BCC LW S8, 48(SP)
\r
5969 BFD02EFC 4C1D ADDIU SP, SP, 56
\r
5970 BFD02EFE 459F JR16 RA
\r
5972 2261: /*-----------------------------------------------------------*/
\r
5974 2263: void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
\r
5976 BFD05E74 4FF1 ADDIU SP, SP, -32
\r
5977 BFD05E76 CBE7 SW RA, 28(SP)
\r
5978 BFD05E78 CBC6 SW S8, 24(SP)
\r
5979 BFD05E7A 0FDD MOVE S8, SP
\r
5980 BFD05E7C 0020F89E SW A0, 32(S8)
\r
5981 BFD05E80 0024F8BE SW A1, 36(S8)
\r
5982 2265: TickType_t xTimeToWake;
\r
5984 2267: configASSERT( pxEventList );
\r
5985 BFD05E84 0020FC5E LW V0, 32(S8)
\r
5986 BFD05E88 000940A2 BNEZC V0, 0xBFD05E9E
\r
5987 BFD05E8C BFD141A2 LUI V0, 0xBFD1
\r
5988 BFD05E8E 3082BFD1 LDC1 F30, 12418(S1)
\r
5989 BFD05E90 98103082 ADDIU A0, V0, -26608
\r
5990 BFD05E92 30A09810 SWC1 F0, 12448(S0)
\r
5991 BFD05E94 08DB30A0 ADDIU A1, ZERO, 2267
\r
5992 BFD05E96 08DB LBU S1, 11(A1)
\r
5993 BFD05E98 4B7E77E8 JALS vAssertCalled
\r
5994 BFD05E9A 4B7E LW K1, 120(SP)
\r
5997 2269: /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
\r
5998 2270: SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
\r
6000 2272: /* Place the event list item of the TCB in the appropriate event list.
\r
6001 2273: This is placed in the list in priority order so the highest priority task
\r
6002 2274: is the first to be woken by the event. The queue that contains the event
\r
6003 2275: list is locked, preventing simultaneous access from interrupts. */
\r
6004 2276: vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
\r
6005 BFD05E9E 8030FC5C LW V0, -32720(GP)
\r
6006 BFD05EA2 6D2C ADDIU V0, V0, 24
\r
6007 BFD05EA4 0020FC9E LW A0, 32(S8)
\r
6008 BFD05EA8 0CA2 MOVE A1, V0
\r
6009 BFD05EAA 304077E8 JALS vListInsert
\r
6010 BFD05EAC 0C003040 ADDIU V0, ZERO, 3072
\r
6013 2278: /* The task must be removed from from the ready list before it is added to
\r
6014 2279: the blocked list as the same list item is used for both lists. Exclusive
\r
6015 2280: access to the ready lists guaranteed because the scheduler is locked. */
\r
6016 2281: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
6017 BFD05EB0 8030FC5C LW V0, -32720(GP)
\r
6018 BFD05EB4 6D22 ADDIU V0, V0, 4
\r
6019 BFD05EB6 0C82 MOVE A0, V0
\r
6020 BFD05EB8 00C877E8 JALS uxListRemove
\r
6021 BFD05EBA 0C0000C8 SLL A2, T0, 1
\r
6023 BFD05EBE 000C40A2 BNEZC V0, 0xBFD05EDA
\r
6025 2283: /* The current task must be in a ready list, so there is no need to
\r
6026 2284: check, and the port reset macro can be called directly. */
\r
6027 2285: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
\r
6028 BFD05EC2 8030FC5C LW V0, -32720(GP)
\r
6029 BFD05EC6 692B LW V0, 44(V0)
\r
6030 BFD05EC8 ED81 LI V1, 1
\r
6031 BFD05ECA 10100062 SLLV V0, V0, V1
\r
6032 BFD05ECC 441A1010 ADDI ZERO, S0, 17434
\r
6033 BFD05ECE 441A NOT16 V1, V0
\r
6034 BFD05ED0 8040FC5C LW V0, -32704(GP)
\r
6035 BFD05ED4 4493 AND16 V0, V1
\r
6036 BFD05ED6 8040F85C SW V0, -32704(GP)
\r
6040 2289: mtCOVERAGE_TEST_MARKER();
\r
6043 2292: #if ( INCLUDE_vTaskSuspend == 1 )
\r
6045 2294: if( xTicksToWait == portMAX_DELAY )
\r
6046 BFD05EDA 0024FC7E LW V1, 36(S8)
\r
6047 BFD05EDE ED7F LI V0, -1
\r
6048 BFD05EE0 000EB443 BNE V1, V0, 0xBFD05F00
\r
6049 BFD05EE2 0C00000E SLL ZERO, T6, 1
\r
6052 2296: /* Add the task to the suspended task list instead of a delayed task
\r
6053 2297: list to ensure the task is not woken by a timing event. It will
\r
6054 2298: block indefinitely. */
\r
6055 2299: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );
\r
6056 BFD05EE6 8030FC5C LW V0, -32720(GP)
\r
6057 BFD05EEA 6D22 ADDIU V0, V0, 4
\r
6058 BFD05EEC BFD241A3 LUI V1, 0xBFD2
\r
6059 BFD05EEE 3083BFD2 LDC1 F30, 12419(S2)
\r
6060 BFD05EF0 80E43083 ADDIU A0, V1, -32540
\r
6061 BFD05EF4 0CA2 MOVE A1, V0
\r
6062 BFD05EF6 3E4A77E8 JALS vListInsertEnd
\r
6063 BFD05EF8 0C003E4A LH S2, 3072(T2)
\r
6065 BFD05EFC CC0D B 0xBFD05F18
\r
6070 2303: /* Calculate the time at which the task should be woken if the event
\r
6071 2304: does not occur. This may overflow but this doesn't matter, the
\r
6072 2305: scheduler will handle it. */
\r
6073 2306: xTimeToWake = xTickCount + xTicksToWait;
\r
6074 BFD05F00 803CFC7C LW V1, -32708(GP)
\r
6075 BFD05F04 0024FC5E LW V0, 36(S8)
\r
6076 BFD05F08 0526 ADDU V0, V1, V0
\r
6077 BFD05F0A 0010F85E SW V0, 16(S8)
\r
6078 2307: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
6079 BFD05F0E 0010FC9E LW A0, 16(S8)
\r
6080 BFD05F12 373477E8 JALS prvAddCurrentTaskToDelayedList
\r
6081 BFD05F14 0C003734 LHU T9, 3072(S4)
\r
6085 2310: #else /* INCLUDE_vTaskSuspend */
\r
6087 2312: /* Calculate the time at which the task should be woken if the event does
\r
6088 2313: not occur. This may overflow but this doesn't matter, the scheduler
\r
6089 2314: will handle it. */
\r
6090 2315: xTimeToWake = xTickCount + xTicksToWait;
\r
6091 2316: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
6093 2318: #endif /* INCLUDE_vTaskSuspend */
\r
6095 BFD05F18 0FBE MOVE SP, S8
\r
6096 BFD05F1A 4BE7 LW RA, 28(SP)
\r
6097 BFD05F1C 4BC6 LW S8, 24(SP)
\r
6098 BFD05F1E 4C11 ADDIU SP, SP, 32
\r
6099 BFD05F20 459F JR16 RA
\r
6101 2320: /*-----------------------------------------------------------*/
\r
6103 2322: void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
\r
6105 BFD04904 4FF1 ADDIU SP, SP, -32
\r
6106 BFD04906 CBE7 SW RA, 28(SP)
\r
6107 BFD04908 CBC6 SW S8, 24(SP)
\r
6108 BFD0490A 0FDD MOVE S8, SP
\r
6109 BFD0490C 0020F89E SW A0, 32(S8)
\r
6110 BFD04910 0024F8BE SW A1, 36(S8)
\r
6111 BFD04914 0028F8DE SW A2, 40(S8)
\r
6112 2324: TickType_t xTimeToWake;
\r
6114 2326: configASSERT( pxEventList );
\r
6115 BFD04918 0020FC5E LW V0, 32(S8)
\r
6116 BFD0491C 000940A2 BNEZC V0, 0xBFD04932
\r
6117 BFD04920 BFD141A2 LUI V0, 0xBFD1
\r
6118 BFD04922 3082BFD1 LDC1 F30, 12418(S1)
\r
6119 BFD04924 98103082 ADDIU A0, V0, -26608
\r
6120 BFD04926 30A09810 SWC1 F0, 12448(S0)
\r
6121 BFD04928 091630A0 ADDIU A1, ZERO, 2326
\r
6122 BFD0492A 0916 LBU V0, 6(S1)
\r
6123 BFD0492C 4B7E77E8 JALS vAssertCalled
\r
6124 BFD0492E 4B7E LW K1, 120(SP)
\r
6127 2328: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
\r
6128 2329: the event groups implementation. */
\r
6129 2330: configASSERT( uxSchedulerSuspended != 0 );
\r
6130 BFD04932 805CFC5C LW V0, -32676(GP)
\r
6131 BFD04936 000940A2 BNEZC V0, 0xBFD0494C
\r
6132 BFD0493A BFD141A2 LUI V0, 0xBFD1
\r
6133 BFD0493C 3082BFD1 LDC1 F30, 12418(S1)
\r
6134 BFD0493E 98103082 ADDIU A0, V0, -26608
\r
6135 BFD04940 30A09810 SWC1 F0, 12448(S0)
\r
6136 BFD04942 091A30A0 ADDIU A1, ZERO, 2330
\r
6137 BFD04944 091A LBU V0, 10(S1)
\r
6138 BFD04946 4B7E77E8 JALS vAssertCalled
\r
6139 BFD04948 4B7E LW K1, 120(SP)
\r
6142 2332: /* Store the item value in the event list item. It is safe to access the
\r
6143 2333: event list item here as interrupts won't access the event list item of a
\r
6144 2334: task that is not in the Blocked state. */
\r
6145 2335: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
\r
6146 BFD0494C 8030FC5C LW V0, -32720(GP)
\r
6147 BFD04950 0024FC9E LW A0, 36(S8)
\r
6148 BFD04954 800041A3 LUI V1, 0x8000
\r
6149 BFD04958 44DC OR16 V1, A0
\r
6150 BFD0495A E9A6 SW V1, 24(V0)
\r
6152 2337: /* Place the event list item of the TCB at the end of the appropriate event
\r
6153 2338: list. It is safe to access the event list here because it is part of an
\r
6154 2339: event group implementation - and interrupts don't access event groups
\r
6155 2340: directly (instead they access them indirectly by pending function calls to
\r
6156 2341: the task level). */
\r
6157 2342: vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
\r
6158 BFD0495C 8030FC5C LW V0, -32720(GP)
\r
6159 BFD04960 6D2C ADDIU V0, V0, 24
\r
6160 BFD04962 0020FC9E LW A0, 32(S8)
\r
6161 BFD04966 0CA2 MOVE A1, V0
\r
6162 BFD04968 3E4A77E8 JALS vListInsertEnd
\r
6163 BFD0496A 0C003E4A LH S2, 3072(T2)
\r
6166 2344: /* The task must be removed from the ready list before it is added to the
\r
6167 2345: blocked list. Exclusive access can be assured to the ready list as the
\r
6168 2346: scheduler is locked. */
\r
6169 2347: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
6170 BFD0496E 8030FC5C LW V0, -32720(GP)
\r
6171 BFD04972 6D22 ADDIU V0, V0, 4
\r
6172 BFD04974 0C82 MOVE A0, V0
\r
6173 BFD04976 00C877E8 JALS uxListRemove
\r
6174 BFD04978 0C0000C8 SLL A2, T0, 1
\r
6176 BFD0497C 000C40A2 BNEZC V0, 0xBFD04998
\r
6178 2349: /* The current task must be in a ready list, so there is no need to
\r
6179 2350: check, and the port reset macro can be called directly. */
\r
6180 2351: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
\r
6181 BFD04980 8030FC5C LW V0, -32720(GP)
\r
6182 BFD04984 692B LW V0, 44(V0)
\r
6183 BFD04986 ED81 LI V1, 1
\r
6184 BFD04988 10100062 SLLV V0, V0, V1
\r
6185 BFD0498A 441A1010 ADDI ZERO, S0, 17434
\r
6186 BFD0498C 441A NOT16 V1, V0
\r
6187 BFD0498E 8040FC5C LW V0, -32704(GP)
\r
6188 BFD04992 4493 AND16 V0, V1
\r
6189 BFD04994 8040F85C SW V0, -32704(GP)
\r
6193 2355: mtCOVERAGE_TEST_MARKER();
\r
6196 2358: #if ( INCLUDE_vTaskSuspend == 1 )
\r
6198 2360: if( xTicksToWait == portMAX_DELAY )
\r
6199 BFD04998 0028FC7E LW V1, 40(S8)
\r
6200 BFD0499C ED7F LI V0, -1
\r
6201 BFD0499E 000EB443 BNE V1, V0, 0xBFD049BE
\r
6202 BFD049A0 0C00000E SLL ZERO, T6, 1
\r
6205 2362: /* Add the task to the suspended task list instead of a delayed task
\r
6206 2363: list to ensure it is not woken by a timing event. It will block
\r
6207 2364: indefinitely. */
\r
6208 2365: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );
\r
6209 BFD049A4 8030FC5C LW V0, -32720(GP)
\r
6210 BFD049A8 6D22 ADDIU V0, V0, 4
\r
6211 BFD049AA BFD241A3 LUI V1, 0xBFD2
\r
6212 BFD049AC 3083BFD2 LDC1 F30, 12419(S2)
\r
6213 BFD049AE 80E43083 ADDIU A0, V1, -32540
\r
6214 BFD049B2 0CA2 MOVE A1, V0
\r
6215 BFD049B4 3E4A77E8 JALS vListInsertEnd
\r
6216 BFD049B6 0C003E4A LH S2, 3072(T2)
\r
6218 BFD049BA CC0D B 0xBFD049D6
\r
6223 2369: /* Calculate the time at which the task should be woken if the event
\r
6224 2370: does not occur. This may overflow but this doesn't matter, the
\r
6225 2371: kernel will manage it correctly. */
\r
6226 2372: xTimeToWake = xTickCount + xTicksToWait;
\r
6227 BFD049BE 803CFC7C LW V1, -32708(GP)
\r
6228 BFD049C2 0028FC5E LW V0, 40(S8)
\r
6229 BFD049C6 0526 ADDU V0, V1, V0
\r
6230 BFD049C8 0010F85E SW V0, 16(S8)
\r
6231 2373: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
6232 BFD049CC 0010FC9E LW A0, 16(S8)
\r
6233 BFD049D0 373477E8 JALS prvAddCurrentTaskToDelayedList
\r
6234 BFD049D2 0C003734 LHU T9, 3072(S4)
\r
6238 2376: #else /* INCLUDE_vTaskSuspend */
\r
6240 2378: /* Calculate the time at which the task should be woken if the event does
\r
6241 2379: not occur. This may overflow but this doesn't matter, the kernel
\r
6242 2380: will manage it correctly. */
\r
6243 2381: xTimeToWake = xTickCount + xTicksToWait;
\r
6244 2382: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
6246 2384: #endif /* INCLUDE_vTaskSuspend */
\r
6248 BFD049D6 0FBE MOVE SP, S8
\r
6249 BFD049D8 4BE7 LW RA, 28(SP)
\r
6250 BFD049DA 4BC6 LW S8, 24(SP)
\r
6251 BFD049DC 4C11 ADDIU SP, SP, 32
\r
6252 BFD049DE 459F JR16 RA
\r
6254 2386: /*-----------------------------------------------------------*/
\r
6256 2388: #if configUSE_TIMERS == 1
\r
6258 2390: void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
\r
6260 BFD05C58 4FF1 ADDIU SP, SP, -32
\r
6261 BFD05C5A CBE7 SW RA, 28(SP)
\r
6262 BFD05C5C CBC6 SW S8, 24(SP)
\r
6263 BFD05C5E 0FDD MOVE S8, SP
\r
6264 BFD05C60 0020F89E SW A0, 32(S8)
\r
6265 BFD05C64 0024F8BE SW A1, 36(S8)
\r
6266 BFD05C68 0028F8DE SW A2, 40(S8)
\r
6267 2392: TickType_t xTimeToWake;
\r
6269 2394: configASSERT( pxEventList );
\r
6270 BFD05C6C 0020FC5E LW V0, 32(S8)
\r
6271 BFD05C70 000940A2 BNEZC V0, 0xBFD05C86
\r
6272 BFD05C74 BFD141A2 LUI V0, 0xBFD1
\r
6273 BFD05C76 3082BFD1 LDC1 F30, 12418(S1)
\r
6274 BFD05C78 98103082 ADDIU A0, V0, -26608
\r
6275 BFD05C7A 30A09810 SWC1 F0, 12448(S0)
\r
6276 BFD05C7C 095A30A0 ADDIU A1, ZERO, 2394
\r
6277 BFD05C7E 095A LBU V0, 10(A1)
\r
6278 BFD05C80 4B7E77E8 JALS vAssertCalled
\r
6279 BFD05C82 4B7E LW K1, 120(SP)
\r
6282 2396: /* This function should not be called by application code hence the
\r
6283 2397: 'Restricted' in its name. It is not part of the public API. It is
\r
6284 2398: designed for use by kernel code, and has special calling requirements -
\r
6285 2399: it should be called with the scheduler suspended. */
\r
6288 2402: /* Place the event list item of the TCB in the appropriate event list.
\r
6289 2403: In this case it is assume that this is the only task that is going to
\r
6290 2404: be waiting on this event list, so the faster vListInsertEnd() function
\r
6291 2405: can be used in place of vListInsert. */
\r
6292 2406: vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
\r
6293 BFD05C86 8030FC5C LW V0, -32720(GP)
\r
6294 BFD05C8A 6D2C ADDIU V0, V0, 24
\r
6295 BFD05C8C 0020FC9E LW A0, 32(S8)
\r
6296 BFD05C90 0CA2 MOVE A1, V0
\r
6297 BFD05C92 3E4A77E8 JALS vListInsertEnd
\r
6298 BFD05C94 0C003E4A LH S2, 3072(T2)
\r
6301 2408: /* We must remove this task from the ready list before adding it to the
\r
6302 2409: blocked list as the same list item is used for both lists. This
\r
6303 2410: function is called with the scheduler locked so interrupts will not
\r
6304 2411: access the lists at the same time. */
\r
6305 2412: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
6306 BFD05C98 8030FC5C LW V0, -32720(GP)
\r
6307 BFD05C9C 6D22 ADDIU V0, V0, 4
\r
6308 BFD05C9E 0C82 MOVE A0, V0
\r
6309 BFD05CA0 00C877E8 JALS uxListRemove
\r
6310 BFD05CA2 0C0000C8 SLL A2, T0, 1
\r
6312 BFD05CA6 000C40A2 BNEZC V0, 0xBFD05CC2
\r
6314 2414: /* The current task must be in a ready list, so there is no need to
\r
6315 2415: check, and the port reset macro can be called directly. */
\r
6316 2416: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
\r
6317 BFD05CAA 8030FC5C LW V0, -32720(GP)
\r
6318 BFD05CAE 692B LW V0, 44(V0)
\r
6319 BFD05CB0 ED81 LI V1, 1
\r
6320 BFD05CB2 10100062 SLLV V0, V0, V1
\r
6321 BFD05CB4 441A1010 ADDI ZERO, S0, 17434
\r
6322 BFD05CB6 441A NOT16 V1, V0
\r
6323 BFD05CB8 8040FC5C LW V0, -32704(GP)
\r
6324 BFD05CBC 4493 AND16 V0, V1
\r
6325 BFD05CBE 8040F85C SW V0, -32704(GP)
\r
6329 2420: mtCOVERAGE_TEST_MARKER();
\r
6332 2423: /* If vTaskSuspend() is available then the suspended task list is also
\r
6333 2424: available and a task that is blocking indefinitely can enter the
\r
6334 2425: suspended state (it is not really suspended as it will re-enter the
\r
6335 2426: Ready state when the event it is waiting indefinitely for occurs).
\r
6336 2427: Blocking indefinitely is useful when using tickless idle mode as when
\r
6337 2428: all tasks are blocked indefinitely all timers can be turned off. */
\r
6338 2429: #if( INCLUDE_vTaskSuspend == 1 )
\r
6340 2431: if( xWaitIndefinitely == pdTRUE )
\r
6341 BFD05CC2 0028FC7E LW V1, 40(S8)
\r
6342 BFD05CC6 ED01 LI V0, 1
\r
6343 BFD05CC8 000EB443 BNE V1, V0, 0xBFD05CE8
\r
6344 BFD05CCA 0C00000E SLL ZERO, T6, 1
\r
6347 2433: /* Add the task to the suspended task list instead of a delayed
\r
6348 2434: task list to ensure the task is not woken by a timing event. It
\r
6349 2435: will block indefinitely. */
\r
6350 2436: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );
\r
6351 BFD05CCE 8030FC5C LW V0, -32720(GP)
\r
6352 BFD05CD2 6D22 ADDIU V0, V0, 4
\r
6353 BFD05CD4 BFD241A3 LUI V1, 0xBFD2
\r
6354 BFD05CD6 3083BFD2 LDC1 F30, 12419(S2)
\r
6355 BFD05CD8 80E43083 ADDIU A0, V1, -32540
\r
6356 BFD05CDC 0CA2 MOVE A1, V0
\r
6357 BFD05CDE 3E4A77E8 JALS vListInsertEnd
\r
6358 BFD05CE0 0C003E4A LH S2, 3072(T2)
\r
6360 BFD05CE4 CC0D B 0xBFD05D00
\r
6365 2440: /* Calculate the time at which the task should be woken if the
\r
6366 2441: event does not occur. This may overflow but this doesn't
\r
6368 2443: xTimeToWake = xTickCount + xTicksToWait;
\r
6369 BFD05CE8 803CFC7C LW V1, -32708(GP)
\r
6370 BFD05CEC 0024FC5E LW V0, 36(S8)
\r
6371 BFD05CF0 0526 ADDU V0, V1, V0
\r
6372 BFD05CF2 0010F85E SW V0, 16(S8)
\r
6373 2444: traceTASK_DELAY_UNTIL();
\r
6374 2445: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
6375 BFD05CF6 0010FC9E LW A0, 16(S8)
\r
6376 BFD05CFA 373477E8 JALS prvAddCurrentTaskToDelayedList
\r
6377 BFD05CFC 0C003734 LHU T9, 3072(S4)
\r
6383 2450: /* Calculate the time at which the task should be woken if the event
\r
6384 2451: does not occur. This may overflow but this doesn't matter. */
\r
6385 2452: xTimeToWake = xTickCount + xTicksToWait;
\r
6386 2453: traceTASK_DELAY_UNTIL();
\r
6387 2454: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
6389 2456: /* Remove compiler warnings when INCLUDE_vTaskSuspend() is not
\r
6391 2458: ( void ) xWaitIndefinitely;
\r
6395 BFD05D00 0FBE MOVE SP, S8
\r
6396 BFD05D02 4BE7 LW RA, 28(SP)
\r
6397 BFD05D04 4BC6 LW S8, 24(SP)
\r
6398 BFD05D06 4C11 ADDIU SP, SP, 32
\r
6399 BFD05D08 459F JR16 RA
\r
6402 2463: #endif /* configUSE_TIMERS */
\r
6403 2464: /*-----------------------------------------------------------*/
\r
6405 2466: BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
\r
6407 BFD04578 4FF1 ADDIU SP, SP, -32
\r
6408 BFD0457A CBE7 SW RA, 28(SP)
\r
6409 BFD0457C CBC6 SW S8, 24(SP)
\r
6410 BFD0457E 0FDD MOVE S8, SP
\r
6411 BFD04580 0020F89E SW A0, 32(S8)
\r
6412 2468: TCB_t *pxUnblockedTCB;
\r
6413 2469: BaseType_t xReturn;
\r
6415 2471: /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be
\r
6416 2472: called from a critical section within an ISR. */
\r
6418 2474: /* The event list is sorted in priority order, so the first in the list can
\r
6419 2475: be removed as it is known to be the highest priority. Remove the TCB from
\r
6420 2476: the delayed list, and add it to the ready list.
\r
6422 2478: If an event is for a queue that is locked then this function will never
\r
6423 2479: get called - the lock count on the queue will get modified instead. This
\r
6424 2480: means exclusive access to the event list is guaranteed here.
\r
6426 2482: This function assumes that a check has already been made to ensure that
\r
6427 2483: pxEventList is not empty. */
\r
6428 2484: pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
\r
6429 BFD04584 0020FC5E LW V0, 32(S8)
\r
6430 BFD04588 6923 LW V0, 12(V0)
\r
6431 BFD0458A 6923 LW V0, 12(V0)
\r
6432 BFD0458C 0014F85E SW V0, 20(S8)
\r
6433 2485: configASSERT( pxUnblockedTCB );
\r
6434 BFD04590 0014FC5E LW V0, 20(S8)
\r
6435 BFD04594 000940A2 BNEZC V0, 0xBFD045AA
\r
6436 BFD04598 BFD141A2 LUI V0, 0xBFD1
\r
6437 BFD0459A 3082BFD1 LDC1 F30, 12418(S1)
\r
6438 BFD0459C 98103082 ADDIU A0, V0, -26608
\r
6439 BFD0459E 30A09810 SWC1 F0, 12448(S0)
\r
6440 BFD045A0 09B530A0 ADDIU A1, ZERO, 2485
\r
6441 BFD045A2 09B5 LBU V1, 5(V1)
\r
6442 BFD045A4 4B7E77E8 JALS vAssertCalled
\r
6443 BFD045A6 4B7E LW K1, 120(SP)
\r
6445 2486: ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
\r
6446 BFD045AA 0014FC5E LW V0, 20(S8)
\r
6447 BFD045AC 6D2C0014 EXT ZERO, S4, 20, 14
\r
6448 BFD045AE 6D2C ADDIU V0, V0, 24
\r
6449 BFD045B0 0C82 MOVE A0, V0
\r
6450 BFD045B2 00C877E8 JALS uxListRemove
\r
6451 BFD045B4 0C0000C8 SLL A2, T0, 1
\r
6454 2488: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
\r
6455 BFD045B8 805CFC5C LW V0, -32676(GP)
\r
6456 BFD045BC 002740A2 BNEZC V0, 0xBFD0460E
\r
6458 2490: ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );
\r
6459 BFD045C0 0014FC5E LW V0, 20(S8)
\r
6460 BFD045C4 6D22 ADDIU V0, V0, 4
\r
6461 BFD045C6 0C82 MOVE A0, V0
\r
6462 BFD045C8 00C877E8 JALS uxListRemove
\r
6463 BFD045CA 0C0000C8 SLL A2, T0, 1
\r
6465 2491: prvAddTaskToReadyList( pxUnblockedTCB );
\r
6466 BFD045CE 0014FC5E LW V0, 20(S8)
\r
6467 BFD045D2 692B LW V0, 44(V0)
\r
6468 BFD045D4 ED81 LI V1, 1
\r
6469 BFD045D6 18100062 SLLV V1, V0, V1
\r
6470 BFD045D8 FC5C1810 SB ZERO, -932(S0)
\r
6471 BFD045DA 8040FC5C LW V0, -32704(GP)
\r
6472 BFD045DE 44D3 OR16 V0, V1
\r
6473 BFD045E0 8040F85C SW V0, -32704(GP)
\r
6474 BFD045E4 0014FC5E LW V0, 20(S8)
\r
6475 BFD045E8 692B LW V0, 44(V0)
\r
6476 BFD045EA 2524 SLL V0, V0, 2
\r
6477 BFD045EC 25A4 SLL V1, V0, 2
\r
6478 BFD045EE 05B4 ADDU V1, V0, V1
\r
6479 BFD045F0 BFD241A2 LUI V0, 0xBFD2
\r
6480 BFD045F2 3042BFD2 LDC1 F30, 12354(S2)
\r
6481 BFD045F4 806C3042 ADDIU V0, V0, -32660
\r
6482 BFD045F8 05A6 ADDU V1, V1, V0
\r
6483 BFD045FA 0014FC5E LW V0, 20(S8)
\r
6484 BFD045FE 6D22 ADDIU V0, V0, 4
\r
6485 BFD04600 0C83 MOVE A0, V1
\r
6486 BFD04602 0CA2 MOVE A1, V0
\r
6487 BFD04604 3E4A77E8 JALS vListInsertEnd
\r
6488 BFD04606 0C003E4A LH S2, 3072(T2)
\r
6490 BFD0460A CC0C B 0xBFD04624
\r
6495 2495: /* The delayed and ready lists cannot be accessed, so hold this task
\r
6496 2496: pending until the scheduler is resumed. */
\r
6497 2497: vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
\r
6498 BFD0460E 0014FC5E LW V0, 20(S8)
\r
6499 BFD04610 6D2C0014 EXT ZERO, S4, 20, 14
\r
6500 BFD04612 6D2C ADDIU V0, V0, 24
\r
6501 BFD04614 BFD241A3 LUI V1, 0xBFD2
\r
6502 BFD04616 3083BFD2 LDC1 F30, 12419(S2)
\r
6503 BFD04618 80D03083 ADDIU A0, V1, -32560
\r
6504 BFD0461C 0CA2 MOVE A1, V0
\r
6505 BFD0461E 3E4A77E8 JALS vListInsertEnd
\r
6506 BFD04620 0C003E4A LH S2, 3072(T2)
\r
6510 2500: if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
\r
6511 BFD04624 0014FC5E LW V0, 20(S8)
\r
6512 BFD04628 69AB LW V1, 44(V0)
\r
6513 BFD0462A 8030FC5C LW V0, -32720(GP)
\r
6514 BFD0462E 692B LW V0, 44(V0)
\r
6515 BFD04630 13900062 SLTU V0, V0, V1
\r
6516 BFD04632 40E21390 ADDI GP, S0, 16610
\r
6517 BFD04634 000840E2 BEQZC V0, 0xBFD04648
\r
6519 2502: /* Return true if the task removed from the event list has a higher
\r
6520 2503: priority than the calling task. This allows the calling task to know if
\r
6521 2504: it should force a context switch now. */
\r
6522 2505: xReturn = pdTRUE;
\r
6523 BFD04638 ED01 LI V0, 1
\r
6524 BFD0463A 0010F85E SW V0, 16(S8)
\r
6526 2507: /* Mark that a yield is pending in case the user is not using the
\r
6527 2508: "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
\r
6528 2509: xYieldPending = pdTRUE;
\r
6529 BFD0463E ED01 LI V0, 1
\r
6530 BFD04640 804CF85C SW V0, -32692(GP)
\r
6531 BFD04644 CC03 B 0xBFD0464C
\r
6536 2513: xReturn = pdFALSE;
\r
6537 BFD04648 0010F81E SW ZERO, 16(S8)
\r
6540 2516: #if( configUSE_TICKLESS_IDLE != 0 )
\r
6542 2518: /* If a task is blocked on a kernel object then xNextTaskUnblockTime
\r
6543 2519: might be set to the blocked task's time out time. If the task is
\r
6544 2520: unblocked for a reason other than a timeout xNextTaskUnblockTime is
\r
6545 2521: normally left unchanged, because it is automatically reset to a new
\r
6546 2522: value when the tick count equals xNextTaskUnblockTime. However if
\r
6547 2523: tickless idling is used it might be more important to enter sleep mode
\r
6548 2524: at the earliest possible time - so reset xNextTaskUnblockTime here to
\r
6549 2525: ensure it is updated at the earliest possible time. */
\r
6550 2526: prvResetNextTaskUnblockTime();
\r
6554 2530: return xReturn;
\r
6555 BFD0464C 0010FC5E LW V0, 16(S8)
\r
6557 BFD04650 0FBE MOVE SP, S8
\r
6558 BFD04652 4BE7 LW RA, 28(SP)
\r
6559 BFD04654 4BC6 LW S8, 24(SP)
\r
6560 BFD04656 4C11 ADDIU SP, SP, 32
\r
6561 BFD04658 459F JR16 RA
\r
6563 2532: /*-----------------------------------------------------------*/
\r
6565 2534: BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
\r
6567 BFD042C4 4FF1 ADDIU SP, SP, -32
\r
6568 BFD042C6 CBE7 SW RA, 28(SP)
\r
6569 BFD042C8 CBC6 SW S8, 24(SP)
\r
6570 BFD042CA 0FDD MOVE S8, SP
\r
6571 BFD042CC 0020F89E SW A0, 32(S8)
\r
6572 BFD042D0 0024F8BE SW A1, 36(S8)
\r
6573 2536: TCB_t *pxUnblockedTCB;
\r
6574 2537: BaseType_t xReturn;
\r
6576 2539: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
\r
6577 2540: the event flags implementation. */
\r
6578 2541: configASSERT( uxSchedulerSuspended != pdFALSE );
\r
6579 BFD042D4 805CFC5C LW V0, -32676(GP)
\r
6580 BFD042D8 000940A2 BNEZC V0, 0xBFD042EE
\r
6581 BFD042DC BFD141A2 LUI V0, 0xBFD1
\r
6582 BFD042DE 3082BFD1 LDC1 F30, 12418(S1)
\r
6583 BFD042E0 98103082 ADDIU A0, V0, -26608
\r
6584 BFD042E2 30A09810 SWC1 F0, 12448(S0)
\r
6585 BFD042E4 09ED30A0 ADDIU A1, ZERO, 2541
\r
6586 BFD042E6 09ED LBU V1, 13(A2)
\r
6587 BFD042E8 4B7E77E8 JALS vAssertCalled
\r
6588 BFD042EA 4B7E LW K1, 120(SP)
\r
6591 2543: /* Store the new item value in the event list. */
\r
6592 2544: listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
\r
6593 BFD042EE 0024FC7E LW V1, 36(S8)
\r
6594 BFD042F2 800041A2 LUI V0, 0x8000
\r
6595 BFD042F6 44DA OR16 V1, V0
\r
6596 BFD042F8 0020FC5E LW V0, 32(S8)
\r
6597 BFD042FC E9A0 SW V1, 0(V0)
\r
6599 2546: /* Remove the event list form the event flag. Interrupts do not access
\r
6600 2547: event flags. */
\r
6601 2548: pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
\r
6602 BFD042FE 0020FC5E LW V0, 32(S8)
\r
6603 BFD04302 6923 LW V0, 12(V0)
\r
6604 BFD04304 0014F85E SW V0, 20(S8)
\r
6605 2549: configASSERT( pxUnblockedTCB );
\r
6606 BFD04308 0014FC5E LW V0, 20(S8)
\r
6607 BFD0430C 000940A2 BNEZC V0, 0xBFD04322
\r
6608 BFD04310 BFD141A2 LUI V0, 0xBFD1
\r
6609 BFD04312 3082BFD1 LDC1 F30, 12418(S1)
\r
6610 BFD04314 98103082 ADDIU A0, V0, -26608
\r
6611 BFD04316 30A09810 SWC1 F0, 12448(S0)
\r
6612 BFD04318 09F530A0 ADDIU A1, ZERO, 2549
\r
6613 BFD0431A 09F5 LBU V1, 5(A3)
\r
6614 BFD0431C 4B7E77E8 JALS vAssertCalled
\r
6615 BFD0431E 4B7E LW K1, 120(SP)
\r
6617 2550: ( void ) uxListRemove( pxEventListItem );
\r
6618 BFD04322 0020FC9E LW A0, 32(S8)
\r
6619 BFD04326 00C877E8 JALS uxListRemove
\r
6620 BFD04328 0C0000C8 SLL A2, T0, 1
\r
6623 2552: /* Remove the task from the delayed list and add it to the ready list. The
\r
6624 2553: scheduler is suspended so interrupts will not be accessing the ready
\r
6626 2555: ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );
\r
6627 BFD0432C 0014FC5E LW V0, 20(S8)
\r
6628 BFD04330 6D22 ADDIU V0, V0, 4
\r
6629 BFD04332 0C82 MOVE A0, V0
\r
6630 BFD04334 00C877E8 JALS uxListRemove
\r
6631 BFD04336 0C0000C8 SLL A2, T0, 1
\r
6633 2556: prvAddTaskToReadyList( pxUnblockedTCB );
\r
6634 BFD0433A 0014FC5E LW V0, 20(S8)
\r
6635 BFD0433E 692B LW V0, 44(V0)
\r
6636 BFD04340 ED81 LI V1, 1
\r
6637 BFD04342 18100062 SLLV V1, V0, V1
\r
6638 BFD04344 FC5C1810 SB ZERO, -932(S0)
\r
6639 BFD04346 8040FC5C LW V0, -32704(GP)
\r
6640 BFD0434A 44D3 OR16 V0, V1
\r
6641 BFD0434C 8040F85C SW V0, -32704(GP)
\r
6642 BFD04350 0014FC5E LW V0, 20(S8)
\r
6643 BFD04354 692B LW V0, 44(V0)
\r
6644 BFD04356 2524 SLL V0, V0, 2
\r
6645 BFD04358 25A4 SLL V1, V0, 2
\r
6646 BFD0435A 05B4 ADDU V1, V0, V1
\r
6647 BFD0435C BFD241A2 LUI V0, 0xBFD2
\r
6648 BFD0435E 3042BFD2 LDC1 F30, 12354(S2)
\r
6649 BFD04360 806C3042 ADDIU V0, V0, -32660
\r
6650 BFD04364 05A6 ADDU V1, V1, V0
\r
6651 BFD04366 0014FC5E LW V0, 20(S8)
\r
6652 BFD0436A 6D22 ADDIU V0, V0, 4
\r
6653 BFD0436C 0C83 MOVE A0, V1
\r
6654 BFD0436E 0CA2 MOVE A1, V0
\r
6655 BFD04370 3E4A77E8 JALS vListInsertEnd
\r
6656 BFD04372 0C003E4A LH S2, 3072(T2)
\r
6659 2558: if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
\r
6660 BFD04376 0014FC5E LW V0, 20(S8)
\r
6661 BFD0437A 69AB LW V1, 44(V0)
\r
6662 BFD0437C 8030FC5C LW V0, -32720(GP)
\r
6663 BFD04380 692B LW V0, 44(V0)
\r
6664 BFD04382 13900062 SLTU V0, V0, V1
\r
6665 BFD04384 40E21390 ADDI GP, S0, 16610
\r
6666 BFD04386 000840E2 BEQZC V0, 0xBFD0439A
\r
6668 2560: /* Return true if the task removed from the event list has
\r
6669 2561: a higher priority than the calling task. This allows
\r
6670 2562: the calling task to know if it should force a context
\r
6671 2563: switch now. */
\r
6672 2564: xReturn = pdTRUE;
\r
6673 BFD0438A ED01 LI V0, 1
\r
6674 BFD0438C 0010F85E SW V0, 16(S8)
\r
6676 2566: /* Mark that a yield is pending in case the user is not using the
\r
6677 2567: "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
\r
6678 2568: xYieldPending = pdTRUE;
\r
6679 BFD04390 ED01 LI V0, 1
\r
6680 BFD04392 804CF85C SW V0, -32692(GP)
\r
6681 BFD04396 CC03 B 0xBFD0439E
\r
6686 2572: xReturn = pdFALSE;
\r
6687 BFD0439A 0010F81E SW ZERO, 16(S8)
\r
6690 2575: return xReturn;
\r
6691 BFD0439E 0010FC5E LW V0, 16(S8)
\r
6693 BFD043A2 0FBE MOVE SP, S8
\r
6694 BFD043A4 4BE7 LW RA, 28(SP)
\r
6695 BFD043A6 4BC6 LW S8, 24(SP)
\r
6696 BFD043A8 4C11 ADDIU SP, SP, 32
\r
6697 BFD043AA 459F JR16 RA
\r
6699 2577: /*-----------------------------------------------------------*/
\r
6701 2579: void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
\r
6703 BFD08F4C 4FF5 ADDIU SP, SP, -24
\r
6704 BFD08F4E CBE5 SW RA, 20(SP)
\r
6705 BFD08F50 CBC4 SW S8, 16(SP)
\r
6706 BFD08F52 0FDD MOVE S8, SP
\r
6707 BFD08F54 0018F89E SW A0, 24(S8)
\r
6708 2581: configASSERT( pxTimeOut );
\r
6709 BFD08F58 0018FC5E LW V0, 24(S8)
\r
6710 BFD08F5C 000940A2 BNEZC V0, 0xBFD08F72
\r
6711 BFD08F60 BFD141A2 LUI V0, 0xBFD1
\r
6712 BFD08F62 3082BFD1 LDC1 F30, 12418(S1)
\r
6713 BFD08F64 98103082 ADDIU A0, V0, -26608
\r
6714 BFD08F66 30A09810 SWC1 F0, 12448(S0)
\r
6715 BFD08F68 0A1530A0 ADDIU A1, ZERO, 2581
\r
6716 BFD08F6A 0A15 LBU A0, 5(S1)
\r
6717 BFD08F6C 4B7E77E8 JALS vAssertCalled
\r
6718 BFD08F6E 4B7E LW K1, 120(SP)
\r
6720 2582: pxTimeOut->xOverflowCount = xNumOfOverflows;
\r
6721 BFD08F72 8050FC7C LW V1, -32688(GP)
\r
6722 BFD08F76 0018FC5E LW V0, 24(S8)
\r
6723 BFD08F7A E9A0 SW V1, 0(V0)
\r
6724 2583: pxTimeOut->xTimeOnEntering = xTickCount;
\r
6725 BFD08F7C 803CFC7C LW V1, -32708(GP)
\r
6726 BFD08F80 0018FC5E LW V0, 24(S8)
\r
6727 BFD08F84 E9A1 SW V1, 4(V0)
\r
6729 BFD08F86 0FBE MOVE SP, S8
\r
6730 BFD08F88 4BE5 LW RA, 20(SP)
\r
6731 BFD08F8A 4BC4 LW S8, 16(SP)
\r
6732 BFD08F8C 4C0D ADDIU SP, SP, 24
\r
6733 BFD08F8E 459F JR16 RA
\r
6735 2585: /*-----------------------------------------------------------*/
\r
6737 2587: BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
\r
6739 BFD03FEC 4FF1 ADDIU SP, SP, -32
\r
6740 BFD03FEE CBE7 SW RA, 28(SP)
\r
6741 BFD03FF0 CBC6 SW S8, 24(SP)
\r
6742 BFD03FF2 0FDD MOVE S8, SP
\r
6743 BFD03FF4 0020F89E SW A0, 32(S8)
\r
6744 BFD03FF8 0024F8BE SW A1, 36(S8)
\r
6745 2589: BaseType_t xReturn;
\r
6747 2591: configASSERT( pxTimeOut );
\r
6748 BFD03FFC 0020FC5E LW V0, 32(S8)
\r
6749 BFD04000 000940A2 BNEZC V0, 0xBFD04016
\r
6750 BFD04004 BFD141A2 LUI V0, 0xBFD1
\r
6751 BFD04006 3082BFD1 LDC1 F30, 12418(S1)
\r
6752 BFD04008 98103082 ADDIU A0, V0, -26608
\r
6753 BFD0400A 30A09810 SWC1 F0, 12448(S0)
\r
6754 BFD0400C 0A1F30A0 ADDIU A1, ZERO, 2591
\r
6755 BFD0400E 0A1F LBU A0, -1(S1)
\r
6756 BFD04010 4B7E77E8 JALS vAssertCalled
\r
6757 BFD04012 4B7E LW K1, 120(SP)
\r
6759 2592: configASSERT( pxTicksToWait );
\r
6760 BFD04016 0024FC5E LW V0, 36(S8)
\r
6761 BFD0401A 000940A2 BNEZC V0, 0xBFD04030
\r
6762 BFD0401E BFD141A2 LUI V0, 0xBFD1
\r
6763 BFD04020 3082BFD1 LDC1 F30, 12418(S1)
\r
6764 BFD04022 98103082 ADDIU A0, V0, -26608
\r
6765 BFD04024 30A09810 SWC1 F0, 12448(S0)
\r
6766 BFD04026 0A2030A0 ADDIU A1, ZERO, 2592
\r
6767 BFD04028 0A20 LBU A0, 0(V0)
\r
6768 BFD0402A 4B7E77E8 JALS vAssertCalled
\r
6769 BFD0402C 4B7E LW K1, 120(SP)
\r
6772 2594: taskENTER_CRITICAL();
\r
6773 BFD04030 33B877E8 JALS vTaskEnterCritical
\r
6774 BFD04032 0C0033B8 ADDIU SP, T8, 3072
\r
6777 2596: /* Minor optimisation. The tick count cannot change in this block. */
\r
6778 2597: const TickType_t xConstTickCount = xTickCount;
\r
6779 BFD04036 803CFC5C LW V0, -32708(GP)
\r
6780 BFD0403A 0014F85E SW V0, 20(S8)
\r
6782 2599: #if ( INCLUDE_vTaskSuspend == 1 )
\r
6783 2600: /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is
\r
6784 2601: the maximum block time then the task should block indefinitely, and
\r
6785 2602: therefore never time out. */
\r
6786 2603: if( *pxTicksToWait == portMAX_DELAY )
\r
6787 BFD0403E 0024FC5E LW V0, 36(S8)
\r
6788 BFD04042 69A0 LW V1, 0(V0)
\r
6789 BFD04044 ED7F LI V0, -1
\r
6790 BFD04046 0005B443 BNE V1, V0, 0xBFD04054
\r
6791 BFD04048 0C000005 SLL ZERO, A1, 1
\r
6794 2605: xReturn = pdFALSE;
\r
6795 BFD0404C 0010F81E SW ZERO, 16(S8)
\r
6796 BFD0404E CC3D0010 REPL.PH T9, 0x10
\r
6797 BFD04050 CC3D B 0xBFD040CC
\r
6800 2607: else /* We are not blocking indefinitely, perform the checks below. */
\r
6803 2610: if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
\r
6804 BFD04054 0020FC5E LW V0, 32(S8)
\r
6805 BFD04058 69A0 LW V1, 0(V0)
\r
6806 BFD0405A 8050FC5C LW V0, -32688(GP)
\r
6807 BFD0405E 000F9443 BEQ V1, V0, 0xBFD04080
\r
6808 BFD04060 0C00000F SLL ZERO, T7, 1
\r
6810 BFD04064 0020FC5E LW V0, 32(S8)
\r
6811 BFD04068 69A1 LW V1, 4(V0)
\r
6812 BFD0406A 0014FC5E LW V0, 20(S8)
\r
6813 BFD0406E 13900062 SLTU V0, V0, V1
\r
6814 BFD04070 40A21390 ADDI GP, S0, 16546
\r
6815 BFD04072 000540A2 BNEZC V0, 0xBFD04080
\r
6817 2612: /* The tick count is greater than the time at which vTaskSetTimeout()
\r
6818 2613: was called, but has also overflowed since vTaskSetTimeOut() was called.
\r
6819 2614: It must have wrapped all the way around and gone past us again. This
\r
6820 2615: passed since vTaskSetTimeout() was called. */
\r
6821 2616: xReturn = pdTRUE;
\r
6822 BFD04076 ED01 LI V0, 1
\r
6823 BFD04078 0010F85E SW V0, 16(S8)
\r
6824 BFD0407C CC27 B 0xBFD040CC
\r
6827 2618: else if( ( xConstTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait )
\r
6828 BFD04080 0020FC5E LW V0, 32(S8)
\r
6829 BFD04084 6921 LW V0, 4(V0)
\r
6830 BFD04086 0014FC7E LW V1, 20(S8)
\r
6831 BFD0408A 05A7 SUBU V1, V1, V0
\r
6832 BFD0408C 0024FC5E LW V0, 36(S8)
\r
6833 BFD04090 6920 LW V0, 0(V0)
\r
6834 BFD04092 13900043 SLTU V0, V1, V0
\r
6835 BFD04094 40E21390 ADDI GP, S0, 16610
\r
6836 BFD04096 001640E2 BEQZC V0, 0xBFD040C6
\r
6838 2620: /* Not a genuine timeout. Adjust parameters for time remaining. */
\r
6839 2621: *pxTicksToWait -= ( xConstTickCount - pxTimeOut->xTimeOnEntering );
\r
6840 BFD0409A 0024FC5E LW V0, 36(S8)
\r
6841 BFD0409E 69A0 LW V1, 0(V0)
\r
6842 BFD040A0 0020FC5E LW V0, 32(S8)
\r
6843 BFD040A4 6A21 LW A0, 4(V0)
\r
6844 BFD040A6 0014FC5E LW V0, 20(S8)
\r
6845 BFD040AA 0529 SUBU V0, A0, V0
\r
6846 BFD040AC 05A6 ADDU V1, V1, V0
\r
6847 BFD040AE 0024FC5E LW V0, 36(S8)
\r
6848 BFD040B2 E9A0 SW V1, 0(V0)
\r
6849 2622: vTaskSetTimeOutState( pxTimeOut );
\r
6850 BFD040B4 0020FC9E LW A0, 32(S8)
\r
6851 BFD040B8 47A677E8 JALS vTaskSetTimeOutState
\r
6853 2623: xReturn = pdFALSE;
\r
6854 BFD040BE 0010F81E SW ZERO, 16(S8)
\r
6855 BFD040C2 CC04 B 0xBFD040CC
\r
6860 2627: xReturn = pdTRUE;
\r
6861 BFD040C6 ED01 LI V0, 1
\r
6862 BFD040C8 0010F85E SW V0, 16(S8)
\r
6865 2630: taskEXIT_CRITICAL();
\r
6866 BFD040CC 40AA77E8 JALS vTaskExitCritical
\r
6867 BFD040CE 0C0040AA BNEZC T2, 0xBFD058D2
\r
6870 2632: return xReturn;
\r
6871 BFD040D2 0010FC5E LW V0, 16(S8)
\r
6873 BFD040D6 0FBE MOVE SP, S8
\r
6874 BFD040D8 4BE7 LW RA, 28(SP)
\r
6875 BFD040DA 4BC6 LW S8, 24(SP)
\r
6876 BFD040DC 4C11 ADDIU SP, SP, 32
\r
6877 BFD040DE 459F JR16 RA
\r
6879 2634: /*-----------------------------------------------------------*/
\r
6881 2636: void vTaskMissedYield( void )
\r
6883 BFD09E54 4FB0 ADDIU SP, SP, -8
\r
6884 BFD09E56 CBC1 SW S8, 4(SP)
\r
6885 BFD09E58 0FDD MOVE S8, SP
\r
6886 2638: xYieldPending = pdTRUE;
\r
6887 BFD09E5A ED01 LI V0, 1
\r
6888 BFD09E5C 804CF85C SW V0, -32692(GP)
\r
6890 BFD09E60 0FBE MOVE SP, S8
\r
6891 BFD09E62 4BC1 LW S8, 4(SP)
\r
6892 BFD09E64 4C05 ADDIU SP, SP, 8
\r
6893 BFD09E66 459F JR16 RA
\r
6895 2640: /*-----------------------------------------------------------*/
\r
6897 2642: #if ( configUSE_TRACE_FACILITY == 1 )
\r
6899 2644: UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
\r
6901 2646: UBaseType_t uxReturn;
\r
6902 2647: TCB_t *pxTCB;
\r
6904 2649: if( xTask != NULL )
\r
6906 2651: pxTCB = ( TCB_t * ) xTask;
\r
6907 2652: uxReturn = pxTCB->uxTaskNumber;
\r
6911 2656: uxReturn = 0U;
\r
6914 2659: return uxReturn;
\r
6917 2662: #endif /* configUSE_TRACE_FACILITY */
\r
6918 2663: /*-----------------------------------------------------------*/
\r
6920 2665: #if ( configUSE_TRACE_FACILITY == 1 )
\r
6922 2667: void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
\r
6924 2669: TCB_t *pxTCB;
\r
6926 2671: if( xTask != NULL )
\r
6928 2673: pxTCB = ( TCB_t * ) xTask;
\r
6929 2674: pxTCB->uxTaskNumber = uxHandle;
\r
6933 2678: #endif /* configUSE_TRACE_FACILITY */
\r
6936 2681: * -----------------------------------------------------------
\r
6937 2682: * The Idle task.
\r
6938 2683: * ----------------------------------------------------------
\r
6940 2685: * The portTASK_FUNCTION() macro is used to allow port/compiler specific
\r
6941 2686: * language extensions. The equivalent prototype for this function is:
\r
6943 2688: * void prvIdleTask( void *pvParameters );
\r
6946 2691: static portTASK_FUNCTION( prvIdleTask, pvParameters )
\r
6948 BFD08BC4 4FF1 ADDIU SP, SP, -32
\r
6949 BFD08BC6 CBE7 SW RA, 28(SP)
\r
6950 BFD08BC8 CBC6 SW S8, 24(SP)
\r
6951 BFD08BCA 0FDD MOVE S8, SP
\r
6952 BFD08BCC 0020F89E SW A0, 32(S8)
\r
6953 BFD08BD0 CC02 B 0xBFD08BD6
\r
6955 2693: /* Stop warnings. */
\r
6956 2694: ( void ) pvParameters;
\r
6960 2698: /* See if any tasks have been deleted. */
\r
6961 2699: prvCheckTasksWaitingTermination();
\r
6962 BFD08BD6 35AE77E8 JALS prvCheckTasksWaitingTermination
\r
6963 BFD08BD8 0C0035AE LHU T5, 3072(T6)
\r
6966 2701: #if ( configUSE_PREEMPTION == 0 )
\r
6968 2703: /* If we are not using preemption we keep forcing a task switch to
\r
6969 2704: see if any other task has become available. If we are using
\r
6970 2705: preemption we don't need to do this as any task becoming available
\r
6971 2706: will automatically get the processor anyway. */
\r
6972 2707: taskYIELD();
\r
6974 2709: #endif /* configUSE_PREEMPTION */
\r
6976 2711: #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
\r
6978 2713: /* When using preemption tasks of equal priority will be
\r
6979 2714: timesliced. If a task that is sharing the idle priority is ready
\r
6980 2715: to run then the idle task should yield before the end of the
\r
6983 2718: A critical region is not required here as we are just reading from
\r
6984 2719: the list, and an occasional incorrect value will not matter. If
\r
6985 2720: the ready list at the idle priority contains more than one task
\r
6986 2721: then a task other than the idle task is ready to execute. */
\r
6987 2722: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
\r
6988 BFD08BDC BFD241A2 LUI V0, 0xBFD2
\r
6989 BFD08BDE FC42BFD2 LDC1 F30, -958(S2)
\r
6990 BFD08BE0 806CFC42 LW V0, -32660(V0)
\r
6991 BFD08BE4 0002B042 SLTIU V0, V0, 2
\r
6992 BFD08BE8 FFF440A2 BNEZC V0, 0xBFD08BD4
\r
6993 BFD08BEA 77E8FFF4 LW RA, 30696(S4)
\r
6995 2724: taskYIELD();
\r
6996 BFD08BEC 4E5677E8 JALS ulPortGetCP0Cause
\r
6997 BFD08BEE 4E56 ADDIU S2, S2, -5
\r
6999 BFD08BF2 0010F85E SW V0, 16(S8)
\r
7000 BFD08BF6 0010FC5E LW V0, 16(S8)
\r
7001 BFD08BFA 01005042 ORI V0, V0, 256
\r
7002 BFD08BFE 0010F85E SW V0, 16(S8)
\r
7003 BFD08C02 0010FC9E LW A0, 16(S8)
\r
7004 BFD08C06 4E6677E8 JALS vPortSetCP0Cause
\r
7005 BFD08C08 4E66 ADDIU S3, S3, 3
\r
7010 2728: mtCOVERAGE_TEST_MARKER();
\r
7013 2731: #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
\r
7015 2733: #if ( configUSE_IDLE_HOOK == 1 )
\r
7017 2735: extern void vApplicationIdleHook( void );
\r
7019 2737: /* Call the user defined function from within the idle task. This
\r
7020 2738: allows the application designer to add background functionality
\r
7021 2739: without the overhead of a separate task.
\r
7022 2740: NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
\r
7023 2741: CALL A FUNCTION THAT MIGHT BLOCK. */
\r
7024 2742: vApplicationIdleHook();
\r
7026 2744: #endif /* configUSE_IDLE_HOOK */
\r
7028 2746: /* This conditional compilation should use inequality to 0, not equality
\r
7029 2747: to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
\r
7030 2748: user defined low power mode implementations require
\r
7031 2749: configUSE_TICKLESS_IDLE to be set to a value other than 1. */
\r
7032 2750: #if ( configUSE_TICKLESS_IDLE != 0 )
\r
7034 2752: TickType_t xExpectedIdleTime;
\r
7036 2754: /* It is not desirable to suspend then resume the scheduler on
\r
7037 2755: each iteration of the idle task. Therefore, a preliminary
\r
7038 2756: test of the expected idle time is performed without the
\r
7039 2757: scheduler suspended. The result here is not necessarily
\r
7041 2759: xExpectedIdleTime = prvGetExpectedIdleTime();
\r
7043 2761: if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
\r
7045 2763: vTaskSuspendAll();
\r
7047 2765: /* Now the scheduler is suspended, the expected idle
\r
7048 2766: time can be sampled again, and this time its value can
\r
7050 2768: configASSERT( xNextTaskUnblockTime >= xTickCount );
\r
7051 2769: xExpectedIdleTime = prvGetExpectedIdleTime();
\r
7053 2771: if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
\r
7055 2773: traceLOW_POWER_IDLE_BEGIN();
\r
7056 2774: portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
\r
7057 2775: traceLOW_POWER_IDLE_END();
\r
7061 2779: mtCOVERAGE_TEST_MARKER();
\r
7064 2782: ( void ) xTaskResumeAll();
\r
7068 2786: mtCOVERAGE_TEST_MARKER();
\r
7071 2789: #endif /* configUSE_TICKLESS_IDLE */
\r
7074 BFD08C0C CFE4 B 0xBFD08BD6
\r
7077 2792: /*-----------------------------------------------------------*/
\r
7079 2794: #if( configUSE_TICKLESS_IDLE != 0 )
\r
7081 2796: eSleepModeStatus eTaskConfirmSleepModeStatus( void )
\r
7083 2798: /* The idle task exists in addition to the application tasks. */
\r
7084 2799: const UBaseType_t uxNonApplicationTasks = 1;
\r
7085 2800: eSleepModeStatus eReturn = eStandardSleep;
\r
7087 2802: if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
\r
7089 2804: /* A task was made ready while the scheduler was suspended. */
\r
7090 2805: eReturn = eAbortSleep;
\r
7092 2807: else if( xYieldPending != pdFALSE )
\r
7094 2809: /* A yield was pended while the scheduler was suspended. */
\r
7095 2810: eReturn = eAbortSleep;
\r
7099 2814: /* If all the tasks are in the suspended list (which might mean they
\r
7100 2815: have an infinite block time rather than actually being suspended)
\r
7101 2816: then it is safe to turn all clocks off and just wait for external
\r
7102 2817: interrupts. */
\r
7103 2818: if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
\r
7105 2820: eReturn = eNoTasksWaitingTimeout;
\r
7109 2824: mtCOVERAGE_TEST_MARKER();
\r
7113 2828: return eReturn;
\r
7116 2831: #endif /* configUSE_TICKLESS_IDLE */
\r
7117 2832: /*-----------------------------------------------------------*/
\r
7119 2834: static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
\r
7121 BFD03CE8 4FED ADDIU SP, SP, -40
\r
7122 BFD03CEA CBE9 SW RA, 36(SP)
\r
7123 BFD03CEC CBC8 SW S8, 32(SP)
\r
7124 BFD03CEE 0FDD MOVE S8, SP
\r
7125 BFD03CF0 0028F89E SW A0, 40(S8)
\r
7126 BFD03CF4 002CF8BE SW A1, 44(S8)
\r
7127 BFD03CF8 0030F8DE SW A2, 48(S8)
\r
7128 BFD03CFC 0034F8FE SW A3, 52(S8)
\r
7129 BFD03D00 0038FC5E LW V0, 56(S8)
\r
7130 BFD03D04 0018385E SH V0, 24(S8)
\r
7131 2836: UBaseType_t x;
\r
7133 2838: /* Store the task name in the TCB. */
\r
7134 2839: for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
\r
7135 BFD03D08 0010F81E SW ZERO, 16(S8)
\r
7136 BFD03D0A CC1D0010 SHILO null, 16
\r
7137 BFD03D0C CC1D B 0xBFD03D48
\r
7139 BFD03D3E 0010FC5E LW V0, 16(S8)
\r
7140 BFD03D42 6D20 ADDIU V0, V0, 1
\r
7141 BFD03D44 0010F85E SW V0, 16(S8)
\r
7142 BFD03D48 0010FC5E LW V0, 16(S8)
\r
7143 BFD03D4C 0008B042 SLTIU V0, V0, 8
\r
7144 BFD03D50 FFDE40A2 BNEZC V0, 0xBFD03D10
\r
7145 BFD03D52 CC02FFDE LW S8, -13310(S8)
\r
7146 BFD03D54 CC02 B 0xBFD03D5A
\r
7149 2841: pxTCB->pcTaskName[ x ] = pcName[ x ];
\r
7150 BFD03D10 002CFC7E LW V1, 44(S8)
\r
7151 BFD03D14 0010FC5E LW V0, 16(S8)
\r
7152 BFD03D18 0526 ADDU V0, V1, V0
\r
7153 BFD03D1A 00001C62 LB V1, 0(V0)
\r
7154 BFD03D1E 0028FC9E LW A0, 40(S8)
\r
7155 BFD03D22 0010FC5E LW V0, 16(S8)
\r
7156 BFD03D26 0528 ADDU V0, A0, V0
\r
7157 BFD03D28 00341862 SB V1, 52(V0)
\r
7159 2843: /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
\r
7160 2844: configMAX_TASK_NAME_LEN characters just in case the memory after the
\r
7161 2845: string is not accessible (extremely unlikely). */
\r
7162 2846: if( pcName[ x ] == 0x00 )
\r
7163 BFD03D2C 002CFC7E LW V1, 44(S8)
\r
7164 BFD03D30 0010FC5E LW V0, 16(S8)
\r
7165 BFD03D34 0526 ADDU V0, V1, V0
\r
7166 BFD03D36 00001C42 LB V0, 0(V0)
\r
7167 BFD03D3A 000D40E2 BEQZC V0, 0xBFD03D58
\r
7174 2852: mtCOVERAGE_TEST_MARKER();
\r
7178 2856: /* Ensure the name string is terminated in the case that the string length
\r
7179 2857: was greater or equal to configMAX_TASK_NAME_LEN. */
\r
7180 2858: pxTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
\r
7181 BFD03D5A 0028FC5E LW V0, 40(S8)
\r
7182 BFD03D5E 003B1802 SB ZERO, 59(V0)
\r
7184 2860: /* This is used as an array index so must ensure it's not too large. First
\r
7185 2861: remove the privilege bit if one is present. */
\r
7186 2862: if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
\r
7187 BFD03D62 0030FC5E LW V0, 48(S8)
\r
7188 BFD03D66 0005B042 SLTIU V0, V0, 5
\r
7189 BFD03D6A 000340A2 BNEZC V0, 0xBFD03D74
\r
7191 2864: uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
\r
7192 BFD03D6E ED04 LI V0, 4
\r
7193 BFD03D70 0030F85E SW V0, 48(S8)
\r
7197 2868: mtCOVERAGE_TEST_MARKER();
\r
7200 2871: pxTCB->uxPriority = uxPriority;
\r
7201 BFD03D74 0028FC5E LW V0, 40(S8)
\r
7202 BFD03D78 0030FC7E LW V1, 48(S8)
\r
7203 BFD03D7C E9AB SW V1, 44(V0)
\r
7204 2872: #if ( configUSE_MUTEXES == 1 )
\r
7206 2874: pxTCB->uxBasePriority = uxPriority;
\r
7207 BFD03D7E 0028FC5E LW V0, 40(S8)
\r
7208 BFD03D82 0030FC7E LW V1, 48(S8)
\r
7209 BFD03D86 0040F862 SW V1, 64(V0)
\r
7210 2875: pxTCB->uxMutexesHeld = 0;
\r
7211 BFD03D8A 0028FC5E LW V0, 40(S8)
\r
7212 BFD03D8E 0044F802 SW ZERO, 68(V0)
\r
7214 2877: #endif /* configUSE_MUTEXES */
\r
7216 2879: vListInitialiseItem( &( pxTCB->xGenericListItem ) );
\r
7217 BFD03D92 0028FC5E LW V0, 40(S8)
\r
7218 BFD03D96 6D22 ADDIU V0, V0, 4
\r
7219 BFD03D98 0C82 MOVE A0, V0
\r
7220 BFD03D9A 4EE677E8 JALS vListInitialiseItem
\r
7221 BFD03D9C 4EE6 ADDIU S7, S7, 3
\r
7223 2880: vListInitialiseItem( &( pxTCB->xEventListItem ) );
\r
7224 BFD03DA0 0028FC5E LW V0, 40(S8)
\r
7225 BFD03DA2 6D2C0028 EXT AT, T0, 20, 14
\r
7226 BFD03DA4 6D2C ADDIU V0, V0, 24
\r
7227 BFD03DA6 0C82 MOVE A0, V0
\r
7228 BFD03DA8 4EE677E8 JALS vListInitialiseItem
\r
7229 BFD03DAA 4EE6 ADDIU S7, S7, 3
\r
7232 2882: /* Set the pxTCB as a link back from the ListItem_t. This is so we can get
\r
7233 2883: back to the containing TCB from a generic item in a list. */
\r
7234 2884: listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );
\r
7235 BFD03DAE 0028FC5E LW V0, 40(S8)
\r
7236 BFD03DB2 0028FC7E LW V1, 40(S8)
\r
7237 BFD03DB6 E9A4 SW V1, 16(V0)
\r
7239 2886: /* Event lists are always in priority order. */
\r
7240 2887: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
7241 BFD03DB8 ED85 LI V1, 5
\r
7242 BFD03DBA 0030FC5E LW V0, 48(S8)
\r
7243 BFD03DBE 05A7 SUBU V1, V1, V0
\r
7244 BFD03DC0 0028FC5E LW V0, 40(S8)
\r
7245 BFD03DC4 E9A6 SW V1, 24(V0)
\r
7246 2888: listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );
\r
7247 BFD03DC6 0028FC5E LW V0, 40(S8)
\r
7248 BFD03DCA 0028FC7E LW V1, 40(S8)
\r
7249 BFD03DCE E9A9 SW V1, 36(V0)
\r
7251 2890: #if ( portCRITICAL_NESTING_IN_TCB == 1 )
\r
7253 2892: pxTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
\r
7254 BFD03DD0 0028FC5E LW V0, 40(S8)
\r
7255 BFD03DD4 E82F SW S0, 60(V0)
\r
7257 2894: #endif /* portCRITICAL_NESTING_IN_TCB */
\r
7259 2896: #if ( configUSE_APPLICATION_TASK_TAG == 1 )
\r
7261 2898: pxTCB->pxTaskTag = NULL;
\r
7263 2900: #endif /* configUSE_APPLICATION_TASK_TAG */
\r
7265 2902: #if ( configGENERATE_RUN_TIME_STATS == 1 )
\r
7267 2904: pxTCB->ulRunTimeCounter = 0UL;
\r
7269 2906: #endif /* configGENERATE_RUN_TIME_STATS */
\r
7271 2908: #if ( portUSING_MPU_WRAPPERS == 1 )
\r
7273 2910: vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );
\r
7275 2912: #else /* portUSING_MPU_WRAPPERS */
\r
7277 2914: ( void ) xRegions;
\r
7278 2915: ( void ) usStackDepth;
\r
7280 2917: #endif /* portUSING_MPU_WRAPPERS */
\r
7282 2919: #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
\r
7284 2921: for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
\r
7286 2923: pxTCB->pvThreadLocalStoragePointers[ x ] = NULL;
\r
7291 2928: #if ( configUSE_TASK_NOTIFICATIONS == 1 )
\r
7293 2930: pxTCB->ulNotifiedValue = 0;
\r
7294 BFD03DD6 0028FC5E LW V0, 40(S8)
\r
7295 BFD03DDA 0048F802 SW ZERO, 72(V0)
\r
7296 2931: pxTCB->eNotifyState = eNotWaitingNotification;
\r
7297 BFD03DDE 0028FC5E LW V0, 40(S8)
\r
7298 BFD03DE2 004CF802 SW ZERO, 76(V0)
\r
7302 2935: #if ( configUSE_NEWLIB_REENTRANT == 1 )
\r
7304 2937: /* Initialise this task's Newlib reent structure. */
\r
7305 2938: _REENT_INIT_PTR( ( &( pxTCB->xNewLib_reent ) ) );
\r
7307 2940: #endif /* configUSE_NEWLIB_REENTRANT */
\r
7309 BFD03DE6 0FBE MOVE SP, S8
\r
7310 BFD03DE8 4BE9 LW RA, 36(SP)
\r
7311 BFD03DEA 4BC8 LW S8, 32(SP)
\r
7312 BFD03DEC 4C15 ADDIU SP, SP, 40
\r
7313 BFD03DEE 459F JR16 RA
\r
7315 2942: /*-----------------------------------------------------------*/
\r
7317 2944: #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
\r
7319 2946: void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
\r
7321 2948: TCB_t *pxTCB;
\r
7323 2950: if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
\r
7325 2952: pxTCB = prvGetTCBFromHandle( xTaskToSet );
\r
7326 2953: pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
\r
7330 2957: #endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
\r
7331 2958: /*-----------------------------------------------------------*/
\r
7333 2960: #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
\r
7335 2962: void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
\r
7337 2964: void *pvReturn = NULL;
\r
7338 2965: TCB_t *pxTCB;
\r
7340 2967: if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
\r
7342 2969: pxTCB = prvGetTCBFromHandle( xTaskToQuery );
\r
7343 2970: pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
\r
7347 2974: pvReturn = NULL;
\r
7350 2977: return pvReturn;
\r
7353 2980: #endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
\r
7354 2981: /*-----------------------------------------------------------*/
\r
7356 2983: #if ( portUSING_MPU_WRAPPERS == 1 )
\r
7358 2985: void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
\r
7360 2987: TCB_t *pxTCB;
\r
7362 2989: /* If null is passed in here then we are modifying the MPU settings of
\r
7363 2990: the calling task. */
\r
7364 2991: pxTCB = prvGetTCBFromHandle( xTaskToModify );
\r
7366 2993: vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
\r
7369 2996: #endif /* portUSING_MPU_WRAPPERS */
\r
7370 2997: /*-----------------------------------------------------------*/
\r
7372 2999: static void prvInitialiseTaskLists( void )
\r
7374 BFD0612C 4FF1 ADDIU SP, SP, -32
\r
7375 BFD0612E CBE7 SW RA, 28(SP)
\r
7376 BFD06130 CBC6 SW S8, 24(SP)
\r
7377 BFD06132 0FDD MOVE S8, SP
\r
7378 3001: UBaseType_t uxPriority;
\r
7380 3003: for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
\r
7381 BFD06134 0010F81E SW ZERO, 16(S8)
\r
7382 BFD06138 CC14 B 0xBFD06162
\r
7384 BFD06158 0010FC5E LW V0, 16(S8)
\r
7385 BFD0615C 6D20 ADDIU V0, V0, 1
\r
7386 BFD0615E 0010F85E SW V0, 16(S8)
\r
7387 BFD06162 0010FC5E LW V0, 16(S8)
\r
7388 BFD06166 0005B042 SLTIU V0, V0, 5
\r
7389 BFD0616A FFE740A2 BNEZC V0, 0xBFD0613C
\r
7390 BFD0616C 41A2FFE7 LW RA, 16802(A3)
\r
7392 3005: vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
\r
7393 BFD0613C 0010FC5E LW V0, 16(S8)
\r
7394 BFD06140 2524 SLL V0, V0, 2
\r
7395 BFD06142 25A4 SLL V1, V0, 2
\r
7396 BFD06144 05B4 ADDU V1, V0, V1
\r
7397 BFD06146 BFD241A2 LUI V0, 0xBFD2
\r
7398 BFD06148 3042BFD2 LDC1 F30, 12354(S2)
\r
7399 BFD0614A 806C3042 ADDIU V0, V0, -32660
\r
7400 BFD0614E 0526 ADDU V0, V1, V0
\r
7401 BFD06150 0C82 MOVE A0, V0
\r
7402 BFD06152 457077E8 JALS vListInitialise
\r
7403 BFD06154 4570 SWM16 0x3, 0(SP)
\r
7407 3008: vListInitialise( &xDelayedTaskList1 );
\r
7408 BFD0616E BFD241A2 LUI V0, 0xBFD2
\r
7409 BFD06170 3082BFD2 LDC1 F30, 12418(S2)
\r
7410 BFD06172 80F83082 ADDIU A0, V0, -32520
\r
7411 BFD06176 457077E8 JALS vListInitialise
\r
7412 BFD06178 4570 SWM16 0x3, 0(SP)
\r
7414 3009: vListInitialise( &xDelayedTaskList2 );
\r
7415 BFD0617C BFD241A2 LUI V0, 0xBFD2
\r
7416 BFD0617E 3082BFD2 LDC1 F30, 12418(S2)
\r
7417 BFD06180 81203082 ADDIU A0, V0, -32480
\r
7418 BFD06184 457077E8 JALS vListInitialise
\r
7419 BFD06186 4570 SWM16 0x3, 0(SP)
\r
7421 3010: vListInitialise( &xPendingReadyList );
\r
7422 BFD0618A BFD241A2 LUI V0, 0xBFD2
\r
7423 BFD0618C 3082BFD2 LDC1 F30, 12418(S2)
\r
7424 BFD0618E 80D03082 ADDIU A0, V0, -32560
\r
7425 BFD06192 457077E8 JALS vListInitialise
\r
7426 BFD06194 4570 SWM16 0x3, 0(SP)
\r
7429 3012: #if ( INCLUDE_vTaskDelete == 1 )
\r
7431 3014: vListInitialise( &xTasksWaitingTermination );
\r
7432 BFD06198 BFD241A2 LUI V0, 0xBFD2
\r
7433 BFD0619A 3082BFD2 LDC1 F30, 12418(S2)
\r
7434 BFD0619C 810C3082 ADDIU A0, V0, -32500
\r
7435 BFD061A0 457077E8 JALS vListInitialise
\r
7436 BFD061A2 4570 SWM16 0x3, 0(SP)
\r
7439 3016: #endif /* INCLUDE_vTaskDelete */
\r
7441 3018: #if ( INCLUDE_vTaskSuspend == 1 )
\r
7443 3020: vListInitialise( &xSuspendedTaskList );
\r
7444 BFD061A6 BFD241A2 LUI V0, 0xBFD2
\r
7445 BFD061A8 3082BFD2 LDC1 F30, 12418(S2)
\r
7446 BFD061AA 80E43082 ADDIU A0, V0, -32540
\r
7447 BFD061AE 457077E8 JALS vListInitialise
\r
7448 BFD061B0 4570 SWM16 0x3, 0(SP)
\r
7451 3022: #endif /* INCLUDE_vTaskSuspend */
\r
7453 3024: /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
\r
7454 3025: using list2. */
\r
7455 3026: pxDelayedTaskList = &xDelayedTaskList1;
\r
7456 BFD061B4 BFD241A2 LUI V0, 0xBFD2
\r
7457 BFD061B6 3042BFD2 LDC1 F30, 12354(S2)
\r
7458 BFD061B8 80F83042 ADDIU V0, V0, -32520
\r
7459 BFD061BC 8074F85C SW V0, -32652(GP)
\r
7460 3027: pxOverflowDelayedTaskList = &xDelayedTaskList2;
\r
7461 BFD061C0 BFD241A2 LUI V0, 0xBFD2
\r
7462 BFD061C2 3042BFD2 LDC1 F30, 12354(S2)
\r
7463 BFD061C4 81203042 ADDIU V0, V0, -32480
\r
7464 BFD061C8 8078F85C SW V0, -32648(GP)
\r
7466 BFD061CC 0FBE MOVE SP, S8
\r
7467 BFD061CE 4BE7 LW RA, 28(SP)
\r
7468 BFD061D0 4BC6 LW S8, 24(SP)
\r
7469 BFD061D2 4C11 ADDIU SP, SP, 32
\r
7470 BFD061D4 459F JR16 RA
\r
7472 3029: /*-----------------------------------------------------------*/
\r
7474 3031: static void prvCheckTasksWaitingTermination( void )
\r
7476 BFD06B5C 4FF1 ADDIU SP, SP, -32
\r
7477 BFD06B5E CBE7 SW RA, 28(SP)
\r
7478 BFD06B60 CBC6 SW S8, 24(SP)
\r
7479 BFD06B62 0FDD MOVE S8, SP
\r
7480 3033: #if ( INCLUDE_vTaskDelete == 1 )
\r
7482 3035: BaseType_t xListIsEmpty;
\r
7484 3037: /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called
\r
7485 3038: too often in the idle task. */
\r
7486 3039: while( uxTasksDeleted > ( UBaseType_t ) 0U )
\r
7487 BFD06B64 CC37 B 0xBFD06BD4
\r
7489 BFD06BD4 8034FC5C LW V0, -32716(GP)
\r
7490 BFD06BD8 FFC640A2 BNEZC V0, 0xBFD06B68
\r
7491 BFD06BDA 0FBEFFC6 LW S8, 4030(A2)
\r
7493 3041: vTaskSuspendAll();
\r
7494 BFD06B68 4EF477E8 JALS vTaskSuspendAll
\r
7495 BFD06B6A 4EF4 ADDIU S7, S7, -6
\r
7498 3043: xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );
\r
7499 BFD06B6E BFD241A2 LUI V0, 0xBFD2
\r
7500 BFD06B70 FC42BFD2 LDC1 F30, -958(S2)
\r
7501 BFD06B72 810CFC42 LW V0, -32500(V0)
\r
7502 BFD06B76 0001B042 SLTIU V0, V0, 1
\r
7503 BFD06B7A 0010F85E SW V0, 16(S8)
\r
7505 3045: ( void ) xTaskResumeAll();
\r
7506 BFD06B7E 158E77E8 JALS xTaskResumeAll
\r
7507 BFD06B80 0C00158E LBU T4, 3072(T6)
\r
7510 3047: if( xListIsEmpty == pdFALSE )
\r
7511 BFD06B84 0010FC5E LW V0, 16(S8)
\r
7512 BFD06B88 002440A2 BNEZC V0, 0xBFD06BD4
\r
7514 3049: TCB_t *pxTCB;
\r
7516 3051: taskENTER_CRITICAL();
\r
7517 BFD06B8C 33B877E8 JALS vTaskEnterCritical
\r
7518 BFD06B8E 0C0033B8 ADDIU SP, T8, 3072
\r
7521 3053: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
\r
7522 BFD06B92 BFD241A2 LUI V0, 0xBFD2
\r
7523 BFD06B94 3042BFD2 LDC1 F30, 12354(S2)
\r
7524 BFD06B96 810C3042 ADDIU V0, V0, -32500
\r
7525 BFD06B9A 6923 LW V0, 12(V0)
\r
7526 BFD06B9C 6923 LW V0, 12(V0)
\r
7527 BFD06B9E 0014F85E SW V0, 20(S8)
\r
7528 3054: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
7529 BFD06BA2 0014FC5E LW V0, 20(S8)
\r
7530 BFD06BA6 6D22 ADDIU V0, V0, 4
\r
7531 BFD06BA8 0C82 MOVE A0, V0
\r
7532 BFD06BAA 00C877E8 JALS uxListRemove
\r
7533 BFD06BAC 0C0000C8 SLL A2, T0, 1
\r
7535 3055: --uxCurrentNumberOfTasks;
\r
7536 BFD06BB0 8038FC5C LW V0, -32712(GP)
\r
7537 BFD06BB4 6D2E ADDIU V0, V0, -1
\r
7538 BFD06BB6 8038F85C SW V0, -32712(GP)
\r
7539 3056: --uxTasksDeleted;
\r
7540 BFD06BBA 8034FC5C LW V0, -32716(GP)
\r
7541 BFD06BBE 6D2E ADDIU V0, V0, -1
\r
7542 BFD06BC0 8034F85C SW V0, -32716(GP)
\r
7544 3058: taskEXIT_CRITICAL();
\r
7545 BFD06BC4 40AA77E8 JALS vTaskExitCritical
\r
7546 BFD06BC6 0C0040AA BNEZC T2, 0xBFD083CA
\r
7549 3060: prvDeleteTCB( pxTCB );
\r
7550 BFD06BCA 0014FC9E LW A0, 20(S8)
\r
7551 BFD06BCE 4C6E77E8 JALS prvDeleteTCB
\r
7552 BFD06BD0 4C6E ADDIU V1, V1, 7
\r
7557 3064: mtCOVERAGE_TEST_MARKER();
\r
7561 3068: #endif /* vTaskDelete */
\r
7563 BFD06BDC 0FBE MOVE SP, S8
\r
7564 BFD06BDE 4BE7 LW RA, 28(SP)
\r
7565 BFD06BE0 4BC6 LW S8, 24(SP)
\r
7566 BFD06BE2 4C11 ADDIU SP, SP, 32
\r
7567 BFD06BE4 459F JR16 RA
\r
7569 3070: /*-----------------------------------------------------------*/
\r
7571 3072: static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake )
\r
7573 BFD06E68 4FF5 ADDIU SP, SP, -24
\r
7574 BFD06E6A CBE5 SW RA, 20(SP)
\r
7575 BFD06E6C CBC4 SW S8, 16(SP)
\r
7576 BFD06E6E 0FDD MOVE S8, SP
\r
7577 BFD06E70 0018F89E SW A0, 24(S8)
\r
7578 3074: /* The list item will be inserted in wake time order. */
\r
7579 3075: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );
\r
7580 BFD06E74 8030FC5C LW V0, -32720(GP)
\r
7581 BFD06E78 0018FC7E LW V1, 24(S8)
\r
7582 BFD06E7C E9A1 SW V1, 4(V0)
\r
7584 3077: if( xTimeToWake < xTickCount )
\r
7585 BFD06E7E 803CFC5C LW V0, -32708(GP)
\r
7586 BFD06E82 0018FC7E LW V1, 24(S8)
\r
7587 BFD06E86 13900043 SLTU V0, V1, V0
\r
7588 BFD06E88 40E21390 ADDI GP, S0, 16610
\r
7589 BFD06E8A 000C40E2 BEQZC V0, 0xBFD06EA6
\r
7591 3079: /* Wake time has overflowed. Place this item in the overflow list. */
\r
7592 3080: vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );
\r
7593 BFD06E8E 8078FC7C LW V1, -32648(GP)
\r
7594 BFD06E92 8030FC5C LW V0, -32720(GP)
\r
7595 BFD06E96 6D22 ADDIU V0, V0, 4
\r
7596 BFD06E98 0C83 MOVE A0, V1
\r
7597 BFD06E9A 0CA2 MOVE A1, V0
\r
7598 BFD06E9C 304077E8 JALS vListInsert
\r
7599 BFD06E9E 0C003040 ADDIU V0, ZERO, 3072
\r
7601 BFD06EA2 CC17 B 0xBFD06ED2
\r
7606 3084: /* The wake time has not overflowed, so the current block list is used. */
\r
7607 3085: vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );
\r
7608 BFD06EA6 8074FC7C LW V1, -32652(GP)
\r
7609 BFD06EAA 8030FC5C LW V0, -32720(GP)
\r
7610 BFD06EAE 6D22 ADDIU V0, V0, 4
\r
7611 BFD06EB0 0C83 MOVE A0, V1
\r
7612 BFD06EB2 0CA2 MOVE A1, V0
\r
7613 BFD06EB4 304077E8 JALS vListInsert
\r
7614 BFD06EB6 0C003040 ADDIU V0, ZERO, 3072
\r
7617 3087: /* If the task entering the blocked state was placed at the head of the
\r
7618 3088: list of blocked tasks then xNextTaskUnblockTime needs to be updated
\r
7620 3090: if( xTimeToWake < xNextTaskUnblockTime )
\r
7621 BFD06EBA 8058FC5C LW V0, -32680(GP)
\r
7622 BFD06EBE 0018FC7E LW V1, 24(S8)
\r
7623 BFD06EC2 13900043 SLTU V0, V1, V0
\r
7624 BFD06EC4 40E21390 ADDI GP, S0, 16610
\r
7625 BFD06EC6 000440E2 BEQZC V0, 0xBFD06ED2
\r
7627 3092: xNextTaskUnblockTime = xTimeToWake;
\r
7628 BFD06ECA 0018FC5E LW V0, 24(S8)
\r
7629 BFD06ECE 8058F85C SW V0, -32680(GP)
\r
7633 3096: mtCOVERAGE_TEST_MARKER();
\r
7637 BFD06ED2 0FBE MOVE SP, S8
\r
7638 BFD06ED4 4BE5 LW RA, 20(SP)
\r
7639 BFD06ED6 4BC4 LW S8, 16(SP)
\r
7640 BFD06ED8 4C0D ADDIU SP, SP, 24
\r
7641 BFD06EDA 459F JR16 RA
\r
7643 3100: /*-----------------------------------------------------------*/
\r
7645 3102: static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer )
\r
7647 BFD06328 4FF1 ADDIU SP, SP, -32
\r
7648 BFD0632A CBE7 SW RA, 28(SP)
\r
7649 BFD0632C CBC6 SW S8, 24(SP)
\r
7650 BFD0632E 0FDD MOVE S8, SP
\r
7651 BFD06330 0C44 MOVE V0, A0
\r
7652 BFD06332 0024F8BE SW A1, 36(S8)
\r
7653 BFD06336 0020385E SH V0, 32(S8)
\r
7654 3104: TCB_t *pxNewTCB;
\r
7656 3106: /* If the stack grows down then allocate the stack then the TCB so the stack
\r
7657 3107: does not grow into the TCB. Likewise if the stack grows up then allocate
\r
7658 3108: the TCB then the stack. */
\r
7659 3109: #if( portSTACK_GROWTH > 0 )
\r
7661 3111: /* Allocate space for the TCB. Where the memory comes from depends on
\r
7662 3112: the implementation of the port malloc function. */
\r
7663 3113: pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
\r
7665 3115: if( pxNewTCB != NULL )
\r
7667 3117: /* Allocate space for the stack used by the task being created.
\r
7668 3118: The base of the stack memory stored in the TCB so the task can
\r
7669 3119: be deleted later if required. */
\r
7670 3120: pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
7672 3122: if( pxNewTCB->pxStack == NULL )
\r
7674 3124: /* Could not allocate the stack. Delete the allocated TCB. */
\r
7675 3125: vPortFree( pxNewTCB );
\r
7676 3126: pxNewTCB = NULL;
\r
7680 3130: #else /* portSTACK_GROWTH */
\r
7682 3132: StackType_t *pxStack;
\r
7684 3134: /* Allocate space for the stack used by the task being created. */
\r
7685 3135: pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
7686 BFD0633A 0024FC5E LW V0, 36(S8)
\r
7687 BFD0633E 000940A2 BNEZC V0, 0xBFD06354
\r
7688 BFD06342 0020345E LHU V0, 32(S8)
\r
7689 BFD06346 2524 SLL V0, V0, 2
\r
7690 BFD06348 0C82 MOVE A0, V0
\r
7691 BFD0634A 111677E8 JALS pvPortMalloc
\r
7692 BFD0634C 0C001116 ADDI T0, S6, 3072
\r
7694 BFD06350 CC03 B 0xBFD06358
\r
7696 BFD06354 0024FC5E LW V0, 36(S8)
\r
7697 BFD06358 0014F85E SW V0, 20(S8)
\r
7699 3137: if( pxStack != NULL )
\r
7700 BFD0635C 0014FC5E LW V0, 20(S8)
\r
7701 BFD06360 001840E2 BEQZC V0, 0xBFD06394
\r
7702 BFD06362 EE500018 AND SP, T8, ZERO
\r
7704 3139: /* Allocate space for the TCB. Where the memory comes from depends
\r
7705 3140: on the implementation of the port malloc function. */
\r
7706 3141: pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
\r
7707 BFD06364 EE50 LI A0, 80
\r
7708 BFD06366 111677E8 JALS pvPortMalloc
\r
7709 BFD06368 0C001116 ADDI T0, S6, 3072
\r
7711 BFD0636C 0010F85E SW V0, 16(S8)
\r
7713 3143: if( pxNewTCB != NULL )
\r
7714 BFD06370 0010FC5E LW V0, 16(S8)
\r
7715 BFD06374 000740E2 BEQZC V0, 0xBFD06386
\r
7717 3145: /* Store the stack location in the TCB. */
\r
7718 3146: pxNewTCB->pxStack = pxStack;
\r
7719 BFD06378 0010FC5E LW V0, 16(S8)
\r
7720 BFD0637C 0014FC7E LW V1, 20(S8)
\r
7721 BFD0637E E9AC0014 EXT ZERO, S4, 6, 30
\r
7722 BFD06380 E9AC SW V1, 48(V0)
\r
7723 BFD06382 CC0A B 0xBFD06398
\r
7728 3150: /* The stack cannot be used as the TCB was not created. Free it
\r
7730 3152: vPortFree( pxStack );
\r
7731 BFD06386 0014FC9E LW A0, 20(S8)
\r
7732 BFD0638A 2FEA77E8 JALS vPortFree
\r
7733 BFD0638C 2FEA ANDI A3, A2, 0x20
\r
7735 BFD06390 CC03 B 0xBFD06398
\r
7741 3157: pxNewTCB = NULL;
\r
7742 BFD06394 0010F81E SW ZERO, 16(S8)
\r
7745 3160: #endif /* portSTACK_GROWTH */
\r
7747 3162: if( pxNewTCB != NULL )
\r
7748 BFD06398 0010FC5E LW V0, 16(S8)
\r
7749 BFD0639C 000D40E2 BEQZC V0, 0xBFD063BA
\r
7751 3164: /* Avoid dependency on memset() if it is not required. */
\r
7752 3165: #if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
\r
7754 3167: /* Just to help debugging. */
\r
7755 3168: ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( StackType_t ) );
\r
7756 BFD063A0 0010FC5E LW V0, 16(S8)
\r
7757 BFD063A2 69AC0010 EXT ZERO, S0, 6, 14
\r
7758 BFD063A4 69AC LW V1, 48(V0)
\r
7759 BFD063A6 0020345E LHU V0, 32(S8)
\r
7760 BFD063AA 2524 SLL V0, V0, 2
\r
7761 BFD063AC 0C83 MOVE A0, V1
\r
7762 BFD063AE 00A530A0 ADDIU A1, ZERO, 165
\r
7763 BFD063B2 0CC2 MOVE A2, V0
\r
7764 BFD063B4 36F677E8 JALS 0xBFD06DEC
\r
7765 BFD063B6 0C0036F6 LHU S7, 3072(S6)
\r
7768 3170: #endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */
\r
7771 3173: return pxNewTCB;
\r
7772 BFD063BA 0010FC5E LW V0, 16(S8)
\r
7774 BFD063BE 0FBE MOVE SP, S8
\r
7775 BFD063C0 4BE7 LW RA, 28(SP)
\r
7776 BFD063C2 4BC6 LW S8, 24(SP)
\r
7777 BFD063C4 4C11 ADDIU SP, SP, 32
\r
7778 BFD063C6 459F JR16 RA
\r
7780 3175: /*-----------------------------------------------------------*/
\r
7782 3177: #if ( configUSE_TRACE_FACILITY == 1 )
\r
7784 3179: static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
\r
7786 3181: volatile TCB_t *pxNextTCB, *pxFirstTCB;
\r
7787 3182: UBaseType_t uxTask = 0;
\r
7789 3184: if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
\r
7791 3186: listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
\r
7793 3188: /* Populate an TaskStatus_t structure within the
\r
7794 3189: pxTaskStatusArray array for each task that is referenced from
\r
7795 3190: pxList. See the definition of TaskStatus_t in task.h for the
\r
7796 3191: meaning of each TaskStatus_t structure member. */
\r
7799 3194: listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
\r
7801 3196: pxTaskStatusArray[ uxTask ].xHandle = ( TaskHandle_t ) pxNextTCB;
\r
7802 3197: pxTaskStatusArray[ uxTask ].pcTaskName = ( const char * ) &( pxNextTCB->pcTaskName [ 0 ] );
\r
7803 3198: pxTaskStatusArray[ uxTask ].xTaskNumber = pxNextTCB->uxTCBNumber;
\r
7804 3199: pxTaskStatusArray[ uxTask ].eCurrentState = eState;
\r
7805 3200: pxTaskStatusArray[ uxTask ].uxCurrentPriority = pxNextTCB->uxPriority;
\r
7807 3202: #if ( INCLUDE_vTaskSuspend == 1 )
\r
7809 3204: /* If the task is in the suspended list then there is a chance
\r
7810 3205: it is actually just blocked indefinitely - so really it should
\r
7811 3206: be reported as being in the Blocked state. */
\r
7812 3207: if( eState == eSuspended )
\r
7814 3209: if( listLIST_ITEM_CONTAINER( &( pxNextTCB->xEventListItem ) ) != NULL )
\r
7816 3211: pxTaskStatusArray[ uxTask ].eCurrentState = eBlocked;
\r
7820 3215: #endif /* INCLUDE_vTaskSuspend */
\r
7822 3217: #if ( configUSE_MUTEXES == 1 )
\r
7824 3219: pxTaskStatusArray[ uxTask ].uxBasePriority = pxNextTCB->uxBasePriority;
\r
7828 3223: pxTaskStatusArray[ uxTask ].uxBasePriority = 0;
\r
7832 3227: #if ( configGENERATE_RUN_TIME_STATS == 1 )
\r
7834 3229: pxTaskStatusArray[ uxTask ].ulRunTimeCounter = pxNextTCB->ulRunTimeCounter;
\r
7838 3233: pxTaskStatusArray[ uxTask ].ulRunTimeCounter = 0;
\r
7842 3237: #if ( portSTACK_GROWTH > 0 )
\r
7844 3239: pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxEndOfStack );
\r
7848 3243: pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxStack );
\r
7854 3249: } while( pxNextTCB != pxFirstTCB );
\r
7858 3253: mtCOVERAGE_TEST_MARKER();
\r
7861 3256: return uxTask;
\r
7864 3259: #endif /* configUSE_TRACE_FACILITY */
\r
7865 3260: /*-----------------------------------------------------------*/
\r
7867 3262: #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
\r
7869 3264: static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
\r
7871 BFD089A4 4FF9 ADDIU SP, SP, -16
\r
7872 BFD089A6 CBC3 SW S8, 12(SP)
\r
7873 BFD089A8 0FDD MOVE S8, SP
\r
7874 BFD089AA 0010F89E SW A0, 16(S8)
\r
7875 3266: uint32_t ulCount = 0U;
\r
7876 BFD089AE 0000F81E SW ZERO, 0(S8)
\r
7878 3268: while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
\r
7879 BFD089B2 CC0B B 0xBFD089CA
\r
7881 BFD089CA 0010FC5E LW V0, 16(S8)
\r
7882 BFD089CE 09A0 LBU V1, 0(V0)
\r
7883 BFD089D0 00A53040 ADDIU V0, ZERO, 165
\r
7884 BFD089D4 FFEF9443 BEQ V1, V0, 0xBFD089B6
\r
7885 BFD089D6 0C00FFEF LW RA, 3072(T7)
\r
7888 3270: pucStackByte -= portSTACK_GROWTH;
\r
7889 BFD089B6 0010FC5E LW V0, 16(S8)
\r
7890 BFD089BA 6D20 ADDIU V0, V0, 1
\r
7891 BFD089BC 0010F85E SW V0, 16(S8)
\r
7893 BFD089C0 0000FC5E LW V0, 0(S8)
\r
7894 BFD089C4 6D20 ADDIU V0, V0, 1
\r
7895 BFD089C6 0000F85E SW V0, 0(S8)
\r
7898 3274: ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
\r
7899 BFD089DA 0000FC5E LW V0, 0(S8)
\r
7900 BFD089DE 2525 SRL V0, V0, 2
\r
7901 BFD089E0 0000F85E SW V0, 0(S8)
\r
7903 3276: return ( uint16_t ) ulCount;
\r
7904 BFD089E4 0000FC5E LW V0, 0(S8)
\r
7905 BFD089E8 2D2F ANDI V0, V0, 0xFFFF
\r
7907 BFD089EA 0FBE MOVE SP, S8
\r
7908 BFD089EC 4BC3 LW S8, 12(SP)
\r
7909 BFD089EE 4C09 ADDIU SP, SP, 16
\r
7910 BFD089F0 459F JR16 RA
\r
7913 3279: #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
\r
7914 3280: /*-----------------------------------------------------------*/
\r
7916 3282: #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
\r
7918 3284: UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
\r
7920 BFD08C10 4FED ADDIU SP, SP, -40
\r
7921 BFD08C12 CBE9 SW RA, 36(SP)
\r
7922 BFD08C14 CBC8 SW S8, 32(SP)
\r
7923 BFD08C16 0FDD MOVE S8, SP
\r
7924 BFD08C18 0028F89E SW A0, 40(S8)
\r
7925 3286: TCB_t *pxTCB;
\r
7926 3287: uint8_t *pucEndOfStack;
\r
7927 3288: UBaseType_t uxReturn;
\r
7929 3290: pxTCB = prvGetTCBFromHandle( xTask );
\r
7930 BFD08C1C 0028FC5E LW V0, 40(S8)
\r
7931 BFD08C20 000440A2 BNEZC V0, 0xBFD08C2C
\r
7932 BFD08C24 8030FC5C LW V0, -32720(GP)
\r
7933 BFD08C28 CC03 B 0xBFD08C30
\r
7935 BFD08C2C 0028FC5E LW V0, 40(S8)
\r
7936 BFD08C30 0010F85E SW V0, 16(S8)
\r
7938 3292: #if portSTACK_GROWTH < 0
\r
7940 3294: pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
\r
7941 BFD08C34 0010FC5E LW V0, 16(S8)
\r
7942 BFD08C36 692C0010 EXT ZERO, S0, 4, 14
\r
7943 BFD08C38 692C LW V0, 48(V0)
\r
7944 BFD08C3A 0014F85E SW V0, 20(S8)
\r
7948 3298: pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
\r
7952 3302: uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
\r
7953 BFD08C3E 0014FC9E LW A0, 20(S8)
\r
7954 BFD08C42 44D277E8 JALS prvTaskCheckFreeStackSpace
\r
7955 BFD08C44 44D2 OR16 V0, V0
\r
7957 BFD08C48 0018F85E SW V0, 24(S8)
\r
7959 3304: return uxReturn;
\r
7960 BFD08C4C 0018FC5E LW V0, 24(S8)
\r
7962 BFD08C50 0FBE MOVE SP, S8
\r
7963 BFD08C52 4BE9 LW RA, 36(SP)
\r
7964 BFD08C54 4BC8 LW S8, 32(SP)
\r
7965 BFD08C56 4C15 ADDIU SP, SP, 40
\r
7966 BFD08C58 459F JR16 RA
\r
7969 3307: #endif /* INCLUDE_uxTaskGetStackHighWaterMark */
\r
7970 3308: /*-----------------------------------------------------------*/
\r
7972 3310: #if ( INCLUDE_vTaskDelete == 1 )
\r
7974 3312: static void prvDeleteTCB( TCB_t *pxTCB )
\r
7976 BFD098DC 4FF5 ADDIU SP, SP, -24
\r
7977 BFD098DE CBE5 SW RA, 20(SP)
\r
7978 BFD098E0 CBC4 SW S8, 16(SP)
\r
7979 BFD098E2 0FDD MOVE S8, SP
\r
7980 BFD098E4 0018F89E SW A0, 24(S8)
\r
7981 3314: /* This call is required specifically for the TriCore port. It must be
\r
7982 3315: above the vPortFree() calls. The call is also used by ports/demos that
\r
7983 3316: want to allocate and clean RAM statically. */
\r
7984 3317: portCLEAN_UP_TCB( pxTCB );
\r
7986 3319: /* Free up the memory allocated by the scheduler for the task. It is up
\r
7987 3320: to the task to free any memory allocated at the application level. */
\r
7988 3321: #if ( configUSE_NEWLIB_REENTRANT == 1 )
\r
7990 3323: _reclaim_reent( &( pxTCB->xNewLib_reent ) );
\r
7992 3325: #endif /* configUSE_NEWLIB_REENTRANT */
\r
7994 3327: #if( portUSING_MPU_WRAPPERS == 1 )
\r
7996 3329: /* Only free the stack if it was allocated dynamically in the first
\r
7998 3331: if( pxTCB->xUsingStaticallyAllocatedStack == pdFALSE )
\r
8000 3333: vPortFreeAligned( pxTCB->pxStack );
\r
8005 3338: vPortFreeAligned( pxTCB->pxStack );
\r
8006 BFD098E8 0018FC5E LW V0, 24(S8)
\r
8007 BFD098EA 692C0018 EXT ZERO, T8, 4, 14
\r
8008 BFD098EC 692C LW V0, 48(V0)
\r
8009 BFD098EE 0C82 MOVE A0, V0
\r
8010 BFD098F0 2FEA77E8 JALS vPortFree
\r
8011 BFD098F2 2FEA ANDI A3, A2, 0x20
\r
8016 3342: vPortFree( pxTCB );
\r
8017 BFD098F6 0018FC9E LW A0, 24(S8)
\r
8018 BFD098FA 2FEA77E8 JALS vPortFree
\r
8019 BFD098FC 2FEA ANDI A3, A2, 0x20
\r
8022 BFD09900 0FBE MOVE SP, S8
\r
8023 BFD09902 4BE5 LW RA, 20(SP)
\r
8024 BFD09904 4BC4 LW S8, 16(SP)
\r
8025 BFD09906 4C0D ADDIU SP, SP, 24
\r
8026 BFD09908 459F JR16 RA
\r
8029 3345: #endif /* INCLUDE_vTaskDelete */
\r
8030 3346: /*-----------------------------------------------------------*/
\r
8032 3348: static void prvResetNextTaskUnblockTime( void )
\r
8034 BFD08F94 4FF9 ADDIU SP, SP, -16
\r
8035 BFD08F96 CBC3 SW S8, 12(SP)
\r
8036 BFD08F98 0FDD MOVE S8, SP
\r
8037 3350: TCB_t *pxTCB;
\r
8039 3352: if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
\r
8040 BFD08F9A 8074FC5C LW V0, -32652(GP)
\r
8041 BFD08F9E 6920 LW V0, 0(V0)
\r
8042 BFD08FA0 000340A2 BNEZC V0, 0xBFD08FAA
\r
8043 BFD08FA4 ED01 LI V0, 1
\r
8044 BFD08FA6 CC02 B 0xBFD08FAC
\r
8046 BFD08FAA 0C40 MOVE V0, ZERO
\r
8047 BFD08FAC 000540E2 BEQZC V0, 0xBFD08FBA
\r
8049 3354: /* The new current delayed list is empty. Set xNextTaskUnblockTime to
\r
8050 3355: the maximum possible value so it is extremely unlikely that the
\r
8051 3356: if( xTickCount >= xNextTaskUnblockTime ) test will pass until
\r
8052 3357: there is an item in the delayed list. */
\r
8053 3358: xNextTaskUnblockTime = portMAX_DELAY;
\r
8054 BFD08FB0 ED7F LI V0, -1
\r
8055 BFD08FB2 8058F85C SW V0, -32680(GP)
\r
8056 BFD08FB6 CC0C B 0xBFD08FD0
\r
8061 3362: /* The new current delayed list is not empty, get the value of
\r
8062 3363: the item at the head of the delayed list. This is the time at
\r
8063 3364: which the task at the head of the delayed list should be removed
\r
8064 3365: from the Blocked state. */
\r
8065 3366: ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
\r
8066 BFD08FBA 8074FC5C LW V0, -32652(GP)
\r
8067 BFD08FBE 6923 LW V0, 12(V0)
\r
8068 BFD08FC0 6923 LW V0, 12(V0)
\r
8069 BFD08FC2 0000F85E SW V0, 0(S8)
\r
8070 3367: xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xGenericListItem ) );
\r
8071 BFD08FC6 0000FC5E LW V0, 0(S8)
\r
8072 BFD08FCA 6921 LW V0, 4(V0)
\r
8073 BFD08FCC 8058F85C SW V0, -32680(GP)
\r
8076 BFD08FD0 0FBE MOVE SP, S8
\r
8077 BFD08FD2 4BC3 LW S8, 12(SP)
\r
8078 BFD08FD4 4C09 ADDIU SP, SP, 16
\r
8079 BFD08FD6 459F JR16 RA
\r
8081 3370: /*-----------------------------------------------------------*/
\r
8083 3372: #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
\r
8085 3374: TaskHandle_t xTaskGetCurrentTaskHandle( void )
\r
8087 BFD09E04 4FF9 ADDIU SP, SP, -16
\r
8088 BFD09E06 CBC3 SW S8, 12(SP)
\r
8089 BFD09E08 0FDD MOVE S8, SP
\r
8090 3376: TaskHandle_t xReturn;
\r
8092 3378: /* A critical section is not required as this is not called from
\r
8093 3379: an interrupt and the current TCB will always be the same for any
\r
8094 3380: individual execution thread. */
\r
8095 3381: xReturn = pxCurrentTCB;
\r
8096 BFD09E0A 8030FC5C LW V0, -32720(GP)
\r
8097 BFD09E0E 0000F85E SW V0, 0(S8)
\r
8099 3383: return xReturn;
\r
8100 BFD09E12 0000FC5E LW V0, 0(S8)
\r
8102 BFD09E16 0FBE MOVE SP, S8
\r
8103 BFD09E18 4BC3 LW S8, 12(SP)
\r
8104 BFD09E1A 4C09 ADDIU SP, SP, 16
\r
8105 BFD09E1C 459F JR16 RA
\r
8108 3386: #endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
\r
8109 3387: /*-----------------------------------------------------------*/
\r
8111 3389: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
\r
8113 3391: BaseType_t xTaskGetSchedulerState( void )
\r
8115 BFD0951C 4FF9 ADDIU SP, SP, -16
\r
8116 BFD0951E CBC3 SW S8, 12(SP)
\r
8117 BFD09520 0FDD MOVE S8, SP
\r
8118 3393: BaseType_t xReturn;
\r
8120 3395: if( xSchedulerRunning == pdFALSE )
\r
8121 BFD09522 8044FC5C LW V0, -32700(GP)
\r
8122 BFD09526 000540A2 BNEZC V0, 0xBFD09534
\r
8124 3397: xReturn = taskSCHEDULER_NOT_STARTED;
\r
8125 BFD0952A ED01 LI V0, 1
\r
8126 BFD0952C 0000F85E SW V0, 0(S8)
\r
8127 BFD0952E CC0C0000 INS ZERO, ZERO, 16, 10
\r
8128 BFD09530 CC0C B 0xBFD0954A
\r
8133 3401: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
\r
8134 BFD09534 805CFC5C LW V0, -32676(GP)
\r
8135 BFD09538 000540A2 BNEZC V0, 0xBFD09546
\r
8137 3403: xReturn = taskSCHEDULER_RUNNING;
\r
8138 BFD0953C ED02 LI V0, 2
\r
8139 BFD0953E 0000F85E SW V0, 0(S8)
\r
8140 BFD09542 CC03 B 0xBFD0954A
\r
8145 3407: xReturn = taskSCHEDULER_SUSPENDED;
\r
8146 BFD09546 0000F81E SW ZERO, 0(S8)
\r
8150 3411: return xReturn;
\r
8151 BFD0954A 0000FC5E LW V0, 0(S8)
\r
8153 BFD0954E 0FBE MOVE SP, S8
\r
8154 BFD09550 4BC3 LW S8, 12(SP)
\r
8155 BFD09552 4C09 ADDIU SP, SP, 16
\r
8156 BFD09554 459F JR16 RA
\r
8159 3414: #endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
\r
8160 3415: /*-----------------------------------------------------------*/
\r
8162 3417: #if ( configUSE_MUTEXES == 1 )
\r
8164 3419: void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
\r
8166 BFD03520 4FF1 ADDIU SP, SP, -32
\r
8167 BFD03522 CBE7 SW RA, 28(SP)
\r
8168 BFD03524 CBC6 SW S8, 24(SP)
\r
8169 BFD03526 0FDD MOVE S8, SP
\r
8170 BFD03528 0020F89E SW A0, 32(S8)
\r
8171 3421: TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
\r
8172 BFD0352C 0020FC5E LW V0, 32(S8)
\r
8173 BFD03530 0010F85E SW V0, 16(S8)
\r
8175 3423: /* If the mutex was given back by an interrupt while the queue was
\r
8176 3424: locked then the mutex holder might now be NULL. */
\r
8177 3425: if( pxMutexHolder != NULL )
\r
8178 BFD03534 0020FC5E LW V0, 32(S8)
\r
8179 BFD03538 007E40E2 BEQZC V0, 0xBFD03638
\r
8181 3427: /* If the holder of the mutex has a priority below the priority of
\r
8182 3428: the task attempting to obtain the mutex then it will temporarily
\r
8183 3429: inherit the priority of the task attempting to obtain the mutex. */
\r
8184 3430: if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )
\r
8185 BFD0353C 0010FC5E LW V0, 16(S8)
\r
8186 BFD03540 69AB LW V1, 44(V0)
\r
8187 BFD03542 8030FC5C LW V0, -32720(GP)
\r
8188 BFD03546 692B LW V0, 44(V0)
\r
8189 BFD03548 13900043 SLTU V0, V1, V0
\r
8190 BFD0354A 40E21390 ADDI GP, S0, 16610
\r
8191 BFD0354C 007440E2 BEQZC V0, 0xBFD03638
\r
8193 3432: /* Adjust the mutex holder state to account for its new
\r
8194 3433: priority. Only reset the event list item value if the value is
\r
8195 3434: not being used for anything else. */
\r
8196 3435: if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
\r
8197 BFD03550 0010FC5E LW V0, 16(S8)
\r
8198 BFD03554 6926 LW V0, 24(V0)
\r
8199 BFD03556 00094002 BLTZ V0, 0xBFD0356C
\r
8200 BFD03558 0C000009 SLL ZERO, T1, 1
\r
8203 3437: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
8204 BFD0355C 8030FC5C LW V0, -32720(GP)
\r
8205 BFD03560 692B LW V0, 44(V0)
\r
8206 BFD03562 ED85 LI V1, 5
\r
8207 BFD03564 05A7 SUBU V1, V1, V0
\r
8208 BFD03566 0010FC5E LW V0, 16(S8)
\r
8209 BFD0356A E9A6 SW V1, 24(V0)
\r
8213 3441: mtCOVERAGE_TEST_MARKER();
\r
8216 3444: /* If the task being modified is in the ready state it will need
\r
8217 3445: to be moved into a new list. */
\r
8218 3446: if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )
\r
8219 BFD0356C 0010FC5E LW V0, 16(S8)
\r
8220 BFD0356E 69A50010 LWX T5, 0(S0)
\r
8221 BFD03570 69A5 LW V1, 20(V0)
\r
8222 BFD03572 0010FC5E LW V0, 16(S8)
\r
8223 BFD03576 692B LW V0, 44(V0)
\r
8224 BFD03578 2524 SLL V0, V0, 2
\r
8225 BFD0357A 2624 SLL A0, V0, 2
\r
8226 BFD0357C 0644 ADDU A0, V0, A0
\r
8227 BFD0357E BFD241A2 LUI V0, 0xBFD2
\r
8228 BFD03580 3042BFD2 LDC1 F30, 12354(S2)
\r
8229 BFD03582 806C3042 ADDIU V0, V0, -32660
\r
8230 BFD03586 0528 ADDU V0, A0, V0
\r
8231 BFD03588 0004B443 BNE V1, V0, 0xBFD03594
\r
8232 BFD0358A 0C000004 SLL ZERO, A0, 1
\r
8234 BFD0358E ED01 LI V0, 1
\r
8235 BFD03590 CC02 B 0xBFD03596
\r
8237 BFD03594 0C40 MOVE V0, ZERO
\r
8238 BFD03596 004940E2 BEQZC V0, 0xBFD0362C
\r
8240 3448: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
8241 BFD0359A 0010FC5E LW V0, 16(S8)
\r
8242 BFD0359E 6D22 ADDIU V0, V0, 4
\r
8243 BFD035A0 0C82 MOVE A0, V0
\r
8244 BFD035A2 00C877E8 JALS uxListRemove
\r
8245 BFD035A4 0C0000C8 SLL A2, T0, 1
\r
8247 BFD035A8 001A40A2 BNEZC V0, 0xBFD035E0
\r
8249 3450: taskRESET_READY_PRIORITY( pxTCB->uxPriority );
\r
8250 BFD035AC 0010FC5E LW V0, 16(S8)
\r
8251 BFD035B0 692B LW V0, 44(V0)
\r
8252 BFD035B2 2524 SLL V0, V0, 2
\r
8253 BFD035B4 25A4 SLL V1, V0, 2
\r
8254 BFD035B6 05B4 ADDU V1, V0, V1
\r
8255 BFD035B8 BFD241A2 LUI V0, 0xBFD2
\r
8256 BFD035BA 3042BFD2 LDC1 F30, 12354(S2)
\r
8257 BFD035BC 806C3042 ADDIU V0, V0, -32660
\r
8258 BFD035C0 0526 ADDU V0, V1, V0
\r
8259 BFD035C2 6920 LW V0, 0(V0)
\r
8260 BFD035C4 000C40A2 BNEZC V0, 0xBFD035E0
\r
8261 BFD035C8 0010FC5E LW V0, 16(S8)
\r
8262 BFD035CC 692B LW V0, 44(V0)
\r
8263 BFD035CE ED81 LI V1, 1
\r
8264 BFD035D0 10100062 SLLV V0, V0, V1
\r
8265 BFD035D2 441A1010 ADDI ZERO, S0, 17434
\r
8266 BFD035D4 441A NOT16 V1, V0
\r
8267 BFD035D6 8040FC5C LW V0, -32704(GP)
\r
8268 BFD035DA 4493 AND16 V0, V1
\r
8269 BFD035DC 8040F85C SW V0, -32704(GP)
\r
8273 3454: mtCOVERAGE_TEST_MARKER();
\r
8276 3457: /* Inherit the priority before being moved into the new list. */
\r
8277 3458: pxTCB->uxPriority = pxCurrentTCB->uxPriority;
\r
8278 BFD035E0 8030FC5C LW V0, -32720(GP)
\r
8279 BFD035E4 69AB LW V1, 44(V0)
\r
8280 BFD035E6 0010FC5E LW V0, 16(S8)
\r
8281 BFD035EA E9AB SW V1, 44(V0)
\r
8282 3459: prvAddTaskToReadyList( pxTCB );
\r
8283 BFD035EC 0010FC5E LW V0, 16(S8)
\r
8284 BFD035F0 692B LW V0, 44(V0)
\r
8285 BFD035F2 ED81 LI V1, 1
\r
8286 BFD035F4 18100062 SLLV V1, V0, V1
\r
8287 BFD035F6 FC5C1810 SB ZERO, -932(S0)
\r
8288 BFD035F8 8040FC5C LW V0, -32704(GP)
\r
8289 BFD035FC 44D3 OR16 V0, V1
\r
8290 BFD035FE 8040F85C SW V0, -32704(GP)
\r
8291 BFD03602 0010FC5E LW V0, 16(S8)
\r
8292 BFD03606 692B LW V0, 44(V0)
\r
8293 BFD03608 2524 SLL V0, V0, 2
\r
8294 BFD0360A 25A4 SLL V1, V0, 2
\r
8295 BFD0360C 05B4 ADDU V1, V0, V1
\r
8296 BFD0360E BFD241A2 LUI V0, 0xBFD2
\r
8297 BFD03610 3042BFD2 LDC1 F30, 12354(S2)
\r
8298 BFD03612 806C3042 ADDIU V0, V0, -32660
\r
8299 BFD03616 05A6 ADDU V1, V1, V0
\r
8300 BFD03618 0010FC5E LW V0, 16(S8)
\r
8301 BFD0361C 6D22 ADDIU V0, V0, 4
\r
8302 BFD0361E 0C83 MOVE A0, V1
\r
8303 BFD03620 0CA2 MOVE A1, V0
\r
8304 BFD03622 3E4A77E8 JALS vListInsertEnd
\r
8305 BFD03624 0C003E4A LH S2, 3072(T2)
\r
8307 BFD03628 CC07 B 0xBFD03638
\r
8312 3463: /* Just inherit the priority. */
\r
8313 3464: pxTCB->uxPriority = pxCurrentTCB->uxPriority;
\r
8314 BFD0362C 8030FC5C LW V0, -32720(GP)
\r
8315 BFD03630 69AB LW V1, 44(V0)
\r
8316 BFD03632 0010FC5E LW V0, 16(S8)
\r
8317 BFD03636 E9AB SW V1, 44(V0)
\r
8320 3467: traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );
\r
8324 3471: mtCOVERAGE_TEST_MARKER();
\r
8329 3476: mtCOVERAGE_TEST_MARKER();
\r
8332 BFD03638 0FBE MOVE SP, S8
\r
8333 BFD0363A 4BE7 LW RA, 28(SP)
\r
8334 BFD0363C 4BC6 LW S8, 24(SP)
\r
8335 BFD0363E 4C11 ADDIU SP, SP, 32
\r
8336 BFD03640 459F JR16 RA
\r
8339 3480: #endif /* configUSE_MUTEXES */
\r
8340 3481: /*-----------------------------------------------------------*/
\r
8342 3483: #if ( configUSE_MUTEXES == 1 )
\r
8344 3485: BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
\r
8346 BFD02F04 4FF1 ADDIU SP, SP, -32
\r
8347 BFD02F06 CBE7 SW RA, 28(SP)
\r
8348 BFD02F08 CBC6 SW S8, 24(SP)
\r
8349 BFD02F0A 0FDD MOVE S8, SP
\r
8350 BFD02F0C 0020F89E SW A0, 32(S8)
\r
8351 3487: TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
\r
8352 BFD02F10 0020FC5E LW V0, 32(S8)
\r
8353 BFD02F14 0014F85E SW V0, 20(S8)
\r
8354 3488: BaseType_t xReturn = pdFALSE;
\r
8355 BFD02F18 0010F81E SW ZERO, 16(S8)
\r
8357 3490: if( pxMutexHolder != NULL )
\r
8358 BFD02F1C 0020FC5E LW V0, 32(S8)
\r
8359 BFD02F20 008B40E2 BEQZC V0, 0xBFD0303A
\r
8361 3492: /* A task can only have an inherited priority if it holds the mutex.
\r
8362 3493: If the mutex is held by a task then it cannot be given from an
\r
8363 3494: interrupt, and if a mutex is given by the holding task then it must
\r
8364 3495: be the running state task. */
\r
8365 3496: configASSERT( pxTCB == pxCurrentTCB );
\r
8366 BFD02F24 8030FC5C LW V0, -32720(GP)
\r
8367 BFD02F28 0014FC7E LW V1, 20(S8)
\r
8368 BFD02F2C 000A9443 BEQ V1, V0, 0xBFD02F44
\r
8369 BFD02F2E 0C00000A SLL ZERO, T2, 1
\r
8371 BFD02F32 BFD141A2 LUI V0, 0xBFD1
\r
8372 BFD02F34 3082BFD1 LDC1 F30, 12418(S1)
\r
8373 BFD02F36 98103082 ADDIU A0, V0, -26608
\r
8374 BFD02F38 30A09810 SWC1 F0, 12448(S0)
\r
8375 BFD02F3A 0DA830A0 ADDIU A1, ZERO, 3496
\r
8376 BFD02F3C 0DA8 MOVE T5, T0
\r
8377 BFD02F3E 4B7E77E8 JALS vAssertCalled
\r
8378 BFD02F40 4B7E LW K1, 120(SP)
\r
8381 3498: configASSERT( pxTCB->uxMutexesHeld );
\r
8382 BFD02F44 0014FC5E LW V0, 20(S8)
\r
8383 BFD02F48 0044FC42 LW V0, 68(V0)
\r
8384 BFD02F4C 000940A2 BNEZC V0, 0xBFD02F62
\r
8385 BFD02F50 BFD141A2 LUI V0, 0xBFD1
\r
8386 BFD02F52 3082BFD1 LDC1 F30, 12418(S1)
\r
8387 BFD02F54 98103082 ADDIU A0, V0, -26608
\r
8388 BFD02F56 30A09810 SWC1 F0, 12448(S0)
\r
8389 BFD02F58 0DAA30A0 ADDIU A1, ZERO, 3498
\r
8390 BFD02F5A 0DAA MOVE T5, T2
\r
8391 BFD02F5C 4B7E77E8 JALS vAssertCalled
\r
8392 BFD02F5E 4B7E LW K1, 120(SP)
\r
8394 3499: ( pxTCB->uxMutexesHeld )--;
\r
8395 BFD02F62 0014FC5E LW V0, 20(S8)
\r
8396 BFD02F66 0044FC42 LW V0, 68(V0)
\r
8397 BFD02F6A 6DAE ADDIU V1, V0, -1
\r
8398 BFD02F6C 0014FC5E LW V0, 20(S8)
\r
8399 BFD02F70 0044F862 SW V1, 68(V0)
\r
8401 3501: /* Has the holder of the mutex inherited the priority of another
\r
8403 3503: if( pxTCB->uxPriority != pxTCB->uxBasePriority )
\r
8404 BFD02F74 0014FC5E LW V0, 20(S8)
\r
8405 BFD02F78 69AB LW V1, 44(V0)
\r
8406 BFD02F7A 0014FC5E LW V0, 20(S8)
\r
8407 BFD02F7E 0040FC42 LW V0, 64(V0)
\r
8408 BFD02F82 005A9443 BEQ V1, V0, 0xBFD0303A
\r
8409 BFD02F84 0C00005A SLL V0, K0, 1
\r
8412 3505: /* Only disinherit if no other mutexes are held. */
\r
8413 3506: if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
\r
8414 BFD02F88 0014FC5E LW V0, 20(S8)
\r
8415 BFD02F8C 0044FC42 LW V0, 68(V0)
\r
8416 BFD02F90 005340A2 BNEZC V0, 0xBFD0303A
\r
8418 3508: /* A task can only have an inherited priority if it holds
\r
8419 3509: the mutex. If the mutex is held by a task then it cannot be
\r
8420 3510: given from an interrupt, and if a mutex is given by the
\r
8421 3511: holding task then it must be the running state task. Remove
\r
8422 3512: the holding task from the ready list. */
\r
8423 3513: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
8424 BFD02F94 0014FC5E LW V0, 20(S8)
\r
8425 BFD02F98 6D22 ADDIU V0, V0, 4
\r
8426 BFD02F9A 0C82 MOVE A0, V0
\r
8427 BFD02F9C 00C877E8 JALS uxListRemove
\r
8428 BFD02F9E 0C0000C8 SLL A2, T0, 1
\r
8430 BFD02FA2 001A40A2 BNEZC V0, 0xBFD02FDA
\r
8432 3515: taskRESET_READY_PRIORITY( pxTCB->uxPriority );
\r
8433 BFD02FA6 0014FC5E LW V0, 20(S8)
\r
8434 BFD02FAA 692B LW V0, 44(V0)
\r
8435 BFD02FAC 2524 SLL V0, V0, 2
\r
8436 BFD02FAE 25A4 SLL V1, V0, 2
\r
8437 BFD02FB0 05B4 ADDU V1, V0, V1
\r
8438 BFD02FB2 BFD241A2 LUI V0, 0xBFD2
\r
8439 BFD02FB4 3042BFD2 LDC1 F30, 12354(S2)
\r
8440 BFD02FB6 806C3042 ADDIU V0, V0, -32660
\r
8441 BFD02FBA 0526 ADDU V0, V1, V0
\r
8442 BFD02FBC 6920 LW V0, 0(V0)
\r
8443 BFD02FBE 000C40A2 BNEZC V0, 0xBFD02FDA
\r
8444 BFD02FC2 0014FC5E LW V0, 20(S8)
\r
8445 BFD02FC6 692B LW V0, 44(V0)
\r
8446 BFD02FC8 ED81 LI V1, 1
\r
8447 BFD02FCA 10100062 SLLV V0, V0, V1
\r
8448 BFD02FCC 441A1010 ADDI ZERO, S0, 17434
\r
8449 BFD02FCE 441A NOT16 V1, V0
\r
8450 BFD02FD0 8040FC5C LW V0, -32704(GP)
\r
8451 BFD02FD4 4493 AND16 V0, V1
\r
8452 BFD02FD6 8040F85C SW V0, -32704(GP)
\r
8456 3519: mtCOVERAGE_TEST_MARKER();
\r
8459 3522: /* Disinherit the priority before adding the task into the
\r
8460 3523: new ready list. */
\r
8461 3524: traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
\r
8462 3525: pxTCB->uxPriority = pxTCB->uxBasePriority;
\r
8463 BFD02FDA 0014FC5E LW V0, 20(S8)
\r
8464 BFD02FDE 0040FC62 LW V1, 64(V0)
\r
8465 BFD02FE2 0014FC5E LW V0, 20(S8)
\r
8466 BFD02FE6 E9AB SW V1, 44(V0)
\r
8468 3527: /* Reset the event list item value. It cannot be in use for
\r
8469 3528: any other purpose if this task is running, and it must be
\r
8470 3529: running to give back the mutex. */
\r
8471 3530: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
8472 BFD02FE8 0014FC5E LW V0, 20(S8)
\r
8473 BFD02FEC 692B LW V0, 44(V0)
\r
8474 BFD02FEE ED85 LI V1, 5
\r
8475 BFD02FF0 05A7 SUBU V1, V1, V0
\r
8476 BFD02FF2 0014FC5E LW V0, 20(S8)
\r
8477 BFD02FF6 E9A6 SW V1, 24(V0)
\r
8478 3531: prvAddTaskToReadyList( pxTCB );
\r
8479 BFD02FF8 0014FC5E LW V0, 20(S8)
\r
8480 BFD02FFC 692B LW V0, 44(V0)
\r
8481 BFD02FFE ED81 LI V1, 1
\r
8482 BFD03000 18100062 SLLV V1, V0, V1
\r
8483 BFD03002 FC5C1810 SB ZERO, -932(S0)
\r
8484 BFD03004 8040FC5C LW V0, -32704(GP)
\r
8485 BFD03008 44D3 OR16 V0, V1
\r
8486 BFD0300A 8040F85C SW V0, -32704(GP)
\r
8487 BFD0300E 0014FC5E LW V0, 20(S8)
\r
8488 BFD03012 692B LW V0, 44(V0)
\r
8489 BFD03014 2524 SLL V0, V0, 2
\r
8490 BFD03016 25A4 SLL V1, V0, 2
\r
8491 BFD03018 05B4 ADDU V1, V0, V1
\r
8492 BFD0301A BFD241A2 LUI V0, 0xBFD2
\r
8493 BFD0301C 3042BFD2 LDC1 F30, 12354(S2)
\r
8494 BFD0301E 806C3042 ADDIU V0, V0, -32660
\r
8495 BFD03022 05A6 ADDU V1, V1, V0
\r
8496 BFD03024 0014FC5E LW V0, 20(S8)
\r
8497 BFD03028 6D22 ADDIU V0, V0, 4
\r
8498 BFD0302A 0C83 MOVE A0, V1
\r
8499 BFD0302C 0CA2 MOVE A1, V0
\r
8500 BFD0302E 3E4A77E8 JALS vListInsertEnd
\r
8501 BFD03030 0C003E4A LH S2, 3072(T2)
\r
8504 3533: /* Return true to indicate that a context switch is required.
\r
8505 3534: This is only actually required in the corner case whereby
\r
8506 3535: multiple mutexes were held and the mutexes were given back
\r
8507 3536: in an order different to that in which they were taken.
\r
8508 3537: If a context switch did not occur when the first mutex was
\r
8509 3538: returned, even if a task was waiting on it, then a context
\r
8510 3539: switch should occur when the last mutex is returned whether
\r
8511 3540: a task is waiting on it or not. */
\r
8512 3541: xReturn = pdTRUE;
\r
8513 BFD03034 ED01 LI V0, 1
\r
8514 BFD03036 0010F85E SW V0, 16(S8)
\r
8518 3545: mtCOVERAGE_TEST_MARKER();
\r
8523 3550: mtCOVERAGE_TEST_MARKER();
\r
8528 3555: mtCOVERAGE_TEST_MARKER();
\r
8531 3558: return xReturn;
\r
8532 BFD0303A 0010FC5E LW V0, 16(S8)
\r
8534 BFD0303E 0FBE MOVE SP, S8
\r
8535 BFD03040 4BE7 LW RA, 28(SP)
\r
8536 BFD03042 4BC6 LW S8, 24(SP)
\r
8537 BFD03044 4C11 ADDIU SP, SP, 32
\r
8538 BFD03046 459F JR16 RA
\r
8541 3561: #endif /* configUSE_MUTEXES */
\r
8542 3562: /*-----------------------------------------------------------*/
\r
8544 3564: #if ( portCRITICAL_NESTING_IN_TCB == 1 )
\r
8546 3566: void vTaskEnterCritical( void )
\r
8548 BFD06770 4FF1 ADDIU SP, SP, -32
\r
8549 BFD06772 CBE7 SW RA, 28(SP)
\r
8550 BFD06774 CBC6 SW S8, 24(SP)
\r
8551 BFD06776 0FDD MOVE S8, SP
\r
8552 3568: portDISABLE_INTERRUPTS();
\r
8553 BFD06778 4E3677E8 JALS ulPortGetCP0Status
\r
8554 BFD0677A 4E36 ADDIU S1, S1, -5
\r
8556 BFD0677E 0010F85E SW V0, 16(S8)
\r
8557 BFD06782 0010FC7E LW V1, 16(S8)
\r
8558 BFD06786 000141A2 LUI V0, 0x1
\r
8559 BFD0678A FC005042 ORI V0, V0, -1024
\r
8560 BFD0678C 4493FC00 LW ZERO, 17555(ZERO)
\r
8561 BFD0678E 4493 AND16 V0, V1
\r
8562 BFD06790 50400042 SRL V0, V0, 10
\r
8563 BFD06792 B0425040 ORI V0, ZERO, -20414
\r
8564 BFD06794 0003B042 SLTIU V0, V0, 3
\r
8565 BFD06798 001140E2 BEQZC V0, 0xBFD067BE
\r
8566 BFD0679C 0010FC7E LW V1, 16(S8)
\r
8567 BFD067A0 FFFE41A2 LUI V0, 0xFFFE
\r
8568 BFD067A2 5042FFFE LW RA, 20546(S8)
\r
8569 BFD067A4 03FF5042 ORI V0, V0, 1023
\r
8570 BFD067A8 4493 AND16 V0, V1
\r
8571 BFD067AA 0010F85E SW V0, 16(S8)
\r
8572 BFD067AE 0010FC5E LW V0, 16(S8)
\r
8573 BFD067B2 0C005042 ORI V0, V0, 3072
\r
8575 BFD067B6 0C82 MOVE A0, V0
\r
8576 BFD067B8 4E4677E8 JALS vPortSetCP0Status
\r
8577 BFD067BA 4E46 ADDIU S2, S2, 3
\r
8580 3570: if( xSchedulerRunning != pdFALSE )
\r
8581 BFD067BE 8044FC5C LW V0, -32700(GP)
\r
8582 BFD067C2 001940E2 BEQZC V0, 0xBFD067F8
\r
8584 3572: ( pxCurrentTCB->uxCriticalNesting )++;
\r
8585 BFD067C6 8030FC5C LW V0, -32720(GP)
\r
8586 BFD067CA 69AF LW V1, 60(V0)
\r
8587 BFD067CC 6DB0 ADDIU V1, V1, 1
\r
8588 BFD067CE E9AF SW V1, 60(V0)
\r
8590 3574: /* This is not the interrupt safe version of the enter critical
\r
8591 3575: function so assert() if it is being called from an interrupt
\r
8592 3576: context. Only API functions that end in "FromISR" can be used in an
\r
8593 3577: interrupt. Only assert if the critical nesting count is 1 to
\r
8594 3578: protect against recursive calls if the assert function also uses a
\r
8595 3579: critical section. */
\r
8596 3580: if( pxCurrentTCB->uxCriticalNesting == 1 )
\r
8597 BFD067D0 8030FC5C LW V0, -32720(GP)
\r
8598 BFD067D4 69AF LW V1, 60(V0)
\r
8599 BFD067D6 ED01 LI V0, 1
\r
8600 BFD067D8 000EB443 BNE V1, V0, 0xBFD067F8
\r
8601 BFD067DA 0C00000E SLL ZERO, T6, 1
\r
8604 3582: portASSERT_IF_IN_ISR();
\r
8605 BFD067DE 8014FC5C LW V0, -32748(GP)
\r
8606 BFD067E2 000940E2 BEQZC V0, 0xBFD067F8
\r
8607 BFD067E6 BFD141A2 LUI V0, 0xBFD1
\r
8608 BFD067E8 3082BFD1 LDC1 F30, 12418(S1)
\r
8609 BFD067EA 98103082 ADDIU A0, V0, -26608
\r
8610 BFD067EC 30A09810 SWC1 F0, 12448(S0)
\r
8611 BFD067EE 0DFE30A0 ADDIU A1, ZERO, 3582
\r
8612 BFD067F0 0DFE MOVE T7, S8
\r
8613 BFD067F2 4B7E77E8 JALS vAssertCalled
\r
8614 BFD067F4 4B7E LW K1, 120(SP)
\r
8621 3588: mtCOVERAGE_TEST_MARKER();
\r
8624 BFD067F8 0FBE MOVE SP, S8
\r
8625 BFD067FA 4BE7 LW RA, 28(SP)
\r
8626 BFD067FC 4BC6 LW S8, 24(SP)
\r
8627 BFD067FE 4C11 ADDIU SP, SP, 32
\r
8628 BFD06800 459F JR16 RA
\r
8631 3592: #endif /* portCRITICAL_NESTING_IN_TCB */
\r
8632 3593: /*-----------------------------------------------------------*/
\r
8634 3595: #if ( portCRITICAL_NESTING_IN_TCB == 1 )
\r
8636 3597: void vTaskExitCritical( void )
\r
8638 BFD08154 4FF1 ADDIU SP, SP, -32
\r
8639 BFD08156 CBE7 SW RA, 28(SP)
\r
8640 BFD08158 CBC6 SW S8, 24(SP)
\r
8641 BFD0815A 0FDD MOVE S8, SP
\r
8642 3599: if( xSchedulerRunning != pdFALSE )
\r
8643 BFD0815C 8044FC5C LW V0, -32700(GP)
\r
8644 BFD08160 002240E2 BEQZC V0, 0xBFD081A8
\r
8646 3601: if( pxCurrentTCB->uxCriticalNesting > 0U )
\r
8647 BFD08164 8030FC5C LW V0, -32720(GP)
\r
8648 BFD08168 692F LW V0, 60(V0)
\r
8649 BFD0816A 001D40E2 BEQZC V0, 0xBFD081A8
\r
8651 3603: ( pxCurrentTCB->uxCriticalNesting )--;
\r
8652 BFD0816E 8030FC5C LW V0, -32720(GP)
\r
8653 BFD08172 69AF LW V1, 60(V0)
\r
8654 BFD08174 6DBE ADDIU V1, V1, -1
\r
8655 BFD08176 E9AF SW V1, 60(V0)
\r
8657 3605: if( pxCurrentTCB->uxCriticalNesting == 0U )
\r
8658 BFD08178 8030FC5C LW V0, -32720(GP)
\r
8659 BFD0817C 692F LW V0, 60(V0)
\r
8660 BFD0817E 001340A2 BNEZC V0, 0xBFD081A8
\r
8662 3607: portENABLE_INTERRUPTS();
\r
8663 BFD08182 4E3677E8 JALS ulPortGetCP0Status
\r
8664 BFD08184 4E36 ADDIU S1, S1, -5
\r
8666 BFD08188 0010F85E SW V0, 16(S8)
\r
8667 BFD0818C 0010FC7E LW V1, 16(S8)
\r
8668 BFD08190 FFFE41A2 LUI V0, 0xFFFE
\r
8669 BFD08192 5042FFFE LW RA, 20546(S8)
\r
8670 BFD08194 03FF5042 ORI V0, V0, 1023
\r
8671 BFD08198 4493 AND16 V0, V1
\r
8672 BFD0819A 0010F85E SW V0, 16(S8)
\r
8673 BFD0819E 0010FC9E LW A0, 16(S8)
\r
8674 BFD081A2 4E4677E8 JALS vPortSetCP0Status
\r
8675 BFD081A4 4E46 ADDIU S2, S2, 3
\r
8680 3611: mtCOVERAGE_TEST_MARKER();
\r
8685 3616: mtCOVERAGE_TEST_MARKER();
\r
8690 3621: mtCOVERAGE_TEST_MARKER();
\r
8693 BFD081A8 0FBE MOVE SP, S8
\r
8694 BFD081AA 4BE7 LW RA, 28(SP)
\r
8695 BFD081AC 4BC6 LW S8, 24(SP)
\r
8696 BFD081AE 4C11 ADDIU SP, SP, 32
\r
8697 BFD081B0 459F JR16 RA
\r
8700 3625: #endif /* portCRITICAL_NESTING_IN_TCB */
\r
8701 3626: /*-----------------------------------------------------------*/
\r
8703 3628: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
\r
8705 3630: static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
\r
8707 3632: BaseType_t x;
\r
8709 3634: /* Start by copying the entire string. */
\r
8710 3635: strcpy( pcBuffer, pcTaskName );
\r
8712 3637: /* Pad the end of the string with spaces to ensure columns line up when
\r
8713 3638: printed out. */
\r
8714 3639: for( x = strlen( pcBuffer ); x < ( configMAX_TASK_NAME_LEN - 1 ); x++ )
\r
8716 3641: pcBuffer[ x ] = ' ';
\r
8719 3644: /* Terminate. */
\r
8720 3645: pcBuffer[ x ] = 0x00;
\r
8722 3647: /* Return the new end of string. */
\r
8723 3648: return &( pcBuffer[ x ] );
\r
8726 3651: #endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
\r
8727 3652: /*-----------------------------------------------------------*/
\r
8729 3654: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
\r
8731 3656: void vTaskList( char * pcWriteBuffer )
\r
8733 3658: TaskStatus_t *pxTaskStatusArray;
\r
8734 3659: volatile UBaseType_t uxArraySize, x;
\r
8735 3660: char cStatus;
\r
8738 3663: * PLEASE NOTE:
\r
8740 3665: * This function is provided for convenience only, and is used by many
\r
8741 3666: * of the demo applications. Do not consider it to be part of the
\r
8742 3667: * scheduler.
\r
8744 3669: * vTaskList() calls uxTaskGetSystemState(), then formats part of the
\r
8745 3670: * uxTaskGetSystemState() output into a human readable table that
\r
8746 3671: * displays task names, states and stack usage.
\r
8748 3673: * vTaskList() has a dependency on the sprintf() C library function that
\r
8749 3674: * might bloat the code size, use a lot of stack, and provide different
\r
8750 3675: * results on different platforms. An alternative, tiny, third party,
\r
8751 3676: * and limited functionality implementation of sprintf() is provided in
\r
8752 3677: * many of the FreeRTOS/Demo sub-directories in a file called
\r
8753 3678: * printf-stdarg.c (note printf-stdarg.c does not provide a full
\r
8754 3679: * snprintf() implementation!).
\r
8756 3681: * It is recommended that production systems call uxTaskGetSystemState()
\r
8757 3682: * directly to get access to raw stats data, rather than indirectly
\r
8758 3683: * through a call to vTaskList().
\r
8762 3687: /* Make sure the write buffer does not contain a string. */
\r
8763 3688: *pcWriteBuffer = 0x00;
\r
8765 3690: /* Take a snapshot of the number of tasks in case it changes while this
\r
8766 3691: function is executing. */
\r
8767 3692: uxArraySize = uxCurrentNumberOfTasks;
\r
8769 3694: /* Allocate an array index for each task. */
\r
8770 3695: pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
\r
8772 3697: if( pxTaskStatusArray != NULL )
\r
8774 3699: /* Generate the (binary) data. */
\r
8775 3700: uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
\r
8777 3702: /* Create a human readable table from the binary data. */
\r
8778 3703: for( x = 0; x < uxArraySize; x++ )
\r
8780 3705: switch( pxTaskStatusArray[ x ].eCurrentState )
\r
8782 3707: case eReady: cStatus = tskREADY_CHAR;
\r
8785 3710: case eBlocked: cStatus = tskBLOCKED_CHAR;
\r
8788 3713: case eSuspended: cStatus = tskSUSPENDED_CHAR;
\r
8791 3716: case eDeleted: cStatus = tskDELETED_CHAR;
\r
8794 3719: default: /* Should not get here, but it is included
\r
8795 3720: to prevent static checking errors. */
\r
8796 3721: cStatus = 0x00;
\r
8800 3725: /* Write the task name to the string, padding with spaces so it
\r
8801 3726: can be printed in tabular form more easily. */
\r
8802 3727: pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
\r
8804 3729: /* Write the rest of the string. */
\r
8805 3730: sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
\r
8806 3731: pcWriteBuffer += strlen( pcWriteBuffer );
\r
8809 3734: /* Free the array again. */
\r
8810 3735: vPortFree( pxTaskStatusArray );
\r
8814 3739: mtCOVERAGE_TEST_MARKER();
\r
8818 3743: #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
\r
8819 3744: /*----------------------------------------------------------*/
\r
8821 3746: #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
\r
8823 3748: void vTaskGetRunTimeStats( char *pcWriteBuffer )
\r
8825 3750: TaskStatus_t *pxTaskStatusArray;
\r
8826 3751: volatile UBaseType_t uxArraySize, x;
\r
8827 3752: uint32_t ulTotalTime, ulStatsAsPercentage;
\r
8829 3754: #if( configUSE_TRACE_FACILITY != 1 )
\r
8831 3756: #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
\r
8836 3761: * PLEASE NOTE:
\r
8838 3763: * This function is provided for convenience only, and is used by many
\r
8839 3764: * of the demo applications. Do not consider it to be part of the
\r
8840 3765: * scheduler.
\r
8842 3767: * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
\r
8843 3768: * of the uxTaskGetSystemState() output into a human readable table that
\r
8844 3769: * displays the amount of time each task has spent in the Running state
\r
8845 3770: * in both absolute and percentage terms.
\r
8847 3772: * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
\r
8848 3773: * function that might bloat the code size, use a lot of stack, and
\r
8849 3774: * provide different results on different platforms. An alternative,
\r
8850 3775: * tiny, third party, and limited functionality implementation of
\r
8851 3776: * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
\r
8852 3777: * a file called printf-stdarg.c (note printf-stdarg.c does not provide
\r
8853 3778: * a full snprintf() implementation!).
\r
8855 3780: * It is recommended that production systems call uxTaskGetSystemState()
\r
8856 3781: * directly to get access to raw stats data, rather than indirectly
\r
8857 3782: * through a call to vTaskGetRunTimeStats().
\r
8860 3785: /* Make sure the write buffer does not contain a string. */
\r
8861 3786: *pcWriteBuffer = 0x00;
\r
8863 3788: /* Take a snapshot of the number of tasks in case it changes while this
\r
8864 3789: function is executing. */
\r
8865 3790: uxArraySize = uxCurrentNumberOfTasks;
\r
8867 3792: /* Allocate an array index for each task. */
\r
8868 3793: pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
\r
8870 3795: if( pxTaskStatusArray != NULL )
\r
8872 3797: /* Generate the (binary) data. */
\r
8873 3798: uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
\r
8875 3800: /* For percentage calculations. */
\r
8876 3801: ulTotalTime /= 100UL;
\r
8878 3803: /* Avoid divide by zero errors. */
\r
8879 3804: if( ulTotalTime > 0 )
\r
8881 3806: /* Create a human readable table from the binary data. */
\r
8882 3807: for( x = 0; x < uxArraySize; x++ )
\r
8884 3809: /* What percentage of the total run time has the task used?
\r
8885 3810: This will always be rounded down to the nearest integer.
\r
8886 3811: ulTotalRunTimeDiv100 has already been divided by 100. */
\r
8887 3812: ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
\r
8889 3814: /* Write the task name to the string, padding with
\r
8890 3815: spaces so it can be printed in tabular form more
\r
8892 3817: pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
\r
8894 3819: if( ulStatsAsPercentage > 0UL )
\r
8896 3821: #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
\r
8898 3823: sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
\r
8902 3827: /* sizeof( int ) == sizeof( long ) so a smaller
\r
8903 3828: printf() library can be used. */
\r
8904 3829: sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
\r
8910 3835: /* If the percentage is zero here then the task has
\r
8911 3836: consumed less than 1% of the total run time. */
\r
8912 3837: #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
\r
8914 3839: sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
\r
8918 3843: /* sizeof( int ) == sizeof( long ) so a smaller
\r
8919 3844: printf() library can be used. */
\r
8920 3845: sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
\r
8925 3850: pcWriteBuffer += strlen( pcWriteBuffer );
\r
8930 3855: mtCOVERAGE_TEST_MARKER();
\r
8933 3858: /* Free the array again. */
\r
8934 3859: vPortFree( pxTaskStatusArray );
\r
8938 3863: mtCOVERAGE_TEST_MARKER();
\r
8942 3867: #endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
\r
8943 3868: /*-----------------------------------------------------------*/
\r
8945 3870: TickType_t uxTaskResetEventItemValue( void )
\r
8947 BFD0990C 4FF9 ADDIU SP, SP, -16
\r
8948 BFD0990E CBC3 SW S8, 12(SP)
\r
8949 BFD09910 0FDD MOVE S8, SP
\r
8950 3872: TickType_t uxReturn;
\r
8952 3874: uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
\r
8953 BFD09912 8030FC5C LW V0, -32720(GP)
\r
8954 BFD09916 6926 LW V0, 24(V0)
\r
8955 BFD09918 0000F85E SW V0, 0(S8)
\r
8957 3876: /* Reset the event list item to its normal value - so it can be used with
\r
8958 3877: queues and semaphores. */
\r
8959 3878: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
8960 BFD0991C 8030FC5C LW V0, -32720(GP)
\r
8961 BFD09920 8030FC7C LW V1, -32720(GP)
\r
8962 BFD09924 69BB LW V1, 44(V1)
\r
8963 BFD09926 EE05 LI A0, 5
\r
8964 BFD09928 05B9 SUBU V1, A0, V1
\r
8965 BFD0992A E9A6 SW V1, 24(V0)
\r
8967 3880: return uxReturn;
\r
8968 BFD0992C 0000FC5E LW V0, 0(S8)
\r
8970 BFD09930 0FBE MOVE SP, S8
\r
8971 BFD09932 4BC3 LW S8, 12(SP)
\r
8972 BFD09934 4C09 ADDIU SP, SP, 16
\r
8973 BFD09936 459F JR16 RA
\r
8975 3882: /*-----------------------------------------------------------*/
\r
8977 3884: #if ( configUSE_MUTEXES == 1 )
\r
8979 3886: void *pvTaskIncrementMutexHeldCount( void )
\r
8981 BFD099C0 4FB0 ADDIU SP, SP, -8
\r
8982 BFD099C2 CBC1 SW S8, 4(SP)
\r
8983 BFD099C4 0FDD MOVE S8, SP
\r
8984 3888: /* If xSemaphoreCreateMutex() is called before any tasks have been created
\r
8985 3889: then pxCurrentTCB will be NULL. */
\r
8986 3890: if( pxCurrentTCB != NULL )
\r
8987 BFD099C6 8030FC5C LW V0, -32720(GP)
\r
8988 BFD099CA 000740E2 BEQZC V0, 0xBFD099DC
\r
8990 3892: ( pxCurrentTCB->uxMutexesHeld )++;
\r
8991 BFD099CE 8030FC5C LW V0, -32720(GP)
\r
8992 BFD099D2 0044FC62 LW V1, 68(V0)
\r
8993 BFD099D6 6DB0 ADDIU V1, V1, 1
\r
8994 BFD099D8 0044F862 SW V1, 68(V0)
\r
8997 3895: return pxCurrentTCB;
\r
8998 BFD099DC 8030FC5C LW V0, -32720(GP)
\r
9000 BFD099E0 0FBE MOVE SP, S8
\r
9001 BFD099E2 4BC1 LW S8, 4(SP)
\r
9002 BFD099E4 4C05 ADDIU SP, SP, 8
\r
9003 BFD099E6 459F JR16 RA
\r
9006 3898: #endif /* configUSE_MUTEXES */
\r
9007 3899: /*-----------------------------------------------------------*/
\r
9009 3901: #if( configUSE_TASK_NOTIFICATIONS == 1 )
\r
9011 3903: uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
\r
9013 BFD039AC 4FED ADDIU SP, SP, -40
\r
9014 BFD039AE CBE9 SW RA, 36(SP)
\r
9015 BFD039B0 CBC8 SW S8, 32(SP)
\r
9016 BFD039B2 0FDD MOVE S8, SP
\r
9017 BFD039B4 0028F89E SW A0, 40(S8)
\r
9018 BFD039B8 002CF8BE SW A1, 44(S8)
\r
9019 3905: TickType_t xTimeToWake;
\r
9020 3906: uint32_t ulReturn;
\r
9022 3908: taskENTER_CRITICAL();
\r
9023 BFD039BC 33B877E8 JALS vTaskEnterCritical
\r
9024 BFD039BE 0C0033B8 ADDIU SP, T8, 3072
\r
9027 3910: /* Only block if the notification count is not already non-zero. */
\r
9028 3911: if( pxCurrentTCB->ulNotifiedValue == 0UL )
\r
9029 BFD039C2 8030FC5C LW V0, -32720(GP)
\r
9030 BFD039C6 0048FC42 LW V0, 72(V0)
\r
9031 BFD039CA 004D40A2 BNEZC V0, 0xBFD03A68
\r
9033 3913: /* Mark this task as waiting for a notification. */
\r
9034 3914: pxCurrentTCB->eNotifyState = eWaitingNotification;
\r
9035 BFD039CE 8030FC5C LW V0, -32720(GP)
\r
9036 BFD039D2 ED81 LI V1, 1
\r
9037 BFD039D4 004CF862 SW V1, 76(V0)
\r
9039 3916: if( xTicksToWait > ( TickType_t ) 0 )
\r
9040 BFD039D8 002CFC5E LW V0, 44(S8)
\r
9041 BFD039DC 004440E2 BEQZC V0, 0xBFD03A68
\r
9043 3918: /* The task is going to block. First it must be removed
\r
9044 3919: from the ready list. */
\r
9045 3920: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
9046 BFD039E0 8030FC5C LW V0, -32720(GP)
\r
9047 BFD039E4 6D22 ADDIU V0, V0, 4
\r
9048 BFD039E6 0C82 MOVE A0, V0
\r
9049 BFD039E8 00C877E8 JALS uxListRemove
\r
9050 BFD039EA 0C0000C8 SLL A2, T0, 1
\r
9052 BFD039EE 000C40A2 BNEZC V0, 0xBFD03A0A
\r
9054 3922: /* The current task must be in a ready list, so there is
\r
9055 3923: no need to check, and the port reset macro can be called
\r
9056 3924: directly. */
\r
9057 3925: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
\r
9058 BFD039F2 8030FC5C LW V0, -32720(GP)
\r
9059 BFD039F6 692B LW V0, 44(V0)
\r
9060 BFD039F8 ED81 LI V1, 1
\r
9061 BFD039FA 10100062 SLLV V0, V0, V1
\r
9062 BFD039FC 441A1010 ADDI ZERO, S0, 17434
\r
9063 BFD039FE 441A NOT16 V1, V0
\r
9064 BFD03A00 8040FC5C LW V0, -32704(GP)
\r
9065 BFD03A04 4493 AND16 V0, V1
\r
9066 BFD03A06 8040F85C SW V0, -32704(GP)
\r
9070 3929: mtCOVERAGE_TEST_MARKER();
\r
9073 3932: #if ( INCLUDE_vTaskSuspend == 1 )
\r
9075 3934: if( xTicksToWait == portMAX_DELAY )
\r
9076 BFD03A0A 002CFC7E LW V1, 44(S8)
\r
9077 BFD03A0E ED7F LI V0, -1
\r
9078 BFD03A10 000EB443 BNE V1, V0, 0xBFD03A30
\r
9079 BFD03A12 0C00000E SLL ZERO, T6, 1
\r
9082 3936: /* Add the task to the suspended task list instead
\r
9083 3937: of a delayed task list to ensure the task is not
\r
9084 3938: woken by a timing event. It will block
\r
9085 3939: indefinitely. */
\r
9086 3940: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );
\r
9087 BFD03A16 8030FC5C LW V0, -32720(GP)
\r
9088 BFD03A1A 6D22 ADDIU V0, V0, 4
\r
9089 BFD03A1C BFD241A3 LUI V1, 0xBFD2
\r
9090 BFD03A1E 3083BFD2 LDC1 F30, 12419(S2)
\r
9091 BFD03A20 80E43083 ADDIU A0, V1, -32540
\r
9092 BFD03A24 0CA2 MOVE A1, V0
\r
9093 BFD03A26 3E4A77E8 JALS vListInsertEnd
\r
9094 BFD03A28 0C003E4A LH S2, 3072(T2)
\r
9096 BFD03A2C CC0D B 0xBFD03A48
\r
9101 3944: /* Calculate the time at which the task should be
\r
9102 3945: woken if no notification events occur. This may
\r
9103 3946: overflow but this doesn't matter, the scheduler will
\r
9104 3947: handle it. */
\r
9105 3948: xTimeToWake = xTickCount + xTicksToWait;
\r
9106 BFD03A30 803CFC7C LW V1, -32708(GP)
\r
9107 BFD03A34 002CFC5E LW V0, 44(S8)
\r
9108 BFD03A38 0526 ADDU V0, V1, V0
\r
9109 BFD03A3A 0010F85E SW V0, 16(S8)
\r
9110 3949: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
9111 BFD03A3E 0010FC9E LW A0, 16(S8)
\r
9112 BFD03A42 373477E8 JALS prvAddCurrentTaskToDelayedList
\r
9113 BFD03A44 0C003734 LHU T9, 3072(S4)
\r
9117 3952: #else /* INCLUDE_vTaskSuspend */
\r
9119 3954: /* Calculate the time at which the task should be
\r
9120 3955: woken if the event does not occur. This may
\r
9121 3956: overflow but this doesn't matter, the scheduler will
\r
9122 3957: handle it. */
\r
9123 3958: xTimeToWake = xTickCount + xTicksToWait;
\r
9124 3959: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
9126 3961: #endif /* INCLUDE_vTaskSuspend */
\r
9128 3963: /* All ports are written to allow a yield in a critical
\r
9129 3964: section (some will yield immediately, others wait until the
\r
9130 3965: critical section exits) - but it is not something that
\r
9131 3966: application code should ever do. */
\r
9132 3967: portYIELD_WITHIN_API();
\r
9133 BFD03A48 4E5677E8 JALS ulPortGetCP0Cause
\r
9134 BFD03A4A 4E56 ADDIU S2, S2, -5
\r
9136 BFD03A4E 0014F85E SW V0, 20(S8)
\r
9137 BFD03A52 0014FC5E LW V0, 20(S8)
\r
9138 BFD03A56 01005042 ORI V0, V0, 256
\r
9139 BFD03A5A 0014F85E SW V0, 20(S8)
\r
9140 BFD03A5E 0014FC9E LW A0, 20(S8)
\r
9141 BFD03A62 4E6677E8 JALS vPortSetCP0Cause
\r
9142 BFD03A64 4E66 ADDIU S3, S3, 3
\r
9147 3971: mtCOVERAGE_TEST_MARKER();
\r
9152 3976: mtCOVERAGE_TEST_MARKER();
\r
9155 3979: taskEXIT_CRITICAL();
\r
9156 BFD03A68 40AA77E8 JALS vTaskExitCritical
\r
9157 BFD03A6A 0C0040AA BNEZC T2, 0xBFD0526E
\r
9160 3981: taskENTER_CRITICAL();
\r
9161 BFD03A6E 33B877E8 JALS vTaskEnterCritical
\r
9162 BFD03A70 0C0033B8 ADDIU SP, T8, 3072
\r
9165 3983: ulReturn = pxCurrentTCB->ulNotifiedValue;
\r
9166 BFD03A74 8030FC5C LW V0, -32720(GP)
\r
9167 BFD03A78 0048FC42 LW V0, 72(V0)
\r
9168 BFD03A7C 0018F85E SW V0, 24(S8)
\r
9170 3985: if( ulReturn != 0UL )
\r
9171 BFD03A80 0018FC5E LW V0, 24(S8)
\r
9172 BFD03A84 001140E2 BEQZC V0, 0xBFD03AAA
\r
9174 3987: if( xClearCountOnExit != pdFALSE )
\r
9175 BFD03A88 0028FC5E LW V0, 40(S8)
\r
9176 BFD03A8C 000640E2 BEQZC V0, 0xBFD03A9C
\r
9178 3989: pxCurrentTCB->ulNotifiedValue = 0UL;
\r
9179 BFD03A90 8030FC5C LW V0, -32720(GP)
\r
9180 BFD03A94 0048F802 SW ZERO, 72(V0)
\r
9181 BFD03A98 CC08 B 0xBFD03AAA
\r
9186 3993: ( pxCurrentTCB->ulNotifiedValue )--;
\r
9187 BFD03A9C 8030FC5C LW V0, -32720(GP)
\r
9188 BFD03AA0 0048FC62 LW V1, 72(V0)
\r
9189 BFD03AA4 6DBE ADDIU V1, V1, -1
\r
9190 BFD03AA6 0048F862 SW V1, 72(V0)
\r
9195 3998: mtCOVERAGE_TEST_MARKER();
\r
9198 4001: pxCurrentTCB->eNotifyState = eNotWaitingNotification;
\r
9199 BFD03AAA 8030FC5C LW V0, -32720(GP)
\r
9200 BFD03AAE 004CF802 SW ZERO, 76(V0)
\r
9202 4003: taskEXIT_CRITICAL();
\r
9203 BFD03AB2 40AA77E8 JALS vTaskExitCritical
\r
9204 BFD03AB4 0C0040AA BNEZC T2, 0xBFD052B8
\r
9207 4005: return ulReturn;
\r
9208 BFD03AB8 0018FC5E LW V0, 24(S8)
\r
9210 BFD03ABC 0FBE MOVE SP, S8
\r
9211 BFD03ABE 4BE9 LW RA, 36(SP)
\r
9212 BFD03AC0 4BC8 LW S8, 32(SP)
\r
9213 BFD03AC2 4C15 ADDIU SP, SP, 40
\r
9214 BFD03AC4 459F JR16 RA
\r
9217 4008: #endif /* configUSE_TASK_NOTIFICATIONS */
\r
9218 4009: /*-----------------------------------------------------------*/
\r
9220 4011: #if( configUSE_TASK_NOTIFICATIONS == 1 )
\r
9222 4013: BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
\r
9224 BFD02C6C 4FED ADDIU SP, SP, -40
\r
9225 BFD02C6E CBE9 SW RA, 36(SP)
\r
9226 BFD02C70 CBC8 SW S8, 32(SP)
\r
9227 BFD02C72 0FDD MOVE S8, SP
\r
9228 BFD02C74 0028F89E SW A0, 40(S8)
\r
9229 BFD02C78 002CF8BE SW A1, 44(S8)
\r
9230 BFD02C7C 0030F8DE SW A2, 48(S8)
\r
9231 BFD02C80 0034F8FE SW A3, 52(S8)
\r
9232 4015: TickType_t xTimeToWake;
\r
9233 4016: BaseType_t xReturn;
\r
9235 4018: taskENTER_CRITICAL();
\r
9236 BFD02C84 33B877E8 JALS vTaskEnterCritical
\r
9237 BFD02C86 0C0033B8 ADDIU SP, T8, 3072
\r
9240 4020: /* Only block if a notification is not already pending. */
\r
9241 4021: if( pxCurrentTCB->eNotifyState != eNotified )
\r
9242 BFD02C8A 8030FC5C LW V0, -32720(GP)
\r
9243 BFD02C8E 004CFC62 LW V1, 76(V0)
\r
9244 BFD02C92 ED02 LI V0, 2
\r
9245 BFD02C94 00589443 BEQ V1, V0, 0xBFD02D48
\r
9246 BFD02C96 0C000058 SLL V0, T8, 1
\r
9249 4023: /* Clear bits in the task's notification value as bits may get
\r
9250 4024: set by the notifying task or interrupt. This can be used to
\r
9251 4025: clear the value to zero. */
\r
9252 4026: pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
\r
9253 BFD02C9A 8030FC5C LW V0, -32720(GP)
\r
9254 BFD02C9E 0048FC82 LW A0, 72(V0)
\r
9255 BFD02CA2 0028FC7E LW V1, 40(S8)
\r
9256 BFD02CA6 441B NOT16 V1, V1
\r
9257 BFD02CA8 449C AND16 V1, A0
\r
9258 BFD02CAA 0048F862 SW V1, 72(V0)
\r
9260 4028: /* Mark this task as waiting for a notification. */
\r
9261 4029: pxCurrentTCB->eNotifyState = eWaitingNotification;
\r
9262 BFD02CAE 8030FC5C LW V0, -32720(GP)
\r
9263 BFD02CB2 ED81 LI V1, 1
\r
9264 BFD02CB4 004CF862 SW V1, 76(V0)
\r
9266 4031: if( xTicksToWait > ( TickType_t ) 0 )
\r
9267 BFD02CB8 0034FC5E LW V0, 52(S8)
\r
9268 BFD02CBC 004440E2 BEQZC V0, 0xBFD02D48
\r
9270 4033: /* The task is going to block. First it must be removed
\r
9271 4034: from the ready list. */
\r
9272 4035: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
\r
9273 BFD02CC0 8030FC5C LW V0, -32720(GP)
\r
9274 BFD02CC4 6D22 ADDIU V0, V0, 4
\r
9275 BFD02CC6 0C82 MOVE A0, V0
\r
9276 BFD02CC8 00C877E8 JALS uxListRemove
\r
9277 BFD02CCA 0C0000C8 SLL A2, T0, 1
\r
9279 BFD02CCE 000C40A2 BNEZC V0, 0xBFD02CEA
\r
9281 4037: /* The current task must be in a ready list, so there is
\r
9282 4038: no need to check, and the port reset macro can be called
\r
9283 4039: directly. */
\r
9284 4040: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
\r
9285 BFD02CD2 8030FC5C LW V0, -32720(GP)
\r
9286 BFD02CD6 692B LW V0, 44(V0)
\r
9287 BFD02CD8 ED81 LI V1, 1
\r
9288 BFD02CDA 10100062 SLLV V0, V0, V1
\r
9289 BFD02CDC 441A1010 ADDI ZERO, S0, 17434
\r
9290 BFD02CDE 441A NOT16 V1, V0
\r
9291 BFD02CE0 8040FC5C LW V0, -32704(GP)
\r
9292 BFD02CE4 4493 AND16 V0, V1
\r
9293 BFD02CE6 8040F85C SW V0, -32704(GP)
\r
9297 4044: mtCOVERAGE_TEST_MARKER();
\r
9300 4047: #if ( INCLUDE_vTaskSuspend == 1 )
\r
9302 4049: if( xTicksToWait == portMAX_DELAY )
\r
9303 BFD02CEA 0034FC7E LW V1, 52(S8)
\r
9304 BFD02CEE ED7F LI V0, -1
\r
9305 BFD02CF0 000EB443 BNE V1, V0, 0xBFD02D10
\r
9306 BFD02CF2 0C00000E SLL ZERO, T6, 1
\r
9309 4051: /* Add the task to the suspended task list instead
\r
9310 4052: of a delayed task list to ensure the task is not
\r
9311 4053: woken by a timing event. It will block
\r
9312 4054: indefinitely. */
\r
9313 4055: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );
\r
9314 BFD02CF6 8030FC5C LW V0, -32720(GP)
\r
9315 BFD02CFA 6D22 ADDIU V0, V0, 4
\r
9316 BFD02CFC BFD241A3 LUI V1, 0xBFD2
\r
9317 BFD02CFE 3083BFD2 LDC1 F30, 12419(S2)
\r
9318 BFD02D00 80E43083 ADDIU A0, V1, -32540
\r
9319 BFD02D04 0CA2 MOVE A1, V0
\r
9320 BFD02D06 3E4A77E8 JALS vListInsertEnd
\r
9321 BFD02D08 0C003E4A LH S2, 3072(T2)
\r
9323 BFD02D0C CC0D B 0xBFD02D28
\r
9328 4059: /* Calculate the time at which the task should be
\r
9329 4060: woken if no notification events occur. This may
\r
9330 4061: overflow but this doesn't matter, the scheduler will
\r
9331 4062: handle it. */
\r
9332 4063: xTimeToWake = xTickCount + xTicksToWait;
\r
9333 BFD02D10 803CFC7C LW V1, -32708(GP)
\r
9334 BFD02D14 0034FC5E LW V0, 52(S8)
\r
9335 BFD02D18 0526 ADDU V0, V1, V0
\r
9336 BFD02D1A 0014F85E SW V0, 20(S8)
\r
9337 4064: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
9338 BFD02D1E 0014FC9E LW A0, 20(S8)
\r
9339 BFD02D22 373477E8 JALS prvAddCurrentTaskToDelayedList
\r
9340 BFD02D24 0C003734 LHU T9, 3072(S4)
\r
9344 4067: #else /* INCLUDE_vTaskSuspend */
\r
9346 4069: /* Calculate the time at which the task should be
\r
9347 4070: woken if the event does not occur. This may
\r
9348 4071: overflow but this doesn't matter, the scheduler will
\r
9349 4072: handle it. */
\r
9350 4073: xTimeToWake = xTickCount + xTicksToWait;
\r
9351 4074: prvAddCurrentTaskToDelayedList( xTimeToWake );
\r
9353 4076: #endif /* INCLUDE_vTaskSuspend */
\r
9355 4078: /* All ports are written to allow a yield in a critical
\r
9356 4079: section (some will yield immediately, others wait until the
\r
9357 4080: critical section exits) - but it is not something that
\r
9358 4081: application code should ever do. */
\r
9359 4082: portYIELD_WITHIN_API();
\r
9360 BFD02D28 4E5677E8 JALS ulPortGetCP0Cause
\r
9361 BFD02D2A 4E56 ADDIU S2, S2, -5
\r
9363 BFD02D2E 0018F85E SW V0, 24(S8)
\r
9364 BFD02D32 0018FC5E LW V0, 24(S8)
\r
9365 BFD02D36 01005042 ORI V0, V0, 256
\r
9366 BFD02D3A 0018F85E SW V0, 24(S8)
\r
9367 BFD02D3E 0018FC9E LW A0, 24(S8)
\r
9368 BFD02D42 4E6677E8 JALS vPortSetCP0Cause
\r
9369 BFD02D44 4E66 ADDIU S3, S3, 3
\r
9374 4086: mtCOVERAGE_TEST_MARKER();
\r
9379 4091: mtCOVERAGE_TEST_MARKER();
\r
9382 4094: taskEXIT_CRITICAL();
\r
9383 BFD02D48 40AA77E8 JALS vTaskExitCritical
\r
9384 BFD02D4A 0C0040AA BNEZC T2, 0xBFD0454E
\r
9387 4096: taskENTER_CRITICAL();
\r
9388 BFD02D4E 33B877E8 JALS vTaskEnterCritical
\r
9389 BFD02D50 0C0033B8 ADDIU SP, T8, 3072
\r
9392 4098: if( pulNotificationValue != NULL )
\r
9393 BFD02D54 0030FC5E LW V0, 48(S8)
\r
9394 BFD02D58 000740E2 BEQZC V0, 0xBFD02D6A
\r
9396 4100: /* Output the current notification value, which may or may not
\r
9397 4101: have changed. */
\r
9398 4102: *pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
\r
9399 BFD02D5C 8030FC5C LW V0, -32720(GP)
\r
9400 BFD02D60 0048FC62 LW V1, 72(V0)
\r
9401 BFD02D64 0030FC5E LW V0, 48(S8)
\r
9402 BFD02D68 E9A0 SW V1, 0(V0)
\r
9405 4105: /* If eNotifyValue is set then either the task never entered the
\r
9406 4106: blocked state (because a notification was already pending) or the
\r
9407 4107: task unblocked because of a notification. Otherwise the task
\r
9408 4108: unblocked because of a timeout. */
\r
9409 4109: if( pxCurrentTCB->eNotifyState == eWaitingNotification )
\r
9410 BFD02D6A 8030FC5C LW V0, -32720(GP)
\r
9411 BFD02D6E 004CFC62 LW V1, 76(V0)
\r
9412 BFD02D72 ED01 LI V0, 1
\r
9413 BFD02D74 0005B443 BNE V1, V0, 0xBFD02D82
\r
9414 BFD02D76 0C000005 SLL ZERO, A1, 1
\r
9417 4111: /* A notification was not received. */
\r
9418 4112: xReturn = pdFALSE;
\r
9419 BFD02D7A 0010F81E SW ZERO, 16(S8)
\r
9420 BFD02D7E CC0E B 0xBFD02D9C
\r
9425 4116: /* A notification was already pending or a notification was
\r
9426 4117: received while the task was waiting. */
\r
9427 4118: pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
\r
9428 BFD02D82 8030FC5C LW V0, -32720(GP)
\r
9429 BFD02D86 0048FC82 LW A0, 72(V0)
\r
9430 BFD02D8A 002CFC7E LW V1, 44(S8)
\r
9431 BFD02D8E 441B NOT16 V1, V1
\r
9432 BFD02D90 449C AND16 V1, A0
\r
9433 BFD02D92 0048F862 SW V1, 72(V0)
\r
9434 4119: xReturn = pdTRUE;
\r
9435 BFD02D96 ED01 LI V0, 1
\r
9436 BFD02D98 0010F85E SW V0, 16(S8)
\r
9439 4122: pxCurrentTCB->eNotifyState = eNotWaitingNotification;
\r
9440 BFD02D9C 8030FC5C LW V0, -32720(GP)
\r
9441 BFD02DA0 004CF802 SW ZERO, 76(V0)
\r
9443 4124: taskEXIT_CRITICAL();
\r
9444 BFD02DA4 40AA77E8 JALS vTaskExitCritical
\r
9445 BFD02DA6 0C0040AA BNEZC T2, 0xBFD045AA
\r
9448 4126: return xReturn;
\r
9449 BFD02DAA 0010FC5E LW V0, 16(S8)
\r
9451 BFD02DAE 0FBE MOVE SP, S8
\r
9452 BFD02DB0 4BE9 LW RA, 36(SP)
\r
9453 BFD02DB2 4BC8 LW S8, 32(SP)
\r
9454 BFD02DB4 4C15 ADDIU SP, SP, 40
\r
9455 BFD02DB6 459F JR16 RA
\r
9458 4129: #endif /* configUSE_TASK_NOTIFICATIONS */
\r
9459 4130: /*-----------------------------------------------------------*/
\r
9461 4132: #if( configUSE_TASK_NOTIFICATIONS == 1 )
\r
9463 4134: BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
\r
9465 BFD01CE8 4FED ADDIU SP, SP, -40
\r
9466 BFD01CEA CBE9 SW RA, 36(SP)
\r
9467 BFD01CEC CBC8 SW S8, 32(SP)
\r
9468 BFD01CEE 0FDD MOVE S8, SP
\r
9469 BFD01CF0 0028F89E SW A0, 40(S8)
\r
9470 BFD01CF4 002CF8BE SW A1, 44(S8)
\r
9471 BFD01CF8 0030F8DE SW A2, 48(S8)
\r
9472 BFD01CFC 0034F8FE SW A3, 52(S8)
\r
9473 4136: TCB_t * pxTCB;
\r
9474 4137: eNotifyValue eOriginalNotifyState;
\r
9475 4138: BaseType_t xReturn = pdPASS;
\r
9476 BFD01D00 ED01 LI V0, 1
\r
9477 BFD01D02 0010F85E SW V0, 16(S8)
\r
9479 4140: configASSERT( xTaskToNotify );
\r
9480 BFD01D06 0028FC5E LW V0, 40(S8)
\r
9481 BFD01D0A 000940A2 BNEZC V0, 0xBFD01D20
\r
9482 BFD01D0E BFD141A2 LUI V0, 0xBFD1
\r
9483 BFD01D10 3082BFD1 LDC1 F30, 12418(S1)
\r
9484 BFD01D12 98103082 ADDIU A0, V0, -26608
\r
9485 BFD01D14 30A09810 SWC1 F0, 12448(S0)
\r
9486 BFD01D16 102C30A0 ADDIU A1, ZERO, 4140
\r
9487 BFD01D18 77E8102C ADDI AT, T4, 30696
\r
9488 BFD01D1A 4B7E77E8 JALS vAssertCalled
\r
9489 BFD01D1C 4B7E LW K1, 120(SP)
\r
9491 4141: pxTCB = ( TCB_t * ) xTaskToNotify;
\r
9492 BFD01D20 0028FC5E LW V0, 40(S8)
\r
9493 BFD01D24 0014F85E SW V0, 20(S8)
\r
9495 4143: taskENTER_CRITICAL();
\r
9496 BFD01D28 33B877E8 JALS vTaskEnterCritical
\r
9497 BFD01D2A 0C0033B8 ADDIU SP, T8, 3072
\r
9500 4145: if( pulPreviousNotificationValue != NULL )
\r
9501 BFD01D2E 0034FC5E LW V0, 52(S8)
\r
9502 BFD01D32 000740E2 BEQZC V0, 0xBFD01D44
\r
9504 4147: *pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
\r
9505 BFD01D36 0014FC5E LW V0, 20(S8)
\r
9506 BFD01D3A 0048FC62 LW V1, 72(V0)
\r
9507 BFD01D3E 0034FC5E LW V0, 52(S8)
\r
9508 BFD01D42 E9A0 SW V1, 0(V0)
\r
9511 4150: eOriginalNotifyState = pxTCB->eNotifyState;
\r
9512 BFD01D44 0014FC5E LW V0, 20(S8)
\r
9513 BFD01D48 004CFC42 LW V0, 76(V0)
\r
9514 BFD01D4C 0018F85E SW V0, 24(S8)
\r
9516 4152: pxTCB->eNotifyState = eNotified;
\r
9517 BFD01D50 0014FC5E LW V0, 20(S8)
\r
9518 BFD01D54 ED82 LI V1, 2
\r
9519 BFD01D56 004CF862 SW V1, 76(V0)
\r
9521 4154: switch( eAction )
\r
9522 BFD01D5A 0030FC5E LW V0, 48(S8)
\r
9523 BFD01D5E 0005B042 SLTIU V0, V0, 5
\r
9524 BFD01D62 004840E2 BEQZC V0, 0xBFD01DF6
\r
9525 BFD01D66 0030FC5E LW V0, 48(S8)
\r
9526 BFD01D6A 25A4 SLL V1, V0, 2
\r
9527 BFD01D6C BFD041A2 LUI V0, 0xBFD0
\r
9528 BFD01D6E 3042BFD0 LDC1 F30, 12354(S0)
\r
9529 BFD01D70 1D7C3042 ADDIU V0, V0, 7548
\r
9530 BFD01D72 05261D7C LB T3, 1318(GP)
\r
9531 BFD01D74 0526 ADDU V0, V1, V0
\r
9532 BFD01D76 6920 LW V0, 0(V0)
\r
9533 BFD01D78 45A2 JRC V0
\r
9535 BFD01D7C BFD01DF5 LB T7, -16432(S5)
\r
9536 BFD01D7E 1D91BFD0 LDC1 F30, 7569(S0)
\r
9537 BFD01D80 BFD01D91 LB T4, -16432(S1)
\r
9538 BFD01D82 1DABBFD0 LDC1 F30, 7595(S0)
\r
9539 BFD01D84 BFD01DAB LB T5, -16432(T3)
\r
9540 BFD01D86 1DC1BFD0 LDC1 F30, 7617(S0)
\r
9541 BFD01D88 BFD01DC1 LB T6, -16432(AT)
\r
9542 BFD01D8A 1DD1BFD0 LDC1 F30, 7633(S0)
\r
9543 BFD01D8C BFD01DD1 LB T6, -16432(S1)
\r
9544 BFD01D8E FC5EBFD0 LDC1 F30, -930(S0)
\r
9546 4156: case eSetBits :
\r
9547 4157: pxTCB->ulNotifiedValue |= ulValue;
\r
9548 BFD01D90 0014FC5E LW V0, 20(S8)
\r
9549 BFD01D94 0048FC62 LW V1, 72(V0)
\r
9550 BFD01D98 002CFC5E LW V0, 44(S8)
\r
9551 BFD01D9C 44DA OR16 V1, V0
\r
9552 BFD01D9E 0014FC5E LW V0, 20(S8)
\r
9553 BFD01DA2 0048F862 SW V1, 72(V0)
\r
9555 BFD01DA6 CC27 B 0xBFD01DF6
\r
9558 4160: case eIncrement :
\r
9559 4161: ( pxTCB->ulNotifiedValue )++;
\r
9560 BFD01DAA 0014FC5E LW V0, 20(S8)
\r
9561 BFD01DAE 0048FC42 LW V0, 72(V0)
\r
9562 BFD01DB2 6DA0 ADDIU V1, V0, 1
\r
9563 BFD01DB4 0014FC5E LW V0, 20(S8)
\r
9564 BFD01DB8 0048F862 SW V1, 72(V0)
\r
9566 BFD01DBC CC1C B 0xBFD01DF6
\r
9569 4164: case eSetValueWithOverwrite :
\r
9570 4165: pxTCB->ulNotifiedValue = ulValue;
\r
9571 BFD01DC0 0014FC5E LW V0, 20(S8)
\r
9572 BFD01DC4 002CFC7E LW V1, 44(S8)
\r
9573 BFD01DC8 0048F862 SW V1, 72(V0)
\r
9575 BFD01DCC CC14 B 0xBFD01DF6
\r
9578 4168: case eSetValueWithoutOverwrite :
\r
9579 4169: if( eOriginalNotifyState != eNotified )
\r
9580 BFD01DD0 0018FC7E LW V1, 24(S8)
\r
9581 BFD01DD4 ED02 LI V0, 2
\r
9582 BFD01DD6 00099443 BEQ V1, V0, 0xBFD01DEC
\r
9583 BFD01DD8 0C000009 SLL ZERO, T1, 1
\r
9586 4171: pxTCB->ulNotifiedValue = ulValue;
\r
9587 BFD01DDC 0014FC5E LW V0, 20(S8)
\r
9588 BFD01DE0 002CFC7E LW V1, 44(S8)
\r
9589 BFD01DE4 0048F862 SW V1, 72(V0)
\r
9593 4175: /* The value could not be written to the task. */
\r
9594 4176: xReturn = pdFAIL;
\r
9595 BFD01DEC 0010F81E SW ZERO, 16(S8)
\r
9598 BFD01DE8 CC06 B 0xBFD01DF6
\r
9600 BFD01DF0 CC02 B 0xBFD01DF6
\r
9603 4180: case eNoAction:
\r
9604 4181: /* The task is being notified without its notify value being
\r
9611 4187: /* If the task is in the blocked state specifically to wait for a
\r
9612 4188: notification then unblock it now. */
\r
9613 4189: if( eOriginalNotifyState == eWaitingNotification )
\r
9614 BFD01DF6 0018FC7E LW V1, 24(S8)
\r
9615 BFD01DFA ED01 LI V0, 1
\r
9616 BFD01DFC 004EB443 BNE V1, V0, 0xBFD01E9C
\r
9617 BFD01DFE 0C00004E SLL V0, T6, 1
\r
9620 4191: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
9621 BFD01E02 0014FC5E LW V0, 20(S8)
\r
9622 BFD01E06 6D22 ADDIU V0, V0, 4
\r
9623 BFD01E08 0C82 MOVE A0, V0
\r
9624 BFD01E0A 00C877E8 JALS uxListRemove
\r
9625 BFD01E0C 0C0000C8 SLL A2, T0, 1
\r
9627 4192: prvAddTaskToReadyList( pxTCB );
\r
9628 BFD01E10 0014FC5E LW V0, 20(S8)
\r
9629 BFD01E14 692B LW V0, 44(V0)
\r
9630 BFD01E16 ED81 LI V1, 1
\r
9631 BFD01E18 18100062 SLLV V1, V0, V1
\r
9632 BFD01E1A FC5C1810 SB ZERO, -932(S0)
\r
9633 BFD01E1C 8040FC5C LW V0, -32704(GP)
\r
9634 BFD01E20 44D3 OR16 V0, V1
\r
9635 BFD01E22 8040F85C SW V0, -32704(GP)
\r
9636 BFD01E26 0014FC5E LW V0, 20(S8)
\r
9637 BFD01E2A 692B LW V0, 44(V0)
\r
9638 BFD01E2C 2524 SLL V0, V0, 2
\r
9639 BFD01E2E 25A4 SLL V1, V0, 2
\r
9640 BFD01E30 05B4 ADDU V1, V0, V1
\r
9641 BFD01E32 BFD241A2 LUI V0, 0xBFD2
\r
9642 BFD01E34 3042BFD2 LDC1 F30, 12354(S2)
\r
9643 BFD01E36 806C3042 ADDIU V0, V0, -32660
\r
9644 BFD01E3A 05A6 ADDU V1, V1, V0
\r
9645 BFD01E3C 0014FC5E LW V0, 20(S8)
\r
9646 BFD01E40 6D22 ADDIU V0, V0, 4
\r
9647 BFD01E42 0C83 MOVE A0, V1
\r
9648 BFD01E44 0CA2 MOVE A1, V0
\r
9649 BFD01E46 3E4A77E8 JALS vListInsertEnd
\r
9650 BFD01E48 0C003E4A LH S2, 3072(T2)
\r
9653 4194: /* The task should not have been on an event list. */
\r
9654 4195: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
\r
9655 BFD01E4C 0014FC5E LW V0, 20(S8)
\r
9656 BFD01E50 692A LW V0, 40(V0)
\r
9657 BFD01E52 000940E2 BEQZC V0, 0xBFD01E68
\r
9658 BFD01E56 BFD141A2 LUI V0, 0xBFD1
\r
9659 BFD01E58 3082BFD1 LDC1 F30, 12418(S1)
\r
9660 BFD01E5A 98103082 ADDIU A0, V0, -26608
\r
9661 BFD01E5C 30A09810 SWC1 F0, 12448(S0)
\r
9662 BFD01E5E 106330A0 ADDIU A1, ZERO, 4195
\r
9663 BFD01E60 77E81063 ADDI V1, V1, 30696
\r
9664 BFD01E62 4B7E77E8 JALS vAssertCalled
\r
9665 BFD01E64 4B7E LW K1, 120(SP)
\r
9668 4197: #if( configUSE_TICKLESS_IDLE != 0 )
\r
9670 4199: /* If a task is blocked waiting for a notification then
\r
9671 4200: xNextTaskUnblockTime might be set to the blocked task's time
\r
9672 4201: out time. If the task is unblocked for a reason other than
\r
9673 4202: a timeout xNextTaskUnblockTime is normally left unchanged,
\r
9674 4203: because it will automatically get reset to a new value when
\r
9675 4204: the tick count equals xNextTaskUnblockTime. However if
\r
9676 4205: tickless idling is used it might be more important to enter
\r
9677 4206: sleep mode at the earliest possible time - so reset
\r
9678 4207: xNextTaskUnblockTime here to ensure it is updated at the
\r
9679 4208: earliest possible time. */
\r
9680 4209: prvResetNextTaskUnblockTime();
\r
9684 4213: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
\r
9685 BFD01E68 0014FC5E LW V0, 20(S8)
\r
9686 BFD01E6C 69AB LW V1, 44(V0)
\r
9687 BFD01E6E 8030FC5C LW V0, -32720(GP)
\r
9688 BFD01E72 692B LW V0, 44(V0)
\r
9689 BFD01E74 13900062 SLTU V0, V0, V1
\r
9690 BFD01E76 40E21390 ADDI GP, S0, 16610
\r
9691 BFD01E78 001040E2 BEQZC V0, 0xBFD01E9C
\r
9693 4215: /* The notified task has a priority above the currently
\r
9694 4216: executing task so a yield is required. */
\r
9695 4217: taskYIELD_IF_USING_PREEMPTION();
\r
9696 BFD01E7C 4E5677E8 JALS ulPortGetCP0Cause
\r
9697 BFD01E7E 4E56 ADDIU S2, S2, -5
\r
9699 BFD01E82 001CF85E SW V0, 28(S8)
\r
9700 BFD01E86 001CFC5E LW V0, 28(S8)
\r
9701 BFD01E8A 01005042 ORI V0, V0, 256
\r
9702 BFD01E8E 001CF85E SW V0, 28(S8)
\r
9703 BFD01E92 001CFC9E LW A0, 28(S8)
\r
9704 BFD01E96 4E6677E8 JALS vPortSetCP0Cause
\r
9705 BFD01E98 4E66 ADDIU S3, S3, 3
\r
9710 4221: mtCOVERAGE_TEST_MARKER();
\r
9715 4226: mtCOVERAGE_TEST_MARKER();
\r
9718 4229: taskEXIT_CRITICAL();
\r
9719 BFD01E9C 40AA77E8 JALS vTaskExitCritical
\r
9720 BFD01E9E 0C0040AA BNEZC T2, 0xBFD036A2
\r
9723 4231: return xReturn;
\r
9724 BFD01EA2 0010FC5E LW V0, 16(S8)
\r
9726 BFD01EA6 0FBE MOVE SP, S8
\r
9727 BFD01EA8 4BE9 LW RA, 36(SP)
\r
9728 BFD01EAA 4BC8 LW S8, 32(SP)
\r
9729 BFD01EAC 4C15 ADDIU SP, SP, 40
\r
9730 BFD01EAE 459F JR16 RA
\r
9733 4234: #endif /* configUSE_TASK_NOTIFICATIONS */
\r
9734 4235: /*-----------------------------------------------------------*/
\r
9736 4237: #if( configUSE_TASK_NOTIFICATIONS == 1 )
\r
9738 4239: BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken )
\r
9740 BFD01EB4 4FED ADDIU SP, SP, -40
\r
9741 BFD01EB6 CBE9 SW RA, 36(SP)
\r
9742 BFD01EB8 CBC8 SW S8, 32(SP)
\r
9743 BFD01EBA 0FDD MOVE S8, SP
\r
9744 BFD01EBC 0028F89E SW A0, 40(S8)
\r
9745 BFD01EC0 002CF8BE SW A1, 44(S8)
\r
9746 BFD01EC4 0030F8DE SW A2, 48(S8)
\r
9747 BFD01EC8 0034F8FE SW A3, 52(S8)
\r
9748 4241: TCB_t * pxTCB;
\r
9749 4242: eNotifyValue eOriginalNotifyState;
\r
9750 4243: BaseType_t xReturn = pdPASS;
\r
9751 BFD01ECC ED01 LI V0, 1
\r
9752 BFD01ECE 0010F85E SW V0, 16(S8)
\r
9753 4244: UBaseType_t uxSavedInterruptStatus;
\r
9755 4246: configASSERT( xTaskToNotify );
\r
9756 BFD01ED2 0028FC5E LW V0, 40(S8)
\r
9757 BFD01ED6 000940A2 BNEZC V0, 0xBFD01EEC
\r
9758 BFD01EDA BFD141A2 LUI V0, 0xBFD1
\r
9759 BFD01EDC 3082BFD1 LDC1 F30, 12418(S1)
\r
9760 BFD01EDE 98103082 ADDIU A0, V0, -26608
\r
9761 BFD01EE0 30A09810 SWC1 F0, 12448(S0)
\r
9762 BFD01EE2 109630A0 ADDIU A1, ZERO, 4246
\r
9763 BFD01EE4 77E81096 ADDI A0, S6, 30696
\r
9764 BFD01EE6 4B7E77E8 JALS vAssertCalled
\r
9765 BFD01EE8 4B7E LW K1, 120(SP)
\r
9768 4248: /* RTOS ports that support interrupt nesting have the concept of a
\r
9769 4249: maximum system call (or maximum API call) interrupt priority.
\r
9770 4250: Interrupts that are above the maximum system call priority are keep
\r
9771 4251: permanently enabled, even when the RTOS kernel is in a critical section,
\r
9772 4252: but cannot make any calls to FreeRTOS API functions. If configASSERT()
\r
9773 4253: is defined in FreeRTOSConfig.h then
\r
9774 4254: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
9775 4255: failure if a FreeRTOS API function is called from an interrupt that has
\r
9776 4256: been assigned a priority above the configured maximum system call
\r
9777 4257: priority. Only FreeRTOS functions that end in FromISR can be called
\r
9778 4258: from interrupts that have been assigned a priority at or (logically)
\r
9779 4259: below the maximum system call interrupt priority. FreeRTOS maintains a
\r
9780 4260: separate interrupt safe API to ensure interrupt entry is as fast and as
\r
9781 4261: simple as possible. More information (albeit Cortex-M specific) is
\r
9782 4262: provided on the following link:
\r
9783 4263: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
9784 4264: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
9786 4266: pxTCB = ( TCB_t * ) xTaskToNotify;
\r
9787 BFD01EEC 0028FC5E LW V0, 40(S8)
\r
9788 BFD01EF0 0014F85E SW V0, 20(S8)
\r
9790 4268: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
9791 BFD01EF4 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
9793 BFD01EFA 0018F85E SW V0, 24(S8)
\r
9795 4270: eOriginalNotifyState = pxTCB->eNotifyState;
\r
9796 BFD01EFE 0014FC5E LW V0, 20(S8)
\r
9797 BFD01F02 004CFC42 LW V0, 76(V0)
\r
9798 BFD01F06 001CF85E SW V0, 28(S8)
\r
9800 4272: pxTCB->eNotifyState = eNotified;
\r
9801 BFD01F0A 0014FC5E LW V0, 20(S8)
\r
9802 BFD01F0E ED82 LI V1, 2
\r
9803 BFD01F10 004CF862 SW V1, 76(V0)
\r
9805 4274: switch( eAction )
\r
9806 BFD01F14 0030FC5E LW V0, 48(S8)
\r
9807 BFD01F18 0005B042 SLTIU V0, V0, 5
\r
9808 BFD01F1C 004740E2 BEQZC V0, 0xBFD01FAE
\r
9809 BFD01F20 0030FC5E LW V0, 48(S8)
\r
9810 BFD01F24 25A4 SLL V1, V0, 2
\r
9811 BFD01F26 BFD041A2 LUI V0, 0xBFD0
\r
9812 BFD01F28 3042BFD0 LDC1 F30, 12354(S0)
\r
9813 BFD01F2A 1F343042 ADDIU V0, V0, 7988
\r
9814 BFD01F2C 05261F34 LB T9, 1318(S4)
\r
9815 BFD01F2E 0526 ADDU V0, V1, V0
\r
9816 BFD01F30 6920 LW V0, 0(V0)
\r
9817 BFD01F32 45A2 JRC V0
\r
9818 BFD01F34 BFD01FAD LB SP, -16432(T5)
\r
9819 BFD01F36 1F49BFD0 LDC1 F30, 8009(S0)
\r
9820 BFD01F38 BFD01F49 LB K0, -16432(T1)
\r
9821 BFD01F3A 1F63BFD0 LDC1 F30, 8035(S0)
\r
9822 BFD01F3C BFD01F63 LB K1, -16432(V1)
\r
9823 BFD01F3E 1F79BFD0 LDC1 F30, 8057(S0)
\r
9824 BFD01F40 BFD01F79 LB K1, -16432(T9)
\r
9825 BFD01F42 1F89BFD0 LDC1 F30, 8073(S0)
\r
9826 BFD01F44 BFD01F89 LB GP, -16432(T1)
\r
9827 BFD01F46 FC5EBFD0 LDC1 F30, -930(S0)
\r
9829 4276: case eSetBits :
\r
9830 4277: pxTCB->ulNotifiedValue |= ulValue;
\r
9831 BFD01F48 0014FC5E LW V0, 20(S8)
\r
9832 BFD01F4C 0048FC62 LW V1, 72(V0)
\r
9833 BFD01F50 002CFC5E LW V0, 44(S8)
\r
9834 BFD01F54 44DA OR16 V1, V0
\r
9835 BFD01F56 0014FC5E LW V0, 20(S8)
\r
9836 BFD01F5A 0048F862 SW V1, 72(V0)
\r
9838 BFD01F5E CC27 B 0xBFD01FAE
\r
9841 4280: case eIncrement :
\r
9842 4281: ( pxTCB->ulNotifiedValue )++;
\r
9843 BFD01F62 0014FC5E LW V0, 20(S8)
\r
9844 BFD01F66 0048FC42 LW V0, 72(V0)
\r
9845 BFD01F6A 6DA0 ADDIU V1, V0, 1
\r
9846 BFD01F6C 0014FC5E LW V0, 20(S8)
\r
9847 BFD01F70 0048F862 SW V1, 72(V0)
\r
9849 BFD01F74 CC1C B 0xBFD01FAE
\r
9852 4284: case eSetValueWithOverwrite :
\r
9853 4285: pxTCB->ulNotifiedValue = ulValue;
\r
9854 BFD01F78 0014FC5E LW V0, 20(S8)
\r
9855 BFD01F7C 002CFC7E LW V1, 44(S8)
\r
9856 BFD01F80 0048F862 SW V1, 72(V0)
\r
9858 BFD01F84 CC14 B 0xBFD01FAE
\r
9861 4288: case eSetValueWithoutOverwrite :
\r
9862 4289: if( eOriginalNotifyState != eNotified )
\r
9863 BFD01F88 001CFC7E LW V1, 28(S8)
\r
9864 BFD01F8C ED02 LI V0, 2
\r
9865 BFD01F8E 00099443 BEQ V1, V0, 0xBFD01FA4
\r
9866 BFD01F90 0C000009 SLL ZERO, T1, 1
\r
9869 4291: pxTCB->ulNotifiedValue = ulValue;
\r
9870 BFD01F94 0014FC5E LW V0, 20(S8)
\r
9871 BFD01F98 002CFC7E LW V1, 44(S8)
\r
9872 BFD01F9C 0048F862 SW V1, 72(V0)
\r
9876 4295: /* The value could not be written to the task. */
\r
9877 4296: xReturn = pdFAIL;
\r
9878 BFD01FA4 0010F81E SW ZERO, 16(S8)
\r
9881 BFD01FA0 CC06 B 0xBFD01FAE
\r
9883 BFD01FA8 CC02 B 0xBFD01FAE
\r
9886 4300: case eNoAction :
\r
9887 4301: /* The task is being notified without its notify value being
\r
9894 4307: /* If the task is in the blocked state specifically to wait for a
\r
9895 4308: notification then unblock it now. */
\r
9896 4309: if( eOriginalNotifyState == eWaitingNotification )
\r
9897 BFD01FAE 001CFC7E LW V1, 28(S8)
\r
9898 BFD01FB2 ED01 LI V0, 1
\r
9899 BFD01FB4 0057B443 BNE V1, V0, 0xBFD02066
\r
9900 BFD01FB6 0C000057 SLL V0, S7, 1
\r
9903 4311: /* The task should not have been on an event list. */
\r
9904 4312: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
\r
9905 BFD01FBA 0014FC5E LW V0, 20(S8)
\r
9906 BFD01FBE 692A LW V0, 40(V0)
\r
9907 BFD01FC0 000940E2 BEQZC V0, 0xBFD01FD6
\r
9908 BFD01FC4 BFD141A2 LUI V0, 0xBFD1
\r
9909 BFD01FC6 3082BFD1 LDC1 F30, 12418(S1)
\r
9910 BFD01FC8 98103082 ADDIU A0, V0, -26608
\r
9911 BFD01FCA 30A09810 SWC1 F0, 12448(S0)
\r
9912 BFD01FCC 10D830A0 ADDIU A1, ZERO, 4312
\r
9913 BFD01FCE 77E810D8 ADDI A2, T8, 30696
\r
9914 BFD01FD0 4B7E77E8 JALS vAssertCalled
\r
9915 BFD01FD2 4B7E LW K1, 120(SP)
\r
9918 4314: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
\r
9919 BFD01FD6 805CFC5C LW V0, -32676(GP)
\r
9920 BFD01FDA 002740A2 BNEZC V0, 0xBFD0202C
\r
9922 4316: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
9923 BFD01FDE 0014FC5E LW V0, 20(S8)
\r
9924 BFD01FE2 6D22 ADDIU V0, V0, 4
\r
9925 BFD01FE4 0C82 MOVE A0, V0
\r
9926 BFD01FE6 00C877E8 JALS uxListRemove
\r
9927 BFD01FE8 0C0000C8 SLL A2, T0, 1
\r
9929 4317: prvAddTaskToReadyList( pxTCB );
\r
9930 BFD01FEC 0014FC5E LW V0, 20(S8)
\r
9931 BFD01FF0 692B LW V0, 44(V0)
\r
9932 BFD01FF2 ED81 LI V1, 1
\r
9933 BFD01FF4 18100062 SLLV V1, V0, V1
\r
9934 BFD01FF6 FC5C1810 SB ZERO, -932(S0)
\r
9935 BFD01FF8 8040FC5C LW V0, -32704(GP)
\r
9936 BFD01FFC 44D3 OR16 V0, V1
\r
9937 BFD01FFE 8040F85C SW V0, -32704(GP)
\r
9938 BFD02002 0014FC5E LW V0, 20(S8)
\r
9939 BFD02006 692B LW V0, 44(V0)
\r
9940 BFD02008 2524 SLL V0, V0, 2
\r
9941 BFD0200A 25A4 SLL V1, V0, 2
\r
9942 BFD0200C 05B4 ADDU V1, V0, V1
\r
9943 BFD0200E BFD241A2 LUI V0, 0xBFD2
\r
9944 BFD02010 3042BFD2 LDC1 F30, 12354(S2)
\r
9945 BFD02012 806C3042 ADDIU V0, V0, -32660
\r
9946 BFD02016 05A6 ADDU V1, V1, V0
\r
9947 BFD02018 0014FC5E LW V0, 20(S8)
\r
9948 BFD0201C 6D22 ADDIU V0, V0, 4
\r
9949 BFD0201E 0C83 MOVE A0, V1
\r
9950 BFD02020 0CA2 MOVE A1, V0
\r
9951 BFD02022 3E4A77E8 JALS vListInsertEnd
\r
9952 BFD02024 0C003E4A LH S2, 3072(T2)
\r
9954 BFD02028 CC0C B 0xBFD02042
\r
9959 4321: /* The delayed and ready lists cannot be accessed, so hold
\r
9960 4322: this task pending until the scheduler is resumed. */
\r
9961 4323: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
\r
9962 BFD0202C 0014FC5E LW V0, 20(S8)
\r
9963 BFD0202E 6D2C0014 EXT ZERO, S4, 20, 14
\r
9964 BFD02030 6D2C ADDIU V0, V0, 24
\r
9965 BFD02032 BFD241A3 LUI V1, 0xBFD2
\r
9966 BFD02034 3083BFD2 LDC1 F30, 12419(S2)
\r
9967 BFD02036 80D03083 ADDIU A0, V1, -32560
\r
9968 BFD0203A 0CA2 MOVE A1, V0
\r
9969 BFD0203C 3E4A77E8 JALS vListInsertEnd
\r
9970 BFD0203E 0C003E4A LH S2, 3072(T2)
\r
9974 4326: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
\r
9975 BFD02042 0014FC5E LW V0, 20(S8)
\r
9976 BFD02046 69AB LW V1, 44(V0)
\r
9977 BFD02048 8030FC5C LW V0, -32720(GP)
\r
9978 BFD0204C 692B LW V0, 44(V0)
\r
9979 BFD0204E 13900062 SLTU V0, V0, V1
\r
9980 BFD02050 40E21390 ADDI GP, S0, 16610
\r
9981 BFD02052 000840E2 BEQZC V0, 0xBFD02066
\r
9983 4328: /* The notified task has a priority above the currently
\r
9984 4329: executing task so a yield is required. */
\r
9985 4330: if( pxHigherPriorityTaskWoken != NULL )
\r
9986 BFD02056 0034FC5E LW V0, 52(S8)
\r
9987 BFD0205A 000440E2 BEQZC V0, 0xBFD02066
\r
9989 4332: *pxHigherPriorityTaskWoken = pdTRUE;
\r
9990 BFD0205E 0034FC5E LW V0, 52(S8)
\r
9991 BFD02062 ED81 LI V1, 1
\r
9992 BFD02064 E9A0 SW V1, 0(V0)
\r
9997 4337: mtCOVERAGE_TEST_MARKER();
\r
10001 4341: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
10002 BFD02066 0018FC9E LW A0, 24(S8)
\r
10003 BFD0206A 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
10004 BFD0206C 4D5E ADDIU T2, T2, -1
\r
10005 BFD0206E 0C00 NOP
\r
10007 4343: return xReturn;
\r
10008 BFD02070 0010FC5E LW V0, 16(S8)
\r
10010 BFD02074 0FBE MOVE SP, S8
\r
10011 BFD02076 4BE9 LW RA, 36(SP)
\r
10012 BFD02078 4BC8 LW S8, 32(SP)
\r
10013 BFD0207A 4C15 ADDIU SP, SP, 40
\r
10014 BFD0207C 459F JR16 RA
\r
10015 BFD0207E 0C00 NOP
\r
10017 4346: #endif /* configUSE_TASK_NOTIFICATIONS */
\r
10018 4347: /*-----------------------------------------------------------*/
\r
10020 4349: #if( configUSE_TASK_NOTIFICATIONS == 1 )
\r
10022 4351: void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
\r
10024 BFD03190 4FED ADDIU SP, SP, -40
\r
10025 BFD03192 CBE9 SW RA, 36(SP)
\r
10026 BFD03194 CBC8 SW S8, 32(SP)
\r
10027 BFD03196 0FDD MOVE S8, SP
\r
10028 BFD03198 0028F89E SW A0, 40(S8)
\r
10029 BFD0319C 002CF8BE SW A1, 44(S8)
\r
10030 4353: TCB_t * pxTCB;
\r
10031 4354: eNotifyValue eOriginalNotifyState;
\r
10032 4355: UBaseType_t uxSavedInterruptStatus;
\r
10034 4357: configASSERT( xTaskToNotify );
\r
10035 BFD031A0 0028FC5E LW V0, 40(S8)
\r
10036 BFD031A4 000940A2 BNEZC V0, 0xBFD031BA
\r
10037 BFD031A8 BFD141A2 LUI V0, 0xBFD1
\r
10038 BFD031AA 3082BFD1 LDC1 F30, 12418(S1)
\r
10039 BFD031AC 98103082 ADDIU A0, V0, -26608
\r
10040 BFD031AE 30A09810 SWC1 F0, 12448(S0)
\r
10041 BFD031B0 110530A0 ADDIU A1, ZERO, 4357
\r
10042 BFD031B2 77E81105 ADDI T0, A1, 30696
\r
10043 BFD031B4 4B7E77E8 JALS vAssertCalled
\r
10044 BFD031B6 4B7E LW K1, 120(SP)
\r
10045 BFD031B8 0C00 NOP
\r
10047 4359: /* RTOS ports that support interrupt nesting have the concept of a
\r
10048 4360: maximum system call (or maximum API call) interrupt priority.
\r
10049 4361: Interrupts that are above the maximum system call priority are keep
\r
10050 4362: permanently enabled, even when the RTOS kernel is in a critical section,
\r
10051 4363: but cannot make any calls to FreeRTOS API functions. If configASSERT()
\r
10052 4364: is defined in FreeRTOSConfig.h then
\r
10053 4365: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
10054 4366: failure if a FreeRTOS API function is called from an interrupt that has
\r
10055 4367: been assigned a priority above the configured maximum system call
\r
10056 4368: priority. Only FreeRTOS functions that end in FromISR can be called
\r
10057 4369: from interrupts that have been assigned a priority at or (logically)
\r
10058 4370: below the maximum system call interrupt priority. FreeRTOS maintains a
\r
10059 4371: separate interrupt safe API to ensure interrupt entry is as fast and as
\r
10060 4372: simple as possible. More information (albeit Cortex-M specific) is
\r
10061 4373: provided on the following link:
\r
10062 4374: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
10063 4375: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
10065 4377: pxTCB = ( TCB_t * ) xTaskToNotify;
\r
10066 BFD031BA 0028FC5E LW V0, 40(S8)
\r
10067 BFD031BE 0010F85E SW V0, 16(S8)
\r
10069 4379: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
10070 BFD031C2 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
10071 BFD031C6 0C00 NOP
\r
10072 BFD031C8 0014F85E SW V0, 20(S8)
\r
10074 4381: eOriginalNotifyState = pxTCB->eNotifyState;
\r
10075 BFD031CC 0010FC5E LW V0, 16(S8)
\r
10076 BFD031D0 004CFC42 LW V0, 76(V0)
\r
10077 BFD031D4 0018F85E SW V0, 24(S8)
\r
10078 4382: pxTCB->eNotifyState = eNotified;
\r
10079 BFD031D8 0010FC5E LW V0, 16(S8)
\r
10080 BFD031DC ED82 LI V1, 2
\r
10081 BFD031DE 004CF862 SW V1, 76(V0)
\r
10083 4384: /* 'Giving' is equivalent to incrementing a count in a counting
\r
10084 4385: semaphore. */
\r
10085 4386: ( pxTCB->ulNotifiedValue )++;
\r
10086 BFD031E2 0010FC5E LW V0, 16(S8)
\r
10087 BFD031E6 0048FC42 LW V0, 72(V0)
\r
10088 BFD031EA 6DA0 ADDIU V1, V0, 1
\r
10089 BFD031EC 0010FC5E LW V0, 16(S8)
\r
10090 BFD031F0 0048F862 SW V1, 72(V0)
\r
10092 4388: /* If the task is in the blocked state specifically to wait for a
\r
10093 4389: notification then unblock it now. */
\r
10094 4390: if( eOriginalNotifyState == eWaitingNotification )
\r
10095 BFD031F4 0018FC7E LW V1, 24(S8)
\r
10096 BFD031F8 ED01 LI V0, 1
\r
10097 BFD031FA 0057B443 BNE V1, V0, 0xBFD032AC
\r
10098 BFD031FC 0C000057 SLL V0, S7, 1
\r
10099 BFD031FE 0C00 NOP
\r
10101 4392: /* The task should not have been on an event list. */
\r
10102 4393: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
\r
10103 BFD03200 0010FC5E LW V0, 16(S8)
\r
10104 BFD03204 692A LW V0, 40(V0)
\r
10105 BFD03206 000940E2 BEQZC V0, 0xBFD0321C
\r
10106 BFD0320A BFD141A2 LUI V0, 0xBFD1
\r
10107 BFD0320C 3082BFD1 LDC1 F30, 12418(S1)
\r
10108 BFD0320E 98103082 ADDIU A0, V0, -26608
\r
10109 BFD03210 30A09810 SWC1 F0, 12448(S0)
\r
10110 BFD03212 112930A0 ADDIU A1, ZERO, 4393
\r
10111 BFD03214 77E81129 ADDI T1, T1, 30696
\r
10112 BFD03216 4B7E77E8 JALS vAssertCalled
\r
10113 BFD03218 4B7E LW K1, 120(SP)
\r
10114 BFD0321A 0C00 NOP
\r
10116 4395: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
\r
10117 BFD0321C 805CFC5C LW V0, -32676(GP)
\r
10118 BFD03220 002740A2 BNEZC V0, 0xBFD03272
\r
10120 4397: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
\r
10121 BFD03224 0010FC5E LW V0, 16(S8)
\r
10122 BFD03228 6D22 ADDIU V0, V0, 4
\r
10123 BFD0322A 0C82 MOVE A0, V0
\r
10124 BFD0322C 00C877E8 JALS uxListRemove
\r
10125 BFD0322E 0C0000C8 SLL A2, T0, 1
\r
10126 BFD03230 0C00 NOP
\r
10127 4398: prvAddTaskToReadyList( pxTCB );
\r
10128 BFD03232 0010FC5E LW V0, 16(S8)
\r
10129 BFD03236 692B LW V0, 44(V0)
\r
10130 BFD03238 ED81 LI V1, 1
\r
10131 BFD0323A 18100062 SLLV V1, V0, V1
\r
10132 BFD0323C FC5C1810 SB ZERO, -932(S0)
\r
10133 BFD0323E 8040FC5C LW V0, -32704(GP)
\r
10134 BFD03242 44D3 OR16 V0, V1
\r
10135 BFD03244 8040F85C SW V0, -32704(GP)
\r
10136 BFD03248 0010FC5E LW V0, 16(S8)
\r
10137 BFD0324C 692B LW V0, 44(V0)
\r
10138 BFD0324E 2524 SLL V0, V0, 2
\r
10139 BFD03250 25A4 SLL V1, V0, 2
\r
10140 BFD03252 05B4 ADDU V1, V0, V1
\r
10141 BFD03254 BFD241A2 LUI V0, 0xBFD2
\r
10142 BFD03256 3042BFD2 LDC1 F30, 12354(S2)
\r
10143 BFD03258 806C3042 ADDIU V0, V0, -32660
\r
10144 BFD0325C 05A6 ADDU V1, V1, V0
\r
10145 BFD0325E 0010FC5E LW V0, 16(S8)
\r
10146 BFD03262 6D22 ADDIU V0, V0, 4
\r
10147 BFD03264 0C83 MOVE A0, V1
\r
10148 BFD03266 0CA2 MOVE A1, V0
\r
10149 BFD03268 3E4A77E8 JALS vListInsertEnd
\r
10150 BFD0326A 0C003E4A LH S2, 3072(T2)
\r
10151 BFD0326C 0C00 NOP
\r
10152 BFD0326E CC0C B 0xBFD03288
\r
10153 BFD03270 0C00 NOP
\r
10157 4402: /* The delayed and ready lists cannot be accessed, so hold
\r
10158 4403: this task pending until the scheduler is resumed. */
\r
10159 4404: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
\r
10160 BFD03272 0010FC5E LW V0, 16(S8)
\r
10161 BFD03274 6D2C0010 EXT ZERO, S0, 20, 14
\r
10162 BFD03276 6D2C ADDIU V0, V0, 24
\r
10163 BFD03278 BFD241A3 LUI V1, 0xBFD2
\r
10164 BFD0327A 3083BFD2 LDC1 F30, 12419(S2)
\r
10165 BFD0327C 80D03083 ADDIU A0, V1, -32560
\r
10166 BFD03280 0CA2 MOVE A1, V0
\r
10167 BFD03282 3E4A77E8 JALS vListInsertEnd
\r
10168 BFD03284 0C003E4A LH S2, 3072(T2)
\r
10169 BFD03286 0C00 NOP
\r
10172 4407: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
\r
10173 BFD03288 0010FC5E LW V0, 16(S8)
\r
10174 BFD0328C 69AB LW V1, 44(V0)
\r
10175 BFD0328E 8030FC5C LW V0, -32720(GP)
\r
10176 BFD03292 692B LW V0, 44(V0)
\r
10177 BFD03294 13900062 SLTU V0, V0, V1
\r
10178 BFD03296 40E21390 ADDI GP, S0, 16610
\r
10179 BFD03298 000840E2 BEQZC V0, 0xBFD032AC
\r
10181 4409: /* The notified task has a priority above the currently
\r
10182 4410: executing task so a yield is required. */
\r
10183 4411: if( pxHigherPriorityTaskWoken != NULL )
\r
10184 BFD0329C 002CFC5E LW V0, 44(S8)
\r
10185 BFD032A0 000440E2 BEQZC V0, 0xBFD032AC
\r
10187 4413: *pxHigherPriorityTaskWoken = pdTRUE;
\r
10188 BFD032A4 002CFC5E LW V0, 44(S8)
\r
10189 BFD032A8 ED81 LI V1, 1
\r
10190 BFD032AA E9A0 SW V1, 0(V0)
\r
10195 4418: mtCOVERAGE_TEST_MARKER();
\r
10199 4422: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
10200 BFD032AC 0014FC9E LW A0, 20(S8)
\r
10201 BFD032B0 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
10202 BFD032B2 4D5E ADDIU T2, T2, -1
\r
10203 BFD032B4 0C00 NOP
\r
10205 BFD032B6 0FBE MOVE SP, S8
\r
10206 BFD032B8 4BE9 LW RA, 36(SP)
\r
10207 BFD032BA 4BC8 LW S8, 32(SP)
\r
10208 BFD032BC 4C15 ADDIU SP, SP, 40
\r
10209 BFD032BE 459F JR16 RA
\r
10210 BFD032C0 0C00 NOP
\r
10212 4425: #endif /* configUSE_TASK_NOTIFICATIONS */
\r
10214 4427: /*-----------------------------------------------------------*/
\r
10217 4430: #ifdef FREERTOS_MODULE_TEST
\r
10218 4431: #include "tasks_test_access_functions.h"
\r
10221 --- c:/e/dev/freertos/workingcopy/freertos/source/queue.c ---------------------------------------------
\r
10223 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
10224 3: All rights reserved
\r
10226 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
10228 7: This file is part of the FreeRTOS distribution.
\r
10230 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10231 10: the terms of the GNU General Public License (version 2) as published by the
\r
10232 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
10234 13: ***************************************************************************
\r
10235 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
10236 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
10237 16: >>! obliged to provide the source code for proprietary components !<<
\r
10238 17: >>! outside of the FreeRTOS kernel. !<<
\r
10239 18: ***************************************************************************
\r
10241 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
10242 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
10243 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
10244 23: link: http://www.freertos.org/a00114.html
\r
10246 25: ***************************************************************************
\r
10248 27: * FreeRTOS provides completely free yet professionally developed, *
\r
10249 28: * robust, strictly quality controlled, supported, and cross *
\r
10250 29: * platform software that is more than just the market leader, it *
\r
10251 30: * is the industry's de facto standard. *
\r
10253 32: * Help yourself get started quickly while simultaneously helping *
\r
10254 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
10255 34: * tutorial book, reference manual, or both: *
\r
10256 35: * http://www.FreeRTOS.org/Documentation *
\r
10258 37: ***************************************************************************
\r
10260 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
10261 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
10262 41: defined configASSERT()?
\r
10264 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
10265 44: embedded software for free we request you assist our global community by
\r
10266 45: participating in the support forum.
\r
10268 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
10269 48: be as productive as possible as early as possible. Now you can receive
\r
10270 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
10271 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
10273 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
10274 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
10275 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
10277 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
10278 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
10280 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
10281 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
10282 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
10284 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
10285 64: engineered and independently SIL3 certified version for use in safety and
\r
10286 65: mission critical applications that require provable dependability.
\r
10288 67: 1 tab == 4 spaces!
\r
10291 70: #include <stdlib.h>
\r
10292 71: #include <string.h>
\r
10294 73: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
\r
10295 74: all the API functions to use the MPU wrappers. That should only be done when
\r
10296 75: task.h is included from an application file. */
\r
10297 76: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
\r
10299 78: #include "FreeRTOS.h"
\r
10300 79: #include "task.h"
\r
10301 80: #include "queue.h"
\r
10303 82: #if ( configUSE_CO_ROUTINES == 1 )
\r
10304 83: #include "croutine.h"
\r
10307 86: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the
\r
10308 87: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
\r
10309 88: header files above, but not in this file, in order to generate the correct
\r
10310 89: privileged Vs unprivileged linkage and placement. */
\r
10311 90: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
\r
10314 93: /* Constants used with the xRxLock and xTxLock structure members. */
\r
10315 94: #define queueUNLOCKED ( ( BaseType_t ) -1 )
\r
10316 95: #define queueLOCKED_UNMODIFIED ( ( BaseType_t ) 0 )
\r
10318 97: /* When the Queue_t structure is used to represent a base queue its pcHead and
\r
10319 98: pcTail members are used as pointers into the queue storage area. When the
\r
10320 99: Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
\r
10321 100: not necessary, and the pcHead pointer is set to NULL to indicate that the
\r
10322 101: pcTail pointer actually points to the mutex holder (if any). Map alternative
\r
10323 102: names to the pcHead and pcTail structure members to ensure the readability of
\r
10324 103: the code is maintained despite this dual use of two structure members. An
\r
10325 104: alternative implementation would be to use a union, but use of a union is
\r
10326 105: against the coding standard (although an exception to the standard has been
\r
10327 106: permitted where the dual use also significantly changes the type of the
\r
10328 107: structure member). */
\r
10329 108: #define pxMutexHolder pcTail
\r
10330 109: #define uxQueueType pcHead
\r
10331 110: #define queueQUEUE_IS_MUTEX NULL
\r
10333 112: /* Semaphores do not actually store or copy data, so have an item size of
\r
10335 114: #define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
\r
10336 115: #define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U )
\r
10338 117: #if( configUSE_PREEMPTION == 0 )
\r
10339 118: /* If the cooperative scheduler is being used then a yield should not be
\r
10340 119: performed just because a higher priority task has been woken. */
\r
10341 120: #define queueYIELD_IF_USING_PREEMPTION()
\r
10343 122: #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
\r
10347 126: * Definition of the queue used by the scheduler.
\r
10348 127: * Items are queued by copy, not reference. See the following link for the
\r
10349 128: * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html
\r
10351 130: typedef struct QueueDefinition
\r
10353 132: int8_t *pcHead; /*< Points to the beginning of the queue storage area. */
\r
10354 133: int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
\r
10355 134: int8_t *pcWriteTo; /*< Points to the free next place in the storage area. */
\r
10357 136: union /* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
\r
10359 138: int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */
\r
10360 139: UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
\r
10363 142: List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */
\r
10364 143: List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */
\r
10366 145: volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
\r
10367 146: UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
\r
10368 147: UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */
\r
10370 149: volatile BaseType_t xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
\r
10371 150: volatile BaseType_t xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
\r
10373 152: #if ( configUSE_TRACE_FACILITY == 1 )
\r
10374 153: UBaseType_t uxQueueNumber;
\r
10375 154: uint8_t ucQueueType;
\r
10378 157: #if ( configUSE_QUEUE_SETS == 1 )
\r
10379 158: struct QueueDefinition *pxQueueSetContainer;
\r
10384 163: /* The old xQUEUE name is maintained above then typedefed to the new Queue_t
\r
10385 164: name below to enable the use of older kernel aware debuggers. */
\r
10386 165: typedef xQUEUE Queue_t;
\r
10388 167: /*-----------------------------------------------------------*/
\r
10391 170: * The queue registry is just a means for kernel aware debuggers to locate
\r
10392 171: * queue structures. It has no other purpose so is an optional component.
\r
10394 173: #if ( configQUEUE_REGISTRY_SIZE > 0 )
\r
10396 175: /* The type stored within the queue registry array. This allows a name
\r
10397 176: to be assigned to each queue making kernel aware debugging a little
\r
10398 177: more user friendly. */
\r
10399 178: typedef struct QUEUE_REGISTRY_ITEM
\r
10401 180: const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
\r
10402 181: QueueHandle_t xHandle;
\r
10403 182: } xQueueRegistryItem;
\r
10405 184: /* The old xQueueRegistryItem name is maintained above then typedefed to the
\r
10406 185: new xQueueRegistryItem name below to enable the use of older kernel aware
\r
10407 186: debuggers. */
\r
10408 187: typedef xQueueRegistryItem QueueRegistryItem_t;
\r
10410 189: /* The queue registry is simply an array of QueueRegistryItem_t structures.
\r
10411 190: The pcQueueName member of a structure being NULL is indicative of the
\r
10412 191: array position being vacant. */
\r
10413 192: PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
\r
10415 194: #endif /* configQUEUE_REGISTRY_SIZE */
\r
10418 197: * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not
\r
10419 198: * prevent an ISR from adding or removing items to the queue, but does prevent
\r
10420 199: * an ISR from removing tasks from the queue event lists. If an ISR finds a
\r
10421 200: * queue is locked it will instead increment the appropriate queue lock count
\r
10422 201: * to indicate that a task may require unblocking. When the queue in unlocked
\r
10423 202: * these lock counts are inspected, and the appropriate action taken.
\r
10425 204: static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
\r
10428 207: * Uses a critical section to determine if there is any data in a queue.
\r
10430 209: * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
\r
10432 211: static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
\r
10435 214: * Uses a critical section to determine if there is any space in a queue.
\r
10437 216: * @return pdTRUE if there is no space, otherwise pdFALSE;
\r
10439 218: static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
\r
10442 221: * Copies an item into the queue, either at the front of the queue or the
\r
10443 222: * back of the queue.
\r
10445 224: static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
\r
10448 227: * Copies an item out of a queue.
\r
10450 229: static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
\r
10452 231: #if ( configUSE_QUEUE_SETS == 1 )
\r
10454 233: * Checks to see if a queue is a member of a queue set, and if so, notifies
\r
10455 234: * the queue set that the queue contains data.
\r
10457 236: static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
\r
10460 239: /*-----------------------------------------------------------*/
\r
10463 242: * Macro to mark a queue as locked. Locking a queue prevents an ISR from
\r
10464 243: * accessing the queue event lists.
\r
10466 245: #define prvLockQueue( pxQueue ) \
\r
10467 246: taskENTER_CRITICAL(); \
\r
10469 248: if( ( pxQueue )->xRxLock == queueUNLOCKED ) \
\r
10471 250: ( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED; \
\r
10473 252: if( ( pxQueue )->xTxLock == queueUNLOCKED ) \
\r
10475 254: ( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED; \
\r
10478 257: taskEXIT_CRITICAL()
\r
10479 258: /*-----------------------------------------------------------*/
\r
10481 260: BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
\r
10483 BFD0388C 4FF1 ADDIU SP, SP, -32
\r
10484 BFD0388E CBE7 SW RA, 28(SP)
\r
10485 BFD03890 CBC6 SW S8, 24(SP)
\r
10486 BFD03892 0FDD MOVE S8, SP
\r
10487 BFD03894 0020F89E SW A0, 32(S8)
\r
10488 BFD03898 0024F8BE SW A1, 36(S8)
\r
10489 262: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
10490 BFD0389C 0020FC5E LW V0, 32(S8)
\r
10491 BFD038A0 0010F85E SW V0, 16(S8)
\r
10493 264: configASSERT( pxQueue );
\r
10494 BFD038A4 0010FC5E LW V0, 16(S8)
\r
10495 BFD038A8 000940A2 BNEZC V0, 0xBFD038BE
\r
10496 BFD038AC BFD141A2 LUI V0, 0xBFD1
\r
10497 BFD038AE 3082BFD1 LDC1 F30, 12418(S1)
\r
10498 BFD038B0 9E3C3082 ADDIU A0, V0, -25028
\r
10499 BFD038B2 30A09E3C LWC1 F17, 12448(GP)
\r
10500 BFD038B4 010830A0 ADDIU A1, ZERO, 264
\r
10501 BFD038B8 4B7E77E8 JALS vAssertCalled
\r
10502 BFD038BA 4B7E LW K1, 120(SP)
\r
10503 BFD038BC 0C00 NOP
\r
10505 266: taskENTER_CRITICAL();
\r
10506 BFD038BE 33B877E8 JALS vTaskEnterCritical
\r
10507 BFD038C0 0C0033B8 ADDIU SP, T8, 3072
\r
10508 BFD038C2 0C00 NOP
\r
10510 268: pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
\r
10511 BFD038C4 0010FC5E LW V0, 16(S8)
\r
10512 BFD038C8 6920 LW V0, 0(V0)
\r
10513 BFD038CA 0010FC7E LW V1, 16(S8)
\r
10514 BFD038CE 6A3F LW A0, 60(V1)
\r
10515 BFD038D0 0010FC7E LW V1, 16(S8)
\r
10516 BFD038D4 0040FC63 LW V1, 64(V1)
\r
10517 BFD038D8 1A100064 MUL V1, A0, V1
\r
10518 BFD038DA 05B41A10 SB S0, 1460(S0)
\r
10519 BFD038DC 05B4 ADDU V1, V0, V1
\r
10520 BFD038DE 0010FC5E LW V0, 16(S8)
\r
10521 BFD038E2 E9A1 SW V1, 4(V0)
\r
10522 269: pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
\r
10523 BFD038E4 0010FC5E LW V0, 16(S8)
\r
10524 BFD038E8 E82E SW S0, 56(V0)
\r
10525 270: pxQueue->pcWriteTo = pxQueue->pcHead;
\r
10526 BFD038EA 0010FC5E LW V0, 16(S8)
\r
10527 BFD038EE 69A0 LW V1, 0(V0)
\r
10528 BFD038F0 0010FC5E LW V0, 16(S8)
\r
10529 BFD038F4 E9A2 SW V1, 8(V0)
\r
10530 271: pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
\r
10531 BFD038F6 0010FC5E LW V0, 16(S8)
\r
10532 BFD038FA 6920 LW V0, 0(V0)
\r
10533 BFD038FC 0010FC7E LW V1, 16(S8)
\r
10534 BFD03900 69BF LW V1, 60(V1)
\r
10535 BFD03902 6E3E ADDIU A0, V1, -1
\r
10536 BFD03904 0010FC7E LW V1, 16(S8)
\r
10537 BFD03908 0040FC63 LW V1, 64(V1)
\r
10538 BFD0390C 1A100064 MUL V1, A0, V1
\r
10539 BFD0390E 05B41A10 SB S0, 1460(S0)
\r
10540 BFD03910 05B4 ADDU V1, V0, V1
\r
10541 BFD03912 0010FC5E LW V0, 16(S8)
\r
10542 BFD03916 E9A3 SW V1, 12(V0)
\r
10543 272: pxQueue->xRxLock = queueUNLOCKED;
\r
10544 BFD03918 0010FC5E LW V0, 16(S8)
\r
10545 BFD0391C EDFF LI V1, -1
\r
10546 BFD0391E 0044F862 SW V1, 68(V0)
\r
10547 273: pxQueue->xTxLock = queueUNLOCKED;
\r
10548 BFD03922 0010FC5E LW V0, 16(S8)
\r
10549 BFD03926 EDFF LI V1, -1
\r
10550 BFD03928 0048F862 SW V1, 72(V0)
\r
10552 275: if( xNewQueue == pdFALSE )
\r
10553 BFD0392C 0024FC5E LW V0, 36(S8)
\r
10554 BFD03930 002340A2 BNEZC V0, 0xBFD0397A
\r
10556 277: /* If there are tasks blocked waiting to read from the queue, then
\r
10557 278: the tasks will remain blocked as after this function exits the queue
\r
10558 279: will still be empty. If there are tasks blocked waiting to write to
\r
10559 280: the queue, then one should be unblocked as after this function exits
\r
10560 281: it will be possible to write to it. */
\r
10561 282: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
\r
10562 BFD03934 0010FC5E LW V0, 16(S8)
\r
10563 BFD03938 6924 LW V0, 16(V0)
\r
10564 BFD0393A 002D40E2 BEQZC V0, 0xBFD03998
\r
10566 284: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
\r
10567 BFD0393E 0010FC5E LW V0, 16(S8)
\r
10568 BFD03942 6D28 ADDIU V0, V0, 16
\r
10569 BFD03944 0C82 MOVE A0, V0
\r
10570 BFD03946 22BC77E8 JALS xTaskRemoveFromEventList
\r
10571 BFD03948 0C0022BC LWC2 S5, 3072(GP)
\r
10572 BFD0394A 0C00 NOP
\r
10573 BFD0394C 0C62 MOVE V1, V0
\r
10574 BFD0394E ED01 LI V0, 1
\r
10575 BFD03950 0022B443 BNE V1, V0, 0xBFD03998
\r
10576 BFD03952 0C000022 SLL AT, V0, 1
\r
10577 BFD03954 0C00 NOP
\r
10579 286: queueYIELD_IF_USING_PREEMPTION();
\r
10580 BFD03956 4E1677E8 JALS ulPortGetCP0Cause
\r
10581 BFD03958 4E16 ADDIU S0, S0, -5
\r
10582 BFD0395A 0C00 NOP
\r
10583 BFD0395C 0014F85E SW V0, 20(S8)
\r
10584 BFD03960 0014FC5E LW V0, 20(S8)
\r
10585 BFD03964 01005042 ORI V0, V0, 256
\r
10586 BFD03968 0014F85E SW V0, 20(S8)
\r
10587 BFD0396C 0014FC9E LW A0, 20(S8)
\r
10588 BFD03970 4E2677E8 JALS vPortSetCP0Cause
\r
10589 BFD03972 4E26 ADDIU S1, S1, 3
\r
10590 BFD03974 0C00 NOP
\r
10591 BFD03976 CC10 B 0xBFD03998
\r
10592 BFD03978 0C00 NOP
\r
10596 290: mtCOVERAGE_TEST_MARKER();
\r
10601 295: mtCOVERAGE_TEST_MARKER();
\r
10606 300: /* Ensure the event queues start in the correct state. */
\r
10607 301: vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
\r
10608 BFD0397A 0010FC5E LW V0, 16(S8)
\r
10609 BFD0397E 6D28 ADDIU V0, V0, 16
\r
10610 BFD03980 0C82 MOVE A0, V0
\r
10611 BFD03982 457077E8 JALS vListInitialise
\r
10612 BFD03984 4570 SWM16 0x3, 0(SP)
\r
10613 BFD03986 0C00 NOP
\r
10614 302: vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
\r
10615 BFD03988 0010FC5E LW V0, 16(S8)
\r
10616 BFD0398C 00243042 ADDIU V0, V0, 36
\r
10617 BFD03990 0C82 MOVE A0, V0
\r
10618 BFD03992 457077E8 JALS vListInitialise
\r
10619 BFD03994 4570 SWM16 0x3, 0(SP)
\r
10620 BFD03996 0C00 NOP
\r
10623 305: taskEXIT_CRITICAL();
\r
10624 BFD03998 40AA77E8 JALS vTaskExitCritical
\r
10625 BFD0399A 0C0040AA BNEZC T2, 0xBFD0519E
\r
10626 BFD0399C 0C00 NOP
\r
10628 307: /* A value is returned for calling semantic consistency with previous
\r
10629 308: versions. */
\r
10630 309: return pdPASS;
\r
10631 BFD0399E ED01 LI V0, 1
\r
10633 BFD039A0 0FBE MOVE SP, S8
\r
10634 BFD039A2 4BE7 LW RA, 28(SP)
\r
10635 BFD039A4 4BC6 LW S8, 24(SP)
\r
10636 BFD039A6 4C11 ADDIU SP, SP, 32
\r
10637 BFD039A8 459F JR16 RA
\r
10638 BFD039AA 0C00 NOP
\r
10639 311: /*-----------------------------------------------------------*/
\r
10641 313: QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
\r
10643 BFD03DF4 4FED ADDIU SP, SP, -40
\r
10644 BFD03DF6 CBE9 SW RA, 36(SP)
\r
10645 BFD03DF8 CBC8 SW S8, 32(SP)
\r
10646 BFD03DFA 0FDD MOVE S8, SP
\r
10647 BFD03DFC 0028F89E SW A0, 40(S8)
\r
10648 BFD03E00 002CF8BE SW A1, 44(S8)
\r
10649 BFD03E04 0C46 MOVE V0, A2
\r
10650 BFD03E06 0030185E SB V0, 48(S8)
\r
10651 315: Queue_t *pxNewQueue;
\r
10652 316: size_t xQueueSizeInBytes;
\r
10653 317: QueueHandle_t xReturn = NULL;
\r
10654 BFD03E0A 0014F81E SW ZERO, 20(S8)
\r
10655 318: int8_t *pcAllocatedBuffer;
\r
10657 320: /* Remove compiler warnings about unused parameters should
\r
10658 321: configUSE_TRACE_FACILITY not be set to 1. */
\r
10659 322: ( void ) ucQueueType;
\r
10661 324: configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
\r
10662 BFD03E0E 0028FC5E LW V0, 40(S8)
\r
10663 BFD03E12 000940A2 BNEZC V0, 0xBFD03E28
\r
10664 BFD03E16 BFD141A2 LUI V0, 0xBFD1
\r
10665 BFD03E18 3082BFD1 LDC1 F30, 12418(S1)
\r
10666 BFD03E1A 9E3C3082 ADDIU A0, V0, -25028
\r
10667 BFD03E1C 30A09E3C LWC1 F17, 12448(GP)
\r
10668 BFD03E1E 014430A0 ADDIU A1, ZERO, 324
\r
10669 BFD03E22 4B7E77E8 JALS vAssertCalled
\r
10670 BFD03E24 4B7E LW K1, 120(SP)
\r
10671 BFD03E26 0C00 NOP
\r
10673 326: if( uxItemSize == ( UBaseType_t ) 0 )
\r
10674 BFD03E28 002CFC5E LW V0, 44(S8)
\r
10675 BFD03E2C 000440A2 BNEZC V0, 0xBFD03E38
\r
10677 328: /* There is not going to be a queue storage area. */
\r
10678 329: xQueueSizeInBytes = ( size_t ) 0;
\r
10679 BFD03E30 0010F81E SW ZERO, 16(S8)
\r
10680 BFD03E34 CC0A B 0xBFD03E4A
\r
10681 BFD03E36 0C00 NOP
\r
10685 333: /* The queue is one byte longer than asked for to make wrap checking
\r
10686 334: easier/faster. */
\r
10687 335: xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
10688 BFD03E38 0028FC7E LW V1, 40(S8)
\r
10689 BFD03E3C 002CFC5E LW V0, 44(S8)
\r
10690 BFD03E40 12100043 MUL V0, V1, V0
\r
10691 BFD03E42 6D201210 ADDI S0, S0, 27936
\r
10692 BFD03E44 6D20 ADDIU V0, V0, 1
\r
10693 BFD03E46 0010F85E SW V0, 16(S8)
\r
10696 338: /* Allocate the new queue structure and storage area. */
\r
10697 339: pcAllocatedBuffer = ( int8_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
\r
10698 BFD03E4A 0010FC5E LW V0, 16(S8)
\r
10699 BFD03E4E 00503042 ADDIU V0, V0, 80
\r
10700 BFD03E52 0C82 MOVE A0, V0
\r
10701 BFD03E54 111677E8 JALS pvPortMalloc
\r
10702 BFD03E56 0C001116 ADDI T0, S6, 3072
\r
10703 BFD03E58 0C00 NOP
\r
10704 BFD03E5A 0018F85E SW V0, 24(S8)
\r
10706 341: if( pcAllocatedBuffer != NULL )
\r
10707 BFD03E5E 0018FC5E LW V0, 24(S8)
\r
10708 BFD03E62 002F40E2 BEQZC V0, 0xBFD03EC4
\r
10710 343: pxNewQueue = ( Queue_t * ) pcAllocatedBuffer; /*lint !e826 MISRA The buffer cannot be too small because it was dimensioned by sizeof( Queue_t ) + xQueueSizeInBytes. */
\r
10711 BFD03E66 0018FC5E LW V0, 24(S8)
\r
10712 BFD03E6A 001CF85E SW V0, 28(S8)
\r
10714 345: if( uxItemSize == ( UBaseType_t ) 0 )
\r
10715 BFD03E6E 002CFC5E LW V0, 44(S8)
\r
10716 BFD03E72 000740A2 BNEZC V0, 0xBFD03E84
\r
10718 347: /* No RAM was allocated for the queue storage area, but PC head
\r
10719 348: cannot be set to NULL because NULL is used as a key to say the queue
\r
10720 349: is used as a mutex. Therefore just set pcHead to point to the queue
\r
10721 350: as a benign value that is known to be within the memory map. */
\r
10722 351: pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
\r
10723 BFD03E76 001CFC7E LW V1, 28(S8)
\r
10724 BFD03E7A 001CFC5E LW V0, 28(S8)
\r
10725 BFD03E7E E9A0 SW V1, 0(V0)
\r
10726 BFD03E80 CC08 B 0xBFD03E92
\r
10727 BFD03E82 0C00 NOP
\r
10731 355: /* Jump past the queue structure to find the location of the queue
\r
10732 356: storage area - adding the padding bytes to get a better alignment. */
\r
10733 357: pxNewQueue->pcHead = pcAllocatedBuffer + sizeof( Queue_t );
\r
10734 BFD03E84 0018FC5E LW V0, 24(S8)
\r
10735 BFD03E88 00503062 ADDIU V1, V0, 80
\r
10736 BFD03E8C 001CFC5E LW V0, 28(S8)
\r
10737 BFD03E90 E9A0 SW V1, 0(V0)
\r
10740 360: /* Initialise the queue members as described above where the queue type
\r
10741 361: is defined. */
\r
10742 362: pxNewQueue->uxLength = uxQueueLength;
\r
10743 BFD03E92 001CFC5E LW V0, 28(S8)
\r
10744 BFD03E96 0028FC7E LW V1, 40(S8)
\r
10745 BFD03E9A E9AF SW V1, 60(V0)
\r
10746 363: pxNewQueue->uxItemSize = uxItemSize;
\r
10747 BFD03E9C 001CFC5E LW V0, 28(S8)
\r
10748 BFD03EA0 002CFC7E LW V1, 44(S8)
\r
10749 BFD03EA4 0040F862 SW V1, 64(V0)
\r
10750 364: ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
\r
10751 BFD03EA8 001CFC9E LW A0, 28(S8)
\r
10752 BFD03EAC EE81 LI A1, 1
\r
10753 BFD03EAE 1C4677E8 JALS xQueueGenericReset
\r
10754 BFD03EB0 0C001C46 LB V0, 3072(A2)
\r
10755 BFD03EB2 0C00 NOP
\r
10757 366: #if ( configUSE_TRACE_FACILITY == 1 )
\r
10759 368: pxNewQueue->ucQueueType = ucQueueType;
\r
10761 370: #endif /* configUSE_TRACE_FACILITY */
\r
10763 372: #if( configUSE_QUEUE_SETS == 1 )
\r
10765 374: pxNewQueue->pxQueueSetContainer = NULL;
\r
10766 BFD03EB4 001CFC5E LW V0, 28(S8)
\r
10767 BFD03EB8 004CF802 SW ZERO, 76(V0)
\r
10769 376: #endif /* configUSE_QUEUE_SETS */
\r
10771 378: traceQUEUE_CREATE( pxNewQueue );
\r
10772 379: xReturn = pxNewQueue;
\r
10773 BFD03EBC 001CFC5E LW V0, 28(S8)
\r
10774 BFD03EC0 0014F85E SW V0, 20(S8)
\r
10778 383: mtCOVERAGE_TEST_MARKER();
\r
10781 386: configASSERT( xReturn );
\r
10782 BFD03EC4 0014FC5E LW V0, 20(S8)
\r
10783 BFD03EC8 000940A2 BNEZC V0, 0xBFD03EDE
\r
10784 BFD03ECC BFD141A2 LUI V0, 0xBFD1
\r
10785 BFD03ECE 3082BFD1 LDC1 F30, 12418(S1)
\r
10786 BFD03ED0 9E3C3082 ADDIU A0, V0, -25028
\r
10787 BFD03ED2 30A09E3C LWC1 F17, 12448(GP)
\r
10788 BFD03ED4 018230A0 ADDIU A1, ZERO, 386
\r
10789 BFD03ED8 4B7E77E8 JALS vAssertCalled
\r
10790 BFD03EDA 4B7E LW K1, 120(SP)
\r
10791 BFD03EDC 0C00 NOP
\r
10793 388: return xReturn;
\r
10794 BFD03EDE 0014FC5E LW V0, 20(S8)
\r
10796 BFD03EE2 0FBE MOVE SP, S8
\r
10797 BFD03EE4 4BE9 LW RA, 36(SP)
\r
10798 BFD03EE6 4BC8 LW S8, 32(SP)
\r
10799 BFD03EE8 4C15 ADDIU SP, SP, 40
\r
10800 BFD03EEA 459F JR16 RA
\r
10801 BFD03EEC 0C00 NOP
\r
10802 390: /*-----------------------------------------------------------*/
\r
10804 392: #if ( configUSE_MUTEXES == 1 )
\r
10806 394: QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
\r
10808 BFD05958 4FF1 ADDIU SP, SP, -32
\r
10809 BFD0595A CBE7 SW RA, 28(SP)
\r
10810 BFD0595C CBC6 SW S8, 24(SP)
\r
10811 BFD0595E 0FDD MOVE S8, SP
\r
10812 BFD05960 0C44 MOVE V0, A0
\r
10813 BFD05962 0020185E SB V0, 32(S8)
\r
10814 BFD05964 EE500020 AND SP, ZERO, AT
\r
10815 396: Queue_t *pxNewQueue;
\r
10817 398: /* Prevent compiler warnings about unused parameters if
\r
10818 399: configUSE_TRACE_FACILITY does not equal 1. */
\r
10819 400: ( void ) ucQueueType;
\r
10821 402: /* Allocate the new queue structure. */
\r
10822 403: pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );
\r
10823 BFD05966 EE50 LI A0, 80
\r
10824 BFD05968 111677E8 JALS pvPortMalloc
\r
10825 BFD0596A 0C001116 ADDI T0, S6, 3072
\r
10826 BFD0596C 0C00 NOP
\r
10827 BFD0596E 0010F85E SW V0, 16(S8)
\r
10828 404: if( pxNewQueue != NULL )
\r
10829 BFD05972 0010FC5E LW V0, 16(S8)
\r
10830 BFD05976 003C40E2 BEQZC V0, 0xBFD059F2
\r
10832 406: /* Information required for priority inheritance. */
\r
10833 407: pxNewQueue->pxMutexHolder = NULL;
\r
10834 BFD0597A 0010FC5E LW V0, 16(S8)
\r
10835 BFD0597E E821 SW S0, 4(V0)
\r
10836 408: pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
\r
10837 BFD05980 0010FC5E LW V0, 16(S8)
\r
10838 BFD05984 E820 SW S0, 0(V0)
\r
10840 410: /* Queues used as a mutex no data is actually copied into or out
\r
10841 411: of the queue. */
\r
10842 412: pxNewQueue->pcWriteTo = NULL;
\r
10843 BFD05986 0010FC5E LW V0, 16(S8)
\r
10844 BFD0598A E822 SW S0, 8(V0)
\r
10845 413: pxNewQueue->u.pcReadFrom = NULL;
\r
10846 BFD0598C 0010FC5E LW V0, 16(S8)
\r
10847 BFD05990 E823 SW S0, 12(V0)
\r
10849 415: /* Each mutex has a length of 1 (like a binary semaphore) and
\r
10850 416: an item size of 0 as nothing is actually copied into or out
\r
10851 417: of the mutex. */
\r
10852 418: pxNewQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
\r
10853 BFD05992 0010FC5E LW V0, 16(S8)
\r
10854 BFD05996 E82E SW S0, 56(V0)
\r
10855 419: pxNewQueue->uxLength = ( UBaseType_t ) 1U;
\r
10856 BFD05998 0010FC5E LW V0, 16(S8)
\r
10857 BFD0599C ED81 LI V1, 1
\r
10858 BFD0599E E9AF SW V1, 60(V0)
\r
10859 420: pxNewQueue->uxItemSize = ( UBaseType_t ) 0U;
\r
10860 BFD059A0 0010FC5E LW V0, 16(S8)
\r
10861 BFD059A4 0040F802 SW ZERO, 64(V0)
\r
10862 421: pxNewQueue->xRxLock = queueUNLOCKED;
\r
10863 BFD059A8 0010FC5E LW V0, 16(S8)
\r
10864 BFD059AC EDFF LI V1, -1
\r
10865 BFD059AE 0044F862 SW V1, 68(V0)
\r
10866 422: pxNewQueue->xTxLock = queueUNLOCKED;
\r
10867 BFD059B2 0010FC5E LW V0, 16(S8)
\r
10868 BFD059B6 EDFF LI V1, -1
\r
10869 BFD059B8 0048F862 SW V1, 72(V0)
\r
10871 424: #if ( configUSE_TRACE_FACILITY == 1 )
\r
10873 426: pxNewQueue->ucQueueType = ucQueueType;
\r
10877 430: #if ( configUSE_QUEUE_SETS == 1 )
\r
10879 432: pxNewQueue->pxQueueSetContainer = NULL;
\r
10880 BFD059BC 0010FC5E LW V0, 16(S8)
\r
10881 BFD059C0 004CF802 SW ZERO, 76(V0)
\r
10885 436: /* Ensure the event queues start with the correct state. */
\r
10886 437: vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );
\r
10887 BFD059C4 0010FC5E LW V0, 16(S8)
\r
10888 BFD059C8 6D28 ADDIU V0, V0, 16
\r
10889 BFD059CA 0C82 MOVE A0, V0
\r
10890 BFD059CC 457077E8 JALS vListInitialise
\r
10891 BFD059CE 4570 SWM16 0x3, 0(SP)
\r
10892 BFD059D0 0C00 NOP
\r
10893 438: vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );
\r
10894 BFD059D2 0010FC5E LW V0, 16(S8)
\r
10895 BFD059D6 00243042 ADDIU V0, V0, 36
\r
10896 BFD059DA 0C82 MOVE A0, V0
\r
10897 BFD059DC 457077E8 JALS vListInitialise
\r
10898 BFD059DE 4570 SWM16 0x3, 0(SP)
\r
10899 BFD059E0 0C00 NOP
\r
10901 440: traceCREATE_MUTEX( pxNewQueue );
\r
10903 442: /* Start with the semaphore in the expected state. */
\r
10904 443: ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
\r
10905 BFD059E2 0010FC9E LW A0, 16(S8)
\r
10906 BFD059E6 0CA0 MOVE A1, ZERO
\r
10907 BFD059E8 0CC0 MOVE A2, ZERO
\r
10908 BFD059EA 0CE0 MOVE A3, ZERO
\r
10909 BFD059EC 06A277E8 JALS xQueueGenericSend
\r
10910 BFD059EE 06A2 ADDU A1, S1, V0
\r
10911 BFD059F0 0C00 NOP
\r
10915 447: traceCREATE_MUTEX_FAILED();
\r
10918 450: configASSERT( pxNewQueue );
\r
10919 BFD059F2 0010FC5E LW V0, 16(S8)
\r
10920 BFD059F6 000940A2 BNEZC V0, 0xBFD05A0C
\r
10921 BFD059FA BFD141A2 LUI V0, 0xBFD1
\r
10922 BFD059FC 3082BFD1 LDC1 F30, 12418(S1)
\r
10923 BFD059FE 9E3C3082 ADDIU A0, V0, -25028
\r
10924 BFD05A00 30A09E3C LWC1 F17, 12448(GP)
\r
10925 BFD05A02 01C230A0 ADDIU A1, ZERO, 450
\r
10926 BFD05A06 4B7E77E8 JALS vAssertCalled
\r
10927 BFD05A08 4B7E LW K1, 120(SP)
\r
10928 BFD05A0A 0C00 NOP
\r
10929 451: return pxNewQueue;
\r
10930 BFD05A0C 0010FC5E LW V0, 16(S8)
\r
10932 BFD05A10 0FBE MOVE SP, S8
\r
10933 BFD05A12 4BE7 LW RA, 28(SP)
\r
10934 BFD05A14 4BC6 LW S8, 24(SP)
\r
10935 BFD05A16 4C11 ADDIU SP, SP, 32
\r
10936 BFD05A18 459F JR16 RA
\r
10937 BFD05A1A 0C00 NOP
\r
10939 454: #endif /* configUSE_MUTEXES */
\r
10940 455: /*-----------------------------------------------------------*/
\r
10942 457: #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
\r
10944 459: void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
\r
10946 461: void *pxReturn;
\r
10948 463: /* This function is called by xSemaphoreGetMutexHolder(), and should not
\r
10949 464: be called directly. Note: This is a good way of determining if the
\r
10950 465: calling task is the mutex holder, but not a good way of determining the
\r
10951 466: identity of the mutex holder, as the holder may change between the
\r
10952 467: following critical section exiting and the function returning. */
\r
10953 468: taskENTER_CRITICAL();
\r
10955 470: if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
\r
10957 472: pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
\r
10961 476: pxReturn = NULL;
\r
10964 479: taskEXIT_CRITICAL();
\r
10966 481: return pxReturn;
\r
10967 482: } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
\r
10970 485: /*-----------------------------------------------------------*/
\r
10972 487: #if ( configUSE_RECURSIVE_MUTEXES == 1 )
\r
10974 489: BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
\r
10976 BFD06AD0 4FED ADDIU SP, SP, -40
\r
10977 BFD06AD2 CBE9 SW RA, 36(SP)
\r
10978 BFD06AD4 CBC8 SW S8, 32(SP)
\r
10979 BFD06AD6 CA07 SW S0, 28(SP)
\r
10980 BFD06AD8 0FDD MOVE S8, SP
\r
10981 BFD06ADA 0028F89E SW A0, 40(S8)
\r
10982 491: BaseType_t xReturn;
\r
10983 492: Queue_t * const pxMutex = ( Queue_t * ) xMutex;
\r
10984 BFD06ADE 0028FC5E LW V0, 40(S8)
\r
10985 BFD06AE2 0014F85E SW V0, 20(S8)
\r
10987 494: configASSERT( pxMutex );
\r
10988 BFD06AE6 0014FC5E LW V0, 20(S8)
\r
10989 BFD06AEA 000940A2 BNEZC V0, 0xBFD06B00
\r
10990 BFD06AEE BFD141A2 LUI V0, 0xBFD1
\r
10991 BFD06AF0 3082BFD1 LDC1 F30, 12418(S1)
\r
10992 BFD06AF2 9E3C3082 ADDIU A0, V0, -25028
\r
10993 BFD06AF4 30A09E3C LWC1 F17, 12448(GP)
\r
10994 BFD06AF6 01EE30A0 ADDIU A1, ZERO, 494
\r
10995 BFD06AFA 4B7E77E8 JALS vAssertCalled
\r
10996 BFD06AFC 4B7E LW K1, 120(SP)
\r
10997 BFD06AFE 0C00 NOP
\r
10999 496: /* If this is the task that holds the mutex then pxMutexHolder will not
\r
11000 497: change outside of this task. If this task does not hold the mutex then
\r
11001 498: pxMutexHolder can never coincidentally equal the tasks handle, and as
\r
11002 499: this is the only condition we are interested in it does not matter if
\r
11003 500: pxMutexHolder is accessed simultaneously by another task. Therefore no
\r
11004 501: mutual exclusion is required to test the pxMutexHolder variable. */
\r
11005 502: if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
\r
11006 BFD06B00 0014FC5E LW V0, 20(S8)
\r
11007 BFD06B04 6821 LW S0, 4(V0)
\r
11008 BFD06B06 4F0277E8 JALS xTaskGetCurrentTaskHandle
\r
11009 BFD06B08 4F02 ADDIU T8, T8, 1
\r
11010 BFD06B0A 0C00 NOP
\r
11011 BFD06B0C 001AB450 BNE S0, V0, 0xBFD06B44
\r
11012 BFD06B0E 0C00001A SLL ZERO, K0, 1
\r
11013 BFD06B10 0C00 NOP
\r
11015 504: traceGIVE_MUTEX_RECURSIVE( pxMutex );
\r
11017 506: /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
\r
11018 507: the task handle, therefore no underflow check is required. Also,
\r
11019 508: uxRecursiveCallCount is only modified by the mutex holder, and as
\r
11020 509: there can only be one, no mutual exclusion is required to modify the
\r
11021 510: uxRecursiveCallCount member. */
\r
11022 511: ( pxMutex->u.uxRecursiveCallCount )--;
\r
11023 BFD06B12 0014FC5E LW V0, 20(S8)
\r
11024 BFD06B16 6923 LW V0, 12(V0)
\r
11025 BFD06B18 6DAE ADDIU V1, V0, -1
\r
11026 BFD06B1A 0014FC5E LW V0, 20(S8)
\r
11027 BFD06B1E E9A3 SW V1, 12(V0)
\r
11029 513: /* Have we unwound the call count? */
\r
11030 514: if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
\r
11031 BFD06B20 0014FC5E LW V0, 20(S8)
\r
11032 BFD06B24 6923 LW V0, 12(V0)
\r
11033 BFD06B26 000840A2 BNEZC V0, 0xBFD06B3A
\r
11035 516: /* Return the mutex. This will automatically unblock any other
\r
11036 517: task that might be waiting to access the mutex. */
\r
11037 518: ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
\r
11038 BFD06B2A 0014FC9E LW A0, 20(S8)
\r
11039 BFD06B2E 0CA0 MOVE A1, ZERO
\r
11040 BFD06B30 0CC0 MOVE A2, ZERO
\r
11041 BFD06B32 0CE0 MOVE A3, ZERO
\r
11042 BFD06B34 06A277E8 JALS xQueueGenericSend
\r
11043 BFD06B36 06A2 ADDU A1, S1, V0
\r
11044 BFD06B38 0C00 NOP
\r
11048 522: mtCOVERAGE_TEST_MARKER();
\r
11051 525: xReturn = pdPASS;
\r
11052 BFD06B3A ED01 LI V0, 1
\r
11053 BFD06B3C 0010F85E SW V0, 16(S8)
\r
11054 BFD06B40 CC03 B 0xBFD06B48
\r
11055 BFD06B42 0C00 NOP
\r
11059 529: /* The mutex cannot be given because the calling task is not the
\r
11061 531: xReturn = pdFAIL;
\r
11062 BFD06B44 0010F81E SW ZERO, 16(S8)
\r
11064 533: traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
\r
11067 536: return xReturn;
\r
11068 BFD06B48 0010FC5E LW V0, 16(S8)
\r
11070 BFD06B4C 0FBE MOVE SP, S8
\r
11071 BFD06B4E 4BE9 LW RA, 36(SP)
\r
11072 BFD06B50 4BC8 LW S8, 32(SP)
\r
11073 BFD06B52 4A07 LW S0, 28(SP)
\r
11074 BFD06B54 4C15 ADDIU SP, SP, 40
\r
11075 BFD06B56 459F JR16 RA
\r
11076 BFD06B58 0C00 NOP
\r
11078 539: #endif /* configUSE_RECURSIVE_MUTEXES */
\r
11079 540: /*-----------------------------------------------------------*/
\r
11081 542: #if ( configUSE_RECURSIVE_MUTEXES == 1 )
\r
11083 544: BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
\r
11085 BFD063CC 4FED ADDIU SP, SP, -40
\r
11086 BFD063CE CBE9 SW RA, 36(SP)
\r
11087 BFD063D0 CBC8 SW S8, 32(SP)
\r
11088 BFD063D2 CA07 SW S0, 28(SP)
\r
11089 BFD063D4 0FDD MOVE S8, SP
\r
11090 BFD063D6 0028F89E SW A0, 40(S8)
\r
11091 BFD063DA 002CF8BE SW A1, 44(S8)
\r
11092 546: BaseType_t xReturn;
\r
11093 547: Queue_t * const pxMutex = ( Queue_t * ) xMutex;
\r
11094 BFD063DE 0028FC5E LW V0, 40(S8)
\r
11095 BFD063E2 0014F85E SW V0, 20(S8)
\r
11097 549: configASSERT( pxMutex );
\r
11098 BFD063E6 0014FC5E LW V0, 20(S8)
\r
11099 BFD063EA 000940A2 BNEZC V0, 0xBFD06400
\r
11100 BFD063EE BFD141A2 LUI V0, 0xBFD1
\r
11101 BFD063F0 3082BFD1 LDC1 F30, 12418(S1)
\r
11102 BFD063F2 9E3C3082 ADDIU A0, V0, -25028
\r
11103 BFD063F4 30A09E3C LWC1 F17, 12448(GP)
\r
11104 BFD063F6 022530A0 ADDIU A1, ZERO, 549
\r
11105 BFD063FA 4B7E77E8 JALS vAssertCalled
\r
11106 BFD063FC 4B7E LW K1, 120(SP)
\r
11107 BFD063FE 0C00 NOP
\r
11109 551: /* Comments regarding mutual exclusion as per those within
\r
11110 552: xQueueGiveMutexRecursive(). */
\r
11112 554: traceTAKE_MUTEX_RECURSIVE( pxMutex );
\r
11114 556: if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
\r
11115 BFD06400 0014FC5E LW V0, 20(S8)
\r
11116 BFD06404 6821 LW S0, 4(V0)
\r
11117 BFD06406 4F0277E8 JALS xTaskGetCurrentTaskHandle
\r
11118 BFD06408 4F02 ADDIU T8, T8, 1
\r
11119 BFD0640A 0C00 NOP
\r
11120 BFD0640C 000DB450 BNE S0, V0, 0xBFD0642A
\r
11121 BFD0640E 0C00000D SLL ZERO, T5, 1
\r
11122 BFD06410 0C00 NOP
\r
11124 558: ( pxMutex->u.uxRecursiveCallCount )++;
\r
11125 BFD06412 0014FC5E LW V0, 20(S8)
\r
11126 BFD06416 6923 LW V0, 12(V0)
\r
11127 BFD06418 6DA0 ADDIU V1, V0, 1
\r
11128 BFD0641A 0014FC5E LW V0, 20(S8)
\r
11129 BFD0641E E9A3 SW V1, 12(V0)
\r
11130 559: xReturn = pdPASS;
\r
11131 BFD06420 ED01 LI V0, 1
\r
11132 BFD06422 0010F85E SW V0, 16(S8)
\r
11133 BFD06426 CC19 B 0xBFD0645A
\r
11134 BFD06428 0C00 NOP
\r
11138 563: xReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );
\r
11139 BFD0642A 0014FC9E LW A0, 20(S8)
\r
11140 BFD0642E 0CA0 MOVE A1, ZERO
\r
11141 BFD06430 002CFCDE LW A2, 44(S8)
\r
11142 BFD06434 0CE0 MOVE A3, ZERO
\r
11143 BFD06436 081E77E8 JALS xQueueGenericReceive
\r
11144 BFD06438 081E LBU S0, 14(S1)
\r
11145 BFD0643A 0C00 NOP
\r
11146 BFD0643C 0010F85E SW V0, 16(S8)
\r
11148 565: /* pdPASS will only be returned if the mutex was successfully
\r
11149 566: obtained. The calling task may have entered the Blocked state
\r
11150 567: before reaching here. */
\r
11151 568: if( xReturn == pdPASS )
\r
11152 BFD06440 0010FC7E LW V1, 16(S8)
\r
11153 BFD06444 ED01 LI V0, 1
\r
11154 BFD06446 0008B443 BNE V1, V0, 0xBFD0645A
\r
11155 BFD06448 0C000008 SLL ZERO, T0, 1
\r
11156 BFD0644A 0C00 NOP
\r
11158 570: ( pxMutex->u.uxRecursiveCallCount )++;
\r
11159 BFD0644C 0014FC5E LW V0, 20(S8)
\r
11160 BFD06450 6923 LW V0, 12(V0)
\r
11161 BFD06452 6DA0 ADDIU V1, V0, 1
\r
11162 BFD06454 0014FC5E LW V0, 20(S8)
\r
11163 BFD06458 E9A3 SW V1, 12(V0)
\r
11167 574: traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
\r
11171 578: return xReturn;
\r
11172 BFD0645A 0010FC5E LW V0, 16(S8)
\r
11174 BFD0645E 0FBE MOVE SP, S8
\r
11175 BFD06460 4BE9 LW RA, 36(SP)
\r
11176 BFD06462 4BC8 LW S8, 32(SP)
\r
11177 BFD06464 4A07 LW S0, 28(SP)
\r
11178 BFD06466 4C15 ADDIU SP, SP, 40
\r
11179 BFD06468 459F JR16 RA
\r
11180 BFD0646A 0C00 NOP
\r
11182 581: #endif /* configUSE_RECURSIVE_MUTEXES */
\r
11183 582: /*-----------------------------------------------------------*/
\r
11185 584: #if ( configUSE_COUNTING_SEMAPHORES == 1 )
\r
11187 586: QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
\r
11189 BFD0650C 4FF1 ADDIU SP, SP, -32
\r
11190 BFD0650E CBE7 SW RA, 28(SP)
\r
11191 BFD06510 CBC6 SW S8, 24(SP)
\r
11192 BFD06512 0FDD MOVE S8, SP
\r
11193 BFD06514 0020F89E SW A0, 32(S8)
\r
11194 BFD06518 0024F8BE SW A1, 36(S8)
\r
11195 588: QueueHandle_t xHandle;
\r
11197 590: configASSERT( uxMaxCount != 0 );
\r
11198 BFD0651C 0020FC5E LW V0, 32(S8)
\r
11199 BFD06520 000940A2 BNEZC V0, 0xBFD06536
\r
11200 BFD06524 BFD141A2 LUI V0, 0xBFD1
\r
11201 BFD06526 3082BFD1 LDC1 F30, 12418(S1)
\r
11202 BFD06528 9E3C3082 ADDIU A0, V0, -25028
\r
11203 BFD0652A 30A09E3C LWC1 F17, 12448(GP)
\r
11204 BFD0652C 024E30A0 ADDIU A1, ZERO, 590
\r
11205 BFD06530 4B7E77E8 JALS vAssertCalled
\r
11206 BFD06532 4B7E LW K1, 120(SP)
\r
11207 BFD06534 0C00 NOP
\r
11208 591: configASSERT( uxInitialCount <= uxMaxCount );
\r
11209 BFD06536 0024FC7E LW V1, 36(S8)
\r
11210 BFD0653A 0020FC5E LW V0, 32(S8)
\r
11211 BFD0653E 13900062 SLTU V0, V0, V1
\r
11212 BFD06540 40E21390 ADDI GP, S0, 16610
\r
11213 BFD06542 000940E2 BEQZC V0, 0xBFD06558
\r
11214 BFD06546 BFD141A2 LUI V0, 0xBFD1
\r
11215 BFD06548 3082BFD1 LDC1 F30, 12418(S1)
\r
11216 BFD0654A 9E3C3082 ADDIU A0, V0, -25028
\r
11217 BFD0654C 30A09E3C LWC1 F17, 12448(GP)
\r
11218 BFD0654E 024F30A0 ADDIU A1, ZERO, 591
\r
11219 BFD06552 4B7E77E8 JALS vAssertCalled
\r
11220 BFD06554 4B7E LW K1, 120(SP)
\r
11221 BFD06556 0C00 NOP
\r
11223 593: xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
\r
11224 BFD06558 0020FC9E LW A0, 32(S8)
\r
11225 BFD0655C 0CA0 MOVE A1, ZERO
\r
11226 BFD0655E EF02 LI A2, 2
\r
11227 BFD06560 1EFA77E8 JALS xQueueGenericCreate
\r
11228 BFD06562 0C001EFA LB S7, 3072(K0)
\r
11229 BFD06564 0C00 NOP
\r
11230 BFD06566 0010F85E SW V0, 16(S8)
\r
11232 595: if( xHandle != NULL )
\r
11233 BFD0656A 0010FC5E LW V0, 16(S8)
\r
11234 BFD0656E 000540E2 BEQZC V0, 0xBFD0657C
\r
11236 597: ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
\r
11237 BFD06572 0010FC5E LW V0, 16(S8)
\r
11238 BFD06576 0024FC7E LW V1, 36(S8)
\r
11239 BFD0657A E9AE SW V1, 56(V0)
\r
11241 599: traceCREATE_COUNTING_SEMAPHORE();
\r
11245 603: traceCREATE_COUNTING_SEMAPHORE_FAILED();
\r
11248 606: configASSERT( xHandle );
\r
11249 BFD0657C 0010FC5E LW V0, 16(S8)
\r
11250 BFD06580 000940A2 BNEZC V0, 0xBFD06596
\r
11251 BFD06584 BFD141A2 LUI V0, 0xBFD1
\r
11252 BFD06586 3082BFD1 LDC1 F30, 12418(S1)
\r
11253 BFD06588 9E3C3082 ADDIU A0, V0, -25028
\r
11254 BFD0658A 30A09E3C LWC1 F17, 12448(GP)
\r
11255 BFD0658C 025E30A0 ADDIU A1, ZERO, 606
\r
11256 BFD06590 4B7E77E8 JALS vAssertCalled
\r
11257 BFD06592 4B7E LW K1, 120(SP)
\r
11258 BFD06594 0C00 NOP
\r
11259 607: return xHandle;
\r
11260 BFD06596 0010FC5E LW V0, 16(S8)
\r
11262 BFD0659A 0FBE MOVE SP, S8
\r
11263 BFD0659C 4BE7 LW RA, 28(SP)
\r
11264 BFD0659E 4BC6 LW S8, 24(SP)
\r
11265 BFD065A0 4C11 ADDIU SP, SP, 32
\r
11266 BFD065A2 459F JR16 RA
\r
11267 BFD065A4 0C00 NOP
\r
11269 610: #endif /* configUSE_COUNTING_SEMAPHORES */
\r
11270 611: /*-----------------------------------------------------------*/
\r
11272 613: BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
\r
11274 BFD00D44 4FE1 ADDIU SP, SP, -64
\r
11275 BFD00D46 CBEF SW RA, 60(SP)
\r
11276 BFD00D48 CBCE SW S8, 56(SP)
\r
11277 BFD00D4A 0FDD MOVE S8, SP
\r
11278 BFD00D4C 0040F89E SW A0, 64(S8)
\r
11279 BFD00D50 0044F8BE SW A1, 68(S8)
\r
11280 BFD00D54 0048F8DE SW A2, 72(S8)
\r
11281 BFD00D58 004CF8FE SW A3, 76(S8)
\r
11282 615: BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
\r
11283 BFD00D5C 0010F81E SW ZERO, 16(S8)
\r
11284 616: TimeOut_t xTimeOut;
\r
11285 617: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
11286 BFD00D60 0040FC5E LW V0, 64(S8)
\r
11287 BFD00D64 0014F85E SW V0, 20(S8)
\r
11289 619: configASSERT( pxQueue );
\r
11290 BFD00D68 0014FC5E LW V0, 20(S8)
\r
11291 BFD00D6C 000940A2 BNEZC V0, 0xBFD00D82
\r
11292 BFD00D70 BFD141A2 LUI V0, 0xBFD1
\r
11293 BFD00D72 3082BFD1 LDC1 F30, 12418(S1)
\r
11294 BFD00D74 9E3C3082 ADDIU A0, V0, -25028
\r
11295 BFD00D76 30A09E3C LWC1 F17, 12448(GP)
\r
11296 BFD00D78 026B30A0 ADDIU A1, ZERO, 619
\r
11297 BFD00D7C 4B7E77E8 JALS vAssertCalled
\r
11298 BFD00D7E 4B7E LW K1, 120(SP)
\r
11299 BFD00D80 0C00 NOP
\r
11300 620: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
\r
11301 BFD00D82 0044FC5E LW V0, 68(S8)
\r
11302 BFD00D86 000640A2 BNEZC V0, 0xBFD00D96
\r
11303 BFD00D8A 0014FC5E LW V0, 20(S8)
\r
11304 BFD00D8E 0040FC42 LW V0, 64(V0)
\r
11305 BFD00D92 000340A2 BNEZC V0, 0xBFD00D9C
\r
11306 BFD00D96 ED01 LI V0, 1
\r
11307 BFD00D98 CC02 B 0xBFD00D9E
\r
11308 BFD00D9A 0C00 NOP
\r
11309 BFD00D9C 0C40 MOVE V0, ZERO
\r
11310 BFD00D9E 000940A2 BNEZC V0, 0xBFD00DB4
\r
11311 BFD00DA2 BFD141A2 LUI V0, 0xBFD1
\r
11312 BFD00DA4 3082BFD1 LDC1 F30, 12418(S1)
\r
11313 BFD00DA6 9E3C3082 ADDIU A0, V0, -25028
\r
11314 BFD00DA8 30A09E3C LWC1 F17, 12448(GP)
\r
11315 BFD00DAA 026C30A0 ADDIU A1, ZERO, 620
\r
11316 BFD00DAE 4B7E77E8 JALS vAssertCalled
\r
11317 BFD00DB0 4B7E LW K1, 120(SP)
\r
11318 BFD00DB2 0C00 NOP
\r
11319 621: configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
\r
11320 BFD00DB4 004CFC7E LW V1, 76(S8)
\r
11321 BFD00DB8 ED02 LI V0, 2
\r
11322 BFD00DBA 0008B443 BNE V1, V0, 0xBFD00DCE
\r
11323 BFD00DBC 0C000008 SLL ZERO, T0, 1
\r
11324 BFD00DBE 0C00 NOP
\r
11325 BFD00DC0 0014FC5E LW V0, 20(S8)
\r
11326 BFD00DC4 69AF LW V1, 60(V0)
\r
11327 BFD00DC6 ED01 LI V0, 1
\r
11328 BFD00DC8 0004B443 BNE V1, V0, 0xBFD00DD4
\r
11329 BFD00DCA 0C000004 SLL ZERO, A0, 1
\r
11330 BFD00DCC 0C00 NOP
\r
11331 BFD00DCE ED01 LI V0, 1
\r
11332 BFD00DD0 CC02 B 0xBFD00DD6
\r
11333 BFD00DD2 0C00 NOP
\r
11334 BFD00DD4 0C40 MOVE V0, ZERO
\r
11335 BFD00DD6 000940A2 BNEZC V0, 0xBFD00DEC
\r
11336 BFD00DDA BFD141A2 LUI V0, 0xBFD1
\r
11337 BFD00DDC 3082BFD1 LDC1 F30, 12418(S1)
\r
11338 BFD00DDE 9E3C3082 ADDIU A0, V0, -25028
\r
11339 BFD00DE0 30A09E3C LWC1 F17, 12448(GP)
\r
11340 BFD00DE2 026D30A0 ADDIU A1, ZERO, 621
\r
11341 BFD00DE6 4B7E77E8 JALS vAssertCalled
\r
11342 BFD00DE8 4B7E LW K1, 120(SP)
\r
11343 BFD00DEA 0C00 NOP
\r
11344 622: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
\r
11346 624: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
\r
11347 BFD00DEC 4A8E77E8 JALS xTaskGetSchedulerState
\r
11348 BFD00DEE 4A8E LW S4, 56(SP)
\r
11349 BFD00DF0 0C00 NOP
\r
11350 BFD00DF2 000440A2 BNEZC V0, 0xBFD00DFE
\r
11351 BFD00DF6 0048FC5E LW V0, 72(S8)
\r
11352 BFD00DFA 000340A2 BNEZC V0, 0xBFD00E04
\r
11353 BFD00DFE ED01 LI V0, 1
\r
11354 BFD00E00 CC02 B 0xBFD00E06
\r
11355 BFD00E02 0C00 NOP
\r
11356 BFD00E04 0C40 MOVE V0, ZERO
\r
11357 BFD00E06 000C40A2 BNEZC V0, 0xBFD00E22
\r
11358 BFD00E0A BFD141A2 LUI V0, 0xBFD1
\r
11359 BFD00E0C 3082BFD1 LDC1 F30, 12418(S1)
\r
11360 BFD00E0E 9E3C3082 ADDIU A0, V0, -25028
\r
11361 BFD00E10 30A09E3C LWC1 F17, 12448(GP)
\r
11362 BFD00E12 027030A0 ADDIU A1, ZERO, 624
\r
11363 BFD00E16 4B7E77E8 JALS vAssertCalled
\r
11364 BFD00E18 4B7E LW K1, 120(SP)
\r
11365 BFD00E1A 0C00 NOP
\r
11366 BFD00E1C CC02 B 0xBFD00E22
\r
11367 BFD00E1E 0C00 NOP
\r
11372 629: /* This function relaxes the coding standard somewhat to allow return
\r
11373 630: statements within the function itself. This is done in the interest
\r
11374 631: of execution time efficiency. */
\r
11377 634: taskENTER_CRITICAL();
\r
11378 BFD00E22 33B877E8 JALS vTaskEnterCritical
\r
11379 BFD00E24 0C0033B8 ADDIU SP, T8, 3072
\r
11380 BFD00E26 0C00 NOP
\r
11382 636: /* Is there room on the queue now? The running task must be the
\r
11383 637: highest priority task wanting to access the queue. If the head item
\r
11384 638: in the queue is to be overwritten then it does not matter if the
\r
11385 639: queue is full. */
\r
11386 640: if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
\r
11387 BFD00E28 0014FC5E LW V0, 20(S8)
\r
11388 BFD00E2C 69AE LW V1, 56(V0)
\r
11389 BFD00E2E 0014FC5E LW V0, 20(S8)
\r
11390 BFD00E32 692F LW V0, 60(V0)
\r
11391 BFD00E34 13900043 SLTU V0, V1, V0
\r
11392 BFD00E36 40A21390 ADDI GP, S0, 16546
\r
11393 BFD00E38 000640A2 BNEZC V0, 0xBFD00E48
\r
11394 BFD00E3C 004CFC7E LW V1, 76(S8)
\r
11395 BFD00E40 ED02 LI V0, 2
\r
11396 BFD00E42 006EB443 BNE V1, V0, 0xBFD00F22
\r
11397 BFD00E44 0C00006E SLL V1, T6, 1
\r
11398 BFD00E46 0C00 NOP
\r
11400 642: traceQUEUE_SEND( pxQueue );
\r
11401 643: xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
\r
11402 BFD00E48 0014FC9E LW A0, 20(S8)
\r
11403 BFD00E4C 0044FCBE LW A1, 68(S8)
\r
11404 BFD00E50 004CFCDE LW A2, 76(S8)
\r
11405 BFD00E54 14E677E8 JALS prvCopyDataToQueue
\r
11406 BFD00E56 0C0014E6 LBU A3, 3072(A2)
\r
11407 BFD00E58 0C00 NOP
\r
11408 BFD00E5A 001CF85E SW V0, 28(S8)
\r
11410 645: #if ( configUSE_QUEUE_SETS == 1 )
\r
11412 647: if( pxQueue->pxQueueSetContainer != NULL )
\r
11413 BFD00E5E 0014FC5E LW V0, 20(S8)
\r
11414 BFD00E62 004CFC42 LW V0, 76(V0)
\r
11415 BFD00E66 001E40E2 BEQZC V0, 0xBFD00EA6
\r
11417 649: if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )
\r
11418 BFD00E6A 0014FC9E LW A0, 20(S8)
\r
11419 BFD00E6E 004CFCBE LW A1, 76(S8)
\r
11420 BFD00E72 21D877E8 JALS prvNotifyQueueSetContainer
\r
11421 BFD00E74 0C0021D8 LWC2 T6, 3072(T8)
\r
11422 BFD00E76 0C00 NOP
\r
11423 BFD00E78 0C62 MOVE V1, V0
\r
11424 BFD00E7A ED01 LI V0, 1
\r
11425 BFD00E7C 004BB443 BNE V1, V0, 0xBFD00F16
\r
11426 BFD00E7E 0C00004B SLL V0, T3, 1
\r
11427 BFD00E80 0C00 NOP
\r
11429 651: /* The queue is a member of a queue set, and posting
\r
11430 652: to the queue set caused a higher priority task to
\r
11431 653: unblock. A context switch is required. */
\r
11432 654: queueYIELD_IF_USING_PREEMPTION();
\r
11433 BFD00E82 4E1677E8 JALS ulPortGetCP0Cause
\r
11434 BFD00E84 4E16 ADDIU S0, S0, -5
\r
11435 BFD00E86 0C00 NOP
\r
11436 BFD00E88 0020F85E SW V0, 32(S8)
\r
11437 BFD00E8C 0020FC5E LW V0, 32(S8)
\r
11438 BFD00E90 01005042 ORI V0, V0, 256
\r
11439 BFD00E94 0020F85E SW V0, 32(S8)
\r
11440 BFD00E98 0020FC9E LW A0, 32(S8)
\r
11441 BFD00E9C 4E2677E8 JALS vPortSetCP0Cause
\r
11442 BFD00E9E 4E26 ADDIU S1, S1, 3
\r
11443 BFD00EA0 0C00 NOP
\r
11444 BFD00EA2 CC39 B 0xBFD00F16
\r
11445 BFD00EA4 0C00 NOP
\r
11449 658: mtCOVERAGE_TEST_MARKER();
\r
11454 663: /* If there was a task waiting for data to arrive on the
\r
11455 664: queue then unblock it now. */
\r
11456 665: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
11457 BFD00EA6 0014FC5E LW V0, 20(S8)
\r
11458 BFD00EAA 6929 LW V0, 36(V0)
\r
11459 BFD00EAC 001F40E2 BEQZC V0, 0xBFD00EEE
\r
11461 667: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
\r
11462 BFD00EB0 0014FC5E LW V0, 20(S8)
\r
11463 BFD00EB4 00243042 ADDIU V0, V0, 36
\r
11464 BFD00EB8 0C82 MOVE A0, V0
\r
11465 BFD00EBA 22BC77E8 JALS xTaskRemoveFromEventList
\r
11466 BFD00EBC 0C0022BC LWC2 S5, 3072(GP)
\r
11467 BFD00EBE 0C00 NOP
\r
11468 BFD00EC0 0C62 MOVE V1, V0
\r
11469 BFD00EC2 ED01 LI V0, 1
\r
11470 BFD00EC4 0027B443 BNE V1, V0, 0xBFD00F16
\r
11471 BFD00EC6 0C000027 SLL AT, A3, 1
\r
11472 BFD00EC8 0C00 NOP
\r
11474 669: /* The unblocked task has a priority higher than
\r
11475 670: our own so yield immediately. Yes it is ok to
\r
11476 671: do this from within the critical section - the
\r
11477 672: kernel takes care of that. */
\r
11478 673: queueYIELD_IF_USING_PREEMPTION();
\r
11479 BFD00ECA 4E1677E8 JALS ulPortGetCP0Cause
\r
11480 BFD00ECC 4E16 ADDIU S0, S0, -5
\r
11481 BFD00ECE 0C00 NOP
\r
11482 BFD00ED0 0024F85E SW V0, 36(S8)
\r
11483 BFD00ED4 0024FC5E LW V0, 36(S8)
\r
11484 BFD00ED8 01005042 ORI V0, V0, 256
\r
11485 BFD00EDC 0024F85E SW V0, 36(S8)
\r
11486 BFD00EE0 0024FC9E LW A0, 36(S8)
\r
11487 BFD00EE4 4E2677E8 JALS vPortSetCP0Cause
\r
11488 BFD00EE6 4E26 ADDIU S1, S1, 3
\r
11489 BFD00EE8 0C00 NOP
\r
11490 BFD00EEA CC15 B 0xBFD00F16
\r
11491 BFD00EEC 0C00 NOP
\r
11495 677: mtCOVERAGE_TEST_MARKER();
\r
11498 680: else if( xYieldRequired != pdFALSE )
\r
11499 BFD00EEE 001CFC5E LW V0, 28(S8)
\r
11500 BFD00EF2 001040E2 BEQZC V0, 0xBFD00F16
\r
11502 682: /* This path is a special case that will only get
\r
11503 683: executed if the task was holding multiple mutexes
\r
11504 684: and the mutexes were given back in an order that is
\r
11505 685: different to that in which they were taken. */
\r
11506 686: queueYIELD_IF_USING_PREEMPTION();
\r
11507 BFD00EF6 4E1677E8 JALS ulPortGetCP0Cause
\r
11508 BFD00EF8 4E16 ADDIU S0, S0, -5
\r
11509 BFD00EFA 0C00 NOP
\r
11510 BFD00EFC 0028F85E SW V0, 40(S8)
\r
11511 BFD00F00 0028FC5E LW V0, 40(S8)
\r
11512 BFD00F04 01005042 ORI V0, V0, 256
\r
11513 BFD00F08 0028F85E SW V0, 40(S8)
\r
11514 BFD00F0C 0028FC9E LW A0, 40(S8)
\r
11515 BFD00F10 4E2677E8 JALS vPortSetCP0Cause
\r
11516 BFD00F12 4E26 ADDIU S1, S1, 3
\r
11517 BFD00F14 0C00 NOP
\r
11521 690: mtCOVERAGE_TEST_MARKER();
\r
11525 694: #else /* configUSE_QUEUE_SETS */
\r
11527 696: /* If there was a task waiting for data to arrive on the
\r
11528 697: queue then unblock it now. */
\r
11529 698: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
11531 700: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
\r
11533 702: /* The unblocked task has a priority higher than
\r
11534 703: our own so yield immediately. Yes it is ok to do
\r
11535 704: this from within the critical section - the kernel
\r
11536 705: takes care of that. */
\r
11537 706: queueYIELD_IF_USING_PREEMPTION();
\r
11541 710: mtCOVERAGE_TEST_MARKER();
\r
11544 713: else if( xYieldRequired != pdFALSE )
\r
11546 715: /* This path is a special case that will only get
\r
11547 716: executed if the task was holding multiple mutexes and
\r
11548 717: the mutexes were given back in an order that is
\r
11549 718: different to that in which they were taken. */
\r
11550 719: queueYIELD_IF_USING_PREEMPTION();
\r
11554 723: mtCOVERAGE_TEST_MARKER();
\r
11557 726: #endif /* configUSE_QUEUE_SETS */
\r
11559 728: taskEXIT_CRITICAL();
\r
11560 BFD00F16 40AA77E8 JALS vTaskExitCritical
\r
11561 BFD00F18 0C0040AA BNEZC T2, 0xBFD0271C
\r
11562 BFD00F1A 0C00 NOP
\r
11563 729: return pdPASS;
\r
11564 BFD00F1C ED01 LI V0, 1
\r
11565 BFD00F1E CC87 B 0xBFD0102E
\r
11566 BFD00F20 0C00 NOP
\r
11570 733: if( xTicksToWait == ( TickType_t ) 0 )
\r
11571 BFD00F22 0048FC5E LW V0, 72(S8)
\r
11572 BFD00F26 000640A2 BNEZC V0, 0xBFD00F36
\r
11574 735: /* The queue was full and no block time is specified (or
\r
11575 736: the block time has expired) so leave now. */
\r
11576 737: taskEXIT_CRITICAL();
\r
11577 BFD00F2A 40AA77E8 JALS vTaskExitCritical
\r
11578 BFD00F2C 0C0040AA BNEZC T2, 0xBFD02730
\r
11579 BFD00F2E 0C00 NOP
\r
11581 739: /* Return to the original privilege level before exiting
\r
11582 740: the function. */
\r
11583 741: traceQUEUE_SEND_FAILED( pxQueue );
\r
11584 742: return errQUEUE_FULL;
\r
11585 BFD00F30 0C40 MOVE V0, ZERO
\r
11586 BFD00F32 CC7D B 0xBFD0102E
\r
11587 BFD00F34 0C00 NOP
\r
11589 744: else if( xEntryTimeSet == pdFALSE )
\r
11590 BFD00F36 0010FC5E LW V0, 16(S8)
\r
11591 BFD00F3A 000940A2 BNEZC V0, 0xBFD00F50
\r
11593 746: /* The queue was full and a block time was specified so
\r
11594 747: configure the timeout structure. */
\r
11595 748: vTaskSetTimeOutState( &xTimeOut );
\r
11596 BFD00F3E 002C305E ADDIU V0, S8, 44
\r
11597 BFD00F42 0C82 MOVE A0, V0
\r
11598 BFD00F44 47A677E8 JALS vTaskSetTimeOutState
\r
11599 BFD00F48 0C00 NOP
\r
11600 749: xEntryTimeSet = pdTRUE;
\r
11601 BFD00F4A ED01 LI V0, 1
\r
11602 BFD00F4C 0010F85E SW V0, 16(S8)
\r
11606 753: /* Entry time was already set. */
\r
11607 754: mtCOVERAGE_TEST_MARKER();
\r
11611 758: taskEXIT_CRITICAL();
\r
11612 BFD00F50 40AA77E8 JALS vTaskExitCritical
\r
11613 BFD00F52 0C0040AA BNEZC T2, 0xBFD02756
\r
11614 BFD00F54 0C00 NOP
\r
11616 760: /* Interrupts and other tasks can send to and receive from the queue
\r
11617 761: now the critical section has been exited. */
\r
11619 763: vTaskSuspendAll();
\r
11620 BFD00F56 4EF477E8 JALS vTaskSuspendAll
\r
11621 BFD00F58 4EF4 ADDIU S7, S7, -6
\r
11622 BFD00F5A 0C00 NOP
\r
11623 764: prvLockQueue( pxQueue );
\r
11624 BFD00F5C 33B877E8 JALS vTaskEnterCritical
\r
11625 BFD00F5E 0C0033B8 ADDIU SP, T8, 3072
\r
11626 BFD00F60 0C00 NOP
\r
11627 BFD00F62 0014FC5E LW V0, 20(S8)
\r
11628 BFD00F66 0044FC62 LW V1, 68(V0)
\r
11629 BFD00F6A ED7F LI V0, -1
\r
11630 BFD00F6C 0005B443 BNE V1, V0, 0xBFD00F7A
\r
11631 BFD00F6E 0C000005 SLL ZERO, A1, 1
\r
11632 BFD00F70 0C00 NOP
\r
11633 BFD00F72 0014FC5E LW V0, 20(S8)
\r
11634 BFD00F76 0044F802 SW ZERO, 68(V0)
\r
11635 BFD00F7A 0014FC5E LW V0, 20(S8)
\r
11636 BFD00F7E 0048FC62 LW V1, 72(V0)
\r
11637 BFD00F82 ED7F LI V0, -1
\r
11638 BFD00F84 0005B443 BNE V1, V0, 0xBFD00F92
\r
11639 BFD00F86 0C000005 SLL ZERO, A1, 1
\r
11640 BFD00F88 0C00 NOP
\r
11641 BFD00F8A 0014FC5E LW V0, 20(S8)
\r
11642 BFD00F8E 0048F802 SW ZERO, 72(V0)
\r
11643 BFD00F92 40AA77E8 JALS vTaskExitCritical
\r
11644 BFD00F94 0C0040AA BNEZC T2, 0xBFD02798
\r
11645 BFD00F96 0C00 NOP
\r
11647 766: /* Update the timeout state to see if it has expired yet. */
\r
11648 767: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
\r
11649 BFD00F98 002C307E ADDIU V1, S8, 44
\r
11650 BFD00F9C 0048305E ADDIU V0, S8, 72
\r
11651 BFD00FA0 0C83 MOVE A0, V1
\r
11652 BFD00FA2 0CA2 MOVE A1, V0
\r
11653 BFD00FA4 1FF677E8 JALS xTaskCheckForTimeOut
\r
11654 BFD00FA6 0C001FF6 LB RA, 3072(S6)
\r
11655 BFD00FA8 0C00 NOP
\r
11656 BFD00FAA 003740A2 BNEZC V0, 0xBFD0101C
\r
11658 769: if( prvIsQueueFull( pxQueue ) != pdFALSE )
\r
11659 BFD00FAE 0014FC9E LW A0, 20(S8)
\r
11660 BFD00FB2 478277E8 JALS prvIsQueueFull
\r
11661 BFD00FB6 0C00 NOP
\r
11662 BFD00FB8 002640E2 BEQZC V0, 0xBFD01008
\r
11664 771: traceBLOCKING_ON_QUEUE_SEND( pxQueue );
\r
11665 772: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
\r
11666 BFD00FBC 0014FC5E LW V0, 20(S8)
\r
11667 BFD00FC0 6DA8 ADDIU V1, V0, 16
\r
11668 BFD00FC2 0048FC5E LW V0, 72(S8)
\r
11669 BFD00FC6 0C83 MOVE A0, V1
\r
11670 BFD00FC8 0CA2 MOVE A1, V0
\r
11671 BFD00FCA 2F3A77E8 JALS vTaskPlaceOnEventList
\r
11672 BFD00FCC 2F3A ANDI A2, V1, 0x20
\r
11673 BFD00FCE 0C00 NOP
\r
11675 774: /* Unlocking the queue means queue events can effect the
\r
11676 775: event list. It is possible that interrupts occurring now
\r
11677 776: remove this task from the event list again - but as the
\r
11678 777: scheduler is suspended the task will go onto the pending
\r
11679 778: ready last instead of the actual ready list. */
\r
11680 779: prvUnlockQueue( pxQueue );
\r
11681 BFD00FD0 0014FC9E LW A0, 20(S8)
\r
11682 BFD00FD4 1DEE77E8 JALS prvUnlockQueue
\r
11683 BFD00FD6 0C001DEE LB T7, 3072(T6)
\r
11684 BFD00FD8 0C00 NOP
\r
11686 781: /* Resuming the scheduler will move tasks from the pending
\r
11687 782: ready list into the ready list - so it is feasible that this
\r
11688 783: task is already in a ready list before it yields - in which
\r
11689 784: case the yield will not cause a context switch unless there
\r
11690 785: is also a higher priority task in the pending ready list. */
\r
11691 786: if( xTaskResumeAll() == pdFALSE )
\r
11692 BFD00FDA 158E77E8 JALS xTaskResumeAll
\r
11693 BFD00FDC 0C00158E LBU T4, 3072(T6)
\r
11694 BFD00FDE 0C00 NOP
\r
11695 BFD00FE0 FF1E40A2 BNEZC V0, 0xBFD00E20
\r
11696 BFD00FE2 77E8FF1E LW T8, 30696(S8)
\r
11698 788: portYIELD_WITHIN_API();
\r
11699 BFD00FE4 4E1677E8 JALS ulPortGetCP0Cause
\r
11700 BFD00FE6 4E16 ADDIU S0, S0, -5
\r
11701 BFD00FE8 0C00 NOP
\r
11702 BFD00FEA 0018F85E SW V0, 24(S8)
\r
11703 BFD00FEE 0018FC5E LW V0, 24(S8)
\r
11704 BFD00FF2 01005042 ORI V0, V0, 256
\r
11705 BFD00FF6 0018F85E SW V0, 24(S8)
\r
11706 BFD00FFA 0018FC9E LW A0, 24(S8)
\r
11707 BFD00FFE 4E2677E8 JALS vPortSetCP0Cause
\r
11708 BFD01000 4E26 ADDIU S1, S1, 3
\r
11709 BFD01002 0C00 NOP
\r
11714 793: /* Try again. */
\r
11715 794: prvUnlockQueue( pxQueue );
\r
11716 BFD01008 0014FC9E LW A0, 20(S8)
\r
11717 BFD0100C 1DEE77E8 JALS prvUnlockQueue
\r
11718 BFD0100E 0C001DEE LB T7, 3072(T6)
\r
11719 BFD01010 0C00 NOP
\r
11720 795: ( void ) xTaskResumeAll();
\r
11721 BFD01012 158E77E8 JALS xTaskResumeAll
\r
11722 BFD01014 0C00158E LBU T4, 3072(T6)
\r
11723 BFD01016 0C00 NOP
\r
11728 800: /* The timeout has expired. */
\r
11729 801: prvUnlockQueue( pxQueue );
\r
11730 BFD0101C 0014FC9E LW A0, 20(S8)
\r
11731 BFD01020 1DEE77E8 JALS prvUnlockQueue
\r
11732 BFD01022 0C001DEE LB T7, 3072(T6)
\r
11733 BFD01024 0C00 NOP
\r
11734 802: ( void ) xTaskResumeAll();
\r
11735 BFD01026 158E77E8 JALS xTaskResumeAll
\r
11736 BFD01028 0C00158E LBU T4, 3072(T6)
\r
11737 BFD0102A 0C00 NOP
\r
11739 804: /* Return to the original privilege level before exiting the
\r
11740 805: function. */
\r
11741 806: traceQUEUE_SEND_FAILED( pxQueue );
\r
11742 807: return errQUEUE_FULL;
\r
11743 BFD0102C 0C40 MOVE V0, ZERO
\r
11746 BFD00E20 0C00 NOP
\r
11747 BFD01004 CF0E B 0xBFD00E22
\r
11748 BFD01006 0C00 NOP
\r
11749 BFD01018 CF04 B 0xBFD00E22
\r
11750 BFD0101A 0C00 NOP
\r
11752 BFD0102E 0FBE MOVE SP, S8
\r
11753 BFD01030 4BEF LW RA, 60(SP)
\r
11754 BFD01032 4BCE LW S8, 56(SP)
\r
11755 BFD01034 4C21 ADDIU SP, SP, 64
\r
11756 BFD01036 459F JR16 RA
\r
11757 BFD01038 0C00 NOP
\r
11758 811: /*-----------------------------------------------------------*/
\r
11760 813: #if ( configUSE_ALTERNATIVE_API == 1 )
\r
11762 815: BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )
\r
11764 817: BaseType_t xEntryTimeSet = pdFALSE;
\r
11765 818: TimeOut_t xTimeOut;
\r
11766 819: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
11768 821: configASSERT( pxQueue );
\r
11769 822: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
\r
11773 826: taskENTER_CRITICAL();
\r
11775 828: /* Is there room on the queue now? To be running we must be
\r
11776 829: the highest priority task wanting to access the queue. */
\r
11777 830: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
\r
11779 832: traceQUEUE_SEND( pxQueue );
\r
11780 833: prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
\r
11782 835: /* If there was a task waiting for data to arrive on the
\r
11783 836: queue then unblock it now. */
\r
11784 837: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
11786 839: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
\r
11788 841: /* The unblocked task has a priority higher than
\r
11789 842: our own so yield immediately. */
\r
11790 843: portYIELD_WITHIN_API();
\r
11794 847: mtCOVERAGE_TEST_MARKER();
\r
11799 852: mtCOVERAGE_TEST_MARKER();
\r
11802 855: taskEXIT_CRITICAL();
\r
11803 856: return pdPASS;
\r
11807 860: if( xTicksToWait == ( TickType_t ) 0 )
\r
11809 862: taskEXIT_CRITICAL();
\r
11810 863: return errQUEUE_FULL;
\r
11812 865: else if( xEntryTimeSet == pdFALSE )
\r
11814 867: vTaskSetTimeOutState( &xTimeOut );
\r
11815 868: xEntryTimeSet = pdTRUE;
\r
11819 872: taskEXIT_CRITICAL();
\r
11821 874: taskENTER_CRITICAL();
\r
11823 876: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
\r
11825 878: if( prvIsQueueFull( pxQueue ) != pdFALSE )
\r
11827 880: traceBLOCKING_ON_QUEUE_SEND( pxQueue );
\r
11828 881: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
\r
11829 882: portYIELD_WITHIN_API();
\r
11833 886: mtCOVERAGE_TEST_MARKER();
\r
11838 891: taskEXIT_CRITICAL();
\r
11839 892: traceQUEUE_SEND_FAILED( pxQueue );
\r
11840 893: return errQUEUE_FULL;
\r
11843 896: taskEXIT_CRITICAL();
\r
11847 900: #endif /* configUSE_ALTERNATIVE_API */
\r
11848 901: /*-----------------------------------------------------------*/
\r
11850 903: #if ( configUSE_ALTERNATIVE_API == 1 )
\r
11852 905: BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )
\r
11854 907: BaseType_t xEntryTimeSet = pdFALSE;
\r
11855 908: TimeOut_t xTimeOut;
\r
11856 909: int8_t *pcOriginalReadPosition;
\r
11857 910: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
11859 912: configASSERT( pxQueue );
\r
11860 913: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
\r
11864 917: taskENTER_CRITICAL();
\r
11866 919: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
\r
11868 921: /* Remember our read position in case we are just peeking. */
\r
11869 922: pcOriginalReadPosition = pxQueue->u.pcReadFrom;
\r
11871 924: prvCopyDataFromQueue( pxQueue, pvBuffer );
\r
11873 926: if( xJustPeeking == pdFALSE )
\r
11875 928: traceQUEUE_RECEIVE( pxQueue );
\r
11877 930: /* Data is actually being removed (not just peeked). */
\r
11878 931: --( pxQueue->uxMessagesWaiting );
\r
11880 933: #if ( configUSE_MUTEXES == 1 )
\r
11882 935: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
\r
11884 937: /* Record the information required to implement
\r
11885 938: priority inheritance should it become necessary. */
\r
11886 939: pxQueue->pxMutexHolder = ( int8_t * ) xTaskGetCurrentTaskHandle();
\r
11890 943: mtCOVERAGE_TEST_MARKER();
\r
11895 948: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
\r
11897 950: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
\r
11899 952: portYIELD_WITHIN_API();
\r
11903 956: mtCOVERAGE_TEST_MARKER();
\r
11909 962: traceQUEUE_PEEK( pxQueue );
\r
11911 964: /* The data is not being removed, so reset our read
\r
11913 966: pxQueue->u.pcReadFrom = pcOriginalReadPosition;
\r
11915 968: /* The data is being left in the queue, so see if there are
\r
11916 969: any other tasks waiting for the data. */
\r
11917 970: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
11919 972: /* Tasks that are removed from the event list will get added to
\r
11920 973: the pending ready list as the scheduler is still suspended. */
\r
11921 974: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
11923 976: /* The task waiting has a higher priority than this task. */
\r
11924 977: portYIELD_WITHIN_API();
\r
11928 981: mtCOVERAGE_TEST_MARKER();
\r
11933 986: mtCOVERAGE_TEST_MARKER();
\r
11937 990: taskEXIT_CRITICAL();
\r
11938 991: return pdPASS;
\r
11942 995: if( xTicksToWait == ( TickType_t ) 0 )
\r
11944 997: taskEXIT_CRITICAL();
\r
11945 998: traceQUEUE_RECEIVE_FAILED( pxQueue );
\r
11946 999: return errQUEUE_EMPTY;
\r
11948 1001: else if( xEntryTimeSet == pdFALSE )
\r
11950 1003: vTaskSetTimeOutState( &xTimeOut );
\r
11951 1004: xEntryTimeSet = pdTRUE;
\r
11955 1008: taskEXIT_CRITICAL();
\r
11957 1010: taskENTER_CRITICAL();
\r
11959 1012: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
\r
11961 1014: if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
\r
11963 1016: traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
\r
11965 1018: #if ( configUSE_MUTEXES == 1 )
\r
11967 1020: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
\r
11969 1022: taskENTER_CRITICAL();
\r
11971 1024: vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
\r
11973 1026: taskEXIT_CRITICAL();
\r
11977 1030: mtCOVERAGE_TEST_MARKER();
\r
11982 1035: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
\r
11983 1036: portYIELD_WITHIN_API();
\r
11987 1040: mtCOVERAGE_TEST_MARKER();
\r
11992 1045: taskEXIT_CRITICAL();
\r
11993 1046: traceQUEUE_RECEIVE_FAILED( pxQueue );
\r
11994 1047: return errQUEUE_EMPTY;
\r
11997 1050: taskEXIT_CRITICAL();
\r
12002 1055: #endif /* configUSE_ALTERNATIVE_API */
\r
12003 1056: /*-----------------------------------------------------------*/
\r
12005 1058: BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
\r
12007 BFD023D4 4FED ADDIU SP, SP, -40
\r
12008 BFD023D6 CBE9 SW RA, 36(SP)
\r
12009 BFD023D8 CBC8 SW S8, 32(SP)
\r
12010 BFD023DA 0FDD MOVE S8, SP
\r
12011 BFD023DC 0028F89E SW A0, 40(S8)
\r
12012 BFD023E0 002CF8BE SW A1, 44(S8)
\r
12013 BFD023E4 0030F8DE SW A2, 48(S8)
\r
12014 BFD023E8 0034F8FE SW A3, 52(S8)
\r
12015 1060: BaseType_t xReturn;
\r
12016 1061: UBaseType_t uxSavedInterruptStatus;
\r
12017 1062: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
12018 BFD023EC 0028FC5E LW V0, 40(S8)
\r
12019 BFD023F0 0014F85E SW V0, 20(S8)
\r
12021 1064: configASSERT( pxQueue );
\r
12022 BFD023F4 0014FC5E LW V0, 20(S8)
\r
12023 BFD023F8 000940A2 BNEZC V0, 0xBFD0240E
\r
12024 BFD023FC BFD141A2 LUI V0, 0xBFD1
\r
12025 BFD023FE 3082BFD1 LDC1 F30, 12418(S1)
\r
12026 BFD02400 9E3C3082 ADDIU A0, V0, -25028
\r
12027 BFD02402 30A09E3C LWC1 F17, 12448(GP)
\r
12028 BFD02404 042830A0 ADDIU A1, ZERO, 1064
\r
12029 BFD02406 0428 ADDU S0, A0, V0
\r
12030 BFD02408 4B7E77E8 JALS vAssertCalled
\r
12031 BFD0240A 4B7E LW K1, 120(SP)
\r
12032 BFD0240C 0C00 NOP
\r
12033 1065: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
\r
12034 BFD0240E 002CFC5E LW V0, 44(S8)
\r
12035 BFD02412 000640A2 BNEZC V0, 0xBFD02422
\r
12036 BFD02416 0014FC5E LW V0, 20(S8)
\r
12037 BFD0241A 0040FC42 LW V0, 64(V0)
\r
12038 BFD0241E 000340A2 BNEZC V0, 0xBFD02428
\r
12039 BFD02422 ED01 LI V0, 1
\r
12040 BFD02424 CC02 B 0xBFD0242A
\r
12041 BFD02426 0C00 NOP
\r
12042 BFD02428 0C40 MOVE V0, ZERO
\r
12043 BFD0242A 000940A2 BNEZC V0, 0xBFD02440
\r
12044 BFD0242E BFD141A2 LUI V0, 0xBFD1
\r
12045 BFD02430 3082BFD1 LDC1 F30, 12418(S1)
\r
12046 BFD02432 9E3C3082 ADDIU A0, V0, -25028
\r
12047 BFD02434 30A09E3C LWC1 F17, 12448(GP)
\r
12048 BFD02436 042930A0 ADDIU A1, ZERO, 1065
\r
12049 BFD02438 0429 SUBU S0, A0, V0
\r
12050 BFD0243A 4B7E77E8 JALS vAssertCalled
\r
12051 BFD0243C 4B7E LW K1, 120(SP)
\r
12052 BFD0243E 0C00 NOP
\r
12053 1066: configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
\r
12054 BFD02440 0034FC7E LW V1, 52(S8)
\r
12055 BFD02444 ED02 LI V0, 2
\r
12056 BFD02446 0008B443 BNE V1, V0, 0xBFD0245A
\r
12057 BFD02448 0C000008 SLL ZERO, T0, 1
\r
12058 BFD0244A 0C00 NOP
\r
12059 BFD0244C 0014FC5E LW V0, 20(S8)
\r
12060 BFD02450 69AF LW V1, 60(V0)
\r
12061 BFD02452 ED01 LI V0, 1
\r
12062 BFD02454 0004B443 BNE V1, V0, 0xBFD02460
\r
12063 BFD02456 0C000004 SLL ZERO, A0, 1
\r
12064 BFD02458 0C00 NOP
\r
12065 BFD0245A ED01 LI V0, 1
\r
12066 BFD0245C CC02 B 0xBFD02462
\r
12067 BFD0245E 0C00 NOP
\r
12068 BFD02460 0C40 MOVE V0, ZERO
\r
12069 BFD02462 000940A2 BNEZC V0, 0xBFD02478
\r
12070 BFD02466 BFD141A2 LUI V0, 0xBFD1
\r
12071 BFD02468 3082BFD1 LDC1 F30, 12418(S1)
\r
12072 BFD0246A 9E3C3082 ADDIU A0, V0, -25028
\r
12073 BFD0246C 30A09E3C LWC1 F17, 12448(GP)
\r
12074 BFD0246E 042A30A0 ADDIU A1, ZERO, 1066
\r
12075 BFD02470 042A ADDU S0, A1, V0
\r
12076 BFD02472 4B7E77E8 JALS vAssertCalled
\r
12077 BFD02474 4B7E LW K1, 120(SP)
\r
12078 BFD02476 0C00 NOP
\r
12080 1068: /* RTOS ports that support interrupt nesting have the concept of a maximum
\r
12081 1069: system call (or maximum API call) interrupt priority. Interrupts that are
\r
12082 1070: above the maximum system call priority are kept permanently enabled, even
\r
12083 1071: when the RTOS kernel is in a critical section, but cannot make any calls to
\r
12084 1072: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
\r
12085 1073: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
12086 1074: failure if a FreeRTOS API function is called from an interrupt that has been
\r
12087 1075: assigned a priority above the configured maximum system call priority.
\r
12088 1076: Only FreeRTOS functions that end in FromISR can be called from interrupts
\r
12089 1077: that have been assigned a priority at or (logically) below the maximum
\r
12090 1078: system call interrupt priority. FreeRTOS maintains a separate interrupt
\r
12091 1079: safe API to ensure interrupt entry is as fast and as simple as possible.
\r
12092 1080: More information (albeit Cortex-M specific) is provided on the following
\r
12093 1081: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
12094 1082: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
12096 1084: /* Similar to xQueueGenericSend, except without blocking if there is no room
\r
12097 1085: in the queue. Also don't directly wake a task that was blocked on a queue
\r
12098 1086: read, instead return a flag to say whether a context switch is required or
\r
12099 1087: not (i.e. has a task with a higher priority than us been woken by this
\r
12101 1089: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
12102 BFD02478 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
12103 BFD0247C 0C00 NOP
\r
12104 BFD0247E 0018F85E SW V0, 24(S8)
\r
12106 1091: if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
\r
12107 BFD02482 0014FC5E LW V0, 20(S8)
\r
12108 BFD02486 69AE LW V1, 56(V0)
\r
12109 BFD02488 0014FC5E LW V0, 20(S8)
\r
12110 BFD0248C 692F LW V0, 60(V0)
\r
12111 BFD0248E 13900043 SLTU V0, V1, V0
\r
12112 BFD02490 40A21390 ADDI GP, S0, 16546
\r
12113 BFD02492 000640A2 BNEZC V0, 0xBFD024A2
\r
12114 BFD02496 0034FC7E LW V1, 52(S8)
\r
12115 BFD0249A ED02 LI V0, 2
\r
12116 BFD0249C 0055B443 BNE V1, V0, 0xBFD0254A
\r
12117 BFD0249E 0C000055 SLL V0, S5, 1
\r
12118 BFD024A0 0C00 NOP
\r
12120 1093: traceQUEUE_SEND_FROM_ISR( pxQueue );
\r
12122 1095: /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
\r
12123 1096: semaphore or mutex. That means prvCopyDataToQueue() cannot result
\r
12124 1097: in a task disinheriting a priority and prvCopyDataToQueue() can be
\r
12125 1098: called here even though the disinherit function does not check if
\r
12126 1099: the scheduler is suspended before accessing the ready lists. */
\r
12127 1100: ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
\r
12128 BFD024A2 0014FC9E LW A0, 20(S8)
\r
12129 BFD024A6 002CFCBE LW A1, 44(S8)
\r
12130 BFD024AA 0034FCDE LW A2, 52(S8)
\r
12131 BFD024AE 14E677E8 JALS prvCopyDataToQueue
\r
12132 BFD024B0 0C0014E6 LBU A3, 3072(A2)
\r
12133 BFD024B2 0C00 NOP
\r
12135 1102: /* The event list is not altered if the queue is locked. This will
\r
12136 1103: be done when the queue is unlocked later. */
\r
12137 1104: if( pxQueue->xTxLock == queueUNLOCKED )
\r
12138 BFD024B4 0014FC5E LW V0, 20(S8)
\r
12139 BFD024B8 0048FC62 LW V1, 72(V0)
\r
12140 BFD024BC ED7F LI V0, -1
\r
12141 BFD024BE 0036B443 BNE V1, V0, 0xBFD0252E
\r
12142 BFD024C0 0C000036 SLL AT, S6, 1
\r
12143 BFD024C2 0C00 NOP
\r
12145 1106: #if ( configUSE_QUEUE_SETS == 1 )
\r
12147 1108: if( pxQueue->pxQueueSetContainer != NULL )
\r
12148 BFD024C4 0014FC5E LW V0, 20(S8)
\r
12149 BFD024C8 004CFC42 LW V0, 76(V0)
\r
12150 BFD024CC 001640E2 BEQZC V0, 0xBFD024FC
\r
12152 1110: if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )
\r
12153 BFD024D0 0014FC9E LW A0, 20(S8)
\r
12154 BFD024D4 0034FCBE LW A1, 52(S8)
\r
12155 BFD024D8 21D877E8 JALS prvNotifyQueueSetContainer
\r
12156 BFD024DA 0C0021D8 LWC2 T6, 3072(T8)
\r
12157 BFD024DC 0C00 NOP
\r
12158 BFD024DE 0C62 MOVE V1, V0
\r
12159 BFD024E0 ED01 LI V0, 1
\r
12160 BFD024E2 002DB443 BNE V1, V0, 0xBFD02540
\r
12161 BFD024E4 0C00002D SLL AT, T5, 1
\r
12162 BFD024E6 0C00 NOP
\r
12164 1112: /* The queue is a member of a queue set, and posting
\r
12165 1113: to the queue set caused a higher priority task to
\r
12166 1114: unblock. A context switch is required. */
\r
12167 1115: if( pxHigherPriorityTaskWoken != NULL )
\r
12168 BFD024E8 0030FC5E LW V0, 48(S8)
\r
12169 BFD024EC 002840E2 BEQZC V0, 0xBFD02540
\r
12171 1117: *pxHigherPriorityTaskWoken = pdTRUE;
\r
12172 BFD024F0 0030FC5E LW V0, 48(S8)
\r
12173 BFD024F4 ED81 LI V1, 1
\r
12174 BFD024F6 E9A0 SW V1, 0(V0)
\r
12175 BFD024F8 CC23 B 0xBFD02540
\r
12176 BFD024FA 0C00 NOP
\r
12180 1121: mtCOVERAGE_TEST_MARKER();
\r
12185 1126: mtCOVERAGE_TEST_MARKER();
\r
12190 1131: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
12191 BFD024FC 0014FC5E LW V0, 20(S8)
\r
12192 BFD02500 6929 LW V0, 36(V0)
\r
12193 BFD02502 001D40E2 BEQZC V0, 0xBFD02540
\r
12195 1133: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
12196 BFD02506 0014FC5E LW V0, 20(S8)
\r
12197 BFD0250A 00243042 ADDIU V0, V0, 36
\r
12198 BFD0250E 0C82 MOVE A0, V0
\r
12199 BFD02510 22BC77E8 JALS xTaskRemoveFromEventList
\r
12200 BFD02512 0C0022BC LWC2 S5, 3072(GP)
\r
12201 BFD02514 0C00 NOP
\r
12202 BFD02516 001340E2 BEQZC V0, 0xBFD02540
\r
12204 1135: /* The task waiting has a higher priority so
\r
12205 1136: record that a context switch is required. */
\r
12206 1137: if( pxHigherPriorityTaskWoken != NULL )
\r
12207 BFD0251A 0030FC5E LW V0, 48(S8)
\r
12208 BFD0251E 000F40E2 BEQZC V0, 0xBFD02540
\r
12210 1139: *pxHigherPriorityTaskWoken = pdTRUE;
\r
12211 BFD02522 0030FC5E LW V0, 48(S8)
\r
12212 BFD02526 ED81 LI V1, 1
\r
12213 BFD02528 E9A0 SW V1, 0(V0)
\r
12214 BFD0252A CC0A B 0xBFD02540
\r
12215 BFD0252C 0C00 NOP
\r
12219 1143: mtCOVERAGE_TEST_MARKER();
\r
12224 1148: mtCOVERAGE_TEST_MARKER();
\r
12229 1153: mtCOVERAGE_TEST_MARKER();
\r
12233 1157: #else /* configUSE_QUEUE_SETS */
\r
12235 1159: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
12237 1161: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
12239 1163: /* The task waiting has a higher priority so record that a
\r
12240 1164: context switch is required. */
\r
12241 1165: if( pxHigherPriorityTaskWoken != NULL )
\r
12243 1167: *pxHigherPriorityTaskWoken = pdTRUE;
\r
12247 1171: mtCOVERAGE_TEST_MARKER();
\r
12252 1176: mtCOVERAGE_TEST_MARKER();
\r
12257 1181: mtCOVERAGE_TEST_MARKER();
\r
12260 1184: #endif /* configUSE_QUEUE_SETS */
\r
12264 1188: /* Increment the lock count so the task that unlocks the queue
\r
12265 1189: knows that data was posted while it was locked. */
\r
12266 1190: ++( pxQueue->xTxLock );
\r
12267 BFD0252E 0014FC5E LW V0, 20(S8)
\r
12268 BFD02532 0048FC42 LW V0, 72(V0)
\r
12269 BFD02536 6DA0 ADDIU V1, V0, 1
\r
12270 BFD02538 0014FC5E LW V0, 20(S8)
\r
12271 BFD0253C 0048F862 SW V1, 72(V0)
\r
12274 1193: xReturn = pdPASS;
\r
12275 BFD02540 ED01 LI V0, 1
\r
12276 BFD02542 0010F85E SW V0, 16(S8)
\r
12277 BFD02546 CC03 B 0xBFD0254E
\r
12278 BFD02548 0C00 NOP
\r
12282 1197: traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
\r
12283 1198: xReturn = errQUEUE_FULL;
\r
12284 BFD0254A 0010F81E SW ZERO, 16(S8)
\r
12287 1201: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
12288 BFD0254E 0018FC9E LW A0, 24(S8)
\r
12289 BFD02552 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
12290 BFD02554 4D5E ADDIU T2, T2, -1
\r
12291 BFD02556 0C00 NOP
\r
12293 1203: return xReturn;
\r
12294 BFD02558 0010FC5E LW V0, 16(S8)
\r
12296 BFD0255C 0FBE MOVE SP, S8
\r
12297 BFD0255E 4BE9 LW RA, 36(SP)
\r
12298 BFD02560 4BC8 LW S8, 32(SP)
\r
12299 BFD02562 4C15 ADDIU SP, SP, 40
\r
12300 BFD02564 459F JR16 RA
\r
12301 BFD02566 0C00 NOP
\r
12302 1205: /*-----------------------------------------------------------*/
\r
12304 1207: BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
\r
12306 BFD0286C 4FED ADDIU SP, SP, -40
\r
12307 BFD0286E CBE9 SW RA, 36(SP)
\r
12308 BFD02870 CBC8 SW S8, 32(SP)
\r
12309 BFD02872 0FDD MOVE S8, SP
\r
12310 BFD02874 0028F89E SW A0, 40(S8)
\r
12311 BFD02878 002CF8BE SW A1, 44(S8)
\r
12312 1209: BaseType_t xReturn;
\r
12313 1210: UBaseType_t uxSavedInterruptStatus;
\r
12314 1211: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
12315 BFD0287C 0028FC5E LW V0, 40(S8)
\r
12316 BFD02880 0014F85E SW V0, 20(S8)
\r
12318 1213: /* Similar to xQueueGenericSendFromISR() but used with semaphores where the
\r
12319 1214: item size is 0. Don't directly wake a task that was blocked on a queue
\r
12320 1215: read, instead return a flag to say whether a context switch is required or
\r
12321 1216: not (i.e. has a task with a higher priority than us been woken by this
\r
12324 1219: configASSERT( pxQueue );
\r
12325 BFD02884 0014FC5E LW V0, 20(S8)
\r
12326 BFD02888 000940A2 BNEZC V0, 0xBFD0289E
\r
12327 BFD0288C BFD141A2 LUI V0, 0xBFD1
\r
12328 BFD0288E 3082BFD1 LDC1 F30, 12418(S1)
\r
12329 BFD02890 9E3C3082 ADDIU A0, V0, -25028
\r
12330 BFD02892 30A09E3C LWC1 F17, 12448(GP)
\r
12331 BFD02894 04C330A0 ADDIU A1, ZERO, 1219
\r
12332 BFD02896 04C3 SUBU S1, S1, A0
\r
12333 BFD02898 4B7E77E8 JALS vAssertCalled
\r
12334 BFD0289A 4B7E LW K1, 120(SP)
\r
12335 BFD0289C 0C00 NOP
\r
12337 1221: /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
\r
12338 1222: if the item size is not 0. */
\r
12339 1223: configASSERT( pxQueue->uxItemSize == 0 );
\r
12340 BFD0289E 0014FC5E LW V0, 20(S8)
\r
12341 BFD028A2 0040FC42 LW V0, 64(V0)
\r
12342 BFD028A6 000940E2 BEQZC V0, 0xBFD028BC
\r
12343 BFD028AA BFD141A2 LUI V0, 0xBFD1
\r
12344 BFD028AC 3082BFD1 LDC1 F30, 12418(S1)
\r
12345 BFD028AE 9E3C3082 ADDIU A0, V0, -25028
\r
12346 BFD028B0 30A09E3C LWC1 F17, 12448(GP)
\r
12347 BFD028B2 04C730A0 ADDIU A1, ZERO, 1223
\r
12348 BFD028B4 04C7 SUBU S1, V1, A0
\r
12349 BFD028B6 4B7E77E8 JALS vAssertCalled
\r
12350 BFD028B8 4B7E LW K1, 120(SP)
\r
12351 BFD028BA 0C00 NOP
\r
12353 1225: /* Normally a mutex would not be given from an interrupt, and doing so is
\r
12354 1226: definitely wrong if there is a mutex holder as priority inheritance makes no
\r
12355 1227: sense for an interrupts, only tasks. */
\r
12356 1228: configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );
\r
12357 BFD028BC 0014FC5E LW V0, 20(S8)
\r
12358 BFD028C0 6920 LW V0, 0(V0)
\r
12359 BFD028C2 000540A2 BNEZC V0, 0xBFD028D0
\r
12360 BFD028C6 0014FC5E LW V0, 20(S8)
\r
12361 BFD028CA 6921 LW V0, 4(V0)
\r
12362 BFD028CC 000340A2 BNEZC V0, 0xBFD028D6
\r
12363 BFD028D0 ED01 LI V0, 1
\r
12364 BFD028D2 CC02 B 0xBFD028D8
\r
12365 BFD028D4 0C00 NOP
\r
12366 BFD028D6 0C40 MOVE V0, ZERO
\r
12367 BFD028D8 000940A2 BNEZC V0, 0xBFD028EE
\r
12368 BFD028DC BFD141A2 LUI V0, 0xBFD1
\r
12369 BFD028DE 3082BFD1 LDC1 F30, 12418(S1)
\r
12370 BFD028E0 9E3C3082 ADDIU A0, V0, -25028
\r
12371 BFD028E2 30A09E3C LWC1 F17, 12448(GP)
\r
12372 BFD028E4 04CC30A0 ADDIU A1, ZERO, 1228
\r
12373 BFD028E6 04CC ADDU S1, A2, A0
\r
12374 BFD028E8 4B7E77E8 JALS vAssertCalled
\r
12375 BFD028EA 4B7E LW K1, 120(SP)
\r
12376 BFD028EC 0C00 NOP
\r
12378 1230: /* RTOS ports that support interrupt nesting have the concept of a maximum
\r
12379 1231: system call (or maximum API call) interrupt priority. Interrupts that are
\r
12380 1232: above the maximum system call priority are kept permanently enabled, even
\r
12381 1233: when the RTOS kernel is in a critical section, but cannot make any calls to
\r
12382 1234: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
\r
12383 1235: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
12384 1236: failure if a FreeRTOS API function is called from an interrupt that has been
\r
12385 1237: assigned a priority above the configured maximum system call priority.
\r
12386 1238: Only FreeRTOS functions that end in FromISR can be called from interrupts
\r
12387 1239: that have been assigned a priority at or (logically) below the maximum
\r
12388 1240: system call interrupt priority. FreeRTOS maintains a separate interrupt
\r
12389 1241: safe API to ensure interrupt entry is as fast and as simple as possible.
\r
12390 1242: More information (albeit Cortex-M specific) is provided on the following
\r
12391 1243: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
12392 1244: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
12394 1246: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
12395 BFD028EE 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
12396 BFD028F2 0C00 NOP
\r
12397 BFD028F4 0018F85E SW V0, 24(S8)
\r
12399 1248: /* When the queue is used to implement a semaphore no data is ever
\r
12400 1249: moved through the queue but it is still valid to see if the queue 'has
\r
12402 1251: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
\r
12403 BFD028F8 0014FC5E LW V0, 20(S8)
\r
12404 BFD028FC 69AE LW V1, 56(V0)
\r
12405 BFD028FE 0014FC5E LW V0, 20(S8)
\r
12406 BFD02902 692F LW V0, 60(V0)
\r
12407 BFD02904 13900043 SLTU V0, V1, V0
\r
12408 BFD02906 40E21390 ADDI GP, S0, 16610
\r
12409 BFD02908 005140E2 BEQZC V0, 0xBFD029AE
\r
12411 1253: traceQUEUE_SEND_FROM_ISR( pxQueue );
\r
12413 1255: /* A task can only have an inherited priority if it is a mutex
\r
12414 1256: holder - and if there is a mutex holder then the mutex cannot be
\r
12415 1257: given from an ISR. As this is the ISR version of the function it
\r
12416 1258: can be assumed there is no mutex holder and no need to determine if
\r
12417 1259: priority disinheritance is needed. Simply increase the count of
\r
12418 1260: messages (semaphores) available. */
\r
12419 1261: ++( pxQueue->uxMessagesWaiting );
\r
12420 BFD0290C 0014FC5E LW V0, 20(S8)
\r
12421 BFD02910 692E LW V0, 56(V0)
\r
12422 BFD02912 6DA0 ADDIU V1, V0, 1
\r
12423 BFD02914 0014FC5E LW V0, 20(S8)
\r
12424 BFD02918 E9AE SW V1, 56(V0)
\r
12426 1263: /* The event list is not altered if the queue is locked. This will
\r
12427 1264: be done when the queue is unlocked later. */
\r
12428 1265: if( pxQueue->xTxLock == queueUNLOCKED )
\r
12429 BFD0291A 0014FC5E LW V0, 20(S8)
\r
12430 BFD0291E 0048FC62 LW V1, 72(V0)
\r
12431 BFD02922 ED7F LI V0, -1
\r
12432 BFD02924 0035B443 BNE V1, V0, 0xBFD02992
\r
12433 BFD02926 0C000035 SLL AT, S5, 1
\r
12434 BFD02928 0C00 NOP
\r
12436 1267: #if ( configUSE_QUEUE_SETS == 1 )
\r
12438 1269: if( pxQueue->pxQueueSetContainer != NULL )
\r
12439 BFD0292A 0014FC5E LW V0, 20(S8)
\r
12440 BFD0292E 004CFC42 LW V0, 76(V0)
\r
12441 BFD02932 001540E2 BEQZC V0, 0xBFD02960
\r
12443 1271: if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )
\r
12444 BFD02936 0014FC9E LW A0, 20(S8)
\r
12445 BFD0293A 0CA0 MOVE A1, ZERO
\r
12446 BFD0293C 21D877E8 JALS prvNotifyQueueSetContainer
\r
12447 BFD0293E 0C0021D8 LWC2 T6, 3072(T8)
\r
12448 BFD02940 0C00 NOP
\r
12449 BFD02942 0C62 MOVE V1, V0
\r
12450 BFD02944 ED01 LI V0, 1
\r
12451 BFD02946 002DB443 BNE V1, V0, 0xBFD029A4
\r
12452 BFD02948 0C00002D SLL AT, T5, 1
\r
12453 BFD0294A 0C00 NOP
\r
12455 1273: /* The semaphore is a member of a queue set, and
\r
12456 1274: posting to the queue set caused a higher priority
\r
12457 1275: task to unblock. A context switch is required. */
\r
12458 1276: if( pxHigherPriorityTaskWoken != NULL )
\r
12459 BFD0294C 002CFC5E LW V0, 44(S8)
\r
12460 BFD02950 002840E2 BEQZC V0, 0xBFD029A4
\r
12462 1278: *pxHigherPriorityTaskWoken = pdTRUE;
\r
12463 BFD02954 002CFC5E LW V0, 44(S8)
\r
12464 BFD02958 ED81 LI V1, 1
\r
12465 BFD0295A E9A0 SW V1, 0(V0)
\r
12466 BFD0295C CC23 B 0xBFD029A4
\r
12467 BFD0295E 0C00 NOP
\r
12471 1282: mtCOVERAGE_TEST_MARKER();
\r
12476 1287: mtCOVERAGE_TEST_MARKER();
\r
12481 1292: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
12482 BFD02960 0014FC5E LW V0, 20(S8)
\r
12483 BFD02964 6929 LW V0, 36(V0)
\r
12484 BFD02966 001D40E2 BEQZC V0, 0xBFD029A4
\r
12486 1294: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
12487 BFD0296A 0014FC5E LW V0, 20(S8)
\r
12488 BFD0296E 00243042 ADDIU V0, V0, 36
\r
12489 BFD02972 0C82 MOVE A0, V0
\r
12490 BFD02974 22BC77E8 JALS xTaskRemoveFromEventList
\r
12491 BFD02976 0C0022BC LWC2 S5, 3072(GP)
\r
12492 BFD02978 0C00 NOP
\r
12493 BFD0297A 001340E2 BEQZC V0, 0xBFD029A4
\r
12495 1296: /* The task waiting has a higher priority so
\r
12496 1297: record that a context switch is required. */
\r
12497 1298: if( pxHigherPriorityTaskWoken != NULL )
\r
12498 BFD0297E 002CFC5E LW V0, 44(S8)
\r
12499 BFD02982 000F40E2 BEQZC V0, 0xBFD029A4
\r
12501 1300: *pxHigherPriorityTaskWoken = pdTRUE;
\r
12502 BFD02986 002CFC5E LW V0, 44(S8)
\r
12503 BFD0298A ED81 LI V1, 1
\r
12504 BFD0298C E9A0 SW V1, 0(V0)
\r
12505 BFD0298E CC0A B 0xBFD029A4
\r
12506 BFD02990 0C00 NOP
\r
12510 1304: mtCOVERAGE_TEST_MARKER();
\r
12515 1309: mtCOVERAGE_TEST_MARKER();
\r
12520 1314: mtCOVERAGE_TEST_MARKER();
\r
12524 1318: #else /* configUSE_QUEUE_SETS */
\r
12526 1320: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
12528 1322: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
12530 1324: /* The task waiting has a higher priority so record that a
\r
12531 1325: context switch is required. */
\r
12532 1326: if( pxHigherPriorityTaskWoken != NULL )
\r
12534 1328: *pxHigherPriorityTaskWoken = pdTRUE;
\r
12538 1332: mtCOVERAGE_TEST_MARKER();
\r
12543 1337: mtCOVERAGE_TEST_MARKER();
\r
12548 1342: mtCOVERAGE_TEST_MARKER();
\r
12551 1345: #endif /* configUSE_QUEUE_SETS */
\r
12555 1349: /* Increment the lock count so the task that unlocks the queue
\r
12556 1350: knows that data was posted while it was locked. */
\r
12557 1351: ++( pxQueue->xTxLock );
\r
12558 BFD02992 0014FC5E LW V0, 20(S8)
\r
12559 BFD02996 0048FC42 LW V0, 72(V0)
\r
12560 BFD0299A 6DA0 ADDIU V1, V0, 1
\r
12561 BFD0299C 0014FC5E LW V0, 20(S8)
\r
12562 BFD029A0 0048F862 SW V1, 72(V0)
\r
12565 1354: xReturn = pdPASS;
\r
12566 BFD029A4 ED01 LI V0, 1
\r
12567 BFD029A6 0010F85E SW V0, 16(S8)
\r
12568 BFD029AA CC03 B 0xBFD029B2
\r
12569 BFD029AC 0C00 NOP
\r
12573 1358: traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
\r
12574 1359: xReturn = errQUEUE_FULL;
\r
12575 BFD029AE 0010F81E SW ZERO, 16(S8)
\r
12578 1362: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
12579 BFD029B2 0018FC9E LW A0, 24(S8)
\r
12580 BFD029B6 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
12581 BFD029B8 4D5E ADDIU T2, T2, -1
\r
12582 BFD029BA 0C00 NOP
\r
12584 1364: return xReturn;
\r
12585 BFD029BC 0010FC5E LW V0, 16(S8)
\r
12587 BFD029C0 0FBE MOVE SP, S8
\r
12588 BFD029C2 4BE9 LW RA, 36(SP)
\r
12589 BFD029C4 4BC8 LW S8, 32(SP)
\r
12590 BFD029C6 4C15 ADDIU SP, SP, 40
\r
12591 BFD029C8 459F JR16 RA
\r
12592 BFD029CA 0C00 NOP
\r
12593 1366: /*-----------------------------------------------------------*/
\r
12595 1368: BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )
\r
12597 BFD0103C 4FE5 ADDIU SP, SP, -56
\r
12598 BFD0103E CBED SW RA, 52(SP)
\r
12599 BFD01040 CBCC SW S8, 48(SP)
\r
12600 BFD01042 0FDD MOVE S8, SP
\r
12601 BFD01044 0038F89E SW A0, 56(S8)
\r
12602 BFD01048 003CF8BE SW A1, 60(S8)
\r
12603 BFD0104C 0040F8DE SW A2, 64(S8)
\r
12604 BFD01050 0044F8FE SW A3, 68(S8)
\r
12605 1370: BaseType_t xEntryTimeSet = pdFALSE;
\r
12606 BFD01054 0010F81E SW ZERO, 16(S8)
\r
12607 1371: TimeOut_t xTimeOut;
\r
12608 1372: int8_t *pcOriginalReadPosition;
\r
12609 1373: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
12610 BFD01058 0038FC5E LW V0, 56(S8)
\r
12611 BFD0105C 0014F85E SW V0, 20(S8)
\r
12613 1375: configASSERT( pxQueue );
\r
12614 BFD01060 0014FC5E LW V0, 20(S8)
\r
12615 BFD01064 000940A2 BNEZC V0, 0xBFD0107A
\r
12616 BFD01068 BFD141A2 LUI V0, 0xBFD1
\r
12617 BFD0106A 3082BFD1 LDC1 F30, 12418(S1)
\r
12618 BFD0106C 9E3C3082 ADDIU A0, V0, -25028
\r
12619 BFD0106E 30A09E3C LWC1 F17, 12448(GP)
\r
12620 BFD01070 055F30A0 ADDIU A1, ZERO, 1375
\r
12621 BFD01072 055F SUBU V0, A3, A1
\r
12622 BFD01074 4B7E77E8 JALS vAssertCalled
\r
12623 BFD01076 4B7E LW K1, 120(SP)
\r
12624 BFD01078 0C00 NOP
\r
12625 1376: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
\r
12626 BFD0107A 003CFC5E LW V0, 60(S8)
\r
12627 BFD0107E 000640A2 BNEZC V0, 0xBFD0108E
\r
12628 BFD01082 0014FC5E LW V0, 20(S8)
\r
12629 BFD01086 0040FC42 LW V0, 64(V0)
\r
12630 BFD0108A 000340A2 BNEZC V0, 0xBFD01094
\r
12631 BFD0108E ED01 LI V0, 1
\r
12632 BFD01090 CC02 B 0xBFD01096
\r
12633 BFD01092 0C00 NOP
\r
12634 BFD01094 0C40 MOVE V0, ZERO
\r
12635 BFD01096 000940A2 BNEZC V0, 0xBFD010AC
\r
12636 BFD0109A BFD141A2 LUI V0, 0xBFD1
\r
12637 BFD0109C 3082BFD1 LDC1 F30, 12418(S1)
\r
12638 BFD0109E 9E3C3082 ADDIU A0, V0, -25028
\r
12639 BFD010A0 30A09E3C LWC1 F17, 12448(GP)
\r
12640 BFD010A2 056030A0 ADDIU A1, ZERO, 1376
\r
12641 BFD010A4 0560 ADDU V0, S0, A2
\r
12642 BFD010A6 4B7E77E8 JALS vAssertCalled
\r
12643 BFD010A8 4B7E LW K1, 120(SP)
\r
12644 BFD010AA 0C00 NOP
\r
12645 1377: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
\r
12647 1379: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
\r
12648 BFD010AC 4A8E77E8 JALS xTaskGetSchedulerState
\r
12649 BFD010AE 4A8E LW S4, 56(SP)
\r
12650 BFD010B0 0C00 NOP
\r
12651 BFD010B2 000440A2 BNEZC V0, 0xBFD010BE
\r
12652 BFD010B6 0040FC5E LW V0, 64(S8)
\r
12653 BFD010BA 000340A2 BNEZC V0, 0xBFD010C4
\r
12654 BFD010BE ED01 LI V0, 1
\r
12655 BFD010C0 CC02 B 0xBFD010C6
\r
12656 BFD010C2 0C00 NOP
\r
12657 BFD010C4 0C40 MOVE V0, ZERO
\r
12658 BFD010C6 000C40A2 BNEZC V0, 0xBFD010E2
\r
12659 BFD010CA BFD141A2 LUI V0, 0xBFD1
\r
12660 BFD010CC 3082BFD1 LDC1 F30, 12418(S1)
\r
12661 BFD010CE 9E3C3082 ADDIU A0, V0, -25028
\r
12662 BFD010D0 30A09E3C LWC1 F17, 12448(GP)
\r
12663 BFD010D2 056330A0 ADDIU A1, ZERO, 1379
\r
12664 BFD010D4 0563 SUBU V0, S1, A2
\r
12665 BFD010D6 4B7E77E8 JALS vAssertCalled
\r
12666 BFD010D8 4B7E LW K1, 120(SP)
\r
12667 BFD010DA 0C00 NOP
\r
12668 BFD010DC CC02 B 0xBFD010E2
\r
12669 BFD010DE 0C00 NOP
\r
12673 1383: /* This function relaxes the coding standard somewhat to allow return
\r
12674 1384: statements within the function itself. This is done in the interest
\r
12675 1385: of execution time efficiency. */
\r
12679 1389: taskENTER_CRITICAL();
\r
12680 BFD010E2 33B877E8 JALS vTaskEnterCritical
\r
12681 BFD010E4 0C0033B8 ADDIU SP, T8, 3072
\r
12682 BFD010E6 0C00 NOP
\r
12684 1391: /* Is there data in the queue now? To be running the calling task
\r
12685 1392: must be the highest priority task wanting to access the queue. */
\r
12686 1393: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
\r
12687 BFD010E8 0014FC5E LW V0, 20(S8)
\r
12688 BFD010EC 692E LW V0, 56(V0)
\r
12689 BFD010EE 007040E2 BEQZC V0, 0xBFD011D2
\r
12691 1395: /* Remember the read position in case the queue is only being
\r
12693 1397: pcOriginalReadPosition = pxQueue->u.pcReadFrom;
\r
12694 BFD010F2 0014FC5E LW V0, 20(S8)
\r
12695 BFD010F6 6923 LW V0, 12(V0)
\r
12696 BFD010F8 0018F85E SW V0, 24(S8)
\r
12698 1399: prvCopyDataFromQueue( pxQueue, pvBuffer );
\r
12699 BFD010FC 0014FC9E LW A0, 20(S8)
\r
12700 BFD01100 003CFCBE LW A1, 60(S8)
\r
12701 BFD01104 367A77E8 JALS prvCopyDataFromQueue
\r
12702 BFD01106 0C00367A LHU S3, 3072(K0)
\r
12703 BFD01108 0C00 NOP
\r
12705 1401: if( xJustPeeking == pdFALSE )
\r
12706 BFD0110A 0044FC5E LW V0, 68(S8)
\r
12707 BFD0110E 003640A2 BNEZC V0, 0xBFD0117E
\r
12709 1403: traceQUEUE_RECEIVE( pxQueue );
\r
12711 1405: /* Actually removing data, not just peeking. */
\r
12712 1406: --( pxQueue->uxMessagesWaiting );
\r
12713 BFD01112 0014FC5E LW V0, 20(S8)
\r
12714 BFD01116 692E LW V0, 56(V0)
\r
12715 BFD01118 6DAE ADDIU V1, V0, -1
\r
12716 BFD0111A 0014FC5E LW V0, 20(S8)
\r
12717 BFD0111E E9AE SW V1, 56(V0)
\r
12719 1408: #if ( configUSE_MUTEXES == 1 )
\r
12721 1410: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
\r
12722 BFD01120 0014FC5E LW V0, 20(S8)
\r
12723 BFD01124 6920 LW V0, 0(V0)
\r
12724 BFD01126 000740A2 BNEZC V0, 0xBFD01138
\r
12726 1412: /* Record the information required to implement
\r
12727 1413: priority inheritance should it become necessary. */
\r
12728 1414: pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
\r
12729 BFD0112A 4CE077E8 JALS pvTaskIncrementMutexHeldCount
\r
12730 BFD0112C 4CE0 ADDIU A3, A3, 0
\r
12731 BFD0112E 0C00 NOP
\r
12732 BFD01130 0C62 MOVE V1, V0
\r
12733 BFD01132 0014FC5E LW V0, 20(S8)
\r
12734 BFD01136 E9A1 SW V1, 4(V0)
\r
12738 1418: mtCOVERAGE_TEST_MARKER();
\r
12741 1421: #endif /* configUSE_MUTEXES */
\r
12743 1423: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
\r
12744 BFD01138 0014FC5E LW V0, 20(S8)
\r
12745 BFD0113C 6924 LW V0, 16(V0)
\r
12746 BFD0113E 004240E2 BEQZC V0, 0xBFD011C6
\r
12748 1425: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
\r
12749 BFD01142 0014FC5E LW V0, 20(S8)
\r
12750 BFD01146 6D28 ADDIU V0, V0, 16
\r
12751 BFD01148 0C82 MOVE A0, V0
\r
12752 BFD0114A 22BC77E8 JALS xTaskRemoveFromEventList
\r
12753 BFD0114C 0C0022BC LWC2 S5, 3072(GP)
\r
12754 BFD0114E 0C00 NOP
\r
12755 BFD01150 0C62 MOVE V1, V0
\r
12756 BFD01152 ED01 LI V0, 1
\r
12757 BFD01154 0037B443 BNE V1, V0, 0xBFD011C6
\r
12758 BFD01156 0C000037 SLL AT, S7, 1
\r
12759 BFD01158 0C00 NOP
\r
12761 1427: queueYIELD_IF_USING_PREEMPTION();
\r
12762 BFD0115A 4E1677E8 JALS ulPortGetCP0Cause
\r
12763 BFD0115C 4E16 ADDIU S0, S0, -5
\r
12764 BFD0115E 0C00 NOP
\r
12765 BFD01160 001CF85E SW V0, 28(S8)
\r
12766 BFD01164 001CFC5E LW V0, 28(S8)
\r
12767 BFD01168 01005042 ORI V0, V0, 256
\r
12768 BFD0116C 001CF85E SW V0, 28(S8)
\r
12769 BFD01170 001CFC9E LW A0, 28(S8)
\r
12770 BFD01174 4E2677E8 JALS vPortSetCP0Cause
\r
12771 BFD01176 4E26 ADDIU S1, S1, 3
\r
12772 BFD01178 0C00 NOP
\r
12773 BFD0117A CC25 B 0xBFD011C6
\r
12774 BFD0117C 0C00 NOP
\r
12778 1431: mtCOVERAGE_TEST_MARKER();
\r
12783 1436: mtCOVERAGE_TEST_MARKER();
\r
12788 1441: traceQUEUE_PEEK( pxQueue );
\r
12790 1443: /* The data is not being removed, so reset the read
\r
12791 1444: pointer. */
\r
12792 1445: pxQueue->u.pcReadFrom = pcOriginalReadPosition;
\r
12793 BFD0117E 0014FC5E LW V0, 20(S8)
\r
12794 BFD01182 0018FC7E LW V1, 24(S8)
\r
12795 BFD01186 E9A3 SW V1, 12(V0)
\r
12797 1447: /* The data is being left in the queue, so see if there are
\r
12798 1448: any other tasks waiting for the data. */
\r
12799 1449: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
12800 BFD01188 0014FC5E LW V0, 20(S8)
\r
12801 BFD0118C 6929 LW V0, 36(V0)
\r
12802 BFD0118E 001A40E2 BEQZC V0, 0xBFD011C6
\r
12804 1451: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
12805 BFD01192 0014FC5E LW V0, 20(S8)
\r
12806 BFD01196 00243042 ADDIU V0, V0, 36
\r
12807 BFD0119A 0C82 MOVE A0, V0
\r
12808 BFD0119C 22BC77E8 JALS xTaskRemoveFromEventList
\r
12809 BFD0119E 0C0022BC LWC2 S5, 3072(GP)
\r
12810 BFD011A0 0C00 NOP
\r
12811 BFD011A2 001040E2 BEQZC V0, 0xBFD011C6
\r
12813 1453: /* The task waiting has a higher priority than this task. */
\r
12814 1454: queueYIELD_IF_USING_PREEMPTION();
\r
12815 BFD011A6 4E1677E8 JALS ulPortGetCP0Cause
\r
12816 BFD011A8 4E16 ADDIU S0, S0, -5
\r
12817 BFD011AA 0C00 NOP
\r
12818 BFD011AC 0020F85E SW V0, 32(S8)
\r
12819 BFD011B0 0020FC5E LW V0, 32(S8)
\r
12820 BFD011B4 01005042 ORI V0, V0, 256
\r
12821 BFD011B8 0020F85E SW V0, 32(S8)
\r
12822 BFD011BC 0020FC9E LW A0, 32(S8)
\r
12823 BFD011C0 4E2677E8 JALS vPortSetCP0Cause
\r
12824 BFD011C2 4E26 ADDIU S1, S1, 3
\r
12825 BFD011C4 0C00 NOP
\r
12829 1458: mtCOVERAGE_TEST_MARKER();
\r
12834 1463: mtCOVERAGE_TEST_MARKER();
\r
12838 1467: taskEXIT_CRITICAL();
\r
12839 BFD011C6 40AA77E8 JALS vTaskExitCritical
\r
12840 BFD011C8 0C0040AA BNEZC T2, prvCopyDataToQueue
\r
12841 BFD011CA 0C00 NOP
\r
12842 1468: return pdPASS;
\r
12843 BFD011CC ED01 LI V0, 1
\r
12844 BFD011CE CC9A B 0xBFD01304
\r
12845 BFD011D0 0C00 NOP
\r
12849 1472: if( xTicksToWait == ( TickType_t ) 0 )
\r
12850 BFD011D2 0040FC5E LW V0, 64(S8)
\r
12851 BFD011D6 000640A2 BNEZC V0, 0xBFD011E6
\r
12853 1474: /* The queue was empty and no block time is specified (or
\r
12854 1475: the block time has expired) so leave now. */
\r
12855 1476: taskEXIT_CRITICAL();
\r
12856 BFD011DA 40AA77E8 JALS vTaskExitCritical
\r
12857 BFD011DC 0C0040AA BNEZC T2, 0xBFD029E0
\r
12858 BFD011DE 0C00 NOP
\r
12859 1477: traceQUEUE_RECEIVE_FAILED( pxQueue );
\r
12860 1478: return errQUEUE_EMPTY;
\r
12861 BFD011E0 0C40 MOVE V0, ZERO
\r
12862 BFD011E2 CC90 B 0xBFD01304
\r
12863 BFD011E4 0C00 NOP
\r
12865 1480: else if( xEntryTimeSet == pdFALSE )
\r
12866 BFD011E6 0010FC5E LW V0, 16(S8)
\r
12867 BFD011EA 000940A2 BNEZC V0, 0xBFD01200
\r
12869 1482: /* The queue was empty and a block time was specified so
\r
12870 1483: configure the timeout structure. */
\r
12871 1484: vTaskSetTimeOutState( &xTimeOut );
\r
12872 BFD011EE 0028305E ADDIU V0, S8, 40
\r
12873 BFD011F2 0C82 MOVE A0, V0
\r
12874 BFD011F4 47A677E8 JALS vTaskSetTimeOutState
\r
12875 BFD011F8 0C00 NOP
\r
12876 1485: xEntryTimeSet = pdTRUE;
\r
12877 BFD011FA ED01 LI V0, 1
\r
12878 BFD011FC 0010F85E SW V0, 16(S8)
\r
12882 1489: /* Entry time was already set. */
\r
12883 1490: mtCOVERAGE_TEST_MARKER();
\r
12887 1494: taskEXIT_CRITICAL();
\r
12888 BFD01200 40AA77E8 JALS vTaskExitCritical
\r
12889 BFD01202 0C0040AA BNEZC T2, 0xBFD02A06
\r
12890 BFD01204 0C00 NOP
\r
12892 1496: /* Interrupts and other tasks can send to and receive from the queue
\r
12893 1497: now the critical section has been exited. */
\r
12895 1499: vTaskSuspendAll();
\r
12896 BFD01206 4EF477E8 JALS vTaskSuspendAll
\r
12897 BFD01208 4EF4 ADDIU S7, S7, -6
\r
12898 BFD0120A 0C00 NOP
\r
12899 1500: prvLockQueue( pxQueue );
\r
12900 BFD0120C 33B877E8 JALS vTaskEnterCritical
\r
12901 BFD0120E 0C0033B8 ADDIU SP, T8, 3072
\r
12902 BFD01210 0C00 NOP
\r
12903 BFD01212 0014FC5E LW V0, 20(S8)
\r
12904 BFD01216 0044FC62 LW V1, 68(V0)
\r
12905 BFD0121A ED7F LI V0, -1
\r
12906 BFD0121C 0005B443 BNE V1, V0, 0xBFD0122A
\r
12907 BFD0121E 0C000005 SLL ZERO, A1, 1
\r
12908 BFD01220 0C00 NOP
\r
12909 BFD01222 0014FC5E LW V0, 20(S8)
\r
12910 BFD01226 0044F802 SW ZERO, 68(V0)
\r
12911 BFD0122A 0014FC5E LW V0, 20(S8)
\r
12912 BFD0122E 0048FC62 LW V1, 72(V0)
\r
12913 BFD01232 ED7F LI V0, -1
\r
12914 BFD01234 0005B443 BNE V1, V0, 0xBFD01242
\r
12915 BFD01236 0C000005 SLL ZERO, A1, 1
\r
12916 BFD01238 0C00 NOP
\r
12917 BFD0123A 0014FC5E LW V0, 20(S8)
\r
12918 BFD0123E 0048F802 SW ZERO, 72(V0)
\r
12919 BFD01242 40AA77E8 JALS vTaskExitCritical
\r
12920 BFD01244 0C0040AA BNEZC T2, 0xBFD02A48
\r
12921 BFD01246 0C00 NOP
\r
12923 1502: /* Update the timeout state to see if it has expired yet. */
\r
12924 1503: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
\r
12925 BFD01248 0028307E ADDIU V1, S8, 40
\r
12926 BFD0124C 0040305E ADDIU V0, S8, 64
\r
12927 BFD01250 0C83 MOVE A0, V1
\r
12928 BFD01252 0CA2 MOVE A1, V0
\r
12929 BFD01254 1FF677E8 JALS xTaskCheckForTimeOut
\r
12930 BFD01256 0C001FF6 LB RA, 3072(S6)
\r
12931 BFD01258 0C00 NOP
\r
12932 BFD0125A 004A40A2 BNEZC V0, 0xBFD012F2
\r
12934 1505: if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
\r
12935 BFD0125E 0014FC9E LW A0, 20(S8)
\r
12936 BFD01262 49D077E8 JALS prvIsQueueEmpty
\r
12937 BFD01264 49D0 LW T6, 64(SP)
\r
12938 BFD01266 0C00 NOP
\r
12939 BFD01268 003940E2 BEQZC V0, 0xBFD012DE
\r
12941 1507: traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
\r
12943 1509: #if ( configUSE_MUTEXES == 1 )
\r
12945 1511: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
\r
12946 BFD0126C 0014FC5E LW V0, 20(S8)
\r
12947 BFD01270 6920 LW V0, 0(V0)
\r
12948 BFD01272 000D40A2 BNEZC V0, 0xBFD01290
\r
12950 1513: taskENTER_CRITICAL();
\r
12951 BFD01276 33B877E8 JALS vTaskEnterCritical
\r
12952 BFD01278 0C0033B8 ADDIU SP, T8, 3072
\r
12953 BFD0127A 0C00 NOP
\r
12955 1515: vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
\r
12956 BFD0127C 0014FC5E LW V0, 20(S8)
\r
12957 BFD01280 6921 LW V0, 4(V0)
\r
12958 BFD01282 0C82 MOVE A0, V0
\r
12959 BFD01284 1A9077E8 JALS vTaskPriorityInherit
\r
12960 BFD01286 0C001A90 SB S4, 3072(S0)
\r
12961 BFD01288 0C00 NOP
\r
12963 1517: taskEXIT_CRITICAL();
\r
12964 BFD0128A 40AA77E8 JALS vTaskExitCritical
\r
12965 BFD0128C 0C0040AA BNEZC T2, 0xBFD02A90
\r
12966 BFD0128E 0C00 NOP
\r
12970 1521: mtCOVERAGE_TEST_MARKER();
\r
12975 1526: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
\r
12976 BFD01290 0014FC5E LW V0, 20(S8)
\r
12977 BFD01294 00243062 ADDIU V1, V0, 36
\r
12978 BFD01298 0040FC5E LW V0, 64(S8)
\r
12979 BFD0129C 0C83 MOVE A0, V1
\r
12980 BFD0129E 0CA2 MOVE A1, V0
\r
12981 BFD012A0 2F3A77E8 JALS vTaskPlaceOnEventList
\r
12982 BFD012A2 2F3A ANDI A2, V1, 0x20
\r
12983 BFD012A4 0C00 NOP
\r
12984 1527: prvUnlockQueue( pxQueue );
\r
12985 BFD012A6 0014FC9E LW A0, 20(S8)
\r
12986 BFD012AA 1DEE77E8 JALS prvUnlockQueue
\r
12987 BFD012AC 0C001DEE LB T7, 3072(T6)
\r
12988 BFD012AE 0C00 NOP
\r
12989 1528: if( xTaskResumeAll() == pdFALSE )
\r
12990 BFD012B0 158E77E8 JALS xTaskResumeAll
\r
12991 BFD012B2 0C00158E LBU T4, 3072(T6)
\r
12992 BFD012B4 0C00 NOP
\r
12993 BFD012B6 FF1340A2 BNEZC V0, 0xBFD010E0
\r
12994 BFD012B8 77E8FF13 LW T8, 30696(S3)
\r
12996 1530: portYIELD_WITHIN_API();
\r
12997 BFD012BA 4E1677E8 JALS ulPortGetCP0Cause
\r
12998 BFD012BC 4E16 ADDIU S0, S0, -5
\r
12999 BFD012BE 0C00 NOP
\r
13000 BFD012C0 0024F85E SW V0, 36(S8)
\r
13001 BFD012C4 0024FC5E LW V0, 36(S8)
\r
13002 BFD012C8 01005042 ORI V0, V0, 256
\r
13003 BFD012CC 0024F85E SW V0, 36(S8)
\r
13004 BFD012D0 0024FC9E LW A0, 36(S8)
\r
13005 BFD012D4 4E2677E8 JALS vPortSetCP0Cause
\r
13006 BFD012D6 4E26 ADDIU S1, S1, 3
\r
13007 BFD012D8 0C00 NOP
\r
13011 1534: mtCOVERAGE_TEST_MARKER();
\r
13016 1539: /* Try again. */
\r
13017 1540: prvUnlockQueue( pxQueue );
\r
13018 BFD012DE 0014FC9E LW A0, 20(S8)
\r
13019 BFD012E2 1DEE77E8 JALS prvUnlockQueue
\r
13020 BFD012E4 0C001DEE LB T7, 3072(T6)
\r
13021 BFD012E6 0C00 NOP
\r
13022 1541: ( void ) xTaskResumeAll();
\r
13023 BFD012E8 158E77E8 JALS xTaskResumeAll
\r
13024 BFD012EA 0C00158E LBU T4, 3072(T6)
\r
13025 BFD012EC 0C00 NOP
\r
13030 1546: prvUnlockQueue( pxQueue );
\r
13031 BFD012F2 0014FC9E LW A0, 20(S8)
\r
13032 BFD012F6 1DEE77E8 JALS prvUnlockQueue
\r
13033 BFD012F8 0C001DEE LB T7, 3072(T6)
\r
13034 BFD012FA 0C00 NOP
\r
13035 1547: ( void ) xTaskResumeAll();
\r
13036 BFD012FC 158E77E8 JALS xTaskResumeAll
\r
13037 BFD012FE 0C00158E LBU T4, 3072(T6)
\r
13038 BFD01300 0C00 NOP
\r
13039 1548: traceQUEUE_RECEIVE_FAILED( pxQueue );
\r
13040 1549: return errQUEUE_EMPTY;
\r
13041 BFD01302 0C40 MOVE V0, ZERO
\r
13044 BFD010E0 0C00 NOP
\r
13045 BFD012DA CF03 B 0xBFD010E2
\r
13046 BFD012DC 0C00 NOP
\r
13047 BFD012EE CEF9 B 0xBFD010E2
\r
13048 BFD012F0 0C00 NOP
\r
13050 BFD01304 0FBE MOVE SP, S8
\r
13051 BFD01306 4BED LW RA, 52(SP)
\r
13052 BFD01308 4BCC LW S8, 48(SP)
\r
13053 BFD0130A 4C1D ADDIU SP, SP, 56
\r
13054 BFD0130C 459F JR16 RA
\r
13055 BFD0130E 0C00 NOP
\r
13056 1553: /*-----------------------------------------------------------*/
\r
13058 1555: BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
\r
13060 BFD03AC8 4FED ADDIU SP, SP, -40
\r
13061 BFD03ACA CBE9 SW RA, 36(SP)
\r
13062 BFD03ACC CBC8 SW S8, 32(SP)
\r
13063 BFD03ACE 0FDD MOVE S8, SP
\r
13064 BFD03AD0 0028F89E SW A0, 40(S8)
\r
13065 BFD03AD4 002CF8BE SW A1, 44(S8)
\r
13066 BFD03AD8 0030F8DE SW A2, 48(S8)
\r
13067 1557: BaseType_t xReturn;
\r
13068 1558: UBaseType_t uxSavedInterruptStatus;
\r
13069 1559: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
13070 BFD03ADC 0028FC5E LW V0, 40(S8)
\r
13071 BFD03AE0 0014F85E SW V0, 20(S8)
\r
13073 1561: configASSERT( pxQueue );
\r
13074 BFD03AE4 0014FC5E LW V0, 20(S8)
\r
13075 BFD03AE8 000940A2 BNEZC V0, 0xBFD03AFE
\r
13076 BFD03AEC BFD141A2 LUI V0, 0xBFD1
\r
13077 BFD03AEE 3082BFD1 LDC1 F30, 12418(S1)
\r
13078 BFD03AF0 9E3C3082 ADDIU A0, V0, -25028
\r
13079 BFD03AF2 30A09E3C LWC1 F17, 12448(GP)
\r
13080 BFD03AF4 061930A0 ADDIU A1, ZERO, 1561
\r
13081 BFD03AF6 0619 SUBU A0, A0, S1
\r
13082 BFD03AF8 4B7E77E8 JALS vAssertCalled
\r
13083 BFD03AFA 4B7E LW K1, 120(SP)
\r
13084 BFD03AFC 0C00 NOP
\r
13085 1562: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
\r
13086 BFD03AFE 002CFC5E LW V0, 44(S8)
\r
13087 BFD03B02 000640A2 BNEZC V0, 0xBFD03B12
\r
13088 BFD03B06 0014FC5E LW V0, 20(S8)
\r
13089 BFD03B0A 0040FC42 LW V0, 64(V0)
\r
13090 BFD03B0E 000340A2 BNEZC V0, 0xBFD03B18
\r
13091 BFD03B12 ED01 LI V0, 1
\r
13092 BFD03B14 CC02 B 0xBFD03B1A
\r
13093 BFD03B16 0C00 NOP
\r
13094 BFD03B18 0C40 MOVE V0, ZERO
\r
13095 BFD03B1A 000940A2 BNEZC V0, 0xBFD03B30
\r
13096 BFD03B1E BFD141A2 LUI V0, 0xBFD1
\r
13097 BFD03B20 3082BFD1 LDC1 F30, 12418(S1)
\r
13098 BFD03B22 9E3C3082 ADDIU A0, V0, -25028
\r
13099 BFD03B24 30A09E3C LWC1 F17, 12448(GP)
\r
13100 BFD03B26 061A30A0 ADDIU A1, ZERO, 1562
\r
13101 BFD03B28 061A ADDU A0, A1, S1
\r
13102 BFD03B2A 4B7E77E8 JALS vAssertCalled
\r
13103 BFD03B2C 4B7E LW K1, 120(SP)
\r
13104 BFD03B2E 0C00 NOP
\r
13106 1564: /* RTOS ports that support interrupt nesting have the concept of a maximum
\r
13107 1565: system call (or maximum API call) interrupt priority. Interrupts that are
\r
13108 1566: above the maximum system call priority are kept permanently enabled, even
\r
13109 1567: when the RTOS kernel is in a critical section, but cannot make any calls to
\r
13110 1568: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
\r
13111 1569: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
13112 1570: failure if a FreeRTOS API function is called from an interrupt that has been
\r
13113 1571: assigned a priority above the configured maximum system call priority.
\r
13114 1572: Only FreeRTOS functions that end in FromISR can be called from interrupts
\r
13115 1573: that have been assigned a priority at or (logically) below the maximum
\r
13116 1574: system call interrupt priority. FreeRTOS maintains a separate interrupt
\r
13117 1575: safe API to ensure interrupt entry is as fast and as simple as possible.
\r
13118 1576: More information (albeit Cortex-M specific) is provided on the following
\r
13119 1577: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
13120 1578: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
13122 1580: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
13123 BFD03B30 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
13124 BFD03B34 0C00 NOP
\r
13125 BFD03B36 0018F85E SW V0, 24(S8)
\r
13127 1582: /* Cannot block in an ISR, so check there is data available. */
\r
13128 1583: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
\r
13129 BFD03B3A 0014FC5E LW V0, 20(S8)
\r
13130 BFD03B3E 692E LW V0, 56(V0)
\r
13131 BFD03B40 003C40E2 BEQZC V0, 0xBFD03BBC
\r
13133 1585: traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
\r
13135 1587: prvCopyDataFromQueue( pxQueue, pvBuffer );
\r
13136 BFD03B44 0014FC9E LW A0, 20(S8)
\r
13137 BFD03B48 002CFCBE LW A1, 44(S8)
\r
13138 BFD03B4C 367A77E8 JALS prvCopyDataFromQueue
\r
13139 BFD03B4E 0C00367A LHU S3, 3072(K0)
\r
13140 BFD03B50 0C00 NOP
\r
13141 1588: --( pxQueue->uxMessagesWaiting );
\r
13142 BFD03B52 0014FC5E LW V0, 20(S8)
\r
13143 BFD03B56 692E LW V0, 56(V0)
\r
13144 BFD03B58 6DAE ADDIU V1, V0, -1
\r
13145 BFD03B5A 0014FC5E LW V0, 20(S8)
\r
13146 BFD03B5E E9AE SW V1, 56(V0)
\r
13148 1590: /* If the queue is locked the event list will not be modified.
\r
13149 1591: Instead update the lock count so the task that unlocks the queue
\r
13150 1592: will know that an ISR has removed data while the queue was
\r
13152 1594: if( pxQueue->xRxLock == queueUNLOCKED )
\r
13153 BFD03B60 0014FC5E LW V0, 20(S8)
\r
13154 BFD03B64 0044FC62 LW V1, 68(V0)
\r
13155 BFD03B68 ED7F LI V0, -1
\r
13156 BFD03B6A 0019B443 BNE V1, V0, 0xBFD03BA0
\r
13157 BFD03B6C 0C000019 SLL ZERO, T9, 1
\r
13158 BFD03B6E 0C00 NOP
\r
13160 1596: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
\r
13161 BFD03B70 0014FC5E LW V0, 20(S8)
\r
13162 BFD03B74 6924 LW V0, 16(V0)
\r
13163 BFD03B76 001C40E2 BEQZC V0, 0xBFD03BB2
\r
13165 1598: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
\r
13166 BFD03B7A 0014FC5E LW V0, 20(S8)
\r
13167 BFD03B7E 6D28 ADDIU V0, V0, 16
\r
13168 BFD03B80 0C82 MOVE A0, V0
\r
13169 BFD03B82 22BC77E8 JALS xTaskRemoveFromEventList
\r
13170 BFD03B84 0C0022BC LWC2 S5, 3072(GP)
\r
13171 BFD03B86 0C00 NOP
\r
13172 BFD03B88 001340E2 BEQZC V0, 0xBFD03BB2
\r
13174 1600: /* The task waiting has a higher priority than us so
\r
13175 1601: force a context switch. */
\r
13176 1602: if( pxHigherPriorityTaskWoken != NULL )
\r
13177 BFD03B8C 0030FC5E LW V0, 48(S8)
\r
13178 BFD03B90 000F40E2 BEQZC V0, 0xBFD03BB2
\r
13180 1604: *pxHigherPriorityTaskWoken = pdTRUE;
\r
13181 BFD03B94 0030FC5E LW V0, 48(S8)
\r
13182 BFD03B98 ED81 LI V1, 1
\r
13183 BFD03B9A E9A0 SW V1, 0(V0)
\r
13184 BFD03B9C CC0A B 0xBFD03BB2
\r
13185 BFD03B9E 0C00 NOP
\r
13189 1608: mtCOVERAGE_TEST_MARKER();
\r
13194 1613: mtCOVERAGE_TEST_MARKER();
\r
13199 1618: mtCOVERAGE_TEST_MARKER();
\r
13204 1623: /* Increment the lock count so the task that unlocks the queue
\r
13205 1624: knows that data was removed while it was locked. */
\r
13206 1625: ++( pxQueue->xRxLock );
\r
13207 BFD03BA0 0014FC5E LW V0, 20(S8)
\r
13208 BFD03BA4 0044FC42 LW V0, 68(V0)
\r
13209 BFD03BA8 6DA0 ADDIU V1, V0, 1
\r
13210 BFD03BAA 0014FC5E LW V0, 20(S8)
\r
13211 BFD03BAE 0044F862 SW V1, 68(V0)
\r
13214 1628: xReturn = pdPASS;
\r
13215 BFD03BB2 ED01 LI V0, 1
\r
13216 BFD03BB4 0010F85E SW V0, 16(S8)
\r
13217 BFD03BB8 CC03 B 0xBFD03BC0
\r
13218 BFD03BBA 0C00 NOP
\r
13222 1632: xReturn = pdFAIL;
\r
13223 BFD03BBC 0010F81E SW ZERO, 16(S8)
\r
13224 1633: traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
\r
13227 1636: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
13228 BFD03BC0 0018FC9E LW A0, 24(S8)
\r
13229 BFD03BC4 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
13230 BFD03BC6 4D5E ADDIU T2, T2, -1
\r
13231 BFD03BC8 0C00 NOP
\r
13233 1638: return xReturn;
\r
13234 BFD03BCA 0010FC5E LW V0, 16(S8)
\r
13236 BFD03BCE 0FBE MOVE SP, S8
\r
13237 BFD03BD0 4BE9 LW RA, 36(SP)
\r
13238 BFD03BD2 4BC8 LW S8, 32(SP)
\r
13239 BFD03BD4 4C15 ADDIU SP, SP, 40
\r
13240 BFD03BD6 459F JR16 RA
\r
13241 BFD03BD8 0C00 NOP
\r
13242 1640: /*-----------------------------------------------------------*/
\r
13244 1642: BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer )
\r
13246 BFD04824 4FED ADDIU SP, SP, -40
\r
13247 BFD04826 CBE9 SW RA, 36(SP)
\r
13248 BFD04828 CBC8 SW S8, 32(SP)
\r
13249 BFD0482A 0FDD MOVE S8, SP
\r
13250 BFD0482C 0028F89E SW A0, 40(S8)
\r
13251 BFD04830 002CF8BE SW A1, 44(S8)
\r
13252 1644: BaseType_t xReturn;
\r
13253 1645: UBaseType_t uxSavedInterruptStatus;
\r
13254 1646: int8_t *pcOriginalReadPosition;
\r
13255 1647: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
13256 BFD04834 0028FC5E LW V0, 40(S8)
\r
13257 BFD04838 0014F85E SW V0, 20(S8)
\r
13259 1649: configASSERT( pxQueue );
\r
13260 BFD0483C 0014FC5E LW V0, 20(S8)
\r
13261 BFD04840 000940A2 BNEZC V0, 0xBFD04856
\r
13262 BFD04844 BFD141A2 LUI V0, 0xBFD1
\r
13263 BFD04846 3082BFD1 LDC1 F30, 12418(S1)
\r
13264 BFD04848 9E3C3082 ADDIU A0, V0, -25028
\r
13265 BFD0484A 30A09E3C LWC1 F17, 12448(GP)
\r
13266 BFD0484C 067130A0 ADDIU A1, ZERO, 1649
\r
13267 BFD0484E 0671 SUBU A0, S0, A3
\r
13268 BFD04850 4B7E77E8 JALS vAssertCalled
\r
13269 BFD04852 4B7E LW K1, 120(SP)
\r
13270 BFD04854 0C00 NOP
\r
13271 1650: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
\r
13272 BFD04856 002CFC5E LW V0, 44(S8)
\r
13273 BFD0485A 000640A2 BNEZC V0, 0xBFD0486A
\r
13274 BFD0485E 0014FC5E LW V0, 20(S8)
\r
13275 BFD04862 0040FC42 LW V0, 64(V0)
\r
13276 BFD04866 000340A2 BNEZC V0, 0xBFD04870
\r
13277 BFD0486A ED01 LI V0, 1
\r
13278 BFD0486C CC02 B 0xBFD04872
\r
13279 BFD0486E 0C00 NOP
\r
13280 BFD04870 0C40 MOVE V0, ZERO
\r
13281 BFD04872 000940A2 BNEZC V0, 0xBFD04888
\r
13282 BFD04876 BFD141A2 LUI V0, 0xBFD1
\r
13283 BFD04878 3082BFD1 LDC1 F30, 12418(S1)
\r
13284 BFD0487A 9E3C3082 ADDIU A0, V0, -25028
\r
13285 BFD0487C 30A09E3C LWC1 F17, 12448(GP)
\r
13286 BFD0487E 067230A0 ADDIU A1, ZERO, 1650
\r
13287 BFD04880 0672 ADDU A0, S1, A3
\r
13288 BFD04882 4B7E77E8 JALS vAssertCalled
\r
13289 BFD04884 4B7E LW K1, 120(SP)
\r
13290 BFD04886 0C00 NOP
\r
13291 1651: configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
\r
13292 BFD04888 0014FC5E LW V0, 20(S8)
\r
13293 BFD0488C 0040FC42 LW V0, 64(V0)
\r
13294 BFD04890 000940A2 BNEZC V0, 0xBFD048A6
\r
13295 BFD04894 BFD141A2 LUI V0, 0xBFD1
\r
13296 BFD04896 3082BFD1 LDC1 F30, 12418(S1)
\r
13297 BFD04898 9E3C3082 ADDIU A0, V0, -25028
\r
13298 BFD0489A 30A09E3C LWC1 F17, 12448(GP)
\r
13299 BFD0489C 067330A0 ADDIU A1, ZERO, 1651
\r
13300 BFD0489E 0673 SUBU A0, S1, A3
\r
13301 BFD048A0 4B7E77E8 JALS vAssertCalled
\r
13302 BFD048A2 4B7E LW K1, 120(SP)
\r
13303 BFD048A4 0C00 NOP
\r
13305 1653: /* RTOS ports that support interrupt nesting have the concept of a maximum
\r
13306 1654: system call (or maximum API call) interrupt priority. Interrupts that are
\r
13307 1655: above the maximum system call priority are kept permanently enabled, even
\r
13308 1656: when the RTOS kernel is in a critical section, but cannot make any calls to
\r
13309 1657: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
\r
13310 1658: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
\r
13311 1659: failure if a FreeRTOS API function is called from an interrupt that has been
\r
13312 1660: assigned a priority above the configured maximum system call priority.
\r
13313 1661: Only FreeRTOS functions that end in FromISR can be called from interrupts
\r
13314 1662: that have been assigned a priority at or (logically) below the maximum
\r
13315 1663: system call interrupt priority. FreeRTOS maintains a separate interrupt
\r
13316 1664: safe API to ensure interrupt entry is as fast and as simple as possible.
\r
13317 1665: More information (albeit Cortex-M specific) is provided on the following
\r
13318 1666: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
\r
13319 1667: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
\r
13321 1669: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
13322 BFD048A6 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
13323 BFD048AA 0C00 NOP
\r
13324 BFD048AC 0018F85E SW V0, 24(S8)
\r
13326 1671: /* Cannot block in an ISR, so check there is data available. */
\r
13327 1672: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
\r
13328 BFD048B0 0014FC5E LW V0, 20(S8)
\r
13329 BFD048B4 692E LW V0, 56(V0)
\r
13330 BFD048B6 001640E2 BEQZC V0, 0xBFD048E6
\r
13332 1674: traceQUEUE_PEEK_FROM_ISR( pxQueue );
\r
13334 1676: /* Remember the read position so it can be reset as nothing is
\r
13335 1677: actually being removed from the queue. */
\r
13336 1678: pcOriginalReadPosition = pxQueue->u.pcReadFrom;
\r
13337 BFD048BA 0014FC5E LW V0, 20(S8)
\r
13338 BFD048BE 6923 LW V0, 12(V0)
\r
13339 BFD048C0 001CF85E SW V0, 28(S8)
\r
13340 1679: prvCopyDataFromQueue( pxQueue, pvBuffer );
\r
13341 BFD048C4 0014FC9E LW A0, 20(S8)
\r
13342 BFD048C8 002CFCBE LW A1, 44(S8)
\r
13343 BFD048CC 367A77E8 JALS prvCopyDataFromQueue
\r
13344 BFD048CE 0C00367A LHU S3, 3072(K0)
\r
13345 BFD048D0 0C00 NOP
\r
13346 1680: pxQueue->u.pcReadFrom = pcOriginalReadPosition;
\r
13347 BFD048D2 0014FC5E LW V0, 20(S8)
\r
13348 BFD048D6 001CFC7E LW V1, 28(S8)
\r
13349 BFD048DA E9A3 SW V1, 12(V0)
\r
13351 1682: xReturn = pdPASS;
\r
13352 BFD048DC ED01 LI V0, 1
\r
13353 BFD048DE 0010F85E SW V0, 16(S8)
\r
13354 BFD048E2 CC03 B 0xBFD048EA
\r
13355 BFD048E4 0C00 NOP
\r
13359 1686: xReturn = pdFAIL;
\r
13360 BFD048E6 0010F81E SW ZERO, 16(S8)
\r
13361 1687: traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
\r
13364 1690: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
13365 BFD048EA 0018FC9E LW A0, 24(S8)
\r
13366 BFD048EE 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
13367 BFD048F0 4D5E ADDIU T2, T2, -1
\r
13368 BFD048F2 0C00 NOP
\r
13370 1692: return xReturn;
\r
13371 BFD048F4 0010FC5E LW V0, 16(S8)
\r
13373 BFD048F8 0FBE MOVE SP, S8
\r
13374 BFD048FA 4BE9 LW RA, 36(SP)
\r
13375 BFD048FC 4BC8 LW S8, 32(SP)
\r
13376 BFD048FE 4C15 ADDIU SP, SP, 40
\r
13377 BFD04900 459F JR16 RA
\r
13378 BFD04902 0C00 NOP
\r
13379 1694: /*-----------------------------------------------------------*/
\r
13381 1696: UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
\r
13383 BFD08B2C 4FF1 ADDIU SP, SP, -32
\r
13384 BFD08B2E CBE7 SW RA, 28(SP)
\r
13385 BFD08B30 CBC6 SW S8, 24(SP)
\r
13386 BFD08B32 0FDD MOVE S8, SP
\r
13387 BFD08B34 0020F89E SW A0, 32(S8)
\r
13388 1698: UBaseType_t uxReturn;
\r
13390 1700: configASSERT( xQueue );
\r
13391 BFD08B38 0020FC5E LW V0, 32(S8)
\r
13392 BFD08B3C 000940A2 BNEZC V0, 0xBFD08B52
\r
13393 BFD08B40 BFD141A2 LUI V0, 0xBFD1
\r
13394 BFD08B42 3082BFD1 LDC1 F30, 12418(S1)
\r
13395 BFD08B44 9E3C3082 ADDIU A0, V0, -25028
\r
13396 BFD08B46 30A09E3C LWC1 F17, 12448(GP)
\r
13397 BFD08B48 06A430A0 ADDIU A1, ZERO, 1700
\r
13398 BFD08B4A 06A4 ADDU A1, V0, V0
\r
13399 BFD08B4C 4B7E77E8 JALS vAssertCalled
\r
13400 BFD08B4E 4B7E LW K1, 120(SP)
\r
13401 BFD08B50 0C00 NOP
\r
13403 1702: taskENTER_CRITICAL();
\r
13404 BFD08B52 33B877E8 JALS vTaskEnterCritical
\r
13405 BFD08B54 0C0033B8 ADDIU SP, T8, 3072
\r
13406 BFD08B56 0C00 NOP
\r
13408 1704: uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
\r
13409 BFD08B58 0020FC5E LW V0, 32(S8)
\r
13410 BFD08B5C 692E LW V0, 56(V0)
\r
13411 BFD08B5E 0010F85E SW V0, 16(S8)
\r
13413 1706: taskEXIT_CRITICAL();
\r
13414 BFD08B62 40AA77E8 JALS vTaskExitCritical
\r
13415 BFD08B64 0C0040AA BNEZC T2, 0xBFD0A368
\r
13416 BFD08B66 0C00 NOP
\r
13418 1708: return uxReturn;
\r
13419 BFD08B68 0010FC5E LW V0, 16(S8)
\r
13420 1709: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
\r
13421 BFD08B6C 0FBE MOVE SP, S8
\r
13422 BFD08B6E 4BE7 LW RA, 28(SP)
\r
13423 BFD08B70 4BC6 LW S8, 24(SP)
\r
13424 BFD08B72 4C11 ADDIU SP, SP, 32
\r
13425 BFD08B74 459F JR16 RA
\r
13426 BFD08B76 0C00 NOP
\r
13427 1710: /*-----------------------------------------------------------*/
\r
13429 1712: UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
\r
13431 BFD082D4 4FF1 ADDIU SP, SP, -32
\r
13432 BFD082D6 CBE7 SW RA, 28(SP)
\r
13433 BFD082D8 CBC6 SW S8, 24(SP)
\r
13434 BFD082DA 0FDD MOVE S8, SP
\r
13435 BFD082DC 0020F89E SW A0, 32(S8)
\r
13436 1714: UBaseType_t uxReturn;
\r
13437 1715: Queue_t *pxQueue;
\r
13439 1717: pxQueue = ( Queue_t * ) xQueue;
\r
13440 BFD082E0 0020FC5E LW V0, 32(S8)
\r
13441 BFD082E4 0010F85E SW V0, 16(S8)
\r
13442 1718: configASSERT( pxQueue );
\r
13443 BFD082E8 0010FC5E LW V0, 16(S8)
\r
13444 BFD082EC 000940A2 BNEZC V0, 0xBFD08302
\r
13445 BFD082F0 BFD141A2 LUI V0, 0xBFD1
\r
13446 BFD082F2 3082BFD1 LDC1 F30, 12418(S1)
\r
13447 BFD082F4 9E3C3082 ADDIU A0, V0, -25028
\r
13448 BFD082F6 30A09E3C LWC1 F17, 12448(GP)
\r
13449 BFD082F8 06B630A0 ADDIU A1, ZERO, 1718
\r
13450 BFD082FA 06B6 ADDU A1, V1, V1
\r
13451 BFD082FC 4B7E77E8 JALS vAssertCalled
\r
13452 BFD082FE 4B7E LW K1, 120(SP)
\r
13453 BFD08300 0C00 NOP
\r
13455 1720: taskENTER_CRITICAL();
\r
13456 BFD08302 33B877E8 JALS vTaskEnterCritical
\r
13457 BFD08304 0C0033B8 ADDIU SP, T8, 3072
\r
13458 BFD08306 0C00 NOP
\r
13460 1722: uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
\r
13461 BFD08308 0010FC5E LW V0, 16(S8)
\r
13462 BFD0830C 69AF LW V1, 60(V0)
\r
13463 BFD0830E 0010FC5E LW V0, 16(S8)
\r
13464 BFD08312 692E LW V0, 56(V0)
\r
13465 BFD08314 0527 SUBU V0, V1, V0
\r
13466 BFD08316 0014F85E SW V0, 20(S8)
\r
13468 1724: taskEXIT_CRITICAL();
\r
13469 BFD0831A 40AA77E8 JALS vTaskExitCritical
\r
13470 BFD0831C 0C0040AA BNEZC T2, 0xBFD09B20
\r
13471 BFD0831E 0C00 NOP
\r
13473 1726: return uxReturn;
\r
13474 BFD08320 0014FC5E LW V0, 20(S8)
\r
13475 1727: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
\r
13476 BFD08324 0FBE MOVE SP, S8
\r
13477 BFD08326 4BE7 LW RA, 28(SP)
\r
13478 BFD08328 4BC6 LW S8, 24(SP)
\r
13479 BFD0832A 4C11 ADDIU SP, SP, 32
\r
13480 BFD0832C 459F JR16 RA
\r
13481 BFD0832E 0C00 NOP
\r
13482 1728: /*-----------------------------------------------------------*/
\r
13484 1730: UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
\r
13486 BFD09360 4FF1 ADDIU SP, SP, -32
\r
13487 BFD09362 CBE7 SW RA, 28(SP)
\r
13488 BFD09364 CBC6 SW S8, 24(SP)
\r
13489 BFD09366 0FDD MOVE S8, SP
\r
13490 BFD09368 0020F89E SW A0, 32(S8)
\r
13491 1732: UBaseType_t uxReturn;
\r
13493 1734: configASSERT( xQueue );
\r
13494 BFD0936C 0020FC5E LW V0, 32(S8)
\r
13495 BFD09370 000940A2 BNEZC V0, 0xBFD09386
\r
13496 BFD09374 BFD141A2 LUI V0, 0xBFD1
\r
13497 BFD09376 3082BFD1 LDC1 F30, 12418(S1)
\r
13498 BFD09378 9E3C3082 ADDIU A0, V0, -25028
\r
13499 BFD0937A 30A09E3C LWC1 F17, 12448(GP)
\r
13500 BFD0937C 06C630A0 ADDIU A1, ZERO, 1734
\r
13501 BFD0937E 06C6 ADDU A1, V1, A0
\r
13502 BFD09380 4B7E77E8 JALS vAssertCalled
\r
13503 BFD09382 4B7E LW K1, 120(SP)
\r
13504 BFD09384 0C00 NOP
\r
13506 1736: uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
\r
13507 BFD09386 0020FC5E LW V0, 32(S8)
\r
13508 BFD0938A 692E LW V0, 56(V0)
\r
13509 BFD0938C 0010F85E SW V0, 16(S8)
\r
13511 1738: return uxReturn;
\r
13512 BFD09390 0010FC5E LW V0, 16(S8)
\r
13513 1739: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
\r
13514 BFD09394 0FBE MOVE SP, S8
\r
13515 BFD09396 4BE7 LW RA, 28(SP)
\r
13516 BFD09398 4BC6 LW S8, 24(SP)
\r
13517 BFD0939A 4C11 ADDIU SP, SP, 32
\r
13518 BFD0939C 459F JR16 RA
\r
13519 BFD0939E 0C00 NOP
\r
13520 1740: /*-----------------------------------------------------------*/
\r
13522 1742: void vQueueDelete( QueueHandle_t xQueue )
\r
13524 BFD09188 4FF1 ADDIU SP, SP, -32
\r
13525 BFD0918A CBE7 SW RA, 28(SP)
\r
13526 BFD0918C CBC6 SW S8, 24(SP)
\r
13527 BFD0918E 0FDD MOVE S8, SP
\r
13528 BFD09190 0020F89E SW A0, 32(S8)
\r
13529 1744: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
13530 BFD09194 0020FC5E LW V0, 32(S8)
\r
13531 BFD09198 0010F85E SW V0, 16(S8)
\r
13533 1746: configASSERT( pxQueue );
\r
13534 BFD0919C 0010FC5E LW V0, 16(S8)
\r
13535 BFD091A0 000940A2 BNEZC V0, 0xBFD091B6
\r
13536 BFD091A4 BFD141A2 LUI V0, 0xBFD1
\r
13537 BFD091A6 3082BFD1 LDC1 F30, 12418(S1)
\r
13538 BFD091A8 9E3C3082 ADDIU A0, V0, -25028
\r
13539 BFD091AA 30A09E3C LWC1 F17, 12448(GP)
\r
13540 BFD091AC 06D230A0 ADDIU A1, ZERO, 1746
\r
13541 BFD091AE 06D2 ADDU A1, S1, A1
\r
13542 BFD091B0 4B7E77E8 JALS vAssertCalled
\r
13543 BFD091B2 4B7E LW K1, 120(SP)
\r
13544 BFD091B4 0C00 NOP
\r
13546 1748: traceQUEUE_DELETE( pxQueue );
\r
13547 1749: #if ( configQUEUE_REGISTRY_SIZE > 0 )
\r
13549 1751: vQueueUnregisterQueue( pxQueue );
\r
13552 1754: vPortFree( pxQueue );
\r
13553 BFD091B6 0010FC9E LW A0, 16(S8)
\r
13554 BFD091BA 2FEA77E8 JALS vPortFree
\r
13555 BFD091BC 2FEA ANDI A3, A2, 0x20
\r
13556 BFD091BE 0C00 NOP
\r
13558 BFD091C0 0FBE MOVE SP, S8
\r
13559 BFD091C2 4BE7 LW RA, 28(SP)
\r
13560 BFD091C4 4BC6 LW S8, 24(SP)
\r
13561 BFD091C6 4C11 ADDIU SP, SP, 32
\r
13562 BFD091C8 459F JR16 RA
\r
13563 BFD091CA 0C00 NOP
\r
13564 1756: /*-----------------------------------------------------------*/
\r
13566 1758: #if ( configUSE_TRACE_FACILITY == 1 )
\r
13568 1760: UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
\r
13570 1762: return ( ( Queue_t * ) xQueue )->uxQueueNumber;
\r
13573 1765: #endif /* configUSE_TRACE_FACILITY */
\r
13574 1766: /*-----------------------------------------------------------*/
\r
13576 1768: #if ( configUSE_TRACE_FACILITY == 1 )
\r
13578 1770: void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
\r
13580 1772: ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
\r
13583 1775: #endif /* configUSE_TRACE_FACILITY */
\r
13584 1776: /*-----------------------------------------------------------*/
\r
13586 1778: #if ( configUSE_TRACE_FACILITY == 1 )
\r
13588 1780: uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
\r
13590 1782: return ( ( Queue_t * ) xQueue )->ucQueueType;
\r
13593 1785: #endif /* configUSE_TRACE_FACILITY */
\r
13594 1786: /*-----------------------------------------------------------*/
\r
13596 1788: static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
\r
13598 BFD029CC 4FF1 ADDIU SP, SP, -32
\r
13599 BFD029CE CBE7 SW RA, 28(SP)
\r
13600 BFD029D0 CBC6 SW S8, 24(SP)
\r
13601 BFD029D2 0FDD MOVE S8, SP
\r
13602 BFD029D4 0020F89E SW A0, 32(S8)
\r
13603 BFD029D8 0024F8BE SW A1, 36(S8)
\r
13604 BFD029DC 0028F8DE SW A2, 40(S8)
\r
13605 1790: BaseType_t xReturn = pdFALSE;
\r
13606 BFD029E0 0010F81E SW ZERO, 16(S8)
\r
13608 1792: if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
\r
13609 BFD029E4 0020FC5E LW V0, 32(S8)
\r
13610 BFD029E8 0040FC42 LW V0, 64(V0)
\r
13611 BFD029EC 001340A2 BNEZC V0, 0xBFD02A16
\r
13613 1794: #if ( configUSE_MUTEXES == 1 )
\r
13615 1796: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
\r
13616 BFD029F0 0020FC5E LW V0, 32(S8)
\r
13617 BFD029F4 6920 LW V0, 0(V0)
\r
13618 BFD029F6 008140A2 BNEZC V0, 0xBFD02AFC
\r
13620 1798: /* The mutex is no longer being held. */
\r
13621 1799: xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
\r
13622 BFD029FA 0020FC5E LW V0, 32(S8)
\r
13623 BFD029FE 6921 LW V0, 4(V0)
\r
13624 BFD02A00 0C82 MOVE A0, V0
\r
13625 BFD02A02 178277E8 JALS xTaskPriorityDisinherit
\r
13626 BFD02A04 0C001782 LBU GP, 3072(V0)
\r
13627 BFD02A06 0C00 NOP
\r
13628 BFD02A08 0010F85E SW V0, 16(S8)
\r
13629 1800: pxQueue->pxMutexHolder = NULL;
\r
13630 BFD02A0C 0020FC5E LW V0, 32(S8)
\r
13631 BFD02A10 E821 SW S0, 4(V0)
\r
13632 BFD02A12 CC74 B 0xBFD02AFC
\r
13633 BFD02A14 0C00 NOP
\r
13637 1804: mtCOVERAGE_TEST_MARKER();
\r
13640 1807: #endif /* configUSE_MUTEXES */
\r
13642 1809: else if( xPosition == queueSEND_TO_BACK )
\r
13643 BFD02A16 0028FC5E LW V0, 40(S8)
\r
13644 BFD02A1A 002B40A2 BNEZC V0, 0xBFD02A74
\r
13646 1811: ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
\r
13647 BFD02A1E 0020FC5E LW V0, 32(S8)
\r
13648 BFD02A22 69A2 LW V1, 8(V0)
\r
13649 BFD02A24 0020FC5E LW V0, 32(S8)
\r
13650 BFD02A28 0040FC42 LW V0, 64(V0)
\r
13651 BFD02A2C 0C83 MOVE A0, V1
\r
13652 BFD02A2E 0024FCBE LW A1, 36(S8)
\r
13653 BFD02A32 0CC2 MOVE A2, V0
\r
13654 BFD02A34 1BB477E8 JALS 0xBFD03768
\r
13655 BFD02A36 0C001BB4 SB SP, 3072(S4)
\r
13656 BFD02A38 0C00 NOP
\r
13657 1812: pxQueue->pcWriteTo += pxQueue->uxItemSize;
\r
13658 BFD02A3A 0020FC5E LW V0, 32(S8)
\r
13659 BFD02A3E 69A2 LW V1, 8(V0)
\r
13660 BFD02A40 0020FC5E LW V0, 32(S8)
\r
13661 BFD02A44 0040FC42 LW V0, 64(V0)
\r
13662 BFD02A48 05A6 ADDU V1, V1, V0
\r
13663 BFD02A4A 0020FC5E LW V0, 32(S8)
\r
13664 BFD02A4E E9A2 SW V1, 8(V0)
\r
13665 1813: if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
\r
13666 BFD02A50 0020FC5E LW V0, 32(S8)
\r
13667 BFD02A54 69A2 LW V1, 8(V0)
\r
13668 BFD02A56 0020FC5E LW V0, 32(S8)
\r
13669 BFD02A5A 6921 LW V0, 4(V0)
\r
13670 BFD02A5C 13900043 SLTU V0, V1, V0
\r
13671 BFD02A5E 40A21390 ADDI GP, S0, 16546
\r
13672 BFD02A60 004C40A2 BNEZC V0, 0xBFD02AFC
\r
13674 1815: pxQueue->pcWriteTo = pxQueue->pcHead;
\r
13675 BFD02A64 0020FC5E LW V0, 32(S8)
\r
13676 BFD02A68 69A0 LW V1, 0(V0)
\r
13677 BFD02A6A 0020FC5E LW V0, 32(S8)
\r
13678 BFD02A6E E9A2 SW V1, 8(V0)
\r
13679 BFD02A70 CC45 B 0xBFD02AFC
\r
13680 BFD02A72 0C00 NOP
\r
13684 1819: mtCOVERAGE_TEST_MARKER();
\r
13689 1824: ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
\r
13690 BFD02A74 0020FC5E LW V0, 32(S8)
\r
13691 BFD02A78 69A3 LW V1, 12(V0)
\r
13692 BFD02A7A 0020FC5E LW V0, 32(S8)
\r
13693 BFD02A7E 0040FC42 LW V0, 64(V0)
\r
13694 BFD02A82 0C83 MOVE A0, V1
\r
13695 BFD02A84 0024FCBE LW A1, 36(S8)
\r
13696 BFD02A88 0CC2 MOVE A2, V0
\r
13697 BFD02A8A 1BB477E8 JALS 0xBFD03768
\r
13698 BFD02A8C 0C001BB4 SB SP, 3072(S4)
\r
13699 BFD02A8E 0C00 NOP
\r
13700 1825: pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
\r
13701 BFD02A90 0020FC5E LW V0, 32(S8)
\r
13702 BFD02A94 69A3 LW V1, 12(V0)
\r
13703 BFD02A96 0020FC5E LW V0, 32(S8)
\r
13704 BFD02A9A 0040FC42 LW V0, 64(V0)
\r
13705 BFD02A9C 00400040 SRL V0, ZERO, 0
\r
13706 BFD02A9E 11D00040 SUBU V0, ZERO, V0
\r
13707 BFD02AA0 05A611D0 ADDI T6, S0, 1446
\r
13708 BFD02AA2 05A6 ADDU V1, V1, V0
\r
13709 BFD02AA4 0020FC5E LW V0, 32(S8)
\r
13710 BFD02AA8 E9A3 SW V1, 12(V0)
\r
13711 1826: if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
\r
13712 BFD02AAA 0020FC5E LW V0, 32(S8)
\r
13713 BFD02AAE 69A3 LW V1, 12(V0)
\r
13714 BFD02AB0 0020FC5E LW V0, 32(S8)
\r
13715 BFD02AB4 6920 LW V0, 0(V0)
\r
13716 BFD02AB6 13900043 SLTU V0, V1, V0
\r
13717 BFD02AB8 40E21390 ADDI GP, S0, 16610
\r
13718 BFD02ABA 000D40E2 BEQZC V0, 0xBFD02AD8
\r
13720 1828: pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
\r
13721 BFD02ABE 0020FC5E LW V0, 32(S8)
\r
13722 BFD02AC2 69A1 LW V1, 4(V0)
\r
13723 BFD02AC4 0020FC5E LW V0, 32(S8)
\r
13724 BFD02AC8 0040FC42 LW V0, 64(V0)
\r
13725 BFD02ACA 00400040 SRL V0, ZERO, 0
\r
13726 BFD02ACC 11D00040 SUBU V0, ZERO, V0
\r
13727 BFD02ACE 05A611D0 ADDI T6, S0, 1446
\r
13728 BFD02AD0 05A6 ADDU V1, V1, V0
\r
13729 BFD02AD2 0020FC5E LW V0, 32(S8)
\r
13730 BFD02AD6 E9A3 SW V1, 12(V0)
\r
13734 1832: mtCOVERAGE_TEST_MARKER();
\r
13737 1835: if( xPosition == queueOVERWRITE )
\r
13738 BFD02AD8 0028FC7E LW V1, 40(S8)
\r
13739 BFD02ADC ED02 LI V0, 2
\r
13740 BFD02ADE 000DB443 BNE V1, V0, 0xBFD02AFC
\r
13741 BFD02AE0 0C00000D SLL ZERO, T5, 1
\r
13742 BFD02AE2 0C00 NOP
\r
13744 1837: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
\r
13745 BFD02AE4 0020FC5E LW V0, 32(S8)
\r
13746 BFD02AE8 692E LW V0, 56(V0)
\r
13747 BFD02AEA 000740E2 BEQZC V0, 0xBFD02AFC
\r
13749 1839: /* An item is not being added but overwritten, so subtract
\r
13750 1840: one from the recorded number of items in the queue so when
\r
13751 1841: one is added again below the number of recorded items remains
\r
13752 1842: correct. */
\r
13753 1843: --( pxQueue->uxMessagesWaiting );
\r
13754 BFD02AEE 0020FC5E LW V0, 32(S8)
\r
13755 BFD02AF2 692E LW V0, 56(V0)
\r
13756 BFD02AF4 6DAE ADDIU V1, V0, -1
\r
13757 BFD02AF6 0020FC5E LW V0, 32(S8)
\r
13758 BFD02AFA E9AE SW V1, 56(V0)
\r
13762 1847: mtCOVERAGE_TEST_MARKER();
\r
13767 1852: mtCOVERAGE_TEST_MARKER();
\r
13771 1856: ++( pxQueue->uxMessagesWaiting );
\r
13772 BFD02AFC 0020FC5E LW V0, 32(S8)
\r
13773 BFD02B00 692E LW V0, 56(V0)
\r
13774 BFD02B02 6DA0 ADDIU V1, V0, 1
\r
13775 BFD02B04 0020FC5E LW V0, 32(S8)
\r
13776 BFD02B08 E9AE SW V1, 56(V0)
\r
13778 1858: return xReturn;
\r
13779 BFD02B0A 0010FC5E LW V0, 16(S8)
\r
13781 BFD02B0E 0FBE MOVE SP, S8
\r
13782 BFD02B10 4BE7 LW RA, 28(SP)
\r
13783 BFD02B12 4BC6 LW S8, 24(SP)
\r
13784 BFD02B14 4C11 ADDIU SP, SP, 32
\r
13785 BFD02B16 459F JR16 RA
\r
13786 BFD02B18 0C00 NOP
\r
13787 1860: /*-----------------------------------------------------------*/
\r
13789 1862: static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
\r
13791 BFD06CF4 4FF5 ADDIU SP, SP, -24
\r
13792 BFD06CF6 CBE5 SW RA, 20(SP)
\r
13793 BFD06CF8 CBC4 SW S8, 16(SP)
\r
13794 BFD06CFA 0FDD MOVE S8, SP
\r
13795 BFD06CFC 0018F89E SW A0, 24(S8)
\r
13796 BFD06D00 001CF8BE SW A1, 28(S8)
\r
13797 1864: if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
\r
13798 BFD06D04 0018FC5E LW V0, 24(S8)
\r
13799 BFD06D08 0040FC42 LW V0, 64(V0)
\r
13800 BFD06D0C 002940E2 BEQZC V0, 0xBFD06D62
\r
13802 1866: pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
\r
13803 BFD06D10 0018FC5E LW V0, 24(S8)
\r
13804 BFD06D14 69A3 LW V1, 12(V0)
\r
13805 BFD06D16 0018FC5E LW V0, 24(S8)
\r
13806 BFD06D1A 0040FC42 LW V0, 64(V0)
\r
13807 BFD06D1E 05A6 ADDU V1, V1, V0
\r
13808 BFD06D20 0018FC5E LW V0, 24(S8)
\r
13809 BFD06D24 E9A3 SW V1, 12(V0)
\r
13810 1867: if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
\r
13811 BFD06D26 0018FC5E LW V0, 24(S8)
\r
13812 BFD06D2A 69A3 LW V1, 12(V0)
\r
13813 BFD06D2C 0018FC5E LW V0, 24(S8)
\r
13814 BFD06D30 6921 LW V0, 4(V0)
\r
13815 BFD06D32 13900043 SLTU V0, V1, V0
\r
13816 BFD06D34 40A21390 ADDI GP, S0, 16546
\r
13817 BFD06D36 000640A2 BNEZC V0, 0xBFD06D46
\r
13819 1869: pxQueue->u.pcReadFrom = pxQueue->pcHead;
\r
13820 BFD06D3A 0018FC5E LW V0, 24(S8)
\r
13821 BFD06D3E 69A0 LW V1, 0(V0)
\r
13822 BFD06D40 0018FC5E LW V0, 24(S8)
\r
13823 BFD06D44 E9A3 SW V1, 12(V0)
\r
13827 1873: mtCOVERAGE_TEST_MARKER();
\r
13829 1875: ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
\r
13830 BFD06D46 0018FC5E LW V0, 24(S8)
\r
13831 BFD06D4A 69A3 LW V1, 12(V0)
\r
13832 BFD06D4C 0018FC5E LW V0, 24(S8)
\r
13833 BFD06D50 0040FC42 LW V0, 64(V0)
\r
13834 BFD06D54 001CFC9E LW A0, 28(S8)
\r
13835 BFD06D58 0CA3 MOVE A1, V1
\r
13836 BFD06D5A 0CC2 MOVE A2, V0
\r
13837 BFD06D5C 1BB477E8 JALS 0xBFD03768
\r
13838 BFD06D5E 0C001BB4 SB SP, 3072(S4)
\r
13839 BFD06D60 0C00 NOP
\r
13842 BFD06D62 0FBE MOVE SP, S8
\r
13843 BFD06D64 4BE5 LW RA, 20(SP)
\r
13844 BFD06D66 4BC4 LW S8, 16(SP)
\r
13845 BFD06D68 4C0D ADDIU SP, SP, 24
\r
13846 BFD06D6A 459F JR16 RA
\r
13847 BFD06D6C 0C00 NOP
\r
13848 1878: /*-----------------------------------------------------------*/
\r
13850 1880: static void prvUnlockQueue( Queue_t * const pxQueue )
\r
13852 BFD03BDC 4FF5 ADDIU SP, SP, -24
\r
13853 BFD03BDE CBE5 SW RA, 20(SP)
\r
13854 BFD03BE0 CBC4 SW S8, 16(SP)
\r
13855 BFD03BE2 0FDD MOVE S8, SP
\r
13856 BFD03BE4 0018F89E SW A0, 24(S8)
\r
13857 1882: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
\r
13859 1884: /* The lock counts contains the number of extra data items placed or
\r
13860 1885: removed from the queue while the queue was locked. When a queue is
\r
13861 1886: locked items can be added or removed, but the event lists cannot be
\r
13862 1887: updated. */
\r
13863 1888: taskENTER_CRITICAL();
\r
13864 BFD03BE8 33B877E8 JALS vTaskEnterCritical
\r
13865 BFD03BEA 0C0033B8 ADDIU SP, T8, 3072
\r
13866 BFD03BEC 0C00 NOP
\r
13868 1890: /* See if data was added to the queue while it was locked. */
\r
13869 1891: while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )
\r
13870 BFD03BEE CC32 B 0xBFD03C54
\r
13871 BFD03BF0 0C00 NOP
\r
13872 BFD03C54 0018FC5E LW V0, 24(S8)
\r
13873 BFD03C58 0048FC42 LW V0, 72(V0)
\r
13874 BFD03C5C FFC940C2 BGTZ V0, 0xBFD03BF2
\r
13875 BFD03C5E 0C00FFC9 LW S8, 3072(T1)
\r
13876 BFD03C60 0C00 NOP
\r
13877 BFD03C62 CC02 B 0xBFD03C68
\r
13878 BFD03C64 0C00 NOP
\r
13880 1893: /* Data was posted while the queue was locked. Are any tasks
\r
13881 1894: blocked waiting for data to become available? */
\r
13882 1895: #if ( configUSE_QUEUE_SETS == 1 )
\r
13884 1897: if( pxQueue->pxQueueSetContainer != NULL )
\r
13885 BFD03BF2 0018FC5E LW V0, 24(S8)
\r
13886 BFD03BF6 004CFC42 LW V0, 76(V0)
\r
13887 BFD03BFA 001040E2 BEQZC V0, 0xBFD03C1E
\r
13889 1899: if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )
\r
13890 BFD03BFE 0018FC9E LW A0, 24(S8)
\r
13891 BFD03C02 0CA0 MOVE A1, ZERO
\r
13892 BFD03C04 21D877E8 JALS prvNotifyQueueSetContainer
\r
13893 BFD03C06 0C0021D8 LWC2 T6, 3072(T8)
\r
13894 BFD03C08 0C00 NOP
\r
13895 BFD03C0A 0C62 MOVE V1, V0
\r
13896 BFD03C0C ED01 LI V0, 1
\r
13897 BFD03C0E 0018B443 BNE V1, V0, 0xBFD03C42
\r
13898 BFD03C10 0C000018 SLL ZERO, T8, 1
\r
13899 BFD03C12 0C00 NOP
\r
13901 1901: /* The queue is a member of a queue set, and posting to
\r
13902 1902: the queue set caused a higher priority task to unblock.
\r
13903 1903: A context switch is required. */
\r
13904 1904: vTaskMissedYield();
\r
13905 BFD03C14 4F2A77E8 JALS vTaskMissedYield
\r
13906 BFD03C16 4F2A ADDIU T9, T9, 5
\r
13907 BFD03C18 0C00 NOP
\r
13908 BFD03C1A CC13 B 0xBFD03C42
\r
13909 BFD03C1C 0C00 NOP
\r
13913 1908: mtCOVERAGE_TEST_MARKER();
\r
13918 1913: /* Tasks that are removed from the event list will get added to
\r
13919 1914: the pending ready list as the scheduler is still suspended. */
\r
13920 1915: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
13921 BFD03C1E 0018FC5E LW V0, 24(S8)
\r
13922 BFD03C22 6929 LW V0, 36(V0)
\r
13923 BFD03C24 001F40E2 BEQZC V0, 0xBFD03C66
\r
13925 1917: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
13926 BFD03C28 0018FC5E LW V0, 24(S8)
\r
13927 BFD03C2C 00243042 ADDIU V0, V0, 36
\r
13928 BFD03C30 0C82 MOVE A0, V0
\r
13929 BFD03C32 22BC77E8 JALS xTaskRemoveFromEventList
\r
13930 BFD03C34 0C0022BC LWC2 S5, 3072(GP)
\r
13931 BFD03C36 0C00 NOP
\r
13932 BFD03C38 000340E2 BEQZC V0, 0xBFD03C42
\r
13934 1919: /* The task waiting has a higher priority so record that a
\r
13935 1920: context switch is required. */
\r
13936 1921: vTaskMissedYield();
\r
13937 BFD03C3C 4F2A77E8 JALS vTaskMissedYield
\r
13938 BFD03C3E 4F2A ADDIU T9, T9, 5
\r
13939 BFD03C40 0C00 NOP
\r
13943 1925: mtCOVERAGE_TEST_MARKER();
\r
13949 BFD03C66 0C00 NOP
\r
13953 1934: #else /* configUSE_QUEUE_SETS */
\r
13955 1936: /* Tasks that are removed from the event list will get added to
\r
13956 1937: the pending ready list as the scheduler is still suspended. */
\r
13957 1938: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
13959 1940: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
13961 1942: /* The task waiting has a higher priority so record that a
\r
13962 1943: context switch is required. */
\r
13963 1944: vTaskMissedYield();
\r
13967 1948: mtCOVERAGE_TEST_MARKER();
\r
13975 1956: #endif /* configUSE_QUEUE_SETS */
\r
13977 1958: --( pxQueue->xTxLock );
\r
13978 BFD03C42 0018FC5E LW V0, 24(S8)
\r
13979 BFD03C46 0048FC42 LW V0, 72(V0)
\r
13980 BFD03C4A 6DAE ADDIU V1, V0, -1
\r
13981 BFD03C4C 0018FC5E LW V0, 24(S8)
\r
13982 BFD03C50 0048F862 SW V1, 72(V0)
\r
13985 1961: pxQueue->xTxLock = queueUNLOCKED;
\r
13986 BFD03C68 0018FC5E LW V0, 24(S8)
\r
13987 BFD03C6C EDFF LI V1, -1
\r
13988 BFD03C6E 0048F862 SW V1, 72(V0)
\r
13990 1963: taskEXIT_CRITICAL();
\r
13991 BFD03C72 40AA77E8 JALS vTaskExitCritical
\r
13992 BFD03C74 0C0040AA BNEZC T2, 0xBFD05478
\r
13993 BFD03C76 0C00 NOP
\r
13995 1965: /* Do the same for the Rx lock. */
\r
13996 1966: taskENTER_CRITICAL();
\r
13997 BFD03C78 33B877E8 JALS vTaskEnterCritical
\r
13998 BFD03C7A 0C0033B8 ADDIU SP, T8, 3072
\r
13999 BFD03C7C 0C00 NOP
\r
14001 1968: while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )
\r
14002 BFD03C7E CC1B B 0xBFD03CB6
\r
14003 BFD03C80 0C00 NOP
\r
14004 BFD03CB6 0018FC5E LW V0, 24(S8)
\r
14005 BFD03CBA 0044FC42 LW V0, 68(V0)
\r
14006 BFD03CBE FFE040C2 BGTZ V0, 0xBFD03C82
\r
14007 BFD03CC0 0C00FFE0 LW RA, 3072(ZERO)
\r
14008 BFD03CC2 0C00 NOP
\r
14009 BFD03CC4 CC02 B 0xBFD03CCA
\r
14010 BFD03CC6 0C00 NOP
\r
14012 1970: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
\r
14013 BFD03C82 0018FC5E LW V0, 24(S8)
\r
14014 BFD03C86 6924 LW V0, 16(V0)
\r
14015 BFD03C88 001E40E2 BEQZC V0, 0xBFD03CC8
\r
14017 1972: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
\r
14018 BFD03C8C 0018FC5E LW V0, 24(S8)
\r
14019 BFD03C90 6D28 ADDIU V0, V0, 16
\r
14020 BFD03C92 0C82 MOVE A0, V0
\r
14021 BFD03C94 22BC77E8 JALS xTaskRemoveFromEventList
\r
14022 BFD03C96 0C0022BC LWC2 S5, 3072(GP)
\r
14023 BFD03C98 0C00 NOP
\r
14024 BFD03C9A 000340E2 BEQZC V0, 0xBFD03CA4
\r
14026 1974: vTaskMissedYield();
\r
14027 BFD03C9E 4F2A77E8 JALS vTaskMissedYield
\r
14028 BFD03CA0 4F2A ADDIU T9, T9, 5
\r
14029 BFD03CA2 0C00 NOP
\r
14033 1978: mtCOVERAGE_TEST_MARKER();
\r
14036 1981: --( pxQueue->xRxLock );
\r
14037 BFD03CA4 0018FC5E LW V0, 24(S8)
\r
14038 BFD03CA8 0044FC42 LW V0, 68(V0)
\r
14039 BFD03CAC 6DAE ADDIU V1, V0, -1
\r
14040 BFD03CAE 0018FC5E LW V0, 24(S8)
\r
14041 BFD03CB2 0044F862 SW V1, 68(V0)
\r
14046 BFD03CC8 0C00 NOP
\r
14050 1989: pxQueue->xRxLock = queueUNLOCKED;
\r
14051 BFD03CCA 0018FC5E LW V0, 24(S8)
\r
14052 BFD03CCE EDFF LI V1, -1
\r
14053 BFD03CD0 0044F862 SW V1, 68(V0)
\r
14055 1991: taskEXIT_CRITICAL();
\r
14056 BFD03CD4 40AA77E8 JALS vTaskExitCritical
\r
14057 BFD03CD6 0C0040AA BNEZC T2, 0xBFD054DA
\r
14058 BFD03CD8 0C00 NOP
\r
14060 BFD03CDA 0FBE MOVE SP, S8
\r
14061 BFD03CDC 4BE5 LW RA, 20(SP)
\r
14062 BFD03CDE 4BC4 LW S8, 16(SP)
\r
14063 BFD03CE0 4C0D ADDIU SP, SP, 24
\r
14064 BFD03CE2 459F JR16 RA
\r
14065 BFD03CE4 0C00 NOP
\r
14066 1993: /*-----------------------------------------------------------*/
\r
14068 1995: static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
\r
14070 BFD093A0 4FF1 ADDIU SP, SP, -32
\r
14071 BFD093A2 CBE7 SW RA, 28(SP)
\r
14072 BFD093A4 CBC6 SW S8, 24(SP)
\r
14073 BFD093A6 0FDD MOVE S8, SP
\r
14074 BFD093A8 0020F89E SW A0, 32(S8)
\r
14075 1997: BaseType_t xReturn;
\r
14077 1999: taskENTER_CRITICAL();
\r
14078 BFD093AC 33B877E8 JALS vTaskEnterCritical
\r
14079 BFD093AE 0C0033B8 ADDIU SP, T8, 3072
\r
14080 BFD093B0 0C00 NOP
\r
14082 2001: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
\r
14083 BFD093B2 0020FC5E LW V0, 32(S8)
\r
14084 BFD093B6 692E LW V0, 56(V0)
\r
14085 BFD093B8 000540A2 BNEZC V0, 0xBFD093C6
\r
14087 2003: xReturn = pdTRUE;
\r
14088 BFD093BC ED01 LI V0, 1
\r
14089 BFD093BE 0010F85E SW V0, 16(S8)
\r
14090 BFD093C2 CC03 B 0xBFD093CA
\r
14091 BFD093C4 0C00 NOP
\r
14095 2007: xReturn = pdFALSE;
\r
14096 BFD093C6 0010F81E SW ZERO, 16(S8)
\r
14099 2010: taskEXIT_CRITICAL();
\r
14100 BFD093CA 40AA77E8 JALS vTaskExitCritical
\r
14101 BFD093CC 0C0040AA BNEZC T2, 0xBFD0ABD0
\r
14102 BFD093CE 0C00 NOP
\r
14104 2012: return xReturn;
\r
14105 BFD093D0 0010FC5E LW V0, 16(S8)
\r
14107 BFD093D4 0FBE MOVE SP, S8
\r
14108 BFD093D6 4BE7 LW RA, 28(SP)
\r
14109 BFD093D8 4BC6 LW S8, 24(SP)
\r
14110 BFD093DA 4C11 ADDIU SP, SP, 32
\r
14111 BFD093DC 459F JR16 RA
\r
14112 BFD093DE 0C00 NOP
\r
14113 2014: /*-----------------------------------------------------------*/
\r
14115 2016: BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
\r
14117 BFD08954 4FF1 ADDIU SP, SP, -32
\r
14118 BFD08956 CBE7 SW RA, 28(SP)
\r
14119 BFD08958 CBC6 SW S8, 24(SP)
\r
14120 BFD0895A 0FDD MOVE S8, SP
\r
14121 BFD0895C 0020F89E SW A0, 32(S8)
\r
14122 2018: BaseType_t xReturn;
\r
14124 2020: configASSERT( xQueue );
\r
14125 BFD08960 0020FC5E LW V0, 32(S8)
\r
14126 BFD08964 000940A2 BNEZC V0, 0xBFD0897A
\r
14127 BFD08968 BFD141A2 LUI V0, 0xBFD1
\r
14128 BFD0896A 3082BFD1 LDC1 F30, 12418(S1)
\r
14129 BFD0896C 9E3C3082 ADDIU A0, V0, -25028
\r
14130 BFD0896E 30A09E3C LWC1 F17, 12448(GP)
\r
14131 BFD08970 07E430A0 ADDIU A1, ZERO, 2020
\r
14132 BFD08972 07E4 ADDU A3, V0, A2
\r
14133 BFD08974 4B7E77E8 JALS vAssertCalled
\r
14134 BFD08976 4B7E LW K1, 120(SP)
\r
14135 BFD08978 0C00 NOP
\r
14136 2021: if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
\r
14137 BFD0897A 0020FC5E LW V0, 32(S8)
\r
14138 BFD0897E 692E LW V0, 56(V0)
\r
14139 BFD08980 000540A2 BNEZC V0, 0xBFD0898E
\r
14141 2023: xReturn = pdTRUE;
\r
14142 BFD08984 ED01 LI V0, 1
\r
14143 BFD08986 0010F85E SW V0, 16(S8)
\r
14144 BFD0898A CC03 B 0xBFD08992
\r
14145 BFD0898C 0C00 NOP
\r
14149 2027: xReturn = pdFALSE;
\r
14150 BFD0898E 0010F81E SW ZERO, 16(S8)
\r
14153 2030: return xReturn;
\r
14154 BFD08992 0010FC5E LW V0, 16(S8)
\r
14155 2031: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
\r
14156 BFD08996 0FBE MOVE SP, S8
\r
14157 BFD08998 4BE7 LW RA, 28(SP)
\r
14158 BFD0899A 4BC6 LW S8, 24(SP)
\r
14159 BFD0899C 4C11 ADDIU SP, SP, 32
\r
14160 BFD0899E 459F JR16 RA
\r
14161 BFD089A0 0C00 NOP
\r
14162 2032: /*-----------------------------------------------------------*/
\r
14164 2034: static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
\r
14166 BFD08F04 4FF1 ADDIU SP, SP, -32
\r
14167 BFD08F06 CBE7 SW RA, 28(SP)
\r
14168 BFD08F08 CBC6 SW S8, 24(SP)
\r
14169 BFD08F0A 0FDD MOVE S8, SP
\r
14170 BFD08F0C 0020F89E SW A0, 32(S8)
\r
14171 2036: BaseType_t xReturn;
\r
14173 2038: taskENTER_CRITICAL();
\r
14174 BFD08F10 33B877E8 JALS vTaskEnterCritical
\r
14175 BFD08F12 0C0033B8 ADDIU SP, T8, 3072
\r
14176 BFD08F14 0C00 NOP
\r
14178 2040: if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
\r
14179 BFD08F16 0020FC5E LW V0, 32(S8)
\r
14180 BFD08F1A 69AE LW V1, 56(V0)
\r
14181 BFD08F1C 0020FC5E LW V0, 32(S8)
\r
14182 BFD08F20 692F LW V0, 60(V0)
\r
14183 BFD08F22 0006B443 BNE V1, V0, 0xBFD08F32
\r
14184 BFD08F24 0C000006 SLL ZERO, A2, 1
\r
14185 BFD08F26 0C00 NOP
\r
14187 2042: xReturn = pdTRUE;
\r
14188 BFD08F28 ED01 LI V0, 1
\r
14189 BFD08F2A 0010F85E SW V0, 16(S8)
\r
14190 BFD08F2E CC03 B 0xBFD08F36
\r
14191 BFD08F30 0C00 NOP
\r
14195 2046: xReturn = pdFALSE;
\r
14196 BFD08F32 0010F81E SW ZERO, 16(S8)
\r
14199 2049: taskEXIT_CRITICAL();
\r
14200 BFD08F36 40AA77E8 JALS vTaskExitCritical
\r
14201 BFD08F38 0C0040AA BNEZC T2, 0xBFD0A73C
\r
14202 BFD08F3A 0C00 NOP
\r
14204 2051: return xReturn;
\r
14205 BFD08F3C 0010FC5E LW V0, 16(S8)
\r
14207 BFD08F40 0FBE MOVE SP, S8
\r
14208 BFD08F42 4BE7 LW RA, 28(SP)
\r
14209 BFD08F44 4BC6 LW S8, 24(SP)
\r
14210 BFD08F46 4C11 ADDIU SP, SP, 32
\r
14211 BFD08F48 459F JR16 RA
\r
14212 BFD08F4A 0C00 NOP
\r
14213 2053: /*-----------------------------------------------------------*/
\r
14215 2055: BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
\r
14217 BFD084F8 4FF1 ADDIU SP, SP, -32
\r
14218 BFD084FA CBE7 SW RA, 28(SP)
\r
14219 BFD084FC CBC6 SW S8, 24(SP)
\r
14220 BFD084FE 0FDD MOVE S8, SP
\r
14221 BFD08500 0020F89E SW A0, 32(S8)
\r
14222 2057: BaseType_t xReturn;
\r
14224 2059: configASSERT( xQueue );
\r
14225 BFD08504 0020FC5E LW V0, 32(S8)
\r
14226 BFD08508 000940A2 BNEZC V0, 0xBFD0851E
\r
14227 BFD0850C BFD141A2 LUI V0, 0xBFD1
\r
14228 BFD0850E 3082BFD1 LDC1 F30, 12418(S1)
\r
14229 BFD08510 9E3C3082 ADDIU A0, V0, -25028
\r
14230 BFD08512 30A09E3C LWC1 F17, 12448(GP)
\r
14231 BFD08514 080B30A0 ADDIU A1, ZERO, 2059
\r
14232 BFD08516 080B LBU S0, 11(S0)
\r
14233 BFD08518 4B7E77E8 JALS vAssertCalled
\r
14234 BFD0851A 4B7E LW K1, 120(SP)
\r
14235 BFD0851C 0C00 NOP
\r
14236 2060: if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
\r
14237 BFD0851E 0020FC5E LW V0, 32(S8)
\r
14238 BFD08522 69AE LW V1, 56(V0)
\r
14239 BFD08524 0020FC5E LW V0, 32(S8)
\r
14240 BFD08528 692F LW V0, 60(V0)
\r
14241 BFD0852A 0006B443 BNE V1, V0, 0xBFD0853A
\r
14242 BFD0852C 0C000006 SLL ZERO, A2, 1
\r
14243 BFD0852E 0C00 NOP
\r
14245 2062: xReturn = pdTRUE;
\r
14246 BFD08530 ED01 LI V0, 1
\r
14247 BFD08532 0010F85E SW V0, 16(S8)
\r
14248 BFD08536 CC03 B 0xBFD0853E
\r
14249 BFD08538 0C00 NOP
\r
14253 2066: xReturn = pdFALSE;
\r
14254 BFD0853A 0010F81E SW ZERO, 16(S8)
\r
14257 2069: return xReturn;
\r
14258 BFD0853E 0010FC5E LW V0, 16(S8)
\r
14259 2070: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
\r
14260 BFD08542 0FBE MOVE SP, S8
\r
14261 BFD08544 4BE7 LW RA, 28(SP)
\r
14262 BFD08546 4BC6 LW S8, 24(SP)
\r
14263 BFD08548 4C11 ADDIU SP, SP, 32
\r
14264 BFD0854A 459F JR16 RA
\r
14265 BFD0854C 0C00 NOP
\r
14266 2071: /*-----------------------------------------------------------*/
\r
14268 2073: #if ( configUSE_CO_ROUTINES == 1 )
\r
14270 2075: BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
\r
14272 2077: BaseType_t xReturn;
\r
14273 2078: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
14275 2080: /* If the queue is already full we may have to block. A critical section
\r
14276 2081: is required to prevent an interrupt removing something from the queue
\r
14277 2082: between the check to see if the queue is full and blocking on the queue. */
\r
14278 2083: portDISABLE_INTERRUPTS();
\r
14280 2085: if( prvIsQueueFull( pxQueue ) != pdFALSE )
\r
14282 2087: /* The queue is full - do we want to block or just leave without
\r
14283 2088: posting? */
\r
14284 2089: if( xTicksToWait > ( TickType_t ) 0 )
\r
14286 2091: /* As this is called from a coroutine we cannot block directly, but
\r
14287 2092: return indicating that we need to block. */
\r
14288 2093: vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
\r
14289 2094: portENABLE_INTERRUPTS();
\r
14290 2095: return errQUEUE_BLOCKED;
\r
14294 2099: portENABLE_INTERRUPTS();
\r
14295 2100: return errQUEUE_FULL;
\r
14299 2104: portENABLE_INTERRUPTS();
\r
14301 2106: portDISABLE_INTERRUPTS();
\r
14303 2108: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
\r
14305 2110: /* There is room in the queue, copy the data into the queue. */
\r
14306 2111: prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
\r
14307 2112: xReturn = pdPASS;
\r
14309 2114: /* Were any co-routines waiting for data to become available? */
\r
14310 2115: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
14312 2117: /* In this instance the co-routine could be placed directly
\r
14313 2118: into the ready list as we are within a critical section.
\r
14314 2119: Instead the same pending ready list mechanism is used as if
\r
14315 2120: the event were caused from within an interrupt. */
\r
14316 2121: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
14318 2123: /* The co-routine waiting has a higher priority so record
\r
14319 2124: that a yield might be appropriate. */
\r
14320 2125: xReturn = errQUEUE_YIELD;
\r
14324 2129: mtCOVERAGE_TEST_MARKER();
\r
14329 2134: mtCOVERAGE_TEST_MARKER();
\r
14334 2139: xReturn = errQUEUE_FULL;
\r
14337 2142: portENABLE_INTERRUPTS();
\r
14339 2144: return xReturn;
\r
14342 2147: #endif /* configUSE_CO_ROUTINES */
\r
14343 2148: /*-----------------------------------------------------------*/
\r
14345 2150: #if ( configUSE_CO_ROUTINES == 1 )
\r
14347 2152: BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
\r
14349 2154: BaseType_t xReturn;
\r
14350 2155: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
14352 2157: /* If the queue is already empty we may have to block. A critical section
\r
14353 2158: is required to prevent an interrupt adding something to the queue
\r
14354 2159: between the check to see if the queue is empty and blocking on the queue. */
\r
14355 2160: portDISABLE_INTERRUPTS();
\r
14357 2162: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
\r
14359 2164: /* There are no messages in the queue, do we want to block or just
\r
14360 2165: leave with nothing? */
\r
14361 2166: if( xTicksToWait > ( TickType_t ) 0 )
\r
14363 2168: /* As this is a co-routine we cannot block directly, but return
\r
14364 2169: indicating that we need to block. */
\r
14365 2170: vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
\r
14366 2171: portENABLE_INTERRUPTS();
\r
14367 2172: return errQUEUE_BLOCKED;
\r
14371 2176: portENABLE_INTERRUPTS();
\r
14372 2177: return errQUEUE_FULL;
\r
14377 2182: mtCOVERAGE_TEST_MARKER();
\r
14380 2185: portENABLE_INTERRUPTS();
\r
14382 2187: portDISABLE_INTERRUPTS();
\r
14384 2189: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
\r
14386 2191: /* Data is available from the queue. */
\r
14387 2192: pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
\r
14388 2193: if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
\r
14390 2195: pxQueue->u.pcReadFrom = pxQueue->pcHead;
\r
14394 2199: mtCOVERAGE_TEST_MARKER();
\r
14396 2201: --( pxQueue->uxMessagesWaiting );
\r
14397 2202: ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
\r
14399 2204: xReturn = pdPASS;
\r
14401 2206: /* Were any co-routines waiting for space to become available? */
\r
14402 2207: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
\r
14404 2209: /* In this instance the co-routine could be placed directly
\r
14405 2210: into the ready list as we are within a critical section.
\r
14406 2211: Instead the same pending ready list mechanism is used as if
\r
14407 2212: the event were caused from within an interrupt. */
\r
14408 2213: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
\r
14410 2215: xReturn = errQUEUE_YIELD;
\r
14414 2219: mtCOVERAGE_TEST_MARKER();
\r
14419 2224: mtCOVERAGE_TEST_MARKER();
\r
14424 2229: xReturn = pdFAIL;
\r
14427 2232: portENABLE_INTERRUPTS();
\r
14429 2234: return xReturn;
\r
14432 2237: #endif /* configUSE_CO_ROUTINES */
\r
14433 2238: /*-----------------------------------------------------------*/
\r
14435 2240: #if ( configUSE_CO_ROUTINES == 1 )
\r
14437 2242: BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
\r
14439 2244: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
14441 2246: /* Cannot block within an ISR so if there is no space on the queue then
\r
14442 2247: exit without doing anything. */
\r
14443 2248: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
\r
14445 2250: prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
\r
14447 2252: /* We only want to wake one co-routine per ISR, so check that a
\r
14448 2253: co-routine has not already been woken. */
\r
14449 2254: if( xCoRoutinePreviouslyWoken == pdFALSE )
\r
14451 2256: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
\r
14453 2258: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
\r
14455 2260: return pdTRUE;
\r
14459 2264: mtCOVERAGE_TEST_MARKER();
\r
14464 2269: mtCOVERAGE_TEST_MARKER();
\r
14469 2274: mtCOVERAGE_TEST_MARKER();
\r
14474 2279: mtCOVERAGE_TEST_MARKER();
\r
14477 2282: return xCoRoutinePreviouslyWoken;
\r
14480 2285: #endif /* configUSE_CO_ROUTINES */
\r
14481 2286: /*-----------------------------------------------------------*/
\r
14483 2288: #if ( configUSE_CO_ROUTINES == 1 )
\r
14485 2290: BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
\r
14487 2292: BaseType_t xReturn;
\r
14488 2293: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
14490 2295: /* We cannot block from an ISR, so check there is data available. If
\r
14491 2296: not then just leave without doing anything. */
\r
14492 2297: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
\r
14494 2299: /* Copy the data from the queue. */
\r
14495 2300: pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
\r
14496 2301: if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
\r
14498 2303: pxQueue->u.pcReadFrom = pxQueue->pcHead;
\r
14502 2307: mtCOVERAGE_TEST_MARKER();
\r
14504 2309: --( pxQueue->uxMessagesWaiting );
\r
14505 2310: ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
\r
14507 2312: if( ( *pxCoRoutineWoken ) == pdFALSE )
\r
14509 2314: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
\r
14511 2316: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
\r
14513 2318: *pxCoRoutineWoken = pdTRUE;
\r
14517 2322: mtCOVERAGE_TEST_MARKER();
\r
14522 2327: mtCOVERAGE_TEST_MARKER();
\r
14527 2332: mtCOVERAGE_TEST_MARKER();
\r
14530 2335: xReturn = pdPASS;
\r
14534 2339: xReturn = pdFAIL;
\r
14537 2342: return xReturn;
\r
14540 2345: #endif /* configUSE_CO_ROUTINES */
\r
14541 2346: /*-----------------------------------------------------------*/
\r
14543 2348: #if ( configQUEUE_REGISTRY_SIZE > 0 )
\r
14545 2350: void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
\r
14547 2352: UBaseType_t ux;
\r
14549 2354: /* See if there is an empty space in the registry. A NULL name denotes
\r
14550 2355: a free slot. */
\r
14551 2356: for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
\r
14553 2358: if( xQueueRegistry[ ux ].pcQueueName == NULL )
\r
14555 2360: /* Store the information on this queue. */
\r
14556 2361: xQueueRegistry[ ux ].pcQueueName = pcQueueName;
\r
14557 2362: xQueueRegistry[ ux ].xHandle = xQueue;
\r
14559 2364: traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
\r
14564 2369: mtCOVERAGE_TEST_MARKER();
\r
14569 2374: #endif /* configQUEUE_REGISTRY_SIZE */
\r
14570 2375: /*-----------------------------------------------------------*/
\r
14572 2377: #if ( configQUEUE_REGISTRY_SIZE > 0 )
\r
14574 2379: void vQueueUnregisterQueue( QueueHandle_t xQueue )
\r
14576 2381: UBaseType_t ux;
\r
14578 2383: /* See if the handle of the queue being unregistered in actually in the
\r
14579 2384: registry. */
\r
14580 2385: for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
\r
14582 2387: if( xQueueRegistry[ ux ].xHandle == xQueue )
\r
14584 2389: /* Set the name to NULL to show that this slot if free again. */
\r
14585 2390: xQueueRegistry[ ux ].pcQueueName = NULL;
\r
14590 2395: mtCOVERAGE_TEST_MARKER();
\r
14594 2399: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
\r
14596 2401: #endif /* configQUEUE_REGISTRY_SIZE */
\r
14597 2402: /*-----------------------------------------------------------*/
\r
14599 2404: #if ( configUSE_TIMERS == 1 )
\r
14601 2406: void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
\r
14603 BFD06928 4FF1 ADDIU SP, SP, -32
\r
14604 BFD0692A CBE7 SW RA, 28(SP)
\r
14605 BFD0692C CBC6 SW S8, 24(SP)
\r
14606 BFD0692E 0FDD MOVE S8, SP
\r
14607 BFD06930 0020F89E SW A0, 32(S8)
\r
14608 BFD06934 0024F8BE SW A1, 36(S8)
\r
14609 BFD06938 0028F8DE SW A2, 40(S8)
\r
14610 2408: Queue_t * const pxQueue = ( Queue_t * ) xQueue;
\r
14611 BFD0693C 0020FC5E LW V0, 32(S8)
\r
14612 BFD06940 0010F85E SW V0, 16(S8)
\r
14614 2410: /* This function should not be called by application code hence the
\r
14615 2411: 'Restricted' in its name. It is not part of the public API. It is
\r
14616 2412: designed for use by kernel code, and has special calling requirements.
\r
14617 2413: It can result in vListInsert() being called on a list that can only
\r
14618 2414: possibly ever have one item in it, so the list will be fast, but even
\r
14619 2415: so it should be called with the scheduler locked and not from a critical
\r
14620 2416: section. */
\r
14622 2418: /* Only do anything if there are no messages in the queue. This function
\r
14623 2419: will not actually cause the task to block, just place it on a blocked
\r
14624 2420: list. It will not block until the scheduler is unlocked - at which
\r
14625 2421: time a yield will be performed. If an item is added to the queue while
\r
14626 2422: the queue is locked, and the calling task blocks on the queue, then the
\r
14627 2423: calling task will be immediately unblocked when the queue is unlocked. */
\r
14628 2424: prvLockQueue( pxQueue );
\r
14629 BFD06944 33B877E8 JALS vTaskEnterCritical
\r
14630 BFD06946 0C0033B8 ADDIU SP, T8, 3072
\r
14631 BFD06948 0C00 NOP
\r
14632 BFD0694A 0010FC5E LW V0, 16(S8)
\r
14633 BFD0694E 0044FC62 LW V1, 68(V0)
\r
14634 BFD06952 ED7F LI V0, -1
\r
14635 BFD06954 0005B443 BNE V1, V0, 0xBFD06962
\r
14636 BFD06956 0C000005 SLL ZERO, A1, 1
\r
14637 BFD06958 0C00 NOP
\r
14638 BFD0695A 0010FC5E LW V0, 16(S8)
\r
14639 BFD0695E 0044F802 SW ZERO, 68(V0)
\r
14640 BFD06962 0010FC5E LW V0, 16(S8)
\r
14641 BFD06966 0048FC62 LW V1, 72(V0)
\r
14642 BFD0696A ED7F LI V0, -1
\r
14643 BFD0696C 0005B443 BNE V1, V0, 0xBFD0697A
\r
14644 BFD0696E 0C000005 SLL ZERO, A1, 1
\r
14645 BFD06970 0C00 NOP
\r
14646 BFD06972 0010FC5E LW V0, 16(S8)
\r
14647 BFD06976 0048F802 SW ZERO, 72(V0)
\r
14648 BFD0697A 40AA77E8 JALS vTaskExitCritical
\r
14649 BFD0697C 0C0040AA BNEZC T2, 0xBFD08180
\r
14650 BFD0697E 0C00 NOP
\r
14651 2425: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
\r
14652 BFD06980 0010FC5E LW V0, 16(S8)
\r
14653 BFD06984 692E LW V0, 56(V0)
\r
14654 BFD06986 000C40A2 BNEZC V0, 0xBFD069A2
\r
14656 2427: /* There is nothing in the queue, block for the specified period. */
\r
14657 2428: vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
\r
14658 BFD0698A 0010FC5E LW V0, 16(S8)
\r
14659 BFD0698E 00243042 ADDIU V0, V0, 36
\r
14660 BFD06992 0C82 MOVE A0, V0
\r
14661 BFD06994 0024FCBE LW A1, 36(S8)
\r
14662 BFD06998 0028FCDE LW A2, 40(S8)
\r
14663 BFD0699C 2E2C77E8 JALS vTaskPlaceOnEventListRestricted
\r
14664 BFD0699E 2E2C ANDI A0, V0, 0x40
\r
14665 BFD069A0 0C00 NOP
\r
14669 2432: mtCOVERAGE_TEST_MARKER();
\r
14671 2434: prvUnlockQueue( pxQueue );
\r
14672 BFD069A2 0010FC9E LW A0, 16(S8)
\r
14673 BFD069A6 1DEE77E8 JALS prvUnlockQueue
\r
14674 BFD069A8 0C001DEE LB T7, 3072(T6)
\r
14675 BFD069AA 0C00 NOP
\r
14677 BFD069AC 0FBE MOVE SP, S8
\r
14678 BFD069AE 4BE7 LW RA, 28(SP)
\r
14679 BFD069B0 4BC6 LW S8, 24(SP)
\r
14680 BFD069B2 4C11 ADDIU SP, SP, 32
\r
14681 BFD069B4 459F JR16 RA
\r
14682 BFD069B6 0C00 NOP
\r
14684 2437: #endif /* configUSE_TIMERS */
\r
14685 2438: /*-----------------------------------------------------------*/
\r
14687 2440: #if ( configUSE_QUEUE_SETS == 1 )
\r
14689 2442: QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
\r
14691 BFD098AC 4FF1 ADDIU SP, SP, -32
\r
14692 BFD098AE CBE7 SW RA, 28(SP)
\r
14693 BFD098B0 CBC6 SW S8, 24(SP)
\r
14694 BFD098B2 0FDD MOVE S8, SP
\r
14695 BFD098B4 0020F89E SW A0, 32(S8)
\r
14696 2444: QueueSetHandle_t pxQueue;
\r
14698 2446: pxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
\r
14699 BFD098B8 0020FC9E LW A0, 32(S8)
\r
14700 BFD098BC EE84 LI A1, 4
\r
14701 BFD098BE 0CC0 MOVE A2, ZERO
\r
14702 BFD098C0 1EFA77E8 JALS xQueueGenericCreate
\r
14703 BFD098C2 0C001EFA LB S7, 3072(K0)
\r
14704 BFD098C4 0C00 NOP
\r
14705 BFD098C6 0010F85E SW V0, 16(S8)
\r
14707 2448: return pxQueue;
\r
14708 BFD098CA 0010FC5E LW V0, 16(S8)
\r
14710 BFD098CE 0FBE MOVE SP, S8
\r
14711 BFD098D0 4BE7 LW RA, 28(SP)
\r
14712 BFD098D2 4BC6 LW S8, 24(SP)
\r
14713 BFD098D4 4C11 ADDIU SP, SP, 32
\r
14714 BFD098D6 459F JR16 RA
\r
14715 BFD098D8 0C00 NOP
\r
14717 2451: #endif /* configUSE_QUEUE_SETS */
\r
14718 2452: /*-----------------------------------------------------------*/
\r
14720 2454: #if ( configUSE_QUEUE_SETS == 1 )
\r
14722 2456: BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
\r
14724 BFD07E9C 4FF1 ADDIU SP, SP, -32
\r
14725 BFD07E9E CBE7 SW RA, 28(SP)
\r
14726 BFD07EA0 CBC6 SW S8, 24(SP)
\r
14727 BFD07EA2 0FDD MOVE S8, SP
\r
14728 BFD07EA4 0020F89E SW A0, 32(S8)
\r
14729 BFD07EA8 0024F8BE SW A1, 36(S8)
\r
14730 2458: BaseType_t xReturn;
\r
14732 2460: taskENTER_CRITICAL();
\r
14733 BFD07EAC 33B877E8 JALS vTaskEnterCritical
\r
14734 BFD07EAE 0C0033B8 ADDIU SP, T8, 3072
\r
14735 BFD07EB0 0C00 NOP
\r
14737 2462: if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
\r
14738 BFD07EB2 0020FC5E LW V0, 32(S8)
\r
14739 BFD07EB6 004CFC42 LW V0, 76(V0)
\r
14740 BFD07EBA 000440E2 BEQZC V0, 0xBFD07EC6
\r
14742 2464: /* Cannot add a queue/semaphore to more than one queue set. */
\r
14743 2465: xReturn = pdFAIL;
\r
14744 BFD07EBE 0010F81E SW ZERO, 16(S8)
\r
14745 BFD07EC2 CC13 B 0xBFD07EEA
\r
14746 BFD07EC4 0C00 NOP
\r
14748 2467: else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
\r
14749 BFD07EC6 0020FC5E LW V0, 32(S8)
\r
14750 BFD07ECA 692E LW V0, 56(V0)
\r
14751 BFD07ECC 000440E2 BEQZC V0, 0xBFD07ED8
\r
14753 2469: /* Cannot add a queue/semaphore to a queue set if there are already
\r
14754 2470: items in the queue/semaphore. */
\r
14755 2471: xReturn = pdFAIL;
\r
14756 BFD07ED0 0010F81E SW ZERO, 16(S8)
\r
14757 BFD07ED4 CC0A B 0xBFD07EEA
\r
14758 BFD07ED6 0C00 NOP
\r
14762 2475: ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
\r
14763 BFD07ED8 0020FC5E LW V0, 32(S8)
\r
14764 BFD07EDC 0024FC7E LW V1, 36(S8)
\r
14765 BFD07EE0 004CF862 SW V1, 76(V0)
\r
14766 2476: xReturn = pdPASS;
\r
14767 BFD07EE4 ED01 LI V0, 1
\r
14768 BFD07EE6 0010F85E SW V0, 16(S8)
\r
14771 2479: taskEXIT_CRITICAL();
\r
14772 BFD07EEA 40AA77E8 JALS vTaskExitCritical
\r
14773 BFD07EEC 0C0040AA BNEZC T2, 0xBFD096F0
\r
14774 BFD07EEE 0C00 NOP
\r
14776 2481: return xReturn;
\r
14777 BFD07EF0 0010FC5E LW V0, 16(S8)
\r
14779 BFD07EF4 0FBE MOVE SP, S8
\r
14780 BFD07EF6 4BE7 LW RA, 28(SP)
\r
14781 BFD07EF8 4BC6 LW S8, 24(SP)
\r
14782 BFD07EFA 4C11 ADDIU SP, SP, 32
\r
14783 BFD07EFC 459F JR16 RA
\r
14784 BFD07EFE 0C00 NOP
\r
14786 2484: #endif /* configUSE_QUEUE_SETS */
\r
14787 2485: /*-----------------------------------------------------------*/
\r
14789 2487: #if ( configUSE_QUEUE_SETS == 1 )
\r
14791 2489: BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
\r
14793 BFD079FC 4FF1 ADDIU SP, SP, -32
\r
14794 BFD079FE CBE7 SW RA, 28(SP)
\r
14795 BFD07A00 CBC6 SW S8, 24(SP)
\r
14796 BFD07A02 0FDD MOVE S8, SP
\r
14797 BFD07A04 0020F89E SW A0, 32(S8)
\r
14798 BFD07A08 0024F8BE SW A1, 36(S8)
\r
14799 2491: BaseType_t xReturn;
\r
14800 2492: Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
\r
14801 BFD07A0C 0020FC5E LW V0, 32(S8)
\r
14802 BFD07A10 0014F85E SW V0, 20(S8)
\r
14804 2494: if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
\r
14805 BFD07A14 0014FC5E LW V0, 20(S8)
\r
14806 BFD07A18 004CFC62 LW V1, 76(V0)
\r
14807 BFD07A1C 0024FC5E LW V0, 36(S8)
\r
14808 BFD07A20 00059443 BEQ V1, V0, 0xBFD07A2E
\r
14809 BFD07A22 0C000005 SLL ZERO, A1, 1
\r
14810 BFD07A24 0C00 NOP
\r
14812 2496: /* The queue was not a member of the set. */
\r
14813 2497: xReturn = pdFAIL;
\r
14814 BFD07A26 0010F81E SW ZERO, 16(S8)
\r
14815 BFD07A2A CC17 B 0xBFD07A5A
\r
14816 BFD07A2C 0C00 NOP
\r
14818 2499: else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
\r
14819 BFD07A2E 0014FC5E LW V0, 20(S8)
\r
14820 BFD07A32 692E LW V0, 56(V0)
\r
14821 BFD07A34 000440E2 BEQZC V0, 0xBFD07A40
\r
14823 2501: /* It is dangerous to remove a queue from a set when the queue is
\r
14824 2502: not empty because the queue set will still hold pending events for
\r
14825 2503: the queue. */
\r
14826 2504: xReturn = pdFAIL;
\r
14827 BFD07A38 0010F81E SW ZERO, 16(S8)
\r
14828 BFD07A3C CC0E B 0xBFD07A5A
\r
14829 BFD07A3E 0C00 NOP
\r
14833 2508: taskENTER_CRITICAL();
\r
14834 BFD07A40 33B877E8 JALS vTaskEnterCritical
\r
14835 BFD07A42 0C0033B8 ADDIU SP, T8, 3072
\r
14836 BFD07A44 0C00 NOP
\r
14838 2510: /* The queue is no longer contained in the set. */
\r
14839 2511: pxQueueOrSemaphore->pxQueueSetContainer = NULL;
\r
14840 BFD07A46 0014FC5E LW V0, 20(S8)
\r
14841 BFD07A4A 004CF802 SW ZERO, 76(V0)
\r
14843 2513: taskEXIT_CRITICAL();
\r
14844 BFD07A4E 40AA77E8 JALS vTaskExitCritical
\r
14845 BFD07A50 0C0040AA BNEZC T2, gpio_port_bitmaps
\r
14846 BFD07A52 0C00 NOP
\r
14847 2514: xReturn = pdPASS;
\r
14848 BFD07A54 ED01 LI V0, 1
\r
14849 BFD07A56 0010F85E SW V0, 16(S8)
\r
14852 2517: return xReturn;
\r
14853 BFD07A5A 0010FC5E LW V0, 16(S8)
\r
14854 2518: } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
\r
14855 BFD07A5E 0FBE MOVE SP, S8
\r
14856 BFD07A60 4BE7 LW RA, 28(SP)
\r
14857 BFD07A62 4BC6 LW S8, 24(SP)
\r
14858 BFD07A64 4C11 ADDIU SP, SP, 32
\r
14859 BFD07A66 459F JR16 RA
\r
14860 BFD07A68 0C00 NOP
\r
14862 2520: #endif /* configUSE_QUEUE_SETS */
\r
14863 2521: /*-----------------------------------------------------------*/
\r
14865 2523: #if ( configUSE_QUEUE_SETS == 1 )
\r
14867 2525: QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
\r
14869 BFD094E0 4FF1 ADDIU SP, SP, -32
\r
14870 BFD094E2 CBE7 SW RA, 28(SP)
\r
14871 BFD094E4 CBC6 SW S8, 24(SP)
\r
14872 BFD094E6 0FDD MOVE S8, SP
\r
14873 BFD094E8 0020F89E SW A0, 32(S8)
\r
14874 BFD094EC 0024F8BE SW A1, 36(S8)
\r
14875 2527: QueueSetMemberHandle_t xReturn = NULL;
\r
14876 BFD094F0 0010F81E SW ZERO, 16(S8)
\r
14878 2529: ( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */
\r
14879 BFD094F4 0020FC9E LW A0, 32(S8)
\r
14880 BFD094F8 0010305E ADDIU V0, S8, 16
\r
14881 BFD094FC 0CA2 MOVE A1, V0
\r
14882 BFD094FE 0024FCDE LW A2, 36(S8)
\r
14883 BFD09502 0CE0 MOVE A3, ZERO
\r
14884 BFD09504 081E77E8 JALS xQueueGenericReceive
\r
14885 BFD09506 081E LBU S0, 14(S1)
\r
14886 BFD09508 0C00 NOP
\r
14887 2530: return xReturn;
\r
14888 BFD0950A 0010FC5E LW V0, 16(S8)
\r
14890 BFD0950E 0FBE MOVE SP, S8
\r
14891 BFD09510 4BE7 LW RA, 28(SP)
\r
14892 BFD09512 4BC6 LW S8, 24(SP)
\r
14893 BFD09514 4C11 ADDIU SP, SP, 32
\r
14894 BFD09516 459F JR16 RA
\r
14895 BFD09518 0C00 NOP
\r
14897 2533: #endif /* configUSE_QUEUE_SETS */
\r
14898 2534: /*-----------------------------------------------------------*/
\r
14900 2536: #if ( configUSE_QUEUE_SETS == 1 )
\r
14902 2538: QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
\r
14904 BFD097DC 4FF1 ADDIU SP, SP, -32
\r
14905 BFD097DE CBE7 SW RA, 28(SP)
\r
14906 BFD097E0 CBC6 SW S8, 24(SP)
\r
14907 BFD097E2 0FDD MOVE S8, SP
\r
14908 BFD097E4 0020F89E SW A0, 32(S8)
\r
14909 2540: QueueSetMemberHandle_t xReturn = NULL;
\r
14910 BFD097E8 0010F81E SW ZERO, 16(S8)
\r
14912 2542: ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
\r
14913 BFD097EC 0020FC9E LW A0, 32(S8)
\r
14914 BFD097F0 0010305E ADDIU V0, S8, 16
\r
14915 BFD097F4 0CA2 MOVE A1, V0
\r
14916 BFD097F6 0CC0 MOVE A2, ZERO
\r
14917 BFD097F8 1D6477E8 JALS xQueueReceiveFromISR
\r
14918 BFD097FA 0C001D64 LB T3, 3072(A0)
\r
14919 BFD097FC 0C00 NOP
\r
14920 2543: return xReturn;
\r
14921 BFD097FE 0010FC5E LW V0, 16(S8)
\r
14923 BFD09802 0FBE MOVE SP, S8
\r
14924 BFD09804 4BE7 LW RA, 28(SP)
\r
14925 BFD09806 4BC6 LW S8, 24(SP)
\r
14926 BFD09808 4C11 ADDIU SP, SP, 32
\r
14927 BFD0980A 459F JR16 RA
\r
14928 BFD0980C 0C00 NOP
\r
14930 2546: #endif /* configUSE_QUEUE_SETS */
\r
14931 2547: /*-----------------------------------------------------------*/
\r
14933 2549: #if ( configUSE_QUEUE_SETS == 1 )
\r
14935 2551: static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
\r
14937 BFD043B0 4FF1 ADDIU SP, SP, -32
\r
14938 BFD043B2 CBE7 SW RA, 28(SP)
\r
14939 BFD043B4 CBC6 SW S8, 24(SP)
\r
14940 BFD043B6 0FDD MOVE S8, SP
\r
14941 BFD043B8 0020F89E SW A0, 32(S8)
\r
14942 BFD043BC 0024F8BE SW A1, 36(S8)
\r
14943 2553: Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
\r
14944 BFD043C0 0020FC5E LW V0, 32(S8)
\r
14945 BFD043C4 004CFC42 LW V0, 76(V0)
\r
14946 BFD043C8 0014F85E SW V0, 20(S8)
\r
14947 2554: BaseType_t xReturn = pdFALSE;
\r
14948 BFD043CC 0010F81E SW ZERO, 16(S8)
\r
14950 2556: /* This function must be called form a critical section. */
\r
14952 2558: configASSERT( pxQueueSetContainer );
\r
14953 BFD043D0 0014FC5E LW V0, 20(S8)
\r
14954 BFD043D4 000940A2 BNEZC V0, 0xBFD043EA
\r
14955 BFD043D8 BFD141A2 LUI V0, 0xBFD1
\r
14956 BFD043DA 3082BFD1 LDC1 F30, 12418(S1)
\r
14957 BFD043DC 9E3C3082 ADDIU A0, V0, -25028
\r
14958 BFD043DE 30A09E3C LWC1 F17, 12448(GP)
\r
14959 BFD043E0 09FE30A0 ADDIU A1, ZERO, 2558
\r
14960 BFD043E2 09FE LBU V1, 14(A3)
\r
14961 BFD043E4 4B7E77E8 JALS vAssertCalled
\r
14962 BFD043E6 4B7E LW K1, 120(SP)
\r
14963 BFD043E8 0C00 NOP
\r
14964 2559: configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
\r
14965 BFD043EA 0014FC5E LW V0, 20(S8)
\r
14966 BFD043EE 69AE LW V1, 56(V0)
\r
14967 BFD043F0 0014FC5E LW V0, 20(S8)
\r
14968 BFD043F4 692F LW V0, 60(V0)
\r
14969 BFD043F6 13900043 SLTU V0, V1, V0
\r
14970 BFD043F8 40A21390 ADDI GP, S0, 16546
\r
14971 BFD043FA 000940A2 BNEZC V0, 0xBFD04410
\r
14972 BFD043FE BFD141A2 LUI V0, 0xBFD1
\r
14973 BFD04400 3082BFD1 LDC1 F30, 12418(S1)
\r
14974 BFD04402 9E3C3082 ADDIU A0, V0, -25028
\r
14975 BFD04404 30A09E3C LWC1 F17, 12448(GP)
\r
14976 BFD04406 09FF30A0 ADDIU A1, ZERO, 2559
\r
14977 BFD04408 09FF LBU V1, -1(A3)
\r
14978 BFD0440A 4B7E77E8 JALS vAssertCalled
\r
14979 BFD0440C 4B7E LW K1, 120(SP)
\r
14980 BFD0440E 0C00 NOP
\r
14982 2561: if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
\r
14983 BFD04410 0014FC5E LW V0, 20(S8)
\r
14984 BFD04414 69AE LW V1, 56(V0)
\r
14985 BFD04416 0014FC5E LW V0, 20(S8)
\r
14986 BFD0441A 692F LW V0, 60(V0)
\r
14987 BFD0441C 13900043 SLTU V0, V1, V0
\r
14988 BFD0441E 40E21390 ADDI GP, S0, 16610
\r
14989 BFD04420 003040E2 BEQZC V0, 0xBFD04484
\r
14991 2563: traceQUEUE_SEND( pxQueueSetContainer );
\r
14993 2565: /* The data copied is the handle of the queue that contains data. */
\r
14994 2566: xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
\r
14995 BFD04424 0014FC9E LW A0, 20(S8)
\r
14996 BFD04428 002030BE ADDIU A1, S8, 32
\r
14997 BFD0442C 0024FCDE LW A2, 36(S8)
\r
14998 BFD04430 14E677E8 JALS prvCopyDataToQueue
\r
14999 BFD04432 0C0014E6 LBU A3, 3072(A2)
\r
15000 BFD04434 0C00 NOP
\r
15001 BFD04436 0010F85E SW V0, 16(S8)
\r
15003 2568: if( pxQueueSetContainer->xTxLock == queueUNLOCKED )
\r
15004 BFD0443A 0014FC5E LW V0, 20(S8)
\r
15005 BFD0443E 0048FC62 LW V1, 72(V0)
\r
15006 BFD04442 ED7F LI V0, -1
\r
15007 BFD04444 0015B443 BNE V1, V0, 0xBFD04472
\r
15008 BFD04446 0C000015 SLL ZERO, S5, 1
\r
15009 BFD04448 0C00 NOP
\r
15011 2570: if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
\r
15012 BFD0444A 0014FC5E LW V0, 20(S8)
\r
15013 BFD0444E 6929 LW V0, 36(V0)
\r
15014 BFD04450 001840E2 BEQZC V0, 0xBFD04484
\r
15016 2572: if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
\r
15017 BFD04454 0014FC5E LW V0, 20(S8)
\r
15018 BFD04458 00243042 ADDIU V0, V0, 36
\r
15019 BFD0445C 0C82 MOVE A0, V0
\r
15020 BFD0445E 22BC77E8 JALS xTaskRemoveFromEventList
\r
15021 BFD04460 0C0022BC LWC2 S5, 3072(GP)
\r
15022 BFD04462 0C00 NOP
\r
15023 BFD04464 000E40E2 BEQZC V0, 0xBFD04484
\r
15025 2574: /* The task waiting has a higher priority. */
\r
15026 2575: xReturn = pdTRUE;
\r
15027 BFD04468 ED01 LI V0, 1
\r
15028 BFD0446A 0010F85E SW V0, 16(S8)
\r
15029 BFD0446E CC0A B 0xBFD04484
\r
15030 BFD04470 0C00 NOP
\r
15034 2579: mtCOVERAGE_TEST_MARKER();
\r
15039 2584: mtCOVERAGE_TEST_MARKER();
\r
15044 2589: ( pxQueueSetContainer->xTxLock )++;
\r
15045 BFD04472 0014FC5E LW V0, 20(S8)
\r
15046 BFD04476 0048FC42 LW V0, 72(V0)
\r
15047 BFD0447A 6DA0 ADDIU V1, V0, 1
\r
15048 BFD0447C 0014FC5E LW V0, 20(S8)
\r
15049 BFD04480 0048F862 SW V1, 72(V0)
\r
15054 2594: mtCOVERAGE_TEST_MARKER();
\r
15057 2597: return xReturn;
\r
15058 BFD04484 0010FC5E LW V0, 16(S8)
\r
15060 BFD04488 0FBE MOVE SP, S8
\r
15061 BFD0448A 4BE7 LW RA, 28(SP)
\r
15062 BFD0448C 4BC6 LW S8, 24(SP)
\r
15063 BFD0448E 4C11 ADDIU SP, SP, 32
\r
15064 BFD04490 459F JR16 RA
\r
15065 BFD04492 0C00 NOP
\r
15067 2600: #endif /* configUSE_QUEUE_SETS */
\r
15080 --- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/portmacro.h -------------
\r
15082 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
15083 3: All rights reserved
\r
15085 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
15087 7: This file is part of the FreeRTOS distribution.
\r
15089 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
15090 10: the terms of the GNU General Public License (version 2) as published by the
\r
15091 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
15093 13: ***************************************************************************
\r
15094 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15095 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
15096 16: >>! obliged to provide the source code for proprietary components !<<
\r
15097 17: >>! outside of the FreeRTOS kernel. !<<
\r
15098 18: ***************************************************************************
\r
15100 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
15101 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
15102 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
15103 23: link: http://www.freertos.org/a00114.html
\r
15105 25: ***************************************************************************
\r
15107 27: * FreeRTOS provides completely free yet professionally developed, *
\r
15108 28: * robust, strictly quality controlled, supported, and cross *
\r
15109 29: * platform software that is more than just the market leader, it *
\r
15110 30: * is the industry's de facto standard. *
\r
15112 32: * Help yourself get started quickly while simultaneously helping *
\r
15113 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
15114 34: * tutorial book, reference manual, or both: *
\r
15115 35: * http://www.FreeRTOS.org/Documentation *
\r
15117 37: ***************************************************************************
\r
15119 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
15120 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
15121 41: defined configASSERT()?
\r
15123 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
15124 44: embedded software for free we request you assist our global community by
\r
15125 45: participating in the support forum.
\r
15127 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
15128 48: be as productive as possible as early as possible. Now you can receive
\r
15129 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
15130 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
15132 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
15133 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
15134 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
15136 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
15137 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
15139 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
15140 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
15141 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
15143 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
15144 64: engineered and independently SIL3 certified version for use in safety and
\r
15145 65: mission critical applications that require provable dependability.
\r
15147 67: 1 tab == 4 spaces!
\r
15150 70: #ifndef PORTMACRO_H
\r
15151 71: #define PORTMACRO_H
\r
15153 73: #ifdef __cplusplus
\r
15157 77: /*-----------------------------------------------------------
\r
15158 78: * Port specific definitions.
\r
15160 80: * The settings in this file configure FreeRTOS correctly for the
\r
15161 81: * given hardware and compiler.
\r
15163 83: * These settings should not be altered.
\r
15164 84: *-----------------------------------------------------------
\r
15167 87: /* Type definitions. */
\r
15168 88: #define portCHAR char
\r
15169 89: #define portFLOAT float
\r
15170 90: #define portDOUBLE double
\r
15171 91: #define portLONG long
\r
15172 92: #define portSHORT short
\r
15173 93: #define portSTACK_TYPE uint32_t
\r
15174 94: #define portBASE_TYPE long
\r
15176 96: typedef portSTACK_TYPE StackType_t;
\r
15177 97: typedef long BaseType_t;
\r
15178 98: typedef unsigned long UBaseType_t;
\r
15180 100: #if( configUSE_16_BIT_TICKS == 1 )
\r
15181 101: typedef uint16_t TickType_t;
\r
15182 102: #define portMAX_DELAY ( TickType_t ) 0xffff
\r
15184 104: typedef uint32_t TickType_t;
\r
15185 105: #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
\r
15187 107: /*-----------------------------------------------------------*/
\r
15189 109: /* Hardware specifics. */
\r
15190 110: #define portBYTE_ALIGNMENT 8
\r
15191 111: #define portSTACK_GROWTH -1
\r
15192 112: #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
\r
15193 113: /*-----------------------------------------------------------*/
\r
15195 115: /* Critical section management. */
\r
15196 116: #define portIPL_SHIFT ( 10UL )
\r
15197 117: /* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
\r
15198 118: never have higher IPL bits set anyway. */
\r
15199 119: #define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
\r
15200 120: #define portSW0_BIT ( 0x01 << 8 )
\r
15202 122: /*-----------------------------------------------------------*/
\r
15204 124: static inline uint32_t ulPortGetCP0Status( void )
\r
15206 BFD09B4C 4FF9 ADDIU SP, SP, -16
\r
15207 BFD09B4E CBC3 SW S8, 12(SP)
\r
15208 BFD09B50 CA02 SW S0, 8(SP)
\r
15209 BFD09B52 0FDD MOVE S8, SP
\r
15210 BFD09C6C 4FF9 ADDIU SP, SP, -16
\r
15211 BFD09C6E CBC3 SW S8, 12(SP)
\r
15212 BFD09C70 CA02 SW S0, 8(SP)
\r
15213 BFD09C72 0FDD MOVE S8, SP
\r
15214 BFD09D6C 4FF9 ADDIU SP, SP, -16
\r
15215 BFD09D6E CBC3 SW S8, 12(SP)
\r
15216 BFD09D70 CA02 SW S0, 8(SP)
\r
15217 BFD09D72 0FDD MOVE S8, SP
\r
15218 126: uint32_t rv;
\r
15220 128: __asm volatile(
\r
15221 BFD09B54 00FC020C MFC0 S0, Status
\r
15222 BFD09B58 0000FA1E SW S0, 0(S8)
\r
15223 BFD09C74 00FC020C MFC0 S0, Status
\r
15224 BFD09C78 0000FA1E SW S0, 0(S8)
\r
15225 BFD09D74 00FC020C MFC0 S0, Status
\r
15226 BFD09D78 0000FA1E SW S0, 0(S8)
\r
15228 130: "mfc0 %0,$12,0 \n\t"
\r
15229 131: : "=r" ( rv ) :: );
\r
15232 BFD09B5C 0000FC5E LW V0, 0(S8)
\r
15233 BFD09C7C 0000FC5E LW V0, 0(S8)
\r
15234 BFD09D7C 0000FC5E LW V0, 0(S8)
\r
15236 BFD09B60 0FBE MOVE SP, S8
\r
15237 BFD09B62 4BC3 LW S8, 12(SP)
\r
15238 BFD09B64 4A02 LW S0, 8(SP)
\r
15239 BFD09B66 459F JR16 RA
\r
15240 BFD09B68 4C09 ADDIU SP, SP, 16
\r
15241 BFD09C80 0FBE MOVE SP, S8
\r
15242 BFD09C82 4BC3 LW S8, 12(SP)
\r
15243 BFD09C84 4A02 LW S0, 8(SP)
\r
15244 BFD09C86 459F JR16 RA
\r
15245 BFD09C88 4C09 ADDIU SP, SP, 16
\r
15246 BFD09D80 0FBE MOVE SP, S8
\r
15247 BFD09D82 4BC3 LW S8, 12(SP)
\r
15248 BFD09D84 4A02 LW S0, 8(SP)
\r
15249 BFD09D86 459F JR16 RA
\r
15250 BFD09D88 4C09 ADDIU SP, SP, 16
\r
15251 135: /*-----------------------------------------------------------*/
\r
15253 137: static inline void vPortSetCP0Status( uint32_t new_status)
\r
15255 BFD09B6C 4FB0 ADDIU SP, SP, -8
\r
15256 BFD09B6E CBC1 SW S8, 4(SP)
\r
15257 BFD09B70 0FDD MOVE S8, SP
\r
15258 BFD09B72 0008F89E SW A0, 8(S8)
\r
15259 BFD09C8C 4FB0 ADDIU SP, SP, -8
\r
15260 BFD09C8E CBC1 SW S8, 4(SP)
\r
15261 BFD09C90 0FDD MOVE S8, SP
\r
15262 BFD09C92 0008F89E SW A0, 8(S8)
\r
15263 BFD09D8C 4FB0 ADDIU SP, SP, -8
\r
15264 BFD09D8E CBC1 SW S8, 4(SP)
\r
15265 BFD09D90 0FDD MOVE S8, SP
\r
15266 BFD09D92 0008F89E SW A0, 8(S8)
\r
15267 139: ( void ) new_status;
\r
15269 141: __asm__ __volatile__(
\r
15270 BFD09B76 0008FC5E LW V0, 8(S8)
\r
15271 BFD09B78 004C0008 INS ZERO, T0, 1, 0
\r
15272 BFD09B7A 02FC004C MTC0 V0, Status
\r
15273 BFD09B7C 000002FC SLL S7, GP, 0
\r
15274 BFD09B7E 18000000 SLL ZERO, ZERO, 3
\r
15275 BFD09B80 0FBE1800 SB ZERO, 4030(ZERO)
\r
15276 BFD09C96 0008FC5E LW V0, 8(S8)
\r
15277 BFD09C98 004C0008 INS ZERO, T0, 1, 0
\r
15278 BFD09C9A 02FC004C MTC0 V0, Status
\r
15279 BFD09C9C 000002FC SLL S7, GP, 0
\r
15280 BFD09C9E 18000000 SLL ZERO, ZERO, 3
\r
15281 BFD09CA0 0FBE1800 SB ZERO, 4030(ZERO)
\r
15282 BFD09D96 0008FC5E LW V0, 8(S8)
\r
15283 BFD09D98 004C0008 INS ZERO, T0, 1, 0
\r
15284 BFD09D9A 02FC004C MTC0 V0, Status
\r
15285 BFD09D9C 000002FC SLL S7, GP, 0
\r
15286 BFD09D9E 18000000 SLL ZERO, ZERO, 3
\r
15287 BFD09DA0 0FBE1800 SB ZERO, 4030(ZERO)
\r
15289 143: "mtc0 %0,$12,0 \n\t"
\r
15292 146: :"r" ( new_status ) : );
\r
15294 BFD09B82 0FBE MOVE SP, S8
\r
15295 BFD09B84 4BC1 LW S8, 4(SP)
\r
15296 BFD09B86 459F JR16 RA
\r
15297 BFD09B88 4C05 ADDIU SP, SP, 8
\r
15298 BFD09CA2 0FBE MOVE SP, S8
\r
15299 BFD09CA4 4BC1 LW S8, 4(SP)
\r
15300 BFD09CA6 459F JR16 RA
\r
15301 BFD09CA8 4C05 ADDIU SP, SP, 8
\r
15302 BFD09DA2 0FBE MOVE SP, S8
\r
15303 BFD09DA4 4BC1 LW S8, 4(SP)
\r
15304 BFD09DA6 459F JR16 RA
\r
15305 BFD09DA8 4C05 ADDIU SP, SP, 8
\r
15306 148: /*-----------------------------------------------------------*/
\r
15308 150: static inline uint32_t ulPortGetCP0Cause( void )
\r
15310 BFD09B8C 4FF9 ADDIU SP, SP, -16
\r
15311 BFD09B8E CBC3 SW S8, 12(SP)
\r
15312 BFD09B90 CA02 SW S0, 8(SP)
\r
15313 BFD09B92 0FDD MOVE S8, SP
\r
15314 BFD09BCC 4FF9 ADDIU SP, SP, -16
\r
15315 BFD09BCE CBC3 SW S8, 12(SP)
\r
15316 BFD09BD0 CA02 SW S0, 8(SP)
\r
15317 BFD09BD2 0FDD MOVE S8, SP
\r
15318 BFD09C2C 4FF9 ADDIU SP, SP, -16
\r
15319 BFD09C2E CBC3 SW S8, 12(SP)
\r
15320 BFD09C30 CA02 SW S0, 8(SP)
\r
15321 BFD09C32 0FDD MOVE S8, SP
\r
15322 BFD09CAC 4FF9 ADDIU SP, SP, -16
\r
15323 BFD09CAE CBC3 SW S8, 12(SP)
\r
15324 BFD09CB0 CA02 SW S0, 8(SP)
\r
15325 BFD09CB2 0FDD MOVE S8, SP
\r
15326 BFD09CEC 4FF9 ADDIU SP, SP, -16
\r
15327 BFD09CEE CBC3 SW S8, 12(SP)
\r
15328 BFD09CF0 CA02 SW S0, 8(SP)
\r
15329 BFD09CF2 0FDD MOVE S8, SP
\r
15330 152: uint32_t rv;
\r
15332 154: __asm volatile(
\r
15333 BFD09B94 00FC020D MFC0 S0, Cause
\r
15334 BFD09B98 0000FA1E SW S0, 0(S8)
\r
15335 BFD09BD4 00FC020D MFC0 S0, Cause
\r
15336 BFD09BD8 0000FA1E SW S0, 0(S8)
\r
15337 BFD09C34 00FC020D MFC0 S0, Cause
\r
15338 BFD09C38 0000FA1E SW S0, 0(S8)
\r
15339 BFD09CB4 00FC020D MFC0 S0, Cause
\r
15340 BFD09CB8 0000FA1E SW S0, 0(S8)
\r
15341 BFD09CF4 00FC020D MFC0 S0, Cause
\r
15342 BFD09CF8 0000FA1E SW S0, 0(S8)
\r
15344 156: "mfc0 %0,$13,0 \n\t"
\r
15345 157: : "=r" ( rv ) :: );
\r
15348 BFD09B9C 0000FC5E LW V0, 0(S8)
\r
15349 BFD09BDC 0000FC5E LW V0, 0(S8)
\r
15350 BFD09C3C 0000FC5E LW V0, 0(S8)
\r
15351 BFD09CBC 0000FC5E LW V0, 0(S8)
\r
15352 BFD09CFC 0000FC5E LW V0, 0(S8)
\r
15354 BFD09BA0 0FBE MOVE SP, S8
\r
15355 BFD09BA2 4BC3 LW S8, 12(SP)
\r
15356 BFD09BA4 4A02 LW S0, 8(SP)
\r
15357 BFD09BA6 459F JR16 RA
\r
15358 BFD09BA8 4C09 ADDIU SP, SP, 16
\r
15359 BFD09BE0 0FBE MOVE SP, S8
\r
15360 BFD09BE2 4BC3 LW S8, 12(SP)
\r
15361 BFD09BE4 4A02 LW S0, 8(SP)
\r
15362 BFD09BE6 459F JR16 RA
\r
15363 BFD09BE8 4C09 ADDIU SP, SP, 16
\r
15364 BFD09C40 0FBE MOVE SP, S8
\r
15365 BFD09C42 4BC3 LW S8, 12(SP)
\r
15366 BFD09C44 4A02 LW S0, 8(SP)
\r
15367 BFD09C46 459F JR16 RA
\r
15368 BFD09C48 4C09 ADDIU SP, SP, 16
\r
15369 BFD09CC0 0FBE MOVE SP, S8
\r
15370 BFD09CC2 4BC3 LW S8, 12(SP)
\r
15371 BFD09CC4 4A02 LW S0, 8(SP)
\r
15372 BFD09CC6 459F JR16 RA
\r
15373 BFD09CC8 4C09 ADDIU SP, SP, 16
\r
15374 BFD09D00 0FBE MOVE SP, S8
\r
15375 BFD09D02 4BC3 LW S8, 12(SP)
\r
15376 BFD09D04 4A02 LW S0, 8(SP)
\r
15377 BFD09D06 459F JR16 RA
\r
15378 BFD09D08 4C09 ADDIU SP, SP, 16
\r
15379 161: /*-----------------------------------------------------------*/
\r
15381 163: static inline void vPortSetCP0Cause( uint32_t new_cause )
\r
15383 BFD09BAC 4FB0 ADDIU SP, SP, -8
\r
15384 BFD09BAE CBC1 SW S8, 4(SP)
\r
15385 BFD09BB0 0FDD MOVE S8, SP
\r
15386 BFD09BB2 0008F89E SW A0, 8(S8)
\r
15387 BFD09BEC 4FB0 ADDIU SP, SP, -8
\r
15388 BFD09BEE CBC1 SW S8, 4(SP)
\r
15389 BFD09BF0 0FDD MOVE S8, SP
\r
15390 BFD09BF2 0008F89E SW A0, 8(S8)
\r
15391 BFD09C4C 4FB0 ADDIU SP, SP, -8
\r
15392 BFD09C4E CBC1 SW S8, 4(SP)
\r
15393 BFD09C50 0FDD MOVE S8, SP
\r
15394 BFD09C52 0008F89E SW A0, 8(S8)
\r
15395 BFD09CCC 4FB0 ADDIU SP, SP, -8
\r
15396 BFD09CCE CBC1 SW S8, 4(SP)
\r
15397 BFD09CD0 0FDD MOVE S8, SP
\r
15398 BFD09CD2 0008F89E SW A0, 8(S8)
\r
15399 BFD09D0C 4FB0 ADDIU SP, SP, -8
\r
15400 BFD09D0E CBC1 SW S8, 4(SP)
\r
15401 BFD09D10 0FDD MOVE S8, SP
\r
15402 BFD09D12 0008F89E SW A0, 8(S8)
\r
15403 165: ( void ) new_cause;
\r
15405 167: __asm__ __volatile__(
\r
15406 BFD09BB6 0008FC5E LW V0, 8(S8)
\r
15407 BFD09BB8 004D0008 ADDQH.PH ZERO, T0, ZERO
\r
15408 BFD09BBA 02FC004D MTC0 V0, Cause
\r
15409 BFD09BBC 000002FC SLL S7, GP, 0
\r
15410 BFD09BBE 18000000 SLL ZERO, ZERO, 3
\r
15411 BFD09BC0 0FBE1800 SB ZERO, 4030(ZERO)
\r
15412 BFD09BF6 0008FC5E LW V0, 8(S8)
\r
15413 BFD09BF8 004D0008 ADDQH.PH ZERO, T0, ZERO
\r
15414 BFD09BFA 02FC004D MTC0 V0, Cause
\r
15415 BFD09BFC 000002FC SLL S7, GP, 0
\r
15416 BFD09BFE 18000000 SLL ZERO, ZERO, 3
\r
15417 BFD09C00 0FBE1800 SB ZERO, 4030(ZERO)
\r
15418 BFD09C56 0008FC5E LW V0, 8(S8)
\r
15419 BFD09C58 004D0008 ADDQH.PH ZERO, T0, ZERO
\r
15420 BFD09C5A 02FC004D MTC0 V0, Cause
\r
15421 BFD09C5C 000002FC SLL S7, GP, 0
\r
15422 BFD09C5E 18000000 SLL ZERO, ZERO, 3
\r
15423 BFD09C60 0FBE1800 SB ZERO, 4030(ZERO)
\r
15424 BFD09CD6 0008FC5E LW V0, 8(S8)
\r
15425 BFD09CD8 004D0008 ADDQH.PH ZERO, T0, ZERO
\r
15426 BFD09CDA 02FC004D MTC0 V0, Cause
\r
15427 BFD09CDC 000002FC SLL S7, GP, 0
\r
15428 BFD09CDE 18000000 SLL ZERO, ZERO, 3
\r
15429 BFD09CE0 0FBE1800 SB ZERO, 4030(ZERO)
\r
15430 BFD09D16 0008FC5E LW V0, 8(S8)
\r
15431 BFD09D18 004D0008 ADDQH.PH ZERO, T0, ZERO
\r
15432 BFD09D1A 02FC004D MTC0 V0, Cause
\r
15433 BFD09D1C 000002FC SLL S7, GP, 0
\r
15434 BFD09D1E 18000000 SLL ZERO, ZERO, 3
\r
15435 BFD09D20 0FBE1800 SB ZERO, 4030(ZERO)
\r
15437 169: "mtc0 %0,$13,0 \n\t"
\r
15440 172: :"r" ( new_cause ) : );
\r
15442 BFD09BC2 0FBE MOVE SP, S8
\r
15443 BFD09BC4 4BC1 LW S8, 4(SP)
\r
15444 BFD09BC6 459F JR16 RA
\r
15445 BFD09BC8 4C05 ADDIU SP, SP, 8
\r
15446 BFD09C02 0FBE MOVE SP, S8
\r
15447 BFD09C04 4BC1 LW S8, 4(SP)
\r
15448 BFD09C06 459F JR16 RA
\r
15449 BFD09C08 4C05 ADDIU SP, SP, 8
\r
15450 BFD09C62 0FBE MOVE SP, S8
\r
15451 BFD09C64 4BC1 LW S8, 4(SP)
\r
15452 BFD09C66 459F JR16 RA
\r
15453 BFD09C68 4C05 ADDIU SP, SP, 8
\r
15454 BFD09CE2 0FBE MOVE SP, S8
\r
15455 BFD09CE4 4BC1 LW S8, 4(SP)
\r
15456 BFD09CE6 459F JR16 RA
\r
15457 BFD09CE8 4C05 ADDIU SP, SP, 8
\r
15458 BFD09D22 0FBE MOVE SP, S8
\r
15459 BFD09D24 4BC1 LW S8, 4(SP)
\r
15460 BFD09D26 459F JR16 RA
\r
15461 BFD09D28 4C05 ADDIU SP, SP, 8
\r
15462 174: /*-----------------------------------------------------------*/
\r
15464 176: /* This clears the IPL bits, then sets them to
\r
15465 177: configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
\r
15466 178: configASSERT() is defined to ensure an assertion handler does not inadvertently
\r
15467 179: attempt to lower the IPL when the call to assert was triggered because the IPL
\r
15468 180: value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
\r
15469 181: safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
\r
15470 182: those that end in FromISR. FreeRTOS maintains a separate interrupt API to
\r
15471 183: ensure API function and interrupt entry is as fast and as simple as possible. */
\r
15472 184: #ifdef configASSERT
\r
15473 185: #define portDISABLE_INTERRUPTS() \
\r
15475 187: uint32_t ulStatus; \
\r
15476 188: /* Mask interrupts at and below the kernel interrupt priority. */ \
\r
15477 189: ulStatus = ulPortGetCP0Status(); \
\r
15478 190: /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
\r
15479 191: if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
\r
15481 193: ulStatus &= ~portALL_IPL_BITS; \
\r
15482 194: vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
\r
15485 197: #else /* configASSERT */
\r
15486 198: #define portDISABLE_INTERRUPTS() \
\r
15488 200: uint32_t ulStatus; \
\r
15489 201: /* Mask interrupts at and below the kernel interrupt priority. */ \
\r
15490 202: ulStatus = ulPortGetCP0Status(); \
\r
15491 203: ulStatus &= ~portALL_IPL_BITS; \
\r
15492 204: vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
\r
15494 206: #endif /* configASSERT */
\r
15496 208: #define portENABLE_INTERRUPTS() \
\r
15498 210: uint32_t ulStatus; \
\r
15499 211: /* Unmask all interrupts. */ \
\r
15500 212: ulStatus = ulPortGetCP0Status(); \
\r
15501 213: ulStatus &= ~portALL_IPL_BITS; \
\r
15502 214: vPortSetCP0Status( ulStatus ); \
\r
15506 218: extern void vTaskEnterCritical( void );
\r
15507 219: extern void vTaskExitCritical( void );
\r
15508 220: #define portCRITICAL_NESTING_IN_TCB 1
\r
15509 221: #define portENTER_CRITICAL() vTaskEnterCritical()
\r
15510 222: #define portEXIT_CRITICAL() vTaskExitCritical()
\r
15512 224: extern UBaseType_t uxPortSetInterruptMaskFromISR();
\r
15513 225: extern void vPortClearInterruptMaskFromISR( UBaseType_t );
\r
15514 226: #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
\r
15515 227: #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
\r
15517 229: #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
\r
15518 230: #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
\r
15521 233: #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
\r
15523 235: /* Check the configuration. */
\r
15524 236: #if( configMAX_PRIORITIES > 32 )
\r
15525 237: #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
\r
15528 240: /* Store/clear the ready priorities in a bit map. */
\r
15529 241: #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
\r
15530 242: #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
\r
15532 244: /*-----------------------------------------------------------*/
\r
15534 246: #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
\r
15536 248: #endif /* taskRECORD_READY_PRIORITY */
\r
15538 250: /*-----------------------------------------------------------*/
\r
15540 252: /* Task utilities. */
\r
15542 254: #define portYIELD() \
\r
15544 256: uint32_t ulCause; \
\r
15545 257: /* Trigger software interrupt. */ \
\r
15546 258: ulCause = ulPortGetCP0Cause(); \
\r
15547 259: ulCause |= portSW0_BIT; \
\r
15548 260: vPortSetCP0Cause( ulCause ); \
\r
15551 263: extern volatile UBaseType_t uxInterruptNesting;
\r
15552 264: #define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
\r
15554 266: #define portNOP() __asm volatile ( "nop" )
\r
15556 268: /*-----------------------------------------------------------*/
\r
15558 270: /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
15559 271: #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
\r
15560 272: #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
15561 273: /*-----------------------------------------------------------*/
\r
15563 275: #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
\r
15565 277: portYIELD(); \
\r
15568 280: /* Required by the kernel aware debugger. */
\r
15569 281: #ifdef __DEBUG
\r
15570 282: #define portREMOVE_STATIC_QUALIFIER
\r
15573 285: #ifdef __cplusplus
\r
15577 289: #endif /* PORTMACRO_H */
\r
15579 --- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/port.c ------------------
\r
15581 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
15582 3: All rights reserved
\r
15584 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
15586 7: This file is part of the FreeRTOS distribution.
\r
15588 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
15589 10: the terms of the GNU General Public License (version 2) as published by the
\r
15590 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
15592 13: ***************************************************************************
\r
15593 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15594 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
15595 16: >>! obliged to provide the source code for proprietary components !<<
\r
15596 17: >>! outside of the FreeRTOS kernel. !<<
\r
15597 18: ***************************************************************************
\r
15599 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
15600 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
15601 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
15602 23: link: http://www.freertos.org/a00114.html
\r
15604 25: ***************************************************************************
\r
15606 27: * FreeRTOS provides completely free yet professionally developed, *
\r
15607 28: * robust, strictly quality controlled, supported, and cross *
\r
15608 29: * platform software that is more than just the market leader, it *
\r
15609 30: * is the industry's de facto standard. *
\r
15611 32: * Help yourself get started quickly while simultaneously helping *
\r
15612 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
15613 34: * tutorial book, reference manual, or both: *
\r
15614 35: * http://www.FreeRTOS.org/Documentation *
\r
15616 37: ***************************************************************************
\r
15618 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
15619 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
15620 41: defined configASSERT()?
\r
15622 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
15623 44: embedded software for free we request you assist our global community by
\r
15624 45: participating in the support forum.
\r
15626 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
15627 48: be as productive as possible as early as possible. Now you can receive
\r
15628 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
15629 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
15631 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
15632 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
15633 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
15635 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
15636 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
15638 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
15639 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
15640 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
15642 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
15643 64: engineered and independently SIL3 certified version for use in safety and
\r
15644 65: mission critical applications that require provable dependability.
\r
15646 67: 1 tab == 4 spaces!
\r
15649 70: /*-----------------------------------------------------------
\r
15650 71: * Implementation of functions defined in portable.h for the PIC32MZ port.
\r
15651 72: *----------------------------------------------------------*/
\r
15653 74: #include <xc.h>
\r
15654 75: #include <cp0defs.h>
\r
15656 77: /* Scheduler include files. */
\r
15657 78: #include "FreeRTOS.h"
\r
15658 79: #include "task.h"
\r
15660 81: #if !defined(__MEC__)
\r
15661 82: #error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
\r
15664 85: #if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
\r
15665 86: #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
\r
15668 89: /* Hardware specifics. */
\r
15669 90: #define portTIMER_PRESCALE 8
\r
15670 91: #define portPRESCALE_BITS 1
\r
15672 93: /* Bits within various registers. */
\r
15673 94: #define portIE_BIT ( 0x00000001 )
\r
15674 95: #define portEXL_BIT ( 0x00000002 )
\r
15675 96: #define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
\r
15677 98: /* Bits within the CAUSE register. */
\r
15678 99: #define portCORE_SW_0 ( 0x00000100 )
\r
15679 100: #define portCORE_SW_1 ( 0x00000200 )
\r
15681 102: /* The EXL bit is set to ensure interrupts do not occur while the context of
\r
15682 103: the first task is being restored. */
\r
15683 104: /* MEC14xx does not have DSP HW */
\r
15684 105: #define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
\r
15686 107: /* MEC14xx RTOS Timer MMCR's */
\r
15687 108: #define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))
\r
15688 109: #define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
\r
15690 111: /* MEC14xx JTVIC external interrupt controller
\r
15691 112: * is mapped to M14K closely-coupled peripheral space.
\r
15693 114: #define portGIRQ23_RTOS_TIMER_BITPOS (4)
\r
15694 115: #define portGIRQ23_RTOS_TIMER_MASK (1ul << (portGIRQ23_RTOS_TIMER_BITPOS))
\r
15695 116: #define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
\r
15696 117: #define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
\r
15697 118: #define portMMCR_JTVIC_GIRQ23_CLREN *((volatile uint32_t *)(0xBFFFC0F8ul))
\r
15698 119: #define portMMCR_JTVIC_GIRQ23_RESULT *((volatile uint32_t *)(0xBFFFC0FCul))
\r
15699 120: #define portMMCR_JTVIC_GIRQ23_AGCTRL *((volatile uint32_t *)(0xBFFFC23Cul))
\r
15700 121: #define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
\r
15701 122: #define portMMCR_JTVIC_GIRQ23_PRIB *((volatile uint32_t *)(0xBFFFC3F4ul))
\r
15702 123: #define portMMCR_JTVIC_GIRQ23_PRIC *((volatile uint32_t *)(0xBFFFC3F8ul))
\r
15703 124: #define portMMCR_JTVIC_GIRQ23_PRID *((volatile uint32_t *)(0xBFFFC3FCul))
\r
15705 126: /* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
\r
15706 127: #define portGIRQ24_M14K_SOFTIRQ0_BITPOS (1)
\r
15707 128: #define portGIRQ24_M14K_SOFTIRQ0_MASK (1ul << (portGIRQ24_M14K_SOFTIRQ0_BITPOS))
\r
15708 129: #define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))
\r
15709 130: #define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))
\r
15710 131: #define portMMCR_JTVIC_GIRQ24_CLREN *((volatile uint32_t *)(0xBFFFC108ul))
\r
15711 132: #define portMMCR_JTVIC_GIRQ24_RESULT *((volatile uint32_t *)(0xBFFFC10Cul))
\r
15712 133: #define portMMCR_JTVIC_GIRQ24_AGCTRL *((volatile uint32_t *)(0xBFFFC240ul))
\r
15713 134: #define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
\r
15714 135: #define portMMCR_JTVIC_GIRQ24_PRIB *((volatile uint32_t *)(0xBFFFC404ul))
\r
15715 136: #define portMMCR_JTVIC_GIRQ24_PRIC *((volatile uint32_t *)(0xBFFFC408ul))
\r
15716 137: #define portMMCR_JTVIC_GIRQ24_PRID *((volatile uint32_t *)(0xBFFFC40Cul))
\r
15719 140: By default port.c generates its tick interrupt from TIMER1. The user can
\r
15720 141: override this behaviour by:
\r
15721 142: 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
\r
15722 143: which is the function that configures the timer. The function is defined
\r
15723 144: as a weak symbol in this file so if the same function name is used in the
\r
15724 145: application code then the version in the application code will be linked
\r
15725 146: into the application in preference to the version defined in this file.
\r
15726 147: 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
\r
15727 148: to generate the tick interrupt. For example, when timer 1 is used then
\r
15728 149: configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
\r
15729 150: configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
\r
15730 151: 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
\r
15731 152: timer used to generate the tick interrupt. For example, when timer 1 is
\r
15732 153: used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
\r
15733 154: IFS0CLR = _IFS0_T1IF_MASK.
\r
15735 156: #ifndef configTICK_INTERRUPT_VECTOR
\r
15736 157: #define configTICK_INTERRUPT_VECTOR girq23_b4
\r
15737 158: #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
\r
15739 160: #ifndef configCLEAR_TICK_TIMER_INTERRUPT
\r
15740 161: #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
\r
15744 165: /* Let the user override the pre-loading of the initial RA with the address of
\r
15745 166: prvTaskExitError() in case is messes up unwinding of the stack in the
\r
15746 167: debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
\r
15747 168: #ifdef configTASK_RETURN_ADDRESS
\r
15748 169: #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
15750 171: #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
15753 174: /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
\r
15754 175: stack checking. A problem in the ISR stack will trigger an assert, not call the
\r
15755 176: stack overflow hook function (because the stack overflow hook is specific to a
\r
15756 177: task stack, not the ISR stack). */
\r
15757 178: #if( configCHECK_FOR_STACK_OVERFLOW > 2 )
\r
15759 180: /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
\r
15760 181: the task stacks, and so will legitimately appear in many positions within
\r
15761 182: the ISR stack. */
\r
15762 183: #define portISR_STACK_FILL_BYTE 0xee
\r
15764 185: static const uint8_t ucExpectedStackBytes[] = {
\r
15765 186: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
15766 187: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
15767 188: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
15768 189: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
15769 190: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
\r
15771 192: #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
\r
15773 194: /* Define the function away. */
\r
15774 195: #define portCHECK_ISR_STACK()
\r
15775 196: #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
\r
15778 199: /*-----------------------------------------------------------*/
\r
15781 202: * Used to catch tasks that attempt to return from their implementing function.
\r
15783 204: static void prvTaskExitError( void );
\r
15785 206: /*-----------------------------------------------------------*/
\r
15787 208: /* Records the interrupt nesting depth. This is initialised to one as it is
\r
15788 209: decremented to 0 when the first task starts. */
\r
15789 210: volatile UBaseType_t uxInterruptNesting = 0x01;
\r
15791 212: /* Stores the task stack pointer when a switch is made to use the system stack. */
\r
15792 213: UBaseType_t uxSavedTaskStackPointer = 0;
\r
15794 215: /* The stack used by interrupt service routines that cause a context switch. */
\r
15795 216: StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
\r
15797 218: /* The top of stack value ensures there is enough space to store 6 registers on
\r
15798 219: the callers stack, as some functions seem to want to do this. */
\r
15799 220: const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
\r
15801 222: /*-----------------------------------------------------------*/
\r
15803 224: /* Local inline assembly routines to read/write MIPS M14K CP0 registers. Avoids
\r
15804 225: the need for compiler intrinsics which vary with compiler. */
\r
15805 226: static uint32_t prvDisableInterrupt( void )
\r
15807 BFD09A98 4FF9 ADDIU SP, SP, -16
\r
15808 BFD09A9A CBC3 SW S8, 12(SP)
\r
15809 BFD09A9C CA02 SW S0, 8(SP)
\r
15810 BFD09A9E 0FDD MOVE S8, SP
\r
15811 228: uint32_t prev_state;
\r
15813 230: __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
\r
15814 BFD09AA0 477C0010 DI S0
\r
15815 BFD09AA4 18000000 SLL ZERO, ZERO, 3
\r
15816 BFD09AA6 FA1E1800 SB ZERO, -1506(ZERO)
\r
15817 BFD09AA8 0000FA1E SW S0, 0(S8)
\r
15818 231: return prev_state;
\r
15819 BFD09AAC 0000FC5E LW V0, 0(S8)
\r
15821 BFD09AB0 0FBE MOVE SP, S8
\r
15822 BFD09AB2 4BC3 LW S8, 12(SP)
\r
15823 BFD09AB4 4A02 LW S0, 8(SP)
\r
15824 BFD09AB6 459F JR16 RA
\r
15825 BFD09AB8 4C09 ADDIU SP, SP, 16
\r
15829 236: * See header file for description.
\r
15831 238: StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
15833 BFD05630 4FF5 ADDIU SP, SP, -24
\r
15834 BFD05632 CBE5 SW RA, 20(SP)
\r
15835 BFD05634 CBC4 SW S8, 16(SP)
\r
15836 BFD05636 0FDD MOVE S8, SP
\r
15837 BFD05638 0018F89E SW A0, 24(S8)
\r
15838 BFD0563C 001CF8BE SW A1, 28(S8)
\r
15839 BFD05640 0020F8DE SW A2, 32(S8)
\r
15840 240: /* Ensure byte alignment is maintained when leaving this function. */
\r
15841 241: pxTopOfStack--;
\r
15842 BFD05644 0018FC5E LW V0, 24(S8)
\r
15843 BFD05646 4C580018 MOVZ T1, T8, ZERO
\r
15844 BFD05648 4C58 ADDIU V0, V0, -4
\r
15845 BFD0564A 0018F85E SW V0, 24(S8)
\r
15847 243: *pxTopOfStack = (StackType_t) 0xDEADBEEF;
\r
15848 BFD0564E 0018FC5E LW V0, 24(S8)
\r
15849 BFD05652 DEAD41A3 LUI V1, 0xDEAD
\r
15850 BFD05656 BEEF5063 ORI V1, V1, -16657
\r
15851 BFD05658 E9A0BEEF LDC1 F23, -5728(T7)
\r
15852 BFD0565A E9A0 SW V1, 0(V0)
\r
15853 244: pxTopOfStack--;
\r
15854 BFD0565C 0018FC5E LW V0, 24(S8)
\r
15855 BFD0565E 4C580018 MOVZ T1, T8, ZERO
\r
15856 BFD05660 4C58 ADDIU V0, V0, -4
\r
15857 BFD05662 0018F85E SW V0, 24(S8)
\r
15859 246: *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
\r
15860 BFD05666 0018FC5E LW V0, 24(S8)
\r
15861 BFD0566A 123441A3 LUI V1, 0x1234
\r
15862 BFD0566C 50631234 ADDI S1, S4, 20579
\r
15863 BFD0566E 56785063 ORI V1, V1, 22136
\r
15864 BFD05670 E9A05678 PREFX 29, 19(T8)
\r
15865 BFD05672 E9A0 SW V1, 0(V0)
\r
15866 247: pxTopOfStack--;
\r
15867 BFD05674 0018FC5E LW V0, 24(S8)
\r
15868 BFD05676 4C580018 MOVZ T1, T8, ZERO
\r
15869 BFD05678 4C58 ADDIU V0, V0, -4
\r
15870 BFD0567A 0018F85E SW V0, 24(S8)
\r
15872 249: *pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
\r
15873 BFD0567E 4DC677E8 JALS ulPortGetCP0Cause
\r
15874 BFD05680 4DC6 ADDIU T6, T6, 3
\r
15875 BFD05682 0C00 NOP
\r
15876 BFD05684 0C62 MOVE V1, V0
\r
15877 BFD05686 0018FC5E LW V0, 24(S8)
\r
15878 BFD0568A E9A0 SW V1, 0(V0)
\r
15879 250: pxTopOfStack--;
\r
15880 BFD0568C 0018FC5E LW V0, 24(S8)
\r
15881 BFD0568E 4C580018 MOVZ T1, T8, ZERO
\r
15882 BFD05690 4C58 ADDIU V0, V0, -4
\r
15883 BFD05692 0018F85E SW V0, 24(S8)
\r
15885 252: *pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */
\r
15886 BFD05696 0018FC5E LW V0, 24(S8)
\r
15887 BFD0569A ED83 LI V1, 3
\r
15888 BFD0569C E9A0 SW V1, 0(V0)
\r
15889 253: pxTopOfStack--;
\r
15890 BFD0569E 0018FC5E LW V0, 24(S8)
\r
15891 BFD056A0 4C580018 MOVZ T1, T8, ZERO
\r
15892 BFD056A2 4C58 ADDIU V0, V0, -4
\r
15893 BFD056A4 0018F85E SW V0, 24(S8)
\r
15895 255: *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
\r
15896 BFD056A8 001CFC7E LW V1, 28(S8)
\r
15897 BFD056AC 0018FC5E LW V0, 24(S8)
\r
15898 BFD056B0 E9A0 SW V1, 0(V0)
\r
15899 256: pxTopOfStack--;
\r
15900 BFD056B2 0018FC5E LW V0, 24(S8)
\r
15901 BFD056B4 4C580018 MOVZ T1, T8, ZERO
\r
15902 BFD056B6 4C58 ADDIU V0, V0, -4
\r
15903 BFD056B8 0018F85E SW V0, 24(S8)
\r
15905 258: *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
\r
15906 BFD056BC BFD041A2 LUI V0, 0xBFD0
\r
15907 BFD056BE 3062BFD0 LDC1 F30, 12386(S0)
\r
15908 BFD056C0 7BBD3062 ADDIU V1, V0, 31677
\r
15909 BFD056C2 FC5E7BBD ADDIUPC A3, 4062302
\r
15910 BFD056C4 0018FC5E LW V0, 24(S8)
\r
15911 BFD056C8 E9A0 SW V1, 0(V0)
\r
15912 259: pxTopOfStack -= 15;
\r
15913 BFD056CA 0018FC5E LW V0, 24(S8)
\r
15914 BFD056CE FFC43042 ADDIU V0, V0, -60
\r
15915 BFD056D0 F85EFFC4 LW S8, -1954(A0)
\r
15916 BFD056D2 0018F85E SW V0, 24(S8)
\r
15918 261: *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
\r
15919 BFD056D6 0020FC7E LW V1, 32(S8)
\r
15920 BFD056DA 0018FC5E LW V0, 24(S8)
\r
15921 BFD056DE E9A0 SW V1, 0(V0)
\r
15922 262: pxTopOfStack -= 15;
\r
15923 BFD056E0 0018FC5E LW V0, 24(S8)
\r
15924 BFD056E4 FFC43042 ADDIU V0, V0, -60
\r
15925 BFD056E6 F85EFFC4 LW S8, -1954(A0)
\r
15926 BFD056E8 0018F85E SW V0, 24(S8)
\r
15928 264: return pxTopOfStack;
\r
15929 BFD056EC 0018FC5E LW V0, 24(S8)
\r
15931 BFD056F0 0FBE MOVE SP, S8
\r
15932 BFD056F2 4BE5 LW RA, 20(SP)
\r
15933 BFD056F4 4BC4 LW S8, 16(SP)
\r
15934 BFD056F6 4C0D ADDIU SP, SP, 24
\r
15935 BFD056F8 459F JR16 RA
\r
15936 BFD056FA 0C00 NOP
\r
15937 266: /*-----------------------------------------------------------*/
\r
15939 268: static void prvTaskExitError( void )
\r
15941 BFD07BBC 4FF1 ADDIU SP, SP, -32
\r
15942 BFD07BBE CBE7 SW RA, 28(SP)
\r
15943 BFD07BC0 CBC6 SW S8, 24(SP)
\r
15944 BFD07BC2 0FDD MOVE S8, SP
\r
15945 270: /* A function that implements a task must not exit or attempt to return to
\r
15946 271: its caller as there is nothing to return to. If a task wants to exit it
\r
15947 272: should instead call vTaskDelete( NULL ).
\r
15949 274: Artificially force an assert() to be triggered if configASSERT() is
\r
15950 275: defined, then stop here so application writers can catch the error. */
\r
15951 276: configASSERT( uxSavedTaskStackPointer == 0UL );
\r
15952 BFD07BC4 802CFC5C LW V0, -32724(GP)
\r
15953 BFD07BC8 000940E2 BEQZC V0, 0xBFD07BDE
\r
15954 BFD07BCC BFD141A2 LUI V0, 0xBFD1
\r
15955 BFD07BCE 3082BFD1 LDC1 F30, 12418(S1)
\r
15956 BFD07BD0 8AAC3082 ADDIU A0, V0, -30036
\r
15957 BFD07BD2 8AAC SB A1, 12(V0)
\r
15958 BFD07BD4 011430A0 ADDIU A1, ZERO, 276
\r
15959 BFD07BD8 4B7E77E8 JALS vAssertCalled
\r
15960 BFD07BDA 4B7E LW K1, 120(SP)
\r
15961 BFD07BDC 0C00 NOP
\r
15962 277: portDISABLE_INTERRUPTS();
\r
15963 BFD07BDE 4DA677E8 JALS ulPortGetCP0Status
\r
15964 BFD07BE0 4DA6 ADDIU T5, T5, 3
\r
15965 BFD07BE2 0C00 NOP
\r
15966 BFD07BE4 0010F85E SW V0, 16(S8)
\r
15967 BFD07BE8 0010FC7E LW V1, 16(S8)
\r
15968 BFD07BEC 000141A2 LUI V0, 0x1
\r
15969 BFD07BF0 FC005042 ORI V0, V0, -1024
\r
15970 BFD07BF2 4493FC00 LW ZERO, 17555(ZERO)
\r
15971 BFD07BF4 4493 AND16 V0, V1
\r
15972 BFD07BF6 50400042 SRL V0, V0, 10
\r
15973 BFD07BF8 B0425040 ORI V0, ZERO, -20414
\r
15974 BFD07BFA 0003B042 SLTIU V0, V0, 3
\r
15975 BFD07BFE 001140E2 BEQZC V0, 0xBFD07C24
\r
15976 BFD07C02 0010FC7E LW V1, 16(S8)
\r
15977 BFD07C06 FFFE41A2 LUI V0, 0xFFFE
\r
15978 BFD07C08 5042FFFE LW RA, 20546(S8)
\r
15979 BFD07C0A 03FF5042 ORI V0, V0, 1023
\r
15980 BFD07C0E 4493 AND16 V0, V1
\r
15981 BFD07C10 0010F85E SW V0, 16(S8)
\r
15982 BFD07C14 0010FC5E LW V0, 16(S8)
\r
15983 BFD07C18 0C005042 ORI V0, V0, 3072
\r
15984 BFD07C1A 0C00 NOP
\r
15985 BFD07C1C 0C82 MOVE A0, V0
\r
15986 BFD07C1E 4DB677E8 JALS vPortSetCP0Status
\r
15987 BFD07C20 4DB6 ADDIU T5, T5, -5
\r
15988 BFD07C22 0C00 NOP
\r
15990 BFD07C24 CFFF B 0xBFD07C24
\r
15991 BFD07C26 0C00 NOP
\r
15993 280: /*-----------------------------------------------------------*/
\r
15996 283: * Setup a timer for a regular tick. This function uses peripheral timer 1.
\r
15997 284: * The function is declared weak so an application writer can use a different
\r
15998 285: * timer by redefining this implementation. If a different timer is used then
\r
15999 286: * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
\r
16000 287: * ensure the RTOS provided tick interrupt handler is installed on the correct
\r
16001 288: * vector number. When Timer 1 is used the vector number is defined as
\r
16002 289: * _TIMER_1_VECTOR.
\r
16004 291: __attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
\r
16006 BFD06284 4FF1 ADDIU SP, SP, -32
\r
16007 BFD06286 CBE7 SW RA, 28(SP)
\r
16008 BFD06288 CBC6 SW S8, 24(SP)
\r
16009 BFD0628A 0FDD MOVE S8, SP
\r
16010 293: /* MEC14xx RTOS Timer whose input clock is 32KHz */
\r
16011 294: const uint32_t preload = ( 32768ul / ( configTICK_RATE_HZ ) );
\r
16012 BFD0628C ED20 LI V0, 32
\r
16013 BFD0628E 0010F85E SW V0, 16(S8)
\r
16014 295: configASSERT( preload != 0UL );
\r
16015 BFD06292 0010FC5E LW V0, 16(S8)
\r
16016 BFD06296 000940A2 BNEZC V0, 0xBFD062AC
\r
16017 BFD0629A BFD141A2 LUI V0, 0xBFD1
\r
16018 BFD0629C 3082BFD1 LDC1 F30, 12418(S1)
\r
16019 BFD0629E 8AAC3082 ADDIU A0, V0, -30036
\r
16020 BFD062A0 8AAC SB A1, 12(V0)
\r
16021 BFD062A2 012730A0 ADDIU A1, ZERO, 295
\r
16022 BFD062A6 4B7E77E8 JALS vAssertCalled
\r
16023 BFD062A8 4B7E LW K1, 120(SP)
\r
16024 BFD062AA 0C00 NOP
\r
16026 297: portMMCR_RTMR_CONTROL = 0ul;
\r
16027 BFD062AC A00041A2 LUI V0, 0xA000
\r
16028 BFD062B0 74085042 ORI V0, V0, 29704
\r
16029 BFD062B2 E8207408 JALS 0xB811D040
\r
16030 BFD062B4 E820 SW S0, 0(V0)
\r
16031 298: portMMCR_RTMR_PRELOAD = preload;
\r
16032 BFD062B6 A00041A2 LUI V0, 0xA000
\r
16033 BFD062BA 74045042 ORI V0, V0, 29700
\r
16034 BFD062BC FC7E7404 JALS 0xB809F8FC
\r
16035 BFD062BE 0010FC7E LW V1, 16(S8)
\r
16036 BFD062C2 E9A0 SW V1, 0(V0)
\r
16038 300: portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
\r
16039 BFD062C4 BFFF41A2 LUI V0, 0xBFFF
\r
16040 BFD062C6 5042BFFF LDC1 F31, 20546(RA)
\r
16041 BFD062C8 C0F05042 ORI V0, V0, -16144
\r
16042 BFD062CC ED90 LI V1, 16
\r
16043 BFD062CE E9A0 SW V1, 0(V0)
\r
16044 301: portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
\r
16045 BFD062D0 BFFF41A2 LUI V0, 0xBFFF
\r
16046 BFD062D2 5042BFFF LDC1 F31, 20546(RA)
\r
16047 BFD062D4 C3F05042 ORI V0, V0, -15376
\r
16048 BFD062D8 BFFF41A3 LUI V1, 0xBFFF
\r
16049 BFD062DA 5063BFFF LDC1 F31, 20579(RA)
\r
16050 BFD062DC C3F05063 ORI V1, V1, -15376
\r
16051 BFD062E0 6A30 LW A0, 0(V1)
\r
16052 BFD062E2 FFF041A3 LUI V1, 0xFFF0
\r
16053 BFD062E4 5063FFF0 LW RA, 20579(S0)
\r
16054 BFD062E6 FFFF5063 ORI V1, V1, -1
\r
16055 BFD062E8 449CFFFF LW RA, 17564(RA)
\r
16056 BFD062EA 449C AND16 V1, A0
\r
16057 BFD062EC E9A0 SW V1, 0(V0)
\r
16058 302: portMMCR_JTVIC_GIRQ23_PRIA |= ( ( configKERNEL_INTERRUPT_PRIORITY ) << 16 );
\r
16059 BFD062EE BFFF41A2 LUI V0, 0xBFFF
\r
16060 BFD062F0 5042BFFF LDC1 F31, 20546(RA)
\r
16061 BFD062F2 C3F05042 ORI V0, V0, -15376
\r
16062 BFD062F6 BFFF41A3 LUI V1, 0xBFFF
\r
16063 BFD062F8 5063BFFF LDC1 F31, 20579(RA)
\r
16064 BFD062FA C3F05063 ORI V1, V1, -15376
\r
16065 BFD062FE 69B0 LW V1, 0(V1)
\r
16066 BFD06300 E9A0 SW V1, 0(V0)
\r
16067 303: portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
\r
16068 BFD06302 BFFF41A2 LUI V0, 0xBFFF
\r
16069 BFD06304 5042BFFF LDC1 F31, 20546(RA)
\r
16070 BFD06306 C0F45042 ORI V0, V0, -16140
\r
16071 BFD0630A ED90 LI V1, 16
\r
16072 BFD0630C E9A0 SW V1, 0(V0)
\r
16074 305: portMMCR_RTMR_CONTROL = 0x0Fu;
\r
16075 BFD0630E A00041A2 LUI V0, 0xA000
\r
16076 BFD06312 74085042 ORI V0, V0, 29704
\r
16077 BFD06314 ED8F7408 JALS 0xB811DB1E
\r
16078 BFD06316 ED8F LI V1, 15
\r
16079 BFD06318 E9A0 SW V1, 0(V0)
\r
16081 BFD0631A 0FBE MOVE SP, S8
\r
16082 BFD0631C 4BE7 LW RA, 28(SP)
\r
16083 BFD0631E 4BC6 LW S8, 24(SP)
\r
16084 BFD06320 4C11 ADDIU SP, SP, 32
\r
16085 BFD06322 459F JR16 RA
\r
16086 BFD06324 0C00 NOP
\r
16087 307: /*-----------------------------------------------------------*/
\r
16089 309: void vPortEndScheduler(void)
\r
16091 BFD097A8 4FF5 ADDIU SP, SP, -24
\r
16092 BFD097AA CBE5 SW RA, 20(SP)
\r
16093 BFD097AC CBC4 SW S8, 16(SP)
\r
16094 BFD097AE 0FDD MOVE S8, SP
\r
16095 311: /* Not implemented in ports where there is nothing to return to.
\r
16096 312: Artificially force an assert. */
\r
16097 313: configASSERT( uxInterruptNesting == 1000UL );
\r
16098 BFD097B0 8014FC7C LW V1, -32748(GP)
\r
16099 BFD097B4 03E83040 ADDIU V0, ZERO, 1000
\r
16100 BFD097B8 000A9443 BEQ V1, V0, 0xBFD097D0
\r
16101 BFD097BA 0C00000A SLL ZERO, T2, 1
\r
16102 BFD097BC 0C00 NOP
\r
16103 BFD097BE BFD141A2 LUI V0, 0xBFD1
\r
16104 BFD097C0 3082BFD1 LDC1 F30, 12418(S1)
\r
16105 BFD097C2 8AAC3082 ADDIU A0, V0, -30036
\r
16106 BFD097C4 8AAC SB A1, 12(V0)
\r
16107 BFD097C6 013930A0 ADDIU A1, ZERO, 313
\r
16108 BFD097CA 4B7E77E8 JALS vAssertCalled
\r
16109 BFD097CC 4B7E LW K1, 120(SP)
\r
16110 BFD097CE 0C00 NOP
\r
16112 BFD097D0 0FBE MOVE SP, S8
\r
16113 BFD097D2 4BE5 LW RA, 20(SP)
\r
16114 BFD097D4 4BC4 LW S8, 16(SP)
\r
16115 BFD097D6 4C0D ADDIU SP, SP, 24
\r
16116 BFD097D8 459F JR16 RA
\r
16117 BFD097DA 0C00 NOP
\r
16118 315: /*-----------------------------------------------------------*/
\r
16120 317: BaseType_t xPortStartScheduler( void )
\r
16122 BFD06898 4FF5 ADDIU SP, SP, -24
\r
16123 BFD0689A CBE5 SW RA, 20(SP)
\r
16124 BFD0689C CBC4 SW S8, 16(SP)
\r
16125 BFD0689E 0FDD MOVE S8, SP
\r
16126 319: extern void vPortStartFirstTask( void );
\r
16127 320: extern void *pxCurrentTCB;
\r
16129 322: #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
\r
16131 324: /* Fill the ISR stack to make it easy to asses how much is being used. */
\r
16132 325: memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
\r
16133 BFD068A0 BFD241A2 LUI V0, 0xBFD2
\r
16134 BFD068A2 3082BFD2 LDC1 F30, 12418(S2)
\r
16135 BFD068A4 AD683082 ADDIU A0, V0, -21144
\r
16136 BFD068A6 AD68 BNEZ V0, 0xBFD06978
\r
16137 BFD068A8 00EE30A0 ADDIU A1, ZERO, 238
\r
16138 BFD068AA 30C000EE ROTR A3, T6, 6
\r
16139 BFD068AC 0BE030C0 ADDIU A2, ZERO, 3040
\r
16140 BFD068AE 0BE0 LBU A3, 0(A2)
\r
16141 BFD068B0 36F677E8 JALS 0xBFD06DEC
\r
16142 BFD068B2 0C0036F6 LHU S7, 3072(S6)
\r
16143 BFD068B4 0C00 NOP
\r
16145 327: #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
\r
16147 329: /* Clear the software interrupt flag. */
\r
16148 330: portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
\r
16149 BFD068B6 BFFF41A2 LUI V0, 0xBFFF
\r
16150 BFD068B8 5042BFFF LDC1 F31, 20546(RA)
\r
16151 BFD068BA C1005042 ORI V0, V0, -16128
\r
16152 BFD068BE ED82 LI V1, 2
\r
16153 BFD068C0 E9A0 SW V1, 0(V0)
\r
16155 332: /* Set software timer priority.
\r
16156 333: Each GIRQn has one nibble containing its priority */
\r
16157 334: portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
\r
16158 BFD068C2 BFFF41A2 LUI V0, 0xBFFF
\r
16159 BFD068C4 5042BFFF LDC1 F31, 20546(RA)
\r
16160 BFD068C6 C4005042 ORI V0, V0, -15360
\r
16161 BFD068CA BFFF41A3 LUI V1, 0xBFFF
\r
16162 BFD068CC 5063BFFF LDC1 F31, 20579(RA)
\r
16163 BFD068CE C4005063 ORI V1, V1, -15360
\r
16164 BFD068D2 6A30 LW A0, 0(V1)
\r
16165 BFD068D4 FF0F3060 ADDIU V1, ZERO, -241
\r
16166 BFD068D6 449CFF0F LW T8, 17564(T7)
\r
16167 BFD068D8 449C AND16 V1, A0
\r
16168 BFD068DA E9A0 SW V1, 0(V0)
\r
16169 335: portMMCR_JTVIC_GIRQ24_PRIA |= ( configKERNEL_INTERRUPT_PRIORITY << 4 );
\r
16170 BFD068DC BFFF41A2 LUI V0, 0xBFFF
\r
16171 BFD068DE 5042BFFF LDC1 F31, 20546(RA)
\r
16172 BFD068E0 C4005042 ORI V0, V0, -15360
\r
16173 BFD068E4 BFFF41A3 LUI V1, 0xBFFF
\r
16174 BFD068E6 5063BFFF LDC1 F31, 20579(RA)
\r
16175 BFD068E8 C4005063 ORI V1, V1, -15360
\r
16176 BFD068EC 69B0 LW V1, 0(V1)
\r
16177 BFD068EE E9A0 SW V1, 0(V0)
\r
16179 337: /* Enable software interrupt. */
\r
16180 338: portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
\r
16181 BFD068F0 BFFF41A2 LUI V0, 0xBFFF
\r
16182 BFD068F2 5042BFFF LDC1 F31, 20546(RA)
\r
16183 BFD068F4 C1045042 ORI V0, V0, -16124
\r
16184 BFD068F8 ED82 LI V1, 2
\r
16185 BFD068FA E9A0 SW V1, 0(V0)
\r
16187 340: /* Setup the timer to generate the tick. Interrupts will have been
\r
16188 341: disabled by the time we get here. */
\r
16189 342: vApplicationSetupTickTimerInterrupt();
\r
16190 BFD068FC 314277E8 JALS vApplicationSetupTickTimerInterrupt
\r
16191 BFD068FE 0C003142 ADDIU T2, V0, 3072
\r
16192 BFD06900 0C00 NOP
\r
16194 344: /* Kick off the highest priority task that has been created so far.
\r
16195 345: Its stack location is loaded into uxSavedTaskStackPointer. */
\r
16196 346: uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
\r
16197 BFD06902 8030FC5C LW V0, -32720(GP)
\r
16198 BFD06906 6920 LW V0, 0(V0)
\r
16199 BFD06908 802CF85C SW V0, -32724(GP)
\r
16200 347: vPortStartFirstTask();
\r
16201 BFD0690C 055A77E8 JALS 0xBFD00AB4
\r
16202 BFD0690E 055A ADDU V0, A1, A1
\r
16203 BFD06910 0C00 NOP
\r
16205 349: /* Should never get here as the tasks will now be executing! Call the task
\r
16206 350: exit error function to prevent compiler warnings about a static function
\r
16207 351: not being called in the case that the application writer overrides this
\r
16208 352: functionality by defining configTASK_RETURN_ADDRESS. */
\r
16209 353: prvTaskExitError();
\r
16210 BFD06912 3DDE77E8 JALS prvTaskExitError
\r
16211 BFD06914 0C003DDE LH T6, 3072(S8)
\r
16212 BFD06916 0C00 NOP
\r
16214 355: return pdFALSE;
\r
16215 BFD06918 0C40 MOVE V0, ZERO
\r
16217 BFD0691A 0FBE MOVE SP, S8
\r
16218 BFD0691C 4BE5 LW RA, 20(SP)
\r
16219 BFD0691E 4BC4 LW S8, 16(SP)
\r
16220 BFD06920 4C0D ADDIU SP, SP, 24
\r
16221 BFD06922 459F JR16 RA
\r
16222 BFD06924 0C00 NOP
\r
16223 357: /*-----------------------------------------------------------*/
\r
16225 359: void vPortIncrementTick( void )
\r
16227 BFD069B8 4FF1 ADDIU SP, SP, -32
\r
16228 BFD069BA CBE7 SW RA, 28(SP)
\r
16229 BFD069BC CBC6 SW S8, 24(SP)
\r
16230 BFD069BE 0FDD MOVE S8, SP
\r
16231 361: UBaseType_t uxSavedStatus;
\r
16232 362: uint32_t ulCause;
\r
16234 364: uxSavedStatus = uxPortSetInterruptMaskFromISR();
\r
16235 BFD069C0 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
16236 BFD069C4 0C00 NOP
\r
16237 BFD069C6 0010F85E SW V0, 16(S8)
\r
16239 366: if( xTaskIncrementTick() != pdFALSE )
\r
16240 BFD069CA 104077E8 JALS xTaskIncrementTick
\r
16241 BFD069CC 0C001040 ADDI V0, ZERO, 3072
\r
16242 BFD069CE 0C00 NOP
\r
16243 BFD069D0 001040E2 BEQZC V0, 0xBFD069F4
\r
16245 368: /* Pend a context switch. */
\r
16246 369: ulCause = ulPortGetCP0Cause();
\r
16247 BFD069D4 4DC677E8 JALS ulPortGetCP0Cause
\r
16248 BFD069D6 4DC6 ADDIU T6, T6, 3
\r
16249 BFD069D8 0C00 NOP
\r
16250 BFD069DA 0014F85E SW V0, 20(S8)
\r
16251 370: ulCause |= ( 1ul << 8UL );
\r
16252 BFD069DE 0014FC5E LW V0, 20(S8)
\r
16253 BFD069E2 01005042 ORI V0, V0, 256
\r
16254 BFD069E6 0014F85E SW V0, 20(S8)
\r
16255 371: vPortSetCP0Cause( ulCause );
\r
16256 BFD069EA 0014FC9E LW A0, 20(S8)
\r
16257 BFD069EE 4DD677E8 JALS vPortSetCP0Cause
\r
16258 BFD069F0 4DD6 ADDIU T6, T6, -5
\r
16259 BFD069F2 0C00 NOP
\r
16262 374: vPortClearInterruptMaskFromISR( uxSavedStatus );
\r
16263 BFD069F4 0010FC9E LW A0, 16(S8)
\r
16264 BFD069F8 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
16265 BFD069FA 4D5E ADDIU T2, T2, -1
\r
16266 BFD069FC 0C00 NOP
\r
16268 376: /* Look for the ISR stack getting near or past its limit. */
\r
16269 377: portCHECK_ISR_STACK();
\r
16270 BFD069FE BFD241A2 LUI V0, 0xBFD2
\r
16271 BFD06A00 3082BFD2 LDC1 F30, 12418(S2)
\r
16272 BFD06A02 AD683082 ADDIU A0, V0, -21144
\r
16273 BFD06A04 AD68 BNEZ V0, 0xBFD06AD6
\r
16274 BFD06A06 BFD141A2 LUI V0, 0xBFD1
\r
16275 BFD06A08 30A2BFD1 LDC1 F30, 12450(S1)
\r
16276 BFD06A0A 8A9430A2 ADDIU A1, V0, -30060
\r
16277 BFD06A0C 8A94 SB A1, 4(S1)
\r
16278 BFD06A0E EF14 LI A2, 20
\r
16279 BFD06A10 3DA677E8 JALS 0xBFD07B4C
\r
16280 BFD06A12 0C003DA6 LH T5, 3072(A2)
\r
16281 BFD06A14 0C00 NOP
\r
16282 BFD06A16 000940E2 BEQZC V0, 0xBFD06A2C
\r
16283 BFD06A1A BFD141A2 LUI V0, 0xBFD1
\r
16284 BFD06A1C 3082BFD1 LDC1 F30, 12418(S1)
\r
16285 BFD06A1E 8AAC3082 ADDIU A0, V0, -30036
\r
16286 BFD06A20 8AAC SB A1, 12(V0)
\r
16287 BFD06A22 017930A0 ADDIU A1, ZERO, 377
\r
16288 BFD06A26 4B7E77E8 JALS vAssertCalled
\r
16289 BFD06A28 4B7E LW K1, 120(SP)
\r
16290 BFD06A2A 0C00 NOP
\r
16292 379: /* Clear timer interrupt. */
\r
16293 380: configCLEAR_TICK_TIMER_INTERRUPT();
\r
16294 BFD06A2C BFFF41A2 LUI V0, 0xBFFF
\r
16295 BFD06A2E 5042BFFF LDC1 F31, 20546(RA)
\r
16296 BFD06A30 C0F05042 ORI V0, V0, -16144
\r
16297 BFD06A34 ED90 LI V1, 16
\r
16298 BFD06A36 E9A0 SW V1, 0(V0)
\r
16300 BFD06A38 0FBE MOVE SP, S8
\r
16301 BFD06A3A 4BE7 LW RA, 28(SP)
\r
16302 BFD06A3C 4BC6 LW S8, 24(SP)
\r
16303 BFD06A3E 4C11 ADDIU SP, SP, 32
\r
16304 BFD06A40 459F JR16 RA
\r
16305 BFD06A42 0C00 NOP
\r
16306 382: /*-----------------------------------------------------------*/
\r
16308 384: UBaseType_t uxPortSetInterruptMaskFromISR( void )
\r
16310 BFD08EBC 4FF1 ADDIU SP, SP, -32
\r
16311 BFD08EBE CBE7 SW RA, 28(SP)
\r
16312 BFD08EC0 CBC6 SW S8, 24(SP)
\r
16313 BFD08EC2 0FDD MOVE S8, SP
\r
16314 386: UBaseType_t uxSavedStatusRegister;
\r
16316 388: prvDisableInterrupt();
\r
16317 BFD08EC4 4D4C77E8 JALS prvDisableInterrupt
\r
16318 BFD08EC6 4D4C ADDIU T2, T2, 6
\r
16319 BFD08EC8 0C00 NOP
\r
16320 389: uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
\r
16321 BFD08ECA 4DA677E8 JALS ulPortGetCP0Status
\r
16322 BFD08ECC 4DA6 ADDIU T5, T5, 3
\r
16323 BFD08ECE 0C00 NOP
\r
16324 BFD08ED0 00015042 ORI V0, V0, 1
\r
16325 BFD08ED4 0010F85E SW V0, 16(S8)
\r
16327 391: /* This clears the IPL bits, then sets them to
\r
16328 392: configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
\r
16329 393: from an interrupt that has a priority above
\r
16330 394: configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
\r
16331 395: can only result in the IPL being unchanged or raised, and therefore never
\r
16333 397: vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
\r
16334 BFD08ED8 0010FC7E LW V1, 16(S8)
\r
16335 BFD08EDC FFFE41A2 LUI V0, 0xFFFE
\r
16336 BFD08EDE 5042FFFE LW RA, 20546(S8)
\r
16337 BFD08EE0 03FF5042 ORI V0, V0, 1023
\r
16338 BFD08EE4 4493 AND16 V0, V1
\r
16339 BFD08EE6 0C005042 ORI V0, V0, 3072
\r
16340 BFD08EE8 0C00 NOP
\r
16341 BFD08EEA 0C82 MOVE A0, V0
\r
16342 BFD08EEC 4DB677E8 JALS vPortSetCP0Status
\r
16343 BFD08EEE 4DB6 ADDIU T5, T5, -5
\r
16344 BFD08EF0 0C00 NOP
\r
16346 399: return uxSavedStatusRegister;
\r
16347 BFD08EF2 0010FC5E LW V0, 16(S8)
\r
16349 BFD08EF6 0FBE MOVE SP, S8
\r
16350 BFD08EF8 4BE7 LW RA, 28(SP)
\r
16351 BFD08EFA 4BC6 LW S8, 24(SP)
\r
16352 BFD08EFC 4C11 ADDIU SP, SP, 32
\r
16353 BFD08EFE 459F JR16 RA
\r
16354 BFD08F00 0C00 NOP
\r
16355 401: /*-----------------------------------------------------------*/
\r
16357 403: void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
\r
16359 BFD09ABC 4FF5 ADDIU SP, SP, -24
\r
16360 BFD09ABE CBE5 SW RA, 20(SP)
\r
16361 BFD09AC0 CBC4 SW S8, 16(SP)
\r
16362 BFD09AC2 0FDD MOVE S8, SP
\r
16363 BFD09AC4 0018F89E SW A0, 24(S8)
\r
16364 405: vPortSetCP0Status( uxSavedStatusRegister );
\r
16365 BFD09AC8 0018FC9E LW A0, 24(S8)
\r
16366 BFD09ACC 4DB677E8 JALS vPortSetCP0Status
\r
16367 BFD09ACE 4DB6 ADDIU T5, T5, -5
\r
16368 BFD09AD0 0C00 NOP
\r
16370 BFD09AD2 0FBE MOVE SP, S8
\r
16371 BFD09AD4 4BE5 LW RA, 20(SP)
\r
16372 BFD09AD6 4BC4 LW S8, 16(SP)
\r
16373 BFD09AD8 4C0D ADDIU SP, SP, 24
\r
16374 BFD09ADA 459F JR16 RA
\r
16375 BFD09ADC 0C00 NOP
\r
16376 407: /*-----------------------------------------------------------*/
\r
16382 --- c:/e/dev/freertos/workingcopy/freertos/source/portable/memmang/heap_2.c ---------------------------
\r
16384 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
16385 3: All rights reserved
\r
16387 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
16389 7: This file is part of the FreeRTOS distribution.
\r
16391 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
16392 10: the terms of the GNU General Public License (version 2) as published by the
\r
16393 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
16395 13: ***************************************************************************
\r
16396 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
16397 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16398 16: >>! obliged to provide the source code for proprietary components !<<
\r
16399 17: >>! outside of the FreeRTOS kernel. !<<
\r
16400 18: ***************************************************************************
\r
16402 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
16403 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
16404 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
16405 23: link: http://www.freertos.org/a00114.html
\r
16407 25: ***************************************************************************
\r
16409 27: * FreeRTOS provides completely free yet professionally developed, *
\r
16410 28: * robust, strictly quality controlled, supported, and cross *
\r
16411 29: * platform software that is more than just the market leader, it *
\r
16412 30: * is the industry's de facto standard. *
\r
16414 32: * Help yourself get started quickly while simultaneously helping *
\r
16415 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
16416 34: * tutorial book, reference manual, or both: *
\r
16417 35: * http://www.FreeRTOS.org/Documentation *
\r
16419 37: ***************************************************************************
\r
16421 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
16422 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
16423 41: defined configASSERT()?
\r
16425 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
16426 44: embedded software for free we request you assist our global community by
\r
16427 45: participating in the support forum.
\r
16429 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
16430 48: be as productive as possible as early as possible. Now you can receive
\r
16431 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
16432 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
16434 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
16435 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
16436 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
16438 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
16439 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
16441 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
16442 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
16443 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
16445 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
16446 64: engineered and independently SIL3 certified version for use in safety and
\r
16447 65: mission critical applications that require provable dependability.
\r
16449 67: 1 tab == 4 spaces!
\r
16453 71: * A sample implementation of pvPortMalloc() and vPortFree() that permits
\r
16454 72: * allocated blocks to be freed, but does not combine adjacent free blocks
\r
16455 73: * into a single larger block (and so will fragment memory). See heap_4.c for
\r
16456 74: * an equivalent that does combine adjacent blocks into single larger blocks.
\r
16458 76: * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the
\r
16459 77: * memory management pages of http://www.FreeRTOS.org for more information.
\r
16461 79: #include <stdlib.h>
\r
16463 81: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
\r
16464 82: all the API functions to use the MPU wrappers. That should only be done when
\r
16465 83: task.h is included from an application file. */
\r
16466 84: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
\r
16468 86: #include "FreeRTOS.h"
\r
16469 87: #include "task.h"
\r
16471 89: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
\r
16473 91: /* A few bytes might be lost to byte aligning the heap start address. */
\r
16474 92: #define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
\r
16477 95: * Initialises the heap structures before their first use.
\r
16479 97: static void prvHeapInit( void );
\r
16481 99: /* Allocate the memory for the heap. */
\r
16482 100: static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
\r
16484 102: /* Define the linked list structure. This is used to link free blocks in order
\r
16485 103: of their size. */
\r
16486 104: typedef struct A_BLOCK_LINK
\r
16488 106: struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */
\r
16489 107: size_t xBlockSize; /*<< The size of the free block. */
\r
16490 108: } BlockLink_t;
\r
16493 111: static const uint16_t heapSTRUCT_SIZE = ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
\r
16494 112: #define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
\r
16496 114: /* Create a couple of list links to mark the start and end of the list. */
\r
16497 115: static BlockLink_t xStart, xEnd;
\r
16499 117: /* Keeps track of the number of free bytes remaining, but says nothing about
\r
16500 118: fragmentation. */
\r
16501 119: static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
\r
16503 121: /* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
\r
16506 124: * Insert a block into the list of free blocks - which is ordered by size of
\r
16507 125: * the block. Small blocks at the start of the list and large blocks at the end
\r
16508 126: * of the list.
\r
16510 128: #define prvInsertBlockIntoFreeList( pxBlockToInsert ) \
\r
16512 130: BlockLink_t *pxIterator; \
\r
16513 131: size_t xBlockSize; \
\r
16515 133: xBlockSize = pxBlockToInsert->xBlockSize; \
\r
16517 135: /* Iterate through the list until a block is found that has a larger size */ \
\r
16518 136: /* than the block we are inserting. */ \
\r
16519 137: for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \
\r
16521 139: /* There is nothing to do here - just iterate to the correct position. */ \
\r
16524 142: /* Update the list to include the block being inserted in the correct */ \
\r
16525 143: /* position. */ \
\r
16526 144: pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \
\r
16527 145: pxIterator->pxNextFreeBlock = pxBlockToInsert; \
\r
16529 147: /*-----------------------------------------------------------*/
\r
16531 149: void *pvPortMalloc( size_t xWantedSize )
\r
16533 BFD0222C 4FE9 ADDIU SP, SP, -48
\r
16534 BFD0222E CBEB SW RA, 44(SP)
\r
16535 BFD02230 CBCA SW S8, 40(SP)
\r
16536 BFD02232 0FDD MOVE S8, SP
\r
16537 BFD02234 0030F89E SW A0, 48(S8)
\r
16538 151: BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
\r
16539 152: static BaseType_t xHeapHasBeenInitialised = pdFALSE;
\r
16540 153: void *pvReturn = NULL;
\r
16541 BFD02238 0018F81E SW ZERO, 24(S8)
\r
16543 155: vTaskSuspendAll();
\r
16544 BFD0223C 4EF477E8 JALS vTaskSuspendAll
\r
16545 BFD0223E 4EF4 ADDIU S7, S7, -6
\r
16546 BFD02240 0C00 NOP
\r
16548 157: /* If this is the first call to malloc then the heap will require
\r
16549 158: initialisation to setup the list of free blocks. */
\r
16550 159: if( xHeapHasBeenInitialised == pdFALSE )
\r
16551 BFD02242 8028FC5C LW V0, -32728(GP)
\r
16552 BFD02246 000640A2 BNEZC V0, 0xBFD02256
\r
16554 161: prvHeapInit();
\r
16555 BFD0224A 425077E8 JALS prvHeapInit
\r
16556 BFD0224E 0C00 NOP
\r
16557 162: xHeapHasBeenInitialised = pdTRUE;
\r
16558 BFD02250 ED01 LI V0, 1
\r
16559 BFD02252 8028F85C SW V0, -32728(GP)
\r
16562 165: /* The wanted size is increased so it can contain a BlockLink_t
\r
16563 166: structure in addition to the requested amount of bytes. */
\r
16564 167: if( xWantedSize > 0 )
\r
16565 BFD02256 0030FC5E LW V0, 48(S8)
\r
16566 BFD0225A 001640E2 BEQZC V0, 0xBFD0228A
\r
16568 169: xWantedSize += heapSTRUCT_SIZE;
\r
16569 BFD0225E BFD141A2 LUI V0, 0xBFD1
\r
16570 BFD02260 3442BFD1 LDC1 F30, 13378(S1)
\r
16571 BFD02262 9F2C3442 LHU V0, -24788(V0)
\r
16572 BFD02264 FC7E9F2C LWC1 F25, -898(T4)
\r
16573 BFD02266 0030FC7E LW V1, 48(S8)
\r
16574 BFD0226A 0526 ADDU V0, V1, V0
\r
16575 BFD0226C 0030F85E SW V0, 48(S8)
\r
16577 171: /* Ensure that blocks are always aligned to the required number of bytes. */
\r
16578 172: if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )
\r
16579 BFD02270 0030FC5E LW V0, 48(S8)
\r
16580 BFD02274 2D25 ANDI V0, V0, 0x7
\r
16581 BFD02276 000840E2 BEQZC V0, 0xBFD0228A
\r
16583 174: /* Byte alignment required. */
\r
16584 175: xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
\r
16585 BFD0227A 0030FC7E LW V1, 48(S8)
\r
16586 BFD0227C 30400030 SRL AT, S0, 6
\r
16587 BFD0227E FFF83040 ADDIU V0, ZERO, -8
\r
16588 BFD02280 4493FFF8 LW RA, 17555(T8)
\r
16589 BFD02282 4493 AND16 V0, V1
\r
16590 BFD02284 6D24 ADDIU V0, V0, 8
\r
16591 BFD02286 0030F85E SW V0, 48(S8)
\r
16595 179: if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )
\r
16596 BFD0228A 0030FC5E LW V0, 48(S8)
\r
16597 BFD0228E 008F40E2 BEQZC V0, 0xBFD023B0
\r
16598 BFD02292 0030FC5E LW V0, 48(S8)
\r
16599 BFD02296 1FF8B042 SLTIU V0, V0, 8184
\r
16600 BFD02298 40E21FF8 LB RA, 16610(T8)
\r
16601 BFD0229A 008940E2 BEQZC V0, 0xBFD023B0
\r
16603 181: /* Blocks are stored in byte order - traverse the list from the start
\r
16604 182: (smallest) block until one of adequate size is found. */
\r
16605 183: pxPreviousBlock = &xStart;
\r
16606 BFD0229E 8018305C ADDIU V0, GP, -32744
\r
16607 BFD022A2 0014F85E SW V0, 20(S8)
\r
16608 184: pxBlock = xStart.pxNextFreeBlock;
\r
16609 BFD022A6 8018FC5C LW V0, -32744(GP)
\r
16610 BFD022AA 0010F85E SW V0, 16(S8)
\r
16611 185: while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
\r
16612 BFD022AE CC0A B 0xBFD022C4
\r
16613 BFD022B0 0C00 NOP
\r
16614 BFD022C4 0010FC5E LW V0, 16(S8)
\r
16615 BFD022C8 69A1 LW V1, 4(V0)
\r
16616 BFD022CA 0030FC5E LW V0, 48(S8)
\r
16617 BFD022CE 13900043 SLTU V0, V1, V0
\r
16618 BFD022D0 40E21390 ADDI GP, S0, 16610
\r
16619 BFD022D2 000540E2 BEQZC V0, 0xBFD022E0
\r
16620 BFD022D6 0010FC5E LW V0, 16(S8)
\r
16621 BFD022DA 6920 LW V0, 0(V0)
\r
16622 BFD022DC FFE940A2 BNEZC V0, 0xBFD022B2
\r
16623 BFD022DE FC7EFFE9 LW RA, -898(T1)
\r
16625 187: pxPreviousBlock = pxBlock;
\r
16626 BFD022B2 0010FC5E LW V0, 16(S8)
\r
16627 BFD022B6 0014F85E SW V0, 20(S8)
\r
16628 188: pxBlock = pxBlock->pxNextFreeBlock;
\r
16629 BFD022BA 0010FC5E LW V0, 16(S8)
\r
16630 BFD022BE 6920 LW V0, 0(V0)
\r
16631 BFD022C0 0010F85E SW V0, 16(S8)
\r
16634 191: /* If we found the end marker then a block of adequate size was not found. */
\r
16635 192: if( pxBlock != &xEnd )
\r
16636 BFD022E0 0010FC7E LW V1, 16(S8)
\r
16637 BFD022E4 8020305C ADDIU V0, GP, -32736
\r
16638 BFD022E8 00629443 BEQ V1, V0, 0xBFD023B0
\r
16639 BFD022EA 0C000062 SLL V1, V0, 1
\r
16640 BFD022EC 0C00 NOP
\r
16642 194: /* Return the memory space - jumping over the BlockLink_t structure
\r
16643 195: at its start. */
\r
16644 196: pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
\r
16645 BFD022EE 0014FC5E LW V0, 20(S8)
\r
16646 BFD022F2 69A0 LW V1, 0(V0)
\r
16647 BFD022F4 BFD141A2 LUI V0, 0xBFD1
\r
16648 BFD022F6 3442BFD1 LDC1 F30, 13378(S1)
\r
16649 BFD022F8 9F2C3442 LHU V0, -24788(V0)
\r
16650 BFD022FA 05269F2C LWC1 F25, 1318(T4)
\r
16651 BFD022FC 0526 ADDU V0, V1, V0
\r
16652 BFD022FE 0018F85E SW V0, 24(S8)
\r
16654 198: /* This block is being returned for use so must be taken out of the
\r
16655 199: list of free blocks. */
\r
16656 200: pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
\r
16657 BFD02302 0010FC5E LW V0, 16(S8)
\r
16658 BFD02306 69A0 LW V1, 0(V0)
\r
16659 BFD02308 0014FC5E LW V0, 20(S8)
\r
16660 BFD0230C E9A0 SW V1, 0(V0)
\r
16662 202: /* If the block is larger than required it can be split into two. */
\r
16663 203: if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
\r
16664 BFD0230E 0010FC5E LW V0, 16(S8)
\r
16665 BFD02312 69A1 LW V1, 4(V0)
\r
16666 BFD02314 0030FC5E LW V0, 48(S8)
\r
16667 BFD02318 05A7 SUBU V1, V1, V0
\r
16668 BFD0231A BFD141A2 LUI V0, 0xBFD1
\r
16669 BFD0231C 3442BFD1 LDC1 F30, 13378(S1)
\r
16670 BFD0231E 9F2C3442 LHU V0, -24788(V0)
\r
16671 BFD02320 25229F2C LWC1 F25, 9506(T4)
\r
16672 BFD02322 2522 SLL V0, V0, 1
\r
16673 BFD02324 13900062 SLTU V0, V0, V1
\r
16674 BFD02326 40E21390 ADDI GP, S0, 16610
\r
16675 BFD02328 003A40E2 BEQZC V0, 0xBFD023A0
\r
16677 205: /* This block is to be split into two. Create a new block
\r
16678 206: following the number of bytes requested. The void cast is
\r
16679 207: used to prevent byte alignment warnings from the compiler. */
\r
16680 208: pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
\r
16681 BFD0232C 0010FC7E LW V1, 16(S8)
\r
16682 BFD02330 0030FC5E LW V0, 48(S8)
\r
16683 BFD02334 0526 ADDU V0, V1, V0
\r
16684 BFD02336 0020F85E SW V0, 32(S8)
\r
16686 210: /* Calculate the sizes of two blocks split from the single
\r
16688 212: pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
\r
16689 BFD0233A 0010FC5E LW V0, 16(S8)
\r
16690 BFD0233E 69A1 LW V1, 4(V0)
\r
16691 BFD02340 0030FC5E LW V0, 48(S8)
\r
16692 BFD02344 05A7 SUBU V1, V1, V0
\r
16693 BFD02346 0020FC5E LW V0, 32(S8)
\r
16694 BFD0234A E9A1 SW V1, 4(V0)
\r
16695 213: pxBlock->xBlockSize = xWantedSize;
\r
16696 BFD0234C 0010FC5E LW V0, 16(S8)
\r
16697 BFD02350 0030FC7E LW V1, 48(S8)
\r
16698 BFD02354 E9A1 SW V1, 4(V0)
\r
16700 215: /* Insert the new block into the list of free blocks. */
\r
16701 216: prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
\r
16702 BFD02356 0020FC5E LW V0, 32(S8)
\r
16703 BFD0235A 6921 LW V0, 4(V0)
\r
16704 BFD0235C 0024F85E SW V0, 36(S8)
\r
16705 BFD02360 8018305C ADDIU V0, GP, -32744
\r
16706 BFD02364 001CF85E SW V0, 28(S8)
\r
16707 BFD02368 CC06 B 0xBFD02376
\r
16708 BFD0236A 0C00 NOP
\r
16709 BFD0236C 001CFC5E LW V0, 28(S8)
\r
16710 BFD02370 6920 LW V0, 0(V0)
\r
16711 BFD02372 001CF85E SW V0, 28(S8)
\r
16712 BFD02376 001CFC5E LW V0, 28(S8)
\r
16713 BFD0237A 6920 LW V0, 0(V0)
\r
16714 BFD0237C 69A1 LW V1, 4(V0)
\r
16715 BFD0237E 0024FC5E LW V0, 36(S8)
\r
16716 BFD02382 13900043 SLTU V0, V1, V0
\r
16717 BFD02384 40A21390 ADDI GP, S0, 16546
\r
16718 BFD02386 FFF140A2 BNEZC V0, 0xBFD0236C
\r
16719 BFD02388 FC5EFFF1 LW RA, -930(S1)
\r
16720 BFD0238A 001CFC5E LW V0, 28(S8)
\r
16721 BFD0238E 69A0 LW V1, 0(V0)
\r
16722 BFD02390 0020FC5E LW V0, 32(S8)
\r
16723 BFD02394 E9A0 SW V1, 0(V0)
\r
16724 BFD02396 001CFC5E LW V0, 28(S8)
\r
16725 BFD0239A 0020FC7E LW V1, 32(S8)
\r
16726 BFD0239E E9A0 SW V1, 0(V0)
\r
16729 219: xFreeBytesRemaining -= pxBlock->xBlockSize;
\r
16730 BFD023A0 8010FC7C LW V1, -32752(GP)
\r
16731 BFD023A4 0010FC5E LW V0, 16(S8)
\r
16732 BFD023A8 6921 LW V0, 4(V0)
\r
16733 BFD023AA 0527 SUBU V0, V1, V0
\r
16734 BFD023AC 8010F85C SW V0, -32752(GP)
\r
16738 223: traceMALLOC( pvReturn, xWantedSize );
\r
16740 225: ( void ) xTaskResumeAll();
\r
16741 BFD023B0 158E77E8 JALS xTaskResumeAll
\r
16742 BFD023B2 0C00158E LBU T4, 3072(T6)
\r
16743 BFD023B4 0C00 NOP
\r
16745 227: #if( configUSE_MALLOC_FAILED_HOOK == 1 )
\r
16747 229: if( pvReturn == NULL )
\r
16748 BFD023B6 0018FC5E LW V0, 24(S8)
\r
16749 BFD023BA 000340A2 BNEZC V0, 0xBFD023C4
\r
16751 231: extern void vApplicationMallocFailedHook( void );
\r
16752 232: vApplicationMallocFailedHook();
\r
16753 BFD023BE 448077E8 JALS vApplicationMallocFailedHook
\r
16754 BFD023C0 4480 AND16 S0, S0
\r
16755 BFD023C2 0C00 NOP
\r
16760 237: return pvReturn;
\r
16761 BFD023C4 0018FC5E LW V0, 24(S8)
\r
16763 BFD023C8 0FBE MOVE SP, S8
\r
16764 BFD023CA 4BEB LW RA, 44(SP)
\r
16765 BFD023CC 4BCA LW S8, 40(SP)
\r
16766 BFD023CE 4C19 ADDIU SP, SP, 48
\r
16767 BFD023D0 459F JR16 RA
\r
16768 BFD023D2 0C00 NOP
\r
16769 239: /*-----------------------------------------------------------*/
\r
16771 241: void vPortFree( void *pv )
\r
16773 BFD05FD4 4FED ADDIU SP, SP, -40
\r
16774 BFD05FD6 CBE9 SW RA, 36(SP)
\r
16775 BFD05FD8 CBC8 SW S8, 32(SP)
\r
16776 BFD05FDA 0FDD MOVE S8, SP
\r
16777 BFD05FDC 0028F89E SW A0, 40(S8)
\r
16778 243: uint8_t *puc = ( uint8_t * ) pv;
\r
16779 BFD05FE0 0028FC5E LW V0, 40(S8)
\r
16780 BFD05FE4 0014F85E SW V0, 20(S8)
\r
16781 244: BlockLink_t *pxLink;
\r
16783 246: if( pv != NULL )
\r
16784 BFD05FE8 0028FC5E LW V0, 40(S8)
\r
16785 BFD05FEC 004240E2 BEQZC V0, 0xBFD06074
\r
16787 248: /* The memory being freed will have an BlockLink_t structure immediately
\r
16788 249: before it. */
\r
16789 250: puc -= heapSTRUCT_SIZE;
\r
16790 BFD05FF0 BFD141A2 LUI V0, 0xBFD1
\r
16791 BFD05FF2 3442BFD1 LDC1 F30, 13378(S1)
\r
16792 BFD05FF4 9F2C3442 LHU V0, -24788(V0)
\r
16793 BFD05FF6 00409F2C LWC1 F25, 64(T4)
\r
16794 BFD05FF8 11D00040 SUBU V0, ZERO, V0
\r
16795 BFD05FFA FC7E11D0 ADDI T6, S0, -898
\r
16796 BFD05FFC 0014FC7E LW V1, 20(S8)
\r
16797 BFD06000 0526 ADDU V0, V1, V0
\r
16798 BFD06002 0014F85E SW V0, 20(S8)
\r
16800 252: /* This unexpected casting is to keep some compilers from issuing
\r
16801 253: byte alignment warnings. */
\r
16802 254: pxLink = ( void * ) puc;
\r
16803 BFD06006 0014FC5E LW V0, 20(S8)
\r
16804 BFD0600A 0018F85E SW V0, 24(S8)
\r
16806 256: vTaskSuspendAll();
\r
16807 BFD0600E 4EF477E8 JALS vTaskSuspendAll
\r
16808 BFD06010 4EF4 ADDIU S7, S7, -6
\r
16809 BFD06012 0C00 NOP
\r
16811 258: /* Add this block to the list of free blocks. */
\r
16812 259: prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
\r
16813 BFD06014 0018FC5E LW V0, 24(S8)
\r
16814 BFD06018 6921 LW V0, 4(V0)
\r
16815 BFD0601A 001CF85E SW V0, 28(S8)
\r
16816 BFD0601E 8018305C ADDIU V0, GP, -32744
\r
16817 BFD06022 0010F85E SW V0, 16(S8)
\r
16818 BFD06026 CC06 B 0xBFD06034
\r
16819 BFD06028 0C00 NOP
\r
16820 BFD0602A 0010FC5E LW V0, 16(S8)
\r
16821 BFD0602E 6920 LW V0, 0(V0)
\r
16822 BFD06030 0010F85E SW V0, 16(S8)
\r
16823 BFD06034 0010FC5E LW V0, 16(S8)
\r
16824 BFD06038 6920 LW V0, 0(V0)
\r
16825 BFD0603A 69A1 LW V1, 4(V0)
\r
16826 BFD0603C 001CFC5E LW V0, 28(S8)
\r
16827 BFD06040 13900043 SLTU V0, V1, V0
\r
16828 BFD06042 40A21390 ADDI GP, S0, 16546
\r
16829 BFD06044 FFF140A2 BNEZC V0, 0xBFD0602A
\r
16830 BFD06046 FC5EFFF1 LW RA, -930(S1)
\r
16831 BFD06048 0010FC5E LW V0, 16(S8)
\r
16832 BFD0604C 69A0 LW V1, 0(V0)
\r
16833 BFD0604E 0018FC5E LW V0, 24(S8)
\r
16834 BFD06052 E9A0 SW V1, 0(V0)
\r
16835 BFD06054 0010FC5E LW V0, 16(S8)
\r
16836 BFD06058 0018FC7E LW V1, 24(S8)
\r
16837 BFD0605C E9A0 SW V1, 0(V0)
\r
16838 260: xFreeBytesRemaining += pxLink->xBlockSize;
\r
16839 BFD0605E 0018FC5E LW V0, 24(S8)
\r
16840 BFD06062 69A1 LW V1, 4(V0)
\r
16841 BFD06064 8010FC5C LW V0, -32752(GP)
\r
16842 BFD06068 0526 ADDU V0, V1, V0
\r
16843 BFD0606A 8010F85C SW V0, -32752(GP)
\r
16844 261: traceFREE( pv, pxLink->xBlockSize );
\r
16846 263: ( void ) xTaskResumeAll();
\r
16847 BFD0606E 158E77E8 JALS xTaskResumeAll
\r
16848 BFD06070 0C00158E LBU T4, 3072(T6)
\r
16849 BFD06072 0C00 NOP
\r
16852 BFD06074 0FBE MOVE SP, S8
\r
16853 BFD06076 4BE9 LW RA, 36(SP)
\r
16854 BFD06078 4BC8 LW S8, 32(SP)
\r
16855 BFD0607A 4C15 ADDIU SP, SP, 40
\r
16856 BFD0607C 459F JR16 RA
\r
16857 BFD0607E 0C00 NOP
\r
16858 266: /*-----------------------------------------------------------*/
\r
16860 268: size_t xPortGetFreeHeapSize( void )
\r
16862 BFD09E84 4FB0 ADDIU SP, SP, -8
\r
16863 BFD09E86 CBC1 SW S8, 4(SP)
\r
16864 BFD09E88 0FDD MOVE S8, SP
\r
16865 270: return xFreeBytesRemaining;
\r
16866 BFD09E8A 8010FC5C LW V0, -32752(GP)
\r
16868 BFD09E8E 0FBE MOVE SP, S8
\r
16869 BFD09E90 4BC1 LW S8, 4(SP)
\r
16870 BFD09E92 4C05 ADDIU SP, SP, 8
\r
16871 BFD09E94 459F JR16 RA
\r
16872 BFD09E96 0C00 NOP
\r
16873 272: /*-----------------------------------------------------------*/
\r
16875 274: void vPortInitialiseBlocks( void )
\r
16877 BFD09ED4 4FB0 ADDIU SP, SP, -8
\r
16878 BFD09ED6 CBC1 SW S8, 4(SP)
\r
16879 BFD09ED8 0FDD MOVE S8, SP
\r
16880 276: /* This just exists to keep the linker quiet. */
\r
16882 BFD09EDA 0FBE MOVE SP, S8
\r
16883 BFD09EDC 4BC1 LW S8, 4(SP)
\r
16884 BFD09EDE 4C05 ADDIU SP, SP, 8
\r
16885 BFD09EE0 459F JR16 RA
\r
16886 BFD09EE2 0C00 NOP
\r
16887 278: /*-----------------------------------------------------------*/
\r
16889 280: static void prvHeapInit( void )
\r
16891 BFD084A0 4FF9 ADDIU SP, SP, -16
\r
16892 BFD084A2 CBC3 SW S8, 12(SP)
\r
16893 BFD084A4 0FDD MOVE S8, SP
\r
16894 282: BlockLink_t *pxFirstFreeBlock;
\r
16895 283: uint8_t *pucAlignedHeap;
\r
16897 285: /* Ensure the heap starts on a correctly aligned boundary. */
\r
16898 286: pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
\r
16899 BFD084A6 BFD241A2 LUI V0, 0xBFD2
\r
16900 BFD084A8 3062BFD2 LDC1 F30, 12386(S2)
\r
16901 BFD084AA 8D703062 ADDIU V1, V0, -29328
\r
16902 BFD084AC 8D70 BEQZ V0, 0xBFD0858E
\r
16903 BFD084AE FFF83040 ADDIU V0, ZERO, -8
\r
16904 BFD084B0 4493FFF8 LW RA, 17555(T8)
\r
16905 BFD084B2 4493 AND16 V0, V1
\r
16906 BFD084B4 0000F85E SW V0, 0(S8)
\r
16908 288: /* xStart is used to hold a pointer to the first item in the list of free
\r
16909 289: blocks. The void cast is used to prevent compiler warnings. */
\r
16910 290: xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
\r
16911 BFD084B8 0000FC5E LW V0, 0(S8)
\r
16912 BFD084BC 8018F85C SW V0, -32744(GP)
\r
16913 291: xStart.xBlockSize = ( size_t ) 0;
\r
16914 BFD084C0 801CF81C SW ZERO, -32740(GP)
\r
16916 293: /* xEnd is used to mark the end of the list of free blocks. */
\r
16917 294: xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
\r
16918 BFD084C4 1FF83040 ADDIU V0, ZERO, 8184
\r
16919 BFD084C6 F85C1FF8 LB RA, -1956(T8)
\r
16920 BFD084C8 8024F85C SW V0, -32732(GP)
\r
16921 295: xEnd.pxNextFreeBlock = NULL;
\r
16922 BFD084CC 8020F81C SW ZERO, -32736(GP)
\r
16924 297: /* To start with there is a single free block that is sized to take up the
\r
16925 298: entire heap space. */
\r
16926 299: pxFirstFreeBlock = ( void * ) pucAlignedHeap;
\r
16927 BFD084D0 0000FC5E LW V0, 0(S8)
\r
16928 BFD084D4 0004F85E SW V0, 4(S8)
\r
16929 300: pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
\r
16930 BFD084D8 0004FC5E LW V0, 4(S8)
\r
16931 BFD084DC 1FF83060 ADDIU V1, ZERO, 8184
\r
16932 BFD084DE E9A11FF8 LB RA, -5727(T8)
\r
16933 BFD084E0 E9A1 SW V1, 4(V0)
\r
16934 301: pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
\r
16935 BFD084E2 0004FC5E LW V0, 4(S8)
\r
16936 BFD084E4 307C0004 MTLO A0, 0
\r
16937 BFD084E6 8020307C ADDIU V1, GP, -32736
\r
16938 BFD084EA E9A0 SW V1, 0(V0)
\r
16940 BFD084EC 0FBE MOVE SP, S8
\r
16941 BFD084EE 4BC3 LW S8, 12(SP)
\r
16942 BFD084F0 4C09 ADDIU SP, SP, 16
\r
16943 BFD084F2 459F JR16 RA
\r
16944 BFD084F4 0C00 NOP
\r
16945 303: /*-----------------------------------------------------------*/
\r
16946 --- c:/e/dev/freertos/workingcopy/freertos/source/list.c ----------------------------------------------
\r
16948 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
16949 3: All rights reserved
\r
16951 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
16953 7: This file is part of the FreeRTOS distribution.
\r
16955 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
16956 10: the terms of the GNU General Public License (version 2) as published by the
\r
16957 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
16959 13: ***************************************************************************
\r
16960 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
16961 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16962 16: >>! obliged to provide the source code for proprietary components !<<
\r
16963 17: >>! outside of the FreeRTOS kernel. !<<
\r
16964 18: ***************************************************************************
\r
16966 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
16967 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
16968 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
16969 23: link: http://www.freertos.org/a00114.html
\r
16971 25: ***************************************************************************
\r
16973 27: * FreeRTOS provides completely free yet professionally developed, *
\r
16974 28: * robust, strictly quality controlled, supported, and cross *
\r
16975 29: * platform software that is more than just the market leader, it *
\r
16976 30: * is the industry's de facto standard. *
\r
16978 32: * Help yourself get started quickly while simultaneously helping *
\r
16979 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
16980 34: * tutorial book, reference manual, or both: *
\r
16981 35: * http://www.FreeRTOS.org/Documentation *
\r
16983 37: ***************************************************************************
\r
16985 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
16986 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
16987 41: defined configASSERT()?
\r
16989 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
16990 44: embedded software for free we request you assist our global community by
\r
16991 45: participating in the support forum.
\r
16993 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
16994 48: be as productive as possible as early as possible. Now you can receive
\r
16995 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
16996 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
16998 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
16999 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
17000 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
17002 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
17003 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
17005 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
17006 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
17007 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
17009 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
17010 64: engineered and independently SIL3 certified version for use in safety and
\r
17011 65: mission critical applications that require provable dependability.
\r
17013 67: 1 tab == 4 spaces!
\r
17017 71: #include <stdlib.h>
\r
17018 72: #include "FreeRTOS.h"
\r
17019 73: #include "list.h"
\r
17021 75: /*-----------------------------------------------------------
\r
17022 76: * PUBLIC LIST API documented in list.h
\r
17023 77: *----------------------------------------------------------*/
\r
17025 79: void vListInitialise( List_t * const pxList )
\r
17027 BFD08AE0 4FB0 ADDIU SP, SP, -8
\r
17028 BFD08AE2 CBC1 SW S8, 4(SP)
\r
17029 BFD08AE4 0FDD MOVE S8, SP
\r
17030 BFD08AE6 0008F89E SW A0, 8(S8)
\r
17031 81: /* The list structure contains a list item which is used to mark the
\r
17032 82: end of the list. To initialise the list the list end is inserted
\r
17033 83: as the only list entry. */
\r
17034 84: pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
\r
17035 BFD08AEA 0008FC5E LW V0, 8(S8)
\r
17036 BFD08AEE 6D24 ADDIU V0, V0, 8
\r
17037 BFD08AF0 0C62 MOVE V1, V0
\r
17038 BFD08AF2 0008FC5E LW V0, 8(S8)
\r
17039 BFD08AF6 E9A1 SW V1, 4(V0)
\r
17041 86: /* The list end value is the highest possible value in the list to
\r
17042 87: ensure it remains at the end of the list. */
\r
17043 88: pxList->xListEnd.xItemValue = portMAX_DELAY;
\r
17044 BFD08AF8 0008FC5E LW V0, 8(S8)
\r
17045 BFD08AFC EDFF LI V1, -1
\r
17046 BFD08AFE E9A2 SW V1, 8(V0)
\r
17048 90: /* The list end next and previous pointers point to itself so we know
\r
17049 91: when the list is empty. */
\r
17050 92: pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
\r
17051 BFD08B00 0008FC5E LW V0, 8(S8)
\r
17052 BFD08B04 6D24 ADDIU V0, V0, 8
\r
17053 BFD08B06 0C62 MOVE V1, V0
\r
17054 BFD08B08 0008FC5E LW V0, 8(S8)
\r
17055 BFD08B0C E9A3 SW V1, 12(V0)
\r
17056 93: pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
\r
17057 BFD08B0E 0008FC5E LW V0, 8(S8)
\r
17058 BFD08B12 6D24 ADDIU V0, V0, 8
\r
17059 BFD08B14 0C62 MOVE V1, V0
\r
17060 BFD08B16 0008FC5E LW V0, 8(S8)
\r
17061 BFD08B1A E9A4 SW V1, 16(V0)
\r
17063 95: pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
\r
17064 BFD08B1C 0008FC5E LW V0, 8(S8)
\r
17065 BFD08B20 E820 SW S0, 0(V0)
\r
17067 97: /* Write known values into the list if
\r
17068 98: configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
\r
17069 99: listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
\r
17070 100: listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
\r
17072 BFD08B22 0FBE MOVE SP, S8
\r
17073 BFD08B24 4BC1 LW S8, 4(SP)
\r
17074 BFD08B26 4C05 ADDIU SP, SP, 8
\r
17075 BFD08B28 459F JR16 RA
\r
17076 BFD08B2A 0C00 NOP
\r
17077 102: /*-----------------------------------------------------------*/
\r
17079 104: void vListInitialiseItem( ListItem_t * const pxItem )
\r
17081 BFD09DCC 4FB0 ADDIU SP, SP, -8
\r
17082 BFD09DCE CBC1 SW S8, 4(SP)
\r
17083 BFD09DD0 0FDD MOVE S8, SP
\r
17084 BFD09DD2 0008F89E SW A0, 8(S8)
\r
17085 106: /* Make sure the list item is not recorded as being on a list. */
\r
17086 107: pxItem->pvContainer = NULL;
\r
17087 BFD09DD6 0008FC5E LW V0, 8(S8)
\r
17088 BFD09DDA E824 SW S0, 16(V0)
\r
17090 109: /* Write known values into the list item if
\r
17091 110: configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
\r
17092 111: listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
\r
17093 112: listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
\r
17095 BFD09DDC 0FBE MOVE SP, S8
\r
17096 BFD09DDE 4BC1 LW S8, 4(SP)
\r
17097 BFD09DE0 4C05 ADDIU SP, SP, 8
\r
17098 BFD09DE2 459F JR16 RA
\r
17099 BFD09DE4 0C00 NOP
\r
17100 114: /*-----------------------------------------------------------*/
\r
17102 116: void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
\r
17104 BFD07C94 4FF9 ADDIU SP, SP, -16
\r
17105 BFD07C96 CBC3 SW S8, 12(SP)
\r
17106 BFD07C98 0FDD MOVE S8, SP
\r
17107 BFD07C9A 0010F89E SW A0, 16(S8)
\r
17108 BFD07C9E 0014F8BE SW A1, 20(S8)
\r
17109 118: ListItem_t * const pxIndex = pxList->pxIndex;
\r
17110 BFD07CA2 0010FC5E LW V0, 16(S8)
\r
17111 BFD07CA6 6921 LW V0, 4(V0)
\r
17112 BFD07CA8 0000F85E SW V0, 0(S8)
\r
17114 120: /* Only effective when configASSERT() is also defined, these tests may catch
\r
17115 121: the list data structures being overwritten in memory. They will not catch
\r
17116 122: data errors caused by incorrect configuration or use of FreeRTOS. */
\r
17117 123: listTEST_LIST_INTEGRITY( pxList );
\r
17118 124: listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
\r
17120 126: /* Insert a new list item into pxList, but rather than sort the list,
\r
17121 127: makes the new list item the last item to be removed by a call to
\r
17122 128: listGET_OWNER_OF_NEXT_ENTRY(). */
\r
17123 129: pxNewListItem->pxNext = pxIndex;
\r
17124 BFD07CAC 0014FC5E LW V0, 20(S8)
\r
17125 BFD07CB0 0000FC7E LW V1, 0(S8)
\r
17126 BFD07CB4 E9A1 SW V1, 4(V0)
\r
17127 130: pxNewListItem->pxPrevious = pxIndex->pxPrevious;
\r
17128 BFD07CB6 0000FC5E LW V0, 0(S8)
\r
17129 BFD07CBA 69A2 LW V1, 8(V0)
\r
17130 BFD07CBC 0014FC5E LW V0, 20(S8)
\r
17131 BFD07CC0 E9A2 SW V1, 8(V0)
\r
17133 132: /* Only used during decision coverage testing. */
\r
17134 133: mtCOVERAGE_TEST_DELAY();
\r
17136 135: pxIndex->pxPrevious->pxNext = pxNewListItem;
\r
17137 BFD07CC2 0000FC5E LW V0, 0(S8)
\r
17138 BFD07CC6 6922 LW V0, 8(V0)
\r
17139 BFD07CC8 0014FC7E LW V1, 20(S8)
\r
17140 BFD07CCC E9A1 SW V1, 4(V0)
\r
17141 136: pxIndex->pxPrevious = pxNewListItem;
\r
17142 BFD07CCE 0000FC5E LW V0, 0(S8)
\r
17143 BFD07CD2 0014FC7E LW V1, 20(S8)
\r
17144 BFD07CD6 E9A2 SW V1, 8(V0)
\r
17146 138: /* Remember which list the item is in. */
\r
17147 139: pxNewListItem->pvContainer = ( void * ) pxList;
\r
17148 BFD07CD8 0014FC5E LW V0, 20(S8)
\r
17149 BFD07CDC 0010FC7E LW V1, 16(S8)
\r
17150 BFD07CE0 E9A4 SW V1, 16(V0)
\r
17152 141: ( pxList->uxNumberOfItems )++;
\r
17153 BFD07CE2 0010FC5E LW V0, 16(S8)
\r
17154 BFD07CE6 6920 LW V0, 0(V0)
\r
17155 BFD07CE8 6DA0 ADDIU V1, V0, 1
\r
17156 BFD07CEA 0010FC5E LW V0, 16(S8)
\r
17157 BFD07CEE E9A0 SW V1, 0(V0)
\r
17159 BFD07CF0 0FBE MOVE SP, S8
\r
17160 BFD07CF2 4BC3 LW S8, 12(SP)
\r
17161 BFD07CF4 4C09 ADDIU SP, SP, 16
\r
17162 BFD07CF6 459F JR16 RA
\r
17163 BFD07CF8 0C00 NOP
\r
17164 143: /*-----------------------------------------------------------*/
\r
17166 145: void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
\r
17168 BFD06080 4FF9 ADDIU SP, SP, -16
\r
17169 BFD06082 CBC3 SW S8, 12(SP)
\r
17170 BFD06084 0FDD MOVE S8, SP
\r
17171 BFD06086 0010F89E SW A0, 16(S8)
\r
17172 BFD0608A 0014F8BE SW A1, 20(S8)
\r
17173 147: ListItem_t *pxIterator;
\r
17174 148: const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
\r
17175 BFD0608E 0014FC5E LW V0, 20(S8)
\r
17176 BFD06092 6920 LW V0, 0(V0)
\r
17177 BFD06094 0004F85E SW V0, 4(S8)
\r
17179 150: /* Only effective when configASSERT() is also defined, these tests may catch
\r
17180 151: the list data structures being overwritten in memory. They will not catch
\r
17181 152: data errors caused by incorrect configuration or use of FreeRTOS. */
\r
17182 153: listTEST_LIST_INTEGRITY( pxList );
\r
17183 154: listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
\r
17185 156: /* Insert the new list item into the list, sorted in xItemValue order.
\r
17187 158: If the list already contains a list item with the same item value then the
\r
17188 159: new list item should be placed after it. This ensures that TCB's which are
\r
17189 160: stored in ready lists (all of which have the same xItemValue value) get a
\r
17190 161: share of the CPU. However, if the xItemValue is the same as the back marker
\r
17191 162: the iteration loop below will not end. Therefore the value is checked
\r
17192 163: first, and the algorithm slightly modified if necessary. */
\r
17193 164: if( xValueOfInsertion == portMAX_DELAY )
\r
17194 BFD06098 0004FC7E LW V1, 4(S8)
\r
17195 BFD0609C ED7F LI V0, -1
\r
17196 BFD0609E 0008B443 BNE V1, V0, 0xBFD060B2
\r
17197 BFD060A0 0C000008 SLL ZERO, T0, 1
\r
17198 BFD060A2 0C00 NOP
\r
17200 166: pxIterator = pxList->xListEnd.pxPrevious;
\r
17201 BFD060A4 0010FC5E LW V0, 16(S8)
\r
17202 BFD060A8 6924 LW V0, 16(V0)
\r
17203 BFD060AA 0000F85E SW V0, 0(S8)
\r
17204 BFD060AE CC17 B 0xBFD060DE
\r
17205 BFD060B0 0C00 NOP
\r
17209 170: /* *** NOTE ***********************************************************
\r
17210 171: If you find your application is crashing here then likely causes are
\r
17211 172: listed below. In addition see http://www.freertos.org/FAQHelp.html for
\r
17212 173: more tips, and ensure configASSERT() is defined!
\r
17213 174: http://www.freertos.org/a00110.html#configASSERT
\r
17215 176: 1) Stack overflow -
\r
17216 177: see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
\r
17217 178: 2) Incorrect interrupt priority assignment, especially on Cortex-M
\r
17218 179: parts where numerically high priority values denote low actual
\r
17219 180: interrupt priorities, which can seem counter intuitive. See
\r
17220 181: http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
\r
17221 182: of configMAX_SYSCALL_INTERRUPT_PRIORITY on
\r
17222 183: http://www.freertos.org/a00110.html
\r
17223 184: 3) Calling an API function from within a critical section or when
\r
17224 185: the scheduler is suspended, or calling an API function that does
\r
17225 186: not end in "FromISR" from an interrupt.
\r
17226 187: 4) Using a queue or semaphore before it has been initialised or
\r
17227 188: before the scheduler has been started (are interrupts firing
\r
17228 189: before vTaskStartScheduler() has been called?).
\r
17229 190: **********************************************************************/
\r
17231 192: for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
\r
17232 BFD060B2 0010FC5E LW V0, 16(S8)
\r
17233 BFD060B6 6D24 ADDIU V0, V0, 8
\r
17234 BFD060B8 0000F85E SW V0, 0(S8)
\r
17235 BFD060BC CC06 B 0xBFD060CA
\r
17236 BFD060BE 0C00 NOP
\r
17237 BFD060C0 0000FC5E LW V0, 0(S8)
\r
17238 BFD060C4 6921 LW V0, 4(V0)
\r
17239 BFD060C6 0000F85E SW V0, 0(S8)
\r
17240 BFD060CA 0000FC5E LW V0, 0(S8)
\r
17241 BFD060CE 6921 LW V0, 4(V0)
\r
17242 BFD060D0 69A0 LW V1, 0(V0)
\r
17243 BFD060D2 0004FC5E LW V0, 4(S8)
\r
17244 BFD060D6 13900062 SLTU V0, V0, V1
\r
17245 BFD060D8 40E21390 ADDI GP, S0, 16610
\r
17246 BFD060DA FFF140E2 BEQZC V0, 0xBFD060C0
\r
17247 BFD060DC FC5EFFF1 LW RA, -930(S1)
\r
17249 194: /* There is nothing to do here, just iterating to the wanted
\r
17250 195: insertion position. */
\r
17254 199: pxNewListItem->pxNext = pxIterator->pxNext;
\r
17255 BFD060DE 0000FC5E LW V0, 0(S8)
\r
17256 BFD060E2 69A1 LW V1, 4(V0)
\r
17257 BFD060E4 0014FC5E LW V0, 20(S8)
\r
17258 BFD060E8 E9A1 SW V1, 4(V0)
\r
17259 200: pxNewListItem->pxNext->pxPrevious = pxNewListItem;
\r
17260 BFD060EA 0014FC5E LW V0, 20(S8)
\r
17261 BFD060EE 6921 LW V0, 4(V0)
\r
17262 BFD060F0 0014FC7E LW V1, 20(S8)
\r
17263 BFD060F4 E9A2 SW V1, 8(V0)
\r
17264 201: pxNewListItem->pxPrevious = pxIterator;
\r
17265 BFD060F6 0014FC5E LW V0, 20(S8)
\r
17266 BFD060FA 0000FC7E LW V1, 0(S8)
\r
17267 BFD060FE E9A2 SW V1, 8(V0)
\r
17268 202: pxIterator->pxNext = pxNewListItem;
\r
17269 BFD06100 0000FC5E LW V0, 0(S8)
\r
17270 BFD06104 0014FC7E LW V1, 20(S8)
\r
17271 BFD06108 E9A1 SW V1, 4(V0)
\r
17273 204: /* Remember which list the item is in. This allows fast removal of the
\r
17274 205: item later. */
\r
17275 206: pxNewListItem->pvContainer = ( void * ) pxList;
\r
17276 BFD0610A 0014FC5E LW V0, 20(S8)
\r
17277 BFD0610E 0010FC7E LW V1, 16(S8)
\r
17278 BFD06112 E9A4 SW V1, 16(V0)
\r
17280 208: ( pxList->uxNumberOfItems )++;
\r
17281 BFD06114 0010FC5E LW V0, 16(S8)
\r
17282 BFD06118 6920 LW V0, 0(V0)
\r
17283 BFD0611A 6DA0 ADDIU V1, V0, 1
\r
17284 BFD0611C 0010FC5E LW V0, 16(S8)
\r
17285 BFD06120 E9A0 SW V1, 0(V0)
\r
17287 BFD06122 0FBE MOVE SP, S8
\r
17288 BFD06124 4BC3 LW S8, 12(SP)
\r
17289 BFD06126 4C09 ADDIU SP, SP, 16
\r
17290 BFD06128 459F JR16 RA
\r
17291 BFD0612A 0C00 NOP
\r
17292 210: /*-----------------------------------------------------------*/
\r
17294 212: UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
\r
17296 BFD00190 4FF9 ADDIU SP, SP, -16
\r
17297 BFD00192 CBC3 SW S8, 12(SP)
\r
17298 BFD00194 0FDD MOVE S8, SP
\r
17299 BFD00196 0010F89E SW A0, 16(S8)
\r
17300 214: /* The list item knows which list it is in. Obtain the list from the list
\r
17302 216: List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
\r
17303 BFD0019A 0010FC5E LW V0, 16(S8)
\r
17304 BFD0019E 6924 LW V0, 16(V0)
\r
17305 BFD001A0 0000F85E SW V0, 0(S8)
\r
17307 218: pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
\r
17308 BFD001A4 0010FC5E LW V0, 16(S8)
\r
17309 BFD001A8 6921 LW V0, 4(V0)
\r
17310 BFD001AA 0010FC7E LW V1, 16(S8)
\r
17311 BFD001AE 69B2 LW V1, 8(V1)
\r
17312 BFD001B0 E9A2 SW V1, 8(V0)
\r
17313 219: pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
\r
17314 BFD001B2 0010FC5E LW V0, 16(S8)
\r
17315 BFD001B6 6922 LW V0, 8(V0)
\r
17316 BFD001B8 0010FC7E LW V1, 16(S8)
\r
17317 BFD001BC 69B1 LW V1, 4(V1)
\r
17318 BFD001BE E9A1 SW V1, 4(V0)
\r
17320 221: /* Only used during decision coverage testing. */
\r
17321 222: mtCOVERAGE_TEST_DELAY();
\r
17323 224: /* Make sure the index is left pointing to a valid item. */
\r
17324 225: if( pxList->pxIndex == pxItemToRemove )
\r
17325 BFD001C0 0000FC5E LW V0, 0(S8)
\r
17326 BFD001C4 69A1 LW V1, 4(V0)
\r
17327 BFD001C6 0010FC5E LW V0, 16(S8)
\r
17328 BFD001CA 0007B443 BNE V1, V0, 0xBFD001DC
\r
17329 BFD001CC 0C000007 SLL ZERO, A3, 1
\r
17330 BFD001CE 0C00 NOP
\r
17332 227: pxList->pxIndex = pxItemToRemove->pxPrevious;
\r
17333 BFD001D0 0010FC5E LW V0, 16(S8)
\r
17334 BFD001D4 69A2 LW V1, 8(V0)
\r
17335 BFD001D6 0000FC5E LW V0, 0(S8)
\r
17336 BFD001DA E9A1 SW V1, 4(V0)
\r
17340 231: mtCOVERAGE_TEST_MARKER();
\r
17343 234: pxItemToRemove->pvContainer = NULL;
\r
17344 BFD001DC 0010FC5E LW V0, 16(S8)
\r
17345 BFD001E0 E824 SW S0, 16(V0)
\r
17346 235: ( pxList->uxNumberOfItems )--;
\r
17347 BFD001E2 0000FC5E LW V0, 0(S8)
\r
17348 BFD001E6 6920 LW V0, 0(V0)
\r
17349 BFD001E8 6DAE ADDIU V1, V0, -1
\r
17350 BFD001EA 0000FC5E LW V0, 0(S8)
\r
17351 BFD001EE E9A0 SW V1, 0(V0)
\r
17353 237: return pxList->uxNumberOfItems;
\r
17354 BFD001F0 0000FC5E LW V0, 0(S8)
\r
17355 BFD001F4 6920 LW V0, 0(V0)
\r
17357 BFD001F6 0FBE MOVE SP, S8
\r
17358 BFD001F8 4BC3 LW S8, 12(SP)
\r
17359 BFD001FA 4C09 ADDIU SP, SP, 16
\r
17360 BFD001FC 459F JR16 RA
\r
17361 BFD001FE 0C00 NOP
\r
17362 239: /*-----------------------------------------------------------*/
\r
17364 --- c:/e/dev/freertos/workingcopy/freertos/source/event_groups.c --------------------------------------
\r
17366 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
17367 3: All rights reserved
\r
17369 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
17371 7: This file is part of the FreeRTOS distribution.
\r
17373 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
17374 10: the terms of the GNU General Public License (version 2) as published by the
\r
17375 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
17377 13: ***************************************************************************
\r
17378 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
17379 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
17380 16: >>! obliged to provide the source code for proprietary components !<<
\r
17381 17: >>! outside of the FreeRTOS kernel. !<<
\r
17382 18: ***************************************************************************
\r
17384 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
17385 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
17386 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
17387 23: link: http://www.freertos.org/a00114.html
\r
17389 25: ***************************************************************************
\r
17391 27: * FreeRTOS provides completely free yet professionally developed, *
\r
17392 28: * robust, strictly quality controlled, supported, and cross *
\r
17393 29: * platform software that is more than just the market leader, it *
\r
17394 30: * is the industry's de facto standard. *
\r
17396 32: * Help yourself get started quickly while simultaneously helping *
\r
17397 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
17398 34: * tutorial book, reference manual, or both: *
\r
17399 35: * http://www.FreeRTOS.org/Documentation *
\r
17401 37: ***************************************************************************
\r
17403 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
17404 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
17405 41: defined configASSERT()?
\r
17407 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
17408 44: embedded software for free we request you assist our global community by
\r
17409 45: participating in the support forum.
\r
17411 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
17412 48: be as productive as possible as early as possible. Now you can receive
\r
17413 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
17414 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
17416 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
17417 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
17418 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
17420 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
17421 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
17423 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
17424 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
17425 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
17427 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
17428 64: engineered and independently SIL3 certified version for use in safety and
\r
17429 65: mission critical applications that require provable dependability.
\r
17431 67: 1 tab == 4 spaces!
\r
17434 70: /* Standard includes. */
\r
17435 71: #include <stdlib.h>
\r
17437 73: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
\r
17438 74: all the API functions to use the MPU wrappers. That should only be done when
\r
17439 75: task.h is included from an application file. */
\r
17440 76: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
\r
17442 78: /* FreeRTOS includes. */
\r
17443 79: #include "FreeRTOS.h"
\r
17444 80: #include "task.h"
\r
17445 81: #include "timers.h"
\r
17446 82: #include "event_groups.h"
\r
17448 84: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the
\r
17449 85: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
\r
17450 86: header files above, but not in this file, in order to generate the correct
\r
17451 87: privileged Vs unprivileged linkage and placement. */
\r
17452 88: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
\r
17454 90: #if ( INCLUDE_xEventGroupSetBitsFromISR == 1 ) && ( configUSE_TIMERS == 0 )
\r
17455 91: #error configUSE_TIMERS must be set to 1 to make the xEventGroupSetBitFromISR() function available.
\r
17458 94: #if ( INCLUDE_xEventGroupSetBitsFromISR == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 0 )
\r
17459 95: #error INCLUDE_xTimerPendFunctionCall must also be set to one to make the xEventGroupSetBitFromISR() function available.
\r
17462 98: /* The following bit fields convey control information in a task's event list
\r
17463 99: item value. It is important they don't clash with the
\r
17464 100: taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
\r
17465 101: #if configUSE_16_BIT_TICKS == 1
\r
17466 102: #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U
\r
17467 103: #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U
\r
17468 104: #define eventWAIT_FOR_ALL_BITS 0x0400U
\r
17469 105: #define eventEVENT_BITS_CONTROL_BYTES 0xff00U
\r
17471 107: #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL
\r
17472 108: #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL
\r
17473 109: #define eventWAIT_FOR_ALL_BITS 0x04000000UL
\r
17474 110: #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL
\r
17477 113: typedef struct xEventGroupDefinition
\r
17479 115: EventBits_t uxEventBits;
\r
17480 116: List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
\r
17482 118: #if( configUSE_TRACE_FACILITY == 1 )
\r
17483 119: UBaseType_t uxEventGroupNumber;
\r
17486 122: } EventGroup_t;
\r
17488 124: /*-----------------------------------------------------------*/
\r
17491 127: * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
\r
17492 128: * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is
\r
17493 129: * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
\r
17494 130: * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the
\r
17495 131: * wait condition is met if any of the bits set in uxBitsToWait for are also set
\r
17496 132: * in uxCurrentEventBits.
\r
17498 134: static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits );
\r
17500 136: /*-----------------------------------------------------------*/
\r
17502 138: EventGroupHandle_t xEventGroupCreate( void )
\r
17504 BFD09320 4FF1 ADDIU SP, SP, -32
\r
17505 BFD09322 CBE7 SW RA, 28(SP)
\r
17506 BFD09324 CBC6 SW S8, 24(SP)
\r
17507 BFD09326 0FDD MOVE S8, SP
\r
17508 140: EventGroup_t *pxEventBits;
\r
17510 142: pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
\r
17511 BFD09328 EE18 LI A0, 24
\r
17512 BFD0932A 111677E8 JALS pvPortMalloc
\r
17513 BFD0932C 0C001116 ADDI T0, S6, 3072
\r
17514 BFD0932E 0C00 NOP
\r
17515 BFD09330 0010F85E SW V0, 16(S8)
\r
17516 143: if( pxEventBits != NULL )
\r
17517 BFD09334 0010FC5E LW V0, 16(S8)
\r
17518 BFD09338 000A40E2 BEQZC V0, 0xBFD09350
\r
17520 145: pxEventBits->uxEventBits = 0;
\r
17521 BFD0933C 0010FC5E LW V0, 16(S8)
\r
17522 BFD09340 E820 SW S0, 0(V0)
\r
17523 146: vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
\r
17524 BFD09342 0010FC5E LW V0, 16(S8)
\r
17525 BFD09346 6D22 ADDIU V0, V0, 4
\r
17526 BFD09348 0C82 MOVE A0, V0
\r
17527 BFD0934A 457077E8 JALS vListInitialise
\r
17528 BFD0934C 4570 SWM16 0x3, 0(SP)
\r
17529 BFD0934E 0C00 NOP
\r
17530 147: traceEVENT_GROUP_CREATE( pxEventBits );
\r
17534 151: traceEVENT_GROUP_CREATE_FAILED();
\r
17537 154: return ( EventGroupHandle_t ) pxEventBits;
\r
17538 BFD09350 0010FC5E LW V0, 16(S8)
\r
17540 BFD09354 0FBE MOVE SP, S8
\r
17541 BFD09356 4BE7 LW RA, 28(SP)
\r
17542 BFD09358 4BC6 LW S8, 24(SP)
\r
17543 BFD0935A 4C11 ADDIU SP, SP, 32
\r
17544 BFD0935C 459F JR16 RA
\r
17545 BFD0935E 0C00 NOP
\r
17546 156: /*-----------------------------------------------------------*/
\r
17548 158: EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
\r
17550 BFD01B0C 4FE9 ADDIU SP, SP, -48
\r
17551 BFD01B0E CBEB SW RA, 44(SP)
\r
17552 BFD01B10 CBCA SW S8, 40(SP)
\r
17553 BFD01B12 0FDD MOVE S8, SP
\r
17554 BFD01B14 0030F89E SW A0, 48(S8)
\r
17555 BFD01B18 0034F8BE SW A1, 52(S8)
\r
17556 BFD01B1C 0038F8DE SW A2, 56(S8)
\r
17557 BFD01B20 003CF8FE SW A3, 60(S8)
\r
17558 160: EventBits_t uxOriginalBitValue, uxReturn;
\r
17559 161: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
\r
17560 BFD01B24 0030FC5E LW V0, 48(S8)
\r
17561 BFD01B28 0014F85E SW V0, 20(S8)
\r
17562 162: BaseType_t xAlreadyYielded;
\r
17563 163: BaseType_t xTimeoutOccurred = pdFALSE;
\r
17564 BFD01B2C 0018F81E SW ZERO, 24(S8)
\r
17566 165: configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
\r
17567 BFD01B30 0038FC7E LW V1, 56(S8)
\r
17568 BFD01B34 FF0041A2 LUI V0, 0xFF00
\r
17569 BFD01B36 4493FF00 LW T8, 17555(ZERO)
\r
17570 BFD01B38 4493 AND16 V0, V1
\r
17571 BFD01B3A 000940E2 BEQZC V0, 0xBFD01B50
\r
17572 BFD01B3E BFD141A2 LUI V0, 0xBFD1
\r
17573 BFD01B40 3082BFD1 LDC1 F30, 12418(S1)
\r
17574 BFD01B42 9C0C3082 ADDIU A0, V0, -25588
\r
17575 BFD01B44 30A09C0C LWC1 F0, 12448(T4)
\r
17576 BFD01B46 00A530A0 ADDIU A1, ZERO, 165
\r
17577 BFD01B4A 4B7E77E8 JALS vAssertCalled
\r
17578 BFD01B4C 4B7E LW K1, 120(SP)
\r
17579 BFD01B4E 0C00 NOP
\r
17580 166: configASSERT( uxBitsToWaitFor != 0 );
\r
17581 BFD01B50 0038FC5E LW V0, 56(S8)
\r
17582 BFD01B54 000940A2 BNEZC V0, 0xBFD01B6A
\r
17583 BFD01B58 BFD141A2 LUI V0, 0xBFD1
\r
17584 BFD01B5A 3082BFD1 LDC1 F30, 12418(S1)
\r
17585 BFD01B5C 9C0C3082 ADDIU A0, V0, -25588
\r
17586 BFD01B5E 30A09C0C LWC1 F0, 12448(T4)
\r
17587 BFD01B60 00A630A0 ADDIU A1, ZERO, 166
\r
17588 BFD01B64 4B7E77E8 JALS vAssertCalled
\r
17589 BFD01B66 4B7E LW K1, 120(SP)
\r
17590 BFD01B68 0C00 NOP
\r
17591 167: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
\r
17593 169: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
\r
17594 BFD01B6A 4A8E77E8 JALS xTaskGetSchedulerState
\r
17595 BFD01B6C 4A8E LW S4, 56(SP)
\r
17596 BFD01B6E 0C00 NOP
\r
17597 BFD01B70 000440A2 BNEZC V0, 0xBFD01B7C
\r
17598 BFD01B74 003CFC5E LW V0, 60(S8)
\r
17599 BFD01B78 000340A2 BNEZC V0, 0xBFD01B82
\r
17600 BFD01B7C ED01 LI V0, 1
\r
17601 BFD01B7E CC02 B 0xBFD01B84
\r
17602 BFD01B80 0C00 NOP
\r
17603 BFD01B82 0C40 MOVE V0, ZERO
\r
17604 BFD01B84 000940A2 BNEZC V0, 0xBFD01B9A
\r
17605 BFD01B88 BFD141A2 LUI V0, 0xBFD1
\r
17606 BFD01B8A 3082BFD1 LDC1 F30, 12418(S1)
\r
17607 BFD01B8C 9C0C3082 ADDIU A0, V0, -25588
\r
17608 BFD01B8E 30A09C0C LWC1 F0, 12448(T4)
\r
17609 BFD01B90 00A930A0 ADDIU A1, ZERO, 169
\r
17610 BFD01B94 4B7E77E8 JALS vAssertCalled
\r
17611 BFD01B96 4B7E LW K1, 120(SP)
\r
17612 BFD01B98 0C00 NOP
\r
17616 173: vTaskSuspendAll();
\r
17617 BFD01B9A 4EF477E8 JALS vTaskSuspendAll
\r
17618 BFD01B9C 4EF4 ADDIU S7, S7, -6
\r
17619 BFD01B9E 0C00 NOP
\r
17621 175: uxOriginalBitValue = pxEventBits->uxEventBits;
\r
17622 BFD01BA0 0014FC5E LW V0, 20(S8)
\r
17623 BFD01BA4 6920 LW V0, 0(V0)
\r
17624 BFD01BA6 001CF85E SW V0, 28(S8)
\r
17626 177: ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
\r
17627 BFD01BAA 0030FC9E LW A0, 48(S8)
\r
17628 BFD01BAE 0034FCBE LW A1, 52(S8)
\r
17629 BFD01BB2 12B477E8 JALS xEventGroupSetBits
\r
17630 BFD01BB4 0C0012B4 ADDI S5, S4, 3072
\r
17631 BFD01BB6 0C00 NOP
\r
17633 179: if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
\r
17634 BFD01BB8 001CFC7E LW V1, 28(S8)
\r
17635 BFD01BBC 0034FC5E LW V0, 52(S8)
\r
17636 BFD01BC0 44DA OR16 V1, V0
\r
17637 BFD01BC2 0038FC5E LW V0, 56(S8)
\r
17638 BFD01BC6 449A AND16 V1, V0
\r
17639 BFD01BC8 0038FC5E LW V0, 56(S8)
\r
17640 BFD01BCC 0016B443 BNE V1, V0, 0xBFD01BFC
\r
17641 BFD01BCE 0C000016 SLL ZERO, S6, 1
\r
17642 BFD01BD0 0C00 NOP
\r
17644 181: /* All the rendezvous bits are now set - no need to block. */
\r
17645 182: uxReturn = ( uxOriginalBitValue | uxBitsToSet );
\r
17646 BFD01BD2 001CFC7E LW V1, 28(S8)
\r
17647 BFD01BD6 0034FC5E LW V0, 52(S8)
\r
17648 BFD01BDA 44D3 OR16 V0, V1
\r
17649 BFD01BDC 0010F85E SW V0, 16(S8)
\r
17651 184: /* Rendezvous always clear the bits. They will have been cleared
\r
17652 185: already unless this is the only task in the rendezvous. */
\r
17653 186: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
\r
17654 BFD01BE0 0014FC5E LW V0, 20(S8)
\r
17655 BFD01BE4 69A0 LW V1, 0(V0)
\r
17656 BFD01BE6 0038FC5E LW V0, 56(S8)
\r
17657 BFD01BEA 4412 NOT16 V0, V0
\r
17658 BFD01BEC 449A AND16 V1, V0
\r
17659 BFD01BEE 0014FC5E LW V0, 20(S8)
\r
17660 BFD01BF2 E9A0 SW V1, 0(V0)
\r
17662 188: xTicksToWait = 0;
\r
17663 BFD01BF4 003CF81E SW ZERO, 60(S8)
\r
17664 BFD01BF6 CC1D003C SHILO null, 60
\r
17665 BFD01BF8 CC1D B 0xBFD01C34
\r
17666 BFD01BFA 0C00 NOP
\r
17670 192: if( xTicksToWait != ( TickType_t ) 0 )
\r
17671 BFD01BFC 003CFC5E LW V0, 60(S8)
\r
17672 BFD01C00 001340E2 BEQZC V0, 0xBFD01C2A
\r
17674 194: traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
\r
17676 196: /* Store the bits that the calling task is waiting for in the
\r
17677 197: task's event list item so the kernel knows when a match is
\r
17678 198: found. Then enter the blocked state. */
\r
17679 199: vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
\r
17680 BFD01C04 0014FC5E LW V0, 20(S8)
\r
17681 BFD01C08 6DA2 ADDIU V1, V0, 4
\r
17682 BFD01C0A 0038FC9E LW A0, 56(S8)
\r
17683 BFD01C0E 050041A2 LUI V0, 0x500
\r
17684 BFD01C10 0500 ADDU V0, S0, S0
\r
17685 BFD01C12 44D4 OR16 V0, A0
\r
17686 BFD01C14 0C83 MOVE A0, V1
\r
17687 BFD01C16 0CA2 MOVE A1, V0
\r
17688 BFD01C18 003CFCDE LW A2, 60(S8)
\r
17689 BFD01C1C 248277E8 JALS vTaskPlaceOnUnorderedEventList
\r
17690 BFD01C1E 2482 SLL S1, S0, 1
\r
17691 BFD01C20 0C00 NOP
\r
17693 201: /* This assignment is obsolete as uxReturn will get set after
\r
17694 202: the task unblocks, but some compilers mistakenly generate a
\r
17695 203: warning about uxReturn being returned without being set if the
\r
17696 204: assignment is omitted. */
\r
17697 205: uxReturn = 0;
\r
17698 BFD01C22 0010F81E SW ZERO, 16(S8)
\r
17699 BFD01C26 CC06 B 0xBFD01C34
\r
17700 BFD01C28 0C00 NOP
\r
17704 209: /* The rendezvous bits were not set, but no block time was
\r
17705 210: specified - just return the current event bit value. */
\r
17706 211: uxReturn = pxEventBits->uxEventBits;
\r
17707 BFD01C2A 0014FC5E LW V0, 20(S8)
\r
17708 BFD01C2E 6920 LW V0, 0(V0)
\r
17709 BFD01C30 0010F85E SW V0, 16(S8)
\r
17713 215: xAlreadyYielded = xTaskResumeAll();
\r
17714 BFD01C34 158E77E8 JALS xTaskResumeAll
\r
17715 BFD01C36 0C00158E LBU T4, 3072(T6)
\r
17716 BFD01C38 0C00 NOP
\r
17717 BFD01C3A 0020F85E SW V0, 32(S8)
\r
17719 217: if( xTicksToWait != ( TickType_t ) 0 )
\r
17720 BFD01C3E 003CFC5E LW V0, 60(S8)
\r
17721 BFD01C42 004840E2 BEQZC V0, 0xBFD01CD6
\r
17723 219: if( xAlreadyYielded == pdFALSE )
\r
17724 BFD01C46 0020FC5E LW V0, 32(S8)
\r
17725 BFD01C4A 001040A2 BNEZC V0, 0xBFD01C6E
\r
17727 221: portYIELD_WITHIN_API();
\r
17728 BFD01C4E 4DE677E8 JALS ulPortGetCP0Cause
\r
17729 BFD01C50 4DE6 ADDIU T7, T7, 3
\r
17730 BFD01C52 0C00 NOP
\r
17731 BFD01C54 0024F85E SW V0, 36(S8)
\r
17732 BFD01C58 0024FC5E LW V0, 36(S8)
\r
17733 BFD01C5C 01005042 ORI V0, V0, 256
\r
17734 BFD01C60 0024F85E SW V0, 36(S8)
\r
17735 BFD01C64 0024FC9E LW A0, 36(S8)
\r
17736 BFD01C68 4DF677E8 JALS vPortSetCP0Cause
\r
17737 BFD01C6A 4DF6 ADDIU T7, T7, -5
\r
17738 BFD01C6C 0C00 NOP
\r
17742 225: mtCOVERAGE_TEST_MARKER();
\r
17745 228: /* The task blocked to wait for its required bits to be set - at this
\r
17746 229: point either the required bits were set or the block time expired. If
\r
17747 230: the required bits were set they will have been stored in the task's
\r
17748 231: event list item, and they should now be retrieved then cleared. */
\r
17749 232: uxReturn = uxTaskResetEventItemValue();
\r
17750 BFD01C6E 4C8677E8 JALS uxTaskResetEventItemValue
\r
17751 BFD01C70 4C86 ADDIU A0, A0, 3
\r
17752 BFD01C72 0C00 NOP
\r
17753 BFD01C74 0010F85E SW V0, 16(S8)
\r
17755 234: if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
\r
17756 BFD01C78 0010FC7E LW V1, 16(S8)
\r
17757 BFD01C7C 020041A2 LUI V0, 0x200
\r
17758 BFD01C80 4493 AND16 V0, V1
\r
17759 BFD01C82 002240A2 BNEZC V0, 0xBFD01CCA
\r
17761 236: /* The task timed out, just return the current event bit value. */
\r
17762 237: taskENTER_CRITICAL();
\r
17763 BFD01C86 33B877E8 JALS vTaskEnterCritical
\r
17764 BFD01C88 0C0033B8 ADDIU SP, T8, 3072
\r
17765 BFD01C8A 0C00 NOP
\r
17767 239: uxReturn = pxEventBits->uxEventBits;
\r
17768 BFD01C8C 0014FC5E LW V0, 20(S8)
\r
17769 BFD01C90 6920 LW V0, 0(V0)
\r
17770 BFD01C92 0010F85E SW V0, 16(S8)
\r
17772 241: /* Although the task got here because it timed out before the
\r
17773 242: bits it was waiting for were set, it is possible that since it
\r
17774 243: unblocked another task has set the bits. If this is the case
\r
17775 244: then it needs to clear the bits before exiting. */
\r
17776 245: if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
\r
17777 BFD01C96 0010FC7E LW V1, 16(S8)
\r
17778 BFD01C9A 0038FC5E LW V0, 56(S8)
\r
17779 BFD01C9E 449A AND16 V1, V0
\r
17780 BFD01CA0 0038FC5E LW V0, 56(S8)
\r
17781 BFD01CA4 000BB443 BNE V1, V0, 0xBFD01CBE
\r
17782 BFD01CA6 0C00000B SLL ZERO, T3, 1
\r
17783 BFD01CA8 0C00 NOP
\r
17785 247: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
\r
17786 BFD01CAA 0014FC5E LW V0, 20(S8)
\r
17787 BFD01CAE 69A0 LW V1, 0(V0)
\r
17788 BFD01CB0 0038FC5E LW V0, 56(S8)
\r
17789 BFD01CB4 4412 NOT16 V0, V0
\r
17790 BFD01CB6 449A AND16 V1, V0
\r
17791 BFD01CB8 0014FC5E LW V0, 20(S8)
\r
17792 BFD01CBC E9A0 SW V1, 0(V0)
\r
17796 251: mtCOVERAGE_TEST_MARKER();
\r
17799 254: taskEXIT_CRITICAL();
\r
17800 BFD01CBE 40AA77E8 JALS vTaskExitCritical
\r
17801 BFD01CC0 0C0040AA BNEZC T2, 0xBFD034C4
\r
17802 BFD01CC2 0C00 NOP
\r
17804 256: xTimeoutOccurred = pdTRUE;
\r
17805 BFD01CC4 ED01 LI V0, 1
\r
17806 BFD01CC6 0018F85E SW V0, 24(S8)
\r
17810 260: /* The task unblocked because the bits were set. */
\r
17813 263: /* Control bits might be set as the task had blocked should not be
\r
17814 264: returned. */
\r
17815 265: uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
\r
17816 BFD01CCA 0010FC5E LW V0, 16(S8)
\r
17817 BFD01CCE B82C0042 EXT V0, V0, 0, 24
\r
17818 BFD01CD0 F85EB82C SDC1 F1, -1954(T4)
\r
17819 BFD01CD2 0010F85E SW V0, 16(S8)
\r
17822 268: traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
\r
17824 270: return uxReturn;
\r
17825 BFD01CD6 0010FC5E LW V0, 16(S8)
\r
17827 BFD01CDA 0FBE MOVE SP, S8
\r
17828 BFD01CDC 4BEB LW RA, 44(SP)
\r
17829 BFD01CDE 4BCA LW S8, 40(SP)
\r
17830 BFD01CE0 4C19 ADDIU SP, SP, 48
\r
17831 BFD01CE2 459F JR16 RA
\r
17832 BFD01CE4 0C00 NOP
\r
17833 272: /*-----------------------------------------------------------*/
\r
17835 274: EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
\r
17837 BFD01310 4FE5 ADDIU SP, SP, -56
\r
17838 BFD01312 CBED SW RA, 52(SP)
\r
17839 BFD01314 CBCC SW S8, 48(SP)
\r
17840 BFD01316 0FDD MOVE S8, SP
\r
17841 BFD01318 0038F89E SW A0, 56(S8)
\r
17842 BFD0131C 003CF8BE SW A1, 60(S8)
\r
17843 BFD01320 0040F8DE SW A2, 64(S8)
\r
17844 BFD01324 0044F8FE SW A3, 68(S8)
\r
17845 276: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
\r
17846 BFD01328 0038FC5E LW V0, 56(S8)
\r
17847 BFD0132C 0018F85E SW V0, 24(S8)
\r
17848 277: EventBits_t uxReturn, uxControlBits = 0;
\r
17849 BFD01330 0014F81E SW ZERO, 20(S8)
\r
17850 278: BaseType_t xWaitConditionMet, xAlreadyYielded;
\r
17851 279: BaseType_t xTimeoutOccurred = pdFALSE;
\r
17852 BFD01334 001CF81E SW ZERO, 28(S8)
\r
17854 281: /* Check the user is not attempting to wait on the bits used by the kernel
\r
17855 282: itself, and that at least one bit is being requested. */
\r
17856 283: configASSERT( xEventGroup );
\r
17857 BFD01338 0038FC5E LW V0, 56(S8)
\r
17858 BFD0133C 000940A2 BNEZC V0, 0xBFD01352
\r
17859 BFD01340 BFD141A2 LUI V0, 0xBFD1
\r
17860 BFD01342 3082BFD1 LDC1 F30, 12418(S1)
\r
17861 BFD01344 9C0C3082 ADDIU A0, V0, -25588
\r
17862 BFD01346 30A09C0C LWC1 F0, 12448(T4)
\r
17863 BFD01348 011B30A0 ADDIU A1, ZERO, 283
\r
17864 BFD0134C 4B7E77E8 JALS vAssertCalled
\r
17865 BFD0134E 4B7E LW K1, 120(SP)
\r
17866 BFD01350 0C00 NOP
\r
17867 284: configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
\r
17868 BFD01352 003CFC7E LW V1, 60(S8)
\r
17869 BFD01356 FF0041A2 LUI V0, 0xFF00
\r
17870 BFD01358 4493FF00 LW T8, 17555(ZERO)
\r
17871 BFD0135A 4493 AND16 V0, V1
\r
17872 BFD0135C 000940E2 BEQZC V0, 0xBFD01372
\r
17873 BFD01360 BFD141A2 LUI V0, 0xBFD1
\r
17874 BFD01362 3082BFD1 LDC1 F30, 12418(S1)
\r
17875 BFD01364 9C0C3082 ADDIU A0, V0, -25588
\r
17876 BFD01366 30A09C0C LWC1 F0, 12448(T4)
\r
17877 BFD01368 011C30A0 ADDIU A1, ZERO, 284
\r
17878 BFD0136C 4B7E77E8 JALS vAssertCalled
\r
17879 BFD0136E 4B7E LW K1, 120(SP)
\r
17880 BFD01370 0C00 NOP
\r
17881 285: configASSERT( uxBitsToWaitFor != 0 );
\r
17882 BFD01372 003CFC5E LW V0, 60(S8)
\r
17883 BFD01376 000940A2 BNEZC V0, 0xBFD0138C
\r
17884 BFD0137A BFD141A2 LUI V0, 0xBFD1
\r
17885 BFD0137C 3082BFD1 LDC1 F30, 12418(S1)
\r
17886 BFD0137E 9C0C3082 ADDIU A0, V0, -25588
\r
17887 BFD01380 30A09C0C LWC1 F0, 12448(T4)
\r
17888 BFD01382 011D30A0 ADDIU A1, ZERO, 285
\r
17889 BFD01386 4B7E77E8 JALS vAssertCalled
\r
17890 BFD01388 4B7E LW K1, 120(SP)
\r
17891 BFD0138A 0C00 NOP
\r
17892 286: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
\r
17894 288: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
\r
17895 BFD0138C 4A8E77E8 JALS xTaskGetSchedulerState
\r
17896 BFD0138E 4A8E LW S4, 56(SP)
\r
17897 BFD01390 0C00 NOP
\r
17898 BFD01392 000440A2 BNEZC V0, 0xBFD0139E
\r
17899 BFD01396 0048FC5E LW V0, 72(S8)
\r
17900 BFD0139A 000340A2 BNEZC V0, 0xBFD013A4
\r
17901 BFD0139E ED01 LI V0, 1
\r
17902 BFD013A0 CC02 B 0xBFD013A6
\r
17903 BFD013A2 0C00 NOP
\r
17904 BFD013A4 0C40 MOVE V0, ZERO
\r
17905 BFD013A6 000940A2 BNEZC V0, 0xBFD013BC
\r
17906 BFD013AA BFD141A2 LUI V0, 0xBFD1
\r
17907 BFD013AC 3082BFD1 LDC1 F30, 12418(S1)
\r
17908 BFD013AE 9C0C3082 ADDIU A0, V0, -25588
\r
17909 BFD013B0 30A09C0C LWC1 F0, 12448(T4)
\r
17910 BFD013B2 012030A0 ADDIU A1, ZERO, 288
\r
17911 BFD013B6 4B7E77E8 JALS vAssertCalled
\r
17912 BFD013B8 4B7E LW K1, 120(SP)
\r
17913 BFD013BA 0C00 NOP
\r
17917 292: vTaskSuspendAll();
\r
17918 BFD013BC 4EF477E8 JALS vTaskSuspendAll
\r
17919 BFD013BE 4EF4 ADDIU S7, S7, -6
\r
17920 BFD013C0 0C00 NOP
\r
17922 294: const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
\r
17923 BFD013C2 0018FC5E LW V0, 24(S8)
\r
17924 BFD013C6 6920 LW V0, 0(V0)
\r
17925 BFD013C8 0020F85E SW V0, 32(S8)
\r
17927 296: /* Check to see if the wait condition is already met or not. */
\r
17928 297: xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
\r
17929 BFD013CC 0020FC9E LW A0, 32(S8)
\r
17930 BFD013D0 003CFCBE LW A1, 60(S8)
\r
17931 BFD013D4 0044FCDE LW A2, 68(S8)
\r
17932 BFD013D8 407A77E8 JALS prvTestWaitCondition
\r
17933 BFD013DA 0C00407A BGEZAL K0, 0xBFD02BDE
\r
17934 BFD013DC 0C00 NOP
\r
17935 BFD013DE 0024F85E SW V0, 36(S8)
\r
17937 299: if( xWaitConditionMet != pdFALSE )
\r
17938 BFD013E2 0024FC5E LW V0, 36(S8)
\r
17939 BFD013E6 001640E2 BEQZC V0, 0xBFD01416
\r
17941 301: /* The wait condition has already been met so there is no need to
\r
17943 303: uxReturn = uxCurrentEventBits;
\r
17944 BFD013EA 0020FC5E LW V0, 32(S8)
\r
17945 BFD013EE 0010F85E SW V0, 16(S8)
\r
17946 304: xTicksToWait = ( TickType_t ) 0;
\r
17947 BFD013F2 0048F81E SW ZERO, 72(S8)
\r
17949 306: /* Clear the wait bits if requested to do so. */
\r
17950 307: if( xClearOnExit != pdFALSE )
\r
17951 BFD013F6 0040FC5E LW V0, 64(S8)
\r
17952 BFD013FA 003D40E2 BEQZC V0, 0xBFD01478
\r
17954 309: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
\r
17955 BFD013FE 0018FC5E LW V0, 24(S8)
\r
17956 BFD01402 69A0 LW V1, 0(V0)
\r
17957 BFD01404 003CFC5E LW V0, 60(S8)
\r
17958 BFD01408 4412 NOT16 V0, V0
\r
17959 BFD0140A 449A AND16 V1, V0
\r
17960 BFD0140C 0018FC5E LW V0, 24(S8)
\r
17961 BFD01410 E9A0 SW V1, 0(V0)
\r
17962 BFD01412 CC32 B 0xBFD01478
\r
17963 BFD01414 0C00 NOP
\r
17967 313: mtCOVERAGE_TEST_MARKER();
\r
17970 316: else if( xTicksToWait == ( TickType_t ) 0 )
\r
17971 BFD01416 0048FC5E LW V0, 72(S8)
\r
17972 BFD0141A 000640A2 BNEZC V0, 0xBFD0142A
\r
17974 318: /* The wait condition has not been met, but no block time was
\r
17975 319: specified, so just return the current value. */
\r
17976 320: uxReturn = uxCurrentEventBits;
\r
17977 BFD0141E 0020FC5E LW V0, 32(S8)
\r
17978 BFD01422 0010F85E SW V0, 16(S8)
\r
17979 BFD01426 CC28 B 0xBFD01478
\r
17980 BFD01428 0C00 NOP
\r
17984 324: /* The task is going to block to wait for its required bits to be
\r
17985 325: set. uxControlBits are used to remember the specified behaviour of
\r
17986 326: this call to xEventGroupWaitBits() - for use when the event bits
\r
17987 327: unblock the task. */
\r
17988 328: if( xClearOnExit != pdFALSE )
\r
17989 BFD0142A 0040FC5E LW V0, 64(S8)
\r
17990 BFD0142E 000740E2 BEQZC V0, 0xBFD01440
\r
17992 330: uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
\r
17993 BFD01432 0014FC7E LW V1, 20(S8)
\r
17994 BFD01436 010041A2 LUI V0, 0x100
\r
17995 BFD0143A 44D3 OR16 V0, V1
\r
17996 BFD0143C 0014F85E SW V0, 20(S8)
\r
18000 334: mtCOVERAGE_TEST_MARKER();
\r
18003 337: if( xWaitForAllBits != pdFALSE )
\r
18004 BFD01440 0044FC5E LW V0, 68(S8)
\r
18005 BFD01444 000740E2 BEQZC V0, 0xBFD01456
\r
18007 339: uxControlBits |= eventWAIT_FOR_ALL_BITS;
\r
18008 BFD01448 0014FC7E LW V1, 20(S8)
\r
18009 BFD0144C 040041A2 LUI V0, 0x400
\r
18010 BFD0144E 0400 ADDU S0, S0, S0
\r
18011 BFD01450 44D3 OR16 V0, V1
\r
18012 BFD01452 0014F85E SW V0, 20(S8)
\r
18016 343: mtCOVERAGE_TEST_MARKER();
\r
18019 346: /* Store the bits that the calling task is waiting for in the
\r
18020 347: task's event list item so the kernel knows when a match is
\r
18021 348: found. Then enter the blocked state. */
\r
18022 349: vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
\r
18023 BFD01456 0018FC5E LW V0, 24(S8)
\r
18024 BFD0145A 6DA2 ADDIU V1, V0, 4
\r
18025 BFD0145C 003CFC9E LW A0, 60(S8)
\r
18026 BFD01460 0014FC5E LW V0, 20(S8)
\r
18027 BFD01464 44D4 OR16 V0, A0
\r
18028 BFD01466 0C83 MOVE A0, V1
\r
18029 BFD01468 0CA2 MOVE A1, V0
\r
18030 BFD0146A 0048FCDE LW A2, 72(S8)
\r
18031 BFD0146E 248277E8 JALS vTaskPlaceOnUnorderedEventList
\r
18032 BFD01470 2482 SLL S1, S0, 1
\r
18033 BFD01472 0C00 NOP
\r
18035 351: /* This is obsolete as it will get set after the task unblocks, but
\r
18036 352: some compilers mistakenly generate a warning about the variable
\r
18037 353: being returned without being set if it is not done. */
\r
18038 354: uxReturn = 0;
\r
18039 BFD01474 0010F81E SW ZERO, 16(S8)
\r
18041 356: traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
\r
18044 359: xAlreadyYielded = xTaskResumeAll();
\r
18045 BFD01478 158E77E8 JALS xTaskResumeAll
\r
18046 BFD0147A 0C00158E LBU T4, 3072(T6)
\r
18047 BFD0147C 0C00 NOP
\r
18048 BFD0147E 0028F85E SW V0, 40(S8)
\r
18050 361: if( xTicksToWait != ( TickType_t ) 0 )
\r
18051 BFD01482 0048FC5E LW V0, 72(S8)
\r
18052 BFD01486 004C40E2 BEQZC V0, 0xBFD01522
\r
18054 363: if( xAlreadyYielded == pdFALSE )
\r
18055 BFD0148A 0028FC5E LW V0, 40(S8)
\r
18056 BFD0148E 001040A2 BNEZC V0, 0xBFD014B2
\r
18058 365: portYIELD_WITHIN_API();
\r
18059 BFD01492 4DE677E8 JALS ulPortGetCP0Cause
\r
18060 BFD01494 4DE6 ADDIU T7, T7, 3
\r
18061 BFD01496 0C00 NOP
\r
18062 BFD01498 002CF85E SW V0, 44(S8)
\r
18063 BFD0149C 002CFC5E LW V0, 44(S8)
\r
18064 BFD014A0 01005042 ORI V0, V0, 256
\r
18065 BFD014A4 002CF85E SW V0, 44(S8)
\r
18066 BFD014A8 002CFC9E LW A0, 44(S8)
\r
18067 BFD014AC 4DF677E8 JALS vPortSetCP0Cause
\r
18068 BFD014AE 4DF6 ADDIU T7, T7, -5
\r
18069 BFD014B0 0C00 NOP
\r
18073 369: mtCOVERAGE_TEST_MARKER();
\r
18076 372: /* The task blocked to wait for its required bits to be set - at this
\r
18077 373: point either the required bits were set or the block time expired. If
\r
18078 374: the required bits were set they will have been stored in the task's
\r
18079 375: event list item, and they should now be retrieved then cleared. */
\r
18080 376: uxReturn = uxTaskResetEventItemValue();
\r
18081 BFD014B2 4C8677E8 JALS uxTaskResetEventItemValue
\r
18082 BFD014B4 4C86 ADDIU A0, A0, 3
\r
18083 BFD014B6 0C00 NOP
\r
18084 BFD014B8 0010F85E SW V0, 16(S8)
\r
18086 378: if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
\r
18087 BFD014BC 0010FC7E LW V1, 16(S8)
\r
18088 BFD014C0 020041A2 LUI V0, 0x200
\r
18089 BFD014C4 4493 AND16 V0, V1
\r
18090 BFD014C6 002640A2 BNEZC V0, 0xBFD01516
\r
18092 380: taskENTER_CRITICAL();
\r
18093 BFD014CA 33B877E8 JALS vTaskEnterCritical
\r
18094 BFD014CC 0C0033B8 ADDIU SP, T8, 3072
\r
18095 BFD014CE 0C00 NOP
\r
18097 382: /* The task timed out, just return the current event bit value. */
\r
18098 383: uxReturn = pxEventBits->uxEventBits;
\r
18099 BFD014D0 0018FC5E LW V0, 24(S8)
\r
18100 BFD014D4 6920 LW V0, 0(V0)
\r
18101 BFD014D6 0010F85E SW V0, 16(S8)
\r
18103 385: /* It is possible that the event bits were updated between this
\r
18104 386: task leaving the Blocked state and running again. */
\r
18105 387: if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
\r
18106 BFD014DA 0010FC9E LW A0, 16(S8)
\r
18107 BFD014DE 003CFCBE LW A1, 60(S8)
\r
18108 BFD014E2 0044FCDE LW A2, 68(S8)
\r
18109 BFD014E6 407A77E8 JALS prvTestWaitCondition
\r
18110 BFD014E8 0C00407A BGEZAL K0, 0xBFD02CEC
\r
18111 BFD014EA 0C00 NOP
\r
18112 BFD014EC 000E40E2 BEQZC V0, 0xBFD0150C
\r
18114 389: if( xClearOnExit != pdFALSE )
\r
18115 BFD014F0 0040FC5E LW V0, 64(S8)
\r
18116 BFD014F4 000A40E2 BEQZC V0, 0xBFD0150C
\r
18118 391: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
\r
18119 BFD014F8 0018FC5E LW V0, 24(S8)
\r
18120 BFD014FC 69A0 LW V1, 0(V0)
\r
18121 BFD014FE 003CFC5E LW V0, 60(S8)
\r
18122 BFD01502 4412 NOT16 V0, V0
\r
18123 BFD01504 449A AND16 V1, V0
\r
18124 BFD01506 0018FC5E LW V0, 24(S8)
\r
18125 BFD0150A E9A0 SW V1, 0(V0)
\r
18129 395: mtCOVERAGE_TEST_MARKER();
\r
18134 400: mtCOVERAGE_TEST_MARKER();
\r
18137 403: taskEXIT_CRITICAL();
\r
18138 BFD0150C 40AA77E8 JALS vTaskExitCritical
\r
18139 BFD0150E 0C0040AA BNEZC T2, 0xBFD02D12
\r
18140 BFD01510 0C00 NOP
\r
18142 405: /* Prevent compiler warnings when trace macros are not used. */
\r
18143 406: xTimeoutOccurred = pdFALSE;
\r
18144 BFD01512 001CF81E SW ZERO, 28(S8)
\r
18148 410: /* The task unblocked because the bits were set. */
\r
18151 413: /* The task blocked so control bits may have been set. */
\r
18152 414: uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
\r
18153 BFD01516 0010FC5E LW V0, 16(S8)
\r
18154 BFD0151A B82C0042 EXT V0, V0, 0, 24
\r
18155 BFD0151C F85EB82C SDC1 F1, -1954(T4)
\r
18156 BFD0151E 0010F85E SW V0, 16(S8)
\r
18158 416: traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
\r
18160 418: return uxReturn;
\r
18161 BFD01522 0010FC5E LW V0, 16(S8)
\r
18163 BFD01526 0FBE MOVE SP, S8
\r
18164 BFD01528 4BED LW RA, 52(SP)
\r
18165 BFD0152A 4BCC LW S8, 48(SP)
\r
18166 BFD0152C 4C1D ADDIU SP, SP, 56
\r
18167 BFD0152E 459F JR16 RA
\r
18168 BFD01530 0C00 NOP
\r
18169 420: /*-----------------------------------------------------------*/
\r
18171 422: EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
\r
18173 BFD06A44 4FF1 ADDIU SP, SP, -32
\r
18174 BFD06A46 CBE7 SW RA, 28(SP)
\r
18175 BFD06A48 CBC6 SW S8, 24(SP)
\r
18176 BFD06A4A 0FDD MOVE S8, SP
\r
18177 BFD06A4C 0020F89E SW A0, 32(S8)
\r
18178 BFD06A50 0024F8BE SW A1, 36(S8)
\r
18179 424: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
\r
18180 BFD06A54 0020FC5E LW V0, 32(S8)
\r
18181 BFD06A58 0010F85E SW V0, 16(S8)
\r
18182 425: EventBits_t uxReturn;
\r
18184 427: /* Check the user is not attempting to clear the bits used by the kernel
\r
18186 429: configASSERT( xEventGroup );
\r
18187 BFD06A5C 0020FC5E LW V0, 32(S8)
\r
18188 BFD06A60 000940A2 BNEZC V0, 0xBFD06A76
\r
18189 BFD06A64 BFD141A2 LUI V0, 0xBFD1
\r
18190 BFD06A66 3082BFD1 LDC1 F30, 12418(S1)
\r
18191 BFD06A68 9C0C3082 ADDIU A0, V0, -25588
\r
18192 BFD06A6A 30A09C0C LWC1 F0, 12448(T4)
\r
18193 BFD06A6C 01AD30A0 ADDIU A1, ZERO, 429
\r
18194 BFD06A70 4B7E77E8 JALS vAssertCalled
\r
18195 BFD06A72 4B7E LW K1, 120(SP)
\r
18196 BFD06A74 0C00 NOP
\r
18197 430: configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
\r
18198 BFD06A76 0024FC7E LW V1, 36(S8)
\r
18199 BFD06A7A FF0041A2 LUI V0, 0xFF00
\r
18200 BFD06A7C 4493FF00 LW T8, 17555(ZERO)
\r
18201 BFD06A7E 4493 AND16 V0, V1
\r
18202 BFD06A80 000940E2 BEQZC V0, 0xBFD06A96
\r
18203 BFD06A84 BFD141A2 LUI V0, 0xBFD1
\r
18204 BFD06A86 3082BFD1 LDC1 F30, 12418(S1)
\r
18205 BFD06A88 9C0C3082 ADDIU A0, V0, -25588
\r
18206 BFD06A8A 30A09C0C LWC1 F0, 12448(T4)
\r
18207 BFD06A8C 01AE30A0 ADDIU A1, ZERO, 430
\r
18208 BFD06A90 4B7E77E8 JALS vAssertCalled
\r
18209 BFD06A92 4B7E LW K1, 120(SP)
\r
18210 BFD06A94 0C00 NOP
\r
18212 432: taskENTER_CRITICAL();
\r
18213 BFD06A96 33B877E8 JALS vTaskEnterCritical
\r
18214 BFD06A98 0C0033B8 ADDIU SP, T8, 3072
\r
18215 BFD06A9A 0C00 NOP
\r
18217 434: traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
\r
18219 436: /* The value returned is the event group value prior to the bits being
\r
18221 438: uxReturn = pxEventBits->uxEventBits;
\r
18222 BFD06A9C 0010FC5E LW V0, 16(S8)
\r
18223 BFD06AA0 6920 LW V0, 0(V0)
\r
18224 BFD06AA2 0014F85E SW V0, 20(S8)
\r
18226 440: /* Clear the bits. */
\r
18227 441: pxEventBits->uxEventBits &= ~uxBitsToClear;
\r
18228 BFD06AA6 0010FC5E LW V0, 16(S8)
\r
18229 BFD06AAA 69A0 LW V1, 0(V0)
\r
18230 BFD06AAC 0024FC5E LW V0, 36(S8)
\r
18231 BFD06AB0 4412 NOT16 V0, V0
\r
18232 BFD06AB2 449A AND16 V1, V0
\r
18233 BFD06AB4 0010FC5E LW V0, 16(S8)
\r
18234 BFD06AB8 E9A0 SW V1, 0(V0)
\r
18236 443: taskEXIT_CRITICAL();
\r
18237 BFD06ABA 40AA77E8 JALS vTaskExitCritical
\r
18238 BFD06ABC 0C0040AA BNEZC T2, 0xBFD082C0
\r
18239 BFD06ABE 0C00 NOP
\r
18241 445: return uxReturn;
\r
18242 BFD06AC0 0014FC5E LW V0, 20(S8)
\r
18244 BFD06AC4 0FBE MOVE SP, S8
\r
18245 BFD06AC6 4BE7 LW RA, 28(SP)
\r
18246 BFD06AC8 4BC6 LW S8, 24(SP)
\r
18247 BFD06ACA 4C11 ADDIU SP, SP, 32
\r
18248 BFD06ACC 459F JR16 RA
\r
18249 BFD06ACE 0C00 NOP
\r
18250 447: /*-----------------------------------------------------------*/
\r
18252 449: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
\r
18254 451: BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
\r
18256 453: BaseType_t xReturn;
\r
18258 455: traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
\r
18259 456: xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
\r
18261 458: return xReturn;
\r
18265 462: /*-----------------------------------------------------------*/
\r
18267 464: EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
\r
18269 BFD09144 4FED ADDIU SP, SP, -40
\r
18270 BFD09146 CBE9 SW RA, 36(SP)
\r
18271 BFD09148 CBC8 SW S8, 32(SP)
\r
18272 BFD0914A 0FDD MOVE S8, SP
\r
18273 BFD0914C 0028F89E SW A0, 40(S8)
\r
18274 466: UBaseType_t uxSavedInterruptStatus;
\r
18275 467: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
\r
18276 BFD09150 0028FC5E LW V0, 40(S8)
\r
18277 BFD09154 0010F85E SW V0, 16(S8)
\r
18278 468: EventBits_t uxReturn;
\r
18280 470: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
\r
18281 BFD09158 475E77E8 JALS uxPortSetInterruptMaskFromISR
\r
18282 BFD0915C 0C00 NOP
\r
18283 BFD0915E 0014F85E SW V0, 20(S8)
\r
18285 472: uxReturn = pxEventBits->uxEventBits;
\r
18286 BFD09162 0010FC5E LW V0, 16(S8)
\r
18287 BFD09166 6920 LW V0, 0(V0)
\r
18288 BFD09168 0018F85E SW V0, 24(S8)
\r
18290 474: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
\r
18291 BFD0916C 0014FC9E LW A0, 20(S8)
\r
18292 BFD09170 4D5E77E8 JALS vPortClearInterruptMaskFromISR
\r
18293 BFD09172 4D5E ADDIU T2, T2, -1
\r
18294 BFD09174 0C00 NOP
\r
18296 476: return uxReturn;
\r
18297 BFD09176 0018FC5E LW V0, 24(S8)
\r
18299 BFD0917A 0FBE MOVE SP, S8
\r
18300 BFD0917C 4BE9 LW RA, 36(SP)
\r
18301 BFD0917E 4BC8 LW S8, 32(SP)
\r
18302 BFD09180 4C15 ADDIU SP, SP, 40
\r
18303 BFD09182 459F JR16 RA
\r
18304 BFD09184 0C00 NOP
\r
18305 478: /*-----------------------------------------------------------*/
\r
18307 480: EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
\r
18309 BFD02568 4FE1 ADDIU SP, SP, -64
\r
18310 BFD0256A CBEF SW RA, 60(SP)
\r
18311 BFD0256C CBCE SW S8, 56(SP)
\r
18312 BFD0256E 0FDD MOVE S8, SP
\r
18313 BFD02570 0040F89E SW A0, 64(S8)
\r
18314 BFD02574 0044F8BE SW A1, 68(S8)
\r
18315 482: ListItem_t *pxListItem, *pxNext;
\r
18316 483: ListItem_t const *pxListEnd;
\r
18317 484: List_t *pxList;
\r
18318 485: EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
\r
18319 BFD02578 0014F81E SW ZERO, 20(S8)
\r
18320 486: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
\r
18321 BFD0257C 0040FC5E LW V0, 64(S8)
\r
18322 BFD02580 001CF85E SW V0, 28(S8)
\r
18323 487: BaseType_t xMatchFound = pdFALSE;
\r
18324 BFD02584 0018F81E SW ZERO, 24(S8)
\r
18326 489: /* Check the user is not attempting to set the bits used by the kernel
\r
18328 491: configASSERT( xEventGroup );
\r
18329 BFD02588 0040FC5E LW V0, 64(S8)
\r
18330 BFD0258C 000940A2 BNEZC V0, 0xBFD025A2
\r
18331 BFD02590 BFD141A2 LUI V0, 0xBFD1
\r
18332 BFD02592 3082BFD1 LDC1 F30, 12418(S1)
\r
18333 BFD02594 9C0C3082 ADDIU A0, V0, -25588
\r
18334 BFD02596 30A09C0C LWC1 F0, 12448(T4)
\r
18335 BFD02598 01EB30A0 ADDIU A1, ZERO, 491
\r
18336 BFD0259C 4B7E77E8 JALS vAssertCalled
\r
18337 BFD0259E 4B7E LW K1, 120(SP)
\r
18338 BFD025A0 0C00 NOP
\r
18339 492: configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
\r
18340 BFD025A2 0044FC7E LW V1, 68(S8)
\r
18341 BFD025A6 FF0041A2 LUI V0, 0xFF00
\r
18342 BFD025A8 4493FF00 LW T8, 17555(ZERO)
\r
18343 BFD025AA 4493 AND16 V0, V1
\r
18344 BFD025AC 000940E2 BEQZC V0, 0xBFD025C2
\r
18345 BFD025B0 BFD141A2 LUI V0, 0xBFD1
\r
18346 BFD025B2 3082BFD1 LDC1 F30, 12418(S1)
\r
18347 BFD025B4 9C0C3082 ADDIU A0, V0, -25588
\r
18348 BFD025B6 30A09C0C LWC1 F0, 12448(T4)
\r
18349 BFD025B8 01EC30A0 ADDIU A1, ZERO, 492
\r
18350 BFD025BC 4B7E77E8 JALS vAssertCalled
\r
18351 BFD025BE 4B7E LW K1, 120(SP)
\r
18352 BFD025C0 0C00 NOP
\r
18354 494: pxList = &( pxEventBits->xTasksWaitingForBits );
\r
18355 BFD025C2 001CFC5E LW V0, 28(S8)
\r
18356 BFD025C6 6D22 ADDIU V0, V0, 4
\r
18357 BFD025C8 0020F85E SW V0, 32(S8)
\r
18358 495: pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
\r
18359 BFD025CC 0020FC5E LW V0, 32(S8)
\r
18360 BFD025D0 6D24 ADDIU V0, V0, 8
\r
18361 BFD025D2 0024F85E SW V0, 36(S8)
\r
18362 496: vTaskSuspendAll();
\r
18363 BFD025D6 4EF477E8 JALS vTaskSuspendAll
\r
18364 BFD025D8 4EF4 ADDIU S7, S7, -6
\r
18365 BFD025DA 0C00 NOP
\r
18367 498: traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
\r
18369 500: pxListItem = listGET_HEAD_ENTRY( pxList );
\r
18370 BFD025DC 0020FC5E LW V0, 32(S8)
\r
18371 BFD025E0 6923 LW V0, 12(V0)
\r
18372 BFD025E2 0010F85E SW V0, 16(S8)
\r
18374 502: /* Set the bits. */
\r
18375 503: pxEventBits->uxEventBits |= uxBitsToSet;
\r
18376 BFD025E6 001CFC5E LW V0, 28(S8)
\r
18377 BFD025EA 69A0 LW V1, 0(V0)
\r
18378 BFD025EC 0044FC5E LW V0, 68(S8)
\r
18379 BFD025F0 44DA OR16 V1, V0
\r
18380 BFD025F2 001CFC5E LW V0, 28(S8)
\r
18381 BFD025F6 E9A0 SW V1, 0(V0)
\r
18383 505: /* See if the new bit value should unblock any tasks. */
\r
18384 506: while( pxListItem != pxListEnd )
\r
18385 BFD025F8 CC5E B 0xBFD026B6
\r
18386 BFD025FA 0C00 NOP
\r
18387 BFD026B6 0010FC7E LW V1, 16(S8)
\r
18388 BFD026BA 0024FC5E LW V0, 36(S8)
\r
18389 BFD026BE FF9DB443 BNE V1, V0, 0xBFD025FC
\r
18390 BFD026C0 0C00FF9D LW GP, 3072(SP)
\r
18391 BFD026C2 0C00 NOP
\r
18393 508: pxNext = listGET_NEXT( pxListItem );
\r
18394 BFD025FC 0010FC5E LW V0, 16(S8)
\r
18395 BFD02600 6921 LW V0, 4(V0)
\r
18396 BFD02602 0028F85E SW V0, 40(S8)
\r
18397 509: uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
\r
18398 BFD02606 0010FC5E LW V0, 16(S8)
\r
18399 BFD0260A 6920 LW V0, 0(V0)
\r
18400 BFD0260C 002CF85E SW V0, 44(S8)
\r
18401 510: xMatchFound = pdFALSE;
\r
18402 BFD02610 0018F81E SW ZERO, 24(S8)
\r
18404 512: /* Split the bits waited for from the control bits. */
\r
18405 513: uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
\r
18406 BFD02614 002CFC7E LW V1, 44(S8)
\r
18407 BFD02618 FF0041A2 LUI V0, 0xFF00
\r
18408 BFD0261A 4493FF00 LW T8, 17555(ZERO)
\r
18409 BFD0261C 4493 AND16 V0, V1
\r
18410 BFD0261E 0030F85E SW V0, 48(S8)
\r
18411 514: uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
\r
18412 BFD02622 002CFC5E LW V0, 44(S8)
\r
18413 BFD02626 B82C0042 EXT V0, V0, 0, 24
\r
18414 BFD02628 F85EB82C SDC1 F1, -1954(T4)
\r
18415 BFD0262A 002CF85E SW V0, 44(S8)
\r
18417 516: if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
\r
18418 BFD0262E 0030FC7E LW V1, 48(S8)
\r
18419 BFD02632 040041A2 LUI V0, 0x400
\r
18420 BFD02634 0400 ADDU S0, S0, S0
\r
18421 BFD02636 4493 AND16 V0, V1
\r
18422 BFD02638 000D40A2 BNEZC V0, 0xBFD02656
\r
18424 518: /* Just looking for single bit being set. */
\r
18425 519: if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
\r
18426 BFD0263C 001CFC5E LW V0, 28(S8)
\r
18427 BFD02640 69A0 LW V1, 0(V0)
\r
18428 BFD02642 002CFC5E LW V0, 44(S8)
\r
18429 BFD02646 4493 AND16 V0, V1
\r
18430 BFD02648 001340E2 BEQZC V0, 0xBFD02672
\r
18432 521: xMatchFound = pdTRUE;
\r
18433 BFD0264C ED01 LI V0, 1
\r
18434 BFD0264E 0018F85E SW V0, 24(S8)
\r
18435 BFD02652 CC0F B 0xBFD02672
\r
18436 BFD02654 0C00 NOP
\r
18440 525: mtCOVERAGE_TEST_MARKER();
\r
18443 528: else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
\r
18444 BFD02656 001CFC5E LW V0, 28(S8)
\r
18445 BFD0265A 69A0 LW V1, 0(V0)
\r
18446 BFD0265C 002CFC5E LW V0, 44(S8)
\r
18447 BFD02660 449A AND16 V1, V0
\r
18448 BFD02662 002CFC5E LW V0, 44(S8)
\r
18449 BFD02666 0004B443 BNE V1, V0, 0xBFD02672
\r
18450 BFD02668 0C000004 SLL ZERO, A0, 1
\r
18451 BFD0266A 0C00 NOP
\r
18453 530: /* All bits are set. */
\r
18454 531: xMatchFound = pdTRUE;
\r
18455 BFD0266C ED01 LI V0, 1
\r
18456 BFD0266E 0018F85E SW V0, 24(S8)
\r
18460 535: /* Need all bits to be set, but not all the bits were set. */
\r
18463 538: if( xMatchFound != pdFALSE )
\r
18464 BFD02672 0018FC5E LW V0, 24(S8)
\r
18465 BFD02676 001A40E2 BEQZC V0, 0xBFD026AE
\r
18467 540: /* The bits match. Should the bits be cleared on exit? */
\r
18468 541: if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
\r
18469 BFD0267A 0030FC7E LW V1, 48(S8)
\r
18470 BFD0267E 010041A2 LUI V0, 0x100
\r
18471 BFD02682 4493 AND16 V0, V1
\r
18472 BFD02684 000740E2 BEQZC V0, 0xBFD02696
\r
18474 543: uxBitsToClear |= uxBitsWaitedFor;
\r
18475 BFD02688 0014FC7E LW V1, 20(S8)
\r
18476 BFD0268C 002CFC5E LW V0, 44(S8)
\r
18477 BFD02690 44D3 OR16 V0, V1
\r
18478 BFD02692 0014F85E SW V0, 20(S8)
\r
18482 547: mtCOVERAGE_TEST_MARKER();
\r
18485 550: /* Store the actual event flag value in the task's event list
\r
18486 551: item before removing the task from the event list. The
\r
18487 552: eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
\r
18488 553: that is was unblocked due to its required bits matching, rather
\r
18489 554: than because it timed out. */
\r
18490 555: ( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
\r
18491 BFD02696 001CFC5E LW V0, 28(S8)
\r
18492 BFD0269A 69A0 LW V1, 0(V0)
\r
18493 BFD0269C 020041A2 LUI V0, 0x200
\r
18494 BFD026A0 44D3 OR16 V0, V1
\r
18495 BFD026A2 0010FC9E LW A0, 16(S8)
\r
18496 BFD026A6 0CA2 MOVE A1, V0
\r
18497 BFD026A8 216277E8 JALS xTaskRemoveFromUnorderedEventList
\r
18498 BFD026AA 0C002162 LWC2 T3, 3072(V0)
\r
18499 BFD026AC 0C00 NOP
\r
18502 558: /* Move onto the next list item. Note pxListItem->pxNext is not
\r
18503 559: used here as the list item may have been removed from the event list
\r
18504 560: and inserted into the ready/pending reading list. */
\r
18505 561: pxListItem = pxNext;
\r
18506 BFD026AE 0028FC5E LW V0, 40(S8)
\r
18507 BFD026B2 0010F85E SW V0, 16(S8)
\r
18510 564: /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
\r
18511 565: bit was set in the control word. */
\r
18512 566: pxEventBits->uxEventBits &= ~uxBitsToClear;
\r
18513 BFD026C4 001CFC5E LW V0, 28(S8)
\r
18514 BFD026C8 69A0 LW V1, 0(V0)
\r
18515 BFD026CA 0014FC5E LW V0, 20(S8)
\r
18516 BFD026CE 4412 NOT16 V0, V0
\r
18517 BFD026D0 449A AND16 V1, V0
\r
18518 BFD026D2 001CFC5E LW V0, 28(S8)
\r
18519 BFD026D6 E9A0 SW V1, 0(V0)
\r
18521 568: ( void ) xTaskResumeAll();
\r
18522 BFD026D8 158E77E8 JALS xTaskResumeAll
\r
18523 BFD026DA 0C00158E LBU T4, 3072(T6)
\r
18524 BFD026DC 0C00 NOP
\r
18526 570: return pxEventBits->uxEventBits;
\r
18527 BFD026DE 001CFC5E LW V0, 28(S8)
\r
18528 BFD026E2 6920 LW V0, 0(V0)
\r
18530 BFD026E4 0FBE MOVE SP, S8
\r
18531 BFD026E6 4BEF LW RA, 60(SP)
\r
18532 BFD026E8 4BCE LW S8, 56(SP)
\r
18533 BFD026EA 4C21 ADDIU SP, SP, 64
\r
18534 BFD026EC 459F JR16 RA
\r
18535 BFD026EE 0C00 NOP
\r
18536 572: /*-----------------------------------------------------------*/
\r
18538 574: void vEventGroupDelete( EventGroupHandle_t xEventGroup )
\r
18540 BFD06C70 4FF1 ADDIU SP, SP, -32
\r
18541 BFD06C72 CBE7 SW RA, 28(SP)
\r
18542 BFD06C74 CBC6 SW S8, 24(SP)
\r
18543 BFD06C76 0FDD MOVE S8, SP
\r
18544 BFD06C78 0020F89E SW A0, 32(S8)
\r
18545 576: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
\r
18546 BFD06C7C 0020FC5E LW V0, 32(S8)
\r
18547 BFD06C80 0010F85E SW V0, 16(S8)
\r
18548 577: const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
\r
18549 BFD06C84 0010FC5E LW V0, 16(S8)
\r
18550 BFD06C88 6D22 ADDIU V0, V0, 4
\r
18551 BFD06C8A 0014F85E SW V0, 20(S8)
\r
18553 579: vTaskSuspendAll();
\r
18554 BFD06C8E 4EF477E8 JALS vTaskSuspendAll
\r
18555 BFD06C90 4EF4 ADDIU S7, S7, -6
\r
18556 BFD06C92 0C00 NOP
\r
18558 581: traceEVENT_GROUP_DELETE( xEventGroup );
\r
18560 583: while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
\r
18561 BFD06C94 CC1C B 0xBFD06CCE
\r
18562 BFD06C96 0C00 NOP
\r
18563 BFD06CCE 0014FC5E LW V0, 20(S8)
\r
18564 BFD06CD2 6920 LW V0, 0(V0)
\r
18565 BFD06CD4 FFE040A2 BNEZC V0, 0xBFD06C98
\r
18566 BFD06CD6 FC9EFFE0 LW RA, -866(ZERO)
\r
18568 585: /* Unblock the task, returning 0 as the event list is being deleted
\r
18569 586: and cannot therefore have any bits set. */
\r
18570 587: configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
\r
18571 BFD06C98 0014FC5E LW V0, 20(S8)
\r
18572 BFD06C9C 69A3 LW V1, 12(V0)
\r
18573 BFD06C9E 0014FC5E LW V0, 20(S8)
\r
18574 BFD06CA2 6D24 ADDIU V0, V0, 8
\r
18575 BFD06CA4 000AB443 BNE V1, V0, 0xBFD06CBC
\r
18576 BFD06CA6 0C00000A SLL ZERO, T2, 1
\r
18577 BFD06CA8 0C00 NOP
\r
18578 BFD06CAA BFD141A2 LUI V0, 0xBFD1
\r
18579 BFD06CAC 3082BFD1 LDC1 F30, 12418(S1)
\r
18580 BFD06CAE 9C0C3082 ADDIU A0, V0, -25588
\r
18581 BFD06CB0 30A09C0C LWC1 F0, 12448(T4)
\r
18582 BFD06CB2 024B30A0 ADDIU A1, ZERO, 587
\r
18583 BFD06CB6 4B7E77E8 JALS vAssertCalled
\r
18584 BFD06CB8 4B7E LW K1, 120(SP)
\r
18585 BFD06CBA 0C00 NOP
\r
18586 588: ( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
\r
18587 BFD06CBC 0014FC5E LW V0, 20(S8)
\r
18588 BFD06CC0 6923 LW V0, 12(V0)
\r
18589 BFD06CC2 0C82 MOVE A0, V0
\r
18590 BFD06CC4 020041A5 LUI A1, 0x200
\r
18591 BFD06CC8 216277E8 JALS xTaskRemoveFromUnorderedEventList
\r
18592 BFD06CCA 0C002162 LWC2 T3, 3072(V0)
\r
18593 BFD06CCC 0C00 NOP
\r
18596 591: vPortFree( pxEventBits );
\r
18597 BFD06CD8 0010FC9E LW A0, 16(S8)
\r
18598 BFD06CDC 2FEA77E8 JALS vPortFree
\r
18599 BFD06CDE 2FEA ANDI A3, A2, 0x20
\r
18600 BFD06CE0 0C00 NOP
\r
18602 593: ( void ) xTaskResumeAll();
\r
18603 BFD06CE2 158E77E8 JALS xTaskResumeAll
\r
18604 BFD06CE4 0C00158E LBU T4, 3072(T6)
\r
18605 BFD06CE6 0C00 NOP
\r
18607 BFD06CE8 0FBE MOVE SP, S8
\r
18608 BFD06CEA 4BE7 LW RA, 28(SP)
\r
18609 BFD06CEC 4BC6 LW S8, 24(SP)
\r
18610 BFD06CEE 4C11 ADDIU SP, SP, 32
\r
18611 BFD06CF0 459F JR16 RA
\r
18612 BFD06CF2 0C00 NOP
\r
18613 595: /*-----------------------------------------------------------*/
\r
18615 597: /* For internal use only - execute a 'set bits' command that was pended from
\r
18616 598: an interrupt. */
\r
18617 599: void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
\r
18619 BFD0993C 4FF5 ADDIU SP, SP, -24
\r
18620 BFD0993E CBE5 SW RA, 20(SP)
\r
18621 BFD09940 CBC4 SW S8, 16(SP)
\r
18622 BFD09942 0FDD MOVE S8, SP
\r
18623 BFD09944 0018F89E SW A0, 24(S8)
\r
18624 BFD09948 001CF8BE SW A1, 28(S8)
\r
18625 601: ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
\r
18626 BFD0994C 0018FC9E LW A0, 24(S8)
\r
18627 BFD09950 001CFCBE LW A1, 28(S8)
\r
18628 BFD09954 12B477E8 JALS xEventGroupSetBits
\r
18629 BFD09956 0C0012B4 ADDI S5, S4, 3072
\r
18630 BFD09958 0C00 NOP
\r
18632 BFD0995A 0FBE MOVE SP, S8
\r
18633 BFD0995C 4BE5 LW RA, 20(SP)
\r
18634 BFD0995E 4BC4 LW S8, 16(SP)
\r
18635 BFD09960 4C0D ADDIU SP, SP, 24
\r
18636 BFD09962 459F JR16 RA
\r
18637 BFD09964 0C00 NOP
\r
18638 603: /*-----------------------------------------------------------*/
\r
18640 605: /* For internal use only - execute a 'clear bits' command that was pended from
\r
18641 606: an interrupt. */
\r
18642 607: void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
\r
18644 BFD09968 4FF5 ADDIU SP, SP, -24
\r
18645 BFD0996A CBE5 SW RA, 20(SP)
\r
18646 BFD0996C CBC4 SW S8, 16(SP)
\r
18647 BFD0996E 0FDD MOVE S8, SP
\r
18648 BFD09970 0018F89E SW A0, 24(S8)
\r
18649 BFD09974 001CF8BE SW A1, 28(S8)
\r
18650 609: ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
\r
18651 BFD09978 0018FC9E LW A0, 24(S8)
\r
18652 BFD0997C 001CFCBE LW A1, 28(S8)
\r
18653 BFD09980 352277E8 JALS xEventGroupClearBits
\r
18654 BFD09982 0C003522 LHU T1, 3072(V0)
\r
18655 BFD09984 0C00 NOP
\r
18657 BFD09986 0FBE MOVE SP, S8
\r
18658 BFD09988 4BE5 LW RA, 20(SP)
\r
18659 BFD0998A 4BC4 LW S8, 16(SP)
\r
18660 BFD0998C 4C0D ADDIU SP, SP, 24
\r
18661 BFD0998E 459F JR16 RA
\r
18662 BFD09990 0C00 NOP
\r
18663 611: /*-----------------------------------------------------------*/
\r
18665 613: static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
\r
18667 BFD080F4 4FF9 ADDIU SP, SP, -16
\r
18668 BFD080F6 CBC3 SW S8, 12(SP)
\r
18669 BFD080F8 0FDD MOVE S8, SP
\r
18670 BFD080FA 0010F89E SW A0, 16(S8)
\r
18671 BFD080FE 0014F8BE SW A1, 20(S8)
\r
18672 BFD08102 0018F8DE SW A2, 24(S8)
\r
18673 615: BaseType_t xWaitConditionMet = pdFALSE;
\r
18674 BFD08106 0000F81E SW ZERO, 0(S8)
\r
18676 617: if( xWaitForAllBits == pdFALSE )
\r
18677 BFD0810A 0018FC5E LW V0, 24(S8)
\r
18678 BFD0810E 000C40A2 BNEZC V0, 0xBFD0812A
\r
18680 619: /* Task only has to wait for one bit within uxBitsToWaitFor to be
\r
18681 620: set. Is one already set? */
\r
18682 621: if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
\r
18683 BFD08112 0010FC7E LW V1, 16(S8)
\r
18684 BFD08116 0014FC5E LW V0, 20(S8)
\r
18685 BFD0811A 4493 AND16 V0, V1
\r
18686 BFD0811C 001240E2 BEQZC V0, 0xBFD08144
\r
18688 623: xWaitConditionMet = pdTRUE;
\r
18689 BFD08120 ED01 LI V0, 1
\r
18690 BFD08122 0000F85E SW V0, 0(S8)
\r
18691 BFD08126 CC0E B 0xBFD08144
\r
18692 BFD08128 0C00 NOP
\r
18696 627: mtCOVERAGE_TEST_MARKER();
\r
18701 632: /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
\r
18702 633: Are they set already? */
\r
18703 634: if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
\r
18704 BFD0812A 0010FC7E LW V1, 16(S8)
\r
18705 BFD0812E 0014FC5E LW V0, 20(S8)
\r
18706 BFD08132 449A AND16 V1, V0
\r
18707 BFD08134 0014FC5E LW V0, 20(S8)
\r
18708 BFD08138 0004B443 BNE V1, V0, 0xBFD08144
\r
18709 BFD0813A 0C000004 SLL ZERO, A0, 1
\r
18710 BFD0813C 0C00 NOP
\r
18712 636: xWaitConditionMet = pdTRUE;
\r
18713 BFD0813E ED01 LI V0, 1
\r
18714 BFD08140 0000F85E SW V0, 0(S8)
\r
18718 640: mtCOVERAGE_TEST_MARKER();
\r
18722 644: return xWaitConditionMet;
\r
18723 BFD08144 0000FC5E LW V0, 0(S8)
\r
18725 BFD08148 0FBE MOVE SP, S8
\r
18726 BFD0814A 4BC3 LW S8, 12(SP)
\r
18727 BFD0814C 4C09 ADDIU SP, SP, 16
\r
18728 BFD0814E 459F JR16 RA
\r
18729 BFD08150 0C00 NOP
\r
18730 646: /*-----------------------------------------------------------*/
\r
18732 648: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
\r
18734 650: BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
\r
18736 652: BaseType_t xReturn;
\r
18738 654: traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
\r
18739 655: xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
\r
18741 657: return xReturn;
\r
18745 661: /*-----------------------------------------------------------*/
\r
18747 663: #if (configUSE_TRACE_FACILITY == 1)
\r
18749 665: UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
\r
18751 667: UBaseType_t xReturn;
\r
18752 668: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
\r
18754 670: if( xEventGroup == NULL )
\r
18756 672: xReturn = 0;
\r
18760 676: xReturn = pxEventBits->uxEventGroupNumber;
\r
18763 679: return xReturn;
\r
18768 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/on_reset.c
\r
18769 1: /*****************************************************************************
\r
18770 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
18771 3: * You may use this software and any derivatives exclusively with
\r
18772 4: * Microchip products.
\r
18773 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
18774 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
18775 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
18776 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
18777 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
18778 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
18779 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
18780 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
18781 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
18782 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
18783 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
18784 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
18785 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
18786 18: * OF THESE TERMS.
\r
18787 19: *****************************************************************************/
\r
18789 21: /** @file on_reset.c
\r
18790 22: *MEC14xx XC32 M14K Startup code _on_reset handler
\r
18792 24: /** @defgroup MEC14xx Startup
\r
18797 29: #include "appcfg.h"
\r
18798 30: #include "platform.h"
\r
18799 31: #include "MEC14xx/mec14xx.h"
\r
18800 32: #include "MEC14xx/mec14xx_pcr.h"
\r
18803 35: * From linker command file
\r
18805 37: extern uint32_t _ebase_address[];
\r
18808 40: /** _on_reset - Very early HW initialization.
\r
18809 41: * @note XC32 startup code has initialized SP & GP. No other
\r
18810 42: * C features have been initialized (before .bss clear and
\r
18811 43: * global data init.) NOTE: MIPS M14K is still in Boot-Strap
\r
18812 44: * mode and EBASE has not been programmed. Any exception or
\r
18813 45: * interrupts will vector to the BEV Exception handler!
\r
18816 48: __attribute__((nomips16)) _on_reset (void)
\r
18818 BFD091CC 4FB0 ADDIU SP, SP, -8
\r
18819 BFD091CE CBC1 SW S8, 4(SP)
\r
18820 BFD091D0 0FDD MOVE S8, SP
\r
18821 50: /* Enable JTAG */
\r
18822 51: ECS_REG->JTAG_ENABLE |= 1u;
\r
18823 BFD091D2 A00041A2 LUI V0, 0xA000
\r
18824 BFD091D6 FC205042 ORI V0, V0, -992
\r
18825 BFD091D8 41A3FC20 LW AT, 16803(ZERO)
\r
18826 BFD091DA A00041A3 LUI V1, 0xA000
\r
18827 BFD091DE FC205063 ORI V1, V1, -992
\r
18828 BFD091E0 69B0FC20 LW AT, 27056(ZERO)
\r
18829 BFD091E2 69B0 LW V1, 0(V1)
\r
18830 BFD091E4 00015063 ORI V1, V1, 1
\r
18831 BFD091E8 E9A0 SW V1, 0(V0)
\r
18833 53: /* Disable WDT */
\r
18834 54: WDT->CONTROL = 0u;
\r
18835 BFD091EA A00041A2 LUI V0, 0xA000
\r
18836 BFD091EE 04005042 ORI V0, V0, 1024
\r
18837 BFD091F0 0400 ADDU S0, S0, S0
\r
18838 BFD091F2 8824 SB S0, 4(V0)
\r
18840 56: /* Set CPU clock divider specified in appcfg.h */
\r
18841 57: PCR->PROC_CLOCK_CNTRL = ( PCR_CLOCK_DIVIDER );
\r
18842 BFD091F4 A00841A2 LUI V0, 0xA008
\r
18843 BFD091F8 01005042 ORI V0, V0, 256
\r
18844 BFD091FC ED81 LI V1, 1
\r
18845 BFD091FE E9A8 SW V1, 32(V0)
\r
18847 BFD09200 18000000 SLL ZERO, ZERO, 3
\r
18848 BFD09202 00001800 SB ZERO, 0(ZERO)
\r
18850 BFD09204 08000000 SSNOP
\r
18851 BFD09206 0800 LBU S0, 0(S0)
\r
18854 BFD09208 0FBE MOVE SP, S8
\r
18855 BFD0920A 4BC1 LW S8, 4(SP)
\r
18856 BFD0920C 459F JR16 RA
\r
18857 BFD0920E 4C05 ADDIU SP, SP, 8
\r
18860 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/default-on-bootstrap.c
\r
18861 1: /*********************************************************************
\r
18863 3: * Default _on_bootstrap Implementation
\r
18865 5: *********************************************************************
\r
18866 6: * Filename: default-on-bootstrap.c
\r
18868 8: * Processor: PIC32
\r
18870 10: * Compiler: MPLAB C Compiler for PIC32 MCUs
\r
18872 12: * Company: Microchip Technology Inc.
\r
18874 14: * Software License Agreement
\r
18876 16: * The software supplied herewith by Microchip Technology Incorporated
\r
18877 17: * (the 'Company') for its PIC32/PIC24F Microcontroller is intended
\r
18878 18: * and supplied to you, the Company's customer, for use solely and
\r
18879 19: * exclusively on Microchip PIC32/PIC24F Microcontroller products.
\r
18880 20: * The software is owned by the Company and/or its supplier, and is
\r
18881 21: * protected under applicable copyright laws. All rights are reserved.
\r
18882 22: * Any use in violation of the foregoing restrictions may subject the
\r
18883 23: * user to criminal sanctions under applicable laws, as well as to
\r
18884 24: * civil liability for the breach of the terms and conditions of this
\r
18887 27: * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
\r
18888 28: * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
\r
18889 29: * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
\r
18890 30: * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
\r
18891 31: * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
\r
18892 32: * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
18894 34: ********************************************************************/
\r
18895 35: /* This is a default definition of an _on_bootstrap() function.
\r
18896 36: * It does nothing and just goes returns. If the user
\r
18897 37: * application supplies a handler function, this function will not be
\r
18898 38: * referenced and thus not pulled in from the library.
\r
18901 41: _on_bootstrap (void)
\r
18903 BFD09EE4 4FB0 ADDIU SP, SP, -8
\r
18904 BFD09EE6 CBC1 SW S8, 4(SP)
\r
18905 BFD09EE8 0FDD MOVE S8, SP
\r
18907 BFD09EEA 0FBE MOVE SP, S8
\r
18908 BFD09EEC 4BC1 LW S8, 4(SP)
\r
18909 BFD09EEE 4C05 ADDIU SP, SP, 8
\r
18910 BFD09EF0 459F JR16 RA
\r
18911 BFD09EF2 0C00 NOP
\r
18912 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_timers.c -------
\r
18913 1: /*****************************************************************************
\r
18914 2: * © 2014 Microchip Technology Inc. and its subsidiaries.
\r
18915 3: * You may use this software and any derivatives exclusively with
\r
18916 4: * Microchip products.
\r
18917 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
18918 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
18919 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
18920 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
18921 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
18922 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
18923 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
18924 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
18925 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
18926 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
18927 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
18928 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
18929 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
18930 18: * OF THESE TERMS.
\r
18931 19: *****************************************************************************/
\r
18934 22: /** @file mec14xx_timers.c
\r
18935 23: *MEC14xx Timers
\r
18937 25: /** @defgroup MEC14xx Peripherals Timers
\r
18942 30: #include "appcfg.h"
\r
18943 31: #include "platform.h"
\r
18944 32: #include "MEC14xx/mec14xx.h"
\r
18945 33: #include "MEC14xx/mec14xx_pcr.h"
\r
18946 34: #include "MEC14xx/mec14xx_timers.h"
\r
18949 37: // pairs of bytes (sleep reg, bit position)
\r
18950 38: // sleep reg = 0 for EC_SLEEP_EN or 1 for EC_SLEEP_EN2
\r
18952 40: struct btmr_sleep_info_s {
\r
18953 41: uint8_t slp_reg;
\r
18954 42: uint8_t bit_pos;
\r
18957 45: static const struct btmr_sleep_info_s btmr_slp_info[BTMR_MAX_INSTANCE] = {
\r
18958 46: { 0, PCR_EC_TIMER0_SLP_BITPOS },
\r
18959 47: { 0, PCR_EC_TIMER1_SLP_BITPOS },
\r
18960 48: { 1, PCR_EC2_TIMER2_SLP_BITPOS },
\r
18961 49: { 1, PCR_EC2_TIMER3_SLP_BITPOS }
\r
18965 53: #ifdef MEC14XX_BTIMER_CHECK_ID
\r
18968 56: * tmr_valid - Local helper that checks if logical Timer ID is
\r
18971 59: * @author sworley
\r
18973 61: * @param tmr_id 0-based Timer ID
\r
18975 63: * @return uint8_t Non-zero(VALID), 0(Invalid)
\r
18977 65: static uint8_t btmr_valid(uint8_t tmr_id)
\r
18979 BFD09A44 4FB0 ADDIU SP, SP, -8
\r
18980 BFD09A46 CBC1 SW S8, 4(SP)
\r
18981 BFD09A48 0FDD MOVE S8, SP
\r
18982 BFD09A4A 0C44 MOVE V0, A0
\r
18983 BFD09A4C 0008185E SB V0, 8(S8)
\r
18984 67: if ( tmr_id < (BTMR_ID_MAX ) ) {
\r
18985 BFD09A50 0008145E LBU V0, 8(S8)
\r
18986 BFD09A54 0004B042 SLTIU V0, V0, 4
\r
18987 BFD09A58 000340E2 BEQZC V0, 0xBFD09A62
\r
18989 BFD09A5C ED01 LI V0, 1
\r
18990 BFD09A5E CC02 B 0xBFD09A64
\r
18991 BFD09A60 0C00 NOP
\r
18993 70: return false;
\r
18994 BFD09A62 0C40 MOVE V0, ZERO
\r
18996 BFD09A64 0FBE MOVE SP, S8
\r
18997 BFD09A66 4BC1 LW S8, 4(SP)
\r
18998 BFD09A68 4C05 ADDIU SP, SP, 8
\r
18999 BFD09A6A 459F JR16 RA
\r
19000 BFD09A6C 0C00 NOP
\r
19005 76: * @brief - This version of tmr_valid skips checking always
\r
19006 77: * returning TRUE. Compiler may optimize it out.
\r
19009 80: static uint8_t btmr_valid(uint8_t tmr_id)
\r
19011 82: (void) tmr_id;
\r
19012 83: return true;
\r
19017 88: uint32_t btmr_get_hw_addr(uint8_t btmr_id)
\r
19019 BFD09A70 4FB0 ADDIU SP, SP, -8
\r
19020 BFD09A72 CBC1 SW S8, 4(SP)
\r
19021 BFD09A74 0FDD MOVE S8, SP
\r
19022 BFD09A76 0C44 MOVE V0, A0
\r
19023 BFD09A78 0008185E SB V0, 8(S8)
\r
19024 90: return (uint32_t)(BTMR0_BASE) +
\r
19025 BFD09A82 A00041A2 LUI V0, 0xA000
\r
19026 BFD09A86 0C005042 ORI V0, V0, 3072
\r
19027 BFD09A88 0C00 NOP
\r
19028 BFD09A8A 0526 ADDU V0, V1, V0
\r
19029 91: ((uint32_t)(btmr_id) << (BTMR_INSTANCE_BITPOS));
\r
19030 BFD09A7C 0008145E LBU V0, 8(S8)
\r
19031 BFD09A80 25AA SLL V1, V0, 5
\r
19033 BFD09A8C 0FBE MOVE SP, S8
\r
19034 BFD09A8E 4BC1 LW S8, 4(SP)
\r
19035 BFD09A90 4C05 ADDIU SP, SP, 8
\r
19036 BFD09A92 459F JR16 RA
\r
19037 BFD09A94 0C00 NOP
\r
19040 95: * btmr_sleep_en - Enable/Disable clock gating on idle of a
\r
19043 98: * @author sworley (8/16/2013)
\r
19045 100: * @param tmr_id zero based timer ID.
\r
19046 101: * @param pwr_on boolean true=ON, false=OFF
\r
19048 103: void btmr_sleep_en(uint8_t tmr_id, uint8_t sleep_en)
\r
19050 BFD05DC0 4FF1 ADDIU SP, SP, -32
\r
19051 BFD05DC2 CBE7 SW RA, 28(SP)
\r
19052 BFD05DC4 CBC6 SW S8, 24(SP)
\r
19053 BFD05DC6 0FDD MOVE S8, SP
\r
19054 BFD05DC8 0C64 MOVE V1, A0
\r
19055 BFD05DCA 0C45 MOVE V0, A1
\r
19056 BFD05DCC 0020187E SB V1, 32(S8)
\r
19057 BFD05DD0 0024185E SB V0, 36(S8)
\r
19058 105: uint32_t sleep_mask;
\r
19059 106: uint32_t volatile * p;
\r
19061 108: sleep_mask = 0ul;
\r
19062 BFD05DD4 0014F81E SW ZERO, 20(S8)
\r
19063 109: if ( btmr_valid(tmr_id) ) {
\r
19064 BFD05DD8 0020145E LBU V0, 32(S8)
\r
19065 BFD05DDC 0C82 MOVE A0, V0
\r
19066 BFD05DDE 4D2277E8 JALS btmr_valid
\r
19067 BFD05DE0 4D22 ADDIU T1, T1, 1
\r
19068 BFD05DE2 0C00 NOP
\r
19069 BFD05DE4 004040E2 BEQZC V0, 0xBFD05E68
\r
19070 110: if (btmr_slp_info[tmr_id].slp_reg) {
\r
19071 BFD05DE8 0020147E LBU V1, 32(S8)
\r
19072 BFD05DEC BFD141A2 LUI V0, 0xBFD1
\r
19073 BFD05DEE 25B2BFD1 LDC1 F30, 9650(S1)
\r
19074 BFD05DF0 25B2 SLL V1, V1, 1
\r
19075 BFD05DF2 9F243042 ADDIU V0, V0, -24796
\r
19076 BFD05DF4 05269F24 LWC1 F25, 1318(A0)
\r
19077 BFD05DF6 0526 ADDU V0, V1, V0
\r
19078 BFD05DF8 0920 LBU V0, 0(V0)
\r
19079 BFD05DFA 000840E2 BEQZC V0, 0xBFD05E0E
\r
19080 111: p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN2);
\r
19081 BFD05DFE A00841A2 LUI V0, 0xA008
\r
19082 BFD05E02 01245042 ORI V0, V0, 292
\r
19083 BFD05E06 0010F85E SW V0, 16(S8)
\r
19084 BFD05E08 CC070010 BREAK
\r
19085 BFD05E0A CC07 B 0xBFD05E1A
\r
19086 BFD05E0C 0C00 NOP
\r
19088 113: p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN);
\r
19089 BFD05E0E A00841A2 LUI V0, 0xA008
\r
19090 BFD05E12 01085042 ORI V0, V0, 264
\r
19091 BFD05E16 0010F85E SW V0, 16(S8)
\r
19093 115: sleep_mask = (1ul << btmr_slp_info[tmr_id].bit_pos);
\r
19094 BFD05E1A 0020147E LBU V1, 32(S8)
\r
19095 BFD05E1E BFD141A2 LUI V0, 0xBFD1
\r
19096 BFD05E20 25B2BFD1 LDC1 F30, 9650(S1)
\r
19097 BFD05E22 25B2 SLL V1, V1, 1
\r
19098 BFD05E24 9F243042 ADDIU V0, V0, -24796
\r
19099 BFD05E26 05269F24 LWC1 F25, 1318(A0)
\r
19100 BFD05E28 0526 ADDU V0, V1, V0
\r
19101 BFD05E2A 0921 LBU V0, 1(V0)
\r
19102 BFD05E2C ED81 LI V1, 1
\r
19103 BFD05E2E 10100062 SLLV V0, V0, V1
\r
19104 BFD05E30 F85E1010 ADDI ZERO, S0, -1954
\r
19105 BFD05E32 0014F85E SW V0, 20(S8)
\r
19106 116: if (sleep_en) {
\r
19107 BFD05E36 0024145E LBU V0, 36(S8)
\r
19108 BFD05E3A 000B40E2 BEQZC V0, 0xBFD05E54
\r
19109 117: *p |= (sleep_mask);
\r
19110 BFD05E3E 0010FC5E LW V0, 16(S8)
\r
19111 BFD05E42 69A0 LW V1, 0(V0)
\r
19112 BFD05E44 0014FC5E LW V0, 20(S8)
\r
19113 BFD05E48 44DA OR16 V1, V0
\r
19114 BFD05E4A 0010FC5E LW V0, 16(S8)
\r
19115 BFD05E4E E9A0 SW V1, 0(V0)
\r
19116 BFD05E50 CC0B B 0xBFD05E68
\r
19117 BFD05E52 0C00 NOP
\r
19119 119: *p &= ~(sleep_mask);
\r
19120 BFD05E54 0010FC5E LW V0, 16(S8)
\r
19121 BFD05E58 69A0 LW V1, 0(V0)
\r
19122 BFD05E5A 0014FC5E LW V0, 20(S8)
\r
19123 BFD05E5E 4412 NOT16 V0, V0
\r
19124 BFD05E60 449A AND16 V1, V0
\r
19125 BFD05E62 0010FC5E LW V0, 16(S8)
\r
19126 BFD05E66 E9A0 SW V1, 0(V0)
\r
19130 BFD05E68 0FBE MOVE SP, S8
\r
19131 BFD05E6A 4BE7 LW RA, 28(SP)
\r
19132 BFD05E6C 4BC6 LW S8, 24(SP)
\r
19133 BFD05E6E 4C11 ADDIU SP, SP, 32
\r
19134 BFD05E70 459F JR16 RA
\r
19135 BFD05E72 0C00 NOP
\r
19138 125: * btmr_reset - Peform soft reset of specified timer.
\r
19140 127: * @author sworley
\r
19142 129: * @param tmr_id 0-based Timer ID
\r
19143 130: * @note Soft reset set all registers to POR values.
\r
19144 131: * Spins 256 times waiting on hardware to clear reset bit.
\r
19146 133: void btmr_reset(uint8_t tmr_id)
\r
19148 BFD07988 4FF1 ADDIU SP, SP, -32
\r
19149 BFD0798A CBE7 SW RA, 28(SP)
\r
19150 BFD0798C CBC6 SW S8, 24(SP)
\r
19151 BFD0798E 0FDD MOVE S8, SP
\r
19152 BFD07990 0C44 MOVE V0, A0
\r
19153 BFD07992 0020185E SB V0, 32(S8)
\r
19154 135: BTMR_TypeDef * p;
\r
19155 136: uint32_t wait_cnt;
\r
19157 138: if (btmr_valid(tmr_id)) {
\r
19158 BFD07996 0020145E LBU V0, 32(S8)
\r
19159 BFD0799A 0C82 MOVE A0, V0
\r
19160 BFD0799C 4D2277E8 JALS btmr_valid
\r
19161 BFD0799E 4D22 ADDIU T1, T1, 1
\r
19162 BFD079A0 0C00 NOP
\r
19163 BFD079A2 002540E2 BEQZC V0, 0xBFD079F0
\r
19164 139: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19165 BFD079A6 0020145E LBU V0, 32(S8)
\r
19166 BFD079AA 0C82 MOVE A0, V0
\r
19167 BFD079AC 4D3877E8 JALS btmr_get_hw_addr
\r
19168 BFD079AE 4D38 ADDIU T1, T1, -4
\r
19169 BFD079B0 0C00 NOP
\r
19170 BFD079B2 0014F85E SW V0, 20(S8)
\r
19172 141: p->CONTROL = (BTMR_CNTL_SOFT_RESET);
\r
19173 BFD079B6 0014FC5E LW V0, 20(S8)
\r
19174 BFD079B8 ED900014 SUB SP, S4, ZERO
\r
19175 BFD079BA ED90 LI V1, 16
\r
19176 BFD079BC E9A4 SW V1, 16(V0)
\r
19178 143: wait_cnt = 256ul;
\r
19179 BFD079BE 01003040 ADDIU V0, ZERO, 256
\r
19180 BFD079C2 0010F85E SW V0, 16(S8)
\r
19182 145: if ( 0ul == (p->CONTROL & BTMR_CNTL_SOFT_RESET) ) {
\r
19183 BFD079C6 0014FC5E LW V0, 20(S8)
\r
19184 BFD079CA 6924 LW V0, 16(V0)
\r
19185 BFD079CC 2D28 ANDI V0, V0, 0x10
\r
19186 BFD079CE 000E40E2 BEQZC V0, 0xBFD079EE
\r
19188 BFD079EE 0C00 NOP
\r
19191 149: while ( wait_cnt-- );
\r
19192 BFD079D2 0010FC5E LW V0, 16(S8)
\r
19193 BFD079D4 00400010 SRL ZERO, S0, 0
\r
19194 BFD079D6 13900040 SLTU V0, ZERO, V0
\r
19195 BFD079D8 2D2D1390 ADDI GP, S0, 11565
\r
19196 BFD079DA 2D2D ANDI V0, V0, 0xFF
\r
19197 BFD079DC 0010FC7E LW V1, 16(S8)
\r
19198 BFD079E0 6DBE ADDIU V1, V1, -1
\r
19199 BFD079E2 0010F87E SW V1, 16(S8)
\r
19200 BFD079E6 FFEE40A2 BNEZC V0, 0xBFD079C6
\r
19201 BFD079E8 CC02FFEE LW RA, -13310(T6)
\r
19202 BFD079EA CC02 B 0xBFD079F0
\r
19203 BFD079EC 0C00 NOP
\r
19206 BFD079F0 0FBE MOVE SP, S8
\r
19207 BFD079F2 4BE7 LW RA, 28(SP)
\r
19208 BFD079F4 4BC6 LW S8, 24(SP)
\r
19209 BFD079F6 4C11 ADDIU SP, SP, 32
\r
19210 BFD079F8 459F JR16 RA
\r
19211 BFD079FA 0C00 NOP
\r
19214 154: * btmr_init - Initialize specified timer
\r
19215 155: * @param zero based timer ID
\r
19216 156: * @param tmr_cntl b[15:0] = timer configuration flags.
\r
19217 157: * @param initial_count
\r
19218 158: * @param preload_count
\r
19219 159: * @note performs a soft reset of the timer before
\r
19220 160: * configuration.
\r
19222 162: void btmr_init(uint8_t tmr_id,
\r
19223 163: uint16_t tmr_cntl,
\r
19224 164: uint16_t prescaler,
\r
19225 165: uint32_t initial_count,
\r
19226 166: uint32_t preload_count)
\r
19228 BFD056FC 4FF1 ADDIU SP, SP, -32
\r
19229 BFD056FE CBE7 SW RA, 28(SP)
\r
19230 BFD05700 CBC6 SW S8, 24(SP)
\r
19231 BFD05702 0FDD MOVE S8, SP
\r
19232 BFD05704 0C65 MOVE V1, A1
\r
19233 BFD05706 0C46 MOVE V0, A2
\r
19234 BFD05708 002CF8FE SW A3, 44(S8)
\r
19235 BFD0570C 0020189E SB A0, 32(S8)
\r
19236 BFD05710 0024387E SH V1, 36(S8)
\r
19237 BFD05714 0028385E SH V0, 40(S8)
\r
19238 168: BTMR_TypeDef * pTMR;
\r
19240 170: pTMR = NULL;
\r
19241 BFD05718 0010F81E SW ZERO, 16(S8)
\r
19243 172: if (btmr_valid(tmr_id)) {
\r
19244 BFD0571C 0020145E LBU V0, 32(S8)
\r
19245 BFD05720 0C82 MOVE A0, V0
\r
19246 BFD05722 4D2277E8 JALS btmr_valid
\r
19247 BFD05724 4D22 ADDIU T1, T1, 1
\r
19248 BFD05726 0C00 NOP
\r
19249 BFD05728 004840E2 BEQZC V0, 0xBFD057BC
\r
19250 173: btmr_reset(tmr_id);
\r
19251 BFD0572C 0020145E LBU V0, 32(S8)
\r
19252 BFD05730 0C82 MOVE A0, V0
\r
19253 BFD05732 3CC477E8 JALS btmr_reset
\r
19254 BFD05734 0C003CC4 LH A2, 3072(A0)
\r
19255 BFD05736 0C00 NOP
\r
19257 175: pTMR = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19258 BFD05738 0020145E LBU V0, 32(S8)
\r
19259 BFD0573C 0C82 MOVE A0, V0
\r
19260 BFD0573E 4D3877E8 JALS btmr_get_hw_addr
\r
19261 BFD05740 4D38 ADDIU T1, T1, -4
\r
19262 BFD05742 0C00 NOP
\r
19263 BFD05744 0010F85E SW V0, 16(S8)
\r
19265 177: // Ungate timer clocks and program prescale
\r
19266 178: pTMR->CONTROL = ((uint32_t)prescaler << 16) + (BTMR_CNTL_ENABLE);
\r
19267 BFD05748 0028345E LHU V0, 40(S8)
\r
19268 BFD0574C 80000042 SLL V0, V0, 16
\r
19269 BFD05750 6DA0 ADDIU V1, V0, 1
\r
19270 BFD05752 0010FC5E LW V0, 16(S8)
\r
19271 BFD05756 E9A4 SW V1, 16(V0)
\r
19273 180: // Program Preload & initial counter value
\r
19274 181: pTMR->PRELOAD = preload_count;
\r
19275 BFD05758 0010FC5E LW V0, 16(S8)
\r
19276 BFD0575C 0030FC7E LW V1, 48(S8)
\r
19277 BFD05760 E9A1 SW V1, 4(V0)
\r
19278 182: pTMR->COUNT = initial_count;
\r
19279 BFD05762 0010FC5E LW V0, 16(S8)
\r
19280 BFD05766 002CFC7E LW V1, 44(S8)
\r
19281 BFD0576A E9A0 SW V1, 0(V0)
\r
19283 184: // Program control register, interrupt enable, and clear status
\r
19284 185: if (tmr_cntl & BTMR_COUNT_UP) {
\r
19285 BFD0576C 0024345E LHU V0, 36(S8)
\r
19286 BFD05770 2D24 ANDI V0, V0, 0x4
\r
19287 BFD05772 000840E2 BEQZC V0, 0xBFD05786
\r
19288 186: pTMR->CONTROL |= BTMR_CNTL_COUNT_UP;
\r
19289 BFD05776 0010FC5E LW V0, 16(S8)
\r
19290 BFD0577A 6924 LW V0, 16(V0)
\r
19291 BFD0577C 00045062 ORI V1, V0, 4
\r
19292 BFD05780 0010FC5E LW V0, 16(S8)
\r
19293 BFD05784 E9A4 SW V1, 16(V0)
\r
19295 188: if (tmr_cntl & BTMR_AUTO_RESTART) {
\r
19296 BFD05786 0024345E LHU V0, 36(S8)
\r
19297 BFD0578A 2D26 ANDI V0, V0, 0x8
\r
19298 BFD0578C 000840E2 BEQZC V0, 0xBFD057A0
\r
19299 189: pTMR->CONTROL |= BTMR_CNTL_AUTO_RESTART;
\r
19300 BFD05790 0010FC5E LW V0, 16(S8)
\r
19301 BFD05794 6924 LW V0, 16(V0)
\r
19302 BFD05796 00085062 ORI V1, V0, 8
\r
19303 BFD0579A 0010FC5E LW V0, 16(S8)
\r
19304 BFD0579E E9A4 SW V1, 16(V0)
\r
19307 192: if (tmr_cntl & BTMR_INT_EN) {
\r
19308 BFD057A0 0024345E LHU V0, 36(S8)
\r
19309 BFD057A4 2D21 ANDI V0, V0, 0x1
\r
19310 BFD057A6 2D2D ANDI V0, V0, 0xFF
\r
19311 BFD057A8 000840E2 BEQZC V0, 0xBFD057BC
\r
19312 193: pTMR->INTEN = 0x01u; // enable first
\r
19313 BFD057AC 0010FC5E LW V0, 16(S8)
\r
19314 BFD057B0 ED81 LI V1, 1
\r
19315 BFD057B2 89AC SB V1, 12(V0)
\r
19316 194: pTMR->STATUS = 0x01u; // clear status
\r
19317 BFD057B4 0010FC5E LW V0, 16(S8)
\r
19318 BFD057B8 ED81 LI V1, 1
\r
19319 BFD057BA 89A8 SB V1, 8(V0)
\r
19323 BFD057BC 0FBE MOVE SP, S8
\r
19324 BFD057BE 4BE7 LW RA, 28(SP)
\r
19325 BFD057C0 4BC6 LW S8, 24(SP)
\r
19326 BFD057C2 4C11 ADDIU SP, SP, 32
\r
19327 BFD057C4 459F JR16 RA
\r
19328 BFD057C6 0C00 NOP
\r
19331 200: * btmr_ien - Enable specified timer's interrupt.
\r
19333 202: * @author sworley
\r
19335 204: * @param tmr_id zero based timer ID.
\r
19336 205: * @param ien Non-zero enable interrupt in timer block, 0
\r
19338 207: * @note Write 0 or 1 to timer's INTEN register.
\r
19340 209: void btmr_ien(uint8_t tmr_id, uint8_t ien)
\r
19342 BFD08330 4FF1 ADDIU SP, SP, -32
\r
19343 BFD08332 CBE7 SW RA, 28(SP)
\r
19344 BFD08334 CBC6 SW S8, 24(SP)
\r
19345 BFD08336 0FDD MOVE S8, SP
\r
19346 BFD08338 0C64 MOVE V1, A0
\r
19347 BFD0833A 0C45 MOVE V0, A1
\r
19348 BFD0833C 0020187E SB V1, 32(S8)
\r
19349 BFD08340 0024185E SB V0, 36(S8)
\r
19350 211: BTMR_TypeDef * p;
\r
19352 213: if (btmr_valid(tmr_id)) {
\r
19353 BFD08344 0020145E LBU V0, 32(S8)
\r
19354 BFD08348 0C82 MOVE A0, V0
\r
19355 BFD0834A 4D2277E8 JALS btmr_valid
\r
19356 BFD0834C 4D22 ADDIU T1, T1, 1
\r
19357 BFD0834E 0C00 NOP
\r
19358 BFD08350 001540E2 BEQZC V0, 0xBFD0837E
\r
19359 214: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19360 BFD08354 0020145E LBU V0, 32(S8)
\r
19361 BFD08358 0C82 MOVE A0, V0
\r
19362 BFD0835A 4D3877E8 JALS btmr_get_hw_addr
\r
19363 BFD0835C 4D38 ADDIU T1, T1, -4
\r
19364 BFD0835E 0C00 NOP
\r
19365 BFD08360 0010F85E SW V0, 16(S8)
\r
19368 BFD08364 0024145E LBU V0, 36(S8)
\r
19369 BFD08368 000640E2 BEQZC V0, 0xBFD08378
\r
19370 217: p->INTEN = (BTMR_INTEN);
\r
19371 BFD0836C 0010FC5E LW V0, 16(S8)
\r
19372 BFD08370 ED81 LI V1, 1
\r
19373 BFD08372 89AC SB V1, 12(V0)
\r
19374 BFD08374 CC04 B 0xBFD0837E
\r
19375 BFD08376 0C00 NOP
\r
19377 219: p->INTEN = (BTMR_INTDIS);
\r
19378 BFD08378 0010FC5E LW V0, 16(S8)
\r
19379 BFD0837A 882C0010 EXT ZERO, S0, 0, 18
\r
19380 BFD0837C 882C SB S0, 12(V0)
\r
19384 BFD0837E 0FBE MOVE SP, S8
\r
19385 BFD08380 4BE7 LW RA, 28(SP)
\r
19386 BFD08382 4BC6 LW S8, 24(SP)
\r
19387 BFD08384 4C11 ADDIU SP, SP, 32
\r
19388 BFD08386 459F JR16 RA
\r
19389 BFD08388 0C00 NOP
\r
19392 225: * tmr_get_clr_ists - Read Timer interrupt status and clear if
\r
19395 228: * @author sworley
\r
19397 230: * @param tmr_id zero based timer ID.
\r
19399 232: * @return uint8_t true (Timer interrupt status set) else false.
\r
19400 233: * @note If timer interrupt status is set then clear it before
\r
19401 234: * returning.
\r
19403 236: uint8_t btmr_get_clr_ists(uint8_t tmr_id)
\r
19405 BFD0838C 4FF1 ADDIU SP, SP, -32
\r
19406 BFD0838E CBE7 SW RA, 28(SP)
\r
19407 BFD08390 CBC6 SW S8, 24(SP)
\r
19408 BFD08392 0FDD MOVE S8, SP
\r
19409 BFD08394 0C44 MOVE V0, A0
\r
19410 BFD08396 0020185E SB V0, 32(S8)
\r
19411 238: BTMR_TypeDef * p;
\r
19414 241: rc = (MEC14XX_FALSE);
\r
19415 BFD0839A 0010181E SB ZERO, 16(S8)
\r
19416 242: if (btmr_valid(tmr_id)) {
\r
19417 BFD0839E 0020145E LBU V0, 32(S8)
\r
19418 BFD083A2 0C82 MOVE A0, V0
\r
19419 BFD083A4 4D2277E8 JALS btmr_valid
\r
19420 BFD083A6 4D22 ADDIU T1, T1, 1
\r
19421 BFD083A8 0C00 NOP
\r
19422 BFD083AA 001540E2 BEQZC V0, 0xBFD083D8
\r
19423 243: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19424 BFD083AE 0020145E LBU V0, 32(S8)
\r
19425 BFD083B2 0C82 MOVE A0, V0
\r
19426 BFD083B4 4D3877E8 JALS btmr_get_hw_addr
\r
19427 BFD083B6 4D38 ADDIU T1, T1, -4
\r
19428 BFD083B8 0C00 NOP
\r
19429 BFD083BA 0014F85E SW V0, 20(S8)
\r
19431 245: if ( p->STATUS ) {
\r
19432 BFD083BE 0014FC5E LW V0, 20(S8)
\r
19433 BFD083C2 0928 LBU V0, 8(V0)
\r
19434 BFD083C4 2D2D ANDI V0, V0, 0xFF
\r
19435 BFD083C6 000740E2 BEQZC V0, 0xBFD083D8
\r
19436 246: p->STATUS = (BTMR_STATUS_ACTIVE);
\r
19437 BFD083CA 0014FC5E LW V0, 20(S8)
\r
19438 BFD083CE ED81 LI V1, 1
\r
19439 BFD083D0 89A8 SB V1, 8(V0)
\r
19441 BFD083D2 ED01 LI V0, 1
\r
19442 BFD083D4 0010185E SB V0, 16(S8)
\r
19446 BFD083D8 0010145E LBU V0, 16(S8)
\r
19448 BFD083DC 0FBE MOVE SP, S8
\r
19449 BFD083DE 4BE7 LW RA, 28(SP)
\r
19450 BFD083E0 4BC6 LW S8, 24(SP)
\r
19451 BFD083E2 4C11 ADDIU SP, SP, 32
\r
19452 BFD083E4 459F JR16 RA
\r
19453 BFD083E6 0C00 NOP
\r
19456 254: * btmr_reload - Force timer to reload counter from preload
\r
19457 255: * register.
\r
19459 257: * @param tmr_id zero based timer ID.
\r
19460 258: * @note Hardware will only reload counter if timer is running.
\r
19462 260: void btmr_reload(uint8_t tmr_id)
\r
19464 BFD086B0 4FF1 ADDIU SP, SP, -32
\r
19465 BFD086B2 CBE7 SW RA, 28(SP)
\r
19466 BFD086B4 CBC6 SW S8, 24(SP)
\r
19467 BFD086B6 0FDD MOVE S8, SP
\r
19468 BFD086B8 0C44 MOVE V0, A0
\r
19469 BFD086BA 0020185E SB V0, 32(S8)
\r
19470 262: BTMR_TypeDef * p;
\r
19472 264: if ( btmr_valid(tmr_id) ) {
\r
19473 BFD086BE 0020145E LBU V0, 32(S8)
\r
19474 BFD086C2 0C82 MOVE A0, V0
\r
19475 BFD086C4 4D2277E8 JALS btmr_valid
\r
19476 BFD086C6 4D22 ADDIU T1, T1, 1
\r
19477 BFD086C8 0C00 NOP
\r
19478 BFD086CA 001640E2 BEQZC V0, 0xBFD086FA
\r
19479 265: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19480 BFD086CE 0020145E LBU V0, 32(S8)
\r
19481 BFD086D2 0C82 MOVE A0, V0
\r
19482 BFD086D4 4D3877E8 JALS btmr_get_hw_addr
\r
19483 BFD086D6 4D38 ADDIU T1, T1, -4
\r
19484 BFD086D8 0C00 NOP
\r
19485 BFD086DA 0010F85E SW V0, 16(S8)
\r
19487 267: if (p->CONTROL & BTMR_CNTL_START) {
\r
19488 BFD086DE 0010FC5E LW V0, 16(S8)
\r
19489 BFD086E2 6924 LW V0, 16(V0)
\r
19490 BFD086E4 2D2A ANDI V0, V0, 0x20
\r
19491 BFD086E6 000840E2 BEQZC V0, 0xBFD086FA
\r
19492 268: p->CONTROL |= BTMR_CNTL_RELOAD;
\r
19493 BFD086EA 0010FC5E LW V0, 16(S8)
\r
19494 BFD086EE 6924 LW V0, 16(V0)
\r
19495 BFD086F0 00405062 ORI V1, V0, 64
\r
19496 BFD086F4 0010FC5E LW V0, 16(S8)
\r
19497 BFD086F8 E9A4 SW V1, 16(V0)
\r
19501 BFD086FA 0FBE MOVE SP, S8
\r
19502 BFD086FC 4BE7 LW RA, 28(SP)
\r
19503 BFD086FE 4BC6 LW S8, 24(SP)
\r
19504 BFD08700 4C11 ADDIU SP, SP, 32
\r
19505 BFD08702 459F JR16 RA
\r
19506 BFD08704 0C00 NOP
\r
19509 274: * btmr_set_count - Program timer's counter register.
\r
19511 276: * @author sworley
\r
19513 278: * @param tmr_id zero based timer ID
\r
19514 279: * @param count new counter value
\r
19515 280: * @note Timer hardware may implement a 16-bit or 32-bit
\r
19516 281: * hardware counter. If the timer is 16-bit only the lower
\r
19517 282: * 16-bits of the count paramter are used.
\r
19519 284: void btmr_set_count(uint8_t tmr_id, uint32_t count)
\r
19521 BFD090FC 4FF1 ADDIU SP, SP, -32
\r
19522 BFD090FE CBE7 SW RA, 28(SP)
\r
19523 BFD09100 CBC6 SW S8, 24(SP)
\r
19524 BFD09102 0FDD MOVE S8, SP
\r
19525 BFD09104 0C44 MOVE V0, A0
\r
19526 BFD09106 0024F8BE SW A1, 36(S8)
\r
19527 BFD0910A 0020185E SB V0, 32(S8)
\r
19528 286: BTMR_TypeDef * p;
\r
19530 288: if (btmr_valid(tmr_id)) {
\r
19531 BFD0910E 0020145E LBU V0, 32(S8)
\r
19532 BFD09112 0C82 MOVE A0, V0
\r
19533 BFD09114 4D2277E8 JALS btmr_valid
\r
19534 BFD09116 4D22 ADDIU T1, T1, 1
\r
19535 BFD09118 0C00 NOP
\r
19536 BFD0911A 000D40E2 BEQZC V0, 0xBFD09138
\r
19537 289: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19538 BFD0911E 0020145E LBU V0, 32(S8)
\r
19539 BFD09122 0C82 MOVE A0, V0
\r
19540 BFD09124 4D3877E8 JALS btmr_get_hw_addr
\r
19541 BFD09126 4D38 ADDIU T1, T1, -4
\r
19542 BFD09128 0C00 NOP
\r
19543 BFD0912A 0010F85E SW V0, 16(S8)
\r
19545 291: p->COUNT = count;
\r
19546 BFD0912E 0010FC5E LW V0, 16(S8)
\r
19547 BFD09132 0024FC7E LW V1, 36(S8)
\r
19548 BFD09136 E9A0 SW V1, 0(V0)
\r
19551 BFD09138 0FBE MOVE SP, S8
\r
19552 BFD0913A 4BE7 LW RA, 28(SP)
\r
19553 BFD0913C 4BC6 LW S8, 24(SP)
\r
19554 BFD0913E 4C11 ADDIU SP, SP, 32
\r
19555 BFD09140 459F JR16 RA
\r
19556 BFD09142 0C00 NOP
\r
19559 296: * btmr_count - Return current value of timer's count register.
\r
19561 298: * @author sworley
\r
19563 300: * @param tmr_id zero based timer ID.
\r
19565 302: * @return uint32_t timer count may be 32 or 16 bits depending
\r
19566 303: * upon the hardware. On MEC1322 Timers 0-3 are 16-bit
\r
19567 304: * and Timers 4-5 are 32-bit.
\r
19569 306: uint32_t btmr_count(uint8_t tmr_id)
\r
19571 BFD08D40 4FF1 ADDIU SP, SP, -32
\r
19572 BFD08D42 CBE7 SW RA, 28(SP)
\r
19573 BFD08D44 CBC6 SW S8, 24(SP)
\r
19574 BFD08D46 0FDD MOVE S8, SP
\r
19575 BFD08D48 0C44 MOVE V0, A0
\r
19576 BFD08D4A 0020185E SB V0, 32(S8)
\r
19577 308: BTMR_TypeDef * p;
\r
19578 309: uint32_t cnt;
\r
19581 BFD08D4E 0010F81E SW ZERO, 16(S8)
\r
19582 312: if ( btmr_valid(tmr_id) ) {
\r
19583 BFD08D52 0020145E LBU V0, 32(S8)
\r
19584 BFD08D56 0C82 MOVE A0, V0
\r
19585 BFD08D58 4D2277E8 JALS btmr_valid
\r
19586 BFD08D5A 4D22 ADDIU T1, T1, 1
\r
19587 BFD08D5C 0C00 NOP
\r
19588 BFD08D5E 000D40E2 BEQZC V0, 0xBFD08D7C
\r
19589 313: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19590 BFD08D62 0020145E LBU V0, 32(S8)
\r
19591 BFD08D66 0C82 MOVE A0, V0
\r
19592 BFD08D68 4D3877E8 JALS btmr_get_hw_addr
\r
19593 BFD08D6A 4D38 ADDIU T1, T1, -4
\r
19594 BFD08D6C 0C00 NOP
\r
19595 BFD08D6E 0014F85E SW V0, 20(S8)
\r
19596 314: cnt = (uint32_t)(p->COUNT);
\r
19597 BFD08D72 0014FC5E LW V0, 20(S8)
\r
19598 BFD08D76 6920 LW V0, 0(V0)
\r
19599 BFD08D78 0010F85E SW V0, 16(S8)
\r
19603 BFD08D7C 0010FC5E LW V0, 16(S8)
\r
19605 BFD08D80 0FBE MOVE SP, S8
\r
19606 BFD08D82 4BE7 LW RA, 28(SP)
\r
19607 BFD08D84 4BC6 LW S8, 24(SP)
\r
19608 BFD08D86 4C11 ADDIU SP, SP, 32
\r
19609 BFD08D88 459F JR16 RA
\r
19610 BFD08D8A 0C00 NOP
\r
19613 321: * btmr_start - Start timer counting.
\r
19615 323: * @author sworley
\r
19617 325: * @param tmr_id zero based timer ID.
\r
19619 327: void btmr_start(uint8_t btmr_id)
\r
19621 BFD08D8C 4FF1 ADDIU SP, SP, -32
\r
19622 BFD08D8E CBE7 SW RA, 28(SP)
\r
19623 BFD08D90 CBC6 SW S8, 24(SP)
\r
19624 BFD08D92 0FDD MOVE S8, SP
\r
19625 BFD08D94 0C44 MOVE V0, A0
\r
19626 BFD08D96 0020185E SB V0, 32(S8)
\r
19627 329: BTMR_TypeDef * p;
\r
19629 331: if ( btmr_valid(btmr_id) ) {
\r
19630 BFD08D9A 0020145E LBU V0, 32(S8)
\r
19631 BFD08D9E 0C82 MOVE A0, V0
\r
19632 BFD08DA0 4D2277E8 JALS btmr_valid
\r
19633 BFD08DA2 4D22 ADDIU T1, T1, 1
\r
19634 BFD08DA4 0C00 NOP
\r
19635 BFD08DA6 001040E2 BEQZC V0, 0xBFD08DCA
\r
19636 332: p = (BTMR_TypeDef *)btmr_get_hw_addr(btmr_id);
\r
19637 BFD08DAA 0020145E LBU V0, 32(S8)
\r
19638 BFD08DAE 0C82 MOVE A0, V0
\r
19639 BFD08DB0 4D3877E8 JALS btmr_get_hw_addr
\r
19640 BFD08DB2 4D38 ADDIU T1, T1, -4
\r
19641 BFD08DB4 0C00 NOP
\r
19642 BFD08DB6 0010F85E SW V0, 16(S8)
\r
19643 333: p->CONTROL |= BTMR_CNTL_START;
\r
19644 BFD08DBA 0010FC5E LW V0, 16(S8)
\r
19645 BFD08DBE 6924 LW V0, 16(V0)
\r
19646 BFD08DC0 00205062 ORI V1, V0, 32
\r
19647 BFD08DC4 0010FC5E LW V0, 16(S8)
\r
19648 BFD08DC8 E9A4 SW V1, 16(V0)
\r
19651 BFD08DCA 0FBE MOVE SP, S8
\r
19652 BFD08DCC 4BE7 LW RA, 28(SP)
\r
19653 BFD08DCE 4BC6 LW S8, 24(SP)
\r
19654 BFD08DD0 4C11 ADDIU SP, SP, 32
\r
19655 BFD08DD2 459F JR16 RA
\r
19656 BFD08DD4 0C00 NOP
\r
19659 338: * btmr_stop - Stop timer.
\r
19661 340: * @author sworley
\r
19663 342: * @param tmr_id zero based timer ID.
\r
19664 343: * @note When a stopped timer is started again it will reload
\r
19665 344: * the count register from preload value.
\r
19667 346: void btmr_stop(uint8_t tmr_id)
\r
19669 BFD08DD8 4FF1 ADDIU SP, SP, -32
\r
19670 BFD08DDA CBE7 SW RA, 28(SP)
\r
19671 BFD08DDC CBC6 SW S8, 24(SP)
\r
19672 BFD08DDE 0FDD MOVE S8, SP
\r
19673 BFD08DE0 0C44 MOVE V0, A0
\r
19674 BFD08DE2 0020185E SB V0, 32(S8)
\r
19675 348: BTMR_TypeDef * p;
\r
19677 350: if (btmr_valid(tmr_id)) {
\r
19678 BFD08DE6 0020145E LBU V0, 32(S8)
\r
19679 BFD08DEA 0C82 MOVE A0, V0
\r
19680 BFD08DEC 4D2277E8 JALS btmr_valid
\r
19681 BFD08DEE 4D22 ADDIU T1, T1, 1
\r
19682 BFD08DF0 0C00 NOP
\r
19683 BFD08DF2 001140E2 BEQZC V0, 0xBFD08E18
\r
19684 351: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19685 BFD08DF6 0020145E LBU V0, 32(S8)
\r
19686 BFD08DFA 0C82 MOVE A0, V0
\r
19687 BFD08DFC 4D3877E8 JALS btmr_get_hw_addr
\r
19688 BFD08DFE 4D38 ADDIU T1, T1, -4
\r
19689 BFD08E00 0C00 NOP
\r
19690 BFD08E02 0010F85E SW V0, 16(S8)
\r
19691 352: p->CONTROL &= ~(BTMR_CNTL_START);
\r
19692 BFD08E06 0010FC5E LW V0, 16(S8)
\r
19693 BFD08E0A 69A4 LW V1, 16(V0)
\r
19694 BFD08E0C FFDF3040 ADDIU V0, ZERO, -33
\r
19695 BFD08E0E 449AFFDF LW S8, 17562(RA)
\r
19696 BFD08E10 449A AND16 V1, V0
\r
19697 BFD08E12 0010FC5E LW V0, 16(S8)
\r
19698 BFD08E16 E9A4 SW V1, 16(V0)
\r
19701 BFD08E18 0FBE MOVE SP, S8
\r
19702 BFD08E1A 4BE7 LW RA, 28(SP)
\r
19703 BFD08E1C 4BC6 LW S8, 24(SP)
\r
19704 BFD08E1E 4C11 ADDIU SP, SP, 32
\r
19705 BFD08E20 459F JR16 RA
\r
19706 BFD08E22 0C00 NOP
\r
19709 357: * btmr_is_stopped - Return state of timer's START bit.
\r
19711 359: * @author sworley
\r
19713 361: * @param tmr_id zero based timer ID.
\r
19715 363: * @return uint8_t false(timer not started), true(timer started)
\r
19717 365: uint8_t btmr_is_stopped(uint8_t tmr_id)
\r
19719 BFD083E8 4FF1 ADDIU SP, SP, -32
\r
19720 BFD083EA CBE7 SW RA, 28(SP)
\r
19721 BFD083EC CBC6 SW S8, 24(SP)
\r
19722 BFD083EE 0FDD MOVE S8, SP
\r
19723 BFD083F0 0C44 MOVE V0, A0
\r
19724 BFD083F2 0020185E SB V0, 32(S8)
\r
19725 367: BTMR_TypeDef * p;
\r
19728 370: rc = (MEC14XX_TRUE);
\r
19729 BFD083F6 ED01 LI V0, 1
\r
19730 BFD083F8 0010185E SB V0, 16(S8)
\r
19731 371: if (btmr_valid(tmr_id)) {
\r
19732 BFD083FC 0020145E LBU V0, 32(S8)
\r
19733 BFD08400 0C82 MOVE A0, V0
\r
19734 BFD08402 4D2277E8 JALS btmr_valid
\r
19735 BFD08404 4D22 ADDIU T1, T1, 1
\r
19736 BFD08406 0C00 NOP
\r
19737 BFD08408 001340E2 BEQZC V0, 0xBFD08432
\r
19738 372: rc = (MEC14XX_FALSE);
\r
19739 BFD0840C 0010181E SB ZERO, 16(S8)
\r
19740 373: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19741 BFD08410 0020145E LBU V0, 32(S8)
\r
19742 BFD08414 0C82 MOVE A0, V0
\r
19743 BFD08416 4D3877E8 JALS btmr_get_hw_addr
\r
19744 BFD08418 4D38 ADDIU T1, T1, -4
\r
19745 BFD0841A 0C00 NOP
\r
19746 BFD0841C 0014F85E SW V0, 20(S8)
\r
19747 374: if ((p->CONTROL & BTMR_CNTL_START) == 0) {
\r
19748 BFD08420 0014FC5E LW V0, 20(S8)
\r
19749 BFD08424 6924 LW V0, 16(V0)
\r
19750 BFD08426 2D2A ANDI V0, V0, 0x20
\r
19751 BFD08428 000340A2 BNEZC V0, 0xBFD08432
\r
19752 375: rc = (MEC14XX_TRUE);
\r
19753 BFD0842C ED01 LI V0, 1
\r
19754 BFD0842E 0010185E SB V0, 16(S8)
\r
19758 BFD08432 0010145E LBU V0, 16(S8)
\r
19760 BFD08436 0FBE MOVE SP, S8
\r
19761 BFD08438 4BE7 LW RA, 28(SP)
\r
19762 BFD0843A 4BC6 LW S8, 24(SP)
\r
19763 BFD0843C 4C11 ADDIU SP, SP, 32
\r
19764 BFD0843E 459F JR16 RA
\r
19765 BFD08440 0C00 NOP
\r
19769 383: * btmr_halt - Halt timer counting with no reload on unhalt.
\r
19771 385: * @author sworley
\r
19773 387: * @param tmr_id zero based timer ID.
\r
19774 388: * @note A halted timer will not reload the count register when
\r
19775 389: * unhalted, it will continue counting from the current
\r
19776 390: * count value.
\r
19778 392: void btmr_halt(uint8_t tmr_id)
\r
19780 BFD08E24 4FF1 ADDIU SP, SP, -32
\r
19781 BFD08E26 CBE7 SW RA, 28(SP)
\r
19782 BFD08E28 CBC6 SW S8, 24(SP)
\r
19783 BFD08E2A 0FDD MOVE S8, SP
\r
19784 BFD08E2C 0C44 MOVE V0, A0
\r
19785 BFD08E2E 0020185E SB V0, 32(S8)
\r
19786 394: BTMR_TypeDef * p;
\r
19788 396: if ( btmr_valid(tmr_id) ) {
\r
19789 BFD08E32 0020145E LBU V0, 32(S8)
\r
19790 BFD08E36 0C82 MOVE A0, V0
\r
19791 BFD08E38 4D2277E8 JALS btmr_valid
\r
19792 BFD08E3A 4D22 ADDIU T1, T1, 1
\r
19793 BFD08E3C 0C00 NOP
\r
19794 BFD08E3E 001040E2 BEQZC V0, 0xBFD08E62
\r
19795 397: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19796 BFD08E42 0020145E LBU V0, 32(S8)
\r
19797 BFD08E46 0C82 MOVE A0, V0
\r
19798 BFD08E48 4D3877E8 JALS btmr_get_hw_addr
\r
19799 BFD08E4A 4D38 ADDIU T1, T1, -4
\r
19800 BFD08E4C 0C00 NOP
\r
19801 BFD08E4E 0010F85E SW V0, 16(S8)
\r
19802 398: p->CONTROL |= (BTMR_CNTL_HALT);
\r
19803 BFD08E52 0010FC5E LW V0, 16(S8)
\r
19804 BFD08E56 6924 LW V0, 16(V0)
\r
19805 BFD08E58 00805062 ORI V1, V0, 128
\r
19806 BFD08E5C 0010FC5E LW V0, 16(S8)
\r
19807 BFD08E60 E9A4 SW V1, 16(V0)
\r
19810 BFD08E62 0FBE MOVE SP, S8
\r
19811 BFD08E64 4BE7 LW RA, 28(SP)
\r
19812 BFD08E66 4BC6 LW S8, 24(SP)
\r
19813 BFD08E68 4C11 ADDIU SP, SP, 32
\r
19814 BFD08E6A 459F JR16 RA
\r
19815 BFD08E6C 0C00 NOP
\r
19819 404: * btmr_unhalt - Unhalt timer counting.
\r
19821 406: * @author sworley
\r
19823 408: * @param tmr_id zero based timer ID.
\r
19825 410: void btmr_unhalt(uint8_t tmr_id)
\r
19827 BFD08E70 4FF1 ADDIU SP, SP, -32
\r
19828 BFD08E72 CBE7 SW RA, 28(SP)
\r
19829 BFD08E74 CBC6 SW S8, 24(SP)
\r
19830 BFD08E76 0FDD MOVE S8, SP
\r
19831 BFD08E78 0C44 MOVE V0, A0
\r
19832 BFD08E7A 0020185E SB V0, 32(S8)
\r
19833 412: BTMR_TypeDef * p;
\r
19835 414: if ( btmr_valid(tmr_id) ) {
\r
19836 BFD08E7E 0020145E LBU V0, 32(S8)
\r
19837 BFD08E82 0C82 MOVE A0, V0
\r
19838 BFD08E84 4D2277E8 JALS btmr_valid
\r
19839 BFD08E86 4D22 ADDIU T1, T1, 1
\r
19840 BFD08E88 0C00 NOP
\r
19841 BFD08E8A 001140E2 BEQZC V0, 0xBFD08EB0
\r
19842 415: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
\r
19843 BFD08E8E 0020145E LBU V0, 32(S8)
\r
19844 BFD08E92 0C82 MOVE A0, V0
\r
19845 BFD08E94 4D3877E8 JALS btmr_get_hw_addr
\r
19846 BFD08E96 4D38 ADDIU T1, T1, -4
\r
19847 BFD08E98 0C00 NOP
\r
19848 BFD08E9A 0010F85E SW V0, 16(S8)
\r
19849 416: p->CONTROL &= ~(BTMR_CNTL_HALT);
\r
19850 BFD08E9E 0010FC5E LW V0, 16(S8)
\r
19851 BFD08EA2 69A4 LW V1, 16(V0)
\r
19852 BFD08EA4 FF7F3040 ADDIU V0, ZERO, -129
\r
19853 BFD08EA6 449AFF7F LW K1, 17562(RA)
\r
19854 BFD08EA8 449A AND16 V1, V0
\r
19855 BFD08EAA 0010FC5E LW V0, 16(S8)
\r
19856 BFD08EAE E9A4 SW V1, 16(V0)
\r
19859 BFD08EB0 0FBE MOVE SP, S8
\r
19860 BFD08EB2 4BE7 LW RA, 28(SP)
\r
19861 BFD08EB4 4BC6 LW S8, 24(SP)
\r
19862 BFD08EB6 4C11 ADDIU SP, SP, 32
\r
19863 BFD08EB8 459F JR16 RA
\r
19864 BFD08EBA 0C00 NOP
\r
19867 421: /* end mec14xx_timers.c */
\r
19870 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_tfdp.c ---------
\r
19871 1: /*****************************************************************************
\r
19872 2: * © 2014 Microchip Technology Inc. and its subsidiaries.
\r
19873 3: * You may use this software and any derivatives exclusively with
\r
19874 4: * Microchip products.
\r
19875 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
19876 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
19877 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
19878 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
19879 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
19880 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
19881 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
19882 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
19883 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
19884 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
19885 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
19886 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
19887 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
19888 18: * OF THESE TERMS.
\r
19889 19: *****************************************************************************/
\r
19891 21: /** @file mec14xx_tfdp.c
\r
19892 22: *MEC14xx Trace FIFO Data Port hardware access
\r
19894 24: /** @defgroup MEC14xx Peripherals TFDP
\r
19898 28: #include "appcfg.h"
\r
19899 29: #include "platform.h"
\r
19900 30: #include "MEC14xx/mec14xx.h"
\r
19901 31: #include "MEC14xx/mec14xx_pcr.h"
\r
19902 32: #include "MEC14xx/mec14xx_gpio.h"
\r
19903 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
19906 36: #ifdef ENABLE_TFDP_TRACE
\r
19908 38: #undef TFDP_PIN_1
\r
19909 39: #undef TFDP_PIN_2
\r
19912 42: #define TFDP_PIN_1 (GPIO_0116_ID) // Func1 PullUp enabled
\r
19913 43: #define TFDP_PIN_2 (GPIO_0117_ID) // Func1 PullUp enabled
\r
19917 47: static void tfdp_xmit_header(uint16_t nbr)
\r
19919 BFD0906C 4FB0 ADDIU SP, SP, -8
\r
19920 BFD0906E CBC1 SW S8, 4(SP)
\r
19921 BFD09070 0FDD MOVE S8, SP
\r
19922 BFD09072 0C44 MOVE V0, A0
\r
19923 BFD09074 0008385E SH V0, 8(S8)
\r
19924 49: TFDP->DATA = TFDP_FRAME_START;
\r
19925 BFD09078 A00041A2 LUI V0, 0xA000
\r
19926 BFD0907C 8C005042 ORI V0, V0, -29696
\r
19927 BFD0907E 8C00 BEQZ S0, 0xBFD09080
\r
19928 BFD09080 FFFD3060 ADDIU V1, ZERO, -3
\r
19929 BFD09082 89A0FFFD LW RA, -30304(SP)
\r
19930 BFD09084 89A0 SB V1, 0(V0)
\r
19931 50: TFDP_DELAY();
\r
19933 52: TFDP->DATA = (uint8_t)nbr;
\r
19934 BFD09086 A00041A2 LUI V0, 0xA000
\r
19935 BFD0908A 8C005042 ORI V0, V0, -29696
\r
19936 BFD0908C 8C00 BEQZ S0, 0xBFD0908E
\r
19937 BFD0908E 0008347E LHU V1, 8(S8)
\r
19938 BFD09092 2DBD ANDI V1, V1, 0xFF
\r
19939 BFD09094 89A0 SB V1, 0(V0)
\r
19940 53: TFDP_DELAY();
\r
19941 54: TFDP->DATA = (uint8_t)(nbr >> 8);
\r
19942 BFD09096 A00041A2 LUI V0, 0xA000
\r
19943 BFD0909A 8C005042 ORI V0, V0, -29696
\r
19944 BFD0909C 8C00 BEQZ S0, 0xBFD0909E
\r
19945 BFD0909E 0008347E LHU V1, 8(S8)
\r
19946 BFD090A2 25B1 SRL V1, V1, 8
\r
19947 BFD090A4 2DBF ANDI V1, V1, 0xFFFF
\r
19948 BFD090A6 2DBD ANDI V1, V1, 0xFF
\r
19949 BFD090A8 89A0 SB V1, 0(V0)
\r
19950 55: TFDP_DELAY();
\r
19952 BFD090AA 0FBE MOVE SP, S8
\r
19953 BFD090AC 4BC1 LW S8, 4(SP)
\r
19954 BFD090AE 4C05 ADDIU SP, SP, 8
\r
19955 BFD090B0 459F JR16 RA
\r
19956 BFD090B2 0C00 NOP
\r
19959 59: static void tfdp_xmit_hword(uint16_t hword)
\r
19961 BFD09648 4FB0 ADDIU SP, SP, -8
\r
19962 BFD0964A CBC1 SW S8, 4(SP)
\r
19963 BFD0964C 0FDD MOVE S8, SP
\r
19964 BFD0964E 0C44 MOVE V0, A0
\r
19965 BFD09650 0008385E SH V0, 8(S8)
\r
19966 61: TFDP->DATA = (uint8_t)hword;
\r
19967 BFD09654 A00041A2 LUI V0, 0xA000
\r
19968 BFD09658 8C005042 ORI V0, V0, -29696
\r
19969 BFD0965A 8C00 BEQZ S0, 0xBFD0965C
\r
19970 BFD0965C 0008347E LHU V1, 8(S8)
\r
19971 BFD09660 2DBD ANDI V1, V1, 0xFF
\r
19972 BFD09662 89A0 SB V1, 0(V0)
\r
19973 62: TFDP_DELAY();
\r
19974 63: TFDP->DATA = (uint8_t)(hword >> 8);
\r
19975 BFD09664 A00041A2 LUI V0, 0xA000
\r
19976 BFD09668 8C005042 ORI V0, V0, -29696
\r
19977 BFD0966A 8C00 BEQZ S0, 0xBFD0966C
\r
19978 BFD0966C 0008347E LHU V1, 8(S8)
\r
19979 BFD09670 25B1 SRL V1, V1, 8
\r
19980 BFD09672 2DBF ANDI V1, V1, 0xFFFF
\r
19981 BFD09674 2DBD ANDI V1, V1, 0xFF
\r
19982 BFD09676 89A0 SB V1, 0(V0)
\r
19983 64: TFDP_DELAY();
\r
19985 BFD09678 0FBE MOVE SP, S8
\r
19986 BFD0967A 4BC1 LW S8, 4(SP)
\r
19987 BFD0967C 4C05 ADDIU SP, SP, 8
\r
19988 BFD0967E 459F JR16 RA
\r
19989 BFD09680 0C00 NOP
\r
19992 68: static void tfdp_xmit_word(uint32_t word)
\r
19994 BFD08CF4 4FF9 ADDIU SP, SP, -16
\r
19995 BFD08CF6 CBC3 SW S8, 12(SP)
\r
19996 BFD08CF8 0FDD MOVE S8, SP
\r
19997 BFD08CFA 0010F89E SW A0, 16(S8)
\r
20000 72: for (i = 0u; i < 4; i++) {
\r
20001 BFD08CFE 0000181E SB ZERO, 0(S8)
\r
20002 BFD08D02 CC13 B 0xBFD08D2A
\r
20003 BFD08D04 0C00 NOP
\r
20004 BFD08D20 0000145E LBU V0, 0(S8)
\r
20005 BFD08D24 6D20 ADDIU V0, V0, 1
\r
20006 BFD08D26 0000185E SB V0, 0(S8)
\r
20007 BFD08D2A 0000145E LBU V0, 0(S8)
\r
20008 BFD08D2E 0004B042 SLTIU V0, V0, 4
\r
20009 BFD08D32 FFE840A2 BNEZC V0, 0xBFD08D06
\r
20010 BFD08D34 0FBEFFE8 LW RA, 4030(T0)
\r
20011 73: TFDP->DATA = (uint8_t)word;
\r
20012 BFD08D06 A00041A2 LUI V0, 0xA000
\r
20013 BFD08D0A 8C005042 ORI V0, V0, -29696
\r
20014 BFD08D0C 8C00 BEQZ S0, 0xBFD08D0E
\r
20015 BFD08D0E 0010FC7E LW V1, 16(S8)
\r
20016 BFD08D12 2DBD ANDI V1, V1, 0xFF
\r
20017 BFD08D14 89A0 SB V1, 0(V0)
\r
20019 BFD08D16 0010FC5E LW V0, 16(S8)
\r
20020 BFD08D1A 2521 SRL V0, V0, 8
\r
20021 BFD08D1C 0010F85E SW V0, 16(S8)
\r
20022 75: TFDP_DELAY();
\r
20025 BFD08D36 0FBE MOVE SP, S8
\r
20026 BFD08D38 4BC3 LW S8, 12(SP)
\r
20027 BFD08D3A 4C09 ADDIU SP, SP, 16
\r
20028 BFD08D3C 459F JR16 RA
\r
20029 BFD08D3E 0C00 NOP
\r
20033 81: * tfdp_sleep_en - Gate clocks On/Off to TFDP block when idle
\r
20035 83: * @author C21969 (2/4/2014)
\r
20037 85: * @param sleep_en (1=Gate clocks when idle), (0=Do not gate
\r
20038 86: * clocks when idle)
\r
20040 88: void tfdp_sleep_en(uint8_t sleep_en)
\r
20042 BFD088AC 4FB0 ADDIU SP, SP, -8
\r
20043 BFD088AE CBC1 SW S8, 4(SP)
\r
20044 BFD088B0 0FDD MOVE S8, SP
\r
20045 BFD088B2 0C44 MOVE V0, A0
\r
20046 BFD088B4 0008185E SB V0, 8(S8)
\r
20047 90: if ( sleep_en ) {
\r
20048 BFD088B8 0008145E LBU V0, 8(S8)
\r
20049 BFD088BC 000E40E2 BEQZC V0, 0xBFD088DC
\r
20050 91: PCR->EC_SLEEP_EN |= (PCR_EC_TFDP_SLP_CLK);
\r
20051 BFD088C0 A00841A2 LUI V0, 0xA008
\r
20052 BFD088C4 01005042 ORI V0, V0, 256
\r
20053 BFD088C8 A00841A3 LUI V1, 0xA008
\r
20054 BFD088CC 01005063 ORI V1, V1, 256
\r
20055 BFD088D0 69B2 LW V1, 8(V1)
\r
20056 BFD088D2 00805063 ORI V1, V1, 128
\r
20057 BFD088D6 E9A2 SW V1, 8(V0)
\r
20058 BFD088D8 CC0E B 0xBFD088F6
\r
20059 BFD088DA 0C00 NOP
\r
20061 93: PCR->EC_SLEEP_EN &= ~(PCR_EC_TFDP_SLP_CLK);
\r
20062 BFD088DC A00841A2 LUI V0, 0xA008
\r
20063 BFD088E0 01005042 ORI V0, V0, 256
\r
20064 BFD088E4 A00841A3 LUI V1, 0xA008
\r
20065 BFD088E8 01005063 ORI V1, V1, 256
\r
20066 BFD088EC 6A32 LW A0, 8(V1)
\r
20067 BFD088EE FF7F3060 ADDIU V1, ZERO, -129
\r
20068 BFD088F0 449CFF7F LW K1, 17564(RA)
\r
20069 BFD088F2 449C AND16 V1, A0
\r
20070 BFD088F4 E9A2 SW V1, 8(V0)
\r
20073 BFD088F6 0FBE MOVE SP, S8
\r
20074 BFD088F8 4BC1 LW S8, 4(SP)
\r
20075 BFD088FA 4C05 ADDIU SP, SP, 8
\r
20076 BFD088FC 459F JR16 RA
\r
20077 BFD088FE 0C00 NOP
\r
20081 99: * tfdp_enable - Init Trace FIFO Data Port
\r
20082 100: * @param boolean true=enable TFDP, false=disable TFDP
\r
20083 101: * @param boolean true=change TFDP pin configuration.
\r
20084 102: * If TFDP is enabled then GPIO103/104 set to Alt. Func. 1
\r
20085 103: * Else GPIO103/104 set to GPIO input, internal PU enabled.
\r
20088 106: void tfdp_enable(uint8_t en, uint8_t pin_cfg)
\r
20090 BFD032C4 4FF9 ADDIU SP, SP, -16
\r
20091 BFD032C6 CBC3 SW S8, 12(SP)
\r
20092 BFD032C8 0FDD MOVE S8, SP
\r
20093 BFD032CA 0C64 MOVE V1, A0
\r
20094 BFD032CC 0C45 MOVE V0, A1
\r
20095 BFD032CE 0010187E SB V1, 16(S8)
\r
20096 BFD032D2 0014185E SB V0, 20(S8)
\r
20097 108: uint32_t delay;
\r
20100 BFD032D6 0010145E LBU V0, 16(S8)
\r
20101 BFD032DA 007240E2 BEQZC V0, 0xBFD033C2
\r
20103 112: if (pin_cfg) {
\r
20104 BFD032DE 0014145E LBU V0, 20(S8)
\r
20105 BFD032E2 006740E2 BEQZC V0, 0xBFD033B4
\r
20106 113: // Input with AltOut=1 to drive high when switched to output
\r
20107 114: GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16);
\r
20108 BFD032E6 A00841A2 LUI V0, 0xA008
\r
20109 BFD032EA 10005042 ORI V0, V0, 4096
\r
20110 BFD032EC 41A31000 ADDI ZERO, ZERO, 16803
\r
20111 BFD032EE 000141A3 LUI V1, 0x1
\r
20112 BFD032F2 0138F862 SW V1, 312(V0)
\r
20113 115: GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16);
\r
20114 BFD032F6 A00841A2 LUI V0, 0xA008
\r
20115 BFD032FA 10005042 ORI V0, V0, 4096
\r
20116 BFD032FC 41A31000 ADDI ZERO, ZERO, 16803
\r
20117 BFD032FE 000141A3 LUI V1, 0x1
\r
20118 BFD03302 013CF862 SW V1, 316(V0)
\r
20119 BFD03304 3040013C SRL T1, GP, 6
\r
20121 117: delay = 128;
\r
20122 BFD03306 00803040 ADDIU V0, ZERO, 128
\r
20123 BFD0330A 0000F85E SW V0, 0(S8)
\r
20124 118: while ( delay-- )
\r
20125 BFD0330E CC03 B 0xBFD03316
\r
20126 BFD03310 0C00 NOP
\r
20127 BFD03316 0000FC5E LW V0, 0(S8)
\r
20128 BFD03318 00400000 SRL ZERO, ZERO, 0
\r
20129 BFD0331A 13900040 SLTU V0, ZERO, V0
\r
20130 BFD0331C 2D2D1390 ADDI GP, S0, 11565
\r
20131 BFD0331E 2D2D ANDI V0, V0, 0xFF
\r
20132 BFD03320 0000FC7E LW V1, 0(S8)
\r
20133 BFD03324 6DBE ADDIU V1, V1, -1
\r
20134 BFD03326 0000F87E SW V1, 0(S8)
\r
20135 BFD0332A FFF240A2 BNEZC V0, 0xBFD03312
\r
20136 BFD0332C 41A2FFF2 LW RA, 16802(S2)
\r
20139 BFD03312 08000000 SSNOP
\r
20140 BFD03314 0800 LBU S0, 0(S0)
\r
20143 123: // GPIO Output enabled (drive based on above settings)
\r
20144 124: GPIO_CTRL->REG[TFDP_PIN_1].w |= (1ul << 9);
\r
20145 BFD0332E A00841A2 LUI V0, 0xA008
\r
20146 BFD03332 10005042 ORI V0, V0, 4096
\r
20147 BFD03334 41A31000 ADDI ZERO, ZERO, 16803
\r
20148 BFD03336 A00841A3 LUI V1, 0xA008
\r
20149 BFD0333A 10005063 ORI V1, V1, 4096
\r
20150 BFD0333C FC631000 ADDI ZERO, ZERO, -925
\r
20151 BFD0333E 0138FC63 LW V1, 312(V1)
\r
20152 BFD03342 02005063 ORI V1, V1, 512
\r
20153 BFD03346 0138F862 SW V1, 312(V0)
\r
20154 125: GPIO_CTRL->REG[TFDP_PIN_2].w |= (1ul << 9);
\r
20155 BFD0334A A00841A2 LUI V0, 0xA008
\r
20156 BFD0334E 10005042 ORI V0, V0, 4096
\r
20157 BFD03350 41A31000 ADDI ZERO, ZERO, 16803
\r
20158 BFD03352 A00841A3 LUI V1, 0xA008
\r
20159 BFD03356 10005063 ORI V1, V1, 4096
\r
20160 BFD03358 FC631000 ADDI ZERO, ZERO, -925
\r
20161 BFD0335A 013CFC63 LW V1, 316(V1)
\r
20162 BFD0335E 02005063 ORI V1, V1, 512
\r
20163 BFD03362 013CF862 SW V1, 316(V0)
\r
20164 BFD03364 3040013C SRL T1, GP, 6
\r
20166 127: delay = 128;
\r
20167 BFD03366 00803040 ADDIU V0, ZERO, 128
\r
20168 128: while ( delay-- )
\r
20169 BFD0336A CC04 B 0xBFD03374
\r
20170 BFD0336C 0000F85E SW V0, 0(S8)
\r
20171 BFD0336E 00000000 NOP
\r
20172 BFD03374 0000FC5E LW V0, 0(S8)
\r
20173 BFD03376 00400000 SRL ZERO, ZERO, 0
\r
20174 BFD03378 13900040 SLTU V0, ZERO, V0
\r
20175 BFD0337A 2D2D1390 ADDI GP, S0, 11565
\r
20176 BFD0337C 2D2D ANDI V0, V0, 0xFF
\r
20177 BFD0337E 0000FC7E LW V1, 0(S8)
\r
20178 BFD03382 6DBE ADDIU V1, V1, -1
\r
20179 BFD03384 0000F87E SW V1, 0(S8)
\r
20180 BFD03388 FFF240A2 BNEZC V0, 0xBFD03370
\r
20181 BFD0338A 41A2FFF2 LW RA, 16802(S2)
\r
20184 BFD03370 08000000 SSNOP
\r
20185 BFD03372 0800 LBU S0, 0(S0)
\r
20188 133: // Switch to Function 1 (TFDP mode b[13:12]=01b)
\r
20189 134: GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16) + (1ul << 12);
\r
20190 BFD0338C A00841A2 LUI V0, 0xA008
\r
20191 BFD03390 10005042 ORI V0, V0, 4096
\r
20192 BFD03392 41A31000 ADDI ZERO, ZERO, 16803
\r
20193 BFD03394 000141A3 LUI V1, 0x1
\r
20194 BFD03398 10005063 ORI V1, V1, 4096
\r
20195 BFD0339A F8621000 ADDI ZERO, ZERO, -1950
\r
20196 BFD0339C 0138F862 SW V1, 312(V0)
\r
20197 135: GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16) + (1ul << 12);
\r
20198 BFD033A0 A00841A2 LUI V0, 0xA008
\r
20199 BFD033A4 10005042 ORI V0, V0, 4096
\r
20200 BFD033A6 41A31000 ADDI ZERO, ZERO, 16803
\r
20201 BFD033A8 000141A3 LUI V1, 0x1
\r
20202 BFD033AC 10005063 ORI V1, V1, 4096
\r
20203 BFD033AE F8621000 ADDI ZERO, ZERO, -1950
\r
20204 BFD033B0 013CF862 SW V1, 316(V0)
\r
20207 138: /* b[0]=1(Enable)
\r
20208 139: * b[1]=0(Shift data out on rising edge)
\r
20209 140: * b[3:2]=00b TFDP shift clocks = AHB_CLK/2
\r
20210 141: * b[6:4]=000b 1 clock inter-packet delay
\r
20212 143: TFDP->CONTROL = 0x01u;
\r
20213 BFD033B4 A00041A2 LUI V0, 0xA000
\r
20214 BFD033B8 8C005042 ORI V0, V0, -29696
\r
20215 BFD033BA 8C00 BEQZ S0, 0xBFD033BC
\r
20216 BFD033BC ED81 LI V1, 1
\r
20217 BFD033BE CC16 B 0xBFD033EC
\r
20218 BFD033C0 89A4 SB V1, 4(V0)
\r
20223 148: TFDP->CONTROL = 0x00u;
\r
20224 BFD033C2 A00041A2 LUI V0, 0xA000
\r
20225 BFD033C6 8C005042 ORI V0, V0, -29696
\r
20226 BFD033C8 8C00 BEQZ S0, 0xBFD033CA
\r
20227 BFD033CA 8824 SB S0, 4(V0)
\r
20228 149: if (pin_cfg)
\r
20229 BFD033CC 0014145E LBU V0, 20(S8)
\r
20230 BFD033D0 000C40E2 BEQZC V0, 0xBFD033EC
\r
20231 150: { /* Set to POR value (tri-stated input) */
\r
20232 151: GPIO_CTRL->REG[TFDP_PIN_1].w = 0;
\r
20233 BFD033D4 A00841A2 LUI V0, 0xA008
\r
20234 BFD033D8 10005042 ORI V0, V0, 4096
\r
20235 BFD033DA F8021000 ADDI ZERO, ZERO, -2046
\r
20236 BFD033DC 0138F802 SW ZERO, 312(V0)
\r
20237 152: GPIO_CTRL->REG[TFDP_PIN_2].w = 0;
\r
20238 BFD033E0 A00841A2 LUI V0, 0xA008
\r
20239 BFD033E4 10005042 ORI V0, V0, 4096
\r
20240 BFD033E6 F8021000 ADDI ZERO, ZERO, -2046
\r
20241 BFD033E8 013CF802 SW ZERO, 316(V0)
\r
20244 155: } // end tfdp_enable()
\r
20245 BFD033EC 0FBE MOVE SP, S8
\r
20246 BFD033EE 4BC3 LW S8, 12(SP)
\r
20247 BFD033F0 459F JR16 RA
\r
20248 BFD033F2 4C09 ADDIU SP, SP, 16
\r
20252 159: * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first
\r
20253 160: * over TFDP.
\r
20255 162: * @author sworley
\r
20257 164: * @param nbr 16-bit trace number
\r
20258 165: * @param b unused
\r
20260 167: * @return uint8_t always TRUE
\r
20261 168: * @note Function implements critical section.
\r
20262 169: * Uses tool kit __disable_irq()/__enable_irq() pair which may use
\r
20263 170: * priviledged Cortex-Mx instructions.
\r
20265 172: void TFDPTrace0 ( uint16_t nbr, uint8_t b )
\r
20267 BFD09A18 4FF5 ADDIU SP, SP, -24
\r
20268 BFD09A1A CBE5 SW RA, 20(SP)
\r
20269 BFD09A1C CBC4 SW S8, 16(SP)
\r
20270 BFD09A1E 0FDD MOVE S8, SP
\r
20271 BFD09A20 0C64 MOVE V1, A0
\r
20272 BFD09A22 0C45 MOVE V0, A1
\r
20273 BFD09A24 0018387E SH V1, 24(S8)
\r
20274 BFD09A28 001C185E SB V0, 28(S8)
\r
20275 174: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20276 175: uint32_t isave;
\r
20278 177: isave = mips32r2_dis_intr();
\r
20282 181: tfdp_xmit_header(nbr);
\r
20283 BFD09A2C 0018345E LHU V0, 24(S8)
\r
20284 BFD09A30 0C82 MOVE A0, V0
\r
20285 BFD09A32 483677E8 JALS tfdp_xmit_header
\r
20286 BFD09A34 4836 LW AT, 88(SP)
\r
20287 BFD09A36 0C00 NOP
\r
20289 183: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20290 184: mips32r2_restore_intr(isave);
\r
20293 BFD09A38 0FBE MOVE SP, S8
\r
20294 BFD09A3A 4BE5 LW RA, 20(SP)
\r
20295 BFD09A3C 4BC4 LW S8, 16(SP)
\r
20296 BFD09A3E 4C0D ADDIU SP, SP, 24
\r
20297 BFD09A40 459F JR16 RA
\r
20298 BFD09A42 0C00 NOP
\r
20302 190: * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first
\r
20303 191: * and 16-bit data lsb first over TFDP.
\r
20305 193: * @author sworley
\r
20307 195: * @param nbr 16-bit trace number
\r
20308 196: * @param b unused
\r
20309 197: * @param uint32_t p1 16-bit data1 in b[15:0]
\r
20311 199: * @return uint8_t always TRUE
\r
20312 200: * @note Function implements critical section.
\r
20313 201: * Uses tool kit __disable_irq()/__enable_irq() pair which may use
\r
20314 202: * priviledged Cortex-Mx instructions.
\r
20316 204: void TFDPTrace1 ( uint16_t nbr, uint8_t b, uint32_t p1 )
\r
20318 BFD094A0 4FF5 ADDIU SP, SP, -24
\r
20319 BFD094A2 CBE5 SW RA, 20(SP)
\r
20320 BFD094A4 CBC4 SW S8, 16(SP)
\r
20321 BFD094A6 0FDD MOVE S8, SP
\r
20322 BFD094A8 0C64 MOVE V1, A0
\r
20323 BFD094AA 0C45 MOVE V0, A1
\r
20324 BFD094AC 0020F8DE SW A2, 32(S8)
\r
20325 BFD094B0 0018387E SH V1, 24(S8)
\r
20326 BFD094B4 001C185E SB V0, 28(S8)
\r
20327 206: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20328 207: uint32_t isave;
\r
20330 209: isave = mips32r2_dis_intr();
\r
20333 212: tfdp_xmit_header(nbr);
\r
20334 BFD094B8 0018345E LHU V0, 24(S8)
\r
20335 BFD094BC 0C82 MOVE A0, V0
\r
20336 BFD094BE 483677E8 JALS tfdp_xmit_header
\r
20337 BFD094C0 4836 LW AT, 88(SP)
\r
20338 BFD094C2 0C00 NOP
\r
20339 213: tfdp_xmit_hword(p1);
\r
20340 BFD094C4 0020FC5E LW V0, 32(S8)
\r
20341 BFD094C8 2D2F ANDI V0, V0, 0xFFFF
\r
20342 BFD094CA 0C82 MOVE A0, V0
\r
20343 BFD094CC 4B2477E8 JALS tfdp_xmit_hword
\r
20344 BFD094CE 4B24 LW T9, 16(SP)
\r
20345 BFD094D0 0C00 NOP
\r
20347 215: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20348 216: mips32r2_restore_intr(isave);
\r
20351 BFD094D2 0FBE MOVE SP, S8
\r
20352 BFD094D4 4BE5 LW RA, 20(SP)
\r
20353 BFD094D6 4BC4 LW S8, 16(SP)
\r
20354 BFD094D8 4C0D ADDIU SP, SP, 24
\r
20355 BFD094DA 459F JR16 RA
\r
20356 BFD094DC 0C00 NOP
\r
20360 222: * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first
\r
20361 223: * and two 16-bit data parameters lsb first over TFDP.
\r
20363 225: * @author sworley
\r
20365 227: * @param nbr trace number
\r
20366 228: * @param b unused
\r
20367 229: * @param uint32_t p1 16-bit data1 in b[15:0]
\r
20368 230: * @param uint32_t p2 16-bit data2 in b[15:0]
\r
20370 232: * @return uint8_t always TRUE
\r
20371 233: * @note Uses tool kit functions to save/disable/restore
\r
20372 234: * interrupts for critical section. These may use
\r
20373 235: * priviledged instructions.
\r
20375 237: void TFDPTrace2 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )
\r
20377 BFD08A44 4FF5 ADDIU SP, SP, -24
\r
20378 BFD08A46 CBE5 SW RA, 20(SP)
\r
20379 BFD08A48 CBC4 SW S8, 16(SP)
\r
20380 BFD08A4A 0FDD MOVE S8, SP
\r
20381 BFD08A4C 0C64 MOVE V1, A0
\r
20382 BFD08A4E 0C45 MOVE V0, A1
\r
20383 BFD08A50 0020F8DE SW A2, 32(S8)
\r
20384 BFD08A54 0024F8FE SW A3, 36(S8)
\r
20385 BFD08A58 0018387E SH V1, 24(S8)
\r
20386 BFD08A5C 001C185E SB V0, 28(S8)
\r
20387 239: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20388 240: uint32_t isave;
\r
20390 242: isave = mips32r2_dis_intr();
\r
20393 245: tfdp_xmit_header(nbr);
\r
20394 BFD08A60 0018345E LHU V0, 24(S8)
\r
20395 BFD08A64 0C82 MOVE A0, V0
\r
20396 BFD08A66 483677E8 JALS tfdp_xmit_header
\r
20397 BFD08A68 4836 LW AT, 88(SP)
\r
20398 BFD08A6A 0C00 NOP
\r
20399 246: tfdp_xmit_hword(p1);
\r
20400 BFD08A6C 0020FC5E LW V0, 32(S8)
\r
20401 BFD08A70 2D2F ANDI V0, V0, 0xFFFF
\r
20402 BFD08A72 0C82 MOVE A0, V0
\r
20403 BFD08A74 4B2477E8 JALS tfdp_xmit_hword
\r
20404 BFD08A76 4B24 LW T9, 16(SP)
\r
20405 BFD08A78 0C00 NOP
\r
20406 247: tfdp_xmit_hword(p2);
\r
20407 BFD08A7A 0024FC5E LW V0, 36(S8)
\r
20408 BFD08A7E 2D2F ANDI V0, V0, 0xFFFF
\r
20409 BFD08A80 0C82 MOVE A0, V0
\r
20410 BFD08A82 4B2477E8 JALS tfdp_xmit_hword
\r
20411 BFD08A84 4B24 LW T9, 16(SP)
\r
20412 BFD08A86 0C00 NOP
\r
20414 249: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20415 250: mips32r2_restore_intr(isave);
\r
20418 BFD08A88 0FBE MOVE SP, S8
\r
20419 BFD08A8A 4BE5 LW RA, 20(SP)
\r
20420 BFD08A8C 4BC4 LW S8, 16(SP)
\r
20421 BFD08A8E 4C0D ADDIU SP, SP, 24
\r
20422 BFD08A90 459F JR16 RA
\r
20423 BFD08A92 0C00 NOP
\r
20427 256: * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first
\r
20428 257: * and three 16-bit data parameters lsb first over TFDP.
\r
20430 259: * @author sworley
\r
20432 261: * @param nbr trace number
\r
20433 262: * @param b unused
\r
20434 263: * @param uint32_t p1 16-bit data1 in b[15:0]
\r
20435 264: * @param uint32_t p2 16-bit data2 in b[15:0]
\r
20436 265: * @param uint32_t p3 16-bit data3 in b[15:0]
\r
20438 267: * @return uint8_t always TRUE
\r
20439 268: * @note Uses tool kit functions to save/disable/restore
\r
20440 269: * interrupts for critical section. These may use
\r
20441 270: * priviledged instructions.
\r
20443 272: void TFDPTrace3 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3)
\r
20445 BFD08274 4FF5 ADDIU SP, SP, -24
\r
20446 BFD08276 CBE5 SW RA, 20(SP)
\r
20447 BFD08278 CBC4 SW S8, 16(SP)
\r
20448 BFD0827A 0FDD MOVE S8, SP
\r
20449 BFD0827C 0C64 MOVE V1, A0
\r
20450 BFD0827E 0C45 MOVE V0, A1
\r
20451 BFD08280 0020F8DE SW A2, 32(S8)
\r
20452 BFD08284 0024F8FE SW A3, 36(S8)
\r
20453 BFD08288 0018387E SH V1, 24(S8)
\r
20454 BFD0828C 001C185E SB V0, 28(S8)
\r
20455 274: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20456 275: uint32_t isave;
\r
20458 277: isave = mips32r2_dis_intr();
\r
20461 280: tfdp_xmit_header(nbr);
\r
20462 BFD08290 0018345E LHU V0, 24(S8)
\r
20463 BFD08294 0C82 MOVE A0, V0
\r
20464 BFD08296 483677E8 JALS tfdp_xmit_header
\r
20465 BFD08298 4836 LW AT, 88(SP)
\r
20466 BFD0829A 0C00 NOP
\r
20467 281: tfdp_xmit_hword(p1);
\r
20468 BFD0829C 0020FC5E LW V0, 32(S8)
\r
20469 BFD082A0 2D2F ANDI V0, V0, 0xFFFF
\r
20470 BFD082A2 0C82 MOVE A0, V0
\r
20471 BFD082A4 4B2477E8 JALS tfdp_xmit_hword
\r
20472 BFD082A6 4B24 LW T9, 16(SP)
\r
20473 BFD082A8 0C00 NOP
\r
20474 282: tfdp_xmit_hword(p2);
\r
20475 BFD082AA 0024FC5E LW V0, 36(S8)
\r
20476 BFD082AE 2D2F ANDI V0, V0, 0xFFFF
\r
20477 BFD082B0 0C82 MOVE A0, V0
\r
20478 BFD082B2 4B2477E8 JALS tfdp_xmit_hword
\r
20479 BFD082B4 4B24 LW T9, 16(SP)
\r
20480 BFD082B6 0C00 NOP
\r
20481 283: tfdp_xmit_hword(p3);
\r
20482 BFD082B8 0028FC5E LW V0, 40(S8)
\r
20483 BFD082BC 2D2F ANDI V0, V0, 0xFFFF
\r
20484 BFD082BE 0C82 MOVE A0, V0
\r
20485 BFD082C0 4B2477E8 JALS tfdp_xmit_hword
\r
20486 BFD082C2 4B24 LW T9, 16(SP)
\r
20487 BFD082C4 0C00 NOP
\r
20489 285: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20490 286: if ( isave & (1ul<<0) )
\r
20492 288: mips32r2_en_intr();
\r
20496 BFD082C6 0FBE MOVE SP, S8
\r
20497 BFD082C8 4BE5 LW RA, 20(SP)
\r
20498 BFD082CA 4BC4 LW S8, 16(SP)
\r
20499 BFD082CC 4C0D ADDIU SP, SP, 24
\r
20500 BFD082CE 459F JR16 RA
\r
20501 BFD082D0 0C00 NOP
\r
20505 295: * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first
\r
20506 296: * and four 16-bit data parameters lsb first over TFDP.
\r
20508 298: * @author sworley
\r
20510 300: * @param nbr trace number
\r
20511 301: * @param b unused
\r
20512 302: * @param uint32_t p1 16-bit data1 in b[15:0]
\r
20513 303: * @param uint32_t p2 16-bit data2 in b[15:0]
\r
20514 304: * @param uint32_t p3 16-bit data3 in b[15:0]
\r
20515 305: * @param uint32_t p4 16-bit data4 in b[15:0]
\r
20517 307: * @return uint8_t always TRUE
\r
20518 308: * @note Uses tool kit functions to save/disable/restore
\r
20519 309: * interrupts for critical section. These may use
\r
20520 310: * priviledged instructions.
\r
20522 312: void TFDPTrace4 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4)
\r
20524 BFD07C28 4FF5 ADDIU SP, SP, -24
\r
20525 BFD07C2A CBE5 SW RA, 20(SP)
\r
20526 BFD07C2C CBC4 SW S8, 16(SP)
\r
20527 BFD07C2E 0FDD MOVE S8, SP
\r
20528 BFD07C30 0C64 MOVE V1, A0
\r
20529 BFD07C32 0C45 MOVE V0, A1
\r
20530 BFD07C34 0020F8DE SW A2, 32(S8)
\r
20531 BFD07C38 0024F8FE SW A3, 36(S8)
\r
20532 BFD07C3C 0018387E SH V1, 24(S8)
\r
20533 BFD07C40 001C185E SB V0, 28(S8)
\r
20534 314: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20535 315: uint32_t isave;
\r
20537 317: isave = mips32r2_dis_intr();
\r
20540 320: tfdp_xmit_header(nbr);
\r
20541 BFD07C44 0018345E LHU V0, 24(S8)
\r
20542 BFD07C48 0C82 MOVE A0, V0
\r
20543 BFD07C4A 483677E8 JALS tfdp_xmit_header
\r
20544 BFD07C4C 4836 LW AT, 88(SP)
\r
20545 BFD07C4E 0C00 NOP
\r
20546 321: tfdp_xmit_hword(p1);
\r
20547 BFD07C50 0020FC5E LW V0, 32(S8)
\r
20548 BFD07C54 2D2F ANDI V0, V0, 0xFFFF
\r
20549 BFD07C56 0C82 MOVE A0, V0
\r
20550 BFD07C58 4B2477E8 JALS tfdp_xmit_hword
\r
20551 BFD07C5A 4B24 LW T9, 16(SP)
\r
20552 BFD07C5C 0C00 NOP
\r
20553 322: tfdp_xmit_hword(p2);
\r
20554 BFD07C5E 0024FC5E LW V0, 36(S8)
\r
20555 BFD07C62 2D2F ANDI V0, V0, 0xFFFF
\r
20556 BFD07C64 0C82 MOVE A0, V0
\r
20557 BFD07C66 4B2477E8 JALS tfdp_xmit_hword
\r
20558 BFD07C68 4B24 LW T9, 16(SP)
\r
20559 BFD07C6A 0C00 NOP
\r
20560 323: tfdp_xmit_hword(p3);
\r
20561 BFD07C6C 0028FC5E LW V0, 40(S8)
\r
20562 BFD07C70 2D2F ANDI V0, V0, 0xFFFF
\r
20563 BFD07C72 0C82 MOVE A0, V0
\r
20564 BFD07C74 4B2477E8 JALS tfdp_xmit_hword
\r
20565 BFD07C76 4B24 LW T9, 16(SP)
\r
20566 BFD07C78 0C00 NOP
\r
20567 324: tfdp_xmit_hword(p4);
\r
20568 BFD07C7A 002CFC5E LW V0, 44(S8)
\r
20569 BFD07C7E 2D2F ANDI V0, V0, 0xFFFF
\r
20570 BFD07C80 0C82 MOVE A0, V0
\r
20571 BFD07C82 4B2477E8 JALS tfdp_xmit_hword
\r
20572 BFD07C84 4B24 LW T9, 16(SP)
\r
20573 BFD07C86 0C00 NOP
\r
20575 326: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20576 327: if ( isave & (1ul<<0) )
\r
20578 329: mips32r2_en_intr();
\r
20582 BFD07C88 0FBE MOVE SP, S8
\r
20583 BFD07C8A 4BE5 LW RA, 20(SP)
\r
20584 BFD07C8C 4BC4 LW S8, 16(SP)
\r
20585 BFD07C8E 4C0D ADDIU SP, SP, 24
\r
20586 BFD07C90 459F JR16 RA
\r
20587 BFD07C92 0C00 NOP
\r
20591 336: * TFDPTrace11 - Transmit one 32-bit data item over TFDP
\r
20593 338: * @param nbr trace number
\r
20594 339: * @param b unused
\r
20595 340: * @param uint32_t p1 32-bit data to be transmitted
\r
20598 343: void TFDPTrace11( uint16_t nbr, uint8_t b, uint32_t p1)
\r
20600 BFD09684 4FF5 ADDIU SP, SP, -24
\r
20601 BFD09686 CBE5 SW RA, 20(SP)
\r
20602 BFD09688 CBC4 SW S8, 16(SP)
\r
20603 BFD0968A 0FDD MOVE S8, SP
\r
20604 BFD0968C 0C64 MOVE V1, A0
\r
20605 BFD0968E 0C45 MOVE V0, A1
\r
20606 BFD09690 0020F8DE SW A2, 32(S8)
\r
20607 BFD09694 0018387E SH V1, 24(S8)
\r
20608 BFD09698 001C185E SB V0, 28(S8)
\r
20609 345: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20610 346: uint32_t isave;
\r
20612 348: isave = mips32r2_dis_intr();
\r
20615 351: tfdp_xmit_header(nbr);
\r
20616 BFD0969C 0018345E LHU V0, 24(S8)
\r
20617 BFD096A0 0C82 MOVE A0, V0
\r
20618 BFD096A2 483677E8 JALS tfdp_xmit_header
\r
20619 BFD096A4 4836 LW AT, 88(SP)
\r
20620 BFD096A6 0C00 NOP
\r
20621 352: tfdp_xmit_word(p1);
\r
20622 BFD096A8 0020FC9E LW A0, 32(S8)
\r
20623 BFD096AC 467A77E8 JALS tfdp_xmit_word
\r
20624 BFD096B0 0C00 NOP
\r
20626 354: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20627 355: if ( isave & (1ul<<0) )
\r
20629 357: mips32r2_en_intr();
\r
20633 BFD096B2 0FBE MOVE SP, S8
\r
20634 BFD096B4 4BE5 LW RA, 20(SP)
\r
20635 BFD096B6 4BC4 LW S8, 16(SP)
\r
20636 BFD096B8 4C0D ADDIU SP, SP, 24
\r
20637 BFD096BA 459F JR16 RA
\r
20638 BFD096BC 0C00 NOP
\r
20642 364: * TFDPTrace12 - Transmit two 32-bit data items over TFDP
\r
20644 366: * @param nbr trace number
\r
20645 367: * @param b unused
\r
20646 368: * @param uint32_t p1 32-bit data1 to be transmitted
\r
20647 369: * @param uint32_t p2 32-bit data2 to be transmitted
\r
20650 372: void TFDPTrace12( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )
\r
20652 BFD090B4 4FF5 ADDIU SP, SP, -24
\r
20653 BFD090B6 CBE5 SW RA, 20(SP)
\r
20654 BFD090B8 CBC4 SW S8, 16(SP)
\r
20655 BFD090BA 0FDD MOVE S8, SP
\r
20656 BFD090BC 0C64 MOVE V1, A0
\r
20657 BFD090BE 0C45 MOVE V0, A1
\r
20658 BFD090C0 0020F8DE SW A2, 32(S8)
\r
20659 BFD090C4 0024F8FE SW A3, 36(S8)
\r
20660 BFD090C8 0018387E SH V1, 24(S8)
\r
20661 BFD090CC 001C185E SB V0, 28(S8)
\r
20662 374: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20663 375: uint32_t isave;
\r
20665 377: isave = mips32r2_dis_intr();
\r
20668 380: tfdp_xmit_header(nbr);
\r
20669 BFD090D0 0018345E LHU V0, 24(S8)
\r
20670 BFD090D4 0C82 MOVE A0, V0
\r
20671 BFD090D6 483677E8 JALS tfdp_xmit_header
\r
20672 BFD090D8 4836 LW AT, 88(SP)
\r
20673 BFD090DA 0C00 NOP
\r
20674 381: tfdp_xmit_word(p1);
\r
20675 BFD090DC 0020FC9E LW A0, 32(S8)
\r
20676 BFD090E0 467A77E8 JALS tfdp_xmit_word
\r
20677 BFD090E4 0C00 NOP
\r
20678 382: tfdp_xmit_word(p2);
\r
20679 BFD090E6 0024FC9E LW A0, 36(S8)
\r
20680 BFD090EA 467A77E8 JALS tfdp_xmit_word
\r
20681 BFD090EE 0C00 NOP
\r
20683 384: #ifdef ENABLE_TRACE_MASK_IRQ
\r
20684 385: if ( isave & (1ul<<0) )
\r
20686 387: mips32r2_en_intr();
\r
20690 BFD090F0 0FBE MOVE SP, S8
\r
20691 BFD090F2 4BE5 LW RA, 20(SP)
\r
20692 BFD090F4 4BC4 LW S8, 16(SP)
\r
20693 BFD090F6 4C0D ADDIU SP, SP, 24
\r
20694 BFD090F8 459F JR16 RA
\r
20695 BFD090FA 0C00 NOP
\r
20697 392: #endif // #ifdef ENABLE_TFDP_TRACE
\r
20700 395: /* end mec14xx_tfdp.c */
\r
20703 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_system.c -------
\r
20704 1: /*****************************************************************************
\r
20705 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
20706 3: * You may use this software and any derivatives exclusively with
\r
20707 4: * Microchip products.
\r
20708 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
20709 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
20710 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
20711 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
20712 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
20713 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
20714 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
20715 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
20716 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
20717 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
20718 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
20719 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
20720 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
20721 18: * OF THESE TERMS.
\r
20722 19: *****************************************************************************/
\r
20724 21: /** @file mec14xx_system.c
\r
20725 22: *MEC14xx system functions
\r
20727 24: /** @defgroup MEC14xx System
\r
20733 30: #include "appcfg.h"
\r
20734 31: #include "platform.h"
\r
20735 32: #include "MEC14xx/mec14xx.h"
\r
20736 33: #include "MEC14xx/mec14xx_system.h"
\r
20737 34: #include "MEC14xx/mec14xx_jtvic.h"
\r
20743 40: * Initialize the system
\r
20745 42: * @param none
\r
20746 43: * @return none
\r
20748 45: * @brief Setup the microcontroller system.
\r
20749 46: * Initialize the System.
\r
20751 48: void SystemInit (void)
\r
20753 BFD09E20 4FB0 ADDIU SP, SP, -8
\r
20754 BFD09E22 CBC1 SW S8, 4(SP)
\r
20755 BFD09E24 0FDD MOVE S8, SP
\r
20757 51: PCR->PROC_CLOCK_CNTRL = (PCR_CLOCK_DIVIDER);
\r
20758 BFD09E26 A00841A2 LUI V0, 0xA008
\r
20759 BFD09E2A 01005042 ORI V0, V0, 256
\r
20760 BFD09E2E ED81 LI V1, 1
\r
20761 BFD09E30 E9A8 SW V1, 32(V0)
\r
20764 BFD09E32 0FBE MOVE SP, S8
\r
20765 BFD09E34 4BC1 LW S8, 4(SP)
\r
20766 BFD09E36 4C05 ADDIU SP, SP, 8
\r
20767 BFD09E38 459F JR16 RA
\r
20768 BFD09E3A 0C00 NOP
\r
20769 54: /*---------------------------------------------------------------------------*/
\r
20771 56: uint32_t sys_code_sram_base(void)
\r
20773 BFD09EAC 4FB0 ADDIU SP, SP, -8
\r
20774 BFD09EAE CBC1 SW S8, 4(SP)
\r
20775 BFD09EB0 0FDD MOVE S8, SP
\r
20776 58: #if MEC14XX_DEVID == MEC1418_DEVID
\r
20777 59: return (uint32_t)(MEC1418_ICODE_PSRAM_BASE);
\r
20779 61: return (uint32_t)(MEC1404_ICODE_PSRAM_BASE);
\r
20780 BFD09EB2 1FD041A2 LUI V0, 0x1FD0
\r
20781 BFD09EB4 0FBE1FD0 LB S8, 4030(S0)
\r
20784 BFD09EB6 0FBE MOVE SP, S8
\r
20785 BFD09EB8 4BC1 LW S8, 4(SP)
\r
20786 BFD09EBA 4C05 ADDIU SP, SP, 8
\r
20787 BFD09EBC 459F JR16 RA
\r
20788 BFD09EBE 0C00 NOP
\r
20789 64: /*---------------------------------------------------------------------------*/
\r
20791 66: uint8_t sys_valid_sram_addr(void * const p)
\r
20793 BFD08CA8 4FF1 ADDIU SP, SP, -32
\r
20794 BFD08CAA CBE7 SW RA, 28(SP)
\r
20795 BFD08CAC CBC6 SW S8, 24(SP)
\r
20796 BFD08CAE 0FDD MOVE S8, SP
\r
20797 BFD08CB0 0020F89E SW A0, 32(S8)
\r
20798 68: uint32_t base;
\r
20800 70: base = sys_code_sram_base();
\r
20801 BFD08CB4 4F5677E8 JALS sys_code_sram_base
\r
20802 BFD08CB6 4F56 ADDIU K0, K0, -5
\r
20803 BFD08CB8 0C00 NOP
\r
20804 BFD08CBA 0010F85E SW V0, 16(S8)
\r
20806 72: if ((uint32_t)p >= base) {
\r
20807 BFD08CBE 0020FC7E LW V1, 32(S8)
\r
20808 BFD08CC2 0010FC5E LW V0, 16(S8)
\r
20809 BFD08CC6 13900043 SLTU V0, V1, V0
\r
20810 BFD08CC8 40A21390 ADDI GP, S0, 16546
\r
20811 BFD08CCA 000B40A2 BNEZC V0, 0xBFD08CE4
\r
20812 73: if ((uint32_t)p < (MEC14XX_DCODE_VSRAM_LIMIT)) {
\r
20813 BFD08CCE 0020FC7E LW V1, 32(S8)
\r
20814 BFD08CD2 BFD241A2 LUI V0, 0xBFD2
\r
20815 BFD08CD4 0043BFD2 LDC1 F30, 67(S2)
\r
20816 BFD08CD6 13900043 SLTU V0, V1, V0
\r
20817 BFD08CD8 40E21390 ADDI GP, S0, 16610
\r
20818 BFD08CDA 000340E2 BEQZC V0, 0xBFD08CE4
\r
20820 BFD08CDE ED01 LI V0, 1
\r
20821 BFD08CE0 CC02 B 0xBFD08CE6
\r
20822 BFD08CE2 0C00 NOP
\r
20826 BFD08CE4 0C40 MOVE V0, ZERO
\r
20828 BFD08CE6 0FBE MOVE SP, S8
\r
20829 BFD08CE8 4BE7 LW RA, 28(SP)
\r
20830 BFD08CEA 4BC6 LW S8, 24(SP)
\r
20831 BFD08CEC 4C11 ADDIU SP, SP, 32
\r
20832 BFD08CEE 459F JR16 RA
\r
20833 BFD08CF0 0C00 NOP
\r
20834 79: /*---------------------------------------------------------------------------*/
\r
20836 81: uint8_t sys_valid_sram_range(void * const p, const uint32_t byte_len)
\r
20838 BFD08858 4FF1 ADDIU SP, SP, -32
\r
20839 BFD0885A CBE7 SW RA, 28(SP)
\r
20840 BFD0885C CBC6 SW S8, 24(SP)
\r
20841 BFD0885E 0FDD MOVE S8, SP
\r
20842 BFD08860 0020F89E SW A0, 32(S8)
\r
20843 BFD08864 0024F8BE SW A1, 36(S8)
\r
20844 83: uint32_t base;
\r
20846 85: base = sys_code_sram_base();
\r
20847 BFD08868 4F5677E8 JALS sys_code_sram_base
\r
20848 BFD0886A 4F56 ADDIU K0, K0, -5
\r
20849 BFD0886C 0C00 NOP
\r
20850 BFD0886E 0010F85E SW V0, 16(S8)
\r
20852 87: if ((uint32_t)p >= base) {
\r
20853 BFD08872 0020FC7E LW V1, 32(S8)
\r
20854 BFD08876 0010FC5E LW V0, 16(S8)
\r
20855 BFD0887A 13900043 SLTU V0, V1, V0
\r
20856 BFD0887C 40A21390 ADDI GP, S0, 16546
\r
20857 BFD0887E 000E40A2 BNEZC V0, 0xBFD0889E
\r
20858 88: if (((uint32_t)p + byte_len) < (MEC14XX_DCODE_VSRAM_LIMIT)) {
\r
20859 BFD08882 0020FC7E LW V1, 32(S8)
\r
20860 BFD08886 0024FC5E LW V0, 36(S8)
\r
20861 BFD0888A 05A6 ADDU V1, V1, V0
\r
20862 BFD0888C BFD241A2 LUI V0, 0xBFD2
\r
20863 BFD0888E 0043BFD2 LDC1 F30, 67(S2)
\r
20864 BFD08890 13900043 SLTU V0, V1, V0
\r
20865 BFD08892 40E21390 ADDI GP, S0, 16610
\r
20866 BFD08894 000340E2 BEQZC V0, 0xBFD0889E
\r
20868 BFD08898 ED01 LI V0, 1
\r
20869 BFD0889A CC02 B 0xBFD088A0
\r
20870 BFD0889C 0C00 NOP
\r
20874 BFD0889E 0C40 MOVE V0, ZERO
\r
20876 BFD088A0 0FBE MOVE SP, S8
\r
20877 BFD088A2 4BE7 LW RA, 28(SP)
\r
20878 BFD088A4 4BC6 LW S8, 24(SP)
\r
20879 BFD088A6 4C11 ADDIU SP, SP, 32
\r
20880 BFD088A8 459F JR16 RA
\r
20881 BFD088AA 0C00 NOP
\r
20882 94: /*---------------------------------------------------------------------------*/
\r
20884 96: void sys_cpu_en_timer(uint32_t counts, uint8_t ien)
\r
20886 BFD07570 4FF5 ADDIU SP, SP, -24
\r
20887 BFD07572 CBE5 SW RA, 20(SP)
\r
20888 BFD07574 CBC4 SW S8, 16(SP)
\r
20889 BFD07576 0FDD MOVE S8, SP
\r
20890 BFD07578 0018F89E SW A0, 24(S8)
\r
20891 BFD0757A 0C450018 CMP.LT.PH ZERO, T8
\r
20892 BFD0757C 0C45 MOVE V0, A1
\r
20893 BFD0757E 001C185E SB V0, 28(S8)
\r
20894 98: /* Disable Counter by setting DC bit to 1 in CP0.Cause */
\r
20895 99: _CP0_BIS_CAUSE(_CP0_CAUSE_DC_MASK);
\r
20896 BFD07582 080041A2 LUI V0, 0x800
\r
20897 BFD07584 0800 LBU S0, 0(S0)
\r
20898 BFD07586 00FC006D MFC0 V1, Cause
\r
20899 BFD07588 0C0000FC SLL A3, GP, 1
\r
20900 BFD0758A 0C00 NOP
\r
20901 BFD0758C 44D3 OR16 V0, V1
\r
20902 BFD0758E 02FC004D MTC0 V0, Cause
\r
20903 BFD07590 000002FC SLL S7, GP, 0
\r
20904 BFD07592 18000000 SLL ZERO, ZERO, 3
\r
20905 BFD07594 FC5E1800 SB ZERO, -930(ZERO)
\r
20907 101: _CP0_SET_COUNT(counts);
\r
20908 BFD07596 0018FC5E LW V0, 24(S8)
\r
20909 BFD0759A 02FC0049 MTC0 V0, Count
\r
20910 BFD0759C 000002FC SLL S7, GP, 0
\r
20911 BFD0759E 18000000 SLL ZERO, ZERO, 3
\r
20912 BFD075A0 145E1800 SB ZERO, 5214(ZERO)
\r
20914 BFD075A2 001C145E LBU V0, 28(S8)
\r
20915 BFD075A6 000840E2 BEQZC V0, 0xBFD075BA
\r
20916 BFD075A8 EE100008 MUL SP, T0, ZERO
\r
20917 103: jtvic_en_source(MEC14xx_GIRQ24_ID, 0, 0);
\r
20918 BFD075AA EE10 LI A0, 16
\r
20919 BFD075AC 0CA0 MOVE A1, ZERO
\r
20920 BFD075AE 0CC0 MOVE A2, ZERO
\r
20921 BFD075B0 3A7C77E8 JALS jtvic_en_source
\r
20922 BFD075B2 0C003A7C SH S3, 3072(GP)
\r
20923 BFD075B4 0C00 NOP
\r
20924 BFD075B6 CC07 B 0xBFD075C6
\r
20925 BFD075B8 0C00 NOP
\r
20927 105: jtvic_dis_clr_source(MEC14xx_GIRQ24_ID, 0, 1);
\r
20928 BFD075BA EE10 LI A0, 16
\r
20929 BFD075BC 0CA0 MOVE A1, ZERO
\r
20930 BFD075BE EF01 LI A2, 1
\r
20931 BFD075C0 3A4077E8 JALS jtvic_dis_clr_source
\r
20932 BFD075C2 0C003A40 SH S2, 3072(ZERO)
\r
20933 BFD075C4 0C00 NOP
\r
20936 108: /* Enable Counter */
\r
20937 109: _CP0_BIC_CAUSE(_CP0_CAUSE_DC_MASK);
\r
20938 BFD075C6 080041A2 LUI V0, 0x800
\r
20939 BFD075C8 0800 LBU S0, 0(S0)
\r
20940 BFD075CA 00FC006D MFC0 V1, Cause
\r
20941 BFD075CC 0C0000FC SLL A3, GP, 1
\r
20942 BFD075CE 0C00 NOP
\r
20943 BFD075D0 4412 NOT16 V0, V0
\r
20944 BFD075D2 4493 AND16 V0, V1
\r
20945 BFD075D4 02FC004D MTC0 V0, Cause
\r
20946 BFD075D6 000002FC SLL S7, GP, 0
\r
20947 BFD075D8 18000000 SLL ZERO, ZERO, 3
\r
20948 BFD075DA 0FBE1800 SB ZERO, 4030(ZERO)
\r
20951 BFD075DC 0FBE MOVE SP, S8
\r
20952 BFD075DE 4BE5 LW RA, 20(SP)
\r
20953 BFD075E0 4BC4 LW S8, 16(SP)
\r
20954 BFD075E2 4C0D ADDIU SP, SP, 24
\r
20955 BFD075E4 459F JR16 RA
\r
20956 BFD075E6 0C00 NOP
\r
20957 112: /*---------------------------------------------------------------------------*/
\r
20959 114: uint32_t cpu_microsecond_count(void)
\r
20961 BFD09EC0 4FB0 ADDIU SP, SP, -8
\r
20962 BFD09EC2 CBC1 SW S8, 4(SP)
\r
20963 BFD09EC4 0FDD MOVE S8, SP
\r
20964 116: return _CP0_GET_COUNT();
\r
20965 BFD09EC6 00FC0049 MFC0 V0, Count
\r
20967 BFD09ECA 0FBE MOVE SP, S8
\r
20968 BFD09ECC 4BC1 LW S8, 4(SP)
\r
20969 BFD09ECE 4C05 ADDIU SP, SP, 8
\r
20970 BFD09ED0 459F JR16 RA
\r
20971 BFD09ED2 0C00 NOP
\r
20972 118: /*---------------------------------------------------------------------------*/
\r
20975 121: * Assumes M14K CPU is running at clock divide by 1 (48MHz)
\r
20976 122: * 1us = 48 counts.
\r
20977 123: * NOTE: We need to find out from DE what the pipeline rate is.
\r
20978 124: * M14K counter ticks at pipeline rate.
\r
20980 126: uint32_t cpu_microsecond_interval(uint32_t start_count)
\r
20982 BFD07DCC 4FF9 ADDIU SP, SP, -16
\r
20983 BFD07DCE CBC3 SW S8, 12(SP)
\r
20984 BFD07DD0 0FDD MOVE S8, SP
\r
20985 BFD07DD2 0010F89E SW A0, 16(S8)
\r
20986 128: uint32_t curr_count;
\r
20988 130: curr_count = _CP0_GET_COUNT();
\r
20989 BFD07DD6 00FC0049 MFC0 V0, Count
\r
20990 BFD07DDA 0000F85E SW V0, 0(S8)
\r
20991 131: if (curr_count >= start_count) {
\r
20992 BFD07DDE 0000FC7E LW V1, 0(S8)
\r
20993 BFD07DE2 0010FC5E LW V0, 16(S8)
\r
20994 BFD07DE6 13900043 SLTU V0, V1, V0
\r
20995 BFD07DE8 40A21390 ADDI GP, S0, 16546
\r
20996 BFD07DEA 000F40A2 BNEZC V0, 0xBFD07E0C
\r
20997 132: return ((curr_count - start_count) >> 4)/ 3ul;
\r
20998 BFD07DEE 0000FC7E LW V1, 0(S8)
\r
20999 BFD07DF2 0010FC5E LW V0, 16(S8)
\r
21000 BFD07DF6 0527 SUBU V0, V1, V0
\r
21001 BFD07DF8 25A9 SRL V1, V0, 4
\r
21002 BFD07DFA ED03 LI V0, 3
\r
21003 BFD07DFC BB3C0043 DIVU V0, V1
\r
21004 BFD07DFE 0002BB3C SDC1 F25, 2(GP)
\r
21005 BFD07E00 703C0002 TEQ V0, ZERO
\r
21006 BFD07E02 4603703C XORI AT, GP, 17923
\r
21007 BFD07E04 4603 MFHI V1
\r
21008 BFD07E06 4642 MFLO V0
\r
21009 BFD07E08 CC0F B 0xBFD07E28
\r
21010 BFD07E0A 0C00 NOP
\r
21012 134: return (((0xFFFFFFFFul - start_count) + curr_count) >> 4) / 3ul;
\r
21013 BFD07E0C 0010FC5E LW V0, 16(S8)
\r
21014 BFD07E10 441A NOT16 V1, V0
\r
21015 BFD07E12 0000FC5E LW V0, 0(S8)
\r
21016 BFD07E16 0526 ADDU V0, V1, V0
\r
21017 BFD07E18 25A9 SRL V1, V0, 4
\r
21018 BFD07E1A ED03 LI V0, 3
\r
21019 BFD07E1C BB3C0043 DIVU V0, V1
\r
21020 BFD07E1E 0002BB3C SDC1 F25, 2(GP)
\r
21021 BFD07E20 703C0002 TEQ V0, ZERO
\r
21022 BFD07E22 4603703C XORI AT, GP, 17923
\r
21023 BFD07E24 4603 MFHI V1
\r
21024 BFD07E26 4642 MFLO V0
\r
21027 BFD07E28 0FBE MOVE SP, S8
\r
21028 BFD07E2A 4BC3 LW S8, 12(SP)
\r
21029 BFD07E2C 4C09 ADDIU SP, SP, 16
\r
21030 BFD07E2E 459F JR16 RA
\r
21031 BFD07E30 0C00 NOP
\r
21032 137: /*---------------------------------------------------------------------------*/
\r
21034 139: /* end mec14xx_system.c */
\r
21038 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_jtvic.c --------
\r
21039 1: /*****************************************************************************
\r
21040 2: * © 2014 Microchip Technology Inc. and its subsidiaries.
\r
21041 3: * You may use this software and any derivatives exclusively with
\r
21042 4: * Microchip products.
\r
21043 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
21044 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
21045 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
21046 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
21047 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
21048 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
21049 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
21050 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
21051 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
21052 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
21053 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
21054 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
21055 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
21056 18: * OF THESE TERMS.
\r
21057 19: *****************************************************************************/
\r
21059 21: /** @file mec14xx_jtvic.c
\r
21060 22: *MEC14xx JTVIC
\r
21062 24: /** @defgroup MEC14xx Peripherals JTVIC
\r
21067 29: #include "appcfg.h"
\r
21068 30: #include "platform.h"
\r
21069 31: #include "MEC14xx/mec14xx.h"
\r
21070 32: #include "MEC14xx/mec14xx_jtvic.h"
\r
21073 35: void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags)
\r
21075 BFD03644 4FF9 ADDIU SP, SP, -16
\r
21076 BFD03646 CBC3 SW S8, 12(SP)
\r
21077 BFD03648 0FDD MOVE S8, SP
\r
21078 BFD0364A 0010F89E SW A0, 16(S8)
\r
21079 BFD0364E 0014F8BE SW A1, 20(S8)
\r
21080 BFD03652 0018F8DE SW A2, 24(S8)
\r
21082 38: uint8_t i, j, pidx;
\r
21084 40: JTVIC_CTRL->w = (1ul << 0); // Soft-Reset
\r
21085 BFD03656 BFFF41A2 LUI V0, 0xBFFF
\r
21086 BFD03658 5042BFFF LDC1 F31, 20546(RA)
\r
21087 BFD0365A C5005042 ORI V0, V0, -15104
\r
21088 BFD0365E ED81 LI V1, 1
\r
21089 BFD03660 E9A0 SW V1, 0(V0)
\r
21091 BFD03662 0000F81E SW ZERO, 0(S8)
\r
21092 42: if ( cflags & (1ul << 0) )
\r
21093 BFD03666 0018FC5E LW V0, 24(S8)
\r
21094 BFD0366A 2D21 ANDI V0, V0, 0x1
\r
21095 BFD0366C 2D2D ANDI V0, V0, 0xFF
\r
21096 BFD0366E 000440E2 BEQZC V0, 0xBFD0367A
\r
21097 BFD03670 30400004 SRL ZERO, A0, 6
\r
21099 44: d = (1ul << 8);
\r
21100 BFD03672 01003040 ADDIU V0, ZERO, 256
\r
21101 BFD03676 0000F85E SW V0, 0(S8)
\r
21103 46: JTVIC_CTRL->w = d; // HW does not automatically clear Soft-Reset
\r
21104 BFD0367A BFFF41A2 LUI V0, 0xBFFF
\r
21105 BFD0367C 5042BFFF LDC1 F31, 20546(RA)
\r
21106 BFD0367E C5005042 ORI V0, V0, -15104
\r
21107 BFD03682 0000FC7E LW V1, 0(S8)
\r
21108 BFD03686 E9A0 SW V1, 0(V0)
\r
21110 48: for (i = 0u; i < (MEC14xx_NUM_JTVIC_INTS); i++) {
\r
21111 BFD03688 0004181E SB ZERO, 4(S8)
\r
21112 BFD0368C CC5C B 0xBFD03746
\r
21113 BFD0368E 0C00 NOP
\r
21114 BFD0373C 0004145E LBU V0, 4(S8)
\r
21115 BFD03740 6D20 ADDIU V0, V0, 1
\r
21116 BFD03742 0004185E SB V0, 4(S8)
\r
21117 BFD03746 0004145E LBU V0, 4(S8)
\r
21118 BFD0374A 0013B042 SLTIU V0, V0, 19
\r
21119 BFD0374E FF9F40A2 BNEZC V0, 0xBFD03690
\r
21120 BFD03750 41A2FF9F LW GP, 16802(RA)
\r
21121 49: pidx = i << 2;
\r
21122 BFD03690 0004145E LBU V0, 4(S8)
\r
21123 BFD03694 2524 SLL V0, V0, 2
\r
21124 BFD03696 0006185E SB V0, 6(S8)
\r
21125 50: for (j = 0u; j < 4u; j++) {
\r
21126 BFD0369A 0005181E SB ZERO, 5(S8)
\r
21127 BFD0369E CC1F B 0xBFD036DE
\r
21128 BFD036A0 0C00 NOP
\r
21129 BFD036D4 0005145E LBU V0, 5(S8)
\r
21130 BFD036D8 6D20 ADDIU V0, V0, 1
\r
21131 BFD036DA 0005185E SB V0, 5(S8)
\r
21132 BFD036DE 0005145E LBU V0, 5(S8)
\r
21133 BFD036E2 0004B042 SLTIU V0, V0, 4
\r
21134 BFD036E6 FFDC40A2 BNEZC V0, 0xBFD036A2
\r
21135 BFD036E8 145EFFDC LW S8, 5214(GP)
\r
21136 51: JTVIC_PRI->REG32[pidx+j] = (uint32_t)(ih_table[i].pri[j]);
\r
21137 BFD036A2 BFFF41A2 LUI V0, 0xBFFF
\r
21138 BFD036A4 5082BFFF LDC1 F31, 20610(RA)
\r
21139 BFD036A6 C3005082 ORI A0, V0, -15616
\r
21140 BFD036AA 0006147E LBU V1, 6(S8)
\r
21141 BFD036AE 0005145E LBU V0, 5(S8)
\r
21142 BFD036B2 06A6 ADDU A1, V1, V0
\r
21143 BFD036B4 0004145E LBU V0, 4(S8)
\r
21144 BFD036B8 2524 SLL V0, V0, 2
\r
21145 BFD036BA 25A4 SLL V1, V0, 2
\r
21146 BFD036BC 0534 ADDU V0, V0, V1
\r
21147 BFD036BE 0010FC7E LW V1, 16(S8)
\r
21148 BFD036C2 05A6 ADDU V1, V1, V0
\r
21149 BFD036C4 0005145E LBU V0, 5(S8)
\r
21150 BFD036C8 2524 SLL V0, V0, 2
\r
21151 BFD036CA 0526 ADDU V0, V1, V0
\r
21152 BFD036CC 69A1 LW V1, 4(V0)
\r
21153 BFD036CE 2554 SLL V0, A1, 2
\r
21154 BFD036D0 0528 ADDU V0, A0, V0
\r
21155 BFD036D2 E9A0 SW V1, 0(V0)
\r
21157 53: d = ih_table[i].isr_addr & ~(1ul << 0);
\r
21158 BFD036EA 0004145E LBU V0, 4(S8)
\r
21159 BFD036EE 2524 SLL V0, V0, 2
\r
21160 BFD036F0 25A4 SLL V1, V0, 2
\r
21161 BFD036F2 0534 ADDU V0, V0, V1
\r
21162 BFD036F4 0010FC7E LW V1, 16(S8)
\r
21163 BFD036F8 0526 ADDU V0, V1, V0
\r
21164 BFD036FA 69A0 LW V1, 0(V0)
\r
21165 BFD036FC FFFE3040 ADDIU V0, ZERO, -2
\r
21166 BFD036FE 4493FFFE LW RA, 17555(S8)
\r
21167 BFD03700 4493 AND16 V0, V1
\r
21168 BFD03702 0000F85E SW V0, 0(S8)
\r
21169 54: if (disagg_bitmap & (1ul << i)) {
\r
21170 BFD03706 0004145E LBU V0, 4(S8)
\r
21171 BFD0370A 0014FC7E LW V1, 20(S8)
\r
21172 BFD0370E 10500062 SRLV V0, V0, V1
\r
21173 BFD03710 2D211050 ADDI V0, S0, 11553
\r
21174 BFD03712 2D21 ANDI V0, V0, 0x1
\r
21175 BFD03714 2D2D ANDI V0, V0, 0xFF
\r
21176 BFD03716 000640E2 BEQZC V0, 0xBFD03726
\r
21177 55: d |= (1ul << 0); // dis-aggregate this GIRQ
\r
21178 BFD0371A 0000FC5E LW V0, 0(S8)
\r
21179 BFD0371E 00015042 ORI V0, V0, 1
\r
21180 BFD03722 0000F85E SW V0, 0(S8)
\r
21182 57: JTVIC_ACTRL->REG32[i] = d;
\r
21183 BFD03726 BFFF41A2 LUI V0, 0xBFFF
\r
21184 BFD03728 5062BFFF LDC1 F31, 20578(RA)
\r
21185 BFD0372A C2005062 ORI V1, V0, -15872
\r
21186 BFD0372E 0004145E LBU V0, 4(S8)
\r
21187 BFD03732 2524 SLL V0, V0, 2
\r
21188 BFD03734 0526 ADDU V0, V1, V0
\r
21189 BFD03736 0000FC7E LW V1, 0(S8)
\r
21190 BFD0373A E9A0 SW V1, 0(V0)
\r
21193 60: JTVIC_GROUP_EN_SET->w = 0xFFFFFFFFul; // Enable GIRQ08 - GIRQ18 (all)
\r
21194 BFD03752 BFFF41A2 LUI V0, 0xBFFF
\r
21195 BFD03754 5042BFFF LDC1 F31, 20546(RA)
\r
21196 BFD03756 C5085042 ORI V0, V0, -15096
\r
21197 BFD0375A EDFF LI V1, -1
\r
21198 BFD0375C E9A0 SW V1, 0(V0)
\r
21201 BFD0375E 0FBE MOVE SP, S8
\r
21202 BFD03760 4BC3 LW S8, 12(SP)
\r
21203 BFD03762 4C09 ADDIU SP, SP, 16
\r
21204 BFD03764 459F JR16 RA
\r
21205 BFD03766 0C00 NOP
\r
21207 64: /* Clear JTVIC GIRQn source bit
\r
21210 67: void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num)
\r
21212 BFD089F4 4FB0 ADDIU SP, SP, -8
\r
21213 BFD089F6 CBC1 SW S8, 4(SP)
\r
21214 BFD089F8 0FDD MOVE S8, SP
\r
21215 BFD089FA 0C64 MOVE V1, A0
\r
21216 BFD089FC 0C45 MOVE V0, A1
\r
21217 BFD089FE 0008187E SB V1, 8(S8)
\r
21218 BFD08A02 000C185E SB V0, 12(S8)
\r
21219 69: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
\r
21220 BFD08A06 0008145E LBU V0, 8(S8)
\r
21221 BFD08A0A 0013B042 SLTIU V0, V0, 19
\r
21222 BFD08A0E 001340E2 BEQZC V0, 0xBFD08A38
\r
21224 71: bit_num &= 0x1Fu;
\r
21225 BFD08A12 000C145E LBU V0, 12(S8)
\r
21226 BFD08A16 2D29 ANDI V0, V0, 0x1F
\r
21227 BFD08A18 000C185E SB V0, 12(S8)
\r
21228 72: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
\r
21229 BFD08A1C BFFF41A2 LUI V0, 0xBFFF
\r
21230 BFD08A1E 5082BFFF LDC1 F31, 20610(RA)
\r
21231 BFD08A20 C0005082 ORI A0, V0, -16384
\r
21232 BFD08A24 0008145E LBU V0, 8(S8)
\r
21233 BFD08A28 000C147E LBU V1, 12(S8)
\r
21234 BFD08A2C EE81 LI A1, 1
\r
21235 BFD08A2E 181000A3 SLLV V1, V1, A1
\r
21236 BFD08A30 25281810 SB ZERO, 9512(S0)
\r
21237 BFD08A32 2528 SLL V0, V0, 4
\r
21238 BFD08A34 0528 ADDU V0, A0, V0
\r
21239 BFD08A36 E9A0 SW V1, 0(V0)
\r
21242 BFD08A38 0FBE MOVE SP, S8
\r
21243 BFD08A3A 4BC1 LW S8, 4(SP)
\r
21244 BFD08A3C 4C05 ADDIU SP, SP, 8
\r
21245 BFD08A3E 459F JR16 RA
\r
21246 BFD08A40 0C00 NOP
\r
21249 77: /* Disable GIRQn source with optional clearing of source.
\r
21250 78: * girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26
\r
21251 79: * bit_num = [0, 31]
\r
21253 81: void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)
\r
21255 BFD07480 4FB0 ADDIU SP, SP, -8
\r
21256 BFD07482 CBC1 SW S8, 4(SP)
\r
21257 BFD07484 0FDD MOVE S8, SP
\r
21258 BFD07486 0C65 MOVE V1, A1
\r
21259 BFD07488 0C46 MOVE V0, A2
\r
21260 BFD0748A 0008189E SB A0, 8(S8)
\r
21261 BFD0748E 000C187E SB V1, 12(S8)
\r
21262 BFD07492 0010185E SB V0, 16(S8)
\r
21263 83: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
\r
21264 BFD07496 0008145E LBU V0, 8(S8)
\r
21265 BFD0749A 0013B042 SLTIU V0, V0, 19
\r
21266 BFD0749E 002540E2 BEQZC V0, 0xBFD074EC
\r
21268 85: bit_num &= 0x1Fu;
\r
21269 BFD074A2 000C145E LBU V0, 12(S8)
\r
21270 BFD074A6 2D29 ANDI V0, V0, 0x1F
\r
21271 BFD074A8 000C185E SB V0, 12(S8)
\r
21272 86: JTVIC_GIRQ->REGS[girq_num].EN_CLR = (1ul << bit_num);
\r
21273 BFD074AC BFFF41A2 LUI V0, 0xBFFF
\r
21274 BFD074AE 5082BFFF LDC1 F31, 20610(RA)
\r
21275 BFD074B0 C0005082 ORI A0, V0, -16384
\r
21276 BFD074B4 0008145E LBU V0, 8(S8)
\r
21277 BFD074B8 000C147E LBU V1, 12(S8)
\r
21278 BFD074BC EE81 LI A1, 1
\r
21279 BFD074BE 181000A3 SLLV V1, V1, A1
\r
21280 BFD074C0 25281810 SB ZERO, 9512(S0)
\r
21281 BFD074C2 2528 SLL V0, V0, 4
\r
21282 BFD074C4 0528 ADDU V0, A0, V0
\r
21283 BFD074C6 E9A2 SW V1, 8(V0)
\r
21284 87: if ( 0 != clr_src )
\r
21285 BFD074C8 0010145E LBU V0, 16(S8)
\r
21286 BFD074CC 000E40E2 BEQZC V0, 0xBFD074EC
\r
21288 89: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
\r
21289 BFD074D0 BFFF41A2 LUI V0, 0xBFFF
\r
21290 BFD074D2 5082BFFF LDC1 F31, 20610(RA)
\r
21291 BFD074D4 C0005082 ORI A0, V0, -16384
\r
21292 BFD074D8 0008145E LBU V0, 8(S8)
\r
21293 BFD074DC 000C147E LBU V1, 12(S8)
\r
21294 BFD074E0 EE81 LI A1, 1
\r
21295 BFD074E2 181000A3 SLLV V1, V1, A1
\r
21296 BFD074E4 25281810 SB ZERO, 9512(S0)
\r
21297 BFD074E6 2528 SLL V0, V0, 4
\r
21298 BFD074E8 0528 ADDU V0, A0, V0
\r
21299 BFD074EA E9A0 SW V1, 0(V0)
\r
21303 BFD074EC 0FBE MOVE SP, S8
\r
21304 BFD074EE 4BC1 LW S8, 4(SP)
\r
21305 BFD074F0 4C05 ADDIU SP, SP, 8
\r
21306 BFD074F2 459F JR16 RA
\r
21307 BFD074F4 0C00 NOP
\r
21310 95: /* Enable with optional source clear before enable.
\r
21311 96: * girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26
\r
21312 97: * bit_num = [0, 31]
\r
21314 99: void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)
\r
21316 BFD074F8 4FB0 ADDIU SP, SP, -8
\r
21317 BFD074FA CBC1 SW S8, 4(SP)
\r
21318 BFD074FC 0FDD MOVE S8, SP
\r
21319 BFD074FE 0C65 MOVE V1, A1
\r
21320 BFD07500 0C46 MOVE V0, A2
\r
21321 BFD07502 0008189E SB A0, 8(S8)
\r
21322 BFD07506 000C187E SB V1, 12(S8)
\r
21323 BFD0750A 0010185E SB V0, 16(S8)
\r
21324 101: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
\r
21325 BFD0750E 0008145E LBU V0, 8(S8)
\r
21326 BFD07512 0013B042 SLTIU V0, V0, 19
\r
21327 BFD07516 002540E2 BEQZC V0, 0xBFD07564
\r
21329 103: bit_num &= 0x1Fu;
\r
21330 BFD0751A 000C145E LBU V0, 12(S8)
\r
21331 BFD0751E 2D29 ANDI V0, V0, 0x1F
\r
21332 BFD07520 000C185E SB V0, 12(S8)
\r
21333 104: if ( 0 != clr_src )
\r
21334 BFD07524 0010145E LBU V0, 16(S8)
\r
21335 BFD07528 000E40E2 BEQZC V0, 0xBFD07548
\r
21337 106: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
\r
21338 BFD0752C BFFF41A2 LUI V0, 0xBFFF
\r
21339 BFD0752E 5082BFFF LDC1 F31, 20610(RA)
\r
21340 BFD07530 C0005082 ORI A0, V0, -16384
\r
21341 BFD07534 0008145E LBU V0, 8(S8)
\r
21342 BFD07538 000C147E LBU V1, 12(S8)
\r
21343 BFD0753C EE81 LI A1, 1
\r
21344 BFD0753E 181000A3 SLLV V1, V1, A1
\r
21345 BFD07540 25281810 SB ZERO, 9512(S0)
\r
21346 BFD07542 2528 SLL V0, V0, 4
\r
21347 BFD07544 0528 ADDU V0, A0, V0
\r
21348 BFD07546 E9A0 SW V1, 0(V0)
\r
21350 108: JTVIC_GIRQ->REGS[girq_num].EN_SET = (1ul << bit_num);
\r
21351 BFD07548 BFFF41A2 LUI V0, 0xBFFF
\r
21352 BFD0754A 5082BFFF LDC1 F31, 20610(RA)
\r
21353 BFD0754C C0005082 ORI A0, V0, -16384
\r
21354 BFD07550 0008145E LBU V0, 8(S8)
\r
21355 BFD07554 000C147E LBU V1, 12(S8)
\r
21356 BFD07558 EE81 LI A1, 1
\r
21357 BFD0755A 181000A3 SLLV V1, V1, A1
\r
21358 BFD0755C 25281810 SB ZERO, 9512(S0)
\r
21359 BFD0755E 2528 SLL V0, V0, 4
\r
21360 BFD07560 0528 ADDU V0, A0, V0
\r
21361 BFD07562 E9A1 SW V1, 4(V0)
\r
21364 BFD07564 0FBE MOVE SP, S8
\r
21365 BFD07566 4BC1 LW S8, 4(SP)
\r
21366 BFD07568 4C05 ADDIU SP, SP, 8
\r
21367 BFD0756A 459F JR16 RA
\r
21368 BFD0756C 0C00 NOP
\r
21371 113: /* end mec14xx_jtvic.c */
\r
21375 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_gpio.c ---------
\r
21376 1: /*****************************************************************************
\r
21377 2: * © 2014 Microchip Technology Inc. and its subsidiaries.
\r
21378 3: * You may use this software and any derivatives exclusively with
\r
21379 4: * Microchip products.
\r
21380 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
21381 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
21382 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
21383 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
21384 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
21385 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
21386 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
21387 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
21388 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
21389 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
21390 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
21391 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
21392 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
21393 18: * OF THESE TERMS.
\r
21394 19: *****************************************************************************/
\r
21397 22: /** @file mec14xx_gpio.c
\r
21398 23: *MEC14xx GPIO hardware access
\r
21400 25: /** @defgroup MEC14xx Peripherals GPIO
\r
21405 30: #include "appcfg.h"
\r
21406 31: #include "platform.h"
\r
21407 32: #include "MEC14xx/mec14xx.h"
\r
21408 33: #include "MEC14xx/mec14xx_gpio.h"
\r
21412 37: static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id );
\r
21415 40: #ifdef ENABLE_GPIO_PIN_VALIDATION
\r
21417 42: static const uint32_t gpio_port_bitmaps[NUM_GPIO_PORTS] =
\r
21419 44: (GPIO_PORT_A_BITMAP),
\r
21420 45: (GPIO_PORT_B_BITMAP),
\r
21421 46: (GPIO_PORT_C_BITMAP),
\r
21422 47: (GPIO_PORT_D_BITMAP)
\r
21428 53: // Drive Strength Register bitmap
\r
21430 55: static const uint32_t gpio_drv_str_bitmap[NUM_GPIO_PORTS] =
\r
21432 57: (GPIO_PORT_A_DRVSTR_BITMAP),
\r
21433 58: (GPIO_PORT_B_DRVSTR_BITMAP),
\r
21434 59: (GPIO_PORT_C_DRVSTR_BITMAP),
\r
21435 60: (GPIO_PORT_D_DRVSTR_BITMAP)
\r
21439 64: struct gpio_cfg
\r
21441 66: uint16_t bit_mask;
\r
21442 67: uint8_t bit_pos;
\r
21445 70: static const struct gpio_cfg gpio_cfg_tbl[GPIO_PROP_MAX] =
\r
21447 72: { 0x0003u, 0x00u },
\r
21448 73: { 0x000Cu, 0x02u },
\r
21449 74: { 0x00F0u, 0x04u },
\r
21450 75: { 0x0100u, 0x08u },
\r
21451 76: { 0x0200u, 0x09u },
\r
21452 77: { 0x0400u, 0x0Au },
\r
21453 78: { 0x0800u, 0x0Bu },
\r
21454 79: { 0x3000u, 0x0Cu },
\r
21455 80: { 0x3FFFu, 0x00u }
\r
21458 83: static uint32_t gpio_pin_ctrl_addr(enum gpio_id_t gpio_id)
\r
21460 BFD09B28 4FB0 ADDIU SP, SP, -8
\r
21461 BFD09B2A CBC1 SW S8, 4(SP)
\r
21462 BFD09B2C 0FDD MOVE S8, SP
\r
21463 BFD09B2E 0008F89E SW A0, 8(S8)
\r
21464 85: return ((uint32_t)(GPIO_BASE) + (uint32_t)(gpio_id << 2));
\r
21465 BFD09B32 0008FC5E LW V0, 8(S8)
\r
21466 BFD09B36 25A4 SLL V1, V0, 2
\r
21467 BFD09B38 A00841A2 LUI V0, 0xA008
\r
21468 BFD09B3C 10005042 ORI V0, V0, 4096
\r
21469 BFD09B3E 05261000 ADDI ZERO, ZERO, 1318
\r
21470 BFD09B40 0526 ADDU V0, V1, V0
\r
21472 BFD09B42 0FBE MOVE SP, S8
\r
21473 BFD09B44 4BC1 LW S8, 4(SP)
\r
21474 BFD09B46 4C05 ADDIU SP, SP, 8
\r
21475 BFD09B48 459F JR16 RA
\r
21476 BFD09B4A 0C00 NOP
\r
21478 88: #ifdef ENABLE_GPIO_PIN_VALIDATION
\r
21481 91: * gpio_is_valid - local helper checks if GPIO pin is
\r
21482 92: * implemented in this hardware.
\r
21484 94: * @author sworley
\r
21486 96: * @param gpio_id 0-based GPIO ID
\r
21488 98: * @return uint8_t Non-zero(GPIO Pin implemented), 0(not
\r
21489 99: * implemented).
\r
21491 101: static uint8_t gpio_is_valid ( enum gpio_id_t gpio_id )
\r
21493 BFD081B4 4FF9 ADDIU SP, SP, -16
\r
21494 BFD081B6 CBC3 SW S8, 12(SP)
\r
21495 BFD081B8 0FDD MOVE S8, SP
\r
21496 BFD081BA 0010F89E SW A0, 16(S8)
\r
21497 103: uint16_t gp_bank;
\r
21499 105: gp_bank = 0;
\r
21500 BFD081BE 0000381E SH ZERO, 0(S8)
\r
21502 107: if ( (uint16_t)gpio_id < (uint16_t)(MAX_GPIO_ID) )
\r
21503 BFD081C2 0010FC5E LW V0, 16(S8)
\r
21504 BFD081C6 2D2F ANDI V0, V0, 0xFFFF
\r
21505 BFD081C8 0078B042 SLTIU V0, V0, 120
\r
21506 BFD081CC 001B40E2 BEQZC V0, 0xBFD08206
\r
21508 109: gp_bank = (uint16_t)gpio_id >> 5;
\r
21509 BFD081D0 0010FC5E LW V0, 16(S8)
\r
21510 BFD081D4 2D2F ANDI V0, V0, 0xFFFF
\r
21511 BFD081D6 252B SRL V0, V0, 5
\r
21512 BFD081D8 0000385E SH V0, 0(S8)
\r
21513 110: if ( gpio_port_bitmaps[gp_bank] & (1 << (gpio_id & 0x001Fu)) )
\r
21514 BFD081DC 0000347E LHU V1, 0(S8)
\r
21515 BFD081E0 BFD141A2 LUI V0, 0xBFD1
\r
21516 BFD081E2 25B4BFD1 LDC1 F30, 9652(S1)
\r
21517 BFD081E4 25B4 SLL V1, V1, 2
\r
21518 BFD081E6 92543042 ADDIU V0, V0, -28076
\r
21519 BFD081E8 05269254 SLTI S2, S4, 1318
\r
21520 BFD081EA 0526 ADDU V0, V1, V0
\r
21521 BFD081EC 69A0 LW V1, 0(V0)
\r
21522 BFD081EE 0010FC5E LW V0, 16(S8)
\r
21523 BFD081F2 2D29 ANDI V0, V0, 0x1F
\r
21524 BFD081F4 EE01 LI A0, 1
\r
21525 BFD081F6 10100082 SLLV V0, V0, A0
\r
21526 BFD081F8 44931010 ADDI ZERO, S0, 17555
\r
21527 BFD081FA 4493 AND16 V0, V1
\r
21528 BFD081FC 000340E2 BEQZC V0, 0xBFD08206
\r
21530 112: return true;
\r
21531 BFD08200 ED01 LI V0, 1
\r
21532 BFD08202 CC02 B 0xBFD08208
\r
21533 BFD08204 0C00 NOP
\r
21537 116: return false;
\r
21538 BFD08206 0C40 MOVE V0, ZERO
\r
21540 BFD08208 0FBE MOVE SP, S8
\r
21541 BFD0820A 4BC3 LW S8, 12(SP)
\r
21542 BFD0820C 4C09 ADDIU SP, SP, 16
\r
21543 BFD0820E 459F JR16 RA
\r
21544 BFD08210 0C00 NOP
\r
21547 120: static uint32_t gpio_is_valid(enum gpio_id_t gpio_id) { return true; }
\r
21551 124: static uint8_t gpio_bank_num(enum gpio_id_t gpio_id)
\r
21553 BFD09D2C 4FB0 ADDIU SP, SP, -8
\r
21554 BFD09D2E CBC1 SW S8, 4(SP)
\r
21555 BFD09D30 0FDD MOVE S8, SP
\r
21556 BFD09D32 0008F89E SW A0, 8(S8)
\r
21557 126: return (uint8_t)(gpio_id) >> 5;
\r
21558 BFD09D36 0008FC5E LW V0, 8(S8)
\r
21559 BFD09D3A 2D2D ANDI V0, V0, 0xFF
\r
21560 BFD09D3C 252B SRL V0, V0, 5
\r
21561 BFD09D3E 2D2D ANDI V0, V0, 0xFF
\r
21563 BFD09D40 0FBE MOVE SP, S8
\r
21564 BFD09D42 4BC1 LW S8, 4(SP)
\r
21565 BFD09D44 4C05 ADDIU SP, SP, 8
\r
21566 BFD09D46 459F JR16 RA
\r
21567 BFD09D48 0C00 NOP
\r
21570 130: static uint8_t gpio_pin_num(enum gpio_id_t gpio_id)
\r
21572 BFD09D4C 4FB0 ADDIU SP, SP, -8
\r
21573 BFD09D4E CBC1 SW S8, 4(SP)
\r
21574 BFD09D50 0FDD MOVE S8, SP
\r
21575 BFD09D52 0008F89E SW A0, 8(S8)
\r
21576 132: return (uint8_t)(gpio_id) & 0x1Fu;
\r
21577 BFD09D56 0008FC5E LW V0, 8(S8)
\r
21578 BFD09D5A 2D2D ANDI V0, V0, 0xFF
\r
21579 BFD09D5C 2D29 ANDI V0, V0, 0x1F
\r
21580 BFD09D5E 2D2D ANDI V0, V0, 0xFF
\r
21582 BFD09D60 0FBE MOVE SP, S8
\r
21583 BFD09D62 4BC1 LW S8, 4(SP)
\r
21584 BFD09D64 4C05 ADDIU SP, SP, 8
\r
21585 BFD09D66 459F JR16 RA
\r
21586 BFD09D68 0C00 NOP
\r
21590 137: * gpio_has_drv_str - Local helper to check if GPIO pin has
\r
21591 138: * associated drive strength register.
\r
21593 140: * @author sworley
\r
21595 142: * @param gpio_id 0-based GPIO ID
\r
21597 144: * @return uint32_t 0(No Drive Strength), Non-zero(Physical
\r
21598 145: * address of Drive Strength Register).
\r
21600 147: static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id )
\r
21602 BFD06644 4FED ADDIU SP, SP, -40
\r
21603 BFD06646 CBE9 SW RA, 36(SP)
\r
21604 BFD06648 CBC8 SW S8, 32(SP)
\r
21605 BFD0664A 0FDD MOVE S8, SP
\r
21606 BFD0664C 0028F89E SW A0, 40(S8)
\r
21607 149: uint32_t bank, bitpos, addr;
\r
21610 BFD06650 0010F81E SW ZERO, 16(S8)
\r
21611 152: if ( gpio_id < MAX_GPIO_ID )
\r
21612 BFD06654 0028FC5E LW V0, 40(S8)
\r
21613 BFD06658 0078B042 SLTIU V0, V0, 120
\r
21614 BFD0665C 003540E2 BEQZC V0, 0xBFD066CA
\r
21616 154: bank = gpio_bank_num(gpio_id);
\r
21617 BFD06660 0028FC9E LW A0, 40(S8)
\r
21618 BFD06664 4E9677E8 JALS gpio_bank_num
\r
21619 BFD06666 4E96 ADDIU S4, S4, -5
\r
21620 BFD06668 0C00 NOP
\r
21621 BFD0666A 0014F85E SW V0, 20(S8)
\r
21622 155: bitpos = gpio_pin_num(gpio_id);
\r
21623 BFD0666E 0028FC9E LW A0, 40(S8)
\r
21624 BFD06672 4EA677E8 JALS gpio_pin_num
\r
21625 BFD06674 4EA6 ADDIU S5, S5, 3
\r
21626 BFD06676 0C00 NOP
\r
21627 BFD06678 0018F85E SW V0, 24(S8)
\r
21628 156: if ( gpio_drv_str_bitmap[bank] & (1ul << bitpos) )
\r
21629 BFD0667C BFD141A2 LUI V0, 0xBFD1
\r
21630 BFD0667E FC7EBFD1 LDC1 F30, -898(S1)
\r
21631 BFD06680 0014FC7E LW V1, 20(S8)
\r
21632 BFD06684 25B4 SLL V1, V1, 2
\r
21633 BFD06686 92643042 ADDIU V0, V0, -28060
\r
21634 BFD06688 05269264 SLTI S3, A0, 1318
\r
21635 BFD0668A 0526 ADDU V0, V1, V0
\r
21636 BFD0668C 69A0 LW V1, 0(V0)
\r
21637 BFD0668E 0018FC5E LW V0, 24(S8)
\r
21638 BFD06692 10500062 SRLV V0, V0, V1
\r
21639 BFD06694 2D211050 ADDI V0, S0, 11553
\r
21640 BFD06696 2D21 ANDI V0, V0, 0x1
\r
21641 BFD06698 2D2D ANDI V0, V0, 0xFF
\r
21642 BFD0669A 001640E2 BEQZC V0, 0xBFD066CA
\r
21644 158: addr = (GPIO_PCTRL2_BASE) + ((uint32_t)(gpio_id) << 2);
\r
21645 BFD0669E 0028FC5E LW V0, 40(S8)
\r
21646 BFD066A2 25A4 SLL V1, V0, 2
\r
21647 BFD066A4 A00841A2 LUI V0, 0xA008
\r
21648 BFD066A8 15005042 ORI V0, V0, 5376
\r
21649 BFD066AA 05261500 LBU T0, 1318(ZERO)
\r
21650 BFD066AC 0526 ADDU V0, V1, V0
\r
21651 BFD066AE 0010F85E SW V0, 16(S8)
\r
21652 159: if ( gpio_id > GPIO_0077_ID )
\r
21653 BFD066B2 0028FC5E LW V0, 40(S8)
\r
21654 BFD066B6 0040B042 SLTIU V0, V0, 64
\r
21655 BFD066BA 000640A2 BNEZC V0, 0xBFD066CA
\r
21657 161: addr -= 0x20ul;
\r
21658 BFD066BE 0010FC5E LW V0, 16(S8)
\r
21659 BFD066C2 FFE03042 ADDIU V0, V0, -32
\r
21660 BFD066C4 F85EFFE0 LW RA, -1954(ZERO)
\r
21661 BFD066C6 0010F85E SW V0, 16(S8)
\r
21666 166: return addr;
\r
21667 BFD066CA 0010FC5E LW V0, 16(S8)
\r
21669 BFD066CE 0FBE MOVE SP, S8
\r
21670 BFD066D0 4BE9 LW RA, 36(SP)
\r
21671 BFD066D2 4BC8 LW S8, 32(SP)
\r
21672 BFD066D4 4C15 ADDIU SP, SP, 40
\r
21673 BFD066D6 459F JR16 RA
\r
21674 BFD066D8 0C00 NOP
\r
21677 170: uint16_t GPIOGetConfig(enum gpio_id_t gpio_id)
\r
21679 BFD09558 4FF5 ADDIU SP, SP, -24
\r
21680 BFD0955A CBE5 SW RA, 20(SP)
\r
21681 BFD0955C CBC4 SW S8, 16(SP)
\r
21682 BFD0955E 0FDD MOVE S8, SP
\r
21683 BFD09560 0018F89E SW A0, 24(S8)
\r
21684 172: if (gpio_is_valid(gpio_id)) {
\r
21685 BFD09564 0018FC9E LW A0, 24(S8)
\r
21686 BFD09568 40DA77E8 JALS gpio_is_valid
\r
21687 BFD0956A 0C0040DA BGTZ K0, 0xBFD0AD6E
\r
21688 BFD0956C 0C00 NOP
\r
21689 BFD0956E 000940E2 BEQZC V0, 0xBFD09584
\r
21690 173: return *((volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id));
\r
21691 BFD09572 0018FC9E LW A0, 24(S8)
\r
21692 BFD09576 4D9477E8 JALS gpio_pin_ctrl_addr
\r
21693 BFD09578 4D94 ADDIU T4, T4, -6
\r
21694 BFD0957A 0C00 NOP
\r
21695 BFD0957C 2920 LHU V0, 0(V0)
\r
21696 BFD0957E 2D2F ANDI V0, V0, 0xFFFF
\r
21697 BFD09580 CC02 B 0xBFD09586
\r
21698 BFD09582 0C00 NOP
\r
21701 BFD09584 0C40 MOVE V0, ZERO
\r
21704 BFD09586 0FBE MOVE SP, S8
\r
21705 BFD09588 4BE5 LW RA, 20(SP)
\r
21706 BFD0958A 4BC4 LW S8, 16(SP)
\r
21707 BFD0958C 4C0D ADDIU SP, SP, 24
\r
21708 BFD0958E 459F JR16 RA
\r
21709 BFD09590 0C00 NOP
\r
21712 180: void GPIOSetConfig(enum gpio_id_t gpio_id, uint16_t config)
\r
21714 BFD09298 4FF1 ADDIU SP, SP, -32
\r
21715 BFD0929A CBE7 SW RA, 28(SP)
\r
21716 BFD0929C CBC6 SW S8, 24(SP)
\r
21717 BFD0929E 0FDD MOVE S8, SP
\r
21718 BFD092A0 0020F89E SW A0, 32(S8)
\r
21719 BFD092A2 0C450020 CMP.LT.PH AT, ZERO
\r
21720 BFD092A4 0C45 MOVE V0, A1
\r
21721 BFD092A6 0024385E SH V0, 36(S8)
\r
21722 182: volatile uint16_t * p;
\r
21724 184: if (gpio_is_valid(gpio_id)) {
\r
21725 BFD092AA 0020FC9E LW A0, 32(S8)
\r
21726 BFD092AE 40DA77E8 JALS gpio_is_valid
\r
21727 BFD092B0 0C0040DA BGTZ K0, 0xBFD0AAB4
\r
21728 BFD092B2 0C00 NOP
\r
21729 BFD092B4 000C40E2 BEQZC V0, 0xBFD092D0
\r
21730 185: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
\r
21731 BFD092B8 0020FC9E LW A0, 32(S8)
\r
21732 BFD092BC 4D9477E8 JALS gpio_pin_ctrl_addr
\r
21733 BFD092BE 4D94 ADDIU T4, T4, -6
\r
21734 BFD092C0 0C00 NOP
\r
21735 BFD092C2 0010F85E SW V0, 16(S8)
\r
21736 186: *p = config;
\r
21737 BFD092C6 0010FC5E LW V0, 16(S8)
\r
21738 BFD092CA 0024347E LHU V1, 36(S8)
\r
21739 BFD092CE A9A0 SH V1, 0(V0)
\r
21742 BFD092D0 0FBE MOVE SP, S8
\r
21743 BFD092D2 4BE7 LW RA, 28(SP)
\r
21744 BFD092D4 4BC6 LW S8, 24(SP)
\r
21745 BFD092D6 4C11 ADDIU SP, SP, 32
\r
21746 BFD092D8 459F JR16 RA
\r
21747 BFD092DA 0C00 NOP
\r
21750 191: void GPIOConfigAndOr(enum gpio_id_t gpio_id, uint16_t and_mask, uint16_t or_mask)
\r
21752 BFD08214 4FF1 ADDIU SP, SP, -32
\r
21753 BFD08216 CBE7 SW RA, 28(SP)
\r
21754 BFD08218 CBC6 SW S8, 24(SP)
\r
21755 BFD0821A 0FDD MOVE S8, SP
\r
21756 BFD0821C 0020F89E SW A0, 32(S8)
\r
21757 BFD0821E 0C650020 MULEQ_S.W.PHR AT, ZERO, AT
\r
21758 BFD08220 0C65 MOVE V1, A1
\r
21759 BFD08222 0C46 MOVE V0, A2
\r
21760 BFD08224 0024387E SH V1, 36(S8)
\r
21761 BFD08228 0028385E SH V0, 40(S8)
\r
21762 193: volatile uint16_t * p;
\r
21765 196: if (gpio_is_valid(gpio_id)) {
\r
21766 BFD0822C 0020FC9E LW A0, 32(S8)
\r
21767 BFD08230 40DA77E8 JALS gpio_is_valid
\r
21768 BFD08232 0C0040DA BGTZ K0, 0xBFD09A36
\r
21769 BFD08234 0C00 NOP
\r
21770 BFD08236 001640E2 BEQZC V0, 0xBFD08266
\r
21771 197: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
\r
21772 BFD0823A 0020FC9E LW A0, 32(S8)
\r
21773 BFD0823E 4D9477E8 JALS gpio_pin_ctrl_addr
\r
21774 BFD08240 4D94 ADDIU T4, T4, -6
\r
21775 BFD08242 0C00 NOP
\r
21776 BFD08244 0010F85E SW V0, 16(S8)
\r
21777 198: *p = (*p & and_mask) | or_mask;
\r
21778 BFD08248 0010FC5E LW V0, 16(S8)
\r
21779 BFD0824C 2920 LHU V0, 0(V0)
\r
21780 BFD0824E 2DAF ANDI V1, V0, 0xFFFF
\r
21781 BFD08250 0024345E LHU V0, 36(S8)
\r
21782 BFD08254 4493 AND16 V0, V1
\r
21783 BFD08256 2DAF ANDI V1, V0, 0xFFFF
\r
21784 BFD08258 0028345E LHU V0, 40(S8)
\r
21785 BFD0825C 44D3 OR16 V0, V1
\r
21786 BFD0825E 2DAF ANDI V1, V0, 0xFFFF
\r
21787 BFD08260 0010FC5E LW V0, 16(S8)
\r
21788 BFD08264 A9A0 SH V1, 0(V0)
\r
21791 BFD08266 0FBE MOVE SP, S8
\r
21792 BFD08268 4BE7 LW RA, 28(SP)
\r
21793 BFD0826A 4BC6 LW S8, 24(SP)
\r
21794 BFD0826C 4C11 ADDIU SP, SP, 32
\r
21795 BFD0826E 459F JR16 RA
\r
21796 BFD08270 0C00 NOP
\r
21799 203: uint32_t GPIOGetControl(enum gpio_id_t gpio_id)
\r
21801 BFD09770 4FF5 ADDIU SP, SP, -24
\r
21802 BFD09772 CBE5 SW RA, 20(SP)
\r
21803 BFD09774 CBC4 SW S8, 16(SP)
\r
21804 BFD09776 0FDD MOVE S8, SP
\r
21805 BFD09778 0018F89E SW A0, 24(S8)
\r
21806 205: if (gpio_is_valid(gpio_id)) {
\r
21807 BFD0977C 0018FC9E LW A0, 24(S8)
\r
21808 BFD09780 40DA77E8 JALS gpio_is_valid
\r
21809 BFD09782 0C0040DA BGTZ K0, 0xBFD0AF86
\r
21810 BFD09784 0C00 NOP
\r
21811 BFD09786 000840E2 BEQZC V0, 0xBFD0979A
\r
21812 206: return *((volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id));
\r
21813 BFD0978A 0018FC9E LW A0, 24(S8)
\r
21814 BFD0978E 4D9477E8 JALS gpio_pin_ctrl_addr
\r
21815 BFD09790 4D94 ADDIU T4, T4, -6
\r
21816 BFD09792 0C00 NOP
\r
21817 BFD09794 6920 LW V0, 0(V0)
\r
21818 BFD09796 CC02 B 0xBFD0979C
\r
21819 BFD09798 0C00 NOP
\r
21821 208: return 0xFFFFFFFFul;
\r
21822 BFD0979A ED7F LI V0, -1
\r
21825 BFD0979C 0FBE MOVE SP, S8
\r
21826 BFD0979E 4BE5 LW RA, 20(SP)
\r
21827 BFD097A0 4BC4 LW S8, 16(SP)
\r
21828 BFD097A2 4C0D ADDIU SP, SP, 24
\r
21829 BFD097A4 459F JR16 RA
\r
21830 BFD097A6 0C00 NOP
\r
21833 213: void GPIOSetControl(enum gpio_id_t gpio_id, uint32_t ctrl_val)
\r
21835 BFD092DC 4FF1 ADDIU SP, SP, -32
\r
21836 BFD092DE CBE7 SW RA, 28(SP)
\r
21837 BFD092E0 CBC6 SW S8, 24(SP)
\r
21838 BFD092E2 0FDD MOVE S8, SP
\r
21839 BFD092E4 0020F89E SW A0, 32(S8)
\r
21840 BFD092E8 0024F8BE SW A1, 36(S8)
\r
21841 215: volatile uint32_t * p;
\r
21843 217: if (gpio_is_valid(gpio_id)) {
\r
21844 BFD092EC 0020FC9E LW A0, 32(S8)
\r
21845 BFD092F0 40DA77E8 JALS gpio_is_valid
\r
21846 BFD092F2 0C0040DA BGTZ K0, 0xBFD0AAF6
\r
21847 BFD092F4 0C00 NOP
\r
21848 BFD092F6 000C40E2 BEQZC V0, 0xBFD09312
\r
21849 218: p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);
\r
21850 BFD092FA 0020FC9E LW A0, 32(S8)
\r
21851 BFD092FE 4D9477E8 JALS gpio_pin_ctrl_addr
\r
21852 BFD09300 4D94 ADDIU T4, T4, -6
\r
21853 BFD09302 0C00 NOP
\r
21854 BFD09304 0010F85E SW V0, 16(S8)
\r
21855 219: *p = ctrl_val;
\r
21856 BFD09308 0010FC5E LW V0, 16(S8)
\r
21857 BFD0930C 0024FC7E LW V1, 36(S8)
\r
21858 BFD09310 E9A0 SW V1, 0(V0)
\r
21861 BFD09312 0FBE MOVE SP, S8
\r
21862 BFD09314 4BE7 LW RA, 28(SP)
\r
21863 BFD09316 4BC6 LW S8, 24(SP)
\r
21864 BFD09318 4C11 ADDIU SP, SP, 32
\r
21865 BFD0931A 459F JR16 RA
\r
21866 BFD0931C 0C00 NOP
\r
21869 224: void GPIOControlAndOr(enum gpio_id_t gpio_id, uint32_t and_mask, uint32_t or_mask)
\r
21871 BFD08804 4FF1 ADDIU SP, SP, -32
\r
21872 BFD08806 CBE7 SW RA, 28(SP)
\r
21873 BFD08808 CBC6 SW S8, 24(SP)
\r
21874 BFD0880A 0FDD MOVE S8, SP
\r
21875 BFD0880C 0020F89E SW A0, 32(S8)
\r
21876 BFD08810 0024F8BE SW A1, 36(S8)
\r
21877 BFD08814 0028F8DE SW A2, 40(S8)
\r
21878 226: volatile uint32_t * p;
\r
21880 228: if (gpio_is_valid(gpio_id)) {
\r
21881 BFD08818 0020FC9E LW A0, 32(S8)
\r
21882 BFD0881C 40DA77E8 JALS gpio_is_valid
\r
21883 BFD0881E 0C0040DA BGTZ K0, 0xBFD0A022
\r
21884 BFD08820 0C00 NOP
\r
21885 BFD08822 001340E2 BEQZC V0, 0xBFD0884C
\r
21886 229: p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);
\r
21887 BFD08826 0020FC9E LW A0, 32(S8)
\r
21888 BFD0882A 4D9477E8 JALS gpio_pin_ctrl_addr
\r
21889 BFD0882C 4D94 ADDIU T4, T4, -6
\r
21890 BFD0882E 0C00 NOP
\r
21891 BFD08830 0010F85E SW V0, 16(S8)
\r
21892 230: *p = (*p & and_mask) | or_mask;
\r
21893 BFD08834 0010FC5E LW V0, 16(S8)
\r
21894 BFD08838 69A0 LW V1, 0(V0)
\r
21895 BFD0883A 0024FC5E LW V0, 36(S8)
\r
21896 BFD0883E 449A AND16 V1, V0
\r
21897 BFD08840 0028FC5E LW V0, 40(S8)
\r
21898 BFD08844 44DA OR16 V1, V0
\r
21899 BFD08846 0010FC5E LW V0, 16(S8)
\r
21900 BFD0884A E9A0 SW V1, 0(V0)
\r
21903 BFD0884C 0FBE MOVE SP, S8
\r
21904 BFD0884E 4BE7 LW RA, 28(SP)
\r
21905 BFD08850 4BC6 LW S8, 24(SP)
\r
21906 BFD08852 4C11 ADDIU SP, SP, 32
\r
21907 BFD08854 459F JR16 RA
\r
21908 BFD08856 0C00 NOP
\r
21912 236: * GPIOPropertySet - Program specified GPIO Pin configuration
\r
21915 239: * @author sworley
\r
21917 241: * @param gpio_id 0-based GPIO ID
\r
21918 242: * @param gpio_prop enumerated GPIO Property(configuration item)
\r
21919 243: * @param prop_val new property value
\r
21921 245: void GPIOPropertySet ( enum gpio_id_t gpio_id,
\r
21922 246: enum gpio_prop_t gpio_prop,
\r
21923 247: uint16_t prop_val
\r
21926 BFD04B98 4FF1 ADDIU SP, SP, -32
\r
21927 BFD04B9A CBE7 SW RA, 28(SP)
\r
21928 BFD04B9C CBC6 SW S8, 24(SP)
\r
21929 BFD04B9E 0FDD MOVE S8, SP
\r
21930 BFD04BA0 0020F89E SW A0, 32(S8)
\r
21931 BFD04BA4 0024F8BE SW A1, 36(S8)
\r
21932 BFD04BA8 0C46 MOVE V0, A2
\r
21933 BFD04BAA 0028385E SH V0, 40(S8)
\r
21934 250: volatile uint16_t * p;
\r
21935 251: uint16_t gp_cfg;
\r
21937 253: gp_cfg = 0u;
\r
21938 BFD04BAE 0010381E SH ZERO, 16(S8)
\r
21940 255: if ( gpio_is_valid(gpio_id) && ((uint16_t)gpio_prop < (uint16_t)GPIO_PROP_MAX) )
\r
21941 BFD04BB2 0020FC9E LW A0, 32(S8)
\r
21942 BFD04BB6 40DA77E8 JALS gpio_is_valid
\r
21943 BFD04BB8 0C0040DA BGTZ K0, 0xBFD063BC
\r
21944 BFD04BBA 0C00 NOP
\r
21945 BFD04BBC 005140E2 BEQZC V0, 0xBFD04C62
\r
21946 BFD04BC0 0024FC5E LW V0, 36(S8)
\r
21947 BFD04BC4 2D2F ANDI V0, V0, 0xFFFF
\r
21948 BFD04BC6 0009B042 SLTIU V0, V0, 9
\r
21949 BFD04BCA 004A40E2 BEQZC V0, 0xBFD04C62
\r
21951 257: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
\r
21952 BFD04BCE 0020FC9E LW A0, 32(S8)
\r
21953 BFD04BD2 4D9477E8 JALS gpio_pin_ctrl_addr
\r
21954 BFD04BD4 4D94 ADDIU T4, T4, -6
\r
21955 BFD04BD6 0C00 NOP
\r
21956 BFD04BD8 0014F85E SW V0, 20(S8)
\r
21957 258: gp_cfg = *p;
\r
21958 BFD04BDC 0014FC5E LW V0, 20(S8)
\r
21959 BFD04BE0 2920 LHU V0, 0(V0)
\r
21960 BFD04BE2 0010385E SH V0, 16(S8)
\r
21961 259: gp_cfg &= ~(gpio_cfg_tbl[gpio_prop].bit_mask);
\r
21962 BFD04BE6 BFD141A2 LUI V0, 0xBFD1
\r
21963 BFD04BE8 FC7EBFD1 LDC1 F30, -898(S1)
\r
21964 BFD04BEA 0024FC7E LW V1, 36(S8)
\r
21965 BFD04BEE 25B4 SLL V1, V1, 2
\r
21966 BFD04BF0 92743042 ADDIU V0, V0, -28044
\r
21967 BFD04BF2 05269274 SLTI S3, S4, 1318
\r
21968 BFD04BF4 0526 ADDU V0, V1, V0
\r
21969 BFD04BF6 2920 LHU V0, 0(V0)
\r
21970 BFD04BF8 3B3C0042 SEH V0, V0
\r
21971 BFD04BFA 44123B3C SH T9, 17426(GP)
\r
21972 BFD04BFC 4412 NOT16 V0, V0
\r
21973 BFD04BFE 3B3C0062 SEH V1, V0
\r
21974 BFD04C00 3C5E3B3C SH T9, 15454(GP)
\r
21975 BFD04C02 00103C5E LH V0, 16(S8)
\r
21976 BFD04C06 4493 AND16 V0, V1
\r
21977 BFD04C08 3B3C0042 SEH V0, V0
\r
21978 BFD04C0A 385E3B3C SH T9, 14430(GP)
\r
21979 BFD04C0C 0010385E SH V0, 16(S8)
\r
21980 260: gp_cfg |= (prop_val << gpio_cfg_tbl[gpio_prop].bit_pos) &
\r
21981 BFD04C10 0028347E LHU V1, 40(S8)
\r
21982 BFD04C14 BFD141A2 LUI V0, 0xBFD1
\r
21983 BFD04C16 FC9EBFD1 LDC1 F30, -866(S1)
\r
21984 BFD04C18 0024FC9E LW A0, 36(S8)
\r
21985 BFD04C1C 2644 SLL A0, A0, 2
\r
21986 BFD04C1E 92743042 ADDIU V0, V0, -28044
\r
21987 BFD04C20 05289274 SLTI S3, S4, 1320
\r
21988 BFD04C22 0528 ADDU V0, A0, V0
\r
21989 BFD04C24 0922 LBU V0, 2(V0)
\r
21990 BFD04C26 10100062 SLLV V0, V0, V1
\r
21991 BFD04C28 00621010 ADDI ZERO, S0, 98
\r
21992 BFD04C2A 3B3C0062 SEH V1, V0
\r
21993 BFD04C2C 41A23B3C SH T9, 16802(GP)
\r
21994 BFD04C40 3B3C0042 SEH V0, V0
\r
21995 BFD04C42 44933B3C SH T9, 17555(GP)
\r
21996 BFD04C44 4493 AND16 V0, V1
\r
21997 BFD04C46 3B3C0062 SEH V1, V0
\r
21998 BFD04C48 3C5E3B3C SH T9, 15454(GP)
\r
21999 BFD04C4A 00103C5E LH V0, 16(S8)
\r
22000 BFD04C4E 44D3 OR16 V0, V1
\r
22001 BFD04C50 3B3C0042 SEH V0, V0
\r
22002 BFD04C52 385E3B3C SH T9, 14430(GP)
\r
22003 BFD04C54 0010385E SH V0, 16(S8)
\r
22004 261: gpio_cfg_tbl[gpio_prop].bit_mask;
\r
22005 BFD04C2E BFD141A2 LUI V0, 0xBFD1
\r
22006 BFD04C30 FC9EBFD1 LDC1 F30, -866(S1)
\r
22007 BFD04C32 0024FC9E LW A0, 36(S8)
\r
22008 BFD04C36 2644 SLL A0, A0, 2
\r
22009 BFD04C38 92743042 ADDIU V0, V0, -28044
\r
22010 BFD04C3A 05289274 SLTI S3, S4, 1320
\r
22011 BFD04C3C 0528 ADDU V0, A0, V0
\r
22012 BFD04C3E 2920 LHU V0, 0(V0)
\r
22013 262: *p = gp_cfg;
\r
22014 BFD04C58 0014FC5E LW V0, 20(S8)
\r
22015 BFD04C5C 0010347E LHU V1, 16(S8)
\r
22016 BFD04C60 A9A0 SH V1, 0(V0)
\r
22019 BFD04C62 0FBE MOVE SP, S8
\r
22020 BFD04C64 4BE7 LW RA, 28(SP)
\r
22021 BFD04C66 4BC6 LW S8, 24(SP)
\r
22022 BFD04C68 4C11 ADDIU SP, SP, 32
\r
22023 BFD04C6A 459F JR16 RA
\r
22024 BFD04C6C 0C00 NOP
\r
22028 268: * GPIOGetSlewRate - Return GPIO Pin Slew Rate
\r
22030 270: * @author sworley
\r
22032 272: * @param gpio_id 0-based GPIO ID
\r
22034 274: * @return uint8_t GPIO Pin Slew Rate: 0(Slow) or 1(Fast)
\r
22036 276: uint8_t GPIOGetSlewRate( enum gpio_id_t gpio_id )
\r
22038 BFD09024 4FF1 ADDIU SP, SP, -32
\r
22039 BFD09026 CBE7 SW RA, 28(SP)
\r
22040 BFD09028 CBC6 SW S8, 24(SP)
\r
22041 BFD0902A 0FDD MOVE S8, SP
\r
22042 BFD0902C 0020F89E SW A0, 32(S8)
\r
22043 278: uint32_t addr;
\r
22044 279: uint8_t slew;
\r
22046 281: addr = gpio_has_drv_str(gpio_id);
\r
22047 BFD09030 0020FC9E LW A0, 32(S8)
\r
22048 BFD09034 332277E8 JALS gpio_has_drv_str
\r
22049 BFD09036 0C003322 ADDIU T9, V0, 3072
\r
22050 BFD09038 0C00 NOP
\r
22051 BFD0903A 0014F85E SW V0, 20(S8)
\r
22052 282: if ( 0ul != addr )
\r
22053 BFD0903E 0014FC5E LW V0, 20(S8)
\r
22054 BFD09042 000940E2 BEQZC V0, 0xBFD09058
\r
22056 284: slew = ((*(volatile uint8_t *)addr) >> GPIO_DRV_SLEW_BITPOS) & 0x01u;
\r
22057 BFD09046 0014FC5E LW V0, 20(S8)
\r
22058 BFD0904A 0920 LBU V0, 0(V0)
\r
22059 BFD0904C 2D2D ANDI V0, V0, 0xFF
\r
22060 BFD0904E 2D21 ANDI V0, V0, 0x1
\r
22061 BFD09050 0010185E SB V0, 16(S8)
\r
22062 BFD09054 CC03 B 0xBFD0905C
\r
22063 BFD09056 0C00 NOP
\r
22068 BFD09058 0010181E SB ZERO, 16(S8)
\r
22071 291: return slew;
\r
22072 BFD0905C 0010145E LBU V0, 16(S8)
\r
22074 BFD09060 0FBE MOVE SP, S8
\r
22075 BFD09062 4BE7 LW RA, 28(SP)
\r
22076 BFD09064 4BC6 LW S8, 24(SP)
\r
22077 BFD09066 4C11 ADDIU SP, SP, 32
\r
22078 BFD09068 459F JR16 RA
\r
22079 BFD0906A 0C00 NOP
\r
22083 296: * GPIOSetSlewRate - Program GPIO Pin's Slew Rate
\r
22085 298: * @author sworley
\r
22087 300: * @param gpio_id 0-based GPIO ID
\r
22088 301: * @param slew_rate new slew rate: 0(Slow), Non-zero(Fast)
\r
22090 303: void GPIOSetSlewRate ( enum gpio_id_t gpio_id,
\r
22091 304: enum gpio_slew_rate_t slew_rate )
\r
22093 BFD08600 4FF1 ADDIU SP, SP, -32
\r
22094 BFD08602 CBE7 SW RA, 28(SP)
\r
22095 BFD08604 CBC6 SW S8, 24(SP)
\r
22096 BFD08606 0FDD MOVE S8, SP
\r
22097 BFD08608 0020F89E SW A0, 32(S8)
\r
22098 BFD0860C 0024F8BE SW A1, 36(S8)
\r
22099 306: uint32_t addr;
\r
22101 308: addr = gpio_has_drv_str(gpio_id );
\r
22102 BFD08610 0020FC9E LW A0, 32(S8)
\r
22103 BFD08614 332277E8 JALS gpio_has_drv_str
\r
22104 BFD08616 0C003322 ADDIU T9, V0, 3072
\r
22105 BFD08618 0C00 NOP
\r
22106 BFD0861A 0010F85E SW V0, 16(S8)
\r
22108 BFD0861E 0010FC5E LW V0, 16(S8)
\r
22109 BFD08622 001240E2 BEQZC V0, 0xBFD0864A
\r
22111 311: *(volatile uint8_t *)addr = (*(volatile uint8_t *)addr &
\r
22112 BFD08626 0010FC5E LW V0, 16(S8)
\r
22113 BFD0862A 0010FC7E LW V1, 16(S8)
\r
22114 BFD0862E 09B0 LBU V1, 0(V1)
\r
22115 BFD08630 2E3D ANDI A0, V1, 0xFF
\r
22116 BFD08632 FFFE3060 ADDIU V1, ZERO, -2
\r
22117 BFD08634 449CFFFE LW RA, 17564(S8)
\r
22118 BFD08636 449C AND16 V1, A0
\r
22119 BFD08638 2E3D ANDI A0, V1, 0xFF
\r
22120 BFD0863A 0024FC7E LW V1, 36(S8)
\r
22121 BFD0863E 2DBD ANDI V1, V1, 0xFF
\r
22122 BFD08640 2DB1 ANDI V1, V1, 0x1
\r
22123 BFD08642 2DBD ANDI V1, V1, 0xFF
\r
22124 BFD08644 44DC OR16 V1, A0
\r
22125 BFD08646 2DBD ANDI V1, V1, 0xFF
\r
22126 BFD08648 89A0 SB V1, 0(V0)
\r
22127 312: ~(GPIO_DRV_SLEW_MASK)) |
\r
22128 313: ((slew_rate << (GPIO_DRV_SLEW_BITPOS)) & (GPIO_DRV_SLEW_MASK));
\r
22131 BFD0864A 0FBE MOVE SP, S8
\r
22132 BFD0864C 4BE7 LW RA, 28(SP)
\r
22133 BFD0864E 4BC6 LW S8, 24(SP)
\r
22134 BFD08650 4C11 ADDIU SP, SP, 32
\r
22135 BFD08652 459F JR16 RA
\r
22136 BFD08654 0C00 NOP
\r
22140 319: * GPIOGetDriveStr - Get GPIO Pin's Drive Strength
\r
22142 321: * @author sworley
\r
22144 323: * @param gpio_id 0-based GPIO ID
\r
22146 325: * @return uint8_t Pin Drive Strength: 0=2mA, 1=4mA, 2=8mA,
\r
22149 328: uint8_t GPIOGetDriveStr ( enum gpio_id_t gpio_id )
\r
22151 BFD09594 4FF1 ADDIU SP, SP, -32
\r
22152 BFD09596 CBE7 SW RA, 28(SP)
\r
22153 BFD09598 CBC6 SW S8, 24(SP)
\r
22154 BFD0959A 0FDD MOVE S8, SP
\r
22155 BFD0959C 0020F89E SW A0, 32(S8)
\r
22156 330: uint32_t addr;
\r
22158 332: addr = gpio_has_drv_str(gpio_id );
\r
22159 BFD095A0 0020FC9E LW A0, 32(S8)
\r
22160 BFD095A4 332277E8 JALS gpio_has_drv_str
\r
22161 BFD095A6 0C003322 ADDIU T9, V0, 3072
\r
22162 BFD095A8 0C00 NOP
\r
22163 BFD095AA 0010F85E SW V0, 16(S8)
\r
22165 BFD095AE 0010FC5E LW V0, 16(S8)
\r
22166 BFD095B2 000640E2 BEQZC V0, 0xBFD095C2
\r
22168 335: return ((*(volatile uint8_t *)addr) >> GPIO_DRV_STR_BITPOS) & (GPIO_DRV_STR_MASK);
\r
22169 BFD095B6 0010FC5E LW V0, 16(S8)
\r
22170 BFD095BA 0920 LBU V0, 0(V0)
\r
22171 BFD095BC 0C40 MOVE V0, ZERO
\r
22172 BFD095BE CC02 B 0xBFD095C4
\r
22173 BFD095C0 0C00 NOP
\r
22178 BFD095C2 0C40 MOVE V0, ZERO
\r
22181 BFD095C4 0FBE MOVE SP, S8
\r
22182 BFD095C6 4BE7 LW RA, 28(SP)
\r
22183 BFD095C8 4BC6 LW S8, 24(SP)
\r
22184 BFD095CA 4C11 ADDIU SP, SP, 32
\r
22185 BFD095CC 459F JR16 RA
\r
22186 BFD095CE 0C00 NOP
\r
22190 345: * GPIOSetDriveStr - Program GPIO Pin's Drive Strength
\r
22192 347: * @author sworley
\r
22194 349: * @param gpio_id 0-based GPIO ID
\r
22195 350: * @param drv_str enumerated drive strength: 0=2mA, 1=4mA,
\r
22196 351: * 2=8mA, 3=12mA
\r
22198 353: void GPIOSetDriveStr ( enum gpio_id_t gpio_id,
\r
22199 354: enum gpio_drv_str_t drv_str )
\r
22201 BFD07D64 4FF1 ADDIU SP, SP, -32
\r
22202 BFD07D66 CBE7 SW RA, 28(SP)
\r
22203 BFD07D68 CBC6 SW S8, 24(SP)
\r
22204 BFD07D6A 0FDD MOVE S8, SP
\r
22205 BFD07D6C 0020F89E SW A0, 32(S8)
\r
22206 BFD07D70 0024F8BE SW A1, 36(S8)
\r
22207 356: uint32_t addr;
\r
22210 359: addr = gpio_has_drv_str(gpio_id);
\r
22211 BFD07D74 0020FC9E LW A0, 32(S8)
\r
22212 BFD07D78 332277E8 JALS gpio_has_drv_str
\r
22213 BFD07D7A 0C003322 ADDIU T9, V0, 3072
\r
22214 BFD07D7C 0C00 NOP
\r
22215 BFD07D7E 0010F85E SW V0, 16(S8)
\r
22217 BFD07D82 0010FC5E LW V0, 16(S8)
\r
22218 BFD07D86 001B40E2 BEQZC V0, 0xBFD07DC0
\r
22220 362: r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_STR_MASK);
\r
22221 BFD07D8A 0010FC5E LW V0, 16(S8)
\r
22222 BFD07D8E 0920 LBU V0, 0(V0)
\r
22223 BFD07D90 2DAD ANDI V1, V0, 0xFF
\r
22224 BFD07D92 FFCF3040 ADDIU V0, ZERO, -49
\r
22225 BFD07D94 4493FFCF LW S8, 17555(T7)
\r
22226 BFD07D96 4493 AND16 V0, V1
\r
22227 BFD07D98 0014185E SB V0, 20(S8)
\r
22228 363: r8 += ((drv_str << GPIO_DRV_STR_BITPOS) & GPIO_DRV_STR_MASK);
\r
22229 BFD07D9C 0024FC5E LW V0, 36(S8)
\r
22230 BFD07DA0 2D2D ANDI V0, V0, 0xFF
\r
22231 BFD07DA2 2528 SLL V0, V0, 4
\r
22232 BFD07DA4 2D2D ANDI V0, V0, 0xFF
\r
22233 BFD07DA6 0030D042 ANDI V0, V0, 48
\r
22234 BFD07DAA 2DAD ANDI V1, V0, 0xFF
\r
22235 BFD07DAC 0014145E LBU V0, 20(S8)
\r
22236 BFD07DB0 0526 ADDU V0, V1, V0
\r
22237 BFD07DB2 0014185E SB V0, 20(S8)
\r
22238 364: *(volatile uint8_t *)addr = r8;
\r
22239 BFD07DB6 0010FC5E LW V0, 16(S8)
\r
22240 BFD07DBA 0014147E LBU V1, 20(S8)
\r
22241 BFD07DBE 89A0 SB V1, 0(V0)
\r
22244 BFD07DC0 0FBE MOVE SP, S8
\r
22245 BFD07DC2 4BE7 LW RA, 28(SP)
\r
22246 BFD07DC4 4BC6 LW S8, 24(SP)
\r
22247 BFD07DC6 4C11 ADDIU SP, SP, 32
\r
22248 BFD07DC8 459F JR16 RA
\r
22249 BFD07DCA 0C00 NOP
\r
22253 370: * GPIOGetDriveStrAndSlew - Return combined value representing
\r
22254 371: * Drive Strength and Slew Rate.
\r
22256 373: * @author sworley
\r
22258 375: * @param gpio_id 0-based GPIO ID
\r
22260 377: * @return uint8_t bit[0] = Slew Rate, bits[3:1]=0(Reserved),
\r
22261 378: * bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)
\r
22263 380: uint8_t GPIOGetDriveStrAndSlew ( enum gpio_id_t gpio_id )
\r
22265 BFD095D0 4FF1 ADDIU SP, SP, -32
\r
22266 BFD095D2 CBE7 SW RA, 28(SP)
\r
22267 BFD095D4 CBC6 SW S8, 24(SP)
\r
22268 BFD095D6 0FDD MOVE S8, SP
\r
22269 BFD095D8 0020F89E SW A0, 32(S8)
\r
22270 382: uint32_t addr;
\r
22272 384: addr = gpio_has_drv_str(gpio_id );
\r
22273 BFD095DC 0020FC9E LW A0, 32(S8)
\r
22274 BFD095E0 332277E8 JALS gpio_has_drv_str
\r
22275 BFD095E2 0C003322 ADDIU T9, V0, 3072
\r
22276 BFD095E4 0C00 NOP
\r
22277 BFD095E6 0010F85E SW V0, 16(S8)
\r
22279 BFD095EA 0010FC5E LW V0, 16(S8)
\r
22280 BFD095EE 000640E2 BEQZC V0, 0xBFD095FE
\r
22282 387: return (*(volatile uint8_t *)addr);
\r
22283 BFD095F2 0010FC5E LW V0, 16(S8)
\r
22284 BFD095F6 0920 LBU V0, 0(V0)
\r
22285 BFD095F8 2D2D ANDI V0, V0, 0xFF
\r
22286 BFD095FA CC02 B 0xBFD09600
\r
22287 BFD095FC 0C00 NOP
\r
22292 BFD095FE 0C40 MOVE V0, ZERO
\r
22295 BFD09600 0FBE MOVE SP, S8
\r
22296 BFD09602 4BE7 LW RA, 28(SP)
\r
22297 BFD09604 4BC6 LW S8, 24(SP)
\r
22298 BFD09606 4C11 ADDIU SP, SP, 32
\r
22299 BFD09608 459F JR16 RA
\r
22300 BFD0960A 0C00 NOP
\r
22304 397: * GPIOSetDriveStrAndSlew - Program GPIO Pin's drive strength
\r
22305 398: * and slew rate.
\r
22307 400: * @author sworley
\r
22309 402: * @param gpio_id 0-based GPIO ID
\r
22310 403: * @param drv_and_slew bit[0] = Slew Rate, bits[3:1]=0(Reserved),
\r
22311 404: * bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)
\r
22313 406: void GPIOSetDriveStrAndSlew ( enum gpio_id_t gpio_id,
\r
22314 407: uint8_t drv_and_slew )
\r
22316 BFD0802C 4FF1 ADDIU SP, SP, -32
\r
22317 BFD0802E CBE7 SW RA, 28(SP)
\r
22318 BFD08030 CBC6 SW S8, 24(SP)
\r
22319 BFD08032 0FDD MOVE S8, SP
\r
22320 BFD08034 0020F89E SW A0, 32(S8)
\r
22321 BFD08036 0C450020 CMP.LT.PH AT, ZERO
\r
22322 BFD08038 0C45 MOVE V0, A1
\r
22323 BFD0803A 0024185E SB V0, 36(S8)
\r
22324 409: uint32_t addr;
\r
22327 412: addr = gpio_has_drv_str(gpio_id);
\r
22328 BFD0803E 0020FC9E LW A0, 32(S8)
\r
22329 BFD08042 332277E8 JALS gpio_has_drv_str
\r
22330 BFD08044 0C003322 ADDIU T9, V0, 3072
\r
22331 BFD08046 0C00 NOP
\r
22332 BFD08048 0010F85E SW V0, 16(S8)
\r
22334 BFD0804C 0010FC5E LW V0, 16(S8)
\r
22335 BFD08050 001840E2 BEQZC V0, 0xBFD08084
\r
22337 415: r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK);
\r
22338 BFD08054 0010FC5E LW V0, 16(S8)
\r
22339 BFD08058 0920 LBU V0, 0(V0)
\r
22340 BFD0805A 2DAD ANDI V1, V0, 0xFF
\r
22341 BFD0805C FFCE3040 ADDIU V0, ZERO, -50
\r
22342 BFD0805E 4493FFCE LW S8, 17555(T6)
\r
22343 BFD08060 4493 AND16 V0, V1
\r
22344 BFD08062 0014185E SB V0, 20(S8)
\r
22345 416: r8 |= (drv_and_slew & (GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK));
\r
22346 BFD08066 0024145E LBU V0, 36(S8)
\r
22347 BFD0806A 0031D042 ANDI V0, V0, 49
\r
22348 BFD0806E 2DAD ANDI V1, V0, 0xFF
\r
22349 BFD08070 0014145E LBU V0, 20(S8)
\r
22350 BFD08074 44D3 OR16 V0, V1
\r
22351 BFD08076 0014185E SB V0, 20(S8)
\r
22352 417: *(volatile uint8_t *)addr = r8;
\r
22353 BFD0807A 0010FC5E LW V0, 16(S8)
\r
22354 BFD0807E 0014147E LBU V1, 20(S8)
\r
22355 BFD08082 89A0 SB V1, 0(V0)
\r
22358 BFD08084 0FBE MOVE SP, S8
\r
22359 BFD08086 4BE7 LW RA, 28(SP)
\r
22360 BFD08088 4BC6 LW S8, 24(SP)
\r
22361 BFD0808A 4C11 ADDIU SP, SP, 32
\r
22362 BFD0808C 459F JR16 RA
\r
22363 BFD0808E 0C00 NOP
\r
22367 423: * GPIOSetOutput - Program GPIO Pin's output state using Pin
\r
22368 424: * configuration register (not parallel output register).
\r
22370 426: * @author sworley
\r
22372 428: * @param gpio_id 0-based GPIO ID
\r
22373 429: * @param gpio_state pin state: actual pin state at pad will
\r
22374 430: * depend upon GPIO Output invert
\r
22375 431: * configuration.
\r
22376 432: * @note peforms a byte wide write to byte offset 2 of the GPIO
\r
22377 433: * Pin's 32-bit configuration register. No
\r
22378 434: * read-modify-write.
\r
22380 436: void GPIOSetOutput ( enum gpio_id_t gpio_id,
\r
22381 437: uint8_t gpio_state
\r
22384 BFD08658 4FF1 ADDIU SP, SP, -32
\r
22385 BFD0865A CBE7 SW RA, 28(SP)
\r
22386 BFD0865C CBC6 SW S8, 24(SP)
\r
22387 BFD0865E 0FDD MOVE S8, SP
\r
22388 BFD08660 0020F89E SW A0, 32(S8)
\r
22389 BFD08662 0C450020 CMP.LT.PH AT, ZERO
\r
22390 BFD08664 0C45 MOVE V0, A1
\r
22391 BFD08666 0024185E SB V0, 36(S8)
\r
22392 440: volatile uint8_t * p;
\r
22394 442: if ( gpio_is_valid(gpio_id) )
\r
22395 BFD0866A 0020FC9E LW A0, 32(S8)
\r
22396 BFD0866E 40DA77E8 JALS gpio_is_valid
\r
22397 BFD08670 0C0040DA BGTZ K0, 0xBFD09E74
\r
22398 BFD08672 0C00 NOP
\r
22399 BFD08674 001540E2 BEQZC V0, 0xBFD086A2
\r
22401 444: p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);
\r
22402 BFD08678 0020FC9E LW A0, 32(S8)
\r
22403 BFD0867C 4D9477E8 JALS gpio_pin_ctrl_addr
\r
22404 BFD0867E 4D94 ADDIU T4, T4, -6
\r
22405 BFD08680 0C00 NOP
\r
22406 BFD08682 4C44 ADDIU V0, V0, 2
\r
22407 BFD08684 0010F85E SW V0, 16(S8)
\r
22408 445: if (gpio_state) {
\r
22409 BFD08688 0024145E LBU V0, 36(S8)
\r
22410 BFD0868C 000640E2 BEQZC V0, 0xBFD0869C
\r
22412 BFD08690 0010FC5E LW V0, 16(S8)
\r
22413 BFD08694 ED81 LI V1, 1
\r
22414 BFD08696 89A0 SB V1, 0(V0)
\r
22415 BFD08698 CC04 B 0xBFD086A2
\r
22416 BFD0869A 0C00 NOP
\r
22419 BFD0869C 0010FC5E LW V0, 16(S8)
\r
22420 BFD086A0 8820 SB S0, 0(V0)
\r
22424 BFD086A2 0FBE MOVE SP, S8
\r
22425 BFD086A4 4BE7 LW RA, 28(SP)
\r
22426 BFD086A6 4BC6 LW S8, 24(SP)
\r
22427 BFD086A8 4C11 ADDIU SP, SP, 32
\r
22428 BFD086AA 459F JR16 RA
\r
22429 BFD086AC 0C00 NOP
\r
22432 454: void GPIOToggleOutput ( enum gpio_id_t gpio_id )
\r
22434 BFD08C5C 4FF1 ADDIU SP, SP, -32
\r
22435 BFD08C5E CBE7 SW RA, 28(SP)
\r
22436 BFD08C60 CBC6 SW S8, 24(SP)
\r
22437 BFD08C62 0FDD MOVE S8, SP
\r
22438 BFD08C64 0020F89E SW A0, 32(S8)
\r
22439 456: volatile uint8_t * p;
\r
22441 458: if ( gpio_is_valid(gpio_id) )
\r
22442 BFD08C68 0020FC9E LW A0, 32(S8)
\r
22443 BFD08C6C 40DA77E8 JALS gpio_is_valid
\r
22444 BFD08C6E 0C0040DA BGTZ K0, 0xBFD0A472
\r
22445 BFD08C70 0C00 NOP
\r
22446 BFD08C72 001240E2 BEQZC V0, 0xBFD08C9A
\r
22448 460: p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);
\r
22449 BFD08C76 0020FC9E LW A0, 32(S8)
\r
22450 BFD08C7A 4D9477E8 JALS gpio_pin_ctrl_addr
\r
22451 BFD08C7C 4D94 ADDIU T4, T4, -6
\r
22452 BFD08C7E 0C00 NOP
\r
22453 BFD08C80 4C44 ADDIU V0, V0, 2
\r
22454 BFD08C82 0010F85E SW V0, 16(S8)
\r
22455 461: *p ^= 0x01u;
\r
22456 BFD08C86 0010FC5E LW V0, 16(S8)
\r
22457 BFD08C8A 0920 LBU V0, 0(V0)
\r
22458 BFD08C8C 2D2D ANDI V0, V0, 0xFF
\r
22459 BFD08C8E 00017042 XORI V0, V0, 1
\r
22460 BFD08C92 2DAD ANDI V1, V0, 0xFF
\r
22461 BFD08C94 0010FC5E LW V0, 16(S8)
\r
22462 BFD08C98 89A0 SB V1, 0(V0)
\r
22465 BFD08C9A 0FBE MOVE SP, S8
\r
22466 BFD08C9C 4BE7 LW RA, 28(SP)
\r
22467 BFD08C9E 4BC6 LW S8, 24(SP)
\r
22468 BFD08CA0 4C11 ADDIU SP, SP, 32
\r
22469 BFD08CA2 459F JR16 RA
\r
22470 BFD08CA4 0C00 NOP
\r
22474 467: * GPIOReadPin - Read GPIO Pin's Pad Input from configuration
\r
22475 468: * register.
\r
22477 470: * @author sworley
\r
22479 472: * @param gpio_id 0-based GPIO ID.
\r
22481 474: * @return uint8_t 0 or 1 depending upon the state of the GPIO
\r
22483 476: * @note performs a byte read of offset 3 of the GPIO Pin's
\r
22484 477: * 32-bit configuration register.
\r
22486 479: uint8_t GPIOReadPin( enum gpio_id_t gpio_id )
\r
22488 BFD0960C 4FF5 ADDIU SP, SP, -24
\r
22489 BFD0960E CBE5 SW RA, 20(SP)
\r
22490 BFD09610 CBC4 SW S8, 16(SP)
\r
22491 BFD09612 0FDD MOVE S8, SP
\r
22492 BFD09614 0018F89E SW A0, 24(S8)
\r
22493 481: if ( gpio_is_valid(gpio_id) )
\r
22494 BFD09618 0018FC9E LW A0, 24(S8)
\r
22495 BFD0961C 40DA77E8 JALS gpio_is_valid
\r
22496 BFD0961E 0C0040DA BGTZ K0, 0xBFD0AE22
\r
22497 BFD09620 0C00 NOP
\r
22498 BFD09622 000A40E2 BEQZC V0, 0xBFD0963A
\r
22500 483: return *((volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 3ul));
\r
22501 BFD09626 0018FC9E LW A0, 24(S8)
\r
22502 BFD0962A 4D9477E8 JALS gpio_pin_ctrl_addr
\r
22503 BFD0962C 4D94 ADDIU T4, T4, -6
\r
22504 BFD0962E 0C00 NOP
\r
22505 BFD09630 4C46 ADDIU V0, V0, 3
\r
22506 BFD09632 0920 LBU V0, 0(V0)
\r
22507 BFD09634 2D2D ANDI V0, V0, 0xFF
\r
22508 BFD09636 CC02 B 0xBFD0963C
\r
22509 BFD09638 0C00 NOP
\r
22514 BFD0963A 0C40 MOVE V0, ZERO
\r
22517 BFD0963C 0FBE MOVE SP, S8
\r
22518 BFD0963E 4BE5 LW RA, 20(SP)
\r
22519 BFD09640 4BC4 LW S8, 16(SP)
\r
22520 BFD09642 4C0D ADDIU SP, SP, 24
\r
22521 BFD09644 459F JR16 RA
\r
22522 BFD09646 0C00 NOP
\r
22525 492: /** GPIOPinLock - Lock specified GPIO's control register.
\r
22526 493: * @param enum gpio_id_t zero based GPIO ID
\r
22527 494: * @note Lock bit is only cleared on POR. Lock registers
\r
22528 495: * are in reverse order, first register is at top address.
\r
22529 496: * GPIO_LOCK_BASE defined to top(first) register address.
\r
22531 498: void GPIOPinLock(enum gpio_id_t gpio_id)
\r
22533 BFD07ADC 4FF1 ADDIU SP, SP, -32
\r
22534 BFD07ADE CBE7 SW RA, 28(SP)
\r
22535 BFD07AE0 CBC6 SW S8, 24(SP)
\r
22536 BFD07AE2 0FDD MOVE S8, SP
\r
22537 BFD07AE4 0020F89E SW A0, 32(S8)
\r
22538 500: uint32_t addr;
\r
22539 501: uint8_t bank, bitpos;
\r
22541 503: if (gpio_is_valid(gpio_id)) {
\r
22542 BFD07AE8 0020FC9E LW A0, 32(S8)
\r
22543 BFD07AEC 40DA77E8 JALS gpio_is_valid
\r
22544 BFD07AEE 0C0040DA BGTZ K0, 0xBFD092F2
\r
22545 BFD07AF0 0C00 NOP
\r
22546 BFD07AF2 002440E2 BEQZC V0, 0xBFD07B3E
\r
22547 504: bank = gpio_bank_num(gpio_id); // 0 - 4
\r
22548 BFD07AF6 0020FC9E LW A0, 32(S8)
\r
22549 BFD07AFA 4E9677E8 JALS gpio_bank_num
\r
22550 BFD07AFC 4E96 ADDIU S4, S4, -5
\r
22551 BFD07AFE 0C00 NOP
\r
22552 BFD07B00 0010185E SB V0, 16(S8)
\r
22553 505: bitpos = gpio_pin_num(gpio_id); // 0 - 31
\r
22554 BFD07B04 0020FC9E LW A0, 32(S8)
\r
22555 BFD07B08 4EA677E8 JALS gpio_pin_num
\r
22556 BFD07B0A 4EA6 ADDIU S5, S5, 3
\r
22557 BFD07B0C 0C00 NOP
\r
22558 BFD07B0E 0011185E SB V0, 17(S8)
\r
22559 506: addr = (uint32_t)(GPIO_LOCK_BASE) - (bank << 2);
\r
22560 BFD07B12 0010145E LBU V0, 16(S8)
\r
22561 BFD07B16 2524 SLL V0, V0, 2
\r
22562 BFD07B18 A00841A3 LUI V1, 0xA008
\r
22563 BFD07B1C 13F05063 ORI V1, V1, 5104
\r
22564 BFD07B1E 052713F0 ADDI RA, S0, 1319
\r
22565 BFD07B20 0527 SUBU V0, V1, V0
\r
22566 BFD07B22 0014F85E SW V0, 20(S8)
\r
22567 507: *(volatile uint32_t *)addr |= (1ul << bitpos);
\r
22568 BFD07B26 0014FC5E LW V0, 20(S8)
\r
22569 BFD07B2A 0014FC7E LW V1, 20(S8)
\r
22570 BFD07B2E 6A30 LW A0, 0(V1)
\r
22571 BFD07B30 0011147E LBU V1, 17(S8)
\r
22572 BFD07B34 EE81 LI A1, 1
\r
22573 BFD07B36 181000A3 SLLV V1, V1, A1
\r
22574 BFD07B38 44DC1810 SB ZERO, 17628(S0)
\r
22575 BFD07B3A 44DC OR16 V1, A0
\r
22576 BFD07B3C E9A0 SW V1, 0(V0)
\r
22579 BFD07B3E 0FBE MOVE SP, S8
\r
22580 BFD07B40 4BE7 LW RA, 28(SP)
\r
22581 BFD07B42 4BC6 LW S8, 24(SP)
\r
22582 BFD07B44 4C11 ADDIU SP, SP, 32
\r
22583 BFD07B46 459F JR16 RA
\r
22584 BFD07B48 0C00 NOP
\r
22587 512: /* end mec14xx_gpio.c */
\r
22591 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_bbled.c --------
\r
22592 1: /*****************************************************************************
\r
22593 2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.
\r
22594 3: * You may use this software and any derivatives exclusively with
\r
22595 4: * Microchip products.
\r
22596 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
22597 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
22598 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
22599 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
22600 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
22601 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
22602 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
22603 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
22604 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
22605 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
22606 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
22607 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
22608 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
22609 18: * OF THESE TERMS.
\r
22610 19: *****************************************************************************/
\r
22612 21: /** @file mec14xx_bbled.c
\r
22613 22: *MEC14xx Breating-Blinking LED definitions
\r
22615 24: /** @defgroup MEC14xx Peripherals BBLED
\r
22618 27: #include "appcfg.h"
\r
22619 28: #include "platform.h"
\r
22620 29: #include "MEC14xx/mec14xx.h"
\r
22621 30: #include "MEC14xx/mec14xx_pcr.h"
\r
22622 31: #include "MEC14xx/mec14xx_bbled.h"
\r
22623 32: #include "MEC14xx/mec14xx_gpio.h"
\r
22624 33: #include "MEC14xx/mec14xx_bbled.h"
\r
22626 35: #ifdef __cplusplus
\r
22631 40: static uint32_t led_addr(uint8_t led_id)
\r
22633 BFD09420 4FB0 ADDIU SP, SP, -8
\r
22634 BFD09422 CBC1 SW S8, 4(SP)
\r
22635 BFD09424 0FDD MOVE S8, SP
\r
22636 BFD09426 0C44 MOVE V0, A0
\r
22637 BFD09428 0008185E SB V0, 8(S8)
\r
22638 42: if (led_id < (LED_ID_MAX) )
\r
22639 BFD0942C 0008145E LBU V0, 8(S8)
\r
22640 BFD09430 0003B042 SLTIU V0, V0, 3
\r
22641 BFD09434 000B40E2 BEQZC V0, 0xBFD0944E
\r
22643 44: return ((LED0_BASE) + (led_id << 8));
\r
22644 BFD09438 0008145E LBU V0, 8(S8)
\r
22645 BFD0943C 2520 SLL V0, V0, 8
\r
22646 BFD0943E 0C62 MOVE V1, V0
\r
22647 BFD09440 A00041A2 LUI V0, 0xA000
\r
22648 BFD09444 B8005042 ORI V0, V0, -18432
\r
22649 BFD09446 0526B800 SDC1 F0, 1318(ZERO)
\r
22650 BFD09448 0526 ADDU V0, V1, V0
\r
22651 BFD0944A CC05 B 0xBFD09456
\r
22652 BFD0944C 0C00 NOP
\r
22656 48: return (LED0_BASE);
\r
22657 BFD0944E A00041A2 LUI V0, 0xA000
\r
22658 BFD09452 B8005042 ORI V0, V0, -18432
\r
22659 BFD09454 0FBEB800 SDC1 F0, 4030(ZERO)
\r
22662 BFD09456 0FBE MOVE SP, S8
\r
22663 BFD09458 4BC1 LW S8, 4(SP)
\r
22664 BFD0945A 4C05 ADDIU SP, SP, 8
\r
22665 BFD0945C 459F JR16 RA
\r
22666 BFD0945E 0C00 NOP
\r
22668 52: #ifdef LED_ENABLE_VALID_CHECK
\r
22670 54: static uint8_t led_is_valid(uint8_t led_id)
\r
22672 56: if (led_id < (LED_ID_MAX)) {
\r
22675 59: return false;
\r
22680 64: static uint8_t led_is_valid(uint8_t led_id) { ( void ) led_id; return (MEC14XX_TRUE); }
\r
22681 BFD09E6C 4FB0 ADDIU SP, SP, -8
\r
22682 BFD09E6E CBC1 SW S8, 4(SP)
\r
22683 BFD09E70 0FDD MOVE S8, SP
\r
22684 BFD09E72 0C44 MOVE V0, A0
\r
22685 BFD09E74 0008185E SB V0, 8(S8)
\r
22686 BFD09E78 ED01 LI V0, 1
\r
22687 BFD09E7A 0FBE MOVE SP, S8
\r
22688 BFD09E7C 4BC1 LW S8, 4(SP)
\r
22689 BFD09E7E 4C05 ADDIU SP, SP, 8
\r
22690 BFD09E80 459F JR16 RA
\r
22691 BFD09E82 0C00 NOP
\r
22697 70: @brief MEC1404 LED are alternate functions of GPIO pins.
\r
22699 72: LED0 is GPIO157 Function 1
\r
22700 73: LED1 is GPIO156 Function 1
\r
22701 74: LED2 is GPIO104 Function 1
\r
22704 77: static const uint8_t led_pcr_slp2_bitpos[LED_ID_MAX] = {
\r
22705 78: (PCR_EC2_LED0_SLP_BITPOS),
\r
22706 79: (PCR_EC2_LED1_SLP_BITPOS),
\r
22707 80: (PCR_EC2_LED2_SLP_BITPOS)
\r
22711 84: static const uint16_t led_gpio_tbl[LED_ID_MAX] = {
\r
22712 85: (((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0157_ID),
\r
22713 86: (((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0156_ID),
\r
22714 87: (((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0104_ID)
\r
22720 93: * led_sleep_en - Enable/Disable gating of clocks on idle to the
\r
22721 94: * BBLED block
\r
22724 97: * @param uint8_t sleep_en (1=Enable sleep on idle), (0=No sleep
\r
22726 99: * @param uint8_t LED ID (0-3)
\r
22727 100: * @note if LED ID > 3 no action taken.
\r
22729 102: void led_sleep_en(uint8_t led_id, uint8_t sleep_en)
\r
22731 BFD05D0C 4FF1 ADDIU SP, SP, -32
\r
22732 BFD05D0E CBE7 SW RA, 28(SP)
\r
22733 BFD05D10 CBC6 SW S8, 24(SP)
\r
22734 BFD05D12 0FDD MOVE S8, SP
\r
22735 BFD05D14 0C64 MOVE V1, A0
\r
22736 BFD05D16 0C45 MOVE V0, A1
\r
22737 BFD05D18 0020187E SB V1, 32(S8)
\r
22738 BFD05D1C 0024185E SB V0, 36(S8)
\r
22739 104: uint32_t slp_mask;
\r
22740 105: uint32_t laddr;
\r
22742 107: slp_mask = 0ul;
\r
22743 BFD05D20 0010F81E SW ZERO, 16(S8)
\r
22744 108: if ( led_is_valid(led_id) ) {
\r
22745 BFD05D24 0020145E LBU V0, 32(S8)
\r
22746 BFD05D28 0C82 MOVE A0, V0
\r
22747 BFD05D2A 4F3677E8 JALS led_is_valid
\r
22748 BFD05D2C 4F36 ADDIU T9, T9, -5
\r
22749 BFD05D2E 0C00 NOP
\r
22750 BFD05D30 003F40E2 BEQZC V0, 0xBFD05DB2
\r
22751 109: slp_mask = (1ul << led_pcr_slp2_bitpos[led_id]);
\r
22752 BFD05D34 0020147E LBU V1, 32(S8)
\r
22753 BFD05D38 BFD041A2 LUI V0, 0xBFD0
\r
22754 BFD05D3A 3042BFD0 LDC1 F30, 12354(S0)
\r
22755 BFD05D3C 01743042 ADDIU V0, V0, 372
\r
22756 BFD05D40 0526 ADDU V0, V1, V0
\r
22757 BFD05D42 0920 LBU V0, 0(V0)
\r
22758 BFD05D44 ED81 LI V1, 1
\r
22759 BFD05D46 10100062 SLLV V0, V0, V1
\r
22760 BFD05D48 F85E1010 ADDI ZERO, S0, -1954
\r
22761 BFD05D4A 0010F85E SW V0, 16(S8)
\r
22762 110: if ( sleep_en ) {
\r
22763 BFD05D4E 0024145E LBU V0, 36(S8)
\r
22764 BFD05D52 002040E2 BEQZC V0, 0xBFD05D96
\r
22765 111: PCR->EC_SLEEP_EN2 |= slp_mask;
\r
22766 BFD05D56 A00841A2 LUI V0, 0xA008
\r
22767 BFD05D5A 01005042 ORI V0, V0, 256
\r
22768 BFD05D5E A00841A3 LUI V1, 0xA008
\r
22769 BFD05D62 01005063 ORI V1, V1, 256
\r
22770 BFD05D66 6A39 LW A0, 36(V1)
\r
22771 BFD05D68 0010FC7E LW V1, 16(S8)
\r
22772 BFD05D6C 44DC OR16 V1, A0
\r
22773 BFD05D6E E9A9 SW V1, 36(V0)
\r
22774 112: laddr = led_addr(led_id);
\r
22775 BFD05D70 0020145E LBU V0, 32(S8)
\r
22776 BFD05D74 0C82 MOVE A0, V0
\r
22777 BFD05D76 4A1077E8 JALS led_addr
\r
22778 BFD05D78 4A10 LW S0, 64(SP)
\r
22779 BFD05D7A 0C00 NOP
\r
22780 BFD05D7C 0014F85E SW V0, 20(S8)
\r
22781 113: ((BBLED_TypeDef *)laddr)->CONFIG &= ~(0x03ul);
\r
22782 BFD05D80 0014FC5E LW V0, 20(S8)
\r
22783 BFD05D84 0014FC7E LW V1, 20(S8)
\r
22784 BFD05D88 6A30 LW A0, 0(V1)
\r
22785 BFD05D8A FFFC3060 ADDIU V1, ZERO, -4
\r
22786 BFD05D8C 449CFFFC LW RA, 17564(GP)
\r
22787 BFD05D8E 449C AND16 V1, A0
\r
22788 BFD05D90 E9A0 SW V1, 0(V0)
\r
22789 BFD05D92 CC0F B 0xBFD05DB2
\r
22790 BFD05D94 0C00 NOP
\r
22792 115: PCR->EC_SLEEP_EN2 &= ~(slp_mask);
\r
22793 BFD05D96 A00841A2 LUI V0, 0xA008
\r
22794 BFD05D9A 01005042 ORI V0, V0, 256
\r
22795 BFD05D9E A00841A3 LUI V1, 0xA008
\r
22796 BFD05DA2 01005063 ORI V1, V1, 256
\r
22797 BFD05DA6 6A39 LW A0, 36(V1)
\r
22798 BFD05DA8 0010FC7E LW V1, 16(S8)
\r
22799 BFD05DAC 441B NOT16 V1, V1
\r
22800 BFD05DAE 449C AND16 V1, A0
\r
22801 BFD05DB0 E9A9 SW V1, 36(V0)
\r
22805 BFD05DB2 0FBE MOVE SP, S8
\r
22806 BFD05DB4 4BE7 LW RA, 28(SP)
\r
22807 BFD05DB6 4BC6 LW S8, 24(SP)
\r
22808 BFD05DB8 4C11 ADDIU SP, SP, 32
\r
22809 BFD05DBA 459F JR16 RA
\r
22810 BFD05DBC 0C00 NOP
\r
22814 122: * led_reset - Reset the specified LED hardware block.
\r
22816 124: * @author sworley
\r
22818 126: * @param led_id 0-based LED ID
\r
22819 127: * @note Sets the LED's soft reset bit and waits for hardware to
\r
22820 128: * clear it. Will wait up to 0x10000 times.
\r
22822 130: void led_reset(uint8_t led_id)
\r
22824 BFD07FC8 4FF1 ADDIU SP, SP, -32
\r
22825 BFD07FCA CBE7 SW RA, 28(SP)
\r
22826 BFD07FCC CBC6 SW S8, 24(SP)
\r
22827 BFD07FCE 0FDD MOVE S8, SP
\r
22828 BFD07FD0 0C44 MOVE V0, A0
\r
22829 BFD07FD2 0020185E SB V0, 32(S8)
\r
22831 133: uint32_t cnt;
\r
22833 135: p = led_addr(led_id);
\r
22834 BFD07FD6 0020145E LBU V0, 32(S8)
\r
22835 BFD07FDA 0C82 MOVE A0, V0
\r
22836 BFD07FDC 4A1077E8 JALS led_addr
\r
22837 BFD07FDE 4A10 LW S0, 64(SP)
\r
22838 BFD07FE0 0C00 NOP
\r
22839 BFD07FE2 0014F85E SW V0, 20(S8)
\r
22840 136: ((BBLED_TypeDef *)p)->CONFIG = (LED_CFG_RESET);
\r
22841 BFD07FE6 0014FC5E LW V0, 20(S8)
\r
22842 BFD07FEA 00803060 ADDIU V1, ZERO, 128
\r
22843 BFD07FEE E9A0 SW V1, 0(V0)
\r
22845 138: cnt = 0x100000UL;
\r
22846 BFD07FF0 001041A2 LUI V0, 0x10
\r
22847 BFD07FF4 0010F85E SW V0, 16(S8)
\r
22848 139: while ( ((BBLED_TypeDef *)p)->CONFIG & (LED_CFG_RESET) ) {
\r
22849 BFD07FF8 CC0A B 0xBFD0800E
\r
22850 BFD07FFA 0C00 NOP
\r
22851 BFD0800E 0014FC5E LW V0, 20(S8)
\r
22852 BFD08012 6920 LW V0, 0(V0)
\r
22853 BFD08014 2D20 ANDI V0, V0, 0x80
\r
22854 BFD08016 FFF140A2 BNEZC V0, 0xBFD07FFC
\r
22855 BFD08018 CC02FFF1 LW RA, -13310(S1)
\r
22856 BFD0801A CC02 B 0xBFD08020
\r
22857 BFD0801C 0C00 NOP
\r
22858 140: if ( cnt != 0UL ) {
\r
22859 BFD07FFC 0010FC5E LW V0, 16(S8)
\r
22860 BFD08000 000D40E2 BEQZC V0, 0xBFD0801E
\r
22862 BFD08004 0010FC5E LW V0, 16(S8)
\r
22863 BFD08008 6D2E ADDIU V0, V0, -1
\r
22864 BFD0800A 0010F85E SW V0, 16(S8)
\r
22867 BFD0801E 0C00 NOP
\r
22871 BFD08020 0FBE MOVE SP, S8
\r
22872 BFD08022 4BE7 LW RA, 28(SP)
\r
22873 BFD08024 4BC6 LW S8, 24(SP)
\r
22874 BFD08026 4C11 ADDIU SP, SP, 32
\r
22875 BFD08028 459F JR16 RA
\r
22876 BFD0802A 0C00 NOP
\r
22879 149: uint8_t led_get_gpio_num(uint8_t led_id)
\r
22881 BFD099EC 4FB0 ADDIU SP, SP, -8
\r
22882 BFD099EE CBC1 SW S8, 4(SP)
\r
22883 BFD099F0 0FDD MOVE S8, SP
\r
22884 BFD099F2 0C44 MOVE V0, A0
\r
22885 BFD099F4 0008185E SB V0, 8(S8)
\r
22886 151: return led_gpio_tbl[(led_id & ((LED_ID_MAX)-1u))];
\r
22887 BFD099F8 0008145E LBU V0, 8(S8)
\r
22888 BFD099FC 2DA2 ANDI V1, V0, 0x2
\r
22889 BFD099FE BFD041A2 LUI V0, 0xBFD0
\r
22890 BFD09A00 25B2BFD0 LDC1 F30, 9650(S0)
\r
22891 BFD09A02 25B2 SLL V1, V1, 1
\r
22892 BFD09A04 01783042 ADDIU V0, V0, 376
\r
22893 BFD09A08 0526 ADDU V0, V1, V0
\r
22894 BFD09A0A 2920 LHU V0, 0(V0)
\r
22895 BFD09A0C 2D2D ANDI V0, V0, 0xFF
\r
22897 BFD09A0E 0FBE MOVE SP, S8
\r
22898 BFD09A10 4BC1 LW S8, 4(SP)
\r
22899 BFD09A12 4C05 ADDIU SP, SP, 8
\r
22900 BFD09A14 459F JR16 RA
\r
22901 BFD09A16 0C00 NOP
\r
22905 156: * led_init - Initialize the specified LED
\r
22907 158: * @author sworley
\r
22909 160: * @param led_id 0-based LED ID
\r
22910 161: * @note Configures the LED's GPIO pin for LED function and then
\r
22911 162: * peforms a soft reset of the LED hardware.
\r
22913 164: void led_init(uint8_t led_id)
\r
22915 BFD07CFC 4FF1 ADDIU SP, SP, -32
\r
22916 BFD07CFE CBE7 SW RA, 28(SP)
\r
22917 BFD07D00 CBC6 SW S8, 24(SP)
\r
22918 BFD07D02 0FDD MOVE S8, SP
\r
22919 BFD07D04 0C44 MOVE V0, A0
\r
22920 BFD07D06 0020185E SB V0, 32(S8)
\r
22921 166: uint16_t ledi;
\r
22923 168: if ( led_id < LED_ID_MAX )
\r
22924 BFD07D0A 0020145E LBU V0, 32(S8)
\r
22925 BFD07D0E 0003B042 SLTIU V0, V0, 3
\r
22926 BFD07D12 002040E2 BEQZC V0, 0xBFD07D56
\r
22928 170: /* bits[7:0] = GPIO_ID, bits[15:8] = GPIO Function */
\r
22929 171: ledi = led_gpio_tbl[led_id];
\r
22930 BFD07D16 0020147E LBU V1, 32(S8)
\r
22931 BFD07D1A BFD041A2 LUI V0, 0xBFD0
\r
22932 BFD07D1C 25B2BFD0 LDC1 F30, 9650(S0)
\r
22933 BFD07D1E 25B2 SLL V1, V1, 1
\r
22934 BFD07D20 01783042 ADDIU V0, V0, 376
\r
22935 BFD07D24 0526 ADDU V0, V1, V0
\r
22936 BFD07D26 2920 LHU V0, 0(V0)
\r
22937 BFD07D28 0010385E SH V0, 16(S8)
\r
22938 172: GPIOPropertySet((ledi & 0xFF), GPIO_PROP_MUX_SEL, (ledi >> 8) & 0xFF);
\r
22939 BFD07D2C 0010345E LHU V0, 16(S8)
\r
22940 BFD07D30 2D2D ANDI V0, V0, 0xFF
\r
22941 BFD07D32 0C62 MOVE V1, V0
\r
22942 BFD07D34 0010345E LHU V0, 16(S8)
\r
22943 BFD07D38 2521 SRL V0, V0, 8
\r
22944 BFD07D3A 2D2F ANDI V0, V0, 0xFFFF
\r
22945 BFD07D3C 0C83 MOVE A0, V1
\r
22946 BFD07D3E EE87 LI A1, 7
\r
22947 BFD07D40 0CC2 MOVE A2, V0
\r
22948 BFD07D42 25CC77E8 JALS GPIOPropertySet
\r
22949 BFD07D44 25CC SLL V1, A0, 6
\r
22950 BFD07D46 0C00 NOP
\r
22951 173: led_reset(ledi & 0xFF);
\r
22952 BFD07D48 0010345E LHU V0, 16(S8)
\r
22953 BFD07D4C 2D2D ANDI V0, V0, 0xFF
\r
22954 BFD07D4E 0C82 MOVE A0, V0
\r
22955 BFD07D50 3FE477E8 JALS led_reset
\r
22956 BFD07D52 0C003FE4 LH RA, 3072(A0)
\r
22957 BFD07D54 0C00 NOP
\r
22960 BFD07D56 0FBE MOVE SP, S8
\r
22961 BFD07D58 4BE7 LW RA, 28(SP)
\r
22962 BFD07D5A 4BC6 LW S8, 24(SP)
\r
22963 BFD07D5C 4C11 ADDIU SP, SP, 32
\r
22964 BFD07D5E 459F JR16 RA
\r
22965 BFD07D60 0C00 NOP
\r
22969 179: * led_mode_blink - Enable LED hardware blink
\r
22971 181: * @author sworley
\r
22973 183: * @param led_id 0-based LED ID
\r
22974 184: * @param duty_cycle duty cycle (0x80 = 50%)
\r
22975 185: * @param prescale sets the blink frequency
\r
22976 186: * @note Blink frequency is (32768 * 255)/(prescale + 1) Hz
\r
22978 188: void led_mode_blink(uint8_t led_id,
\r
22979 189: uint8_t duty_cycle,
\r
22980 190: uint16_t prescale)
\r
22982 BFD07914 4FF1 ADDIU SP, SP, -32
\r
22983 BFD07916 CBE7 SW RA, 28(SP)
\r
22984 BFD07918 CBC6 SW S8, 24(SP)
\r
22985 BFD0791A 0FDD MOVE S8, SP
\r
22986 BFD0791C 0C65 MOVE V1, A1
\r
22987 BFD0791E 0C46 MOVE V0, A2
\r
22988 BFD07920 0020189E SB A0, 32(S8)
\r
22989 BFD07924 0024187E SB V1, 36(S8)
\r
22990 BFD07928 0028385E SH V0, 40(S8)
\r
22991 192: uint32_t pLed;
\r
22994 BFD0792C 0010F81E SW ZERO, 16(S8)
\r
22996 196: if (led_is_valid(led_id)) {
\r
22997 BFD07930 0020145E LBU V0, 32(S8)
\r
22998 BFD07934 0C82 MOVE A0, V0
\r
22999 BFD07936 4F3677E8 JALS led_is_valid
\r
23000 BFD07938 4F36 ADDIU T9, T9, -5
\r
23001 BFD0793A 0C00 NOP
\r
23002 BFD0793C 001E40E2 BEQZC V0, 0xBFD0797C
\r
23003 197: pLed = led_addr(led_id);
\r
23004 BFD07940 0020145E LBU V0, 32(S8)
\r
23005 BFD07944 0C82 MOVE A0, V0
\r
23006 BFD07946 4A1077E8 JALS led_addr
\r
23007 BFD07948 4A10 LW S0, 64(SP)
\r
23008 BFD0794A 0C00 NOP
\r
23009 BFD0794C 0010F85E SW V0, 16(S8)
\r
23011 199: ((BBLED_TypeDef *)pLed)->CONFIG = LED_CFG_CNTL_BLINK;
\r
23012 BFD07950 0010FC5E LW V0, 16(S8)
\r
23013 BFD07954 ED82 LI V1, 2
\r
23014 BFD07956 E9A0 SW V1, 0(V0)
\r
23015 200: ((BBLED_TypeDef *)pLed)->LIMIT = (uint32_t)duty_cycle;
\r
23016 BFD07958 0010FC5E LW V0, 16(S8)
\r
23017 BFD0795C 0024147E LBU V1, 36(S8)
\r
23018 BFD07960 E9A1 SW V1, 4(V0)
\r
23019 201: ((BBLED_TypeDef *)pLed)->DELAY = (uint32_t)prescale;
\r
23020 BFD07962 0010FC5E LW V0, 16(S8)
\r
23021 BFD07966 0028347E LHU V1, 40(S8)
\r
23022 BFD0796A E9A2 SW V1, 8(V0)
\r
23023 202: ((BBLED_TypeDef *)pLed)->CONFIG |= (LED_CFG_EN_UPDATE);
\r
23024 BFD0796C 0010FC5E LW V0, 16(S8)
\r
23025 BFD07970 0010FC7E LW V1, 16(S8)
\r
23026 BFD07974 69B0 LW V1, 0(V1)
\r
23027 BFD07976 00405063 ORI V1, V1, 64
\r
23028 BFD0797A E9A0 SW V1, 0(V0)
\r
23031 BFD0797C 0FBE MOVE SP, S8
\r
23032 BFD0797E 4BE7 LW RA, 28(SP)
\r
23033 BFD07980 4BC6 LW S8, 24(SP)
\r
23034 BFD07982 4C11 ADDIU SP, SP, 32
\r
23035 BFD07984 459F JR16 RA
\r
23036 BFD07986 0C00 NOP
\r
23040 208: * led_out_toggle - Toggle the LED output pin.
\r
23042 210: * @author sworley
\r
23044 212: * @param led_id 0-based LED ID.
\r
23046 214: void led_out_toggle(uint8_t led_id)
\r
23048 BFD085A8 4FF1 ADDIU SP, SP, -32
\r
23049 BFD085AA CBE7 SW RA, 28(SP)
\r
23050 BFD085AC CBC6 SW S8, 24(SP)
\r
23051 BFD085AE 0FDD MOVE S8, SP
\r
23052 BFD085B0 0C44 MOVE V0, A0
\r
23053 BFD085B2 0020185E SB V0, 32(S8)
\r
23056 218: if (led_is_valid(led_id)) {
\r
23057 BFD085B6 0020145E LBU V0, 32(S8)
\r
23058 BFD085BA 0C82 MOVE A0, V0
\r
23059 BFD085BC 4F3677E8 JALS led_is_valid
\r
23060 BFD085BE 4F36 ADDIU T9, T9, -5
\r
23061 BFD085C0 0C00 NOP
\r
23062 BFD085C2 001740E2 BEQZC V0, 0xBFD085F4
\r
23063 219: p = led_addr(led_id);
\r
23064 BFD085C6 0020145E LBU V0, 32(S8)
\r
23065 BFD085CA 0C82 MOVE A0, V0
\r
23066 BFD085CC 4A1077E8 JALS led_addr
\r
23067 BFD085CE 4A10 LW S0, 64(SP)
\r
23068 BFD085D0 0C00 NOP
\r
23069 BFD085D2 0010F85E SW V0, 16(S8)
\r
23071 221: if (((BBLED_TypeDef *)p)->CONFIG & LED_CFG_CNTL_MASK) {
\r
23072 BFD085D6 0010FC5E LW V0, 16(S8)
\r
23073 BFD085DA 6920 LW V0, 0(V0)
\r
23074 BFD085DC 2D23 ANDI V0, V0, 0x3
\r
23075 BFD085DE 000540E2 BEQZC V0, 0xBFD085EC
\r
23076 222: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;
\r
23077 BFD085E2 0010FC5E LW V0, 16(S8)
\r
23078 BFD085E6 E820 SW S0, 0(V0)
\r
23079 BFD085E8 CC05 B 0xBFD085F4
\r
23080 BFD085EA 0C00 NOP
\r
23082 224: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;
\r
23083 BFD085EC 0010FC5E LW V0, 16(S8)
\r
23084 BFD085F0 ED83 LI V1, 3
\r
23085 BFD085F2 E9A0 SW V1, 0(V0)
\r
23089 BFD085F4 0FBE MOVE SP, S8
\r
23090 BFD085F6 4BE7 LW RA, 28(SP)
\r
23091 BFD085F8 4BC6 LW S8, 24(SP)
\r
23092 BFD085FA 4C11 ADDIU SP, SP, 32
\r
23093 BFD085FC 459F JR16 RA
\r
23094 BFD085FE 0C00 NOP
\r
23098 231: * led_out_high - Set the LED block to drive the pin High
\r
23100 233: * @author sworley
\r
23102 235: * @param led_id 0-based LED ID
\r
23103 236: * @note The LED controller will drive the pin High. Depending
\r
23104 237: * upon the external circuit the LED may be in ON or OFF
\r
23107 240: void led_out_high(uint8_t led_id)
\r
23109 BFD09210 4FF1 ADDIU SP, SP, -32
\r
23110 BFD09212 CBE7 SW RA, 28(SP)
\r
23111 BFD09214 CBC6 SW S8, 24(SP)
\r
23112 BFD09216 0FDD MOVE S8, SP
\r
23113 BFD09218 0C44 MOVE V0, A0
\r
23114 BFD0921A 0020185E SB V0, 32(S8)
\r
23117 244: if (led_is_valid(led_id)) {
\r
23118 BFD0921E 0020145E LBU V0, 32(S8)
\r
23119 BFD09222 0C82 MOVE A0, V0
\r
23120 BFD09224 4F3677E8 JALS led_is_valid
\r
23121 BFD09226 4F36 ADDIU T9, T9, -5
\r
23122 BFD09228 0C00 NOP
\r
23123 BFD0922A 000C40E2 BEQZC V0, 0xBFD09246
\r
23124 245: p = led_addr(led_id);
\r
23125 BFD0922E 0020145E LBU V0, 32(S8)
\r
23126 BFD09232 0C82 MOVE A0, V0
\r
23127 BFD09234 4A1077E8 JALS led_addr
\r
23128 BFD09236 4A10 LW S0, 64(SP)
\r
23129 BFD09238 0C00 NOP
\r
23130 BFD0923A 0010F85E SW V0, 16(S8)
\r
23131 246: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;
\r
23132 BFD0923E 0010FC5E LW V0, 16(S8)
\r
23133 BFD09242 ED83 LI V1, 3
\r
23134 BFD09244 E9A0 SW V1, 0(V0)
\r
23137 BFD09246 0FBE MOVE SP, S8
\r
23138 BFD09248 4BE7 LW RA, 28(SP)
\r
23139 BFD0924A 4BC6 LW S8, 24(SP)
\r
23140 BFD0924C 4C11 ADDIU SP, SP, 32
\r
23141 BFD0924E 459F JR16 RA
\r
23142 BFD09250 0C00 NOP
\r
23146 252: * led_out_low - Set the LED block to drive the pin Low
\r
23148 254: * @author sworley
\r
23150 256: * @param led_id 0-based LED ID
\r
23151 257: * @note The LED controller will drive the pin Low. Depending
\r
23152 258: * upon the external circuit the LED may be in ON or OFF
\r
23155 261: void led_out_low(uint8_t led_id)
\r
23157 BFD09460 4FF1 ADDIU SP, SP, -32
\r
23158 BFD09462 CBE7 SW RA, 28(SP)
\r
23159 BFD09464 CBC6 SW S8, 24(SP)
\r
23160 BFD09466 0FDD MOVE S8, SP
\r
23161 BFD09468 0C44 MOVE V0, A0
\r
23162 BFD0946A 0020185E SB V0, 32(S8)
\r
23165 265: if (led_is_valid(led_id)) {
\r
23166 BFD0946E 0020145E LBU V0, 32(S8)
\r
23167 BFD09472 0C82 MOVE A0, V0
\r
23168 BFD09474 4F3677E8 JALS led_is_valid
\r
23169 BFD09476 4F36 ADDIU T9, T9, -5
\r
23170 BFD09478 0C00 NOP
\r
23171 BFD0947A 000B40E2 BEQZC V0, 0xBFD09494
\r
23172 266: p = led_addr(led_id);
\r
23173 BFD0947E 0020145E LBU V0, 32(S8)
\r
23174 BFD09482 0C82 MOVE A0, V0
\r
23175 BFD09484 4A1077E8 JALS led_addr
\r
23176 BFD09486 4A10 LW S0, 64(SP)
\r
23177 BFD09488 0C00 NOP
\r
23178 BFD0948A 0010F85E SW V0, 16(S8)
\r
23179 267: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;
\r
23180 BFD0948E 0010FC5E LW V0, 16(S8)
\r
23181 BFD09492 E820 SW S0, 0(V0)
\r
23184 BFD09494 0FBE MOVE SP, S8
\r
23185 BFD09496 4BE7 LW RA, 28(SP)
\r
23186 BFD09498 4BC6 LW S8, 24(SP)
\r
23187 BFD0949A 4C11 ADDIU SP, SP, 32
\r
23188 BFD0949C 459F JR16 RA
\r
23189 BFD0949E 0C00 NOP
\r
23192 272: #ifdef __cplusplus
\r
23196 276: /* end mec14xx_bbled.h */
\r
23199 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq26.c ----
\r
23200 1: /*****************************************************************************
\r
23201 2: * (c) 2013 Microchip Technology Inc. and its subsidiaries.
\r
23202 3: * You may use this software and any derivatives exclusively with
\r
23203 4: * Microchip products.
\r
23204 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
23205 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
23206 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
23207 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
23208 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
23209 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
23210 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
23211 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
23212 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
23213 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
23214 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
23215 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
23216 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
23217 18: * OF THESE TERMS.
\r
23218 19: *****************************************************************************/
\r
23220 21: /** @file girq26.c
\r
23221 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
23223 24: /** @defgroup MEC14xx ISR
\r
23228 29: #include "appcfg.h"
\r
23229 30: #include "platform.h"
\r
23230 31: #include "MEC14xx/mec14xx.h"
\r
23231 32: #include "MEC14xx/mec14xx_girqs.h"
\r
23232 33: #include "MEC14xx/mec14xx_gpio.h"
\r
23233 34: #include "MEC14xx/mec14xx_trace_func.h"
\r
23236 37: #if GIRQ26_DISAGG == 0
\r
23238 39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
23239 40: girq26_isr(void)
\r
23241 BFD07408 E17C03BD RDPGPR SP, SP
\r
23242 BFD0740C 00FC036E MFC0 K1, EPC
\r
23243 BFD0740E 034C00FC INS A3, GP, 13, -12
\r
23244 BFD07410 10FC034C MFC0 K0, SRSCtl
\r
23245 BFD07412 4FF110FC ADDI A3, GP, 20465
\r
23246 BFD07414 4FF1 ADDIU SP, SP, -32
\r
23247 BFD07416 CB67 SW K1, 28(SP)
\r
23248 BFD07418 00FC036C MFC0 K1, Status
\r
23249 BFD0741C CB46 SW K0, 24(SP)
\r
23250 BFD0741E 00FC034D MFC0 K0, Cause
\r
23251 BFD07422 CB65 SW K1, 20(SP)
\r
23252 BFD07424 5040035A SRL K0, K0, 10
\r
23253 BFD07426 037A5040 ORI V0, ZERO, 890
\r
23254 BFD07428 7A8C037A INS K1, K0, 10, 6
\r
23255 BFD0742A 03607A8C ADDIUPC A1, 787296
\r
23256 BFD0742C 204C0360 INS K1, ZERO, 1, 4
\r
23257 BFD0742E 036C204C LWC2 V0, 876(T4)
\r
23258 BFD07430 02FC036C MTC0 K1, Status
\r
23259 BFD07434 C862 SW V1, 8(SP)
\r
23260 BFD07436 C841 SW V0, 4(SP)
\r
23261 BFD07438 4866 LW V1, 24(SP)
\r
23262 BFD0743A 2DB7 ANDI V1, V1, 0xF
\r
23263 BFD0743C CBC3 SW S8, 12(SP)
\r
23264 BFD0743E 0FDD MOVE S8, SP
\r
23265 42: JTVIC_GROUP_EN_CLR->w = (1ul<<16);
\r
23266 BFD07440 BFFF41A2 LUI V0, 0xBFFF
\r
23267 BFD07442 5042BFFF LDC1 F31, 20546(RA)
\r
23268 BFD07444 C50C5042 ORI V0, V0, -15092
\r
23269 BFD07448 000141A3 LUI V1, 0x1
\r
23270 BFD0744C E9A0 SW V1, 0(V0)
\r
23272 BFD0744E 0FBE MOVE SP, S8
\r
23273 BFD07450 4846 LW V0, 24(SP)
\r
23274 BFD07452 2D27 ANDI V0, V0, 0xF
\r
23275 BFD07454 4BC3 LW S8, 12(SP)
\r
23276 BFD07456 4862 LW V1, 8(SP)
\r
23277 BFD07458 4841 LW V0, 4(SP)
\r
23278 BFD0745A 477C0000 DI ZERO
\r
23279 BFD0745E 18000000 SLL ZERO, ZERO, 3
\r
23280 BFD07460 4B471800 SB ZERO, 19271(ZERO)
\r
23281 BFD07462 4B47 LW K0, 28(SP)
\r
23282 BFD07464 4B65 LW K1, 20(SP)
\r
23283 BFD07466 02FC034E MTC0 K0, EPC
\r
23284 BFD0746A 4B46 LW K0, 24(SP)
\r
23285 BFD0746C 4C11 ADDIU SP, SP, 32
\r
23286 BFD0746E 12FC034C MTC0 K0, SRSCtl
\r
23287 BFD07470 03BD12FC ADDI S7, GP, 957
\r
23288 BFD07472 F17C03BD WRPGPR SP, SP
\r
23289 BFD07474 036CF17C JALX 0xBDF00DB0
\r
23290 BFD07476 02FC036C MTC0 K1, Status
\r
23291 BFD07478 000002FC SLL S7, GP, 0
\r
23292 BFD0747A F37C0000 ERET
\r
23293 BFD0747C 0C00F37C JALX 0xBDF03000
\r
23297 47: void __attribute__((weak, interrupt, nomips16))
\r
23298 48: girq26_b0(void)
\r
23300 50: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 0);
\r
23303 53: void __attribute__((weak, interrupt, nomips16))
\r
23304 54: girq26_b1(void)
\r
23306 56: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 1);
\r
23309 59: void __attribute__((weak, interrupt, nomips16))
\r
23310 60: girq26_b2(void)
\r
23312 62: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 2);
\r
23315 65: void __attribute__((weak, interrupt, nomips16))
\r
23316 66: girq26_b3(void)
\r
23318 68: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 3);
\r
23321 71: void __attribute__((weak, interrupt, nomips16))
\r
23322 72: girq26_b4(void)
\r
23324 74: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 4);
\r
23327 77: void __attribute__((weak, interrupt, nomips16))
\r
23328 78: girq26_b5(void)
\r
23330 80: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 5);
\r
23333 83: void __attribute__((weak, interrupt, nomips16))
\r
23334 84: girq26_b6(void)
\r
23336 86: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 6);
\r
23339 89: void __attribute__((weak, interrupt, nomips16))
\r
23340 90: girq26_b7(void)
\r
23342 92: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 7);
\r
23345 95: void __attribute__((weak, interrupt, nomips16))
\r
23346 96: girq26_b8(void)
\r
23348 98: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 8);
\r
23351 101: void __attribute__((weak, interrupt, nomips16))
\r
23352 102: girq26_b9(void)
\r
23354 104: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 9);
\r
23357 107: void __attribute__((weak, interrupt, nomips16))
\r
23358 108: girq26_b10(void)
\r
23360 110: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 10);
\r
23363 113: void __attribute__((weak, interrupt, nomips16))
\r
23364 114: girq26_b11(void)
\r
23366 116: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 11);
\r
23372 122: /* end girq26.c */
\r
23376 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq25.c ----
\r
23377 1: /*****************************************************************************
\r
23378 2: * (c) 2013 Microchip Technology Inc. and its subsidiaries.
\r
23379 3: * You may use this software and any derivatives exclusively with
\r
23380 4: * Microchip products.
\r
23381 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
23382 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
23383 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
23384 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
23385 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
23386 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
23387 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
23388 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
23389 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
23390 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
23391 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
23392 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
23393 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
23394 18: * OF THESE TERMS.
\r
23395 19: *****************************************************************************/
\r
23397 21: /** @file girq25.c
\r
23398 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
23400 24: /** @defgroup MEC14xx ISR
\r
23404 28: #include "appcfg.h"
\r
23405 29: #include "platform.h"
\r
23406 30: #include "MEC14xx/mec14xx.h"
\r
23407 31: #include "MEC14xx/mec14xx_girqs.h"
\r
23408 32: #include "MEC14xx/mec14xx_gpio.h"
\r
23409 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
23412 36: #if GIRQ25_DISAGG == 0
\r
23414 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
23415 39: girq25_isr(void)
\r
23417 BFD07390 E17C03BD RDPGPR SP, SP
\r
23418 BFD07394 00FC036E MFC0 K1, EPC
\r
23419 BFD07396 034C00FC INS A3, GP, 13, -12
\r
23420 BFD07398 10FC034C MFC0 K0, SRSCtl
\r
23421 BFD0739A 4FF110FC ADDI A3, GP, 20465
\r
23422 BFD0739C 4FF1 ADDIU SP, SP, -32
\r
23423 BFD0739E CB67 SW K1, 28(SP)
\r
23424 BFD073A0 00FC036C MFC0 K1, Status
\r
23425 BFD073A4 CB46 SW K0, 24(SP)
\r
23426 BFD073A6 00FC034D MFC0 K0, Cause
\r
23427 BFD073AA CB65 SW K1, 20(SP)
\r
23428 BFD073AC 5040035A SRL K0, K0, 10
\r
23429 BFD073AE 037A5040 ORI V0, ZERO, 890
\r
23430 BFD073B0 7A8C037A INS K1, K0, 10, 6
\r
23431 BFD073B2 03607A8C ADDIUPC A1, 787296
\r
23432 BFD073B4 204C0360 INS K1, ZERO, 1, 4
\r
23433 BFD073B6 036C204C LWC2 V0, 876(T4)
\r
23434 BFD073B8 02FC036C MTC0 K1, Status
\r
23435 BFD073BC C862 SW V1, 8(SP)
\r
23436 BFD073BE C841 SW V0, 4(SP)
\r
23437 BFD073C0 4866 LW V1, 24(SP)
\r
23438 BFD073C2 2DB7 ANDI V1, V1, 0xF
\r
23439 BFD073C4 CBC3 SW S8, 12(SP)
\r
23440 BFD073C6 0FDD MOVE S8, SP
\r
23441 41: JTVIC_GROUP_EN_CLR->w = (1ul<<15);
\r
23442 BFD073C8 BFFF41A2 LUI V0, 0xBFFF
\r
23443 BFD073CA 5042BFFF LDC1 F31, 20546(RA)
\r
23444 BFD073CC C50C5042 ORI V0, V0, -15092
\r
23445 BFD073D0 80005060 ORI V1, ZERO, -32768
\r
23446 BFD073D4 E9A0 SW V1, 0(V0)
\r
23448 BFD073D6 0FBE MOVE SP, S8
\r
23449 BFD073D8 4846 LW V0, 24(SP)
\r
23450 BFD073DA 2D27 ANDI V0, V0, 0xF
\r
23451 BFD073DC 4BC3 LW S8, 12(SP)
\r
23452 BFD073DE 4862 LW V1, 8(SP)
\r
23453 BFD073E0 4841 LW V0, 4(SP)
\r
23454 BFD073E2 477C0000 DI ZERO
\r
23455 BFD073E6 18000000 SLL ZERO, ZERO, 3
\r
23456 BFD073E8 4B471800 SB ZERO, 19271(ZERO)
\r
23457 BFD073EA 4B47 LW K0, 28(SP)
\r
23458 BFD073EC 4B65 LW K1, 20(SP)
\r
23459 BFD073EE 02FC034E MTC0 K0, EPC
\r
23460 BFD073F2 4B46 LW K0, 24(SP)
\r
23461 BFD073F4 4C11 ADDIU SP, SP, 32
\r
23462 BFD073F6 12FC034C MTC0 K0, SRSCtl
\r
23463 BFD073F8 03BD12FC ADDI S7, GP, 957
\r
23464 BFD073FA F17C03BD WRPGPR SP, SP
\r
23465 BFD073FC 036CF17C JALX 0xBDF00DB0
\r
23466 BFD073FE 02FC036C MTC0 K1, Status
\r
23467 BFD07400 000002FC SLL S7, GP, 0
\r
23468 BFD07402 F37C0000 ERET
\r
23469 BFD07404 0C00F37C JALX 0xBDF03000
\r
23473 46: void __attribute__((weak, interrupt, nomips16))
\r
23474 47: girq25_b0(void)
\r
23476 49: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 0);
\r
23479 52: void __attribute__((weak, interrupt, nomips16))
\r
23480 53: girq25_b1(void)
\r
23482 55: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 1);
\r
23485 58: void __attribute__((weak, interrupt, nomips16))
\r
23486 59: girq25_b2(void)
\r
23488 61: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 2);
\r
23491 64: void __attribute__((weak, interrupt, nomips16))
\r
23492 65: girq25_b3(void)
\r
23494 67: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 3);
\r
23497 70: void __attribute__((weak, interrupt, nomips16))
\r
23498 71: girq25_b4(void)
\r
23500 73: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 4);
\r
23503 76: void __attribute__((weak, interrupt, nomips16))
\r
23504 77: girq25_b5(void)
\r
23506 79: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 5);
\r
23509 82: void __attribute__((weak, interrupt, nomips16))
\r
23510 83: girq25_b6(void)
\r
23512 85: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 6);
\r
23515 88: void __attribute__((weak, interrupt, nomips16))
\r
23516 89: girq25_b7(void)
\r
23518 91: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 7);
\r
23521 94: void __attribute__((weak, interrupt, nomips16))
\r
23522 95: girq25_b8(void)
\r
23524 97: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 8);
\r
23527 100: void __attribute__((weak, interrupt, nomips16))
\r
23528 101: girq25_b9(void)
\r
23530 103: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 9);
\r
23533 106: void __attribute__((weak, interrupt, nomips16))
\r
23534 107: girq25_b10(void)
\r
23536 109: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 10);
\r
23539 112: void __attribute__((weak, interrupt, nomips16))
\r
23540 113: girq25_b11(void)
\r
23542 115: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 11);
\r
23545 118: void __attribute__((weak, interrupt, nomips16))
\r
23546 119: girq25_b12(void)
\r
23548 121: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 12);
\r
23551 124: void __attribute__((weak, interrupt, nomips16))
\r
23552 125: girq25_b13(void)
\r
23554 127: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 13);
\r
23557 130: void __attribute__((weak, interrupt, nomips16))
\r
23558 131: girq25_b14(void)
\r
23560 133: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 14);
\r
23563 136: void __attribute__((weak, interrupt, nomips16))
\r
23564 137: girq25_b15(void)
\r
23566 139: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 15);
\r
23569 142: void __attribute__((weak, interrupt, nomips16))
\r
23570 143: girq25_b16(void)
\r
23572 145: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 16);
\r
23575 148: void __attribute__((weak, interrupt, nomips16))
\r
23576 149: girq25_b17(void)
\r
23578 151: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 17);
\r
23581 154: void __attribute__((weak, interrupt, nomips16))
\r
23582 155: girq25_b18(void)
\r
23584 157: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 18);
\r
23587 160: void __attribute__((weak, interrupt, nomips16))
\r
23588 161: girq25_b19(void)
\r
23590 163: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 19);
\r
23593 166: void __attribute__((weak, interrupt, nomips16))
\r
23594 167: girq25_b20(void)
\r
23596 169: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 20);
\r
23599 172: void __attribute__((weak, interrupt, nomips16))
\r
23600 173: girq25_b21(void)
\r
23602 175: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 21);
\r
23605 178: void __attribute__((weak, interrupt, nomips16))
\r
23606 179: girq25_b22(void)
\r
23608 181: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 22);
\r
23611 184: void __attribute__((weak, interrupt, nomips16))
\r
23612 185: girq25_b23(void)
\r
23614 187: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 23);
\r
23617 190: void __attribute__((weak, interrupt, nomips16))
\r
23618 191: girq25_b24(void)
\r
23620 193: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 24);
\r
23623 196: void __attribute__((weak, interrupt, nomips16))
\r
23624 197: girq25_b25(void)
\r
23626 199: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 25);
\r
23629 202: void __attribute__((weak, interrupt, nomips16))
\r
23630 203: girq25_b26(void)
\r
23632 205: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 26);
\r
23635 208: void __attribute__((weak, interrupt, nomips16))
\r
23636 209: girq25_b27(void)
\r
23638 211: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 27);
\r
23644 217: /* end girq25.c */
\r
23648 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq24.c ----
\r
23649 1: /*****************************************************************************
\r
23650 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
23651 3: * You may use this software and any derivatives exclusively with
\r
23652 4: * Microchip products.
\r
23653 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
23654 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
23655 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
23656 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
23657 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
23658 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
23659 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
23660 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
23661 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
23662 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
23663 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
23664 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
23665 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
23666 18: * OF THESE TERMS.
\r
23667 19: *****************************************************************************/
\r
23669 21: /** @file girq24.c
\r
23670 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
23672 24: /** @defgroup MEC14xx ISR
\r
23676 28: #include "appcfg.h"
\r
23677 29: #include "platform.h"
\r
23678 30: #include "MEC14xx/mec14xx.h"
\r
23679 31: #include "MEC14xx/mec14xx_girqs.h"
\r
23680 32: #include "MEC14xx/mec14xx_gpio.h"
\r
23681 33: #include "MEC14xx/mec14xx_bbled.h"
\r
23682 34: #include "MEC14xx/mec14xx_trace_func.h"
\r
23685 37: typedef void (* GIRQ24_FPVU8)(uint8_t);
\r
23688 40: /* MIPS M14K internal counter is connected to GIRQ24 bit[0]
\r
23689 41: * It is a simple counter which fires an interrupt when its
\r
23690 42: * count value is equal to a match value.
\r
23694 46: #if GIRQ24_DISAGG == 0
\r
23697 49: void girq24_dflt_handler(uint8_t inum)
\r
23699 51: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].EN_CLR = (1ul << inum);
\r
23700 52: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << inum);
\r
23703 55: void __attribute__((weak)) m14k_counter_handler(uint8_t inum)
\r
23709 61: r = _CP0_GET_COUNT();
\r
23710 62: r += (M14K_TIMER_COMPARE);
\r
23711 63: /* Write of CP0.Compare clears status in M14K */
\r
23712 64: _CP0_SET_COUNT(r);
\r
23714 66: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
\r
23719 71: * TODO - FreeRTOS M14K Software Interrupt 0 handler
\r
23720 72: * is vPortYieldISR in port_asm.S
\r
23721 73: * vPortYieldISR was designed to be entered directly by the
\r
23722 74: * CPU not via a higher level ISR handler.
\r
23723 75: * One work-around is to modify vPortYieldISR to do the work
\r
23724 76: * of girq24_handler below. It must determine which GIRQ24 source
\r
23725 77: * was active: M14K counter, SoftIRQ0, or SoftIRQ1.
\r
23727 79: void __attribute__((weak)) m14k_soft_irq0(uint8_t inum)
\r
23731 83: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 1);
\r
23735 87: void __attribute__((weak)) m14k_soft_irq1(uint8_t inum)
\r
23739 91: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 2);
\r
23743 95: void girq24_b_0_2( void )
\r
23747 99: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
\r
23749 101: if ( d & (1ul << 0) )
\r
23751 103: m14k_counter_handler(0);
\r
23754 106: if ( d & (1ul << 2) )
\r
23756 108: m14k_soft_irq1(2);
\r
23761 113: const GIRQ24_FPVU8 girq24_htable[GIRQ24_NUM_SOURCES] =
\r
23763 115: m14k_counter_handler, /* m14k_counter_handler, */
\r
23764 116: m14k_soft_irq0, /* m14k_soft_irq0, */
\r
23765 117: m14k_soft_irq1, /* m14k_soft_irq1 */
\r
23768 120: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
23769 121: girq24_isr(void)
\r
23772 124: uint8_t bitpos;
\r
23774 126: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
\r
23775 127: while ( 0 != d )
\r
23777 129: bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
\r
23778 130: (girq24_htable[bitpos])(bitpos);
\r
23779 131: d &= ~(1ul << bitpos);
\r
23785 137: void __attribute__((weak, interrupt, nomips16))
\r
23786 138: girq24_b0(void)
\r
23788 BFD065A8 E17C03BD RDPGPR SP, SP
\r
23789 BFD065AC 00FC036E MFC0 K1, EPC
\r
23790 BFD065AE 034C00FC INS A3, GP, 13, -12
\r
23791 BFD065B0 10FC034C MFC0 K0, SRSCtl
\r
23792 BFD065B2 4FED10FC ADDI A3, GP, 20461
\r
23793 BFD065B4 4FED ADDIU SP, SP, -40
\r
23794 BFD065B6 CB69 SW K1, 36(SP)
\r
23795 BFD065B8 00FC036C MFC0 K1, Status
\r
23796 BFD065BC CB48 SW K0, 32(SP)
\r
23797 BFD065BE 00FC034D MFC0 K0, Cause
\r
23798 BFD065C2 CB67 SW K1, 28(SP)
\r
23799 BFD065C4 5040035A SRL K0, K0, 10
\r
23800 BFD065C6 037A5040 ORI V0, ZERO, 890
\r
23801 BFD065C8 7A8C037A INS K1, K0, 10, 6
\r
23802 BFD065CA 03607A8C ADDIUPC A1, 787296
\r
23803 BFD065CC 204C0360 INS K1, ZERO, 1, 4
\r
23804 BFD065CE 036C204C LWC2 V0, 876(T4)
\r
23805 BFD065D0 02FC036C MTC0 K1, Status
\r
23806 BFD065D4 C864 SW V1, 16(SP)
\r
23807 BFD065D6 C843 SW V0, 12(SP)
\r
23808 BFD065D8 4868 LW V1, 32(SP)
\r
23809 BFD065DA 2DB7 ANDI V1, V1, 0xF
\r
23810 BFD065DC CBC5 SW S8, 20(SP)
\r
23811 BFD065DE 0FDD MOVE S8, SP
\r
23814 142: r = _CP0_GET_COUNT();
\r
23815 BFD065E0 00FC0049 MFC0 V0, Count
\r
23816 BFD065E4 0000F85E SW V0, 0(S8)
\r
23817 143: r += (M14K_TIMER_COMPARE);
\r
23818 BFD065E8 0000FC7E LW V1, 0(S8)
\r
23819 BFD065EC 00B741A2 LUI V0, 0xB7
\r
23820 BFD065F0 1B005042 ORI V0, V0, 6912
\r
23821 BFD065F2 05261B00 SB T8, 1318(ZERO)
\r
23822 BFD065F4 0526 ADDU V0, V1, V0
\r
23823 BFD065F6 0000F85E SW V0, 0(S8)
\r
23824 144: _CP0_SET_COUNT(r);
\r
23825 BFD065FA 0000FC5E LW V0, 0(S8)
\r
23826 BFD065FE 02FC0049 MTC0 V0, Count
\r
23827 BFD06600 000002FC SLL S7, GP, 0
\r
23828 BFD06602 18000000 SLL ZERO, ZERO, 3
\r
23829 BFD06604 41A21800 SB ZERO, 16802(ZERO)
\r
23831 146: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
\r
23832 BFD06606 BFFF41A2 LUI V0, 0xBFFF
\r
23833 BFD06608 5042BFFF LDC1 F31, 20546(RA)
\r
23834 BFD0660A C0005042 ORI V0, V0, -16384
\r
23835 BFD0660E ED81 LI V1, 1
\r
23836 BFD06610 0100F862 SW V1, 256(V0)
\r
23838 BFD06614 0FBE MOVE SP, S8
\r
23839 BFD06616 4848 LW V0, 32(SP)
\r
23840 BFD06618 2D27 ANDI V0, V0, 0xF
\r
23841 BFD0661A 4BC5 LW S8, 20(SP)
\r
23842 BFD0661C 4864 LW V1, 16(SP)
\r
23843 BFD0661E 4843 LW V0, 12(SP)
\r
23844 BFD06620 477C0000 DI ZERO
\r
23845 BFD06624 18000000 SLL ZERO, ZERO, 3
\r
23846 BFD06626 4B491800 SB ZERO, 19273(ZERO)
\r
23847 BFD06628 4B49 LW K0, 36(SP)
\r
23848 BFD0662A 4B67 LW K1, 28(SP)
\r
23849 BFD0662C 02FC034E MTC0 K0, EPC
\r
23850 BFD06630 4B48 LW K0, 32(SP)
\r
23851 BFD06632 4C15 ADDIU SP, SP, 40
\r
23852 BFD06634 12FC034C MTC0 K0, SRSCtl
\r
23853 BFD06636 03BD12FC ADDI S7, GP, 957
\r
23854 BFD06638 F17C03BD WRPGPR SP, SP
\r
23855 BFD0663A 036CF17C JALX 0xBDF00DB0
\r
23856 BFD0663C 02FC036C MTC0 K1, Status
\r
23857 BFD0663E 000002FC SLL S7, GP, 0
\r
23858 BFD06640 F37C0000 ERET
\r
23859 BFD06642 4FEDF37C JALX 0xBDF13FB4
\r
23861 149: void __attribute__((weak, interrupt, nomips16))
\r
23862 150: girq24_b1(void)
\r
23864 BFD0465C E17C03BD RDPGPR SP, SP
\r
23865 BFD04660 00FC036E MFC0 K1, EPC
\r
23866 BFD04662 034C00FC INS A3, GP, 13, -12
\r
23867 BFD04664 10FC034C MFC0 K0, SRSCtl
\r
23868 BFD04666 4FC510FC ADDI A3, GP, 20421
\r
23869 BFD04668 4FC5 ADDIU SP, SP, -120
\r
23870 BFD0466A CB7D SW K1, 116(SP)
\r
23871 BFD0466C 00FC036C MFC0 K1, Status
\r
23872 BFD04670 CB5C SW K0, 112(SP)
\r
23873 BFD04672 00FC034D MFC0 K0, Cause
\r
23874 BFD04676 CB7B SW K1, 108(SP)
\r
23875 BFD04678 5040035A SRL K0, K0, 10
\r
23876 BFD0467A 037A5040 ORI V0, ZERO, 890
\r
23877 BFD0467C 7A8C037A INS K1, K0, 10, 6
\r
23878 BFD0467E 03607A8C ADDIUPC A1, 787296
\r
23879 BFD04680 204C0360 INS K1, ZERO, 1, 4
\r
23880 BFD04682 036C204C LWC2 V0, 876(T4)
\r
23881 BFD04684 02FC036C MTC0 K1, Status
\r
23882 BFD04688 C867 SW V1, 28(SP)
\r
23883 BFD0468A C846 SW V0, 24(SP)
\r
23884 BFD0468C 487C LW V1, 112(SP)
\r
23885 BFD0468E 2DB7 ANDI V1, V1, 0xF
\r
23886 BFD04690 001140A3 BNEZC V1, 0xBFD046B6
\r
23887 BFD04694 CBF7 SW RA, 92(SP)
\r
23888 BFD04696 CBD6 SW S8, 88(SP)
\r
23889 BFD04698 CB35 SW T9, 84(SP)
\r
23890 BFD0469A CB14 SW T8, 80(SP)
\r
23891 BFD0469C C9F3 SW T7, 76(SP)
\r
23892 BFD0469E C9D2 SW T6, 72(SP)
\r
23893 BFD046A0 C9B1 SW T5, 68(SP)
\r
23894 BFD046A2 C990 SW T4, 64(SP)
\r
23895 BFD046A4 C96F SW T3, 60(SP)
\r
23896 BFD046A6 C94E SW T2, 56(SP)
\r
23897 BFD046A8 C92D SW T1, 52(SP)
\r
23898 BFD046AA C90C SW T0, 48(SP)
\r
23899 BFD046AC C8EB SW A3, 44(SP)
\r
23900 BFD046AE C8CA SW A2, 40(SP)
\r
23901 BFD046B0 C8A9 SW A1, 36(SP)
\r
23902 BFD046B2 C888 SW A0, 32(SP)
\r
23903 BFD046B4 C825 SW AT, 20(SP)
\r
23904 BFD046B6 4642 MFLO V0
\r
23905 BFD046B8 C859 SW V0, 100(SP)
\r
23906 BFD046BA 4603 MFHI V1
\r
23907 BFD046BC C878 SW V1, 96(SP)
\r
23908 BFD046BE 0FDD MOVE S8, SP
\r
23910 153: _CP0_BIC_CAUSE(0x100ul);
\r
23911 BFD046C0 01003040 ADDIU V0, ZERO, 256
\r
23912 BFD046C2 006D0100 PRECR.QB.PH ZERO, ZERO, T0
\r
23913 BFD046C4 00FC006D MFC0 V1, Cause
\r
23914 BFD046C6 0C0000FC SLL A3, GP, 1
\r
23915 BFD046C8 0C00 NOP
\r
23916 BFD046CA 4412 NOT16 V0, V0
\r
23917 BFD046CC 4493 AND16 V0, V1
\r
23918 BFD046CE 02FC004D MTC0 V0, Cause
\r
23919 BFD046D0 000002FC SLL S7, GP, 0
\r
23920 BFD046D2 18000000 SLL ZERO, ZERO, 3
\r
23921 BFD046D4 EE101800 SB ZERO, -4592(ZERO)
\r
23923 155: jtvic_clr_source(MEC14xx_GIRQ24_ID, 1);
\r
23924 BFD046D6 EE10 LI A0, 16
\r
23925 BFD046D8 EE81 LI A1, 1
\r
23926 BFD046DA 44FA77E8 JALS jtvic_clr_source
\r
23927 BFD046DC 44FA OR16 A3, V0
\r
23928 BFD046DE 0C00 NOP
\r
23930 BFD046E0 0FBE MOVE SP, S8
\r
23931 BFD046E2 4859 LW V0, 100(SP)
\r
23932 BFD046E4 3D7C0002 MTLO V0
\r
23933 BFD046E6 48783D7C LH T3, 18552(GP)
\r
23934 BFD046E8 4878 LW V1, 96(SP)
\r
23935 BFD046EA 2D7C0003 MTHI V1
\r
23936 BFD046EC 2D7C ANDI V0, A3, 0x40
\r
23937 BFD046EE 485C LW V0, 112(SP)
\r
23938 BFD046F0 2D27 ANDI V0, V0, 0xF
\r
23939 BFD046F2 001340A2 BNEZC V0, 0xBFD0471C
\r
23940 BFD046F6 4BF7 LW RA, 92(SP)
\r
23941 BFD046F8 4BD6 LW S8, 88(SP)
\r
23942 BFD046FA 4B35 LW T9, 84(SP)
\r
23943 BFD046FC 4B14 LW T8, 80(SP)
\r
23944 BFD046FE 49F3 LW T7, 76(SP)
\r
23945 BFD04700 49D2 LW T6, 72(SP)
\r
23946 BFD04702 49B1 LW T5, 68(SP)
\r
23947 BFD04704 4990 LW T4, 64(SP)
\r
23948 BFD04706 496F LW T3, 60(SP)
\r
23949 BFD04708 494E LW T2, 56(SP)
\r
23950 BFD0470A 492D LW T1, 52(SP)
\r
23951 BFD0470C 490C LW T0, 48(SP)
\r
23952 BFD0470E 48EB LW A3, 44(SP)
\r
23953 BFD04710 48CA LW A2, 40(SP)
\r
23954 BFD04712 48A9 LW A1, 36(SP)
\r
23955 BFD04714 4888 LW A0, 32(SP)
\r
23956 BFD04716 4867 LW V1, 28(SP)
\r
23957 BFD04718 4846 LW V0, 24(SP)
\r
23958 BFD0471A 4825 LW AT, 20(SP)
\r
23959 BFD0471C 477C0000 DI ZERO
\r
23960 BFD04720 18000000 SLL ZERO, ZERO, 3
\r
23961 BFD04722 4B5D1800 SB ZERO, 19293(ZERO)
\r
23962 BFD04724 4B5D LW K0, 116(SP)
\r
23963 BFD04726 4B7B LW K1, 108(SP)
\r
23964 BFD04728 02FC034E MTC0 K0, EPC
\r
23965 BFD0472C 4B5C LW K0, 112(SP)
\r
23966 BFD0472E 4C3D ADDIU SP, SP, 120
\r
23967 BFD04730 12FC034C MTC0 K0, SRSCtl
\r
23968 BFD04732 03BD12FC ADDI S7, GP, 957
\r
23969 BFD04734 F17C03BD WRPGPR SP, SP
\r
23970 BFD04736 036CF17C JALX 0xBDF00DB0
\r
23971 BFD04738 02FC036C MTC0 K1, Status
\r
23972 BFD0473A 000002FC SLL S7, GP, 0
\r
23973 BFD0473C F37C0000 ERET
\r
23974 BFD0473E 03BDF37C JALX 0xBDF00EF4
\r
23976 158: void __attribute__((weak, interrupt, nomips16))
\r
23977 159: girq24_b2(void)
\r
23979 BFD04740 E17C03BD RDPGPR SP, SP
\r
23980 BFD04744 00FC036E MFC0 K1, EPC
\r
23981 BFD04746 034C00FC INS A3, GP, 13, -12
\r
23982 BFD04748 10FC034C MFC0 K0, SRSCtl
\r
23983 BFD0474A 4FC510FC ADDI A3, GP, 20421
\r
23984 BFD0474C 4FC5 ADDIU SP, SP, -120
\r
23985 BFD0474E CB7D SW K1, 116(SP)
\r
23986 BFD04750 00FC036C MFC0 K1, Status
\r
23987 BFD04754 CB5C SW K0, 112(SP)
\r
23988 BFD04756 00FC034D MFC0 K0, Cause
\r
23989 BFD0475A CB7B SW K1, 108(SP)
\r
23990 BFD0475C 5040035A SRL K0, K0, 10
\r
23991 BFD0475E 037A5040 ORI V0, ZERO, 890
\r
23992 BFD04760 7A8C037A INS K1, K0, 10, 6
\r
23993 BFD04762 03607A8C ADDIUPC A1, 787296
\r
23994 BFD04764 204C0360 INS K1, ZERO, 1, 4
\r
23995 BFD04766 036C204C LWC2 V0, 876(T4)
\r
23996 BFD04768 02FC036C MTC0 K1, Status
\r
23997 BFD0476C C867 SW V1, 28(SP)
\r
23998 BFD0476E C846 SW V0, 24(SP)
\r
23999 BFD04770 487C LW V1, 112(SP)
\r
24000 BFD04772 2DB7 ANDI V1, V1, 0xF
\r
24001 BFD04774 001140A3 BNEZC V1, 0xBFD0479A
\r
24002 BFD04778 CBF7 SW RA, 92(SP)
\r
24003 BFD0477A CBD6 SW S8, 88(SP)
\r
24004 BFD0477C CB35 SW T9, 84(SP)
\r
24005 BFD0477E CB14 SW T8, 80(SP)
\r
24006 BFD04780 C9F3 SW T7, 76(SP)
\r
24007 BFD04782 C9D2 SW T6, 72(SP)
\r
24008 BFD04784 C9B1 SW T5, 68(SP)
\r
24009 BFD04786 C990 SW T4, 64(SP)
\r
24010 BFD04788 C96F SW T3, 60(SP)
\r
24011 BFD0478A C94E SW T2, 56(SP)
\r
24012 BFD0478C C92D SW T1, 52(SP)
\r
24013 BFD0478E C90C SW T0, 48(SP)
\r
24014 BFD04790 C8EB SW A3, 44(SP)
\r
24015 BFD04792 C8CA SW A2, 40(SP)
\r
24016 BFD04794 C8A9 SW A1, 36(SP)
\r
24017 BFD04796 C888 SW A0, 32(SP)
\r
24018 BFD04798 C825 SW AT, 20(SP)
\r
24019 BFD0479A 4642 MFLO V0
\r
24020 BFD0479C C859 SW V0, 100(SP)
\r
24021 BFD0479E 4603 MFHI V1
\r
24022 BFD047A0 C878 SW V1, 96(SP)
\r
24023 BFD047A2 0FDD MOVE S8, SP
\r
24025 162: _CP0_BIC_CAUSE(0x200ul);
\r
24026 BFD047A4 02003040 ADDIU V0, ZERO, 512
\r
24027 BFD047A6 006D0200 PRECR.QB.PH ZERO, ZERO, S0
\r
24028 BFD047A8 00FC006D MFC0 V1, Cause
\r
24029 BFD047AA 0C0000FC SLL A3, GP, 1
\r
24030 BFD047AC 0C00 NOP
\r
24031 BFD047AE 4412 NOT16 V0, V0
\r
24032 BFD047B0 4493 AND16 V0, V1
\r
24033 BFD047B2 02FC004D MTC0 V0, Cause
\r
24034 BFD047B4 000002FC SLL S7, GP, 0
\r
24035 BFD047B6 18000000 SLL ZERO, ZERO, 3
\r
24036 BFD047B8 EE101800 SB ZERO, -4592(ZERO)
\r
24038 164: jtvic_clr_source(MEC14xx_GIRQ24_ID, 2);
\r
24039 BFD047BA EE10 LI A0, 16
\r
24040 BFD047BC EE82 LI A1, 2
\r
24041 BFD047BE 44FA77E8 JALS jtvic_clr_source
\r
24042 BFD047C0 44FA OR16 A3, V0
\r
24043 BFD047C2 0C00 NOP
\r
24045 BFD047C4 0FBE MOVE SP, S8
\r
24046 BFD047C6 4859 LW V0, 100(SP)
\r
24047 BFD047C8 3D7C0002 MTLO V0
\r
24048 BFD047CA 48783D7C LH T3, 18552(GP)
\r
24049 BFD047CC 4878 LW V1, 96(SP)
\r
24050 BFD047CE 2D7C0003 MTHI V1
\r
24051 BFD047D0 2D7C ANDI V0, A3, 0x40
\r
24052 BFD047D2 485C LW V0, 112(SP)
\r
24053 BFD047D4 2D27 ANDI V0, V0, 0xF
\r
24054 BFD047D6 001340A2 BNEZC V0, 0xBFD04800
\r
24055 BFD047DA 4BF7 LW RA, 92(SP)
\r
24056 BFD047DC 4BD6 LW S8, 88(SP)
\r
24057 BFD047DE 4B35 LW T9, 84(SP)
\r
24058 BFD047E0 4B14 LW T8, 80(SP)
\r
24059 BFD047E2 49F3 LW T7, 76(SP)
\r
24060 BFD047E4 49D2 LW T6, 72(SP)
\r
24061 BFD047E6 49B1 LW T5, 68(SP)
\r
24062 BFD047E8 4990 LW T4, 64(SP)
\r
24063 BFD047EA 496F LW T3, 60(SP)
\r
24064 BFD047EC 494E LW T2, 56(SP)
\r
24065 BFD047EE 492D LW T1, 52(SP)
\r
24066 BFD047F0 490C LW T0, 48(SP)
\r
24067 BFD047F2 48EB LW A3, 44(SP)
\r
24068 BFD047F4 48CA LW A2, 40(SP)
\r
24069 BFD047F6 48A9 LW A1, 36(SP)
\r
24070 BFD047F8 4888 LW A0, 32(SP)
\r
24071 BFD047FA 4867 LW V1, 28(SP)
\r
24072 BFD047FC 4846 LW V0, 24(SP)
\r
24073 BFD047FE 4825 LW AT, 20(SP)
\r
24074 BFD04800 477C0000 DI ZERO
\r
24075 BFD04804 18000000 SLL ZERO, ZERO, 3
\r
24076 BFD04806 4B5D1800 SB ZERO, 19293(ZERO)
\r
24077 BFD04808 4B5D LW K0, 116(SP)
\r
24078 BFD0480A 4B7B LW K1, 108(SP)
\r
24079 BFD0480C 02FC034E MTC0 K0, EPC
\r
24080 BFD04810 4B5C LW K0, 112(SP)
\r
24081 BFD04812 4C3D ADDIU SP, SP, 120
\r
24082 BFD04814 12FC034C MTC0 K0, SRSCtl
\r
24083 BFD04816 03BD12FC ADDI S7, GP, 957
\r
24084 BFD04818 F17C03BD WRPGPR SP, SP
\r
24085 BFD0481A 036CF17C JALX 0xBDF00DB0
\r
24086 BFD0481C 02FC036C MTC0 K1, Status
\r
24087 BFD0481E 000002FC SLL S7, GP, 0
\r
24088 BFD04820 F37C0000 ERET
\r
24089 BFD04822 4FEDF37C JALX 0xBDF13FB4
\r
24093 169: /* end girq24.c */
\r
24097 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq23.c ----
\r
24098 1: /*****************************************************************************
\r
24099 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
24100 3: * You may use this software and any derivatives exclusively with
\r
24101 4: * Microchip products.
\r
24102 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
24103 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
24104 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
24105 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
24106 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
24107 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
24108 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
24109 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
24110 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
24111 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
24112 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
24113 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
24114 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
24115 18: * OF THESE TERMS.
\r
24116 19: *****************************************************************************/
\r
24118 21: /** @file girq23.c
\r
24119 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
24121 24: /** @defgroup MEC14xx ISR
\r
24125 28: #include "appcfg.h"
\r
24126 29: #include "platform.h"
\r
24127 30: #include "MEC14xx/mec14xx.h"
\r
24128 31: #include "MEC14xx/mec14xx_girqs.h"
\r
24129 32: #include "MEC14xx/mec14xx_gpio.h"
\r
24130 33: #include "MEC14xx/mec14xx_bbled.h"
\r
24131 34: #include "MEC14xx/mec14xx_trace_func.h"
\r
24134 37: typedef void (* GIRQ23_FPVU8)(uint8_t);
\r
24136 39: #if GIRQ23_DISAGG == 0
\r
24139 42: * FreeRTOS ISR for HW timer used as RTOS tick.
\r
24140 43: * Implemented in MEC14xx FreeRTOS porting layer, port_asm.S
\r
24141 44: * It save/restores CPU context and clears HW timer interrupt
\r
24142 45: * status in JTVIC. On each timer tick it checks if any task
\r
24143 46: * requires service. If yes then it triggers the PendSV low
\r
24144 47: * priority software interrupt.
\r
24146 49: * When aggregated girq23_isr save CPU context but this context
\r
24147 50: * is not the same as a FreeRTOS context save. If the RTOS timer
\r
24148 51: * is active then girq23_isr would call vPortTickInterruptHandler
\r
24149 52: * which uses FreeRTOS portSAVE_CONTEXT macro to save RTOS + CPU
\r
24150 53: * context. At this point you have two context saves on the stack.
\r
24151 54: * There is a problem:
\r
24152 55: * vPortTickInterruptHandler does not return but exits using
\r
24153 56: * portRESTORE_CONTEXT. This means the context save performed
\r
24154 57: * by aggregated girq23_isr is left on the stack. Eventually
\r
24155 58: * a stack overflow will occur.
\r
24158 61: * 1. vPortTickInterruptHandler must be modified to handle scan
\r
24159 62: * GIRQ23 Result bits and all the respective handler. All
\r
24160 63: * other GIRQ23 source are called as hook functions.
\r
24162 65: * 2. Do not use vPortTickInterruptHandler.
\r
24163 66: * Modify girq23_isr here to use FreeRTOS portSAVE_CONTEXT
\r
24164 67: * and portRESTORE_CONTEXT macros.
\r
24165 68: * If RTOS timer is active interrupt then call vPortIncrementTick
\r
24166 69: * as vPortTickInterruptHandler does.
\r
24167 70: * For all other GIRQ23 sources call the respective handlers.
\r
24169 72: * NOTE: for both of the above solutions a we must either:
\r
24170 73: * A. Service one source only resulting in GIRQ23 firing multiple
\r
24171 74: * times if more than one source is active.
\r
24172 75: * B. Service all active sources with RTOS Timer checked first.
\r
24174 77: * We will implement 1A with a single hook for all other sources.
\r
24178 81: extern void vPortIncrementTick(void);
\r
24180 83: void girq23_dflt_handler(uint8_t inum)
\r
24182 85: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].EN_CLR = (1ul << inum);
\r
24183 86: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << inum);
\r
24186 89: void __attribute__((weak)) rtos_tmr_handler(uint8_t inum)
\r
24190 93: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
\r
24193 96: const GIRQ23_FPVU8 girq23_htable[GIRQ23_NUM_SOURCES] =
\r
24195 98: girq23_dflt_handler, /* btmr0_handler, */
\r
24196 99: girq23_dflt_handler, /* btmr1_handler, */
\r
24197 100: girq23_dflt_handler, /* btmr2_handler, */
\r
24198 101: girq23_dflt_handler, /* btmr3_handler, */
\r
24199 102: vPortIncrementTick,
\r
24200 103: girq23_dflt_handler, /* hib_tmr_handler, */
\r
24201 104: girq23_dflt_handler, /* week_tmr_handler, */
\r
24202 105: girq23_dflt_handler, /* week_tmr_handler, */
\r
24203 106: girq23_dflt_handler, /* week_tmr_handler, */
\r
24204 107: girq23_dflt_handler, /* week_tmr_handler, */
\r
24205 108: girq23_dflt_handler, /* week_tmr_handler, */
\r
24206 109: girq23_dflt_handler, /* vci_handler, */
\r
24207 110: girq23_dflt_handler, /* vci_handler, */
\r
24208 111: girq23_dflt_handler, /* vci_handler, */
\r
24211 114: /* Called by FreeRTOS vPortTickInterruptHandler(girq23_isr)
\r
24212 115: * after saving FreeRTOS context
\r
24214 117: void girq23_handler(void)
\r
24217 120: uint8_t bitpos;
\r
24219 122: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
\r
24220 123: while ( 0 != d )
\r
24222 125: bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
\r
24223 126: (girq23_htable[bitpos])(bitpos);
\r
24224 127: d &= ~(1ul << bitpos);
\r
24228 131: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
24229 132: girq23_isr(void)
\r
24232 135: uint8_t bitpos;
\r
24234 137: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
\r
24235 138: while ( 0 != d )
\r
24237 140: bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
\r
24238 141: (girq23_htable[bitpos])(bitpos);
\r
24239 142: d &= ~(1ul << bitpos);
\r
24246 149: /* 16-bit Basic Timer 0 */
\r
24247 150: void __attribute__((weak, interrupt, nomips16))
\r
24248 151: girq23_b0(void)
\r
24250 BFD072A0 E17C03BD RDPGPR SP, SP
\r
24251 BFD072A4 00FC036E MFC0 K1, EPC
\r
24252 BFD072A6 034C00FC INS A3, GP, 13, -12
\r
24253 BFD072A8 10FC034C MFC0 K0, SRSCtl
\r
24254 BFD072AA 4FF110FC ADDI A3, GP, 20465
\r
24255 BFD072AC 4FF1 ADDIU SP, SP, -32
\r
24256 BFD072AE CB67 SW K1, 28(SP)
\r
24257 BFD072B0 00FC036C MFC0 K1, Status
\r
24258 BFD072B4 CB46 SW K0, 24(SP)
\r
24259 BFD072B6 00FC034D MFC0 K0, Cause
\r
24260 BFD072BA CB65 SW K1, 20(SP)
\r
24261 BFD072BC 5040035A SRL K0, K0, 10
\r
24262 BFD072BE 037A5040 ORI V0, ZERO, 890
\r
24263 BFD072C0 7A8C037A INS K1, K0, 10, 6
\r
24264 BFD072C2 03607A8C ADDIUPC A1, 787296
\r
24265 BFD072C4 204C0360 INS K1, ZERO, 1, 4
\r
24266 BFD072C6 036C204C LWC2 V0, 876(T4)
\r
24267 BFD072C8 02FC036C MTC0 K1, Status
\r
24268 BFD072CC C862 SW V1, 8(SP)
\r
24269 BFD072CE C841 SW V0, 4(SP)
\r
24270 BFD072D0 4866 LW V1, 24(SP)
\r
24271 BFD072D2 2DB7 ANDI V1, V1, 0xF
\r
24272 BFD072D4 CBC3 SW S8, 12(SP)
\r
24273 BFD072D6 0FDD MOVE S8, SP
\r
24274 153: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 0);
\r
24275 BFD072D8 BFFF41A2 LUI V0, 0xBFFF
\r
24276 BFD072DA 5042BFFF LDC1 F31, 20546(RA)
\r
24277 BFD072DC C0005042 ORI V0, V0, -16384
\r
24278 BFD072E0 ED81 LI V1, 1
\r
24279 BFD072E2 00F0F862 SW V1, 240(V0)
\r
24281 BFD072E6 0FBE MOVE SP, S8
\r
24282 BFD072E8 4846 LW V0, 24(SP)
\r
24283 BFD072EA 2D27 ANDI V0, V0, 0xF
\r
24284 BFD072EC 4BC3 LW S8, 12(SP)
\r
24285 BFD072EE 4862 LW V1, 8(SP)
\r
24286 BFD072F0 4841 LW V0, 4(SP)
\r
24287 BFD072F2 477C0000 DI ZERO
\r
24288 BFD072F6 18000000 SLL ZERO, ZERO, 3
\r
24289 BFD072F8 4B471800 SB ZERO, 19271(ZERO)
\r
24290 BFD072FA 4B47 LW K0, 28(SP)
\r
24291 BFD072FC 4B65 LW K1, 20(SP)
\r
24292 BFD072FE 02FC034E MTC0 K0, EPC
\r
24293 BFD07302 4B46 LW K0, 24(SP)
\r
24294 BFD07304 4C11 ADDIU SP, SP, 32
\r
24295 BFD07306 12FC034C MTC0 K0, SRSCtl
\r
24296 BFD07308 03BD12FC ADDI S7, GP, 957
\r
24297 BFD0730A F17C03BD WRPGPR SP, SP
\r
24298 BFD0730C 036CF17C JALX 0xBDF00DB0
\r
24299 BFD0730E 02FC036C MTC0 K1, Status
\r
24300 BFD07310 000002FC SLL S7, GP, 0
\r
24301 BFD07312 F37C0000 ERET
\r
24302 BFD07314 0C00F37C JALX 0xBDF03000
\r
24304 156: /* 16-bit Basic Timer 1 */
\r
24305 157: void __attribute__((weak, interrupt, nomips16))
\r
24306 158: girq23_b1(void)
\r
24308 BFD04C70 E17C03BD RDPGPR SP, SP
\r
24309 BFD04C74 00FC036E MFC0 K1, EPC
\r
24310 BFD04C76 034C00FC INS A3, GP, 13, -12
\r
24311 BFD04C78 10FC034C MFC0 K0, SRSCtl
\r
24312 BFD04C7A 4FC510FC ADDI A3, GP, 20421
\r
24313 BFD04C7C 4FC5 ADDIU SP, SP, -120
\r
24314 BFD04C7E CB7D SW K1, 116(SP)
\r
24315 BFD04C80 00FC036C MFC0 K1, Status
\r
24316 BFD04C84 CB5C SW K0, 112(SP)
\r
24317 BFD04C86 00FC034D MFC0 K0, Cause
\r
24318 BFD04C8A CB7B SW K1, 108(SP)
\r
24319 BFD04C8C 5040035A SRL K0, K0, 10
\r
24320 BFD04C8E 037A5040 ORI V0, ZERO, 890
\r
24321 BFD04C90 7A8C037A INS K1, K0, 10, 6
\r
24322 BFD04C92 03607A8C ADDIUPC A1, 787296
\r
24323 BFD04C94 204C0360 INS K1, ZERO, 1, 4
\r
24324 BFD04C96 036C204C LWC2 V0, 876(T4)
\r
24325 BFD04C98 02FC036C MTC0 K1, Status
\r
24326 BFD04C9C C867 SW V1, 28(SP)
\r
24327 BFD04C9E C846 SW V0, 24(SP)
\r
24328 BFD04CA0 487C LW V1, 112(SP)
\r
24329 BFD04CA2 2DB7 ANDI V1, V1, 0xF
\r
24330 BFD04CA4 001140A3 BNEZC V1, 0xBFD04CCA
\r
24331 BFD04CA8 CBF7 SW RA, 92(SP)
\r
24332 BFD04CAA CBD6 SW S8, 88(SP)
\r
24333 BFD04CAC CB35 SW T9, 84(SP)
\r
24334 BFD04CAE CB14 SW T8, 80(SP)
\r
24335 BFD04CB0 C9F3 SW T7, 76(SP)
\r
24336 BFD04CB2 C9D2 SW T6, 72(SP)
\r
24337 BFD04CB4 C9B1 SW T5, 68(SP)
\r
24338 BFD04CB6 C990 SW T4, 64(SP)
\r
24339 BFD04CB8 C96F SW T3, 60(SP)
\r
24340 BFD04CBA C94E SW T2, 56(SP)
\r
24341 BFD04CBC C92D SW T1, 52(SP)
\r
24342 BFD04CBE C90C SW T0, 48(SP)
\r
24343 BFD04CC0 C8EB SW A3, 44(SP)
\r
24344 BFD04CC2 C8CA SW A2, 40(SP)
\r
24345 BFD04CC4 C8A9 SW A1, 36(SP)
\r
24346 BFD04CC6 C888 SW A0, 32(SP)
\r
24347 BFD04CC8 C825 SW AT, 20(SP)
\r
24348 BFD04CCA 4642 MFLO V0
\r
24349 BFD04CCC C859 SW V0, 100(SP)
\r
24350 BFD04CCE 4603 MFHI V1
\r
24351 BFD04CD0 C878 SW V1, 96(SP)
\r
24352 BFD04CD2 0FDD MOVE S8, SP
\r
24353 160: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 1, TRUE);
\r
24354 BFD04CD4 EE0F LI A0, 15
\r
24355 BFD04CD6 EE81 LI A1, 1
\r
24356 BFD04CD8 EF01 LI A2, 1
\r
24357 BFD04CDA 3A4077E8 JALS jtvic_dis_clr_source
\r
24358 BFD04CDC 0C003A40 SH S2, 3072(ZERO)
\r
24359 BFD04CDE 0C00 NOP
\r
24361 BFD04CE0 0FBE MOVE SP, S8
\r
24362 BFD04CE2 4859 LW V0, 100(SP)
\r
24363 BFD04CE4 3D7C0002 MTLO V0
\r
24364 BFD04CE6 48783D7C LH T3, 18552(GP)
\r
24365 BFD04CE8 4878 LW V1, 96(SP)
\r
24366 BFD04CEA 2D7C0003 MTHI V1
\r
24367 BFD04CEC 2D7C ANDI V0, A3, 0x40
\r
24368 BFD04CEE 485C LW V0, 112(SP)
\r
24369 BFD04CF0 2D27 ANDI V0, V0, 0xF
\r
24370 BFD04CF2 001340A2 BNEZC V0, 0xBFD04D1C
\r
24371 BFD04CF6 4BF7 LW RA, 92(SP)
\r
24372 BFD04CF8 4BD6 LW S8, 88(SP)
\r
24373 BFD04CFA 4B35 LW T9, 84(SP)
\r
24374 BFD04CFC 4B14 LW T8, 80(SP)
\r
24375 BFD04CFE 49F3 LW T7, 76(SP)
\r
24376 BFD04D00 49D2 LW T6, 72(SP)
\r
24377 BFD04D02 49B1 LW T5, 68(SP)
\r
24378 BFD04D04 4990 LW T4, 64(SP)
\r
24379 BFD04D06 496F LW T3, 60(SP)
\r
24380 BFD04D08 494E LW T2, 56(SP)
\r
24381 BFD04D0A 492D LW T1, 52(SP)
\r
24382 BFD04D0C 490C LW T0, 48(SP)
\r
24383 BFD04D0E 48EB LW A3, 44(SP)
\r
24384 BFD04D10 48CA LW A2, 40(SP)
\r
24385 BFD04D12 48A9 LW A1, 36(SP)
\r
24386 BFD04D14 4888 LW A0, 32(SP)
\r
24387 BFD04D16 4867 LW V1, 28(SP)
\r
24388 BFD04D18 4846 LW V0, 24(SP)
\r
24389 BFD04D1A 4825 LW AT, 20(SP)
\r
24390 BFD04D1C 477C0000 DI ZERO
\r
24391 BFD04D20 18000000 SLL ZERO, ZERO, 3
\r
24392 BFD04D22 4B5D1800 SB ZERO, 19293(ZERO)
\r
24393 BFD04D24 4B5D LW K0, 116(SP)
\r
24394 BFD04D26 4B7B LW K1, 108(SP)
\r
24395 BFD04D28 02FC034E MTC0 K0, EPC
\r
24396 BFD04D2C 4B5C LW K0, 112(SP)
\r
24397 BFD04D2E 4C3D ADDIU SP, SP, 120
\r
24398 BFD04D30 12FC034C MTC0 K0, SRSCtl
\r
24399 BFD04D32 03BD12FC ADDI S7, GP, 957
\r
24400 BFD04D34 F17C03BD WRPGPR SP, SP
\r
24401 BFD04D36 036CF17C JALX 0xBDF00DB0
\r
24402 BFD04D38 02FC036C MTC0 K1, Status
\r
24403 BFD04D3A 000002FC SLL S7, GP, 0
\r
24404 BFD04D3C F37C0000 ERET
\r
24405 BFD04D3E 03BDF37C JALX 0xBDF00EF4
\r
24407 163: /* 16-bit Basic Timer 2 */
\r
24408 164: void __attribute__((weak, interrupt, nomips16))
\r
24409 165: girq23_b2(void)
\r
24411 BFD04D40 E17C03BD RDPGPR SP, SP
\r
24412 BFD04D44 00FC036E MFC0 K1, EPC
\r
24413 BFD04D46 034C00FC INS A3, GP, 13, -12
\r
24414 BFD04D48 10FC034C MFC0 K0, SRSCtl
\r
24415 BFD04D4A 4FC510FC ADDI A3, GP, 20421
\r
24416 BFD04D4C 4FC5 ADDIU SP, SP, -120
\r
24417 BFD04D4E CB7D SW K1, 116(SP)
\r
24418 BFD04D50 00FC036C MFC0 K1, Status
\r
24419 BFD04D54 CB5C SW K0, 112(SP)
\r
24420 BFD04D56 00FC034D MFC0 K0, Cause
\r
24421 BFD04D5A CB7B SW K1, 108(SP)
\r
24422 BFD04D5C 5040035A SRL K0, K0, 10
\r
24423 BFD04D5E 037A5040 ORI V0, ZERO, 890
\r
24424 BFD04D60 7A8C037A INS K1, K0, 10, 6
\r
24425 BFD04D62 03607A8C ADDIUPC A1, 787296
\r
24426 BFD04D64 204C0360 INS K1, ZERO, 1, 4
\r
24427 BFD04D66 036C204C LWC2 V0, 876(T4)
\r
24428 BFD04D68 02FC036C MTC0 K1, Status
\r
24429 BFD04D6C C867 SW V1, 28(SP)
\r
24430 BFD04D6E C846 SW V0, 24(SP)
\r
24431 BFD04D70 487C LW V1, 112(SP)
\r
24432 BFD04D72 2DB7 ANDI V1, V1, 0xF
\r
24433 BFD04D74 001140A3 BNEZC V1, 0xBFD04D9A
\r
24434 BFD04D78 CBF7 SW RA, 92(SP)
\r
24435 BFD04D7A CBD6 SW S8, 88(SP)
\r
24436 BFD04D7C CB35 SW T9, 84(SP)
\r
24437 BFD04D7E CB14 SW T8, 80(SP)
\r
24438 BFD04D80 C9F3 SW T7, 76(SP)
\r
24439 BFD04D82 C9D2 SW T6, 72(SP)
\r
24440 BFD04D84 C9B1 SW T5, 68(SP)
\r
24441 BFD04D86 C990 SW T4, 64(SP)
\r
24442 BFD04D88 C96F SW T3, 60(SP)
\r
24443 BFD04D8A C94E SW T2, 56(SP)
\r
24444 BFD04D8C C92D SW T1, 52(SP)
\r
24445 BFD04D8E C90C SW T0, 48(SP)
\r
24446 BFD04D90 C8EB SW A3, 44(SP)
\r
24447 BFD04D92 C8CA SW A2, 40(SP)
\r
24448 BFD04D94 C8A9 SW A1, 36(SP)
\r
24449 BFD04D96 C888 SW A0, 32(SP)
\r
24450 BFD04D98 C825 SW AT, 20(SP)
\r
24451 BFD04D9A 4642 MFLO V0
\r
24452 BFD04D9C C859 SW V0, 100(SP)
\r
24453 BFD04D9E 4603 MFHI V1
\r
24454 BFD04DA0 C878 SW V1, 96(SP)
\r
24455 BFD04DA2 0FDD MOVE S8, SP
\r
24456 167: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 2, TRUE);
\r
24457 BFD04DA4 EE0F LI A0, 15
\r
24458 BFD04DA6 EE82 LI A1, 2
\r
24459 BFD04DA8 EF01 LI A2, 1
\r
24460 BFD04DAA 3A4077E8 JALS jtvic_dis_clr_source
\r
24461 BFD04DAC 0C003A40 SH S2, 3072(ZERO)
\r
24462 BFD04DAE 0C00 NOP
\r
24464 BFD04DB0 0FBE MOVE SP, S8
\r
24465 BFD04DB2 4859 LW V0, 100(SP)
\r
24466 BFD04DB4 3D7C0002 MTLO V0
\r
24467 BFD04DB6 48783D7C LH T3, 18552(GP)
\r
24468 BFD04DB8 4878 LW V1, 96(SP)
\r
24469 BFD04DBA 2D7C0003 MTHI V1
\r
24470 BFD04DBC 2D7C ANDI V0, A3, 0x40
\r
24471 BFD04DBE 485C LW V0, 112(SP)
\r
24472 BFD04DC0 2D27 ANDI V0, V0, 0xF
\r
24473 BFD04DC2 001340A2 BNEZC V0, 0xBFD04DEC
\r
24474 BFD04DC6 4BF7 LW RA, 92(SP)
\r
24475 BFD04DC8 4BD6 LW S8, 88(SP)
\r
24476 BFD04DCA 4B35 LW T9, 84(SP)
\r
24477 BFD04DCC 4B14 LW T8, 80(SP)
\r
24478 BFD04DCE 49F3 LW T7, 76(SP)
\r
24479 BFD04DD0 49D2 LW T6, 72(SP)
\r
24480 BFD04DD2 49B1 LW T5, 68(SP)
\r
24481 BFD04DD4 4990 LW T4, 64(SP)
\r
24482 BFD04DD6 496F LW T3, 60(SP)
\r
24483 BFD04DD8 494E LW T2, 56(SP)
\r
24484 BFD04DDA 492D LW T1, 52(SP)
\r
24485 BFD04DDC 490C LW T0, 48(SP)
\r
24486 BFD04DDE 48EB LW A3, 44(SP)
\r
24487 BFD04DE0 48CA LW A2, 40(SP)
\r
24488 BFD04DE2 48A9 LW A1, 36(SP)
\r
24489 BFD04DE4 4888 LW A0, 32(SP)
\r
24490 BFD04DE6 4867 LW V1, 28(SP)
\r
24491 BFD04DE8 4846 LW V0, 24(SP)
\r
24492 BFD04DEA 4825 LW AT, 20(SP)
\r
24493 BFD04DEC 477C0000 DI ZERO
\r
24494 BFD04DF0 18000000 SLL ZERO, ZERO, 3
\r
24495 BFD04DF2 4B5D1800 SB ZERO, 19293(ZERO)
\r
24496 BFD04DF4 4B5D LW K0, 116(SP)
\r
24497 BFD04DF6 4B7B LW K1, 108(SP)
\r
24498 BFD04DF8 02FC034E MTC0 K0, EPC
\r
24499 BFD04DFC 4B5C LW K0, 112(SP)
\r
24500 BFD04DFE 4C3D ADDIU SP, SP, 120
\r
24501 BFD04E00 12FC034C MTC0 K0, SRSCtl
\r
24502 BFD04E02 03BD12FC ADDI S7, GP, 957
\r
24503 BFD04E04 F17C03BD WRPGPR SP, SP
\r
24504 BFD04E06 036CF17C JALX 0xBDF00DB0
\r
24505 BFD04E08 02FC036C MTC0 K1, Status
\r
24506 BFD04E0A 000002FC SLL S7, GP, 0
\r
24507 BFD04E0C F37C0000 ERET
\r
24508 BFD04E0E 03BDF37C JALX 0xBDF00EF4
\r
24510 170: /* 16-bit Basic Timer 3 */
\r
24511 171: void __attribute__((weak, interrupt, nomips16))
\r
24512 172: girq23_b3(void)
\r
24514 BFD04E10 E17C03BD RDPGPR SP, SP
\r
24515 BFD04E14 00FC036E MFC0 K1, EPC
\r
24516 BFD04E16 034C00FC INS A3, GP, 13, -12
\r
24517 BFD04E18 10FC034C MFC0 K0, SRSCtl
\r
24518 BFD04E1A 4FC510FC ADDI A3, GP, 20421
\r
24519 BFD04E1C 4FC5 ADDIU SP, SP, -120
\r
24520 BFD04E1E CB7D SW K1, 116(SP)
\r
24521 BFD04E20 00FC036C MFC0 K1, Status
\r
24522 BFD04E24 CB5C SW K0, 112(SP)
\r
24523 BFD04E26 00FC034D MFC0 K0, Cause
\r
24524 BFD04E2A CB7B SW K1, 108(SP)
\r
24525 BFD04E2C 5040035A SRL K0, K0, 10
\r
24526 BFD04E2E 037A5040 ORI V0, ZERO, 890
\r
24527 BFD04E30 7A8C037A INS K1, K0, 10, 6
\r
24528 BFD04E32 03607A8C ADDIUPC A1, 787296
\r
24529 BFD04E34 204C0360 INS K1, ZERO, 1, 4
\r
24530 BFD04E36 036C204C LWC2 V0, 876(T4)
\r
24531 BFD04E38 02FC036C MTC0 K1, Status
\r
24532 BFD04E3C C867 SW V1, 28(SP)
\r
24533 BFD04E3E C846 SW V0, 24(SP)
\r
24534 BFD04E40 487C LW V1, 112(SP)
\r
24535 BFD04E42 2DB7 ANDI V1, V1, 0xF
\r
24536 BFD04E44 001140A3 BNEZC V1, 0xBFD04E6A
\r
24537 BFD04E48 CBF7 SW RA, 92(SP)
\r
24538 BFD04E4A CBD6 SW S8, 88(SP)
\r
24539 BFD04E4C CB35 SW T9, 84(SP)
\r
24540 BFD04E4E CB14 SW T8, 80(SP)
\r
24541 BFD04E50 C9F3 SW T7, 76(SP)
\r
24542 BFD04E52 C9D2 SW T6, 72(SP)
\r
24543 BFD04E54 C9B1 SW T5, 68(SP)
\r
24544 BFD04E56 C990 SW T4, 64(SP)
\r
24545 BFD04E58 C96F SW T3, 60(SP)
\r
24546 BFD04E5A C94E SW T2, 56(SP)
\r
24547 BFD04E5C C92D SW T1, 52(SP)
\r
24548 BFD04E5E C90C SW T0, 48(SP)
\r
24549 BFD04E60 C8EB SW A3, 44(SP)
\r
24550 BFD04E62 C8CA SW A2, 40(SP)
\r
24551 BFD04E64 C8A9 SW A1, 36(SP)
\r
24552 BFD04E66 C888 SW A0, 32(SP)
\r
24553 BFD04E68 C825 SW AT, 20(SP)
\r
24554 BFD04E6A 4642 MFLO V0
\r
24555 BFD04E6C C859 SW V0, 100(SP)
\r
24556 BFD04E6E 4603 MFHI V1
\r
24557 BFD04E70 C878 SW V1, 96(SP)
\r
24558 BFD04E72 0FDD MOVE S8, SP
\r
24559 174: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 3, TRUE);
\r
24560 BFD04E74 EE0F LI A0, 15
\r
24561 BFD04E76 EE83 LI A1, 3
\r
24562 BFD04E78 EF01 LI A2, 1
\r
24563 BFD04E7A 3A4077E8 JALS jtvic_dis_clr_source
\r
24564 BFD04E7C 0C003A40 SH S2, 3072(ZERO)
\r
24565 BFD04E7E 0C00 NOP
\r
24567 BFD04E80 0FBE MOVE SP, S8
\r
24568 BFD04E82 4859 LW V0, 100(SP)
\r
24569 BFD04E84 3D7C0002 MTLO V0
\r
24570 BFD04E86 48783D7C LH T3, 18552(GP)
\r
24571 BFD04E88 4878 LW V1, 96(SP)
\r
24572 BFD04E8A 2D7C0003 MTHI V1
\r
24573 BFD04E8C 2D7C ANDI V0, A3, 0x40
\r
24574 BFD04E8E 485C LW V0, 112(SP)
\r
24575 BFD04E90 2D27 ANDI V0, V0, 0xF
\r
24576 BFD04E92 001340A2 BNEZC V0, 0xBFD04EBC
\r
24577 BFD04E96 4BF7 LW RA, 92(SP)
\r
24578 BFD04E98 4BD6 LW S8, 88(SP)
\r
24579 BFD04E9A 4B35 LW T9, 84(SP)
\r
24580 BFD04E9C 4B14 LW T8, 80(SP)
\r
24581 BFD04E9E 49F3 LW T7, 76(SP)
\r
24582 BFD04EA0 49D2 LW T6, 72(SP)
\r
24583 BFD04EA2 49B1 LW T5, 68(SP)
\r
24584 BFD04EA4 4990 LW T4, 64(SP)
\r
24585 BFD04EA6 496F LW T3, 60(SP)
\r
24586 BFD04EA8 494E LW T2, 56(SP)
\r
24587 BFD04EAA 492D LW T1, 52(SP)
\r
24588 BFD04EAC 490C LW T0, 48(SP)
\r
24589 BFD04EAE 48EB LW A3, 44(SP)
\r
24590 BFD04EB0 48CA LW A2, 40(SP)
\r
24591 BFD04EB2 48A9 LW A1, 36(SP)
\r
24592 BFD04EB4 4888 LW A0, 32(SP)
\r
24593 BFD04EB6 4867 LW V1, 28(SP)
\r
24594 BFD04EB8 4846 LW V0, 24(SP)
\r
24595 BFD04EBA 4825 LW AT, 20(SP)
\r
24596 BFD04EBC 477C0000 DI ZERO
\r
24597 BFD04EC0 18000000 SLL ZERO, ZERO, 3
\r
24598 BFD04EC2 4B5D1800 SB ZERO, 19293(ZERO)
\r
24599 BFD04EC4 4B5D LW K0, 116(SP)
\r
24600 BFD04EC6 4B7B LW K1, 108(SP)
\r
24601 BFD04EC8 02FC034E MTC0 K0, EPC
\r
24602 BFD04ECC 4B5C LW K0, 112(SP)
\r
24603 BFD04ECE 4C3D ADDIU SP, SP, 120
\r
24604 BFD04ED0 12FC034C MTC0 K0, SRSCtl
\r
24605 BFD04ED2 03BD12FC ADDI S7, GP, 957
\r
24606 BFD04ED4 F17C03BD WRPGPR SP, SP
\r
24607 BFD04ED6 036CF17C JALX 0xBDF00DB0
\r
24608 BFD04ED8 02FC036C MTC0 K1, Status
\r
24609 BFD04EDA 000002FC SLL S7, GP, 0
\r
24610 BFD04EDC F37C0000 ERET
\r
24611 BFD04EDE 03BDF37C JALX 0xBDF00EF4
\r
24613 177: /* RTOS Timer */
\r
24614 178: void __attribute__((weak, interrupt, nomips16))
\r
24615 179: girq23_b4(void)
\r
24617 BFD07318 E17C03BD RDPGPR SP, SP
\r
24618 BFD0731C 00FC036E MFC0 K1, EPC
\r
24619 BFD0731E 034C00FC INS A3, GP, 13, -12
\r
24620 BFD07320 10FC034C MFC0 K0, SRSCtl
\r
24621 BFD07322 4FF110FC ADDI A3, GP, 20465
\r
24622 BFD07324 4FF1 ADDIU SP, SP, -32
\r
24623 BFD07326 CB67 SW K1, 28(SP)
\r
24624 BFD07328 00FC036C MFC0 K1, Status
\r
24625 BFD0732C CB46 SW K0, 24(SP)
\r
24626 BFD0732E 00FC034D MFC0 K0, Cause
\r
24627 BFD07332 CB65 SW K1, 20(SP)
\r
24628 BFD07334 5040035A SRL K0, K0, 10
\r
24629 BFD07336 037A5040 ORI V0, ZERO, 890
\r
24630 BFD07338 7A8C037A INS K1, K0, 10, 6
\r
24631 BFD0733A 03607A8C ADDIUPC A1, 787296
\r
24632 BFD0733C 204C0360 INS K1, ZERO, 1, 4
\r
24633 BFD0733E 036C204C LWC2 V0, 876(T4)
\r
24634 BFD07340 02FC036C MTC0 K1, Status
\r
24635 BFD07344 C862 SW V1, 8(SP)
\r
24636 BFD07346 C841 SW V0, 4(SP)
\r
24637 BFD07348 4866 LW V1, 24(SP)
\r
24638 BFD0734A 2DB7 ANDI V1, V1, 0xF
\r
24639 BFD0734C CBC3 SW S8, 12(SP)
\r
24640 BFD0734E 0FDD MOVE S8, SP
\r
24641 181: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
\r
24642 BFD07350 BFFF41A2 LUI V0, 0xBFFF
\r
24643 BFD07352 5042BFFF LDC1 F31, 20546(RA)
\r
24644 BFD07354 C0005042 ORI V0, V0, -16384
\r
24645 BFD07358 ED90 LI V1, 16
\r
24646 BFD0735A 00F0F862 SW V1, 240(V0)
\r
24649 BFD0735E 0FBE MOVE SP, S8
\r
24650 BFD07360 4846 LW V0, 24(SP)
\r
24651 BFD07362 2D27 ANDI V0, V0, 0xF
\r
24652 BFD07364 4BC3 LW S8, 12(SP)
\r
24653 BFD07366 4862 LW V1, 8(SP)
\r
24654 BFD07368 4841 LW V0, 4(SP)
\r
24655 BFD0736A 477C0000 DI ZERO
\r
24656 BFD0736E 18000000 SLL ZERO, ZERO, 3
\r
24657 BFD07370 4B471800 SB ZERO, 19271(ZERO)
\r
24658 BFD07372 4B47 LW K0, 28(SP)
\r
24659 BFD07374 4B65 LW K1, 20(SP)
\r
24660 BFD07376 02FC034E MTC0 K0, EPC
\r
24661 BFD0737A 4B46 LW K0, 24(SP)
\r
24662 BFD0737C 4C11 ADDIU SP, SP, 32
\r
24663 BFD0737E 12FC034C MTC0 K0, SRSCtl
\r
24664 BFD07380 03BD12FC ADDI S7, GP, 957
\r
24665 BFD07382 F17C03BD WRPGPR SP, SP
\r
24666 BFD07384 036CF17C JALX 0xBDF00DB0
\r
24667 BFD07386 02FC036C MTC0 K1, Status
\r
24668 BFD07388 000002FC SLL S7, GP, 0
\r
24669 BFD0738A F37C0000 ERET
\r
24670 BFD0738C 0C00F37C JALX 0xBDF03000
\r
24672 185: /* Hibernation Timer */
\r
24673 186: void __attribute__((weak, interrupt, nomips16))
\r
24674 187: girq23_b5(void)
\r
24676 BFD04EE0 E17C03BD RDPGPR SP, SP
\r
24677 BFD04EE4 00FC036E MFC0 K1, EPC
\r
24678 BFD04EE6 034C00FC INS A3, GP, 13, -12
\r
24679 BFD04EE8 10FC034C MFC0 K0, SRSCtl
\r
24680 BFD04EEA 4FC510FC ADDI A3, GP, 20421
\r
24681 BFD04EEC 4FC5 ADDIU SP, SP, -120
\r
24682 BFD04EEE CB7D SW K1, 116(SP)
\r
24683 BFD04EF0 00FC036C MFC0 K1, Status
\r
24684 BFD04EF4 CB5C SW K0, 112(SP)
\r
24685 BFD04EF6 00FC034D MFC0 K0, Cause
\r
24686 BFD04EFA CB7B SW K1, 108(SP)
\r
24687 BFD04EFC 5040035A SRL K0, K0, 10
\r
24688 BFD04EFE 037A5040 ORI V0, ZERO, 890
\r
24689 BFD04F00 7A8C037A INS K1, K0, 10, 6
\r
24690 BFD04F02 03607A8C ADDIUPC A1, 787296
\r
24691 BFD04F04 204C0360 INS K1, ZERO, 1, 4
\r
24692 BFD04F06 036C204C LWC2 V0, 876(T4)
\r
24693 BFD04F08 02FC036C MTC0 K1, Status
\r
24694 BFD04F0C C867 SW V1, 28(SP)
\r
24695 BFD04F0E C846 SW V0, 24(SP)
\r
24696 BFD04F10 487C LW V1, 112(SP)
\r
24697 BFD04F12 2DB7 ANDI V1, V1, 0xF
\r
24698 BFD04F14 001140A3 BNEZC V1, 0xBFD04F3A
\r
24699 BFD04F18 CBF7 SW RA, 92(SP)
\r
24700 BFD04F1A CBD6 SW S8, 88(SP)
\r
24701 BFD04F1C CB35 SW T9, 84(SP)
\r
24702 BFD04F1E CB14 SW T8, 80(SP)
\r
24703 BFD04F20 C9F3 SW T7, 76(SP)
\r
24704 BFD04F22 C9D2 SW T6, 72(SP)
\r
24705 BFD04F24 C9B1 SW T5, 68(SP)
\r
24706 BFD04F26 C990 SW T4, 64(SP)
\r
24707 BFD04F28 C96F SW T3, 60(SP)
\r
24708 BFD04F2A C94E SW T2, 56(SP)
\r
24709 BFD04F2C C92D SW T1, 52(SP)
\r
24710 BFD04F2E C90C SW T0, 48(SP)
\r
24711 BFD04F30 C8EB SW A3, 44(SP)
\r
24712 BFD04F32 C8CA SW A2, 40(SP)
\r
24713 BFD04F34 C8A9 SW A1, 36(SP)
\r
24714 BFD04F36 C888 SW A0, 32(SP)
\r
24715 BFD04F38 C825 SW AT, 20(SP)
\r
24716 BFD04F3A 4642 MFLO V0
\r
24717 BFD04F3C C859 SW V0, 100(SP)
\r
24718 BFD04F3E 4603 MFHI V1
\r
24719 BFD04F40 C878 SW V1, 96(SP)
\r
24720 BFD04F42 0FDD MOVE S8, SP
\r
24721 189: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 5, TRUE);
\r
24722 BFD04F44 EE0F LI A0, 15
\r
24723 BFD04F46 EE85 LI A1, 5
\r
24724 BFD04F48 EF01 LI A2, 1
\r
24725 BFD04F4A 3A4077E8 JALS jtvic_dis_clr_source
\r
24726 BFD04F4C 0C003A40 SH S2, 3072(ZERO)
\r
24727 BFD04F4E 0C00 NOP
\r
24729 BFD04F50 0FBE MOVE SP, S8
\r
24730 BFD04F52 4859 LW V0, 100(SP)
\r
24731 BFD04F54 3D7C0002 MTLO V0
\r
24732 BFD04F56 48783D7C LH T3, 18552(GP)
\r
24733 BFD04F58 4878 LW V1, 96(SP)
\r
24734 BFD04F5A 2D7C0003 MTHI V1
\r
24735 BFD04F5C 2D7C ANDI V0, A3, 0x40
\r
24736 BFD04F5E 485C LW V0, 112(SP)
\r
24737 BFD04F60 2D27 ANDI V0, V0, 0xF
\r
24738 BFD04F62 001340A2 BNEZC V0, 0xBFD04F8C
\r
24739 BFD04F66 4BF7 LW RA, 92(SP)
\r
24740 BFD04F68 4BD6 LW S8, 88(SP)
\r
24741 BFD04F6A 4B35 LW T9, 84(SP)
\r
24742 BFD04F6C 4B14 LW T8, 80(SP)
\r
24743 BFD04F6E 49F3 LW T7, 76(SP)
\r
24744 BFD04F70 49D2 LW T6, 72(SP)
\r
24745 BFD04F72 49B1 LW T5, 68(SP)
\r
24746 BFD04F74 4990 LW T4, 64(SP)
\r
24747 BFD04F76 496F LW T3, 60(SP)
\r
24748 BFD04F78 494E LW T2, 56(SP)
\r
24749 BFD04F7A 492D LW T1, 52(SP)
\r
24750 BFD04F7C 490C LW T0, 48(SP)
\r
24751 BFD04F7E 48EB LW A3, 44(SP)
\r
24752 BFD04F80 48CA LW A2, 40(SP)
\r
24753 BFD04F82 48A9 LW A1, 36(SP)
\r
24754 BFD04F84 4888 LW A0, 32(SP)
\r
24755 BFD04F86 4867 LW V1, 28(SP)
\r
24756 BFD04F88 4846 LW V0, 24(SP)
\r
24757 BFD04F8A 4825 LW AT, 20(SP)
\r
24758 BFD04F8C 477C0000 DI ZERO
\r
24759 BFD04F90 18000000 SLL ZERO, ZERO, 3
\r
24760 BFD04F92 4B5D1800 SB ZERO, 19293(ZERO)
\r
24761 BFD04F94 4B5D LW K0, 116(SP)
\r
24762 BFD04F96 4B7B LW K1, 108(SP)
\r
24763 BFD04F98 02FC034E MTC0 K0, EPC
\r
24764 BFD04F9C 4B5C LW K0, 112(SP)
\r
24765 BFD04F9E 4C3D ADDIU SP, SP, 120
\r
24766 BFD04FA0 12FC034C MTC0 K0, SRSCtl
\r
24767 BFD04FA2 03BD12FC ADDI S7, GP, 957
\r
24768 BFD04FA4 F17C03BD WRPGPR SP, SP
\r
24769 BFD04FA6 036CF17C JALX 0xBDF00DB0
\r
24770 BFD04FA8 02FC036C MTC0 K1, Status
\r
24771 BFD04FAA 000002FC SLL S7, GP, 0
\r
24772 BFD04FAC F37C0000 ERET
\r
24773 BFD04FAE 03BDF37C JALX 0xBDF00EF4
\r
24775 192: /* Week Alarm */
\r
24776 193: void __attribute__((weak, interrupt, nomips16))
\r
24777 194: girq23_b6(void)
\r
24779 BFD04FB0 E17C03BD RDPGPR SP, SP
\r
24780 BFD04FB4 00FC036E MFC0 K1, EPC
\r
24781 BFD04FB6 034C00FC INS A3, GP, 13, -12
\r
24782 BFD04FB8 10FC034C MFC0 K0, SRSCtl
\r
24783 BFD04FBA 4FC510FC ADDI A3, GP, 20421
\r
24784 BFD04FBC 4FC5 ADDIU SP, SP, -120
\r
24785 BFD04FBE CB7D SW K1, 116(SP)
\r
24786 BFD04FC0 00FC036C MFC0 K1, Status
\r
24787 BFD04FC4 CB5C SW K0, 112(SP)
\r
24788 BFD04FC6 00FC034D MFC0 K0, Cause
\r
24789 BFD04FCA CB7B SW K1, 108(SP)
\r
24790 BFD04FCC 5040035A SRL K0, K0, 10
\r
24791 BFD04FCE 037A5040 ORI V0, ZERO, 890
\r
24792 BFD04FD0 7A8C037A INS K1, K0, 10, 6
\r
24793 BFD04FD2 03607A8C ADDIUPC A1, 787296
\r
24794 BFD04FD4 204C0360 INS K1, ZERO, 1, 4
\r
24795 BFD04FD6 036C204C LWC2 V0, 876(T4)
\r
24796 BFD04FD8 02FC036C MTC0 K1, Status
\r
24797 BFD04FDC C867 SW V1, 28(SP)
\r
24798 BFD04FDE C846 SW V0, 24(SP)
\r
24799 BFD04FE0 487C LW V1, 112(SP)
\r
24800 BFD04FE2 2DB7 ANDI V1, V1, 0xF
\r
24801 BFD04FE4 001140A3 BNEZC V1, 0xBFD0500A
\r
24802 BFD04FE8 CBF7 SW RA, 92(SP)
\r
24803 BFD04FEA CBD6 SW S8, 88(SP)
\r
24804 BFD04FEC CB35 SW T9, 84(SP)
\r
24805 BFD04FEE CB14 SW T8, 80(SP)
\r
24806 BFD04FF0 C9F3 SW T7, 76(SP)
\r
24807 BFD04FF2 C9D2 SW T6, 72(SP)
\r
24808 BFD04FF4 C9B1 SW T5, 68(SP)
\r
24809 BFD04FF6 C990 SW T4, 64(SP)
\r
24810 BFD04FF8 C96F SW T3, 60(SP)
\r
24811 BFD04FFA C94E SW T2, 56(SP)
\r
24812 BFD04FFC C92D SW T1, 52(SP)
\r
24813 BFD04FFE C90C SW T0, 48(SP)
\r
24814 BFD05000 C8EB SW A3, 44(SP)
\r
24815 BFD05002 C8CA SW A2, 40(SP)
\r
24816 BFD05004 C8A9 SW A1, 36(SP)
\r
24817 BFD05006 C888 SW A0, 32(SP)
\r
24818 BFD05008 C825 SW AT, 20(SP)
\r
24819 BFD0500A 4642 MFLO V0
\r
24820 BFD0500C C859 SW V0, 100(SP)
\r
24821 BFD0500E 4603 MFHI V1
\r
24822 BFD05010 C878 SW V1, 96(SP)
\r
24823 BFD05012 0FDD MOVE S8, SP
\r
24824 196: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 6, TRUE);
\r
24825 BFD05014 EE0F LI A0, 15
\r
24826 BFD05016 EE86 LI A1, 6
\r
24827 BFD05018 EF01 LI A2, 1
\r
24828 BFD0501A 3A4077E8 JALS jtvic_dis_clr_source
\r
24829 BFD0501C 0C003A40 SH S2, 3072(ZERO)
\r
24830 BFD0501E 0C00 NOP
\r
24832 BFD05020 0FBE MOVE SP, S8
\r
24833 BFD05022 4859 LW V0, 100(SP)
\r
24834 BFD05024 3D7C0002 MTLO V0
\r
24835 BFD05026 48783D7C LH T3, 18552(GP)
\r
24836 BFD05028 4878 LW V1, 96(SP)
\r
24837 BFD0502A 2D7C0003 MTHI V1
\r
24838 BFD0502C 2D7C ANDI V0, A3, 0x40
\r
24839 BFD0502E 485C LW V0, 112(SP)
\r
24840 BFD05030 2D27 ANDI V0, V0, 0xF
\r
24841 BFD05032 001340A2 BNEZC V0, 0xBFD0505C
\r
24842 BFD05036 4BF7 LW RA, 92(SP)
\r
24843 BFD05038 4BD6 LW S8, 88(SP)
\r
24844 BFD0503A 4B35 LW T9, 84(SP)
\r
24845 BFD0503C 4B14 LW T8, 80(SP)
\r
24846 BFD0503E 49F3 LW T7, 76(SP)
\r
24847 BFD05040 49D2 LW T6, 72(SP)
\r
24848 BFD05042 49B1 LW T5, 68(SP)
\r
24849 BFD05044 4990 LW T4, 64(SP)
\r
24850 BFD05046 496F LW T3, 60(SP)
\r
24851 BFD05048 494E LW T2, 56(SP)
\r
24852 BFD0504A 492D LW T1, 52(SP)
\r
24853 BFD0504C 490C LW T0, 48(SP)
\r
24854 BFD0504E 48EB LW A3, 44(SP)
\r
24855 BFD05050 48CA LW A2, 40(SP)
\r
24856 BFD05052 48A9 LW A1, 36(SP)
\r
24857 BFD05054 4888 LW A0, 32(SP)
\r
24858 BFD05056 4867 LW V1, 28(SP)
\r
24859 BFD05058 4846 LW V0, 24(SP)
\r
24860 BFD0505A 4825 LW AT, 20(SP)
\r
24861 BFD0505C 477C0000 DI ZERO
\r
24862 BFD05060 18000000 SLL ZERO, ZERO, 3
\r
24863 BFD05062 4B5D1800 SB ZERO, 19293(ZERO)
\r
24864 BFD05064 4B5D LW K0, 116(SP)
\r
24865 BFD05066 4B7B LW K1, 108(SP)
\r
24866 BFD05068 02FC034E MTC0 K0, EPC
\r
24867 BFD0506C 4B5C LW K0, 112(SP)
\r
24868 BFD0506E 4C3D ADDIU SP, SP, 120
\r
24869 BFD05070 12FC034C MTC0 K0, SRSCtl
\r
24870 BFD05072 03BD12FC ADDI S7, GP, 957
\r
24871 BFD05074 F17C03BD WRPGPR SP, SP
\r
24872 BFD05076 036CF17C JALX 0xBDF00DB0
\r
24873 BFD05078 02FC036C MTC0 K1, Status
\r
24874 BFD0507A 000002FC SLL S7, GP, 0
\r
24875 BFD0507C F37C0000 ERET
\r
24876 BFD0507E 03BDF37C JALX 0xBDF00EF4
\r
24878 199: /* Sub-Week Alarm */
\r
24879 200: void __attribute__((weak, interrupt, nomips16))
\r
24880 201: girq23_b7(void)
\r
24882 BFD05080 E17C03BD RDPGPR SP, SP
\r
24883 BFD05084 00FC036E MFC0 K1, EPC
\r
24884 BFD05086 034C00FC INS A3, GP, 13, -12
\r
24885 BFD05088 10FC034C MFC0 K0, SRSCtl
\r
24886 BFD0508A 4FC510FC ADDI A3, GP, 20421
\r
24887 BFD0508C 4FC5 ADDIU SP, SP, -120
\r
24888 BFD0508E CB7D SW K1, 116(SP)
\r
24889 BFD05090 00FC036C MFC0 K1, Status
\r
24890 BFD05094 CB5C SW K0, 112(SP)
\r
24891 BFD05096 00FC034D MFC0 K0, Cause
\r
24892 BFD0509A CB7B SW K1, 108(SP)
\r
24893 BFD0509C 5040035A SRL K0, K0, 10
\r
24894 BFD0509E 037A5040 ORI V0, ZERO, 890
\r
24895 BFD050A0 7A8C037A INS K1, K0, 10, 6
\r
24896 BFD050A2 03607A8C ADDIUPC A1, 787296
\r
24897 BFD050A4 204C0360 INS K1, ZERO, 1, 4
\r
24898 BFD050A6 036C204C LWC2 V0, 876(T4)
\r
24899 BFD050A8 02FC036C MTC0 K1, Status
\r
24900 BFD050AC C867 SW V1, 28(SP)
\r
24901 BFD050AE C846 SW V0, 24(SP)
\r
24902 BFD050B0 487C LW V1, 112(SP)
\r
24903 BFD050B2 2DB7 ANDI V1, V1, 0xF
\r
24904 BFD050B4 001140A3 BNEZC V1, 0xBFD050DA
\r
24905 BFD050B8 CBF7 SW RA, 92(SP)
\r
24906 BFD050BA CBD6 SW S8, 88(SP)
\r
24907 BFD050BC CB35 SW T9, 84(SP)
\r
24908 BFD050BE CB14 SW T8, 80(SP)
\r
24909 BFD050C0 C9F3 SW T7, 76(SP)
\r
24910 BFD050C2 C9D2 SW T6, 72(SP)
\r
24911 BFD050C4 C9B1 SW T5, 68(SP)
\r
24912 BFD050C6 C990 SW T4, 64(SP)
\r
24913 BFD050C8 C96F SW T3, 60(SP)
\r
24914 BFD050CA C94E SW T2, 56(SP)
\r
24915 BFD050CC C92D SW T1, 52(SP)
\r
24916 BFD050CE C90C SW T0, 48(SP)
\r
24917 BFD050D0 C8EB SW A3, 44(SP)
\r
24918 BFD050D2 C8CA SW A2, 40(SP)
\r
24919 BFD050D4 C8A9 SW A1, 36(SP)
\r
24920 BFD050D6 C888 SW A0, 32(SP)
\r
24921 BFD050D8 C825 SW AT, 20(SP)
\r
24922 BFD050DA 4642 MFLO V0
\r
24923 BFD050DC C859 SW V0, 100(SP)
\r
24924 BFD050DE 4603 MFHI V1
\r
24925 BFD050E0 C878 SW V1, 96(SP)
\r
24926 BFD050E2 0FDD MOVE S8, SP
\r
24927 203: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 7, TRUE);
\r
24928 BFD050E4 EE0F LI A0, 15
\r
24929 BFD050E6 EE87 LI A1, 7
\r
24930 BFD050E8 EF01 LI A2, 1
\r
24931 BFD050EA 3A4077E8 JALS jtvic_dis_clr_source
\r
24932 BFD050EC 0C003A40 SH S2, 3072(ZERO)
\r
24933 BFD050EE 0C00 NOP
\r
24935 BFD050F0 0FBE MOVE SP, S8
\r
24936 BFD050F2 4859 LW V0, 100(SP)
\r
24937 BFD050F4 3D7C0002 MTLO V0
\r
24938 BFD050F6 48783D7C LH T3, 18552(GP)
\r
24939 BFD050F8 4878 LW V1, 96(SP)
\r
24940 BFD050FA 2D7C0003 MTHI V1
\r
24941 BFD050FC 2D7C ANDI V0, A3, 0x40
\r
24942 BFD050FE 485C LW V0, 112(SP)
\r
24943 BFD05100 2D27 ANDI V0, V0, 0xF
\r
24944 BFD05102 001340A2 BNEZC V0, 0xBFD0512C
\r
24945 BFD05106 4BF7 LW RA, 92(SP)
\r
24946 BFD05108 4BD6 LW S8, 88(SP)
\r
24947 BFD0510A 4B35 LW T9, 84(SP)
\r
24948 BFD0510C 4B14 LW T8, 80(SP)
\r
24949 BFD0510E 49F3 LW T7, 76(SP)
\r
24950 BFD05110 49D2 LW T6, 72(SP)
\r
24951 BFD05112 49B1 LW T5, 68(SP)
\r
24952 BFD05114 4990 LW T4, 64(SP)
\r
24953 BFD05116 496F LW T3, 60(SP)
\r
24954 BFD05118 494E LW T2, 56(SP)
\r
24955 BFD0511A 492D LW T1, 52(SP)
\r
24956 BFD0511C 490C LW T0, 48(SP)
\r
24957 BFD0511E 48EB LW A3, 44(SP)
\r
24958 BFD05120 48CA LW A2, 40(SP)
\r
24959 BFD05122 48A9 LW A1, 36(SP)
\r
24960 BFD05124 4888 LW A0, 32(SP)
\r
24961 BFD05126 4867 LW V1, 28(SP)
\r
24962 BFD05128 4846 LW V0, 24(SP)
\r
24963 BFD0512A 4825 LW AT, 20(SP)
\r
24964 BFD0512C 477C0000 DI ZERO
\r
24965 BFD05130 18000000 SLL ZERO, ZERO, 3
\r
24966 BFD05132 4B5D1800 SB ZERO, 19293(ZERO)
\r
24967 BFD05134 4B5D LW K0, 116(SP)
\r
24968 BFD05136 4B7B LW K1, 108(SP)
\r
24969 BFD05138 02FC034E MTC0 K0, EPC
\r
24970 BFD0513C 4B5C LW K0, 112(SP)
\r
24971 BFD0513E 4C3D ADDIU SP, SP, 120
\r
24972 BFD05140 12FC034C MTC0 K0, SRSCtl
\r
24973 BFD05142 03BD12FC ADDI S7, GP, 957
\r
24974 BFD05144 F17C03BD WRPGPR SP, SP
\r
24975 BFD05146 036CF17C JALX 0xBDF00DB0
\r
24976 BFD05148 02FC036C MTC0 K1, Status
\r
24977 BFD0514A 000002FC SLL S7, GP, 0
\r
24978 BFD0514C F37C0000 ERET
\r
24979 BFD0514E 03BDF37C JALX 0xBDF00EF4
\r
24981 206: /* Week Alarm One Second */
\r
24982 207: void __attribute__((weak, interrupt, nomips16))
\r
24983 208: girq23_b8(void)
\r
24985 BFD05150 E17C03BD RDPGPR SP, SP
\r
24986 BFD05154 00FC036E MFC0 K1, EPC
\r
24987 BFD05156 034C00FC INS A3, GP, 13, -12
\r
24988 BFD05158 10FC034C MFC0 K0, SRSCtl
\r
24989 BFD0515A 4FC510FC ADDI A3, GP, 20421
\r
24990 BFD0515C 4FC5 ADDIU SP, SP, -120
\r
24991 BFD0515E CB7D SW K1, 116(SP)
\r
24992 BFD05160 00FC036C MFC0 K1, Status
\r
24993 BFD05164 CB5C SW K0, 112(SP)
\r
24994 BFD05166 00FC034D MFC0 K0, Cause
\r
24995 BFD0516A CB7B SW K1, 108(SP)
\r
24996 BFD0516C 5040035A SRL K0, K0, 10
\r
24997 BFD0516E 037A5040 ORI V0, ZERO, 890
\r
24998 BFD05170 7A8C037A INS K1, K0, 10, 6
\r
24999 BFD05172 03607A8C ADDIUPC A1, 787296
\r
25000 BFD05174 204C0360 INS K1, ZERO, 1, 4
\r
25001 BFD05176 036C204C LWC2 V0, 876(T4)
\r
25002 BFD05178 02FC036C MTC0 K1, Status
\r
25003 BFD0517C C867 SW V1, 28(SP)
\r
25004 BFD0517E C846 SW V0, 24(SP)
\r
25005 BFD05180 487C LW V1, 112(SP)
\r
25006 BFD05182 2DB7 ANDI V1, V1, 0xF
\r
25007 BFD05184 001140A3 BNEZC V1, 0xBFD051AA
\r
25008 BFD05188 CBF7 SW RA, 92(SP)
\r
25009 BFD0518A CBD6 SW S8, 88(SP)
\r
25010 BFD0518C CB35 SW T9, 84(SP)
\r
25011 BFD0518E CB14 SW T8, 80(SP)
\r
25012 BFD05190 C9F3 SW T7, 76(SP)
\r
25013 BFD05192 C9D2 SW T6, 72(SP)
\r
25014 BFD05194 C9B1 SW T5, 68(SP)
\r
25015 BFD05196 C990 SW T4, 64(SP)
\r
25016 BFD05198 C96F SW T3, 60(SP)
\r
25017 BFD0519A C94E SW T2, 56(SP)
\r
25018 BFD0519C C92D SW T1, 52(SP)
\r
25019 BFD0519E C90C SW T0, 48(SP)
\r
25020 BFD051A0 C8EB SW A3, 44(SP)
\r
25021 BFD051A2 C8CA SW A2, 40(SP)
\r
25022 BFD051A4 C8A9 SW A1, 36(SP)
\r
25023 BFD051A6 C888 SW A0, 32(SP)
\r
25024 BFD051A8 C825 SW AT, 20(SP)
\r
25025 BFD051AA 4642 MFLO V0
\r
25026 BFD051AC C859 SW V0, 100(SP)
\r
25027 BFD051AE 4603 MFHI V1
\r
25028 BFD051B0 C878 SW V1, 96(SP)
\r
25029 BFD051B2 0FDD MOVE S8, SP
\r
25030 210: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 8, TRUE);
\r
25031 BFD051B4 EE0F LI A0, 15
\r
25032 BFD051B6 EE88 LI A1, 8
\r
25033 BFD051B8 EF01 LI A2, 1
\r
25034 BFD051BA 3A4077E8 JALS jtvic_dis_clr_source
\r
25035 BFD051BC 0C003A40 SH S2, 3072(ZERO)
\r
25036 BFD051BE 0C00 NOP
\r
25038 BFD051C0 0FBE MOVE SP, S8
\r
25039 BFD051C2 4859 LW V0, 100(SP)
\r
25040 BFD051C4 3D7C0002 MTLO V0
\r
25041 BFD051C6 48783D7C LH T3, 18552(GP)
\r
25042 BFD051C8 4878 LW V1, 96(SP)
\r
25043 BFD051CA 2D7C0003 MTHI V1
\r
25044 BFD051CC 2D7C ANDI V0, A3, 0x40
\r
25045 BFD051CE 485C LW V0, 112(SP)
\r
25046 BFD051D0 2D27 ANDI V0, V0, 0xF
\r
25047 BFD051D2 001340A2 BNEZC V0, 0xBFD051FC
\r
25048 BFD051D6 4BF7 LW RA, 92(SP)
\r
25049 BFD051D8 4BD6 LW S8, 88(SP)
\r
25050 BFD051DA 4B35 LW T9, 84(SP)
\r
25051 BFD051DC 4B14 LW T8, 80(SP)
\r
25052 BFD051DE 49F3 LW T7, 76(SP)
\r
25053 BFD051E0 49D2 LW T6, 72(SP)
\r
25054 BFD051E2 49B1 LW T5, 68(SP)
\r
25055 BFD051E4 4990 LW T4, 64(SP)
\r
25056 BFD051E6 496F LW T3, 60(SP)
\r
25057 BFD051E8 494E LW T2, 56(SP)
\r
25058 BFD051EA 492D LW T1, 52(SP)
\r
25059 BFD051EC 490C LW T0, 48(SP)
\r
25060 BFD051EE 48EB LW A3, 44(SP)
\r
25061 BFD051F0 48CA LW A2, 40(SP)
\r
25062 BFD051F2 48A9 LW A1, 36(SP)
\r
25063 BFD051F4 4888 LW A0, 32(SP)
\r
25064 BFD051F6 4867 LW V1, 28(SP)
\r
25065 BFD051F8 4846 LW V0, 24(SP)
\r
25066 BFD051FA 4825 LW AT, 20(SP)
\r
25067 BFD051FC 477C0000 DI ZERO
\r
25068 BFD05200 18000000 SLL ZERO, ZERO, 3
\r
25069 BFD05202 4B5D1800 SB ZERO, 19293(ZERO)
\r
25070 BFD05204 4B5D LW K0, 116(SP)
\r
25071 BFD05206 4B7B LW K1, 108(SP)
\r
25072 BFD05208 02FC034E MTC0 K0, EPC
\r
25073 BFD0520C 4B5C LW K0, 112(SP)
\r
25074 BFD0520E 4C3D ADDIU SP, SP, 120
\r
25075 BFD05210 12FC034C MTC0 K0, SRSCtl
\r
25076 BFD05212 03BD12FC ADDI S7, GP, 957
\r
25077 BFD05214 F17C03BD WRPGPR SP, SP
\r
25078 BFD05216 036CF17C JALX 0xBDF00DB0
\r
25079 BFD05218 02FC036C MTC0 K1, Status
\r
25080 BFD0521A 000002FC SLL S7, GP, 0
\r
25081 BFD0521C F37C0000 ERET
\r
25082 BFD0521E 03BDF37C JALX 0xBDF00EF4
\r
25084 213: /* Week Alarm Sub Second */
\r
25085 214: void __attribute__((weak, interrupt, nomips16))
\r
25086 215: girq23_b9(void)
\r
25088 BFD05220 E17C03BD RDPGPR SP, SP
\r
25089 BFD05224 00FC036E MFC0 K1, EPC
\r
25090 BFD05226 034C00FC INS A3, GP, 13, -12
\r
25091 BFD05228 10FC034C MFC0 K0, SRSCtl
\r
25092 BFD0522A 4FC510FC ADDI A3, GP, 20421
\r
25093 BFD0522C 4FC5 ADDIU SP, SP, -120
\r
25094 BFD0522E CB7D SW K1, 116(SP)
\r
25095 BFD05230 00FC036C MFC0 K1, Status
\r
25096 BFD05234 CB5C SW K0, 112(SP)
\r
25097 BFD05236 00FC034D MFC0 K0, Cause
\r
25098 BFD0523A CB7B SW K1, 108(SP)
\r
25099 BFD0523C 5040035A SRL K0, K0, 10
\r
25100 BFD0523E 037A5040 ORI V0, ZERO, 890
\r
25101 BFD05240 7A8C037A INS K1, K0, 10, 6
\r
25102 BFD05242 03607A8C ADDIUPC A1, 787296
\r
25103 BFD05244 204C0360 INS K1, ZERO, 1, 4
\r
25104 BFD05246 036C204C LWC2 V0, 876(T4)
\r
25105 BFD05248 02FC036C MTC0 K1, Status
\r
25106 BFD0524C C867 SW V1, 28(SP)
\r
25107 BFD0524E C846 SW V0, 24(SP)
\r
25108 BFD05250 487C LW V1, 112(SP)
\r
25109 BFD05252 2DB7 ANDI V1, V1, 0xF
\r
25110 BFD05254 001140A3 BNEZC V1, 0xBFD0527A
\r
25111 BFD05258 CBF7 SW RA, 92(SP)
\r
25112 BFD0525A CBD6 SW S8, 88(SP)
\r
25113 BFD0525C CB35 SW T9, 84(SP)
\r
25114 BFD0525E CB14 SW T8, 80(SP)
\r
25115 BFD05260 C9F3 SW T7, 76(SP)
\r
25116 BFD05262 C9D2 SW T6, 72(SP)
\r
25117 BFD05264 C9B1 SW T5, 68(SP)
\r
25118 BFD05266 C990 SW T4, 64(SP)
\r
25119 BFD05268 C96F SW T3, 60(SP)
\r
25120 BFD0526A C94E SW T2, 56(SP)
\r
25121 BFD0526C C92D SW T1, 52(SP)
\r
25122 BFD0526E C90C SW T0, 48(SP)
\r
25123 BFD05270 C8EB SW A3, 44(SP)
\r
25124 BFD05272 C8CA SW A2, 40(SP)
\r
25125 BFD05274 C8A9 SW A1, 36(SP)
\r
25126 BFD05276 C888 SW A0, 32(SP)
\r
25127 BFD05278 C825 SW AT, 20(SP)
\r
25128 BFD0527A 4642 MFLO V0
\r
25129 BFD0527C C859 SW V0, 100(SP)
\r
25130 BFD0527E 4603 MFHI V1
\r
25131 BFD05280 C878 SW V1, 96(SP)
\r
25132 BFD05282 0FDD MOVE S8, SP
\r
25133 217: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 9, TRUE);
\r
25134 BFD05284 EE0F LI A0, 15
\r
25135 BFD05286 EE89 LI A1, 9
\r
25136 BFD05288 EF01 LI A2, 1
\r
25137 BFD0528A 3A4077E8 JALS jtvic_dis_clr_source
\r
25138 BFD0528C 0C003A40 SH S2, 3072(ZERO)
\r
25139 BFD0528E 0C00 NOP
\r
25141 BFD05290 0FBE MOVE SP, S8
\r
25142 BFD05292 4859 LW V0, 100(SP)
\r
25143 BFD05294 3D7C0002 MTLO V0
\r
25144 BFD05296 48783D7C LH T3, 18552(GP)
\r
25145 BFD05298 4878 LW V1, 96(SP)
\r
25146 BFD0529A 2D7C0003 MTHI V1
\r
25147 BFD0529C 2D7C ANDI V0, A3, 0x40
\r
25148 BFD0529E 485C LW V0, 112(SP)
\r
25149 BFD052A0 2D27 ANDI V0, V0, 0xF
\r
25150 BFD052A2 001340A2 BNEZC V0, 0xBFD052CC
\r
25151 BFD052A6 4BF7 LW RA, 92(SP)
\r
25152 BFD052A8 4BD6 LW S8, 88(SP)
\r
25153 BFD052AA 4B35 LW T9, 84(SP)
\r
25154 BFD052AC 4B14 LW T8, 80(SP)
\r
25155 BFD052AE 49F3 LW T7, 76(SP)
\r
25156 BFD052B0 49D2 LW T6, 72(SP)
\r
25157 BFD052B2 49B1 LW T5, 68(SP)
\r
25158 BFD052B4 4990 LW T4, 64(SP)
\r
25159 BFD052B6 496F LW T3, 60(SP)
\r
25160 BFD052B8 494E LW T2, 56(SP)
\r
25161 BFD052BA 492D LW T1, 52(SP)
\r
25162 BFD052BC 490C LW T0, 48(SP)
\r
25163 BFD052BE 48EB LW A3, 44(SP)
\r
25164 BFD052C0 48CA LW A2, 40(SP)
\r
25165 BFD052C2 48A9 LW A1, 36(SP)
\r
25166 BFD052C4 4888 LW A0, 32(SP)
\r
25167 BFD052C6 4867 LW V1, 28(SP)
\r
25168 BFD052C8 4846 LW V0, 24(SP)
\r
25169 BFD052CA 4825 LW AT, 20(SP)
\r
25170 BFD052CC 477C0000 DI ZERO
\r
25171 BFD052D0 18000000 SLL ZERO, ZERO, 3
\r
25172 BFD052D2 4B5D1800 SB ZERO, 19293(ZERO)
\r
25173 BFD052D4 4B5D LW K0, 116(SP)
\r
25174 BFD052D6 4B7B LW K1, 108(SP)
\r
25175 BFD052D8 02FC034E MTC0 K0, EPC
\r
25176 BFD052DC 4B5C LW K0, 112(SP)
\r
25177 BFD052DE 4C3D ADDIU SP, SP, 120
\r
25178 BFD052E0 12FC034C MTC0 K0, SRSCtl
\r
25179 BFD052E2 03BD12FC ADDI S7, GP, 957
\r
25180 BFD052E4 F17C03BD WRPGPR SP, SP
\r
25181 BFD052E6 036CF17C JALX 0xBDF00DB0
\r
25182 BFD052E8 02FC036C MTC0 K1, Status
\r
25183 BFD052EA 000002FC SLL S7, GP, 0
\r
25184 BFD052EC F37C0000 ERET
\r
25185 BFD052EE 03BDF37C JALX 0xBDF00EF4
\r
25187 220: /* Week Alarm System Power Present Pin */
\r
25188 221: void __attribute__((weak, interrupt, nomips16))
\r
25189 222: girq23_b10(void)
\r
25191 BFD052F0 E17C03BD RDPGPR SP, SP
\r
25192 BFD052F4 00FC036E MFC0 K1, EPC
\r
25193 BFD052F6 034C00FC INS A3, GP, 13, -12
\r
25194 BFD052F8 10FC034C MFC0 K0, SRSCtl
\r
25195 BFD052FA 4FC510FC ADDI A3, GP, 20421
\r
25196 BFD052FC 4FC5 ADDIU SP, SP, -120
\r
25197 BFD052FE CB7D SW K1, 116(SP)
\r
25198 BFD05300 00FC036C MFC0 K1, Status
\r
25199 BFD05304 CB5C SW K0, 112(SP)
\r
25200 BFD05306 00FC034D MFC0 K0, Cause
\r
25201 BFD0530A CB7B SW K1, 108(SP)
\r
25202 BFD0530C 5040035A SRL K0, K0, 10
\r
25203 BFD0530E 037A5040 ORI V0, ZERO, 890
\r
25204 BFD05310 7A8C037A INS K1, K0, 10, 6
\r
25205 BFD05312 03607A8C ADDIUPC A1, 787296
\r
25206 BFD05314 204C0360 INS K1, ZERO, 1, 4
\r
25207 BFD05316 036C204C LWC2 V0, 876(T4)
\r
25208 BFD05318 02FC036C MTC0 K1, Status
\r
25209 BFD0531C C867 SW V1, 28(SP)
\r
25210 BFD0531E C846 SW V0, 24(SP)
\r
25211 BFD05320 487C LW V1, 112(SP)
\r
25212 BFD05322 2DB7 ANDI V1, V1, 0xF
\r
25213 BFD05324 001140A3 BNEZC V1, 0xBFD0534A
\r
25214 BFD05328 CBF7 SW RA, 92(SP)
\r
25215 BFD0532A CBD6 SW S8, 88(SP)
\r
25216 BFD0532C CB35 SW T9, 84(SP)
\r
25217 BFD0532E CB14 SW T8, 80(SP)
\r
25218 BFD05330 C9F3 SW T7, 76(SP)
\r
25219 BFD05332 C9D2 SW T6, 72(SP)
\r
25220 BFD05334 C9B1 SW T5, 68(SP)
\r
25221 BFD05336 C990 SW T4, 64(SP)
\r
25222 BFD05338 C96F SW T3, 60(SP)
\r
25223 BFD0533A C94E SW T2, 56(SP)
\r
25224 BFD0533C C92D SW T1, 52(SP)
\r
25225 BFD0533E C90C SW T0, 48(SP)
\r
25226 BFD05340 C8EB SW A3, 44(SP)
\r
25227 BFD05342 C8CA SW A2, 40(SP)
\r
25228 BFD05344 C8A9 SW A1, 36(SP)
\r
25229 BFD05346 C888 SW A0, 32(SP)
\r
25230 BFD05348 C825 SW AT, 20(SP)
\r
25231 BFD0534A 4642 MFLO V0
\r
25232 BFD0534C C859 SW V0, 100(SP)
\r
25233 BFD0534E 4603 MFHI V1
\r
25234 BFD05350 C878 SW V1, 96(SP)
\r
25235 BFD05352 0FDD MOVE S8, SP
\r
25236 224: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 10, TRUE);
\r
25237 BFD05354 EE0F LI A0, 15
\r
25238 BFD05356 EE8A LI A1, 10
\r
25239 BFD05358 EF01 LI A2, 1
\r
25240 BFD0535A 3A4077E8 JALS jtvic_dis_clr_source
\r
25241 BFD0535C 0C003A40 SH S2, 3072(ZERO)
\r
25242 BFD0535E 0C00 NOP
\r
25244 BFD05360 0FBE MOVE SP, S8
\r
25245 BFD05362 4859 LW V0, 100(SP)
\r
25246 BFD05364 3D7C0002 MTLO V0
\r
25247 BFD05366 48783D7C LH T3, 18552(GP)
\r
25248 BFD05368 4878 LW V1, 96(SP)
\r
25249 BFD0536A 2D7C0003 MTHI V1
\r
25250 BFD0536C 2D7C ANDI V0, A3, 0x40
\r
25251 BFD0536E 485C LW V0, 112(SP)
\r
25252 BFD05370 2D27 ANDI V0, V0, 0xF
\r
25253 BFD05372 001340A2 BNEZC V0, 0xBFD0539C
\r
25254 BFD05376 4BF7 LW RA, 92(SP)
\r
25255 BFD05378 4BD6 LW S8, 88(SP)
\r
25256 BFD0537A 4B35 LW T9, 84(SP)
\r
25257 BFD0537C 4B14 LW T8, 80(SP)
\r
25258 BFD0537E 49F3 LW T7, 76(SP)
\r
25259 BFD05380 49D2 LW T6, 72(SP)
\r
25260 BFD05382 49B1 LW T5, 68(SP)
\r
25261 BFD05384 4990 LW T4, 64(SP)
\r
25262 BFD05386 496F LW T3, 60(SP)
\r
25263 BFD05388 494E LW T2, 56(SP)
\r
25264 BFD0538A 492D LW T1, 52(SP)
\r
25265 BFD0538C 490C LW T0, 48(SP)
\r
25266 BFD0538E 48EB LW A3, 44(SP)
\r
25267 BFD05390 48CA LW A2, 40(SP)
\r
25268 BFD05392 48A9 LW A1, 36(SP)
\r
25269 BFD05394 4888 LW A0, 32(SP)
\r
25270 BFD05396 4867 LW V1, 28(SP)
\r
25271 BFD05398 4846 LW V0, 24(SP)
\r
25272 BFD0539A 4825 LW AT, 20(SP)
\r
25273 BFD0539C 477C0000 DI ZERO
\r
25274 BFD053A0 18000000 SLL ZERO, ZERO, 3
\r
25275 BFD053A2 4B5D1800 SB ZERO, 19293(ZERO)
\r
25276 BFD053A4 4B5D LW K0, 116(SP)
\r
25277 BFD053A6 4B7B LW K1, 108(SP)
\r
25278 BFD053A8 02FC034E MTC0 K0, EPC
\r
25279 BFD053AC 4B5C LW K0, 112(SP)
\r
25280 BFD053AE 4C3D ADDIU SP, SP, 120
\r
25281 BFD053B0 12FC034C MTC0 K0, SRSCtl
\r
25282 BFD053B2 03BD12FC ADDI S7, GP, 957
\r
25283 BFD053B4 F17C03BD WRPGPR SP, SP
\r
25284 BFD053B6 036CF17C JALX 0xBDF00DB0
\r
25285 BFD053B8 02FC036C MTC0 K1, Status
\r
25286 BFD053BA 000002FC SLL S7, GP, 0
\r
25287 BFD053BC F37C0000 ERET
\r
25288 BFD053BE 03BDF37C JALX 0xBDF00EF4
\r
25290 227: /* VCI OVRD Input */
\r
25291 228: void __attribute__((weak, interrupt, nomips16))
\r
25292 229: girq23_b11(void)
\r
25294 BFD053C0 E17C03BD RDPGPR SP, SP
\r
25295 BFD053C4 00FC036E MFC0 K1, EPC
\r
25296 BFD053C6 034C00FC INS A3, GP, 13, -12
\r
25297 BFD053C8 10FC034C MFC0 K0, SRSCtl
\r
25298 BFD053CA 4FC510FC ADDI A3, GP, 20421
\r
25299 BFD053CC 4FC5 ADDIU SP, SP, -120
\r
25300 BFD053CE CB7D SW K1, 116(SP)
\r
25301 BFD053D0 00FC036C MFC0 K1, Status
\r
25302 BFD053D4 CB5C SW K0, 112(SP)
\r
25303 BFD053D6 00FC034D MFC0 K0, Cause
\r
25304 BFD053DA CB7B SW K1, 108(SP)
\r
25305 BFD053DC 5040035A SRL K0, K0, 10
\r
25306 BFD053DE 037A5040 ORI V0, ZERO, 890
\r
25307 BFD053E0 7A8C037A INS K1, K0, 10, 6
\r
25308 BFD053E2 03607A8C ADDIUPC A1, 787296
\r
25309 BFD053E4 204C0360 INS K1, ZERO, 1, 4
\r
25310 BFD053E6 036C204C LWC2 V0, 876(T4)
\r
25311 BFD053E8 02FC036C MTC0 K1, Status
\r
25312 BFD053EC C867 SW V1, 28(SP)
\r
25313 BFD053EE C846 SW V0, 24(SP)
\r
25314 BFD053F0 487C LW V1, 112(SP)
\r
25315 BFD053F2 2DB7 ANDI V1, V1, 0xF
\r
25316 BFD053F4 001140A3 BNEZC V1, 0xBFD0541A
\r
25317 BFD053F8 CBF7 SW RA, 92(SP)
\r
25318 BFD053FA CBD6 SW S8, 88(SP)
\r
25319 BFD053FC CB35 SW T9, 84(SP)
\r
25320 BFD053FE CB14 SW T8, 80(SP)
\r
25321 BFD05400 C9F3 SW T7, 76(SP)
\r
25322 BFD05402 C9D2 SW T6, 72(SP)
\r
25323 BFD05404 C9B1 SW T5, 68(SP)
\r
25324 BFD05406 C990 SW T4, 64(SP)
\r
25325 BFD05408 C96F SW T3, 60(SP)
\r
25326 BFD0540A C94E SW T2, 56(SP)
\r
25327 BFD0540C C92D SW T1, 52(SP)
\r
25328 BFD0540E C90C SW T0, 48(SP)
\r
25329 BFD05410 C8EB SW A3, 44(SP)
\r
25330 BFD05412 C8CA SW A2, 40(SP)
\r
25331 BFD05414 C8A9 SW A1, 36(SP)
\r
25332 BFD05416 C888 SW A0, 32(SP)
\r
25333 BFD05418 C825 SW AT, 20(SP)
\r
25334 BFD0541A 4642 MFLO V0
\r
25335 BFD0541C C859 SW V0, 100(SP)
\r
25336 BFD0541E 4603 MFHI V1
\r
25337 BFD05420 C878 SW V1, 96(SP)
\r
25338 BFD05422 0FDD MOVE S8, SP
\r
25339 231: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 11, TRUE);
\r
25340 BFD05424 EE0F LI A0, 15
\r
25341 BFD05426 EE8B LI A1, 11
\r
25342 BFD05428 EF01 LI A2, 1
\r
25343 BFD0542A 3A4077E8 JALS jtvic_dis_clr_source
\r
25344 BFD0542C 0C003A40 SH S2, 3072(ZERO)
\r
25345 BFD0542E 0C00 NOP
\r
25347 BFD05430 0FBE MOVE SP, S8
\r
25348 BFD05432 4859 LW V0, 100(SP)
\r
25349 BFD05434 3D7C0002 MTLO V0
\r
25350 BFD05436 48783D7C LH T3, 18552(GP)
\r
25351 BFD05438 4878 LW V1, 96(SP)
\r
25352 BFD0543A 2D7C0003 MTHI V1
\r
25353 BFD0543C 2D7C ANDI V0, A3, 0x40
\r
25354 BFD0543E 485C LW V0, 112(SP)
\r
25355 BFD05440 2D27 ANDI V0, V0, 0xF
\r
25356 BFD05442 001340A2 BNEZC V0, 0xBFD0546C
\r
25357 BFD05446 4BF7 LW RA, 92(SP)
\r
25358 BFD05448 4BD6 LW S8, 88(SP)
\r
25359 BFD0544A 4B35 LW T9, 84(SP)
\r
25360 BFD0544C 4B14 LW T8, 80(SP)
\r
25361 BFD0544E 49F3 LW T7, 76(SP)
\r
25362 BFD05450 49D2 LW T6, 72(SP)
\r
25363 BFD05452 49B1 LW T5, 68(SP)
\r
25364 BFD05454 4990 LW T4, 64(SP)
\r
25365 BFD05456 496F LW T3, 60(SP)
\r
25366 BFD05458 494E LW T2, 56(SP)
\r
25367 BFD0545A 492D LW T1, 52(SP)
\r
25368 BFD0545C 490C LW T0, 48(SP)
\r
25369 BFD0545E 48EB LW A3, 44(SP)
\r
25370 BFD05460 48CA LW A2, 40(SP)
\r
25371 BFD05462 48A9 LW A1, 36(SP)
\r
25372 BFD05464 4888 LW A0, 32(SP)
\r
25373 BFD05466 4867 LW V1, 28(SP)
\r
25374 BFD05468 4846 LW V0, 24(SP)
\r
25375 BFD0546A 4825 LW AT, 20(SP)
\r
25376 BFD0546C 477C0000 DI ZERO
\r
25377 BFD05470 18000000 SLL ZERO, ZERO, 3
\r
25378 BFD05472 4B5D1800 SB ZERO, 19293(ZERO)
\r
25379 BFD05474 4B5D LW K0, 116(SP)
\r
25380 BFD05476 4B7B LW K1, 108(SP)
\r
25381 BFD05478 02FC034E MTC0 K0, EPC
\r
25382 BFD0547C 4B5C LW K0, 112(SP)
\r
25383 BFD0547E 4C3D ADDIU SP, SP, 120
\r
25384 BFD05480 12FC034C MTC0 K0, SRSCtl
\r
25385 BFD05482 03BD12FC ADDI S7, GP, 957
\r
25386 BFD05484 F17C03BD WRPGPR SP, SP
\r
25387 BFD05486 036CF17C JALX 0xBDF00DB0
\r
25388 BFD05488 02FC036C MTC0 K1, Status
\r
25389 BFD0548A 000002FC SLL S7, GP, 0
\r
25390 BFD0548C F37C0000 ERET
\r
25391 BFD0548E 03BDF37C JALX 0xBDF00EF4
\r
25393 234: /* VCI IN0 */
\r
25394 235: void __attribute__((weak, interrupt, nomips16))
\r
25395 236: girq23_b12(void)
\r
25397 BFD05490 E17C03BD RDPGPR SP, SP
\r
25398 BFD05494 00FC036E MFC0 K1, EPC
\r
25399 BFD05496 034C00FC INS A3, GP, 13, -12
\r
25400 BFD05498 10FC034C MFC0 K0, SRSCtl
\r
25401 BFD0549A 4FC510FC ADDI A3, GP, 20421
\r
25402 BFD0549C 4FC5 ADDIU SP, SP, -120
\r
25403 BFD0549E CB7D SW K1, 116(SP)
\r
25404 BFD054A0 00FC036C MFC0 K1, Status
\r
25405 BFD054A4 CB5C SW K0, 112(SP)
\r
25406 BFD054A6 00FC034D MFC0 K0, Cause
\r
25407 BFD054AA CB7B SW K1, 108(SP)
\r
25408 BFD054AC 5040035A SRL K0, K0, 10
\r
25409 BFD054AE 037A5040 ORI V0, ZERO, 890
\r
25410 BFD054B0 7A8C037A INS K1, K0, 10, 6
\r
25411 BFD054B2 03607A8C ADDIUPC A1, 787296
\r
25412 BFD054B4 204C0360 INS K1, ZERO, 1, 4
\r
25413 BFD054B6 036C204C LWC2 V0, 876(T4)
\r
25414 BFD054B8 02FC036C MTC0 K1, Status
\r
25415 BFD054BC C867 SW V1, 28(SP)
\r
25416 BFD054BE C846 SW V0, 24(SP)
\r
25417 BFD054C0 487C LW V1, 112(SP)
\r
25418 BFD054C2 2DB7 ANDI V1, V1, 0xF
\r
25419 BFD054C4 001140A3 BNEZC V1, 0xBFD054EA
\r
25420 BFD054C8 CBF7 SW RA, 92(SP)
\r
25421 BFD054CA CBD6 SW S8, 88(SP)
\r
25422 BFD054CC CB35 SW T9, 84(SP)
\r
25423 BFD054CE CB14 SW T8, 80(SP)
\r
25424 BFD054D0 C9F3 SW T7, 76(SP)
\r
25425 BFD054D2 C9D2 SW T6, 72(SP)
\r
25426 BFD054D4 C9B1 SW T5, 68(SP)
\r
25427 BFD054D6 C990 SW T4, 64(SP)
\r
25428 BFD054D8 C96F SW T3, 60(SP)
\r
25429 BFD054DA C94E SW T2, 56(SP)
\r
25430 BFD054DC C92D SW T1, 52(SP)
\r
25431 BFD054DE C90C SW T0, 48(SP)
\r
25432 BFD054E0 C8EB SW A3, 44(SP)
\r
25433 BFD054E2 C8CA SW A2, 40(SP)
\r
25434 BFD054E4 C8A9 SW A1, 36(SP)
\r
25435 BFD054E6 C888 SW A0, 32(SP)
\r
25436 BFD054E8 C825 SW AT, 20(SP)
\r
25437 BFD054EA 4642 MFLO V0
\r
25438 BFD054EC C859 SW V0, 100(SP)
\r
25439 BFD054EE 4603 MFHI V1
\r
25440 BFD054F0 C878 SW V1, 96(SP)
\r
25441 BFD054F2 0FDD MOVE S8, SP
\r
25442 238: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 12, TRUE);
\r
25443 BFD054F4 EE0F LI A0, 15
\r
25444 BFD054F6 EE8C LI A1, 12
\r
25445 BFD054F8 EF01 LI A2, 1
\r
25446 BFD054FA 3A4077E8 JALS jtvic_dis_clr_source
\r
25447 BFD054FC 0C003A40 SH S2, 3072(ZERO)
\r
25448 BFD054FE 0C00 NOP
\r
25450 BFD05500 0FBE MOVE SP, S8
\r
25451 BFD05502 4859 LW V0, 100(SP)
\r
25452 BFD05504 3D7C0002 MTLO V0
\r
25453 BFD05506 48783D7C LH T3, 18552(GP)
\r
25454 BFD05508 4878 LW V1, 96(SP)
\r
25455 BFD0550A 2D7C0003 MTHI V1
\r
25456 BFD0550C 2D7C ANDI V0, A3, 0x40
\r
25457 BFD0550E 485C LW V0, 112(SP)
\r
25458 BFD05510 2D27 ANDI V0, V0, 0xF
\r
25459 BFD05512 001340A2 BNEZC V0, 0xBFD0553C
\r
25460 BFD05516 4BF7 LW RA, 92(SP)
\r
25461 BFD05518 4BD6 LW S8, 88(SP)
\r
25462 BFD0551A 4B35 LW T9, 84(SP)
\r
25463 BFD0551C 4B14 LW T8, 80(SP)
\r
25464 BFD0551E 49F3 LW T7, 76(SP)
\r
25465 BFD05520 49D2 LW T6, 72(SP)
\r
25466 BFD05522 49B1 LW T5, 68(SP)
\r
25467 BFD05524 4990 LW T4, 64(SP)
\r
25468 BFD05526 496F LW T3, 60(SP)
\r
25469 BFD05528 494E LW T2, 56(SP)
\r
25470 BFD0552A 492D LW T1, 52(SP)
\r
25471 BFD0552C 490C LW T0, 48(SP)
\r
25472 BFD0552E 48EB LW A3, 44(SP)
\r
25473 BFD05530 48CA LW A2, 40(SP)
\r
25474 BFD05532 48A9 LW A1, 36(SP)
\r
25475 BFD05534 4888 LW A0, 32(SP)
\r
25476 BFD05536 4867 LW V1, 28(SP)
\r
25477 BFD05538 4846 LW V0, 24(SP)
\r
25478 BFD0553A 4825 LW AT, 20(SP)
\r
25479 BFD0553C 477C0000 DI ZERO
\r
25480 BFD05540 18000000 SLL ZERO, ZERO, 3
\r
25481 BFD05542 4B5D1800 SB ZERO, 19293(ZERO)
\r
25482 BFD05544 4B5D LW K0, 116(SP)
\r
25483 BFD05546 4B7B LW K1, 108(SP)
\r
25484 BFD05548 02FC034E MTC0 K0, EPC
\r
25485 BFD0554C 4B5C LW K0, 112(SP)
\r
25486 BFD0554E 4C3D ADDIU SP, SP, 120
\r
25487 BFD05550 12FC034C MTC0 K0, SRSCtl
\r
25488 BFD05552 03BD12FC ADDI S7, GP, 957
\r
25489 BFD05554 F17C03BD WRPGPR SP, SP
\r
25490 BFD05556 036CF17C JALX 0xBDF00DB0
\r
25491 BFD05558 02FC036C MTC0 K1, Status
\r
25492 BFD0555A 000002FC SLL S7, GP, 0
\r
25493 BFD0555C F37C0000 ERET
\r
25494 BFD0555E 03BDF37C JALX 0xBDF00EF4
\r
25496 241: /* VCI IN1 */
\r
25497 242: void __attribute__((weak, interrupt, nomips16))
\r
25498 243: girq23_b13(void)
\r
25500 BFD05560 E17C03BD RDPGPR SP, SP
\r
25501 BFD05564 00FC036E MFC0 K1, EPC
\r
25502 BFD05566 034C00FC INS A3, GP, 13, -12
\r
25503 BFD05568 10FC034C MFC0 K0, SRSCtl
\r
25504 BFD0556A 4FC510FC ADDI A3, GP, 20421
\r
25505 BFD0556C 4FC5 ADDIU SP, SP, -120
\r
25506 BFD0556E CB7D SW K1, 116(SP)
\r
25507 BFD05570 00FC036C MFC0 K1, Status
\r
25508 BFD05574 CB5C SW K0, 112(SP)
\r
25509 BFD05576 00FC034D MFC0 K0, Cause
\r
25510 BFD0557A CB7B SW K1, 108(SP)
\r
25511 BFD0557C 5040035A SRL K0, K0, 10
\r
25512 BFD0557E 037A5040 ORI V0, ZERO, 890
\r
25513 BFD05580 7A8C037A INS K1, K0, 10, 6
\r
25514 BFD05582 03607A8C ADDIUPC A1, 787296
\r
25515 BFD05584 204C0360 INS K1, ZERO, 1, 4
\r
25516 BFD05586 036C204C LWC2 V0, 876(T4)
\r
25517 BFD05588 02FC036C MTC0 K1, Status
\r
25518 BFD0558C C867 SW V1, 28(SP)
\r
25519 BFD0558E C846 SW V0, 24(SP)
\r
25520 BFD05590 487C LW V1, 112(SP)
\r
25521 BFD05592 2DB7 ANDI V1, V1, 0xF
\r
25522 BFD05594 001140A3 BNEZC V1, 0xBFD055BA
\r
25523 BFD05598 CBF7 SW RA, 92(SP)
\r
25524 BFD0559A CBD6 SW S8, 88(SP)
\r
25525 BFD0559C CB35 SW T9, 84(SP)
\r
25526 BFD0559E CB14 SW T8, 80(SP)
\r
25527 BFD055A0 C9F3 SW T7, 76(SP)
\r
25528 BFD055A2 C9D2 SW T6, 72(SP)
\r
25529 BFD055A4 C9B1 SW T5, 68(SP)
\r
25530 BFD055A6 C990 SW T4, 64(SP)
\r
25531 BFD055A8 C96F SW T3, 60(SP)
\r
25532 BFD055AA C94E SW T2, 56(SP)
\r
25533 BFD055AC C92D SW T1, 52(SP)
\r
25534 BFD055AE C90C SW T0, 48(SP)
\r
25535 BFD055B0 C8EB SW A3, 44(SP)
\r
25536 BFD055B2 C8CA SW A2, 40(SP)
\r
25537 BFD055B4 C8A9 SW A1, 36(SP)
\r
25538 BFD055B6 C888 SW A0, 32(SP)
\r
25539 BFD055B8 C825 SW AT, 20(SP)
\r
25540 BFD055BA 4642 MFLO V0
\r
25541 BFD055BC C859 SW V0, 100(SP)
\r
25542 BFD055BE 4603 MFHI V1
\r
25543 BFD055C0 C878 SW V1, 96(SP)
\r
25544 BFD055C2 0FDD MOVE S8, SP
\r
25545 245: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 13, TRUE);
\r
25546 BFD055C4 EE0F LI A0, 15
\r
25547 BFD055C6 EE8D LI A1, 13
\r
25548 BFD055C8 EF01 LI A2, 1
\r
25549 BFD055CA 3A4077E8 JALS jtvic_dis_clr_source
\r
25550 BFD055CC 0C003A40 SH S2, 3072(ZERO)
\r
25551 BFD055CE 0C00 NOP
\r
25553 BFD055D0 0FBE MOVE SP, S8
\r
25554 BFD055D2 4859 LW V0, 100(SP)
\r
25555 BFD055D4 3D7C0002 MTLO V0
\r
25556 BFD055D6 48783D7C LH T3, 18552(GP)
\r
25557 BFD055D8 4878 LW V1, 96(SP)
\r
25558 BFD055DA 2D7C0003 MTHI V1
\r
25559 BFD055DC 2D7C ANDI V0, A3, 0x40
\r
25560 BFD055DE 485C LW V0, 112(SP)
\r
25561 BFD055E0 2D27 ANDI V0, V0, 0xF
\r
25562 BFD055E2 001340A2 BNEZC V0, 0xBFD0560C
\r
25563 BFD055E6 4BF7 LW RA, 92(SP)
\r
25564 BFD055E8 4BD6 LW S8, 88(SP)
\r
25565 BFD055EA 4B35 LW T9, 84(SP)
\r
25566 BFD055EC 4B14 LW T8, 80(SP)
\r
25567 BFD055EE 49F3 LW T7, 76(SP)
\r
25568 BFD055F0 49D2 LW T6, 72(SP)
\r
25569 BFD055F2 49B1 LW T5, 68(SP)
\r
25570 BFD055F4 4990 LW T4, 64(SP)
\r
25571 BFD055F6 496F LW T3, 60(SP)
\r
25572 BFD055F8 494E LW T2, 56(SP)
\r
25573 BFD055FA 492D LW T1, 52(SP)
\r
25574 BFD055FC 490C LW T0, 48(SP)
\r
25575 BFD055FE 48EB LW A3, 44(SP)
\r
25576 BFD05600 48CA LW A2, 40(SP)
\r
25577 BFD05602 48A9 LW A1, 36(SP)
\r
25578 BFD05604 4888 LW A0, 32(SP)
\r
25579 BFD05606 4867 LW V1, 28(SP)
\r
25580 BFD05608 4846 LW V0, 24(SP)
\r
25581 BFD0560A 4825 LW AT, 20(SP)
\r
25582 BFD0560C 477C0000 DI ZERO
\r
25583 BFD05610 18000000 SLL ZERO, ZERO, 3
\r
25584 BFD05612 4B5D1800 SB ZERO, 19293(ZERO)
\r
25585 BFD05614 4B5D LW K0, 116(SP)
\r
25586 BFD05616 4B7B LW K1, 108(SP)
\r
25587 BFD05618 02FC034E MTC0 K0, EPC
\r
25588 BFD0561C 4B5C LW K0, 112(SP)
\r
25589 BFD0561E 4C3D ADDIU SP, SP, 120
\r
25590 BFD05620 12FC034C MTC0 K0, SRSCtl
\r
25591 BFD05622 03BD12FC ADDI S7, GP, 957
\r
25592 BFD05624 F17C03BD WRPGPR SP, SP
\r
25593 BFD05626 036CF17C JALX 0xBDF00DB0
\r
25594 BFD05628 02FC036C MTC0 K1, Status
\r
25595 BFD0562A 000002FC SLL S7, GP, 0
\r
25596 BFD0562C F37C0000 ERET
\r
25597 BFD0562E 4FF5F37C JALX 0xBDF13FD4
\r
25603 252: /* end girq23.c */
\r
25607 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq22.c ----
\r
25608 1: /*****************************************************************************
\r
25609 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
25610 3: * You may use this software and any derivatives exclusively with
\r
25611 4: * Microchip products.
\r
25612 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
25613 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
25614 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
25615 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
25616 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
25617 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
25618 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
25619 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
25620 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
25621 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
25622 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
25623 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
25624 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
25625 18: * OF THESE TERMS.
\r
25626 19: *****************************************************************************/
\r
25628 21: /** @file girq22.c
\r
25629 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
25631 24: /** @defgroup MEC14xx ISR
\r
25635 28: #include "appcfg.h"
\r
25636 29: #include "platform.h"
\r
25637 30: #include "MEC14xx/mec14xx.h"
\r
25638 31: #include "MEC14xx/mec14xx_girqs.h"
\r
25639 32: #include "MEC14xx/mec14xx_gpio.h"
\r
25640 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
25643 36: #if GIRQ22_DISAGG == 0
\r
25645 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
25646 39: girq22_isr(void)
\r
25648 BFD07228 E17C03BD RDPGPR SP, SP
\r
25649 BFD0722C 00FC036E MFC0 K1, EPC
\r
25650 BFD0722E 034C00FC INS A3, GP, 13, -12
\r
25651 BFD07230 10FC034C MFC0 K0, SRSCtl
\r
25652 BFD07232 4FF110FC ADDI A3, GP, 20465
\r
25653 BFD07234 4FF1 ADDIU SP, SP, -32
\r
25654 BFD07236 CB67 SW K1, 28(SP)
\r
25655 BFD07238 00FC036C MFC0 K1, Status
\r
25656 BFD0723C CB46 SW K0, 24(SP)
\r
25657 BFD0723E 00FC034D MFC0 K0, Cause
\r
25658 BFD07242 CB65 SW K1, 20(SP)
\r
25659 BFD07244 5040035A SRL K0, K0, 10
\r
25660 BFD07246 037A5040 ORI V0, ZERO, 890
\r
25661 BFD07248 7A8C037A INS K1, K0, 10, 6
\r
25662 BFD0724A 03607A8C ADDIUPC A1, 787296
\r
25663 BFD0724C 204C0360 INS K1, ZERO, 1, 4
\r
25664 BFD0724E 036C204C LWC2 V0, 876(T4)
\r
25665 BFD07250 02FC036C MTC0 K1, Status
\r
25666 BFD07254 C862 SW V1, 8(SP)
\r
25667 BFD07256 C841 SW V0, 4(SP)
\r
25668 BFD07258 4866 LW V1, 24(SP)
\r
25669 BFD0725A 2DB7 ANDI V1, V1, 0xF
\r
25670 BFD0725C CBC3 SW S8, 12(SP)
\r
25671 BFD0725E 0FDD MOVE S8, SP
\r
25672 41: JTVIC_GROUP_EN_CLR->w = (1ul<<14);
\r
25673 BFD07260 BFFF41A2 LUI V0, 0xBFFF
\r
25674 BFD07262 5042BFFF LDC1 F31, 20546(RA)
\r
25675 BFD07264 C50C5042 ORI V0, V0, -15092
\r
25676 BFD07268 40003060 ADDIU V1, ZERO, 16384
\r
25677 BFD0726A E9A04000 BLTZ ZERO, 0xBFD045AE
\r
25678 BFD0726C E9A0 SW V1, 0(V0)
\r
25680 BFD0726E 0FBE MOVE SP, S8
\r
25681 BFD07270 4846 LW V0, 24(SP)
\r
25682 BFD07272 2D27 ANDI V0, V0, 0xF
\r
25683 BFD07274 4BC3 LW S8, 12(SP)
\r
25684 BFD07276 4862 LW V1, 8(SP)
\r
25685 BFD07278 4841 LW V0, 4(SP)
\r
25686 BFD0727A 477C0000 DI ZERO
\r
25687 BFD0727E 18000000 SLL ZERO, ZERO, 3
\r
25688 BFD07280 4B471800 SB ZERO, 19271(ZERO)
\r
25689 BFD07282 4B47 LW K0, 28(SP)
\r
25690 BFD07284 4B65 LW K1, 20(SP)
\r
25691 BFD07286 02FC034E MTC0 K0, EPC
\r
25692 BFD0728A 4B46 LW K0, 24(SP)
\r
25693 BFD0728C 4C11 ADDIU SP, SP, 32
\r
25694 BFD0728E 12FC034C MTC0 K0, SRSCtl
\r
25695 BFD07290 03BD12FC ADDI S7, GP, 957
\r
25696 BFD07292 F17C03BD WRPGPR SP, SP
\r
25697 BFD07294 036CF17C JALX 0xBDF00DB0
\r
25698 BFD07296 02FC036C MTC0 K1, Status
\r
25699 BFD07298 000002FC SLL S7, GP, 0
\r
25700 BFD0729A F37C0000 ERET
\r
25701 BFD0729C 0C00F37C JALX 0xBDF03000
\r
25705 46: void __attribute__((weak, interrupt, nomips16))
\r
25706 47: girq22_b0(void)
\r
25708 49: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 0);
\r
25711 52: void __attribute__((weak, interrupt, nomips16))
\r
25712 53: girq22_b1(void)
\r
25714 55: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 1);
\r
25717 58: void __attribute__((weak, interrupt, nomips16))
\r
25718 59: girq22_b2(void)
\r
25720 61: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 2);
\r
25723 64: void __attribute__((weak, interrupt, nomips16))
\r
25724 65: girq22_b3(void)
\r
25726 67: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 3);
\r
25729 70: void __attribute__((weak, interrupt, nomips16))
\r
25730 71: girq22_b4(void)
\r
25732 73: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 4);
\r
25735 76: void __attribute__((weak, interrupt, nomips16))
\r
25736 77: girq22_b5(void)
\r
25738 79: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 5);
\r
25741 82: void __attribute__((weak, interrupt, nomips16))
\r
25742 83: girq22_b6(void)
\r
25744 85: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 6);
\r
25747 88: void __attribute__((weak, interrupt, nomips16))
\r
25748 89: girq22_b7(void)
\r
25750 91: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 7);
\r
25753 94: void __attribute__((weak, interrupt, nomips16))
\r
25754 95: girq22_b8(void)
\r
25756 97: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 8);
\r
25759 100: void __attribute__((weak, interrupt, nomips16))
\r
25760 101: girq22_b9(void)
\r
25762 103: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 9);
\r
25768 109: /* end girq22.c */
\r
25772 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq21.c ----
\r
25773 1: /*****************************************************************************
\r
25774 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
25775 3: * You may use this software and any derivatives exclusively with
\r
25776 4: * Microchip products.
\r
25777 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
25778 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
25779 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
25780 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
25781 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
25782 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
25783 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
25784 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
25785 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
25786 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
25787 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
25788 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
25789 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
25790 18: * OF THESE TERMS.
\r
25791 19: *****************************************************************************/
\r
25793 21: /** @file girq21.c
\r
25794 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
25796 24: /** @defgroup MEC14xx ISR
\r
25800 28: #include "appcfg.h"
\r
25801 29: #include "platform.h"
\r
25802 30: #include "MEC14xx/mec14xx.h"
\r
25803 31: #include "MEC14xx/mec14xx_girqs.h"
\r
25804 32: #include "MEC14xx/mec14xx_gpio.h"
\r
25805 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
25808 36: #if GIRQ21_DISAGG == 0
\r
25811 39: * GIRQ21 is a wake peripheral logic only interrupt.
\r
25812 40: * It's purpose is to allow the peripheral logic such as SMBus or LPC to
\r
25813 41: * wake an service HW event without waking the EC.
\r
25814 42: * This handler is superfluous.
\r
25817 45: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
25818 46: girq21_isr(void)
\r
25820 BFD071B0 E17C03BD RDPGPR SP, SP
\r
25821 BFD071B4 00FC036E MFC0 K1, EPC
\r
25822 BFD071B6 034C00FC INS A3, GP, 13, -12
\r
25823 BFD071B8 10FC034C MFC0 K0, SRSCtl
\r
25824 BFD071BA 4FF110FC ADDI A3, GP, 20465
\r
25825 BFD071BC 4FF1 ADDIU SP, SP, -32
\r
25826 BFD071BE CB67 SW K1, 28(SP)
\r
25827 BFD071C0 00FC036C MFC0 K1, Status
\r
25828 BFD071C4 CB46 SW K0, 24(SP)
\r
25829 BFD071C6 00FC034D MFC0 K0, Cause
\r
25830 BFD071CA CB65 SW K1, 20(SP)
\r
25831 BFD071CC 5040035A SRL K0, K0, 10
\r
25832 BFD071CE 037A5040 ORI V0, ZERO, 890
\r
25833 BFD071D0 7A8C037A INS K1, K0, 10, 6
\r
25834 BFD071D2 03607A8C ADDIUPC A1, 787296
\r
25835 BFD071D4 204C0360 INS K1, ZERO, 1, 4
\r
25836 BFD071D6 036C204C LWC2 V0, 876(T4)
\r
25837 BFD071D8 02FC036C MTC0 K1, Status
\r
25838 BFD071DC C862 SW V1, 8(SP)
\r
25839 BFD071DE C841 SW V0, 4(SP)
\r
25840 BFD071E0 4866 LW V1, 24(SP)
\r
25841 BFD071E2 2DB7 ANDI V1, V1, 0xF
\r
25842 BFD071E4 CBC3 SW S8, 12(SP)
\r
25843 BFD071E6 0FDD MOVE S8, SP
\r
25844 48: JTVIC_GROUP_EN_CLR->w = (1ul<<13);
\r
25845 BFD071E8 BFFF41A2 LUI V0, 0xBFFF
\r
25846 BFD071EA 5042BFFF LDC1 F31, 20546(RA)
\r
25847 BFD071EC C50C5042 ORI V0, V0, -15092
\r
25848 BFD071F0 20003060 ADDIU V1, ZERO, 8192
\r
25849 BFD071F4 E9A0 SW V1, 0(V0)
\r
25851 BFD071F6 0FBE MOVE SP, S8
\r
25852 BFD071F8 4846 LW V0, 24(SP)
\r
25853 BFD071FA 2D27 ANDI V0, V0, 0xF
\r
25854 BFD071FC 4BC3 LW S8, 12(SP)
\r
25855 BFD071FE 4862 LW V1, 8(SP)
\r
25856 BFD07200 4841 LW V0, 4(SP)
\r
25857 BFD07202 477C0000 DI ZERO
\r
25858 BFD07206 18000000 SLL ZERO, ZERO, 3
\r
25859 BFD07208 4B471800 SB ZERO, 19271(ZERO)
\r
25860 BFD0720A 4B47 LW K0, 28(SP)
\r
25861 BFD0720C 4B65 LW K1, 20(SP)
\r
25862 BFD0720E 02FC034E MTC0 K0, EPC
\r
25863 BFD07212 4B46 LW K0, 24(SP)
\r
25864 BFD07214 4C11 ADDIU SP, SP, 32
\r
25865 BFD07216 12FC034C MTC0 K0, SRSCtl
\r
25866 BFD07218 03BD12FC ADDI S7, GP, 957
\r
25867 BFD0721A F17C03BD WRPGPR SP, SP
\r
25868 BFD0721C 036CF17C JALX 0xBDF00DB0
\r
25869 BFD0721E 02FC036C MTC0 K1, Status
\r
25870 BFD07220 000002FC SLL S7, GP, 0
\r
25871 BFD07222 F37C0000 ERET
\r
25872 BFD07224 0C00F37C JALX 0xBDF03000
\r
25876 53: void __attribute__((weak, interrupt, nomips16))
\r
25877 54: girq21_b0(void)
\r
25879 56: JTVIC_GROUP_EN_CLR->w = (1ul<<13);
\r
25884 61: /* end girq21.c */
\r
25888 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq20.c ----
\r
25889 1: /*****************************************************************************
\r
25890 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
25891 3: * You may use this software and any derivatives exclusively with
\r
25892 4: * Microchip products.
\r
25893 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
25894 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
25895 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
25896 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
25897 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
25898 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
25899 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
25900 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
25901 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
25902 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
25903 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
25904 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
25905 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
25906 18: * OF THESE TERMS.
\r
25907 19: *****************************************************************************/
\r
25909 21: /** @file girq20.c
\r
25910 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
25912 24: /** @defgroup MEC14xx ISR
\r
25916 28: #include "appcfg.h"
\r
25917 29: #include "platform.h"
\r
25918 30: #include "MEC14xx/mec14xx.h"
\r
25919 31: #include "MEC14xx/mec14xx_girqs.h"
\r
25920 32: #include "MEC14xx/mec14xx_gpio.h"
\r
25921 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
25924 36: #if GIRQ20_DISAGG == 0
\r
25926 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
25927 39: girq20_isr(void)
\r
25929 BFD07138 E17C03BD RDPGPR SP, SP
\r
25930 BFD0713C 00FC036E MFC0 K1, EPC
\r
25931 BFD0713E 034C00FC INS A3, GP, 13, -12
\r
25932 BFD07140 10FC034C MFC0 K0, SRSCtl
\r
25933 BFD07142 4FF110FC ADDI A3, GP, 20465
\r
25934 BFD07144 4FF1 ADDIU SP, SP, -32
\r
25935 BFD07146 CB67 SW K1, 28(SP)
\r
25936 BFD07148 00FC036C MFC0 K1, Status
\r
25937 BFD0714C CB46 SW K0, 24(SP)
\r
25938 BFD0714E 00FC034D MFC0 K0, Cause
\r
25939 BFD07152 CB65 SW K1, 20(SP)
\r
25940 BFD07154 5040035A SRL K0, K0, 10
\r
25941 BFD07156 037A5040 ORI V0, ZERO, 890
\r
25942 BFD07158 7A8C037A INS K1, K0, 10, 6
\r
25943 BFD0715A 03607A8C ADDIUPC A1, 787296
\r
25944 BFD0715C 204C0360 INS K1, ZERO, 1, 4
\r
25945 BFD0715E 036C204C LWC2 V0, 876(T4)
\r
25946 BFD07160 02FC036C MTC0 K1, Status
\r
25947 BFD07164 C862 SW V1, 8(SP)
\r
25948 BFD07166 C841 SW V0, 4(SP)
\r
25949 BFD07168 4866 LW V1, 24(SP)
\r
25950 BFD0716A 2DB7 ANDI V1, V1, 0xF
\r
25951 BFD0716C CBC3 SW S8, 12(SP)
\r
25952 BFD0716E 0FDD MOVE S8, SP
\r
25953 41: JTVIC_GROUP_EN_CLR->w = (1ul<<12);
\r
25954 BFD07170 BFFF41A2 LUI V0, 0xBFFF
\r
25955 BFD07172 5042BFFF LDC1 F31, 20546(RA)
\r
25956 BFD07174 C50C5042 ORI V0, V0, -15092
\r
25957 BFD07178 10003060 ADDIU V1, ZERO, 4096
\r
25958 BFD0717A E9A01000 ADDI ZERO, ZERO, -5728
\r
25959 BFD0717C E9A0 SW V1, 0(V0)
\r
25961 BFD0717E 0FBE MOVE SP, S8
\r
25962 BFD07180 4846 LW V0, 24(SP)
\r
25963 BFD07182 2D27 ANDI V0, V0, 0xF
\r
25964 BFD07184 4BC3 LW S8, 12(SP)
\r
25965 BFD07186 4862 LW V1, 8(SP)
\r
25966 BFD07188 4841 LW V0, 4(SP)
\r
25967 BFD0718A 477C0000 DI ZERO
\r
25968 BFD0718E 18000000 SLL ZERO, ZERO, 3
\r
25969 BFD07190 4B471800 SB ZERO, 19271(ZERO)
\r
25970 BFD07192 4B47 LW K0, 28(SP)
\r
25971 BFD07194 4B65 LW K1, 20(SP)
\r
25972 BFD07196 02FC034E MTC0 K0, EPC
\r
25973 BFD0719A 4B46 LW K0, 24(SP)
\r
25974 BFD0719C 4C11 ADDIU SP, SP, 32
\r
25975 BFD0719E 12FC034C MTC0 K0, SRSCtl
\r
25976 BFD071A0 03BD12FC ADDI S7, GP, 957
\r
25977 BFD071A2 F17C03BD WRPGPR SP, SP
\r
25978 BFD071A4 036CF17C JALX 0xBDF00DB0
\r
25979 BFD071A6 02FC036C MTC0 K1, Status
\r
25980 BFD071A8 000002FC SLL S7, GP, 0
\r
25981 BFD071AA F37C0000 ERET
\r
25982 BFD071AC 0C00F37C JALX 0xBDF03000
\r
25986 46: void __attribute__((weak, interrupt, nomips16))
\r
25987 47: girq20_b0(void)
\r
25989 49: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 0);
\r
25992 52: void __attribute__((weak, interrupt, nomips16))
\r
25993 53: girq20_b1(void)
\r
25995 55: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 1);
\r
25998 58: void __attribute__((weak, interrupt, nomips16))
\r
25999 59: girq20_b2(void)
\r
26001 61: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 2);
\r
26004 64: void __attribute__((weak, interrupt, nomips16))
\r
26005 65: girq20_b3(void)
\r
26007 67: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 3);
\r
26010 70: void __attribute__((weak, interrupt, nomips16))
\r
26011 71: girq20_b4(void)
\r
26013 73: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 4);
\r
26016 76: void __attribute__((weak, interrupt, nomips16))
\r
26017 77: girq20_b5(void)
\r
26019 79: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 5);
\r
26025 85: /* end girq20.c */
\r
26029 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq19.c ----
\r
26030 1: /*****************************************************************************
\r
26031 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
26032 3: * You may use this software and any derivatives exclusively with
\r
26033 4: * Microchip products.
\r
26034 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
26035 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
26036 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
26037 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
26038 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
26039 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
26040 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
26041 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
26042 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
26043 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
26044 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
26045 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
26046 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
26047 18: * OF THESE TERMS.
\r
26048 19: *****************************************************************************/
\r
26050 21: /** @file girq19.c
\r
26051 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
26053 24: /** @defgroup MEC14xx ISR
\r
26057 28: #include "appcfg.h"
\r
26058 29: #include "platform.h"
\r
26059 30: #include "MEC14xx/mec14xx.h"
\r
26060 31: #include "MEC14xx/mec14xx_girqs.h"
\r
26061 32: #include "MEC14xx/mec14xx_gpio.h"
\r
26062 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
26065 36: #if GIRQ19_DISAGG == 0
\r
26067 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
26068 39: girq19_isr(void)
\r
26070 BFD070C0 E17C03BD RDPGPR SP, SP
\r
26071 BFD070C4 00FC036E MFC0 K1, EPC
\r
26072 BFD070C6 034C00FC INS A3, GP, 13, -12
\r
26073 BFD070C8 10FC034C MFC0 K0, SRSCtl
\r
26074 BFD070CA 4FF110FC ADDI A3, GP, 20465
\r
26075 BFD070CC 4FF1 ADDIU SP, SP, -32
\r
26076 BFD070CE CB67 SW K1, 28(SP)
\r
26077 BFD070D0 00FC036C MFC0 K1, Status
\r
26078 BFD070D4 CB46 SW K0, 24(SP)
\r
26079 BFD070D6 00FC034D MFC0 K0, Cause
\r
26080 BFD070DA CB65 SW K1, 20(SP)
\r
26081 BFD070DC 5040035A SRL K0, K0, 10
\r
26082 BFD070DE 037A5040 ORI V0, ZERO, 890
\r
26083 BFD070E0 7A8C037A INS K1, K0, 10, 6
\r
26084 BFD070E2 03607A8C ADDIUPC A1, 787296
\r
26085 BFD070E4 204C0360 INS K1, ZERO, 1, 4
\r
26086 BFD070E6 036C204C LWC2 V0, 876(T4)
\r
26087 BFD070E8 02FC036C MTC0 K1, Status
\r
26088 BFD070EC C862 SW V1, 8(SP)
\r
26089 BFD070EE C841 SW V0, 4(SP)
\r
26090 BFD070F0 4866 LW V1, 24(SP)
\r
26091 BFD070F2 2DB7 ANDI V1, V1, 0xF
\r
26092 BFD070F4 CBC3 SW S8, 12(SP)
\r
26093 BFD070F6 0FDD MOVE S8, SP
\r
26094 41: JTVIC_GROUP_EN_CLR->w = (1ul<<11);
\r
26095 BFD070F8 BFFF41A2 LUI V0, 0xBFFF
\r
26096 BFD070FA 5042BFFF LDC1 F31, 20546(RA)
\r
26097 BFD070FC C50C5042 ORI V0, V0, -15092
\r
26098 BFD07100 08003060 ADDIU V1, ZERO, 2048
\r
26099 BFD07102 0800 LBU S0, 0(S0)
\r
26100 BFD07104 E9A0 SW V1, 0(V0)
\r
26102 BFD07106 0FBE MOVE SP, S8
\r
26103 BFD07108 4846 LW V0, 24(SP)
\r
26104 BFD0710A 2D27 ANDI V0, V0, 0xF
\r
26105 BFD0710C 4BC3 LW S8, 12(SP)
\r
26106 BFD0710E 4862 LW V1, 8(SP)
\r
26107 BFD07110 4841 LW V0, 4(SP)
\r
26108 BFD07112 477C0000 DI ZERO
\r
26109 BFD07116 18000000 SLL ZERO, ZERO, 3
\r
26110 BFD07118 4B471800 SB ZERO, 19271(ZERO)
\r
26111 BFD0711A 4B47 LW K0, 28(SP)
\r
26112 BFD0711C 4B65 LW K1, 20(SP)
\r
26113 BFD0711E 02FC034E MTC0 K0, EPC
\r
26114 BFD07122 4B46 LW K0, 24(SP)
\r
26115 BFD07124 4C11 ADDIU SP, SP, 32
\r
26116 BFD07126 12FC034C MTC0 K0, SRSCtl
\r
26117 BFD07128 03BD12FC ADDI S7, GP, 957
\r
26118 BFD0712A F17C03BD WRPGPR SP, SP
\r
26119 BFD0712C 036CF17C JALX 0xBDF00DB0
\r
26120 BFD0712E 02FC036C MTC0 K1, Status
\r
26121 BFD07130 000002FC SLL S7, GP, 0
\r
26122 BFD07132 F37C0000 ERET
\r
26123 BFD07134 0C00F37C JALX 0xBDF03000
\r
26127 46: void __attribute__((weak, interrupt, nomips16))
\r
26128 47: girq19_b0(void)
\r
26130 49: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 0);
\r
26133 52: void __attribute__((weak, interrupt, nomips16))
\r
26134 53: girq19_b1(void)
\r
26136 55: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 1);
\r
26139 58: void __attribute__((weak, interrupt, nomips16))
\r
26140 59: girq19_b2(void)
\r
26142 61: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 2);
\r
26145 64: void __attribute__((weak, interrupt, nomips16))
\r
26146 65: girq19_b3(void)
\r
26148 67: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 3);
\r
26151 70: void __attribute__((weak, interrupt, nomips16))
\r
26152 71: girq19_b4(void)
\r
26154 73: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 4);
\r
26157 76: void __attribute__((weak, interrupt, nomips16))
\r
26158 77: girq19_b5(void)
\r
26160 79: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 5);
\r
26163 82: void __attribute__((weak, interrupt, nomips16))
\r
26164 83: girq19_b6(void)
\r
26166 85: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 6);
\r
26169 88: void __attribute__((weak, interrupt, nomips16))
\r
26170 89: girq19_b7(void)
\r
26172 91: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 7);
\r
26175 94: void __attribute__((weak, interrupt, nomips16))
\r
26176 95: girq19_b8(void)
\r
26178 97: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 8);
\r
26184 103: /* end girq19.c */
\r
26188 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq18.c ----
\r
26189 1: /*****************************************************************************
\r
26190 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
26191 3: * You may use this software and any derivatives exclusively with
\r
26192 4: * Microchip products.
\r
26193 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
26194 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
26195 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
26196 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
26197 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
26198 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
26199 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
26200 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
26201 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
26202 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
26203 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
26204 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
26205 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
26206 18: * OF THESE TERMS.
\r
26207 19: *****************************************************************************/
\r
26209 21: /** @file girq18.c
\r
26210 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
26212 24: /** @defgroup MEC14xx ISR
\r
26216 28: #include "appcfg.h"
\r
26217 29: #include "platform.h"
\r
26218 30: #include "MEC14xx/mec14xx.h"
\r
26219 31: #include "MEC14xx/mec14xx_girqs.h"
\r
26220 32: #include "MEC14xx/mec14xx_gpio.h"
\r
26221 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
26224 36: #if GIRQ18_DISAGG == 0
\r
26226 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
26227 39: girq18_isr(void)
\r
26229 BFD07048 E17C03BD RDPGPR SP, SP
\r
26230 BFD0704C 00FC036E MFC0 K1, EPC
\r
26231 BFD0704E 034C00FC INS A3, GP, 13, -12
\r
26232 BFD07050 10FC034C MFC0 K0, SRSCtl
\r
26233 BFD07052 4FF110FC ADDI A3, GP, 20465
\r
26234 BFD07054 4FF1 ADDIU SP, SP, -32
\r
26235 BFD07056 CB67 SW K1, 28(SP)
\r
26236 BFD07058 00FC036C MFC0 K1, Status
\r
26237 BFD0705C CB46 SW K0, 24(SP)
\r
26238 BFD0705E 00FC034D MFC0 K0, Cause
\r
26239 BFD07062 CB65 SW K1, 20(SP)
\r
26240 BFD07064 5040035A SRL K0, K0, 10
\r
26241 BFD07066 037A5040 ORI V0, ZERO, 890
\r
26242 BFD07068 7A8C037A INS K1, K0, 10, 6
\r
26243 BFD0706A 03607A8C ADDIUPC A1, 787296
\r
26244 BFD0706C 204C0360 INS K1, ZERO, 1, 4
\r
26245 BFD0706E 036C204C LWC2 V0, 876(T4)
\r
26246 BFD07070 02FC036C MTC0 K1, Status
\r
26247 BFD07074 C862 SW V1, 8(SP)
\r
26248 BFD07076 C841 SW V0, 4(SP)
\r
26249 BFD07078 4866 LW V1, 24(SP)
\r
26250 BFD0707A 2DB7 ANDI V1, V1, 0xF
\r
26251 BFD0707C CBC3 SW S8, 12(SP)
\r
26252 BFD0707E 0FDD MOVE S8, SP
\r
26253 41: JTVIC_GROUP_EN_CLR->w = (1ul<<10);
\r
26254 BFD07080 BFFF41A2 LUI V0, 0xBFFF
\r
26255 BFD07082 5042BFFF LDC1 F31, 20546(RA)
\r
26256 BFD07084 C50C5042 ORI V0, V0, -15092
\r
26257 BFD07088 04003060 ADDIU V1, ZERO, 1024
\r
26258 BFD0708A 0400 ADDU S0, S0, S0
\r
26259 BFD0708C E9A0 SW V1, 0(V0)
\r
26261 BFD0708E 0FBE MOVE SP, S8
\r
26262 BFD07090 4846 LW V0, 24(SP)
\r
26263 BFD07092 2D27 ANDI V0, V0, 0xF
\r
26264 BFD07094 4BC3 LW S8, 12(SP)
\r
26265 BFD07096 4862 LW V1, 8(SP)
\r
26266 BFD07098 4841 LW V0, 4(SP)
\r
26267 BFD0709A 477C0000 DI ZERO
\r
26268 BFD0709E 18000000 SLL ZERO, ZERO, 3
\r
26269 BFD070A0 4B471800 SB ZERO, 19271(ZERO)
\r
26270 BFD070A2 4B47 LW K0, 28(SP)
\r
26271 BFD070A4 4B65 LW K1, 20(SP)
\r
26272 BFD070A6 02FC034E MTC0 K0, EPC
\r
26273 BFD070AA 4B46 LW K0, 24(SP)
\r
26274 BFD070AC 4C11 ADDIU SP, SP, 32
\r
26275 BFD070AE 12FC034C MTC0 K0, SRSCtl
\r
26276 BFD070B0 03BD12FC ADDI S7, GP, 957
\r
26277 BFD070B2 F17C03BD WRPGPR SP, SP
\r
26278 BFD070B4 036CF17C JALX 0xBDF00DB0
\r
26279 BFD070B6 02FC036C MTC0 K1, Status
\r
26280 BFD070B8 000002FC SLL S7, GP, 0
\r
26281 BFD070BA F37C0000 ERET
\r
26282 BFD070BC 0C00F37C JALX 0xBDF03000
\r
26286 46: void __attribute__((weak, interrupt, nomips16))
\r
26287 47: girq18_b0(void)
\r
26289 49: jtvic_dis_clr_source(MEC14xx_GIRQ18_ID, 0);
\r
26294 54: /* end girq18.c */
\r
26298 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq17.c ----
\r
26299 1: /*****************************************************************************
\r
26300 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
26301 3: * You may use this software and any derivatives exclusively with
\r
26302 4: * Microchip products.
\r
26303 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
26304 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
26305 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
26306 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
26307 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
26308 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
26309 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
26310 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
26311 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
26312 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
26313 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
26314 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
26315 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
26316 18: * OF THESE TERMS.
\r
26317 19: *****************************************************************************/
\r
26319 21: /** @file girq17.c
\r
26320 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
26322 24: /** @defgroup MEC14xx ISR
\r
26326 28: #include "appcfg.h"
\r
26327 29: #include "platform.h"
\r
26328 30: #include "MEC14xx/mec14xx.h"
\r
26329 31: #include "MEC14xx/mec14xx_girqs.h"
\r
26330 32: #include "MEC14xx/mec14xx_gpio.h"
\r
26331 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
26334 36: #if GIRQ17_DISAGG == 0
\r
26336 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
26337 39: girq17_isr(void)
\r
26339 BFD06FD0 E17C03BD RDPGPR SP, SP
\r
26340 BFD06FD4 00FC036E MFC0 K1, EPC
\r
26341 BFD06FD6 034C00FC INS A3, GP, 13, -12
\r
26342 BFD06FD8 10FC034C MFC0 K0, SRSCtl
\r
26343 BFD06FDA 4FF110FC ADDI A3, GP, 20465
\r
26344 BFD06FDC 4FF1 ADDIU SP, SP, -32
\r
26345 BFD06FDE CB67 SW K1, 28(SP)
\r
26346 BFD06FE0 00FC036C MFC0 K1, Status
\r
26347 BFD06FE4 CB46 SW K0, 24(SP)
\r
26348 BFD06FE6 00FC034D MFC0 K0, Cause
\r
26349 BFD06FEA CB65 SW K1, 20(SP)
\r
26350 BFD06FEC 5040035A SRL K0, K0, 10
\r
26351 BFD06FEE 037A5040 ORI V0, ZERO, 890
\r
26352 BFD06FF0 7A8C037A INS K1, K0, 10, 6
\r
26353 BFD06FF2 03607A8C ADDIUPC A1, 787296
\r
26354 BFD06FF4 204C0360 INS K1, ZERO, 1, 4
\r
26355 BFD06FF6 036C204C LWC2 V0, 876(T4)
\r
26356 BFD06FF8 02FC036C MTC0 K1, Status
\r
26357 BFD06FFC C862 SW V1, 8(SP)
\r
26358 BFD06FFE C841 SW V0, 4(SP)
\r
26359 BFD07000 4866 LW V1, 24(SP)
\r
26360 BFD07002 2DB7 ANDI V1, V1, 0xF
\r
26361 BFD07004 CBC3 SW S8, 12(SP)
\r
26362 BFD07006 0FDD MOVE S8, SP
\r
26363 41: JTVIC_GROUP_EN_CLR->w = (1ul<<9);
\r
26364 BFD07008 BFFF41A2 LUI V0, 0xBFFF
\r
26365 BFD0700A 5042BFFF LDC1 F31, 20546(RA)
\r
26366 BFD0700C C50C5042 ORI V0, V0, -15092
\r
26367 BFD07010 02003060 ADDIU V1, ZERO, 512
\r
26368 BFD07014 E9A0 SW V1, 0(V0)
\r
26370 BFD07016 0FBE MOVE SP, S8
\r
26371 BFD07018 4846 LW V0, 24(SP)
\r
26372 BFD0701A 2D27 ANDI V0, V0, 0xF
\r
26373 BFD0701C 4BC3 LW S8, 12(SP)
\r
26374 BFD0701E 4862 LW V1, 8(SP)
\r
26375 BFD07020 4841 LW V0, 4(SP)
\r
26376 BFD07022 477C0000 DI ZERO
\r
26377 BFD07026 18000000 SLL ZERO, ZERO, 3
\r
26378 BFD07028 4B471800 SB ZERO, 19271(ZERO)
\r
26379 BFD0702A 4B47 LW K0, 28(SP)
\r
26380 BFD0702C 4B65 LW K1, 20(SP)
\r
26381 BFD0702E 02FC034E MTC0 K0, EPC
\r
26382 BFD07032 4B46 LW K0, 24(SP)
\r
26383 BFD07034 4C11 ADDIU SP, SP, 32
\r
26384 BFD07036 12FC034C MTC0 K0, SRSCtl
\r
26385 BFD07038 03BD12FC ADDI S7, GP, 957
\r
26386 BFD0703A F17C03BD WRPGPR SP, SP
\r
26387 BFD0703C 036CF17C JALX 0xBDF00DB0
\r
26388 BFD0703E 02FC036C MTC0 K1, Status
\r
26389 BFD07040 000002FC SLL S7, GP, 0
\r
26390 BFD07042 F37C0000 ERET
\r
26391 BFD07044 0C00F37C JALX 0xBDF03000
\r
26395 46: void __attribute__((weak, interrupt, nomips16))
\r
26396 47: girq17_b0(void)
\r
26398 49: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 0);
\r
26399 50: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 0);
\r
26402 53: void __attribute__((weak, interrupt, nomips16))
\r
26403 54: girq17_b1(void)
\r
26405 56: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 1);
\r
26406 57: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 1);
\r
26409 60: void __attribute__((weak, interrupt, nomips16))
\r
26410 61: girq17_b2(void)
\r
26412 63: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 2);
\r
26413 64: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 2);
\r
26416 67: void __attribute__((weak, interrupt, nomips16))
\r
26417 68: girq17_b3(void)
\r
26419 70: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 3);
\r
26420 71: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 3);
\r
26423 74: void __attribute__((weak, interrupt, nomips16))
\r
26424 75: girq17_b4(void)
\r
26426 77: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 4);
\r
26427 78: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 4);
\r
26430 81: void __attribute__((weak, interrupt, nomips16))
\r
26431 82: girq17_b5(void)
\r
26433 84: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 5);
\r
26434 85: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 5);
\r
26437 88: void __attribute__((weak, interrupt, nomips16))
\r
26438 89: girq17_b6(void)
\r
26440 91: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 6);
\r
26441 92: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 6);
\r
26444 95: void __attribute__((weak, interrupt, nomips16))
\r
26445 96: girq17_b7(void)
\r
26447 98: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 7);
\r
26448 99: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 7);
\r
26451 102: void __attribute__((weak, interrupt, nomips16))
\r
26452 103: girq17_b8(void)
\r
26454 105: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 8);
\r
26455 106: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 8);
\r
26458 109: void __attribute__((weak, interrupt, nomips16))
\r
26459 110: girq17_b9(void)
\r
26461 112: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 9);
\r
26462 113: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 9);
\r
26465 116: void __attribute__((weak, interrupt, nomips16))
\r
26466 117: girq17_b10(void)
\r
26468 119: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 10);
\r
26469 120: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 10);
\r
26474 125: /* end girq17.c */
\r
26478 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq16.c ----
\r
26479 1: /*****************************************************************************
\r
26480 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
26481 3: * You may use this software and any derivatives exclusively with
\r
26482 4: * Microchip products.
\r
26483 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
26484 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
26485 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
26486 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
26487 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
26488 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
26489 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
26490 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
26491 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
26492 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
26493 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
26494 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
26495 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
26496 18: * OF THESE TERMS.
\r
26497 19: *****************************************************************************/
\r
26499 21: /** @file girq16.c
\r
26500 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
26502 24: /** @defgroup MEC14xx ISR
\r
26507 29: #include "appcfg.h"
\r
26508 30: #include "platform.h"
\r
26509 31: #include "MEC14xx/mec14xx.h"
\r
26510 32: #include "MEC14xx/mec14xx_girqs.h"
\r
26511 33: #include "MEC14xx/mec14xx_gpio.h"
\r
26512 34: #include "MEC14xx/mec14xx_trace_func.h"
\r
26515 37: #if GIRQ16_DISAGG == 0
\r
26517 39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
26518 40: girq16_isr(void)
\r
26520 BFD06F58 E17C03BD RDPGPR SP, SP
\r
26521 BFD06F5C 00FC036E MFC0 K1, EPC
\r
26522 BFD06F5E 034C00FC INS A3, GP, 13, -12
\r
26523 BFD06F60 10FC034C MFC0 K0, SRSCtl
\r
26524 BFD06F62 4FF110FC ADDI A3, GP, 20465
\r
26525 BFD06F64 4FF1 ADDIU SP, SP, -32
\r
26526 BFD06F66 CB67 SW K1, 28(SP)
\r
26527 BFD06F68 00FC036C MFC0 K1, Status
\r
26528 BFD06F6C CB46 SW K0, 24(SP)
\r
26529 BFD06F6E 00FC034D MFC0 K0, Cause
\r
26530 BFD06F72 CB65 SW K1, 20(SP)
\r
26531 BFD06F74 5040035A SRL K0, K0, 10
\r
26532 BFD06F76 037A5040 ORI V0, ZERO, 890
\r
26533 BFD06F78 7A8C037A INS K1, K0, 10, 6
\r
26534 BFD06F7A 03607A8C ADDIUPC A1, 787296
\r
26535 BFD06F7C 204C0360 INS K1, ZERO, 1, 4
\r
26536 BFD06F7E 036C204C LWC2 V0, 876(T4)
\r
26537 BFD06F80 02FC036C MTC0 K1, Status
\r
26538 BFD06F84 C862 SW V1, 8(SP)
\r
26539 BFD06F86 C841 SW V0, 4(SP)
\r
26540 BFD06F88 4866 LW V1, 24(SP)
\r
26541 BFD06F8A 2DB7 ANDI V1, V1, 0xF
\r
26542 BFD06F8C CBC3 SW S8, 12(SP)
\r
26543 BFD06F8E 0FDD MOVE S8, SP
\r
26544 42: JTVIC_GROUP_EN_CLR->w = (1ul<<8);
\r
26545 BFD06F90 BFFF41A2 LUI V0, 0xBFFF
\r
26546 BFD06F92 5042BFFF LDC1 F31, 20546(RA)
\r
26547 BFD06F94 C50C5042 ORI V0, V0, -15092
\r
26548 BFD06F98 01003060 ADDIU V1, ZERO, 256
\r
26549 BFD06F9C E9A0 SW V1, 0(V0)
\r
26551 BFD06F9E 0FBE MOVE SP, S8
\r
26552 BFD06FA0 4846 LW V0, 24(SP)
\r
26553 BFD06FA2 2D27 ANDI V0, V0, 0xF
\r
26554 BFD06FA4 4BC3 LW S8, 12(SP)
\r
26555 BFD06FA6 4862 LW V1, 8(SP)
\r
26556 BFD06FA8 4841 LW V0, 4(SP)
\r
26557 BFD06FAA 477C0000 DI ZERO
\r
26558 BFD06FAE 18000000 SLL ZERO, ZERO, 3
\r
26559 BFD06FB0 4B471800 SB ZERO, 19271(ZERO)
\r
26560 BFD06FB2 4B47 LW K0, 28(SP)
\r
26561 BFD06FB4 4B65 LW K1, 20(SP)
\r
26562 BFD06FB6 02FC034E MTC0 K0, EPC
\r
26563 BFD06FBA 4B46 LW K0, 24(SP)
\r
26564 BFD06FBC 4C11 ADDIU SP, SP, 32
\r
26565 BFD06FBE 12FC034C MTC0 K0, SRSCtl
\r
26566 BFD06FC0 03BD12FC ADDI S7, GP, 957
\r
26567 BFD06FC2 F17C03BD WRPGPR SP, SP
\r
26568 BFD06FC4 036CF17C JALX 0xBDF00DB0
\r
26569 BFD06FC6 02FC036C MTC0 K1, Status
\r
26570 BFD06FC8 000002FC SLL S7, GP, 0
\r
26571 BFD06FCA F37C0000 ERET
\r
26572 BFD06FCC 0C00F37C JALX 0xBDF03000
\r
26576 47: void __attribute__((weak, interrupt, nomips16))
\r
26577 48: girq16_b0(void)
\r
26579 50: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 0);
\r
26582 53: void __attribute__((weak, interrupt, nomips16))
\r
26583 54: girq16_b1(void)
\r
26585 56: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 1);
\r
26588 59: void __attribute__((weak, interrupt, nomips16))
\r
26589 60: girq16_b2(void)
\r
26591 62: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 2);
\r
26594 65: void __attribute__((weak, interrupt, nomips16))
\r
26595 66: girq16_b3(void)
\r
26597 68: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 3);
\r
26600 71: void __attribute__((weak, interrupt, nomips16))
\r
26601 72: girq16_b4(void)
\r
26603 74: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 4);
\r
26606 77: void __attribute__((weak, interrupt, nomips16))
\r
26607 78: girq16_b5(void)
\r
26609 80: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 5);
\r
26612 83: void __attribute__((weak, interrupt, nomips16))
\r
26613 84: girq16_b6(void)
\r
26615 86: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 6);
\r
26618 89: void __attribute__((weak, interrupt, nomips16))
\r
26619 90: girq16_b7(void)
\r
26621 92: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 7);
\r
26624 95: void __attribute__((weak, interrupt, nomips16))
\r
26625 96: girq16_b8(void)
\r
26627 98: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 8);
\r
26630 101: void __attribute__((weak, interrupt, nomips16))
\r
26631 102: girq16_b9(void)
\r
26633 104: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 9);
\r
26638 109: /* end girq16.c */
\r
26642 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq15.c ----
\r
26643 1: /*****************************************************************************
\r
26644 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
26645 3: * You may use this software and any derivatives exclusively with
\r
26646 4: * Microchip products.
\r
26647 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
26648 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
26649 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
26650 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
26651 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
26652 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
26653 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
26654 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
26655 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
26656 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
26657 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
26658 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
26659 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
26660 18: * OF THESE TERMS.
\r
26661 19: *****************************************************************************/
\r
26663 21: /** @file girq15.c
\r
26664 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
26666 24: /** @defgroup MEC14xx ISR
\r
26670 28: #include "appcfg.h"
\r
26671 29: #include "platform.h"
\r
26672 30: #include "MEC14xx/mec14xx.h"
\r
26673 31: #include "MEC14xx/mec14xx_girqs.h"
\r
26674 32: #include "MEC14xx/mec14xx_gpio.h"
\r
26675 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
26678 36: #if GIRQ15_DISAGG == 0
\r
26680 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
26681 39: girq15_isr(void)
\r
26683 BFD06EE0 E17C03BD RDPGPR SP, SP
\r
26684 BFD06EE4 00FC036E MFC0 K1, EPC
\r
26685 BFD06EE6 034C00FC INS A3, GP, 13, -12
\r
26686 BFD06EE8 10FC034C MFC0 K0, SRSCtl
\r
26687 BFD06EEA 4FF110FC ADDI A3, GP, 20465
\r
26688 BFD06EEC 4FF1 ADDIU SP, SP, -32
\r
26689 BFD06EEE CB67 SW K1, 28(SP)
\r
26690 BFD06EF0 00FC036C MFC0 K1, Status
\r
26691 BFD06EF4 CB46 SW K0, 24(SP)
\r
26692 BFD06EF6 00FC034D MFC0 K0, Cause
\r
26693 BFD06EFA CB65 SW K1, 20(SP)
\r
26694 BFD06EFC 5040035A SRL K0, K0, 10
\r
26695 BFD06EFE 037A5040 ORI V0, ZERO, 890
\r
26696 BFD06F00 7A8C037A INS K1, K0, 10, 6
\r
26697 BFD06F02 03607A8C ADDIUPC A1, 787296
\r
26698 BFD06F04 204C0360 INS K1, ZERO, 1, 4
\r
26699 BFD06F06 036C204C LWC2 V0, 876(T4)
\r
26700 BFD06F08 02FC036C MTC0 K1, Status
\r
26701 BFD06F0C C862 SW V1, 8(SP)
\r
26702 BFD06F0E C841 SW V0, 4(SP)
\r
26703 BFD06F10 4866 LW V1, 24(SP)
\r
26704 BFD06F12 2DB7 ANDI V1, V1, 0xF
\r
26705 BFD06F14 CBC3 SW S8, 12(SP)
\r
26706 BFD06F16 0FDD MOVE S8, SP
\r
26707 41: JTVIC_GROUP_EN_CLR->w = (1ul<<7);
\r
26708 BFD06F18 BFFF41A2 LUI V0, 0xBFFF
\r
26709 BFD06F1A 5042BFFF LDC1 F31, 20546(RA)
\r
26710 BFD06F1C C50C5042 ORI V0, V0, -15092
\r
26711 BFD06F20 00803060 ADDIU V1, ZERO, 128
\r
26712 BFD06F24 E9A0 SW V1, 0(V0)
\r
26714 BFD06F26 0FBE MOVE SP, S8
\r
26715 BFD06F28 4846 LW V0, 24(SP)
\r
26716 BFD06F2A 2D27 ANDI V0, V0, 0xF
\r
26717 BFD06F2C 4BC3 LW S8, 12(SP)
\r
26718 BFD06F2E 4862 LW V1, 8(SP)
\r
26719 BFD06F30 4841 LW V0, 4(SP)
\r
26720 BFD06F32 477C0000 DI ZERO
\r
26721 BFD06F36 18000000 SLL ZERO, ZERO, 3
\r
26722 BFD06F38 4B471800 SB ZERO, 19271(ZERO)
\r
26723 BFD06F3A 4B47 LW K0, 28(SP)
\r
26724 BFD06F3C 4B65 LW K1, 20(SP)
\r
26725 BFD06F3E 02FC034E MTC0 K0, EPC
\r
26726 BFD06F42 4B46 LW K0, 24(SP)
\r
26727 BFD06F44 4C11 ADDIU SP, SP, 32
\r
26728 BFD06F46 12FC034C MTC0 K0, SRSCtl
\r
26729 BFD06F48 03BD12FC ADDI S7, GP, 957
\r
26730 BFD06F4A F17C03BD WRPGPR SP, SP
\r
26731 BFD06F4C 036CF17C JALX 0xBDF00DB0
\r
26732 BFD06F4E 02FC036C MTC0 K1, Status
\r
26733 BFD06F50 000002FC SLL S7, GP, 0
\r
26734 BFD06F52 F37C0000 ERET
\r
26735 BFD06F54 0C00F37C JALX 0xBDF03000
\r
26739 46: void __attribute__((weak, interrupt, nomips16))
\r
26740 47: girq15_b0(void)
\r
26742 49: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 0);
\r
26745 52: void __attribute__((weak, interrupt, nomips16))
\r
26746 53: girq15_b1(void)
\r
26748 55: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 1);
\r
26751 58: void __attribute__((weak, interrupt, nomips16))
\r
26752 59: girq15_b2(void)
\r
26754 61: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 2);
\r
26757 64: void __attribute__((weak, interrupt, nomips16))
\r
26758 65: girq15_b3(void)
\r
26760 67: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 3);
\r
26763 70: void __attribute__((weak, interrupt, nomips16))
\r
26764 71: girq15_b4(void)
\r
26766 73: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 4);
\r
26769 76: void __attribute__((weak, interrupt, nomips16))
\r
26770 77: girq15_b5(void)
\r
26772 79: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 5);
\r
26775 82: void __attribute__((weak, interrupt, nomips16))
\r
26776 83: girq15_b6(void)
\r
26778 85: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 6);
\r
26781 88: void __attribute__((weak, interrupt, nomips16))
\r
26782 89: girq15_b7(void)
\r
26784 91: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 7);
\r
26787 94: void __attribute__((weak, interrupt, nomips16))
\r
26788 95: girq15_b8(void)
\r
26790 97: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 8);
\r
26793 100: void __attribute__((weak, interrupt, nomips16))
\r
26794 101: girq15_b9(void)
\r
26796 103: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 9);
\r
26799 106: void __attribute__((weak, interrupt, nomips16))
\r
26800 107: girq15_b10(void)
\r
26802 109: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 10);
\r
26805 112: void __attribute__((weak, interrupt, nomips16))
\r
26806 113: girq15_b11(void)
\r
26808 115: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 11);
\r
26811 118: void __attribute__((weak, interrupt, nomips16))
\r
26812 119: girq15_b12(void)
\r
26814 121: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 12);
\r
26817 124: void __attribute__((weak, interrupt, nomips16))
\r
26818 125: girq15_b13(void)
\r
26820 127: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 13);
\r
26823 130: void __attribute__((weak, interrupt, nomips16))
\r
26824 131: girq15_b14(void)
\r
26826 133: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 14);
\r
26829 136: void __attribute__((weak, interrupt, nomips16))
\r
26830 137: girq15_b15(void)
\r
26832 139: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 15);
\r
26835 142: void __attribute__((weak, interrupt, nomips16))
\r
26836 143: girq15_b16(void)
\r
26838 145: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 16);
\r
26841 148: void __attribute__((weak, interrupt, nomips16))
\r
26842 149: girq15_b17(void)
\r
26844 151: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 17);
\r
26847 154: void __attribute__((weak, interrupt, nomips16))
\r
26848 155: girq15_b18(void)
\r
26850 157: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 18);
\r
26856 163: /* end girq15.c */
\r
26860 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq14.c ----
\r
26861 1: /*****************************************************************************
\r
26862 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
26863 3: * You may use this software and any derivatives exclusively with
\r
26864 4: * Microchip products.
\r
26865 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
26866 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
26867 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
26868 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
26869 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
26870 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
26871 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
26872 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
26873 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
26874 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
26875 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
26876 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
26877 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
26878 18: * OF THESE TERMS.
\r
26879 19: *****************************************************************************/
\r
26881 21: /** @file girq14.c
\r
26882 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
26884 24: /** @defgroup MEC14xx ISR
\r
26888 28: #include "appcfg.h"
\r
26889 29: #include "platform.h"
\r
26890 30: #include "MEC14xx/mec14xx.h"
\r
26891 31: #include "MEC14xx/mec14xx_girqs.h"
\r
26892 32: #include "MEC14xx/mec14xx_gpio.h"
\r
26893 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
26896 36: #if GIRQ14_DISAGG == 0
\r
26898 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
26899 39: girq14_isr(void)
\r
26901 BFD078A0 E17C03BD RDPGPR SP, SP
\r
26902 BFD078A4 00FC036E MFC0 K1, EPC
\r
26903 BFD078A6 034C00FC INS A3, GP, 13, -12
\r
26904 BFD078A8 10FC034C MFC0 K0, SRSCtl
\r
26905 BFD078AA 4FF110FC ADDI A3, GP, 20465
\r
26906 BFD078AC 4FF1 ADDIU SP, SP, -32
\r
26907 BFD078AE CB67 SW K1, 28(SP)
\r
26908 BFD078B0 00FC036C MFC0 K1, Status
\r
26909 BFD078B4 CB46 SW K0, 24(SP)
\r
26910 BFD078B6 00FC034D MFC0 K0, Cause
\r
26911 BFD078BA CB65 SW K1, 20(SP)
\r
26912 BFD078BC 5040035A SRL K0, K0, 10
\r
26913 BFD078BE 037A5040 ORI V0, ZERO, 890
\r
26914 BFD078C0 7A8C037A INS K1, K0, 10, 6
\r
26915 BFD078C2 03607A8C ADDIUPC A1, 787296
\r
26916 BFD078C4 204C0360 INS K1, ZERO, 1, 4
\r
26917 BFD078C6 036C204C LWC2 V0, 876(T4)
\r
26918 BFD078C8 02FC036C MTC0 K1, Status
\r
26919 BFD078CC C862 SW V1, 8(SP)
\r
26920 BFD078CE C841 SW V0, 4(SP)
\r
26921 BFD078D0 4866 LW V1, 24(SP)
\r
26922 BFD078D2 2DB7 ANDI V1, V1, 0xF
\r
26923 BFD078D4 CBC3 SW S8, 12(SP)
\r
26924 BFD078D6 0FDD MOVE S8, SP
\r
26925 41: JTVIC_GROUP_EN_CLR->w = (1ul<<6);
\r
26926 BFD078D8 BFFF41A2 LUI V0, 0xBFFF
\r
26927 BFD078DA 5042BFFF LDC1 F31, 20546(RA)
\r
26928 BFD078DC C50C5042 ORI V0, V0, -15092
\r
26929 BFD078E0 EDC0 LI V1, 64
\r
26930 BFD078E2 E9A0 SW V1, 0(V0)
\r
26932 BFD078E4 0FBE MOVE SP, S8
\r
26933 BFD078E6 4846 LW V0, 24(SP)
\r
26934 BFD078E8 2D27 ANDI V0, V0, 0xF
\r
26935 BFD078EA 4BC3 LW S8, 12(SP)
\r
26936 BFD078EC 4862 LW V1, 8(SP)
\r
26937 BFD078EE 4841 LW V0, 4(SP)
\r
26938 BFD078F0 477C0000 DI ZERO
\r
26939 BFD078F4 18000000 SLL ZERO, ZERO, 3
\r
26940 BFD078F6 4B471800 SB ZERO, 19271(ZERO)
\r
26941 BFD078F8 4B47 LW K0, 28(SP)
\r
26942 BFD078FA 4B65 LW K1, 20(SP)
\r
26943 BFD078FC 02FC034E MTC0 K0, EPC
\r
26944 BFD07900 4B46 LW K0, 24(SP)
\r
26945 BFD07902 4C11 ADDIU SP, SP, 32
\r
26946 BFD07904 12FC034C MTC0 K0, SRSCtl
\r
26947 BFD07906 03BD12FC ADDI S7, GP, 957
\r
26948 BFD07908 F17C03BD WRPGPR SP, SP
\r
26949 BFD0790A 036CF17C JALX 0xBDF00DB0
\r
26950 BFD0790C 02FC036C MTC0 K1, Status
\r
26951 BFD0790E 000002FC SLL S7, GP, 0
\r
26952 BFD07910 F37C0000 ERET
\r
26953 BFD07912 4FF1F37C JALX 0xBDF13FC4
\r
26957 46: void __attribute__((weak, interrupt, nomips16))
\r
26958 47: girq14_b0(void)
\r
26960 49: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 0);
\r
26963 52: void __attribute__((weak, interrupt, nomips16))
\r
26964 53: girq14_b1(void)
\r
26966 55: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 1);
\r
26969 58: void __attribute__((weak, interrupt, nomips16))
\r
26970 59: girq14_b2(void)
\r
26972 61: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 2);
\r
26975 64: void __attribute__((weak, interrupt, nomips16))
\r
26976 65: girq14_b3(void)
\r
26978 67: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 3);
\r
26981 70: void __attribute__((weak, interrupt, nomips16))
\r
26982 71: girq14_b4(void)
\r
26984 73: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 4);
\r
26987 76: void __attribute__((weak, interrupt, nomips16))
\r
26988 77: girq14_b5(void)
\r
26990 79: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 5);
\r
26996 85: /* end girq14.c */
\r
27000 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq13.c ----
\r
27001 1: /*****************************************************************************
\r
27002 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
27003 3: * You may use this software and any derivatives exclusively with
\r
27004 4: * Microchip products.
\r
27005 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
27006 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
27007 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
27008 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
27009 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
27010 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
27011 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
27012 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
27013 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
27014 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
27015 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
27016 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
27017 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
27018 18: * OF THESE TERMS.
\r
27019 19: *****************************************************************************/
\r
27021 21: /** @file girq13.c
\r
27022 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
27024 24: /** @defgroup MEC14xx ISR
\r
27028 28: #include "appcfg.h"
\r
27029 29: #include "platform.h"
\r
27030 30: #include "MEC14xx/mec14xx.h"
\r
27031 31: #include "MEC14xx/mec14xx_girqs.h"
\r
27032 32: #include "MEC14xx/mec14xx_gpio.h"
\r
27033 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
27036 36: #if GIRQ13_DISAGG == 0
\r
27038 38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
27039 39: girq13_isr(void)
\r
27041 BFD0782C E17C03BD RDPGPR SP, SP
\r
27042 BFD07830 00FC036E MFC0 K1, EPC
\r
27043 BFD07832 034C00FC INS A3, GP, 13, -12
\r
27044 BFD07834 10FC034C MFC0 K0, SRSCtl
\r
27045 BFD07836 4FF110FC ADDI A3, GP, 20465
\r
27046 BFD07838 4FF1 ADDIU SP, SP, -32
\r
27047 BFD0783A CB67 SW K1, 28(SP)
\r
27048 BFD0783C 00FC036C MFC0 K1, Status
\r
27049 BFD07840 CB46 SW K0, 24(SP)
\r
27050 BFD07842 00FC034D MFC0 K0, Cause
\r
27051 BFD07846 CB65 SW K1, 20(SP)
\r
27052 BFD07848 5040035A SRL K0, K0, 10
\r
27053 BFD0784A 037A5040 ORI V0, ZERO, 890
\r
27054 BFD0784C 7A8C037A INS K1, K0, 10, 6
\r
27055 BFD0784E 03607A8C ADDIUPC A1, 787296
\r
27056 BFD07850 204C0360 INS K1, ZERO, 1, 4
\r
27057 BFD07852 036C204C LWC2 V0, 876(T4)
\r
27058 BFD07854 02FC036C MTC0 K1, Status
\r
27059 BFD07858 C862 SW V1, 8(SP)
\r
27060 BFD0785A C841 SW V0, 4(SP)
\r
27061 BFD0785C 4866 LW V1, 24(SP)
\r
27062 BFD0785E 2DB7 ANDI V1, V1, 0xF
\r
27063 BFD07860 CBC3 SW S8, 12(SP)
\r
27064 BFD07862 0FDD MOVE S8, SP
\r
27065 41: JTVIC_GROUP_EN_CLR->w = (1ul<<5);
\r
27066 BFD07864 BFFF41A2 LUI V0, 0xBFFF
\r
27067 BFD07866 5042BFFF LDC1 F31, 20546(RA)
\r
27068 BFD07868 C50C5042 ORI V0, V0, -15092
\r
27069 BFD0786C EDA0 LI V1, 32
\r
27070 BFD0786E E9A0 SW V1, 0(V0)
\r
27072 BFD07870 0FBE MOVE SP, S8
\r
27073 BFD07872 4846 LW V0, 24(SP)
\r
27074 BFD07874 2D27 ANDI V0, V0, 0xF
\r
27075 BFD07876 4BC3 LW S8, 12(SP)
\r
27076 BFD07878 4862 LW V1, 8(SP)
\r
27077 BFD0787A 4841 LW V0, 4(SP)
\r
27078 BFD0787C 477C0000 DI ZERO
\r
27079 BFD07880 18000000 SLL ZERO, ZERO, 3
\r
27080 BFD07882 4B471800 SB ZERO, 19271(ZERO)
\r
27081 BFD07884 4B47 LW K0, 28(SP)
\r
27082 BFD07886 4B65 LW K1, 20(SP)
\r
27083 BFD07888 02FC034E MTC0 K0, EPC
\r
27084 BFD0788C 4B46 LW K0, 24(SP)
\r
27085 BFD0788E 4C11 ADDIU SP, SP, 32
\r
27086 BFD07890 12FC034C MTC0 K0, SRSCtl
\r
27087 BFD07892 03BD12FC ADDI S7, GP, 957
\r
27088 BFD07894 F17C03BD WRPGPR SP, SP
\r
27089 BFD07896 036CF17C JALX 0xBDF00DB0
\r
27090 BFD07898 02FC036C MTC0 K1, Status
\r
27091 BFD0789A 000002FC SLL S7, GP, 0
\r
27092 BFD0789C F37C0000 ERET
\r
27093 BFD0789E 03BDF37C JALX 0xBDF00EF4
\r
27097 46: void __attribute__((weak, interrupt, nomips16))
\r
27098 47: girq13_b0(void)
\r
27100 49: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 0);
\r
27103 52: void __attribute__((weak, interrupt, nomips16))
\r
27104 53: girq13_b1(void)
\r
27106 55: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 1);
\r
27109 58: void __attribute__((weak, interrupt, nomips16))
\r
27110 59: girq13_b2(void)
\r
27112 61: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 2);
\r
27115 64: void __attribute__((weak, interrupt, nomips16))
\r
27116 65: girq13_b3(void)
\r
27118 67: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 3);
\r
27121 70: void __attribute__((weak, interrupt, nomips16))
\r
27122 71: girq13_b4(void)
\r
27124 73: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 4);
\r
27127 76: void __attribute__((weak, interrupt, nomips16))
\r
27128 77: girq13_b5(void)
\r
27130 79: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 5);
\r
27133 82: void __attribute__((weak, interrupt, nomips16))
\r
27134 83: girq13_b6(void)
\r
27136 85: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 6);
\r
27141 90: /* end girq13.c */
\r
27145 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq12.c ----
\r
27146 1: /*****************************************************************************
\r
27147 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
27148 3: * You may use this software and any derivatives exclusively with
\r
27149 4: * Microchip products.
\r
27150 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
27151 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
27152 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
27153 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
27154 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
27155 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
27156 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
27157 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
27158 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
27159 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
27160 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
27161 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
27162 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
27163 18: * OF THESE TERMS.
\r
27164 19: *****************************************************************************/
\r
27166 21: /** @file girq12.c
\r
27167 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
27169 24: /** @defgroup MEC14xx ISR
\r
27174 29: #include "appcfg.h"
\r
27175 30: #include "platform.h"
\r
27176 31: #include "MEC14xx/mec14xx.h"
\r
27177 32: #include "MEC14xx/mec14xx_girqs.h"
\r
27178 33: #include "MEC14xx/mec14xx_gpio.h"
\r
27179 34: #include "MEC14xx/mec14xx_trace_func.h"
\r
27182 37: #if GIRQ12_DISAGG == 0
\r
27184 39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
27185 40: girq12_isr(void)
\r
27187 BFD077B8 E17C03BD RDPGPR SP, SP
\r
27188 BFD077BC 00FC036E MFC0 K1, EPC
\r
27189 BFD077BE 034C00FC INS A3, GP, 13, -12
\r
27190 BFD077C0 10FC034C MFC0 K0, SRSCtl
\r
27191 BFD077C2 4FF110FC ADDI A3, GP, 20465
\r
27192 BFD077C4 4FF1 ADDIU SP, SP, -32
\r
27193 BFD077C6 CB67 SW K1, 28(SP)
\r
27194 BFD077C8 00FC036C MFC0 K1, Status
\r
27195 BFD077CC CB46 SW K0, 24(SP)
\r
27196 BFD077CE 00FC034D MFC0 K0, Cause
\r
27197 BFD077D2 CB65 SW K1, 20(SP)
\r
27198 BFD077D4 5040035A SRL K0, K0, 10
\r
27199 BFD077D6 037A5040 ORI V0, ZERO, 890
\r
27200 BFD077D8 7A8C037A INS K1, K0, 10, 6
\r
27201 BFD077DA 03607A8C ADDIUPC A1, 787296
\r
27202 BFD077DC 204C0360 INS K1, ZERO, 1, 4
\r
27203 BFD077DE 036C204C LWC2 V0, 876(T4)
\r
27204 BFD077E0 02FC036C MTC0 K1, Status
\r
27205 BFD077E4 C862 SW V1, 8(SP)
\r
27206 BFD077E6 C841 SW V0, 4(SP)
\r
27207 BFD077E8 4866 LW V1, 24(SP)
\r
27208 BFD077EA 2DB7 ANDI V1, V1, 0xF
\r
27209 BFD077EC CBC3 SW S8, 12(SP)
\r
27210 BFD077EE 0FDD MOVE S8, SP
\r
27211 42: JTVIC_GROUP_EN_CLR->w = (1ul<<4);
\r
27212 BFD077F0 BFFF41A2 LUI V0, 0xBFFF
\r
27213 BFD077F2 5042BFFF LDC1 F31, 20546(RA)
\r
27214 BFD077F4 C50C5042 ORI V0, V0, -15092
\r
27215 BFD077F8 ED90 LI V1, 16
\r
27216 BFD077FA E9A0 SW V1, 0(V0)
\r
27218 BFD077FC 0FBE MOVE SP, S8
\r
27219 BFD077FE 4846 LW V0, 24(SP)
\r
27220 BFD07800 2D27 ANDI V0, V0, 0xF
\r
27221 BFD07802 4BC3 LW S8, 12(SP)
\r
27222 BFD07804 4862 LW V1, 8(SP)
\r
27223 BFD07806 4841 LW V0, 4(SP)
\r
27224 BFD07808 477C0000 DI ZERO
\r
27225 BFD0780C 18000000 SLL ZERO, ZERO, 3
\r
27226 BFD0780E 4B471800 SB ZERO, 19271(ZERO)
\r
27227 BFD07810 4B47 LW K0, 28(SP)
\r
27228 BFD07812 4B65 LW K1, 20(SP)
\r
27229 BFD07814 02FC034E MTC0 K0, EPC
\r
27230 BFD07818 4B46 LW K0, 24(SP)
\r
27231 BFD0781A 4C11 ADDIU SP, SP, 32
\r
27232 BFD0781C 12FC034C MTC0 K0, SRSCtl
\r
27233 BFD0781E 03BD12FC ADDI S7, GP, 957
\r
27234 BFD07820 F17C03BD WRPGPR SP, SP
\r
27235 BFD07822 036CF17C JALX 0xBDF00DB0
\r
27236 BFD07824 02FC036C MTC0 K1, Status
\r
27237 BFD07826 000002FC SLL S7, GP, 0
\r
27238 BFD07828 F37C0000 ERET
\r
27239 BFD0782A 03BDF37C JALX 0xBDF00EF4
\r
27243 47: void __attribute__((weak, interrupt, nomips16))
\r
27244 48: girq12_b0(void)
\r
27246 50: jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 0);
\r
27249 53: void __attribute__((weak, interrupt, nomips16))
\r
27250 54: girq12_b1(void)
\r
27252 56: jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 1);
\r
27255 59: void __attribute__((weak, interrupt, nomips16))
\r
27256 60: girq12_b2(void)
\r
27258 62: jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 2);
\r
27263 67: /* end girq12.c */
\r
27267 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq11.c ----
\r
27268 1: /*****************************************************************************
\r
27269 2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.
\r
27270 3: * You may use this software and any derivatives exclusively with
\r
27271 4: * Microchip products.
\r
27272 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
27273 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
27274 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
27275 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
27276 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
27277 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
27278 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
27279 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
27280 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
27281 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
27282 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
27283 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
27284 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
27285 18: * OF THESE TERMS.
\r
27286 19: *****************************************************************************/
\r
27288 21: /** @file girq11.c
\r
27289 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
27291 24: /** @defgroup MEC14xx ISR
\r
27296 29: #include "appcfg.h"
\r
27297 30: #include "platform.h"
\r
27298 31: #include "MEC14xx/mec14xx.h"
\r
27299 32: #include "MEC14xx/mec14xx_girqs.h"
\r
27300 33: #include "MEC14xx/mec14xx_gpio.h"
\r
27301 34: #include "MEC14xx/mec14xx_trace_func.h"
\r
27304 37: #if GIRQ11_DISAGG == 0
\r
27306 39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
27307 40: girq11_isr(void)
\r
27309 BFD07744 E17C03BD RDPGPR SP, SP
\r
27310 BFD07748 00FC036E MFC0 K1, EPC
\r
27311 BFD0774A 034C00FC INS A3, GP, 13, -12
\r
27312 BFD0774C 10FC034C MFC0 K0, SRSCtl
\r
27313 BFD0774E 4FF110FC ADDI A3, GP, 20465
\r
27314 BFD07750 4FF1 ADDIU SP, SP, -32
\r
27315 BFD07752 CB67 SW K1, 28(SP)
\r
27316 BFD07754 00FC036C MFC0 K1, Status
\r
27317 BFD07758 CB46 SW K0, 24(SP)
\r
27318 BFD0775A 00FC034D MFC0 K0, Cause
\r
27319 BFD0775E CB65 SW K1, 20(SP)
\r
27320 BFD07760 5040035A SRL K0, K0, 10
\r
27321 BFD07762 037A5040 ORI V0, ZERO, 890
\r
27322 BFD07764 7A8C037A INS K1, K0, 10, 6
\r
27323 BFD07766 03607A8C ADDIUPC A1, 787296
\r
27324 BFD07768 204C0360 INS K1, ZERO, 1, 4
\r
27325 BFD0776A 036C204C LWC2 V0, 876(T4)
\r
27326 BFD0776C 02FC036C MTC0 K1, Status
\r
27327 BFD07770 C862 SW V1, 8(SP)
\r
27328 BFD07772 C841 SW V0, 4(SP)
\r
27329 BFD07774 4866 LW V1, 24(SP)
\r
27330 BFD07776 2DB7 ANDI V1, V1, 0xF
\r
27331 BFD07778 CBC3 SW S8, 12(SP)
\r
27332 BFD0777A 0FDD MOVE S8, SP
\r
27333 42: JTVIC_GROUP_EN_CLR->w = (1ul<<3);
\r
27334 BFD0777C BFFF41A2 LUI V0, 0xBFFF
\r
27335 BFD0777E 5042BFFF LDC1 F31, 20546(RA)
\r
27336 BFD07780 C50C5042 ORI V0, V0, -15092
\r
27337 BFD07784 ED88 LI V1, 8
\r
27338 BFD07786 E9A0 SW V1, 0(V0)
\r
27340 BFD07788 0FBE MOVE SP, S8
\r
27341 BFD0778A 4846 LW V0, 24(SP)
\r
27342 BFD0778C 2D27 ANDI V0, V0, 0xF
\r
27343 BFD0778E 4BC3 LW S8, 12(SP)
\r
27344 BFD07790 4862 LW V1, 8(SP)
\r
27345 BFD07792 4841 LW V0, 4(SP)
\r
27346 BFD07794 477C0000 DI ZERO
\r
27347 BFD07798 18000000 SLL ZERO, ZERO, 3
\r
27348 BFD0779A 4B471800 SB ZERO, 19271(ZERO)
\r
27349 BFD0779C 4B47 LW K0, 28(SP)
\r
27350 BFD0779E 4B65 LW K1, 20(SP)
\r
27351 BFD077A0 02FC034E MTC0 K0, EPC
\r
27352 BFD077A4 4B46 LW K0, 24(SP)
\r
27353 BFD077A6 4C11 ADDIU SP, SP, 32
\r
27354 BFD077A8 12FC034C MTC0 K0, SRSCtl
\r
27355 BFD077AA 03BD12FC ADDI S7, GP, 957
\r
27356 BFD077AC F17C03BD WRPGPR SP, SP
\r
27357 BFD077AE 036CF17C JALX 0xBDF00DB0
\r
27358 BFD077B0 02FC036C MTC0 K1, Status
\r
27359 BFD077B2 000002FC SLL S7, GP, 0
\r
27360 BFD077B4 F37C0000 ERET
\r
27361 BFD077B6 03BDF37C JALX 0xBDF00EF4
\r
27365 47: void __attribute__((weak, interrupt, nomips16))
\r
27366 48: girq11_b0(void)
\r
27371 53: void __attribute__((weak, interrupt, nomips16))
\r
27372 54: girq11_b1(void)
\r
27374 56: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 1, JTVIC_CLR_SRC);
\r
27377 59: void __attribute__((weak, interrupt, nomips16))
\r
27378 60: girq11_b2(void)
\r
27380 62: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 2, JTVIC_CLR_SRC);
\r
27383 65: void __attribute__((weak, interrupt, nomips16))
\r
27384 66: girq11_b3(void)
\r
27386 68: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 3, JTVIC_CLR_SRC);
\r
27389 71: void __attribute__((weak, interrupt, nomips16))
\r
27390 72: girq11_b4(void)
\r
27392 74: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 4, JTVIC_CLR_SRC);
\r
27395 77: void __attribute__((weak, interrupt, nomips16))
\r
27396 78: girq11_b5(void)
\r
27398 80: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 5, JTVIC_CLR_SRC);
\r
27401 83: void __attribute__((weak, interrupt, nomips16))
\r
27402 84: girq11_b6(void)
\r
27404 86: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 6, JTVIC_CLR_SRC);
\r
27407 89: void __attribute__((weak, interrupt, nomips16))
\r
27408 90: girq11_b7(void)
\r
27410 92: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 7, JTVIC_CLR_SRC);
\r
27413 95: void __attribute__((weak, interrupt, nomips16))
\r
27414 96: girq11_b8(void)
\r
27416 98: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 8, JTVIC_CLR_SRC);
\r
27419 101: void __attribute__((weak, interrupt, nomips16))
\r
27420 102: girq11_b9(void)
\r
27422 104: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 9, JTVIC_CLR_SRC);
\r
27425 107: void __attribute__((weak, interrupt, nomips16))
\r
27426 108: girq11_b10(void)
\r
27428 110: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 10, JTVIC_CLR_SRC);
\r
27431 113: void __attribute__((weak, interrupt, nomips16))
\r
27432 114: girq11_b11(void)
\r
27434 116: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 11, JTVIC_CLR_SRC);
\r
27437 119: void __attribute__((weak, interrupt, nomips16))
\r
27438 120: girq11_b12(void)
\r
27440 122: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 12, JTVIC_CLR_SRC);
\r
27443 125: void __attribute__((weak, interrupt, nomips16))
\r
27444 126: girq11_b13(void)
\r
27446 128: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 13, JTVIC_CLR_SRC);
\r
27449 131: void __attribute__((weak, interrupt, nomips16))
\r
27450 132: girq11_b14(void)
\r
27452 134: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 14, JTVIC_CLR_SRC);
\r
27455 137: void __attribute__((weak, interrupt, nomips16))
\r
27456 138: girq11_b15(void)
\r
27458 140: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 15, JTVIC_CLR_SRC);
\r
27461 143: void __attribute__((weak, interrupt, nomips16))
\r
27462 144: girq11_b16(void)
\r
27464 146: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 16, JTVIC_CLR_SRC);
\r
27467 149: void __attribute__((weak, interrupt, nomips16))
\r
27468 150: girq11_b17(void)
\r
27470 152: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 17, JTVIC_CLR_SRC);
\r
27473 155: void __attribute__((weak, interrupt, nomips16))
\r
27474 156: girq11_b18(void)
\r
27476 158: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 18, JTVIC_CLR_SRC);
\r
27479 161: void __attribute__((weak, interrupt, nomips16))
\r
27480 162: girq11_b19(void)
\r
27482 164: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 19, JTVIC_CLR_SRC);
\r
27485 167: void __attribute__((weak, interrupt, nomips16))
\r
27486 168: girq11_b20(void)
\r
27488 170: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 20, JTVIC_CLR_SRC);
\r
27491 173: void __attribute__((weak, interrupt, nomips16))
\r
27492 174: girq11_b21(void)
\r
27494 176: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 21, JTVIC_CLR_SRC);
\r
27497 179: void __attribute__((weak, interrupt, nomips16))
\r
27498 180: girq11_b22(void)
\r
27500 182: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 22, JTVIC_CLR_SRC);
\r
27503 185: void __attribute__((weak, interrupt, nomips16))
\r
27504 186: girq11_b23(void)
\r
27506 188: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 23, JTVIC_CLR_SRC);
\r
27509 191: void __attribute__((weak, interrupt, nomips16))
\r
27510 192: girq11_b24(void)
\r
27512 194: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 24, JTVIC_CLR_SRC);
\r
27515 197: void __attribute__((weak, interrupt, nomips16))
\r
27516 198: girq11_b25(void)
\r
27518 200: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 25, JTVIC_CLR_SRC);
\r
27521 203: void __attribute__((weak, interrupt, nomips16))
\r
27522 204: girq11_b26(void)
\r
27524 206: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 26, JTVIC_CLR_SRC);
\r
27527 209: void __attribute__((weak, interrupt, nomips16))
\r
27528 210: girq11_b27(void)
\r
27530 212: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 27, JTVIC_CLR_SRC);
\r
27533 215: void __attribute__((weak, interrupt, nomips16))
\r
27534 216: girq11_b28(void)
\r
27536 218: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 28, JTVIC_CLR_SRC);
\r
27539 221: void __attribute__((weak, interrupt, nomips16))
\r
27540 222: girq11_b29(void)
\r
27542 224: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 29, JTVIC_CLR_SRC);
\r
27545 227: void __attribute__((weak, interrupt, nomips16))
\r
27546 228: girq11_b30(void)
\r
27548 230: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 30, JTVIC_CLR_SRC);
\r
27553 235: /* end girq11.c */
\r
27557 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq10.c ----
\r
27558 1: /*****************************************************************************
\r
27559 2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.
\r
27560 3: * You may use this software and any derivatives exclusively with
\r
27561 4: * Microchip products.
\r
27562 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
27563 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
27564 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
27565 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
27566 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
27567 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
27568 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
27569 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
27570 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
27571 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
27572 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
27573 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
27574 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
27575 18: * OF THESE TERMS.
\r
27576 19: *****************************************************************************/
\r
27578 21: /** @file girq10.c
\r
27579 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
27581 24: /** @defgroup MEC14xx ISR
\r
27586 29: #include "appcfg.h"
\r
27587 30: #include "platform.h"
\r
27588 31: #include "MEC14xx/mec14xx.h"
\r
27589 32: #include "MEC14xx/mec14xx_girqs.h"
\r
27590 33: #include "MEC14xx/mec14xx_gpio.h"
\r
27591 34: #include "MEC14xx/mec14xx_trace_func.h"
\r
27594 37: #if GIRQ10_DISAGG == 0
\r
27596 39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
27597 40: girq10_isr(void)
\r
27599 BFD076D0 E17C03BD RDPGPR SP, SP
\r
27600 BFD076D4 00FC036E MFC0 K1, EPC
\r
27601 BFD076D6 034C00FC INS A3, GP, 13, -12
\r
27602 BFD076D8 10FC034C MFC0 K0, SRSCtl
\r
27603 BFD076DA 4FF110FC ADDI A3, GP, 20465
\r
27604 BFD076DC 4FF1 ADDIU SP, SP, -32
\r
27605 BFD076DE CB67 SW K1, 28(SP)
\r
27606 BFD076E0 00FC036C MFC0 K1, Status
\r
27607 BFD076E4 CB46 SW K0, 24(SP)
\r
27608 BFD076E6 00FC034D MFC0 K0, Cause
\r
27609 BFD076EA CB65 SW K1, 20(SP)
\r
27610 BFD076EC 5040035A SRL K0, K0, 10
\r
27611 BFD076EE 037A5040 ORI V0, ZERO, 890
\r
27612 BFD076F0 7A8C037A INS K1, K0, 10, 6
\r
27613 BFD076F2 03607A8C ADDIUPC A1, 787296
\r
27614 BFD076F4 204C0360 INS K1, ZERO, 1, 4
\r
27615 BFD076F6 036C204C LWC2 V0, 876(T4)
\r
27616 BFD076F8 02FC036C MTC0 K1, Status
\r
27617 BFD076FC C862 SW V1, 8(SP)
\r
27618 BFD076FE C841 SW V0, 4(SP)
\r
27619 BFD07700 4866 LW V1, 24(SP)
\r
27620 BFD07702 2DB7 ANDI V1, V1, 0xF
\r
27621 BFD07704 CBC3 SW S8, 12(SP)
\r
27622 BFD07706 0FDD MOVE S8, SP
\r
27623 42: JTVIC_GROUP_EN_CLR->w = (1ul<<2);
\r
27624 BFD07708 BFFF41A2 LUI V0, 0xBFFF
\r
27625 BFD0770A 5042BFFF LDC1 F31, 20546(RA)
\r
27626 BFD0770C C50C5042 ORI V0, V0, -15092
\r
27627 BFD07710 ED84 LI V1, 4
\r
27628 BFD07712 E9A0 SW V1, 0(V0)
\r
27630 BFD07714 0FBE MOVE SP, S8
\r
27631 BFD07716 4846 LW V0, 24(SP)
\r
27632 BFD07718 2D27 ANDI V0, V0, 0xF
\r
27633 BFD0771A 4BC3 LW S8, 12(SP)
\r
27634 BFD0771C 4862 LW V1, 8(SP)
\r
27635 BFD0771E 4841 LW V0, 4(SP)
\r
27636 BFD07720 477C0000 DI ZERO
\r
27637 BFD07724 18000000 SLL ZERO, ZERO, 3
\r
27638 BFD07726 4B471800 SB ZERO, 19271(ZERO)
\r
27639 BFD07728 4B47 LW K0, 28(SP)
\r
27640 BFD0772A 4B65 LW K1, 20(SP)
\r
27641 BFD0772C 02FC034E MTC0 K0, EPC
\r
27642 BFD07730 4B46 LW K0, 24(SP)
\r
27643 BFD07732 4C11 ADDIU SP, SP, 32
\r
27644 BFD07734 12FC034C MTC0 K0, SRSCtl
\r
27645 BFD07736 03BD12FC ADDI S7, GP, 957
\r
27646 BFD07738 F17C03BD WRPGPR SP, SP
\r
27647 BFD0773A 036CF17C JALX 0xBDF00DB0
\r
27648 BFD0773C 02FC036C MTC0 K1, Status
\r
27649 BFD0773E 000002FC SLL S7, GP, 0
\r
27650 BFD07740 F37C0000 ERET
\r
27651 BFD07742 03BDF37C JALX 0xBDF00EF4
\r
27655 47: void __attribute__((weak, interrupt, nomips16))
\r
27656 48: girq10_b0(void)
\r
27658 50: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 0, JTVIC_CLR_SRC);
\r
27661 53: void __attribute__((weak, interrupt, nomips16))
\r
27662 54: girq10_b1(void)
\r
27664 56: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 1, JTVIC_CLR_SRC);
\r
27667 59: void __attribute__((weak, interrupt, nomips16))
\r
27668 60: girq10_b2(void)
\r
27670 62: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 2, JTVIC_CLR_SRC);
\r
27673 65: void __attribute__((weak, interrupt, nomips16))
\r
27674 66: girq10_b3(void)
\r
27676 68: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 3, JTVIC_CLR_SRC);
\r
27679 71: void __attribute__((weak, interrupt, nomips16))
\r
27680 72: girq10_b4(void)
\r
27682 74: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 4, JTVIC_CLR_SRC);
\r
27685 77: void __attribute__((weak, interrupt, nomips16))
\r
27686 78: girq10_b5(void)
\r
27688 80: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 5, JTVIC_CLR_SRC);
\r
27691 83: void __attribute__((weak, interrupt, nomips16))
\r
27692 84: girq10_b6(void)
\r
27694 86: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 6, JTVIC_CLR_SRC);
\r
27697 89: void __attribute__((weak, interrupt, nomips16))
\r
27698 90: girq10_b7(void)
\r
27700 92: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 7, JTVIC_CLR_SRC);
\r
27703 95: void __attribute__((weak, interrupt, nomips16))
\r
27704 96: girq10_b8(void)
\r
27706 98: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 8, JTVIC_CLR_SRC);
\r
27709 101: void __attribute__((weak, interrupt, nomips16))
\r
27710 102: girq10_b9(void)
\r
27712 104: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 9, JTVIC_CLR_SRC);
\r
27715 107: void __attribute__((weak, interrupt, nomips16))
\r
27716 108: girq10_b10(void)
\r
27718 110: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 10, JTVIC_CLR_SRC);
\r
27721 113: void __attribute__((weak, interrupt, nomips16))
\r
27722 114: girq10_b11(void)
\r
27724 116: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 11, JTVIC_CLR_SRC);
\r
27728 120: void __attribute__((weak, interrupt, nomips16))
\r
27729 121: girq10_b12(void)
\r
27731 123: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 12, JTVIC_CLR_SRC);
\r
27734 126: void __attribute__((weak, interrupt, nomips16))
\r
27735 127: girq10_b13(void)
\r
27737 129: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 13, JTVIC_CLR_SRC);
\r
27740 132: void __attribute__((weak, interrupt, nomips16))
\r
27741 133: girq10_b14(void)
\r
27743 135: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 14, JTVIC_CLR_SRC);
\r
27746 138: void __attribute__((weak, interrupt, nomips16))
\r
27747 139: girq10_b15(void)
\r
27749 141: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 15, JTVIC_CLR_SRC);
\r
27752 144: void __attribute__((weak, interrupt, nomips16))
\r
27753 145: girq10_b16(void)
\r
27755 147: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 16, JTVIC_CLR_SRC);
\r
27758 150: void __attribute__((weak, interrupt, nomips16))
\r
27759 151: girq10_b17(void)
\r
27761 153: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 17, JTVIC_CLR_SRC);
\r
27764 156: void __attribute__((weak, interrupt, nomips16))
\r
27765 157: girq10_b18(void)
\r
27767 159: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 18, JTVIC_CLR_SRC);
\r
27770 162: void __attribute__((weak, interrupt, nomips16))
\r
27771 163: girq10_b19(void)
\r
27773 165: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 19, JTVIC_CLR_SRC);
\r
27776 168: void __attribute__((weak, interrupt, nomips16))
\r
27777 169: girq10_b20(void)
\r
27779 171: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 20, JTVIC_CLR_SRC);
\r
27782 174: void __attribute__((weak, interrupt, nomips16))
\r
27783 175: girq10_b21(void)
\r
27785 177: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 21, JTVIC_CLR_SRC);
\r
27788 180: void __attribute__((weak, interrupt, nomips16))
\r
27789 181: girq10_b22(void)
\r
27791 183: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 22, JTVIC_CLR_SRC);
\r
27794 186: void __attribute__((weak, interrupt, nomips16))
\r
27795 187: girq10_b23(void)
\r
27797 189: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 23, JTVIC_CLR_SRC);
\r
27802 194: /* end girq10.c */
\r
27806 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq09.c ----
\r
27807 1: /*****************************************************************************
\r
27808 2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.
\r
27809 3: * You may use this software and any derivatives exclusively with
\r
27810 4: * Microchip products.
\r
27811 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
27812 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
27813 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
27814 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
27815 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
27816 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
27817 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
27818 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
27819 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
27820 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
27821 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
27822 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
27823 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
27824 18: * OF THESE TERMS.
\r
27825 19: *****************************************************************************/
\r
27827 21: /** @file girq09.c
\r
27828 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
27830 24: /** @defgroup MEC14xx ISR
\r
27836 30: #include "appcfg.h"
\r
27837 31: #include "platform.h"
\r
27838 32: #include "MEC14xx/mec14xx.h"
\r
27839 33: #include "MEC14xx/mec14xx_girqs.h"
\r
27840 34: #include "MEC14xx/mec14xx_gpio.h"
\r
27841 35: #include "MEC14xx/mec14xx_trace_func.h"
\r
27844 38: #if GIRQ09_DISAGG == 0
\r
27847 41: * Aggregated mode handler, must handle all enabled
\r
27848 42: * GIRQ08 sources.
\r
27850 44: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
27851 45: girq09_isr( void )
\r
27853 BFD0765C E17C03BD RDPGPR SP, SP
\r
27854 BFD07660 00FC036E MFC0 K1, EPC
\r
27855 BFD07662 034C00FC INS A3, GP, 13, -12
\r
27856 BFD07664 10FC034C MFC0 K0, SRSCtl
\r
27857 BFD07666 4FF110FC ADDI A3, GP, 20465
\r
27858 BFD07668 4FF1 ADDIU SP, SP, -32
\r
27859 BFD0766A CB67 SW K1, 28(SP)
\r
27860 BFD0766C 00FC036C MFC0 K1, Status
\r
27861 BFD07670 CB46 SW K0, 24(SP)
\r
27862 BFD07672 00FC034D MFC0 K0, Cause
\r
27863 BFD07676 CB65 SW K1, 20(SP)
\r
27864 BFD07678 5040035A SRL K0, K0, 10
\r
27865 BFD0767A 037A5040 ORI V0, ZERO, 890
\r
27866 BFD0767C 7A8C037A INS K1, K0, 10, 6
\r
27867 BFD0767E 03607A8C ADDIUPC A1, 787296
\r
27868 BFD07680 204C0360 INS K1, ZERO, 1, 4
\r
27869 BFD07682 036C204C LWC2 V0, 876(T4)
\r
27870 BFD07684 02FC036C MTC0 K1, Status
\r
27871 BFD07688 C862 SW V1, 8(SP)
\r
27872 BFD0768A C841 SW V0, 4(SP)
\r
27873 BFD0768C 4866 LW V1, 24(SP)
\r
27874 BFD0768E 2DB7 ANDI V1, V1, 0xF
\r
27875 BFD07690 CBC3 SW S8, 12(SP)
\r
27876 BFD07692 0FDD MOVE S8, SP
\r
27877 47: JTVIC_GROUP_EN_CLR->w = (1ul<<1);
\r
27878 BFD07694 BFFF41A2 LUI V0, 0xBFFF
\r
27879 BFD07696 5042BFFF LDC1 F31, 20546(RA)
\r
27880 BFD07698 C50C5042 ORI V0, V0, -15092
\r
27881 BFD0769C ED82 LI V1, 2
\r
27882 BFD0769E E9A0 SW V1, 0(V0)
\r
27884 BFD076A0 0FBE MOVE SP, S8
\r
27885 BFD076A2 4846 LW V0, 24(SP)
\r
27886 BFD076A4 2D27 ANDI V0, V0, 0xF
\r
27887 BFD076A6 4BC3 LW S8, 12(SP)
\r
27888 BFD076A8 4862 LW V1, 8(SP)
\r
27889 BFD076AA 4841 LW V0, 4(SP)
\r
27890 BFD076AC 477C0000 DI ZERO
\r
27891 BFD076B0 18000000 SLL ZERO, ZERO, 3
\r
27892 BFD076B2 4B471800 SB ZERO, 19271(ZERO)
\r
27893 BFD076B4 4B47 LW K0, 28(SP)
\r
27894 BFD076B6 4B65 LW K1, 20(SP)
\r
27895 BFD076B8 02FC034E MTC0 K0, EPC
\r
27896 BFD076BC 4B46 LW K0, 24(SP)
\r
27897 BFD076BE 4C11 ADDIU SP, SP, 32
\r
27898 BFD076C0 12FC034C MTC0 K0, SRSCtl
\r
27899 BFD076C2 03BD12FC ADDI S7, GP, 957
\r
27900 BFD076C4 F17C03BD WRPGPR SP, SP
\r
27901 BFD076C6 036CF17C JALX 0xBDF00DB0
\r
27902 BFD076C8 02FC036C MTC0 K1, Status
\r
27903 BFD076CA 000002FC SLL S7, GP, 0
\r
27904 BFD076CC F37C0000 ERET
\r
27905 BFD076CE 03BDF37C JALX 0xBDF00EF4
\r
27909 52: void __attribute__((weak, interrupt, nomips16))
\r
27910 53: girq09_b0(void)
\r
27912 55: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 0);
\r
27913 56: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 0);
\r
27916 59: void __attribute__((weak, interrupt, nomips16))
\r
27917 60: girq09_b1(void)
\r
27919 62: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 1);
\r
27920 63: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 1);
\r
27923 66: void __attribute__((weak, interrupt, nomips16))
\r
27924 67: girq09_b2(void)
\r
27926 69: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 2);
\r
27927 70: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 2);
\r
27930 73: void __attribute__((weak, interrupt, nomips16))
\r
27931 74: girq09_b3(void)
\r
27933 76: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 3);
\r
27934 77: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 3);
\r
27937 80: void __attribute__((weak, interrupt, nomips16))
\r
27938 81: girq09_b4(void)
\r
27940 83: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 4);
\r
27941 84: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 4);
\r
27944 87: void __attribute__((weak, interrupt, nomips16))
\r
27945 88: girq09_b5(void)
\r
27947 90: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 5);
\r
27948 91: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 5);
\r
27951 94: void __attribute__((weak, interrupt, nomips16))
\r
27952 95: girq09_b6(void)
\r
27954 97: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 6);
\r
27955 98: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 6);
\r
27958 101: void __attribute__((weak, interrupt, nomips16))
\r
27959 102: girq09_b7(void)
\r
27961 104: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 7);
\r
27962 105: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 7);
\r
27965 108: void __attribute__((weak, interrupt, nomips16))
\r
27966 109: girq09_b8(void)
\r
27968 111: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 8);
\r
27969 112: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 8);
\r
27972 115: void __attribute__((weak, interrupt, nomips16))
\r
27973 116: girq09_b9(void)
\r
27975 118: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 9);
\r
27976 119: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 9);
\r
27979 122: void __attribute__((weak, interrupt, nomips16))
\r
27980 123: girq09_b10(void)
\r
27982 125: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 10);
\r
27983 126: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 10);
\r
27986 129: void __attribute__((weak, interrupt, nomips16))
\r
27987 130: girq09_b11(void)
\r
27989 132: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 11);
\r
27990 133: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 11);
\r
27993 136: void __attribute__((weak, interrupt, nomips16))
\r
27994 137: girq09_b12(void)
\r
27996 139: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 12);
\r
27997 140: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 12);
\r
28000 143: void __attribute__((weak, interrupt, nomips16))
\r
28001 144: girq09_b13(void)
\r
28003 146: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 13);
\r
28004 147: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 13);
\r
28007 150: void __attribute__((weak, interrupt, nomips16))
\r
28008 151: girq09_b14(void)
\r
28010 153: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 14);
\r
28011 154: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 14);
\r
28014 157: void __attribute__((weak, interrupt, nomips16))
\r
28015 158: girq09_b15(void)
\r
28017 160: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 15);
\r
28018 161: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 15);
\r
28021 164: void __attribute__((weak, interrupt, nomips16))
\r
28022 165: girq09_b16(void)
\r
28024 167: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 16);
\r
28025 168: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 16);
\r
28028 171: void __attribute__((weak, interrupt, nomips16))
\r
28029 172: girq09_b17(void)
\r
28031 174: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 17);
\r
28032 175: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 17);
\r
28035 178: void __attribute__((weak, interrupt, nomips16))
\r
28036 179: girq09_b18(void)
\r
28038 181: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 18);
\r
28039 182: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 18);
\r
28042 185: void __attribute__((weak, interrupt, nomips16))
\r
28043 186: girq09_b19(void)
\r
28045 188: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 19);
\r
28046 189: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 19);
\r
28049 192: void __attribute__((weak, interrupt, nomips16))
\r
28050 193: girq09_b20(void)
\r
28052 195: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 20);
\r
28053 196: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 20);
\r
28056 199: void __attribute__((weak, interrupt, nomips16))
\r
28057 200: girq09_b21(void)
\r
28059 202: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 21);
\r
28060 203: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 21);
\r
28063 206: void __attribute__((weak, interrupt, nomips16))
\r
28064 207: girq09_b22(void)
\r
28066 209: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 22);
\r
28067 210: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 22);
\r
28070 213: void __attribute__((weak, interrupt, nomips16))
\r
28071 214: girq09_b23(void)
\r
28073 216: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 23);
\r
28074 217: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 23);
\r
28077 220: void __attribute__((weak, interrupt, nomips16))
\r
28078 221: girq09_b24(void)
\r
28080 223: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 24);
\r
28081 224: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 24);
\r
28084 227: void __attribute__((weak, interrupt, nomips16))
\r
28085 228: girq09_b25(void)
\r
28087 230: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 25);
\r
28088 231: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 25);
\r
28091 234: void __attribute__((weak, interrupt, nomips16))
\r
28092 235: girq09_b26(void)
\r
28094 237: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 26);
\r
28095 238: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 26);
\r
28098 241: void __attribute__((weak, interrupt, nomips16))
\r
28099 242: girq09_b27(void)
\r
28101 244: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 27);
\r
28102 245: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 27);
\r
28105 248: void __attribute__((weak, interrupt, nomips16))
\r
28106 249: girq09_b28(void)
\r
28108 251: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 28);
\r
28109 252: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 28);
\r
28112 255: void __attribute__((weak, interrupt, nomips16))
\r
28113 256: girq09_b29(void)
\r
28115 258: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 29);
\r
28116 259: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 29);
\r
28119 262: void __attribute__((weak, interrupt, nomips16))
\r
28120 263: girq09_b30(void)
\r
28122 265: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 30);
\r
28123 266: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 30);
\r
28129 272: /* end girq09.c */
\r
28133 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq08.c ----
\r
28134 1: /*****************************************************************************
\r
28135 2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.
\r
28136 3: * You may use this software and any derivatives exclusively with
\r
28137 4: * Microchip products.
\r
28138 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
28139 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
28140 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
28141 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
28142 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
28143 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
28144 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
28145 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
28146 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
28147 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
28148 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
28149 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
28150 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
28151 18: * OF THESE TERMS.
\r
28152 19: *****************************************************************************/
\r
28154 21: /** @file girq08.c
\r
28155 22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
\r
28157 24: /** @defgroup MEC14xx ISR
\r
28161 28: #include "appcfg.h"
\r
28162 29: #include "platform.h"
\r
28163 30: #include "MEC14xx/mec14xx.h"
\r
28164 31: #include "MEC14xx/mec14xx_girqs.h"
\r
28165 32: #include "MEC14xx/mec14xx_gpio.h"
\r
28166 33: #include "MEC14xx/mec14xx_trace_func.h"
\r
28170 37: #if GIRQ08_DISAGG == 0
\r
28173 40: * Aggregated mode handler, must handle all enabled
\r
28174 41: * GIRQ08 sources.
\r
28176 43: void __attribute__((weak, interrupt, nomips16, section(".girqs")))
\r
28177 44: girq08_isr( void )
\r
28179 BFD075E8 E17C03BD RDPGPR SP, SP
\r
28180 BFD075EC 00FC036E MFC0 K1, EPC
\r
28181 BFD075EE 034C00FC INS A3, GP, 13, -12
\r
28182 BFD075F0 10FC034C MFC0 K0, SRSCtl
\r
28183 BFD075F2 4FF110FC ADDI A3, GP, 20465
\r
28184 BFD075F4 4FF1 ADDIU SP, SP, -32
\r
28185 BFD075F6 CB67 SW K1, 28(SP)
\r
28186 BFD075F8 00FC036C MFC0 K1, Status
\r
28187 BFD075FC CB46 SW K0, 24(SP)
\r
28188 BFD075FE 00FC034D MFC0 K0, Cause
\r
28189 BFD07602 CB65 SW K1, 20(SP)
\r
28190 BFD07604 5040035A SRL K0, K0, 10
\r
28191 BFD07606 037A5040 ORI V0, ZERO, 890
\r
28192 BFD07608 7A8C037A INS K1, K0, 10, 6
\r
28193 BFD0760A 03607A8C ADDIUPC A1, 787296
\r
28194 BFD0760C 204C0360 INS K1, ZERO, 1, 4
\r
28195 BFD0760E 036C204C LWC2 V0, 876(T4)
\r
28196 BFD07610 02FC036C MTC0 K1, Status
\r
28197 BFD07614 C862 SW V1, 8(SP)
\r
28198 BFD07616 C841 SW V0, 4(SP)
\r
28199 BFD07618 4866 LW V1, 24(SP)
\r
28200 BFD0761A 2DB7 ANDI V1, V1, 0xF
\r
28201 BFD0761C CBC3 SW S8, 12(SP)
\r
28202 BFD0761E 0FDD MOVE S8, SP
\r
28203 46: JTVIC_GROUP_EN_CLR->w = (1ul<<0);
\r
28204 BFD07620 BFFF41A2 LUI V0, 0xBFFF
\r
28205 BFD07622 5042BFFF LDC1 F31, 20546(RA)
\r
28206 BFD07624 C50C5042 ORI V0, V0, -15092
\r
28207 BFD07628 ED81 LI V1, 1
\r
28208 BFD0762A E9A0 SW V1, 0(V0)
\r
28210 BFD0762C 0FBE MOVE SP, S8
\r
28211 BFD0762E 4846 LW V0, 24(SP)
\r
28212 BFD07630 2D27 ANDI V0, V0, 0xF
\r
28213 BFD07632 4BC3 LW S8, 12(SP)
\r
28214 BFD07634 4862 LW V1, 8(SP)
\r
28215 BFD07636 4841 LW V0, 4(SP)
\r
28216 BFD07638 477C0000 DI ZERO
\r
28217 BFD0763C 18000000 SLL ZERO, ZERO, 3
\r
28218 BFD0763E 4B471800 SB ZERO, 19271(ZERO)
\r
28219 BFD07640 4B47 LW K0, 28(SP)
\r
28220 BFD07642 4B65 LW K1, 20(SP)
\r
28221 BFD07644 02FC034E MTC0 K0, EPC
\r
28222 BFD07648 4B46 LW K0, 24(SP)
\r
28223 BFD0764A 4C11 ADDIU SP, SP, 32
\r
28224 BFD0764C 12FC034C MTC0 K0, SRSCtl
\r
28225 BFD0764E 03BD12FC ADDI S7, GP, 957
\r
28226 BFD07650 F17C03BD WRPGPR SP, SP
\r
28227 BFD07652 036CF17C JALX 0xBDF00DB0
\r
28228 BFD07654 02FC036C MTC0 K1, Status
\r
28229 BFD07656 000002FC SLL S7, GP, 0
\r
28230 BFD07658 F37C0000 ERET
\r
28231 BFD0765A 03BDF37C JALX 0xBDF00EF4
\r
28236 52: * Disaggregated GIRQ08 subhandlers, one for each
\r
28237 53: * source. Called by assembly language wrapper.
\r
28241 57: void __attribute__((weak, interrupt, nomips16))
\r
28242 58: girq08_b0(void)
\r
28244 60: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 0);
\r
28248 64: void __attribute__((weak, interrupt, nomips16))
\r
28249 65: girq08_b1(void)
\r
28251 67: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 1);
\r
28255 71: void __attribute__((weak, interrupt, nomips16))
\r
28256 72: girq08_b2(void)
\r
28258 74: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 2);
\r
28262 78: void __attribute__((weak, interrupt, nomips16))
\r
28263 79: girq08_b3(void)
\r
28265 81: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 3);
\r
28269 85: void __attribute__((weak, interrupt, nomips16))
\r
28270 86: girq08_b4(void)
\r
28272 88: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 4);
\r
28276 92: void __attribute__((weak, interrupt, nomips16))
\r
28277 93: girq08_b5(void)
\r
28279 95: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 5);
\r
28283 99: void __attribute__((weak, interrupt, nomips16))
\r
28284 100: girq08_b6(void)
\r
28286 102: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 6);
\r
28290 106: void __attribute__((weak, interrupt, nomips16))
\r
28291 107: girq08_b7(void)
\r
28293 109: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 7);
\r
28297 113: void __attribute__((weak, interrupt, nomips16))
\r
28298 114: girq08_b8(void)
\r
28300 116: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 8);
\r
28304 120: void __attribute__((weak, interrupt, nomips16))
\r
28305 121: girq08_b9(void)
\r
28307 123: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 9);
\r
28311 127: void __attribute__((weak, interrupt, nomips16))
\r
28312 128: girq08_b10(void)
\r
28314 130: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 10);
\r
28318 134: void __attribute__((weak, interrupt, nomips16))
\r
28319 135: girq08_b11(void)
\r
28321 137: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 11);
\r
28325 141: void __attribute__((weak, interrupt, nomips16))
\r
28326 142: girq08_b12(void)
\r
28328 144: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 12);
\r
28332 148: void __attribute__((weak, interrupt, nomips16))
\r
28333 149: girq08_b13(void)
\r
28335 151: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 13);
\r
28339 155: void __attribute__((weak, interrupt, nomips16))
\r
28340 156: girq08_b14(void)
\r
28342 158: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 14);
\r
28346 162: void __attribute__((weak, interrupt, nomips16))
\r
28347 163: girq08_b15(void)
\r
28349 165: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 15);
\r
28353 169: void __attribute__((weak, interrupt, nomips16))
\r
28354 170: girq08_b16(void)
\r
28356 172: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 16);
\r
28360 176: void __attribute__((weak, interrupt, nomips16))
\r
28361 177: girq08_b17(void)
\r
28363 179: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 17);
\r
28367 183: void __attribute__((weak, interrupt, nomips16))
\r
28368 184: girq08_b18(void)
\r
28370 186: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 18);
\r
28374 190: void __attribute__((weak, interrupt, nomips16))
\r
28375 191: girq08_b19(void)
\r
28377 193: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 19);
\r
28381 197: void __attribute__((weak, interrupt, nomips16))
\r
28382 198: girq08_b20(void)
\r
28384 200: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 20);
\r
28388 204: void __attribute__((weak, interrupt, nomips16))
\r
28389 205: girq08_b21(void)
\r
28391 207: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 21);
\r
28395 211: void __attribute__((weak, interrupt, nomips16))
\r
28396 212: girq08_b22(void)
\r
28398 214: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 22);
\r
28405 221: /* end girq08.c */
\r
28409 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/exceptions/mplab/general_exception.c
\r
28410 1: /*****************************************************************************
\r
28411 2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.
\r
28412 3: * You may use this software and any derivatives exclusively with
\r
28413 4: * Microchip products.
\r
28414 5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
\r
28415 6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
\r
28416 7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
\r
28417 8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
\r
28418 9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
\r
28419 10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
\r
28420 11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
\r
28421 12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
\r
28422 13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
\r
28423 14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
\r
28424 15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
\r
28425 16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
\r
28426 17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
\r
28427 18: * OF THESE TERMS.
\r
28428 19: *****************************************************************************/
\r
28430 21: /** @file general_exception.c
\r
28431 22: *MEC14xx General Exception Handler
\r
28433 24: /** @defgroup MEC14xx Exceptions
\r
28438 29: #include "appcfg.h"
\r
28439 30: #include "platform.h"
\r
28440 31: #include "MEC14xx/mec14xx.h"
\r
28441 32: #include "MEC14xx/mec14xx_trace_inline.h"
\r
28443 34: typedef struct gen_except_capture
\r
28445 36: uint32_t stack_ptr;
\r
28446 37: uint32_t cp0_status;
\r
28447 38: uint32_t cp0_cause;
\r
28448 39: uint32_t cp0_epc;
\r
28449 40: uint32_t cp0_error_epc;
\r
28450 41: uint32_t cp0_nexc;
\r
28451 42: uint32_t cp0_nepc;
\r
28452 43: uint32_t cp0_badvaddr;
\r
28453 44: uint32_t ahb_err;
\r
28454 45: } GEN_EXCEPT_CAPTURE;
\r
28456 47: GEN_EXCEPT_CAPTURE gexc_cap;
\r
28459 50: __attribute__((nomips16, noreturn)) _general_exception_handler (void)
\r
28461 BFD00460 4FF9 ADDIU SP, SP, -16
\r
28462 BFD00462 CBE3 SW RA, 12(SP)
\r
28463 BFD00464 CBC2 SW S8, 8(SP)
\r
28464 BFD00466 0FDD MOVE S8, SP
\r
28466 53: * MEC14xx Application General Exception handler
\r
28470 57: /* Get current Stack Pointer. Note: this is not SP at
\r
28471 58: * exception. XC32 wraps _general_exception_handler in
\r
28472 59: * assembly code which saves state resulting is a
\r
28473 60: * modified SP. Wrapper allocates 88 bytes for context
\r
28474 61: * save. Original SP = SPcurrent + 88.
\r
28476 63: __asm__ __volatile (
\r
28477 BFD00468 0FFD MOVE RA, SP
\r
28478 BFD0046A 0C00 NOP
\r
28479 BFD0046C 0000FBFE SW RA, 0(S8)
\r
28480 64: "move %0,$sp \n\t"
\r
28484 68: gexc_cap.stack_ptr = e;
\r
28485 BFD00470 BFD241A2 LUI V0, 0xBFD2
\r
28486 BFD00472 FC7EBFD2 LDC1 F30, -898(S2)
\r
28487 BFD00474 0000FC7E LW V1, 0(S8)
\r
28488 BFD00478 8134F862 SW V1, -32460(V0)
\r
28490 70: gexc_cap.cp0_status = _CP0_GET_STATUS();
\r
28491 BFD0047C 00FC006C MFC0 V1, Status
\r
28492 BFD00480 BFD241A2 LUI V0, 0xBFD2
\r
28493 BFD00482 3042BFD2 LDC1 F30, 12354(S2)
\r
28494 BFD00484 81343042 ADDIU V0, V0, -32460
\r
28495 BFD00488 E9A1 SW V1, 4(V0)
\r
28496 71: gexc_cap.cp0_cause = _CP0_GET_CAUSE();
\r
28497 BFD0048A 00FC006D MFC0 V1, Cause
\r
28498 BFD0048E BFD241A2 LUI V0, 0xBFD2
\r
28499 BFD00490 3042BFD2 LDC1 F30, 12354(S2)
\r
28500 BFD00492 81343042 ADDIU V0, V0, -32460
\r
28501 BFD00496 E9A2 SW V1, 8(V0)
\r
28502 72: gexc_cap.cp0_epc = _CP0_GET_EPC();
\r
28503 BFD00498 00FC006E MFC0 V1, EPC
\r
28504 BFD0049C BFD241A2 LUI V0, 0xBFD2
\r
28505 BFD0049E 3042BFD2 LDC1 F30, 12354(S2)
\r
28506 BFD004A0 81343042 ADDIU V0, V0, -32460
\r
28507 BFD004A4 E9A3 SW V1, 12(V0)
\r
28508 73: gexc_cap.cp0_error_epc = _CP0_GET_ERROREPC();
\r
28509 BFD004A6 00FC007E MFC0 V1, ErrorEPC
\r
28510 BFD004AA BFD241A2 LUI V0, 0xBFD2
\r
28511 BFD004AC 3042BFD2 LDC1 F30, 12354(S2)
\r
28512 BFD004AE 81343042 ADDIU V0, V0, -32460
\r
28513 BFD004B2 E9A4 SW V1, 16(V0)
\r
28514 74: gexc_cap.cp0_nexc = _CP0_GET_NESTEDEXC();
\r
28515 BFD004B4 10FC006D MFC0 V1, $13, 2
\r
28516 BFD004B6 41A210FC ADDI A3, GP, 16802
\r
28517 BFD004B8 BFD241A2 LUI V0, 0xBFD2
\r
28518 BFD004BA 3042BFD2 LDC1 F30, 12354(S2)
\r
28519 BFD004BC 81343042 ADDIU V0, V0, -32460
\r
28520 BFD004C0 E9A5 SW V1, 20(V0)
\r
28521 75: gexc_cap.cp0_nepc = _CP0_GET_NESTEDEPC();
\r
28522 BFD004C2 08FC006E MFC0 V1, $14, 1
\r
28523 BFD004C4 08FC LBU S1, 12(A3)
\r
28524 BFD004C6 BFD241A2 LUI V0, 0xBFD2
\r
28525 BFD004C8 3042BFD2 LDC1 F30, 12354(S2)
\r
28526 BFD004CA 81343042 ADDIU V0, V0, -32460
\r
28527 BFD004CE E9A6 SW V1, 24(V0)
\r
28528 76: gexc_cap.cp0_badvaddr = _CP0_GET_BADVADDR();
\r
28529 BFD004D0 00FC0068 MFC0 V1, BadVAddr
\r
28530 BFD004D4 BFD241A2 LUI V0, 0xBFD2
\r
28531 BFD004D6 3042BFD2 LDC1 F30, 12354(S2)
\r
28532 BFD004D8 81343042 ADDIU V0, V0, -32460
\r
28533 BFD004DC E9A7 SW V1, 28(V0)
\r
28535 78: trace0(0, AP3GENEXCEPT, 0, "Application General Exception Handler (BEV=0)");
\r
28536 79: TRACE11(601, AP3GENEXCEPT, 0, "Current SP = 0x%08x",gexc_cap.stack_ptr);
\r
28537 BFD004DE A00041A2 LUI V0, 0xA000
\r
28538 BFD004E2 8C005042 ORI V0, V0, -29696
\r
28539 BFD004E4 8C00 BEQZ S0, 0xBFD004E6
\r
28540 BFD004E6 FFFD3060 ADDIU V1, ZERO, -3
\r
28541 BFD004E8 89A0FFFD LW RA, -30304(SP)
\r
28542 BFD004EA 89A0 SB V1, 0(V0)
\r
28543 BFD004EC A00041A2 LUI V0, 0xA000
\r
28544 BFD004F0 8C005042 ORI V0, V0, -29696
\r
28545 BFD004F2 8C00 BEQZ S0, 0xBFD004F4
\r
28546 BFD004F4 EDD9 LI V1, 89
\r
28547 BFD004F6 89A0 SB V1, 0(V0)
\r
28548 BFD004F8 A00041A2 LUI V0, 0xA000
\r
28549 BFD004FC 8C005042 ORI V0, V0, -29696
\r
28550 BFD004FE 8C00 BEQZ S0, 0xBFD00500
\r
28551 BFD00500 ED82 LI V1, 2
\r
28552 BFD00502 89A0 SB V1, 0(V0)
\r
28553 BFD00504 A00041A2 LUI V0, 0xA000
\r
28554 BFD00508 8C005042 ORI V0, V0, -29696
\r
28555 BFD0050A 8C00 BEQZ S0, 0xBFD0050C
\r
28556 BFD0050C BFD241A3 LUI V1, 0xBFD2
\r
28557 BFD0050E FC63BFD2 LDC1 F30, -925(S2)
\r
28558 BFD00510 8134FC63 LW V1, -32460(V1)
\r
28559 BFD00514 2DBD ANDI V1, V1, 0xFF
\r
28560 BFD00516 89A0 SB V1, 0(V0)
\r
28561 BFD00518 A00041A2 LUI V0, 0xA000
\r
28562 BFD0051C 8C005042 ORI V0, V0, -29696
\r
28563 BFD0051E 8C00 BEQZ S0, 0xBFD00520
\r
28564 BFD00520 BFD241A3 LUI V1, 0xBFD2
\r
28565 BFD00522 FC63BFD2 LDC1 F30, -925(S2)
\r
28566 BFD00524 8134FC63 LW V1, -32460(V1)
\r
28567 BFD00528 25B1 SRL V1, V1, 8
\r
28568 BFD0052A 2DBD ANDI V1, V1, 0xFF
\r
28569 BFD0052C 89A0 SB V1, 0(V0)
\r
28570 BFD0052E A00041A2 LUI V0, 0xA000
\r
28571 BFD00532 8C005042 ORI V0, V0, -29696
\r
28572 BFD00534 8C00 BEQZ S0, 0xBFD00536
\r
28573 BFD00536 BFD241A3 LUI V1, 0xBFD2
\r
28574 BFD00538 FC63BFD2 LDC1 F30, -925(S2)
\r
28575 BFD0053A 8134FC63 LW V1, -32460(V1)
\r
28576 BFD0053E 80400063 SRL V1, V1, 16
\r
28577 BFD00542 2DBD ANDI V1, V1, 0xFF
\r
28578 BFD00544 89A0 SB V1, 0(V0)
\r
28579 BFD00546 A00041A2 LUI V0, 0xA000
\r
28580 BFD0054A 8C005042 ORI V0, V0, -29696
\r
28581 BFD0054C 8C00 BEQZ S0, 0xBFD0054E
\r
28582 BFD0054E BFD241A3 LUI V1, 0xBFD2
\r
28583 BFD00550 FC63BFD2 LDC1 F30, -925(S2)
\r
28584 BFD00552 8134FC63 LW V1, -32460(V1)
\r
28585 BFD00556 C0400063 SRL V1, V1, 24
\r
28586 BFD0055A 2DBD ANDI V1, V1, 0xFF
\r
28587 BFD0055C 89A0 SB V1, 0(V0)
\r
28588 80: TRACE11(602, AP3GENEXCEPT, 0, "CP0 STATUS = 0x%08x",gexc_cap.cp0_status);
\r
28589 BFD0055E A00041A2 LUI V0, 0xA000
\r
28590 BFD00562 8C005042 ORI V0, V0, -29696
\r
28591 BFD00564 8C00 BEQZ S0, 0xBFD00566
\r
28592 BFD00566 FFFD3060 ADDIU V1, ZERO, -3
\r
28593 BFD00568 89A0FFFD LW RA, -30304(SP)
\r
28594 BFD0056A 89A0 SB V1, 0(V0)
\r
28595 BFD0056C A00041A2 LUI V0, 0xA000
\r
28596 BFD00570 8C005042 ORI V0, V0, -29696
\r
28597 BFD00572 8C00 BEQZ S0, 0xBFD00574
\r
28598 BFD00574 EDDA LI V1, 90
\r
28599 BFD00576 89A0 SB V1, 0(V0)
\r
28600 BFD00578 A00041A2 LUI V0, 0xA000
\r
28601 BFD0057C 8C005042 ORI V0, V0, -29696
\r
28602 BFD0057E 8C00 BEQZ S0, 0xBFD00580
\r
28603 BFD00580 ED82 LI V1, 2
\r
28604 BFD00582 89A0 SB V1, 0(V0)
\r
28605 BFD00584 A00041A2 LUI V0, 0xA000
\r
28606 BFD00588 8C005042 ORI V0, V0, -29696
\r
28607 BFD0058A 8C00 BEQZ S0, 0xBFD0058C
\r
28608 BFD0058C BFD241A3 LUI V1, 0xBFD2
\r
28609 BFD0058E 3063BFD2 LDC1 F30, 12387(S2)
\r
28610 BFD00590 81343063 ADDIU V1, V1, -32460
\r
28611 BFD00594 69B1 LW V1, 4(V1)
\r
28612 BFD00596 2DBD ANDI V1, V1, 0xFF
\r
28613 BFD00598 89A0 SB V1, 0(V0)
\r
28614 BFD0059A A00041A2 LUI V0, 0xA000
\r
28615 BFD0059E 8C005042 ORI V0, V0, -29696
\r
28616 BFD005A0 8C00 BEQZ S0, 0xBFD005A2
\r
28617 BFD005A2 BFD241A3 LUI V1, 0xBFD2
\r
28618 BFD005A4 3063BFD2 LDC1 F30, 12387(S2)
\r
28619 BFD005A6 81343063 ADDIU V1, V1, -32460
\r
28620 BFD005AA 69B1 LW V1, 4(V1)
\r
28621 BFD005AC 25B1 SRL V1, V1, 8
\r
28622 BFD005AE 2DBD ANDI V1, V1, 0xFF
\r
28623 BFD005B0 89A0 SB V1, 0(V0)
\r
28624 BFD005B2 A00041A2 LUI V0, 0xA000
\r
28625 BFD005B6 8C005042 ORI V0, V0, -29696
\r
28626 BFD005B8 8C00 BEQZ S0, 0xBFD005BA
\r
28627 BFD005BA BFD241A3 LUI V1, 0xBFD2
\r
28628 BFD005BC 3063BFD2 LDC1 F30, 12387(S2)
\r
28629 BFD005BE 81343063 ADDIU V1, V1, -32460
\r
28630 BFD005C2 69B1 LW V1, 4(V1)
\r
28631 BFD005C4 80400063 SRL V1, V1, 16
\r
28632 BFD005C8 2DBD ANDI V1, V1, 0xFF
\r
28633 BFD005CA 89A0 SB V1, 0(V0)
\r
28634 BFD005CC A00041A2 LUI V0, 0xA000
\r
28635 BFD005D0 8C005042 ORI V0, V0, -29696
\r
28636 BFD005D2 8C00 BEQZ S0, 0xBFD005D4
\r
28637 BFD005D4 BFD241A3 LUI V1, 0xBFD2
\r
28638 BFD005D6 3063BFD2 LDC1 F30, 12387(S2)
\r
28639 BFD005D8 81343063 ADDIU V1, V1, -32460
\r
28640 BFD005DC 69B1 LW V1, 4(V1)
\r
28641 BFD005DE C0400063 SRL V1, V1, 24
\r
28642 BFD005E2 2DBD ANDI V1, V1, 0xFF
\r
28643 BFD005E4 89A0 SB V1, 0(V0)
\r
28644 81: TRACE11(603, AP3GENEXCEPT, 0, "CP0 CAUSE = 0x%08x",gexc_cap.cp0_cause);
\r
28645 BFD005E6 A00041A2 LUI V0, 0xA000
\r
28646 BFD005EA 8C005042 ORI V0, V0, -29696
\r
28647 BFD005EC 8C00 BEQZ S0, 0xBFD005EE
\r
28648 BFD005EE FFFD3060 ADDIU V1, ZERO, -3
\r
28649 BFD005F0 89A0FFFD LW RA, -30304(SP)
\r
28650 BFD005F2 89A0 SB V1, 0(V0)
\r
28651 BFD005F4 A00041A2 LUI V0, 0xA000
\r
28652 BFD005F8 8C005042 ORI V0, V0, -29696
\r
28653 BFD005FA 8C00 BEQZ S0, 0xBFD005FC
\r
28654 BFD005FC EDDB LI V1, 91
\r
28655 BFD005FE 89A0 SB V1, 0(V0)
\r
28656 BFD00600 A00041A2 LUI V0, 0xA000
\r
28657 BFD00604 8C005042 ORI V0, V0, -29696
\r
28658 BFD00606 8C00 BEQZ S0, 0xBFD00608
\r
28659 BFD00608 ED82 LI V1, 2
\r
28660 BFD0060A 89A0 SB V1, 0(V0)
\r
28661 BFD0060C A00041A2 LUI V0, 0xA000
\r
28662 BFD00610 8C005042 ORI V0, V0, -29696
\r
28663 BFD00612 8C00 BEQZ S0, 0xBFD00614
\r
28664 BFD00614 BFD241A3 LUI V1, 0xBFD2
\r
28665 BFD00616 3063BFD2 LDC1 F30, 12387(S2)
\r
28666 BFD00618 81343063 ADDIU V1, V1, -32460
\r
28667 BFD0061C 69B2 LW V1, 8(V1)
\r
28668 BFD0061E 2DBD ANDI V1, V1, 0xFF
\r
28669 BFD00620 89A0 SB V1, 0(V0)
\r
28670 BFD00622 A00041A2 LUI V0, 0xA000
\r
28671 BFD00626 8C005042 ORI V0, V0, -29696
\r
28672 BFD00628 8C00 BEQZ S0, 0xBFD0062A
\r
28673 BFD0062A BFD241A3 LUI V1, 0xBFD2
\r
28674 BFD0062C 3063BFD2 LDC1 F30, 12387(S2)
\r
28675 BFD0062E 81343063 ADDIU V1, V1, -32460
\r
28676 BFD00632 69B2 LW V1, 8(V1)
\r
28677 BFD00634 25B1 SRL V1, V1, 8
\r
28678 BFD00636 2DBD ANDI V1, V1, 0xFF
\r
28679 BFD00638 89A0 SB V1, 0(V0)
\r
28680 BFD0063A A00041A2 LUI V0, 0xA000
\r
28681 BFD0063E 8C005042 ORI V0, V0, -29696
\r
28682 BFD00640 8C00 BEQZ S0, 0xBFD00642
\r
28683 BFD00642 BFD241A3 LUI V1, 0xBFD2
\r
28684 BFD00644 3063BFD2 LDC1 F30, 12387(S2)
\r
28685 BFD00646 81343063 ADDIU V1, V1, -32460
\r
28686 BFD0064A 69B2 LW V1, 8(V1)
\r
28687 BFD0064C 80400063 SRL V1, V1, 16
\r
28688 BFD00650 2DBD ANDI V1, V1, 0xFF
\r
28689 BFD00652 89A0 SB V1, 0(V0)
\r
28690 BFD00654 A00041A2 LUI V0, 0xA000
\r
28691 BFD00658 8C005042 ORI V0, V0, -29696
\r
28692 BFD0065A 8C00 BEQZ S0, 0xBFD0065C
\r
28693 BFD0065C BFD241A3 LUI V1, 0xBFD2
\r
28694 BFD0065E 3063BFD2 LDC1 F30, 12387(S2)
\r
28695 BFD00660 81343063 ADDIU V1, V1, -32460
\r
28696 BFD00664 69B2 LW V1, 8(V1)
\r
28697 BFD00666 C0400063 SRL V1, V1, 24
\r
28698 BFD0066A 2DBD ANDI V1, V1, 0xFF
\r
28699 BFD0066C 89A0 SB V1, 0(V0)
\r
28700 82: TRACE11(604, AP3GENEXCEPT, 0, "CP0 EPC = 0x%08x",gexc_cap.cp0_epc);
\r
28701 BFD0066E A00041A2 LUI V0, 0xA000
\r
28702 BFD00672 8C005042 ORI V0, V0, -29696
\r
28703 BFD00674 8C00 BEQZ S0, 0xBFD00676
\r
28704 BFD00676 FFFD3060 ADDIU V1, ZERO, -3
\r
28705 BFD00678 89A0FFFD LW RA, -30304(SP)
\r
28706 BFD0067A 89A0 SB V1, 0(V0)
\r
28707 BFD0067C A00041A2 LUI V0, 0xA000
\r
28708 BFD00680 8C005042 ORI V0, V0, -29696
\r
28709 BFD00682 8C00 BEQZ S0, 0xBFD00684
\r
28710 BFD00684 EDDC LI V1, 92
\r
28711 BFD00686 89A0 SB V1, 0(V0)
\r
28712 BFD00688 A00041A2 LUI V0, 0xA000
\r
28713 BFD0068C 8C005042 ORI V0, V0, -29696
\r
28714 BFD0068E 8C00 BEQZ S0, 0xBFD00690
\r
28715 BFD00690 ED82 LI V1, 2
\r
28716 BFD00692 89A0 SB V1, 0(V0)
\r
28717 BFD00694 A00041A2 LUI V0, 0xA000
\r
28718 BFD00698 8C005042 ORI V0, V0, -29696
\r
28719 BFD0069A 8C00 BEQZ S0, 0xBFD0069C
\r
28720 BFD0069C BFD241A3 LUI V1, 0xBFD2
\r
28721 BFD0069E 3063BFD2 LDC1 F30, 12387(S2)
\r
28722 BFD006A0 81343063 ADDIU V1, V1, -32460
\r
28723 BFD006A4 69B3 LW V1, 12(V1)
\r
28724 BFD006A6 2DBD ANDI V1, V1, 0xFF
\r
28725 BFD006A8 89A0 SB V1, 0(V0)
\r
28726 BFD006AA A00041A2 LUI V0, 0xA000
\r
28727 BFD006AE 8C005042 ORI V0, V0, -29696
\r
28728 BFD006B0 8C00 BEQZ S0, 0xBFD006B2
\r
28729 BFD006B2 BFD241A3 LUI V1, 0xBFD2
\r
28730 BFD006B4 3063BFD2 LDC1 F30, 12387(S2)
\r
28731 BFD006B6 81343063 ADDIU V1, V1, -32460
\r
28732 BFD006BA 69B3 LW V1, 12(V1)
\r
28733 BFD006BC 25B1 SRL V1, V1, 8
\r
28734 BFD006BE 2DBD ANDI V1, V1, 0xFF
\r
28735 BFD006C0 89A0 SB V1, 0(V0)
\r
28736 BFD006C2 A00041A2 LUI V0, 0xA000
\r
28737 BFD006C6 8C005042 ORI V0, V0, -29696
\r
28738 BFD006C8 8C00 BEQZ S0, 0xBFD006CA
\r
28739 BFD006CA BFD241A3 LUI V1, 0xBFD2
\r
28740 BFD006CC 3063BFD2 LDC1 F30, 12387(S2)
\r
28741 BFD006CE 81343063 ADDIU V1, V1, -32460
\r
28742 BFD006D2 69B3 LW V1, 12(V1)
\r
28743 BFD006D4 80400063 SRL V1, V1, 16
\r
28744 BFD006D8 2DBD ANDI V1, V1, 0xFF
\r
28745 BFD006DA 89A0 SB V1, 0(V0)
\r
28746 BFD006DC A00041A2 LUI V0, 0xA000
\r
28747 BFD006E0 8C005042 ORI V0, V0, -29696
\r
28748 BFD006E2 8C00 BEQZ S0, 0xBFD006E4
\r
28749 BFD006E4 BFD241A3 LUI V1, 0xBFD2
\r
28750 BFD006E6 3063BFD2 LDC1 F30, 12387(S2)
\r
28751 BFD006E8 81343063 ADDIU V1, V1, -32460
\r
28752 BFD006EC 69B3 LW V1, 12(V1)
\r
28753 BFD006EE C0400063 SRL V1, V1, 24
\r
28754 BFD006F2 2DBD ANDI V1, V1, 0xFF
\r
28755 BFD006F4 89A0 SB V1, 0(V0)
\r
28756 83: TRACE11(605, AP3GENEXCEPT, 0, "CP0 ERROREPC = 0x%08x",gexc_cap.cp0_error_epc);
\r
28757 BFD006F6 A00041A2 LUI V0, 0xA000
\r
28758 BFD006FA 8C005042 ORI V0, V0, -29696
\r
28759 BFD006FC 8C00 BEQZ S0, 0xBFD006FE
\r
28760 BFD006FE FFFD3060 ADDIU V1, ZERO, -3
\r
28761 BFD00700 89A0FFFD LW RA, -30304(SP)
\r
28762 BFD00702 89A0 SB V1, 0(V0)
\r
28763 BFD00704 A00041A2 LUI V0, 0xA000
\r
28764 BFD00708 8C005042 ORI V0, V0, -29696
\r
28765 BFD0070A 8C00 BEQZ S0, 0xBFD0070C
\r
28766 BFD0070C EDDD LI V1, 93
\r
28767 BFD0070E 89A0 SB V1, 0(V0)
\r
28768 BFD00710 A00041A2 LUI V0, 0xA000
\r
28769 BFD00714 8C005042 ORI V0, V0, -29696
\r
28770 BFD00716 8C00 BEQZ S0, 0xBFD00718
\r
28771 BFD00718 ED82 LI V1, 2
\r
28772 BFD0071A 89A0 SB V1, 0(V0)
\r
28773 BFD0071C A00041A2 LUI V0, 0xA000
\r
28774 BFD00720 8C005042 ORI V0, V0, -29696
\r
28775 BFD00722 8C00 BEQZ S0, 0xBFD00724
\r
28776 BFD00724 BFD241A3 LUI V1, 0xBFD2
\r
28777 BFD00726 3063BFD2 LDC1 F30, 12387(S2)
\r
28778 BFD00728 81343063 ADDIU V1, V1, -32460
\r
28779 BFD0072C 69B4 LW V1, 16(V1)
\r
28780 BFD0072E 2DBD ANDI V1, V1, 0xFF
\r
28781 BFD00730 89A0 SB V1, 0(V0)
\r
28782 BFD00732 A00041A2 LUI V0, 0xA000
\r
28783 BFD00736 8C005042 ORI V0, V0, -29696
\r
28784 BFD00738 8C00 BEQZ S0, 0xBFD0073A
\r
28785 BFD0073A BFD241A3 LUI V1, 0xBFD2
\r
28786 BFD0073C 3063BFD2 LDC1 F30, 12387(S2)
\r
28787 BFD0073E 81343063 ADDIU V1, V1, -32460
\r
28788 BFD00742 69B4 LW V1, 16(V1)
\r
28789 BFD00744 25B1 SRL V1, V1, 8
\r
28790 BFD00746 2DBD ANDI V1, V1, 0xFF
\r
28791 BFD00748 89A0 SB V1, 0(V0)
\r
28792 BFD0074A A00041A2 LUI V0, 0xA000
\r
28793 BFD0074E 8C005042 ORI V0, V0, -29696
\r
28794 BFD00750 8C00 BEQZ S0, 0xBFD00752
\r
28795 BFD00752 BFD241A3 LUI V1, 0xBFD2
\r
28796 BFD00754 3063BFD2 LDC1 F30, 12387(S2)
\r
28797 BFD00756 81343063 ADDIU V1, V1, -32460
\r
28798 BFD0075A 69B4 LW V1, 16(V1)
\r
28799 BFD0075C 80400063 SRL V1, V1, 16
\r
28800 BFD00760 2DBD ANDI V1, V1, 0xFF
\r
28801 BFD00762 89A0 SB V1, 0(V0)
\r
28802 BFD00764 A00041A2 LUI V0, 0xA000
\r
28803 BFD00768 8C005042 ORI V0, V0, -29696
\r
28804 BFD0076A 8C00 BEQZ S0, 0xBFD0076C
\r
28805 BFD0076C BFD241A3 LUI V1, 0xBFD2
\r
28806 BFD0076E 3063BFD2 LDC1 F30, 12387(S2)
\r
28807 BFD00770 81343063 ADDIU V1, V1, -32460
\r
28808 BFD00774 69B4 LW V1, 16(V1)
\r
28809 BFD00776 C0400063 SRL V1, V1, 24
\r
28810 BFD0077A 2DBD ANDI V1, V1, 0xFF
\r
28811 BFD0077C 89A0 SB V1, 0(V0)
\r
28812 84: TRACE11(606, AP3GENEXCEPT, 0, "CP0 NEXC = 0x%08x",gexc_cap.cp0_nexc);
\r
28813 BFD0077E A00041A2 LUI V0, 0xA000
\r
28814 BFD00782 8C005042 ORI V0, V0, -29696
\r
28815 BFD00784 8C00 BEQZ S0, 0xBFD00786
\r
28816 BFD00786 FFFD3060 ADDIU V1, ZERO, -3
\r
28817 BFD00788 89A0FFFD LW RA, -30304(SP)
\r
28818 BFD0078A 89A0 SB V1, 0(V0)
\r
28819 BFD0078C A00041A2 LUI V0, 0xA000
\r
28820 BFD00790 8C005042 ORI V0, V0, -29696
\r
28821 BFD00792 8C00 BEQZ S0, 0xBFD00794
\r
28822 BFD00794 EDDE LI V1, 94
\r
28823 BFD00796 89A0 SB V1, 0(V0)
\r
28824 BFD00798 A00041A2 LUI V0, 0xA000
\r
28825 BFD0079C 8C005042 ORI V0, V0, -29696
\r
28826 BFD0079E 8C00 BEQZ S0, 0xBFD007A0
\r
28827 BFD007A0 ED82 LI V1, 2
\r
28828 BFD007A2 89A0 SB V1, 0(V0)
\r
28829 BFD007A4 A00041A2 LUI V0, 0xA000
\r
28830 BFD007A8 8C005042 ORI V0, V0, -29696
\r
28831 BFD007AA 8C00 BEQZ S0, 0xBFD007AC
\r
28832 BFD007AC BFD241A3 LUI V1, 0xBFD2
\r
28833 BFD007AE 3063BFD2 LDC1 F30, 12387(S2)
\r
28834 BFD007B0 81343063 ADDIU V1, V1, -32460
\r
28835 BFD007B4 69B5 LW V1, 20(V1)
\r
28836 BFD007B6 2DBD ANDI V1, V1, 0xFF
\r
28837 BFD007B8 89A0 SB V1, 0(V0)
\r
28838 BFD007BA A00041A2 LUI V0, 0xA000
\r
28839 BFD007BE 8C005042 ORI V0, V0, -29696
\r
28840 BFD007C0 8C00 BEQZ S0, 0xBFD007C2
\r
28841 BFD007C2 BFD241A3 LUI V1, 0xBFD2
\r
28842 BFD007C4 3063BFD2 LDC1 F30, 12387(S2)
\r
28843 BFD007C6 81343063 ADDIU V1, V1, -32460
\r
28844 BFD007CA 69B5 LW V1, 20(V1)
\r
28845 BFD007CC 25B1 SRL V1, V1, 8
\r
28846 BFD007CE 2DBD ANDI V1, V1, 0xFF
\r
28847 BFD007D0 89A0 SB V1, 0(V0)
\r
28848 BFD007D2 A00041A2 LUI V0, 0xA000
\r
28849 BFD007D6 8C005042 ORI V0, V0, -29696
\r
28850 BFD007D8 8C00 BEQZ S0, 0xBFD007DA
\r
28851 BFD007DA BFD241A3 LUI V1, 0xBFD2
\r
28852 BFD007DC 3063BFD2 LDC1 F30, 12387(S2)
\r
28853 BFD007DE 81343063 ADDIU V1, V1, -32460
\r
28854 BFD007E2 69B5 LW V1, 20(V1)
\r
28855 BFD007E4 80400063 SRL V1, V1, 16
\r
28856 BFD007E8 2DBD ANDI V1, V1, 0xFF
\r
28857 BFD007EA 89A0 SB V1, 0(V0)
\r
28858 BFD007EC A00041A2 LUI V0, 0xA000
\r
28859 BFD007F0 8C005042 ORI V0, V0, -29696
\r
28860 BFD007F2 8C00 BEQZ S0, 0xBFD007F4
\r
28861 BFD007F4 BFD241A3 LUI V1, 0xBFD2
\r
28862 BFD007F6 3063BFD2 LDC1 F30, 12387(S2)
\r
28863 BFD007F8 81343063 ADDIU V1, V1, -32460
\r
28864 BFD007FC 69B5 LW V1, 20(V1)
\r
28865 BFD007FE C0400063 SRL V1, V1, 24
\r
28866 BFD00802 2DBD ANDI V1, V1, 0xFF
\r
28867 BFD00804 89A0 SB V1, 0(V0)
\r
28868 85: TRACE11(607, AP3GENEXCEPT, 0, "CP0 NEPC = 0x%08x",gexc_cap.cp0_nepc);
\r
28869 BFD00806 A00041A2 LUI V0, 0xA000
\r
28870 BFD0080A 8C005042 ORI V0, V0, -29696
\r
28871 BFD0080C 8C00 BEQZ S0, 0xBFD0080E
\r
28872 BFD0080E FFFD3060 ADDIU V1, ZERO, -3
\r
28873 BFD00810 89A0FFFD LW RA, -30304(SP)
\r
28874 BFD00812 89A0 SB V1, 0(V0)
\r
28875 BFD00814 A00041A2 LUI V0, 0xA000
\r
28876 BFD00818 8C005042 ORI V0, V0, -29696
\r
28877 BFD0081A 8C00 BEQZ S0, 0xBFD0081C
\r
28878 BFD0081C EDDF LI V1, 95
\r
28879 BFD0081E 89A0 SB V1, 0(V0)
\r
28880 BFD00820 A00041A2 LUI V0, 0xA000
\r
28881 BFD00824 8C005042 ORI V0, V0, -29696
\r
28882 BFD00826 8C00 BEQZ S0, 0xBFD00828
\r
28883 BFD00828 ED82 LI V1, 2
\r
28884 BFD0082A 89A0 SB V1, 0(V0)
\r
28885 BFD0082C A00041A2 LUI V0, 0xA000
\r
28886 BFD00830 8C005042 ORI V0, V0, -29696
\r
28887 BFD00832 8C00 BEQZ S0, 0xBFD00834
\r
28888 BFD00834 BFD241A3 LUI V1, 0xBFD2
\r
28889 BFD00836 3063BFD2 LDC1 F30, 12387(S2)
\r
28890 BFD00838 81343063 ADDIU V1, V1, -32460
\r
28891 BFD0083C 69B6 LW V1, 24(V1)
\r
28892 BFD0083E 2DBD ANDI V1, V1, 0xFF
\r
28893 BFD00840 89A0 SB V1, 0(V0)
\r
28894 BFD00842 A00041A2 LUI V0, 0xA000
\r
28895 BFD00846 8C005042 ORI V0, V0, -29696
\r
28896 BFD00848 8C00 BEQZ S0, 0xBFD0084A
\r
28897 BFD0084A BFD241A3 LUI V1, 0xBFD2
\r
28898 BFD0084C 3063BFD2 LDC1 F30, 12387(S2)
\r
28899 BFD0084E 81343063 ADDIU V1, V1, -32460
\r
28900 BFD00852 69B6 LW V1, 24(V1)
\r
28901 BFD00854 25B1 SRL V1, V1, 8
\r
28902 BFD00856 2DBD ANDI V1, V1, 0xFF
\r
28903 BFD00858 89A0 SB V1, 0(V0)
\r
28904 BFD0085A A00041A2 LUI V0, 0xA000
\r
28905 BFD0085E 8C005042 ORI V0, V0, -29696
\r
28906 BFD00860 8C00 BEQZ S0, 0xBFD00862
\r
28907 BFD00862 BFD241A3 LUI V1, 0xBFD2
\r
28908 BFD00864 3063BFD2 LDC1 F30, 12387(S2)
\r
28909 BFD00866 81343063 ADDIU V1, V1, -32460
\r
28910 BFD0086A 69B6 LW V1, 24(V1)
\r
28911 BFD0086C 80400063 SRL V1, V1, 16
\r
28912 BFD00870 2DBD ANDI V1, V1, 0xFF
\r
28913 BFD00872 89A0 SB V1, 0(V0)
\r
28914 BFD00874 A00041A2 LUI V0, 0xA000
\r
28915 BFD00878 8C005042 ORI V0, V0, -29696
\r
28916 BFD0087A 8C00 BEQZ S0, 0xBFD0087C
\r
28917 BFD0087C BFD241A3 LUI V1, 0xBFD2
\r
28918 BFD0087E 3063BFD2 LDC1 F30, 12387(S2)
\r
28919 BFD00880 81343063 ADDIU V1, V1, -32460
\r
28920 BFD00884 69B6 LW V1, 24(V1)
\r
28921 BFD00886 C0400063 SRL V1, V1, 24
\r
28922 BFD0088A 2DBD ANDI V1, V1, 0xFF
\r
28923 BFD0088C 89A0 SB V1, 0(V0)
\r
28924 86: TRACE11(608, AP3GENEXCEPT, 0, "CP0 BADVADDR = 0x%08x",gexc_cap.cp0_badvaddr);
\r
28925 BFD0088E A00041A2 LUI V0, 0xA000
\r
28926 BFD00892 8C005042 ORI V0, V0, -29696
\r
28927 BFD00894 8C00 BEQZ S0, 0xBFD00896
\r
28928 BFD00896 FFFD3060 ADDIU V1, ZERO, -3
\r
28929 BFD00898 89A0FFFD LW RA, -30304(SP)
\r
28930 BFD0089A 89A0 SB V1, 0(V0)
\r
28931 BFD0089C A00041A2 LUI V0, 0xA000
\r
28932 BFD008A0 8C005042 ORI V0, V0, -29696
\r
28933 BFD008A2 8C00 BEQZ S0, 0xBFD008A4
\r
28934 BFD008A4 EDE0 LI V1, 96
\r
28935 BFD008A6 89A0 SB V1, 0(V0)
\r
28936 BFD008A8 A00041A2 LUI V0, 0xA000
\r
28937 BFD008AC 8C005042 ORI V0, V0, -29696
\r
28938 BFD008AE 8C00 BEQZ S0, 0xBFD008B0
\r
28939 BFD008B0 ED82 LI V1, 2
\r
28940 BFD008B2 89A0 SB V1, 0(V0)
\r
28941 BFD008B4 A00041A2 LUI V0, 0xA000
\r
28942 BFD008B8 8C005042 ORI V0, V0, -29696
\r
28943 BFD008BA 8C00 BEQZ S0, 0xBFD008BC
\r
28944 BFD008BC BFD241A3 LUI V1, 0xBFD2
\r
28945 BFD008BE 3063BFD2 LDC1 F30, 12387(S2)
\r
28946 BFD008C0 81343063 ADDIU V1, V1, -32460
\r
28947 BFD008C4 69B7 LW V1, 28(V1)
\r
28948 BFD008C6 2DBD ANDI V1, V1, 0xFF
\r
28949 BFD008C8 89A0 SB V1, 0(V0)
\r
28950 BFD008CA A00041A2 LUI V0, 0xA000
\r
28951 BFD008CE 8C005042 ORI V0, V0, -29696
\r
28952 BFD008D0 8C00 BEQZ S0, 0xBFD008D2
\r
28953 BFD008D2 BFD241A3 LUI V1, 0xBFD2
\r
28954 BFD008D4 3063BFD2 LDC1 F30, 12387(S2)
\r
28955 BFD008D6 81343063 ADDIU V1, V1, -32460
\r
28956 BFD008DA 69B7 LW V1, 28(V1)
\r
28957 BFD008DC 25B1 SRL V1, V1, 8
\r
28958 BFD008DE 2DBD ANDI V1, V1, 0xFF
\r
28959 BFD008E0 89A0 SB V1, 0(V0)
\r
28960 BFD008E2 A00041A2 LUI V0, 0xA000
\r
28961 BFD008E6 8C005042 ORI V0, V0, -29696
\r
28962 BFD008E8 8C00 BEQZ S0, 0xBFD008EA
\r
28963 BFD008EA BFD241A3 LUI V1, 0xBFD2
\r
28964 BFD008EC 3063BFD2 LDC1 F30, 12387(S2)
\r
28965 BFD008EE 81343063 ADDIU V1, V1, -32460
\r
28966 BFD008F2 69B7 LW V1, 28(V1)
\r
28967 BFD008F4 80400063 SRL V1, V1, 16
\r
28968 BFD008F8 2DBD ANDI V1, V1, 0xFF
\r
28969 BFD008FA 89A0 SB V1, 0(V0)
\r
28970 BFD008FC A00041A2 LUI V0, 0xA000
\r
28971 BFD00900 8C005042 ORI V0, V0, -29696
\r
28972 BFD00902 8C00 BEQZ S0, 0xBFD00904
\r
28973 BFD00904 BFD241A3 LUI V1, 0xBFD2
\r
28974 BFD00906 3063BFD2 LDC1 F30, 12387(S2)
\r
28975 BFD00908 81343063 ADDIU V1, V1, -32460
\r
28976 BFD0090C 69B7 LW V1, 28(V1)
\r
28977 BFD0090E C0400063 SRL V1, V1, 24
\r
28978 BFD00912 2DBD ANDI V1, V1, 0xFF
\r
28979 BFD00914 89A0 SB V1, 0(V0)
\r
28982 89: __asm__ __volatile ("%(ssnop%)" : :);
\r
28983 BFD00916 08000000 SSNOP
\r
28984 BFD00918 0800 LBU S0, 0(S0)
\r
28986 BFD0091A CFFD B 0xBFD00916
\r
28987 BFD0091C 0C00 NOP
\r
28991 94: /* end general_exception.c */
\r
28995 --- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/main.c -------------------------
\r
28996 1: #warning configTIMERS_DISAGGREGATED_ISRS and configCPU_DISAGGREGATED_ISRS need documenting.
\r
28999 4: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
29000 5: All rights reserved
\r
29002 7: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
29004 9: This file is part of the FreeRTOS distribution.
\r
29006 11: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
29007 12: the terms of the GNU General Public License (version 2) as published by the
\r
29008 13: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
29010 15: ***************************************************************************
\r
29011 16: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
29012 17: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
29013 18: >>! obliged to provide the source code for proprietary components !<<
\r
29014 19: >>! outside of the FreeRTOS kernel. !<<
\r
29015 20: ***************************************************************************
\r
29017 22: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
29018 23: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
29019 24: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
29020 25: link: http://www.freertos.org/a00114.html
\r
29022 27: ***************************************************************************
\r
29024 29: * FreeRTOS provides completely free yet professionally developed, *
\r
29025 30: * robust, strictly quality controlled, supported, and cross *
\r
29026 31: * platform software that is more than just the market leader, it *
\r
29027 32: * is the industry's de facto standard. *
\r
29029 34: * Help yourself get started quickly while simultaneously helping *
\r
29030 35: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
29031 36: * tutorial book, reference manual, or both: *
\r
29032 37: * http://www.FreeRTOS.org/Documentation *
\r
29034 39: ***************************************************************************
\r
29036 41: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
29037 42: the FAQ page "My application does not run, what could be wrong?". Have you
\r
29038 43: defined configASSERT()?
\r
29040 45: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
29041 46: embedded software for free we request you assist our global community by
\r
29042 47: participating in the support forum.
\r
29044 49: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
29045 50: be as productive as possible as early as possible. Now you can receive
\r
29046 51: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
29047 52: Ltd, and the world's leading authority on the world's leading RTOS.
\r
29049 54: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
29050 55: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
29051 56: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
29053 58: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
29054 59: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
29056 61: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
29057 62: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
29058 63: licenses offer ticketed support, indemnification and commercial middleware.
\r
29060 65: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
29061 66: engineered and independently SIL3 certified version for use in safety and
\r
29062 67: mission critical applications that require provable dependability.
\r
29064 69: 1 tab == 4 spaces!
\r
29067 72: /******************************************************************************
\r
29068 73: * This project only provides a simple blinky demonstration.
\r
29070 75: * main() creates one queue, two tasks, and one software timer. It then starts
\r
29071 76: * the scheduler.
\r
29073 78: * The Blinky Software Timer:
\r
29074 79: * This demonstrates an auto-reload software timer. The timer callback function
\r
29075 80: * does nothing but toggle an LED.
\r
29077 82: * The Queue Send Task:
\r
29078 83: * The queue send task is implemented by prvQueueSendTask(). It sends the value
\r
29079 84: * 100 to the queue every 200 milliseconds.
\r
29081 86: * The Queue Receive Task:
\r
29082 87: * The queue receive task is implemented by prvQueueReceiveTask().
\r
29083 88: * prvQueueReceiveTask() repeatedly blocks on attempts to read from the queue,
\r
29084 89: * toggling an LED each time data is received. The queue send task sends data
\r
29085 90: * to the queue every 200 milliseconds, so the LED will toggle every 200
\r
29086 91: * milliseconds.
\r
29089 94: /* Kernel includes. */
\r
29090 95: #include "FreeRTOS.h"
\r
29091 96: #include "task.h"
\r
29092 97: #include "queue.h"
\r
29093 98: #include "timers.h"
\r
29095 100: /* Target includes. */
\r
29096 101: #include "appcfg.h"
\r
29097 102: #include "MEC14xx/mec14xx.h"
\r
29098 103: #include "MEC14xx/mec14xx_jtvic.h"
\r
29099 104: #include "MEC14xx/mec14xx_bbled.h"
\r
29100 105: #include "MEC14xx/mec14xx_girqs.h"
\r
29102 107: /* Priorities at which the tasks are created. */
\r
29103 108: #define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
\r
29104 109: #define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
\r
29106 111: /* The rate at which data is sent to the queue. The 200ms value is converted
\r
29107 112: to ticks using the pdMS_TO_TICKS() macro. */
\r
29108 113: #define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200UL ) )
\r
29110 115: /* The number of items the queue can hold. This is 1 as the receive task
\r
29111 116: will remove items as they are added, meaning the send task should always find
\r
29112 117: the queue empty. */
\r
29113 118: #define mainQUEUE_LENGTH ( 1 )
\r
29115 120: /* Values passed to the two tasks just to check the task parameter
\r
29116 121: functionality. */
\r
29117 122: #define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
\r
29118 123: #define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
\r
29120 125: /* The period of the software timer. The period is specified in ms and
\r
29121 126: converted to ticks using the pdMS_TO_TICKS() macro. */
\r
29122 127: #define mainBLINKY_TIMER_PERIOD ( pdMS_TO_TICKS( 50UL ) )
\r
29124 129: /* The LED used by the communicating tasks and the timer respectively. */
\r
29125 130: #define mainTASKS_LED ( LED0_ID )
\r
29126 131: #define mainTIMER_LED ( LED1_ID )
\r
29129 134: #define mainDONT_BLOCK ( 0 )
\r
29132 137: /*-----------------------------------------------------------*/
\r
29135 140: * The tasks as described in the comments at the top of this file.
\r
29137 142: static void prvQueueReceiveTask( void *pvParameters );
\r
29138 143: static void prvQueueSendTask( void *pvParameters );
\r
29141 146: * The callback function for the software timer, as described at the top of this
\r
29144 149: static void prvBlinkyTimerCallback( TimerHandle_t xTimer );
\r
29147 152: * Performs any hardware setup necessary.
\r
29149 154: static void prvSetupHardware( void );
\r
29152 157: * Add some thread safety to the LED toggle function.
\r
29154 159: static void prvToggleLED( uint8_t ucLED );
\r
29156 161: /*-----------------------------------------------------------*/
\r
29158 163: /* The queue used by both tasks. */
\r
29159 164: static QueueHandle_t xQueue = NULL;
\r
29161 166: /*-----------------------------------------------------------*/
\r
29163 168: int main( void )
\r
29165 BFD096C0 4FF1 ADDIU SP, SP, -32
\r
29166 BFD096C2 CBE7 SW RA, 28(SP)
\r
29167 BFD096C4 CBC6 SW S8, 24(SP)
\r
29168 BFD096C6 0FDD MOVE S8, SP
\r
29169 170: TimerHandle_t xTimer;
\r
29171 172: /* Perform any hardware initialisation necessary. */
\r
29172 173: //prvSetupHardware();
\r
29174 175: __asm volatile( "di" );
\r
29175 BFD096C8 477C0000 DI ZERO
\r
29179 179: volatile uint32_t ulx = 0;
\r
29180 BFD096CC 0010F81E SW ZERO, 16(S8)
\r
29184 183: for( ulx = 0; ulx < 0x1fff; ulx++ )
\r
29185 BFD096D0 CC0A B 0xBFD096E6
\r
29186 BFD096D2 0010F81E SW ZERO, 16(S8)
\r
29187 BFD096D4 0C000010 SLL ZERO, S0, 1
\r
29188 BFD096DC 0010FC5E LW V0, 16(S8)
\r
29189 BFD096E0 6D20 ADDIU V0, V0, 1
\r
29190 BFD096E2 0010F85E SW V0, 16(S8)
\r
29191 BFD096E6 0010FC5E LW V0, 16(S8)
\r
29192 BFD096EA 1FFFB042 SLTIU V0, V0, 8191
\r
29193 BFD096EC 40A21FFF LB RA, 16546(RA)
\r
29194 BFD096EE FFF240A2 BNEZC V0, 0xBFD096D6
\r
29195 BFD096F0 77E8FFF2 LW RA, 30696(S2)
\r
29197 185: __asm volatile( "NOP" );
\r
29198 BFD096D6 0C00 NOP
\r
29199 186: __asm volatile( "NOP" );
\r
29200 BFD096D8 0C00 NOP
\r
29201 187: __asm volatile( "NOP" );
\r
29202 BFD096DA 0C00 NOP
\r
29205 190: led_out_toggle( 0 );
\r
29206 BFD096F2 42D477E8 JALS led_out_toggle
\r
29207 BFD096F6 0C80 MOVE A0, ZERO
\r
29209 BFD096F8 CFEB B 0xBFD096D0
\r
29210 BFD096FA 0C00 NOP
\r
29215 196: /* Create the queue. */
\r
29216 197: xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
\r
29217 198: configASSERT( xQueue );
\r
29219 200: if( xQueue != NULL )
\r
29221 202: /* Create the two tasks as described in the comments at the top of this
\r
29223 204: xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
\r
29224 205: "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
\r
29225 206: configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
\r
29226 207: ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
\r
29227 208: mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
\r
29228 209: NULL ); /* The task handle is not required, so NULL is passed. */
\r
29230 211: xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
\r
29233 214: /* Create the blinky software timer as described at the top of this file. */
\r
29234 215: xTimer = xTimerCreate( "Blinky", /* A text name, purely to help debugging. */
\r
29235 216: ( mainBLINKY_TIMER_PERIOD ),/* The timer period. */
\r
29236 217: pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
\r
29237 218: ( void * ) 0, /* The ID is not used, so can be set to anything. */
\r
29238 219: prvBlinkyTimerCallback ); /* The callback function that inspects the status of all the other tasks. */
\r
29239 220: configASSERT( xTimer );
\r
29241 222: if( xTimer != NULL )
\r
29243 224: xTimerStart( xTimer, mainDONT_BLOCK );
\r
29246 227: /* Start the tasks and timer running. */
\r
29247 228: vTaskStartScheduler();
\r
29250 231: /* If all is well, the scheduler will now be running, and the following
\r
29251 232: line will never be reached. If the following line does execute, then
\r
29252 233: there was insufficient FreeRTOS heap memory available for the idle and/or
\r
29253 234: timer tasks to be created. See the memory management section on the
\r
29254 235: FreeRTOS web site for more details. http://www.freertos.org/a00111.html */
\r
29257 238: /*-----------------------------------------------------------*/
\r
29259 240: static void prvQueueSendTask( void *pvParameters )
\r
29261 BFD07E34 4FF1 ADDIU SP, SP, -32
\r
29262 BFD07E36 CBE7 SW RA, 28(SP)
\r
29263 BFD07E38 CBC6 SW S8, 24(SP)
\r
29264 BFD07E3A 0FDD MOVE S8, SP
\r
29265 BFD07E3C 0020F89E SW A0, 32(S8)
\r
29266 242: TickType_t xNextWakeTime;
\r
29267 243: const unsigned long ulValueToSend = 100UL;
\r
29268 BFD07E40 ED64 LI V0, 100
\r
29269 BFD07E42 0014F85E SW V0, 20(S8)
\r
29271 245: /* Remove compiler warnigns in the case that configASSERT() is not dfined. */
\r
29272 246: ( void ) pvParameters;
\r
29274 248: /* Check the task parameter is as expected. */
\r
29275 249: configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
\r
29276 BFD07E46 0020FC7E LW V1, 32(S8)
\r
29277 BFD07E48 30400020 SRL AT, ZERO, 6
\r
29278 BFD07E4A 11113040 ADDIU V0, ZERO, 4369
\r
29279 BFD07E4C 94431111 ADDI T0, S1, -27581
\r
29280 BFD07E4E 000A9443 BEQ V1, V0, 0xBFD07E66
\r
29281 BFD07E50 0C00000A SLL ZERO, T2, 1
\r
29282 BFD07E52 0C00 NOP
\r
29283 BFD07E54 BFD141A2 LUI V0, 0xBFD1
\r
29284 BFD07E56 3082BFD1 LDC1 F30, 12418(S1)
\r
29285 BFD07E58 9EF43082 ADDIU A0, V0, -24844
\r
29286 BFD07E5A 30A09EF4 LWC1 F23, 12448(S4)
\r
29287 BFD07E5C 00F930A0 ADDIU A1, ZERO, 249
\r
29288 BFD07E60 4B7E77E8 JALS vAssertCalled
\r
29289 BFD07E62 4B7E LW K1, 120(SP)
\r
29290 BFD07E64 0C00 NOP
\r
29292 251: /* Initialise xNextWakeTime - this only needs to be done once. */
\r
29293 252: xNextWakeTime = xTaskGetTickCount();
\r
29294 BFD07E66 4CCA77E8 JALS xTaskGetTickCount
\r
29295 BFD07E68 4CCA ADDIU A2, A2, 5
\r
29296 BFD07E6A 0C00 NOP
\r
29297 BFD07E6C 0010F85E SW V0, 16(S8)
\r
29301 256: /* Place this task in the blocked state until it is time to run again.
\r
29302 257: The block time is specified in ticks, the constant used converts ticks
\r
29303 258: to ms. While in the Blocked state this task will not consume any CPU
\r
29305 260: vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
\r
29306 BFD07E70 0010305E ADDIU V0, S8, 16
\r
29307 BFD07E74 0C82 MOVE A0, V0
\r
29308 BFD07E76 00C830A0 ADDIU A1, ZERO, 200
\r
29309 BFD07E7A 000477E8 JALS vTaskDelayUntil
\r
29310 BFD07E7C 0C000004 SLL ZERO, A0, 1
\r
29311 BFD07E7E 0C00 NOP
\r
29313 262: /* Send to the queue - causing the queue receive task to unblock and
\r
29314 263: toggle the LED. 0 is used as the block time so the sending operation
\r
29315 264: will not block - it shouldn't need to block as the queue should always
\r
29316 265: be empty at this point in the code. */
\r
29317 266: xQueueSend( xQueue, &ulValueToSend, 0U );
\r
29318 BFD07E80 8070FC7C LW V1, -32656(GP)
\r
29319 BFD07E84 0014305E ADDIU V0, S8, 20
\r
29320 BFD07E88 0C83 MOVE A0, V1
\r
29321 BFD07E8A 0CA2 MOVE A1, V0
\r
29322 BFD07E8C 0CC0 MOVE A2, ZERO
\r
29323 BFD07E8E 0CE0 MOVE A3, ZERO
\r
29324 BFD07E90 06A277E8 JALS xQueueGenericSend
\r
29325 BFD07E92 06A2 ADDU A1, S1, V0
\r
29326 BFD07E94 0C00 NOP
\r
29328 BFD07E96 CFEC B 0xBFD07E70
\r
29329 BFD07E98 0C00 NOP
\r
29331 269: /*-----------------------------------------------------------*/
\r
29333 271: static void prvQueueReceiveTask( void *pvParameters )
\r
29335 BFD08090 4FF1 ADDIU SP, SP, -32
\r
29336 BFD08092 CBE7 SW RA, 28(SP)
\r
29337 BFD08094 CBC6 SW S8, 24(SP)
\r
29338 BFD08096 0FDD MOVE S8, SP
\r
29339 BFD08098 0020F89E SW A0, 32(S8)
\r
29340 273: unsigned long ulReceivedValue;
\r
29342 275: /* Remove compiler warnings in the case where configASSERT() is not defined. */
\r
29343 276: ( void ) pvParameters;
\r
29345 278: /* Check the task parameter is as expected. */
\r
29346 279: configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
\r
29347 BFD0809C 0020FC7E LW V1, 32(S8)
\r
29348 BFD080A0 ED22 LI V0, 34
\r
29349 BFD080A2 000D9443 BEQ V1, V0, 0xBFD080C0
\r
29350 BFD080A4 0C00000D SLL ZERO, T5, 1
\r
29351 BFD080A6 0C00 NOP
\r
29352 BFD080A8 BFD141A2 LUI V0, 0xBFD1
\r
29353 BFD080AA 3082BFD1 LDC1 F30, 12418(S1)
\r
29354 BFD080AC 9EF43082 ADDIU A0, V0, -24844
\r
29355 BFD080AE 30A09EF4 LWC1 F23, 12448(S4)
\r
29356 BFD080B0 011730A0 ADDIU A1, ZERO, 279
\r
29357 BFD080B4 4B7E77E8 JALS vAssertCalled
\r
29358 BFD080B6 4B7E LW K1, 120(SP)
\r
29359 BFD080B8 0C00 NOP
\r
29360 BFD080BA CC02 B 0xBFD080C0
\r
29361 BFD080BC 0C00 NOP
\r
29365 283: /* Wait until something arrives in the queue - this task will block
\r
29366 284: indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
\r
29367 285: FreeRTOSConfig.h. */
\r
29368 286: xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
\r
29369 BFD080C0 8070FC5C LW V0, -32656(GP)
\r
29370 BFD080C4 0C82 MOVE A0, V0
\r
29371 BFD080C6 0010305E ADDIU V0, S8, 16
\r
29372 BFD080CA 0CA2 MOVE A1, V0
\r
29373 BFD080CC EF7F LI A2, -1
\r
29374 BFD080CE 0CE0 MOVE A3, ZERO
\r
29375 BFD080D0 081E77E8 JALS xQueueGenericReceive
\r
29376 BFD080D2 081E LBU S0, 14(S1)
\r
29377 BFD080D4 0C00 NOP
\r
29379 288: /* To get here something must have been received from the queue, but
\r
29380 289: is it the expected value? If it is, toggle the LED. */
\r
29381 290: if( ulReceivedValue == 100UL )
\r
29382 BFD080D6 0010FC7E LW V1, 16(S8)
\r
29383 BFD080DA ED64 LI V0, 100
\r
29384 BFD080DC FFEFB443 BNE V1, V0, 0xBFD080BE
\r
29385 BFD080DE 0C00FFEF LW RA, 3072(T7)
\r
29386 BFD080E0 0C00 NOP
\r
29388 292: prvToggleLED( mainTASKS_LED );
\r
29389 BFD080E2 0C80 MOVE A0, ZERO
\r
29390 BFD080E4 4C3C77E8 JALS prvToggleLED
\r
29391 BFD080E6 4C3C ADDIU AT, AT, -2
\r
29392 BFD080E8 0C00 NOP
\r
29393 293: ulReceivedValue = 0U;
\r
29394 BFD080EA 0010F81E SW ZERO, 16(S8)
\r
29397 BFD080BE 0C00 NOP
\r
29398 BFD080EE CFE8 B 0xBFD080C0
\r
29399 BFD080F0 0C00 NOP
\r
29401 297: /*-----------------------------------------------------------*/
\r
29403 299: static void prvBlinkyTimerCallback( TimerHandle_t xTimer )
\r
29405 BFD09DAC 4FF5 ADDIU SP, SP, -24
\r
29406 BFD09DAE CBE5 SW RA, 20(SP)
\r
29407 BFD09DB0 CBC4 SW S8, 16(SP)
\r
29408 BFD09DB2 0FDD MOVE S8, SP
\r
29409 BFD09DB4 0018F89E SW A0, 24(S8)
\r
29410 301: /* Avoid compiler warnings. */
\r
29411 302: ( void ) xTimer;
\r
29413 304: /* This function is called when the blinky software time expires. All the
\r
29414 305: function does is toggle the LED. LED mainTIMER_LED should therefore toggle
\r
29415 306: with the period set by mainBLINKY_TIMER_PERIOD. */
\r
29416 307: prvToggleLED( mainTIMER_LED );
\r
29417 BFD09DB8 EE01 LI A0, 1
\r
29418 BFD09DBA 4C3C77E8 JALS prvToggleLED
\r
29419 BFD09DBC 4C3C ADDIU AT, AT, -2
\r
29420 BFD09DBE 0C00 NOP
\r
29422 BFD09DC0 0FBE MOVE SP, S8
\r
29423 BFD09DC2 4BE5 LW RA, 20(SP)
\r
29424 BFD09DC4 4BC4 LW S8, 16(SP)
\r
29425 BFD09DC6 4C0D ADDIU SP, SP, 24
\r
29426 BFD09DC8 459F JR16 RA
\r
29427 BFD09DCA 0C00 NOP
\r
29428 309: /*-----------------------------------------------------------*/
\r
29430 311: static void prvToggleLED( uint8_t ucLED )
\r
29432 BFD09878 4FF5 ADDIU SP, SP, -24
\r
29433 BFD0987A CBE5 SW RA, 20(SP)
\r
29434 BFD0987C CBC4 SW S8, 16(SP)
\r
29435 BFD0987E 0FDD MOVE S8, SP
\r
29436 BFD09880 0C44 MOVE V0, A0
\r
29437 BFD09882 0018185E SB V0, 24(S8)
\r
29438 313: taskENTER_CRITICAL();
\r
29439 BFD09886 33B877E8 JALS vTaskEnterCritical
\r
29440 BFD09888 0C0033B8 ADDIU SP, T8, 3072
\r
29441 BFD0988A 0C00 NOP
\r
29443 315: led_out_toggle( ucLED );
\r
29444 BFD0988C 0018145E LBU V0, 24(S8)
\r
29445 BFD09890 0C82 MOVE A0, V0
\r
29446 BFD09892 42D477E8 JALS led_out_toggle
\r
29447 BFD09896 0C00 NOP
\r
29449 317: taskEXIT_CRITICAL();
\r
29450 BFD09898 40AA77E8 JALS vTaskExitCritical
\r
29451 BFD0989A 0C0040AA BNEZC T2, 0xBFD0B09E
\r
29452 BFD0989C 0C00 NOP
\r
29454 BFD0989E 0FBE MOVE SP, S8
\r
29455 BFD098A0 4BE5 LW RA, 20(SP)
\r
29456 BFD098A2 4BC4 LW S8, 16(SP)
\r
29457 BFD098A4 4C0D ADDIU SP, SP, 24
\r
29458 BFD098A6 459F JR16 RA
\r
29459 BFD098A8 0C00 NOP
\r
29460 319: /*-----------------------------------------------------------*/
\r
29462 321: static void prvSetupHardware( void )
\r
29464 BFD05890 4FF1 ADDIU SP, SP, -32
\r
29465 BFD05892 CBE7 SW RA, 28(SP)
\r
29466 BFD05894 CBC6 SW S8, 24(SP)
\r
29467 BFD05896 0FDD MOVE S8, SP
\r
29468 323: volatile uint32_t ulTemp;
\r
29470 325: /* Interrupts are automatically re-enabled when the scheduler is started. */
\r
29471 326: __asm volatile( "di" );
\r
29472 BFD05898 477C0000 DI ZERO
\r
29474 328: /* Enable M14K Vector Pre-fetch: CP0.IntCtl b[22]=1
\r
29475 329: IRET (interrupt chaining): b[21]=1
\r
29476 330: Enable Auto-Prolog: b[14]=1 */
\r
29477 331: ulTemp = _CP0_GET_INTCTL();
\r
29478 BFD0589C 08FC004C MFC0 V0, IntCtl
\r
29479 BFD0589E 08FC LBU S1, 12(A3)
\r
29480 BFD058A0 0010F85E SW V0, 16(S8)
\r
29481 332: ulTemp |= ( 1ul << 22 ) + ( 1ul << 21 ) + ( 1ul << 14 );
\r
29482 BFD058A4 0010FC7E LW V1, 16(S8)
\r
29483 BFD058A8 006041A2 LUI V0, 0x60
\r
29484 BFD058AC 40005042 ORI V0, V0, 16384
\r
29485 BFD058AE 44D34000 BLTZ ZERO, 0xBFD0E258
\r
29486 BFD058B0 44D3 OR16 V0, V1
\r
29487 BFD058B2 0010F85E SW V0, 16(S8)
\r
29488 333: _CP0_SET_INTCTL( ulTemp );
\r
29489 BFD058B6 0010FC5E LW V0, 16(S8)
\r
29490 BFD058B8 004C0010 INS ZERO, S0, 1, 0
\r
29491 BFD058BA 0AFC004C MTC0 V0, IntCtl
\r
29492 BFD058BC 0AFC LBU A1, 12(A3)
\r
29493 BFD058BE 18000000 SLL ZERO, ZERO, 3
\r
29494 BFD058C0 41A21800 SB ZERO, 16802(ZERO)
\r
29496 335: /* Configure 32KHz for Switched Clock Source always ON
\r
29497 336: b[ 0 ] = XOSEL = 1
\r
29498 337: b[ 1 ] = EXT_32K_OSC_EN = 1
\r
29499 338: b[ 2 ] = INT_32K_OSC_EN = 1
\r
29500 339: b[ 3 ] = INT_32K_VTR_PWR_WELL_EMUL = 0
\r
29501 340: b[ 4 ] = 32K_SWITCHER_CTRL = 0 */
\r
29502 341: VBAT_REGS->CLOCK_ENABLE = 0x07;
\r
29503 BFD058C2 A00041A2 LUI V0, 0xA000
\r
29504 BFD058C6 A4005042 ORI V0, V0, -23552
\r
29505 BFD058CA ED87 LI V1, 7
\r
29506 BFD058CC E9A2 SW V1, 8(V0)
\r
29508 343: ulTemp = 256;
\r
29509 BFD058CE 01003040 ADDIU V0, ZERO, 256
\r
29510 344: while (ulTemp--)
\r
29511 BFD058D2 CC06 B 0xBFD058E0
\r
29512 BFD058D4 0010F85E SW V0, 16(S8)
\r
29513 BFD058D6 0C000010 SLL ZERO, S0, 1
\r
29514 BFD058E0 0010FC5E LW V0, 16(S8)
\r
29515 BFD058E2 00400010 SRL ZERO, S0, 0
\r
29516 BFD058E4 1B900040 SLTU V1, ZERO, V0
\r
29517 BFD058E6 2DBD1B90 SB GP, 11709(S0)
\r
29518 BFD058E8 2DBD ANDI V1, V1, 0xFF
\r
29519 BFD058EA 6D2E ADDIU V0, V0, -1
\r
29520 BFD058EC 0010F85E SW V0, 16(S8)
\r
29521 BFD058F0 FFF240A3 BNEZC V1, 0xBFD058D8
\r
29522 BFD058F2 41A2FFF2 LW RA, 16802(S2)
\r
29524 346: __asm volatile( "NOP" );
\r
29525 BFD058D8 0C00 NOP
\r
29526 347: __asm volatile( "NOP" );
\r
29527 BFD058DA 0C00 NOP
\r
29528 348: __asm volatile( "NOP" );
\r
29529 BFD058DC 0C00 NOP
\r
29530 349: __asm volatile( "NOP" );
\r
29531 BFD058DE 0C00 NOP
\r
29534 352: /* Disaggregate GIRQ23 & GIRQ24 for FreeRTOS. Second parameter is a bit-map
\r
29535 353: for each GIRQ where
\r
29536 354: 0 = Aggregated, 1 = Dis-aggregate
\r
29537 355: Bit position = GIRQ_Number - 8
\r
29538 356: Example: GIRQ23 ( 23 - 8 ) = 15
\r
29539 357: Dis-aggregate GIRQ23 & GIRQ24
\r
29540 358: The symbols JTVIC_DISAGR_BITMAP is generated in header file mec14xx_girqm.h
\r
29542 360: Each disaggregated interrupt handler is spaced 8-bytes apart starting at
\r
29543 361: base address for that GIRQ. */
\r
29544 362: jtvic_init( dflt_ih_table, ( JTVIC_DISAGR_BITMAP ), ( JTVIC_FLAG_DISAGR_SPACING_8 ) );
\r
29545 BFD058F4 BFD041A2 LUI V0, 0xBFD0
\r
29546 BFD058F6 3082BFD0 LDC1 F30, 12418(S0)
\r
29547 BFD058F8 26F03082 ADDIU A0, V0, 9968
\r
29548 BFD058FA 26F0 SLL A1, A3, 8
\r
29549 BFD058FC 000141A2 LUI V0, 0x1
\r
29550 BFD05900 800050A2 ORI A1, V0, -32768
\r
29551 BFD05904 1B2277E8 JALS jtvic_init
\r
29552 BFD05906 0CC01B22 SB T9, 3264(V0)
\r
29553 BFD05908 0CC0 MOVE A2, ZERO
\r
29555 364: /* Initialise the LEDs. */
\r
29556 365: for( ulTemp = 0; ulTemp < LED_ID_MAX; ulTemp++ )
\r
29557 BFD0590A CC1A B 0xBFD05940
\r
29558 BFD0590C 0010F81E SW ZERO, 16(S8)
\r
29559 BFD05936 0010FC5E LW V0, 16(S8)
\r
29560 BFD0593A 6D20 ADDIU V0, V0, 1
\r
29561 BFD0593C 0010F85E SW V0, 16(S8)
\r
29562 BFD05940 0010FC5E LW V0, 16(S8)
\r
29563 BFD05944 0003B042 SLTIU V0, V0, 3
\r
29564 BFD05948 FFE240A2 BNEZC V0, 0xBFD05910
\r
29565 BFD0594A 0FBEFFE2 LW RA, 4030(V0)
\r
29567 367: led_sleep_en( ulTemp, ADISABLE );
\r
29568 BFD05910 0010FC5E LW V0, 16(S8)
\r
29569 BFD05914 2D2D ANDI V0, V0, 0xFF
\r
29570 BFD05916 0C82 MOVE A0, V0
\r
29571 BFD05918 2E8677E8 JALS led_sleep_en
\r
29572 BFD0591A 2E86 ANDI A1, S0, 0x8
\r
29573 BFD0591C 0CA0 MOVE A1, ZERO
\r
29574 368: led_init( ulTemp );
\r
29575 BFD0591E 0010FC5E LW V0, 16(S8)
\r
29576 BFD05922 2D2D ANDI V0, V0, 0xFF
\r
29577 BFD05924 3E7E77E8 JALS led_init
\r
29578 BFD05926 0C823E7E LH S3, 3202(S8)
\r
29579 BFD05928 0C82 MOVE A0, V0
\r
29580 369: led_out_low( ulTemp );
\r
29581 BFD0592A 0010FC5E LW V0, 16(S8)
\r
29582 BFD0592E 2D2D ANDI V0, V0, 0xFF
\r
29583 BFD05930 4A3077E8 JALS led_out_low
\r
29584 BFD05932 4A30 LW S1, 64(SP)
\r
29585 BFD05934 0C82 MOVE A0, V0
\r
29588 BFD0594C 0FBE MOVE SP, S8
\r
29589 BFD0594E 4BE7 LW RA, 28(SP)
\r
29590 BFD05950 4BC6 LW S8, 24(SP)
\r
29591 BFD05952 459F JR16 RA
\r
29592 BFD05954 4C11 ADDIU SP, SP, 32
\r
29593 372: /*-----------------------------------------------------------*/
\r
29595 374: void vApplicationMallocFailedHook( void )
\r
29597 BFD08900 4FF1 ADDIU SP, SP, -32
\r
29598 BFD08902 CBE7 SW RA, 28(SP)
\r
29599 BFD08904 CBC6 SW S8, 24(SP)
\r
29600 BFD08906 0FDD MOVE S8, SP
\r
29601 376: /* vApplicationMallocFailedHook() will only be called if
\r
29602 377: configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
\r
29603 378: function that will get called if a call to pvPortMalloc() fails.
\r
29604 379: pvPortMalloc() is called internally by the kernel whenever a task, queue,
\r
29605 380: timer or semaphore is created. It is also called by various parts of the
\r
29606 381: demo application. If heap_1.c or heap_2.c are used, then the size of the
\r
29607 382: heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
\r
29608 383: FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
\r
29609 384: to query the size of free heap space that remains (although it does not
\r
29610 385: provide information on how the remaining heap might be fragmented). */
\r
29611 386: taskDISABLE_INTERRUPTS();
\r
29612 BFD08908 4EB677E8 JALS ulPortGetCP0Status
\r
29613 BFD0890A 4EB6 ADDIU S5, S5, -5
\r
29614 BFD0890C 0C00 NOP
\r
29615 BFD0890E 0010F85E SW V0, 16(S8)
\r
29616 BFD08912 0010FC7E LW V1, 16(S8)
\r
29617 BFD08916 000141A2 LUI V0, 0x1
\r
29618 BFD0891A FC005042 ORI V0, V0, -1024
\r
29619 BFD0891C 4493FC00 LW ZERO, 17555(ZERO)
\r
29620 BFD0891E 4493 AND16 V0, V1
\r
29621 BFD08920 50400042 SRL V0, V0, 10
\r
29622 BFD08922 B0425040 ORI V0, ZERO, -20414
\r
29623 BFD08924 0003B042 SLTIU V0, V0, 3
\r
29624 BFD08928 001140E2 BEQZC V0, 0xBFD0894E
\r
29625 BFD0892C 0010FC7E LW V1, 16(S8)
\r
29626 BFD08930 FFFE41A2 LUI V0, 0xFFFE
\r
29627 BFD08932 5042FFFE LW RA, 20546(S8)
\r
29628 BFD08934 03FF5042 ORI V0, V0, 1023
\r
29629 BFD08938 4493 AND16 V0, V1
\r
29630 BFD0893A 0010F85E SW V0, 16(S8)
\r
29631 BFD0893E 0010FC5E LW V0, 16(S8)
\r
29632 BFD08942 0C005042 ORI V0, V0, 3072
\r
29633 BFD08944 0C00 NOP
\r
29634 BFD08946 0C82 MOVE A0, V0
\r
29635 BFD08948 4EC677E8 JALS vPortSetCP0Status
\r
29636 BFD0894A 4EC6 ADDIU S6, S6, 3
\r
29637 BFD0894C 0C00 NOP
\r
29639 BFD0894E CFFF B 0xBFD0894E
\r
29640 BFD08950 0C00 NOP
\r
29642 389: /*-----------------------------------------------------------*/
\r
29644 391: void vApplicationIdleHook( void )
\r
29646 BFD09F04 4FB0 ADDIU SP, SP, -8
\r
29647 BFD09F06 CBC1 SW S8, 4(SP)
\r
29648 BFD09F08 0FDD MOVE S8, SP
\r
29649 393: /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
\r
29650 394: to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
\r
29651 395: task. It is essential that code added to this hook function never attempts
\r
29652 396: to block in any way (for example, call xQueueReceive() with a block time
\r
29653 397: specified, or call vTaskDelay()). If the application makes use of the
\r
29654 398: vTaskDelete() API function (as this demo application does) then it is also
\r
29655 399: important that vApplicationIdleHook() is permitted to return to its calling
\r
29656 400: function, because it is the responsibility of the idle task to clean up
\r
29657 401: memory allocated by the kernel to any task that has since been deleted. */
\r
29659 BFD09F0A 0FBE MOVE SP, S8
\r
29660 BFD09F0C 4BC1 LW S8, 4(SP)
\r
29661 BFD09F0E 4C05 ADDIU SP, SP, 8
\r
29662 BFD09F10 459F JR16 RA
\r
29663 BFD09F12 0C00 NOP
\r
29664 403: /*-----------------------------------------------------------*/
\r
29666 405: void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
\r
29668 BFD08444 4FF1 ADDIU SP, SP, -32
\r
29669 BFD08446 CBE7 SW RA, 28(SP)
\r
29670 BFD08448 CBC6 SW S8, 24(SP)
\r
29671 BFD0844A 0FDD MOVE S8, SP
\r
29672 BFD0844C 0020F89E SW A0, 32(S8)
\r
29673 BFD08450 0024F8BE SW A1, 36(S8)
\r
29674 407: ( void ) pcTaskName;
\r
29675 408: ( void ) pxTask;
\r
29677 410: /* Run time task stack overflow checking is performed if
\r
29678 411: configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
\r
29679 412: called if a task stack overflow is detected. Note the system/interrupt
\r
29680 413: stack is not checked. */
\r
29681 414: taskDISABLE_INTERRUPTS();
\r
29682 BFD08454 4EB677E8 JALS ulPortGetCP0Status
\r
29683 BFD08456 4EB6 ADDIU S5, S5, -5
\r
29684 BFD08458 0C00 NOP
\r
29685 BFD0845A 0010F85E SW V0, 16(S8)
\r
29686 BFD0845E 0010FC7E LW V1, 16(S8)
\r
29687 BFD08462 000141A2 LUI V0, 0x1
\r
29688 BFD08466 FC005042 ORI V0, V0, -1024
\r
29689 BFD08468 4493FC00 LW ZERO, 17555(ZERO)
\r
29690 BFD0846A 4493 AND16 V0, V1
\r
29691 BFD0846C 50400042 SRL V0, V0, 10
\r
29692 BFD0846E B0425040 ORI V0, ZERO, -20414
\r
29693 BFD08470 0003B042 SLTIU V0, V0, 3
\r
29694 BFD08474 001140E2 BEQZC V0, 0xBFD0849A
\r
29695 BFD08478 0010FC7E LW V1, 16(S8)
\r
29696 BFD0847C FFFE41A2 LUI V0, 0xFFFE
\r
29697 BFD0847E 5042FFFE LW RA, 20546(S8)
\r
29698 BFD08480 03FF5042 ORI V0, V0, 1023
\r
29699 BFD08484 4493 AND16 V0, V1
\r
29700 BFD08486 0010F85E SW V0, 16(S8)
\r
29701 BFD0848A 0010FC5E LW V0, 16(S8)
\r
29702 BFD0848E 0C005042 ORI V0, V0, 3072
\r
29703 BFD08490 0C00 NOP
\r
29704 BFD08492 0C82 MOVE A0, V0
\r
29705 BFD08494 4EC677E8 JALS vPortSetCP0Status
\r
29706 BFD08496 4EC6 ADDIU S6, S6, 3
\r
29707 BFD08498 0C00 NOP
\r
29709 BFD0849A CFFF B 0xBFD0849A
\r
29710 BFD0849C 0C00 NOP
\r
29712 417: /*-----------------------------------------------------------*/
\r
29714 419: void vApplicationTickHook( void )
\r
29716 BFD09F14 4FB0 ADDIU SP, SP, -8
\r
29717 BFD09F16 CBC1 SW S8, 4(SP)
\r
29718 BFD09F18 0FDD MOVE S8, SP
\r
29719 421: /* This function will be called by each tick interrupt if
\r
29720 422: configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
\r
29721 423: added here, but the tick hook is called from an interrupt context, so
\r
29722 424: code must not attempt to block, and only the interrupt safe FreeRTOS API
\r
29723 425: functions can be used (those that end in FromISR()). */
\r
29725 BFD09F1A 0FBE MOVE SP, S8
\r
29726 BFD09F1C 4BC1 LW S8, 4(SP)
\r
29727 BFD09F1E 4C05 ADDIU SP, SP, 8
\r
29728 BFD09F20 459F JR16 RA
\r
29729 BFD09F22 0C00 NOP
\r
29730 427: /*-----------------------------------------------------------*/
\r
29732 429: void vAssertCalled( const char * pcFile, unsigned long ulLine )
\r
29734 BFD096FC 4FF9 ADDIU SP, SP, -16
\r
29735 BFD096FE CBC3 SW S8, 12(SP)
\r
29736 BFD09700 0FDD MOVE S8, SP
\r
29737 BFD09702 0010F89E SW A0, 16(S8)
\r
29738 BFD09706 0014F8BE SW A1, 20(S8)
\r
29739 431: volatile char *pcFileName;
\r
29740 432: volatile unsigned long ulLineNumber;
\r
29742 434: /* Prevent things that are useful to view in the debugger from being
\r
29743 435: optimised away. */
\r
29744 436: pcFileName = ( char * ) pcFile;
\r
29745 BFD0970A 0010FC5E LW V0, 16(S8)
\r
29746 BFD0970E 0000F85E SW V0, 0(S8)
\r
29747 437: ( void ) pcFileName;
\r
29748 438: ulLineNumber = ulLine;
\r
29749 BFD09712 0014FC5E LW V0, 20(S8)
\r
29750 BFD09716 0004F85E SW V0, 4(S8)
\r
29752 440: /* Set ulLineNumber to 0 in the debugger to break out of this loop and
\r
29753 441: return to the line that triggered the assert. */
\r
29754 442: while( ulLineNumber != 0 )
\r
29755 BFD0971A CC06 B 0xBFD09728
\r
29756 BFD0971C 0C00 NOP
\r
29757 BFD09728 0004FC5E LW V0, 4(S8)
\r
29758 BFD0972C FFF740A2 BNEZC V0, 0xBFD0971E
\r
29759 BFD0972E 0FBEFFF7 LW RA, 4030(S7)
\r
29761 444: __asm volatile( "NOP" );
\r
29762 BFD0971E 0C00 NOP
\r
29763 445: __asm volatile( "NOP" );
\r
29764 BFD09720 0C00 NOP
\r
29765 446: __asm volatile( "NOP" );
\r
29766 BFD09722 0C00 NOP
\r
29767 447: __asm volatile( "NOP" );
\r
29768 BFD09724 0C00 NOP
\r
29769 448: __asm volatile( "NOP" );
\r
29770 BFD09726 0C00 NOP
\r
29773 BFD09730 0FBE MOVE SP, S8
\r
29774 BFD09732 4BC3 LW S8, 12(SP)
\r
29775 BFD09734 459F JR16 RA
\r
29776 BFD09736 4C09 ADDIU SP, SP, 16
\r
29778 --- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S --------------
\r
29780 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
29781 3: All rights reserved
\r
29783 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
29785 7: This file is part of the FreeRTOS distribution.
\r
29787 9: FreeRTOS is free software; you can redistribute it and/or modify it under
\r
29788 10: the terms of the GNU General Public License (version 2) as published by the
\r
29789 11: Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
29791 13: ***************************************************************************
\r
29792 14: >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
29793 15: >>! distribute a combined work that includes FreeRTOS without being !<<
\r
29794 16: >>! obliged to provide the source code for proprietary components !<<
\r
29795 17: >>! outside of the FreeRTOS kernel. !<<
\r
29796 18: ***************************************************************************
\r
29798 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
29799 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
29800 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
29801 23: link: http://www.freertos.org/a00114.html
\r
29803 25: ***************************************************************************
\r
29805 27: * FreeRTOS provides completely free yet professionally developed, *
\r
29806 28: * robust, strictly quality controlled, supported, and cross *
\r
29807 29: * platform software that is more than just the market leader, it *
\r
29808 30: * is the industry's de facto standard. *
\r
29810 32: * Help yourself get started quickly while simultaneously helping *
\r
29811 33: * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
29812 34: * tutorial book, reference manual, or both: *
\r
29813 35: * http://www.FreeRTOS.org/Documentation *
\r
29815 37: ***************************************************************************
\r
29817 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
29818 40: the FAQ page "My application does not run, what could be wrong?". Have you
\r
29819 41: defined configASSERT()?
\r
29821 43: http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
29822 44: embedded software for free we request you assist our global community by
\r
29823 45: participating in the support forum.
\r
29825 47: http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
29826 48: be as productive as possible as early as possible. Now you can receive
\r
29827 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
29828 50: Ltd, and the world's leading authority on the world's leading RTOS.
\r
29830 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
29831 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
29832 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
29834 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
29835 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
29837 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
29838 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
29839 61: licenses offer ticketed support, indemnification and commercial middleware.
\r
29841 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
29842 64: engineered and independently SIL3 certified version for use in safety and
\r
29843 65: mission critical applications that require provable dependability.
\r
29845 67: 1 tab == 4 spaces!
\r
29848 70: #include <xc.h>
\r
29849 71: #include <sys/asm.h>
\r
29850 72: #include "FreeRTOSConfig.h"
\r
29851 73: #include "ISR_Support.h"
\r
29854 76: .extern pxCurrentTCB
\r
29855 77: .extern vTaskSwitchContext
\r
29856 78: .extern vPortIncrementTick
\r
29857 79: .extern xISRStackTop
\r
29859 81: PORT_CPP_JTVIC_BASE = 0xBFFFC000
\r
29860 82: PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100
\r
29862 84: .global vPortStartFirstTask .text
\r
29863 85: .global vPortYieldISR .text
\r
29864 86: .global vPortTickInterruptHandler .text
\r
29867 89: /******************************************************************/
\r
29870 92: /***************************************************************
\r
29871 93: * The following is needed to locate the
\r
29872 94: * vPortTickInterruptHandler function into the correct vector
\r
29873 95: * MEC14xx - This ISR will only be used if HW timers' interrupts
\r
29874 96: * in GIRQ23 are disaggregated.
\r
29876 98: ***************************************************************/
\r
29878 100: .set noreorder
\r
29880 102: .set micromips
\r
29882 104: .section .text, code
\r
29883 105: .ent vPortTickInterruptHandler
\r
29885 107: #if configTIMERS_DISAGGREGATED_ISRS == 0
\r
29887 109: .globl girq23_isr
\r
29890 112: vPortTickInterruptHandler:
\r
29892 114: portSAVE_CONTEXT2 vpti
\r
29894 116: jal girq23_handler
\r
29897 119: portRESTORE_CONTEXT
\r
29899 121: .end vPortTickInterruptHandler
\r
29903 125: .globl girq23_b4
\r
29906 128: vPortTickInterruptHandler:
\r
29908 130: /* portSAVE_CONTEXT */
\r
29909 BFD00920 00FC034D MFC0 K0, Cause 131: portSAVE_CONTEXT2 vpti
\r
29911 BFD009F0 34DCF7E8 JAL 0xBFD069B8 133: jal vPortIncrementTick
\r
29912 BFD009F4 00000000 NOP 134: nop
\r
29914 BFD009F8 BFD241B6 LUI S6, 0xBFD2 136: portRESTORE_CONTEXT
\r
29916 138: .end vPortTickInterruptHandler
\r
29918 140: #endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */
\r
29920 142: /******************************************************************/
\r
29922 144: .set micromips
\r
29923 145: .set noreorder
\r
29926 148: .section .text, code
\r
29927 149: .ent vPortStartFirstTask
\r
29929 151: vPortStartFirstTask:
\r
29931 153: /* Simply restore the context of the highest priority task that has
\r
29932 154: been created so far. */
\r
29933 BFD00AB4 BFD241B6 LUI S6, 0xBFD2 155: portRESTORE_CONTEXT
\r
29935 157: .end vPortStartFirstTask
\r
29939 161: /*******************************************************************/
\r
29941 163: /***************************************************************
\r
29942 164: * The following is needed to locate the vPortYieldISR function
\r
29943 165: * into the correct vector
\r
29944 166: ***************************************************************/
\r
29946 168: .set micromips
\r
29947 169: .set noreorder
\r
29950 172: .section .text, code
\r
29952 174: .global vPortYieldISR
\r
29955 177: #if configCPU_DISAGGREGATED_ISRS == 0
\r
29956 178: .global girq24_isr
\r
29957 179: .ent girq24_isr
\r
29959 181: la k0, PORT_CPP_JTVIC_BASE
\r
29960 182: lw k0, 0x10C(k0)
\r
29961 183: andi k1, k0, 0x2
\r
29962 184: bgtz k1, vPortYieldISR
\r
29965 187: portSAVE_CONTEXT
\r
29967 189: jal girq24_b_0_2
\r
29969 191: portRESTORE_CONTEXT
\r
29971 193: .end girq24_isr
\r
29974 196: .global girq24_b1
\r
29977 199: .ent vPortYieldISR
\r
29978 200: vPortYieldISR:
\r
29980 202: /* Make room for the context. First save the current status so it can be
\r
29981 203: manipulated, and the cause and EPC registers so thier original values
\r
29982 204: are captured. */
\r
29983 BFD00B70 4FBF ADDIU SP, SP, -132 205: addiu sp, sp, -portCONTEXT_SIZE
\r
29984 BFD00B72 00FC036C MFC0 K1, Status 206: mfc0 k1, _CP0_STATUS
\r
29986 208: /* Also save s6 and s5 so they can be used. Any nesting interrupts should
\r
29987 209: maintain the values of these registers across the ISR. */
\r
29988 BFD00B76 CACB SW S6, 44(SP) 210: sw s6, 44(sp)
\r
29989 BFD00B78 CAAA SW S5, 40(SP) 211: sw s5, 40(sp)
\r
29990 BFD00B7A 0080FB7D SW K1, 128(SP) 212: sw k1, portSTATUS_STACK_LOCATION(sp)
\r
29992 214: /* Prepare to re-enabled interrupts above the kernel priority. */
\r
29993 BFD00B7E 828C0360 INS K1, ZERO, 10, 7 215: ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
\r
29994 BFD00B82 948C0360 INS K1, ZERO, 18, 1 216: ins k1, zero, 18, 1 /* Clear IPL bit 7 */
\r
29995 BFD00B86 0C00537B ORI K1, K1, 3072 217: ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
\r
29996 BFD00B8A 204C0360 INS K1, ZERO, 1, 4 218: ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
\r
29998 220: /* s5 is used as the frame pointer. */
\r
29999 BFD00B8E A91003A0 ADD S5, ZERO, SP 221: add s5, zero, sp
\r
30001 223: /* Swap to the system stack. This is not conditional on the nesting
\r
30002 224: count as this interrupt is always the lowest priority and therefore
\r
30003 225: the nesting is always 0. */
\r
30004 BFD00B92 BFD141BD LUI SP, 0xBFD1 226: la sp, xISRStackTop
\r
30005 BFD00B9A 4BA0 LW SP, 0(SP) 227: lw sp, (sp)
\r
30007 229: /* Set the nesting count. */
\r
30008 BFD00B9C BFD241BA LUI K0, 0xBFD2 230: la k0, uxInterruptNesting
\r
30009 BFD00BA4 000132C0 ADDIU S6, ZERO, 1 231: addiu s6, zero, 1
\r
30010 BFD00BA8 0000FADA SW S6, 0(K0) 232: sw s6, 0(k0)
\r
30012 234: /* s6 holds the EPC value, this is saved with the rest of the context
\r
30013 235: after interrupts are enabled. */
\r
30014 BFD00BAC 00FC02CE MFC0 S6, EPC 236: mfc0 s6, _CP0_EPC
\r
30016 238: /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
\r
30017 BFD00BB0 02FC036C MTC0 K1, Status 239: mtc0 k1, _CP0_STATUS
\r
30019 241: /* Save the context into the space just created. s6 is saved again
\r
30020 242: here as it now contains the EPC value. */
\r
30021 BFD00BB4 0078FBF5 SW RA, 120(S5) 243: sw ra, 120(s5)
\r
30022 BFD00BB8 0074FBD5 SW S8, 116(S5) 244: sw s8, 116(s5)
\r
30023 BFD00BBC 0070FB35 SW T9, 112(S5) 245: sw t9, 112(s5)
\r
30024 BFD00BC0 006CFB15 SW T8, 108(S5) 246: sw t8, 108(s5)
\r
30025 BFD00BC4 0068F9F5 SW T7, 104(S5) 247: sw t7, 104(s5)
\r
30026 BFD00BC8 0064F9D5 SW T6, 100(S5) 248: sw t6, 100(s5)
\r
30027 BFD00BCC 0060F9B5 SW T5, 96(S5) 249: sw t5, 96(s5)
\r
30028 BFD00BD0 005CF995 SW T4, 92(S5) 250: sw t4, 92(s5)
\r
30029 BFD00BD4 0058F975 SW T3, 88(S5) 251: sw t3, 88(s5)
\r
30030 BFD00BD8 0054F955 SW T2, 84(S5) 252: sw t2, 84(s5)
\r
30031 BFD00BDC 0050F935 SW T1, 80(S5) 253: sw t1, 80(s5)
\r
30032 BFD00BE0 004CF915 SW T0, 76(S5) 254: sw t0, 76(s5)
\r
30033 BFD00BE4 0048F8F5 SW A3, 72(S5) 255: sw a3, 72(s5)
\r
30034 BFD00BE8 0044F8D5 SW A2, 68(S5) 256: sw a2, 68(s5)
\r
30035 BFD00BEC 0040F8B5 SW A1, 64(S5) 257: sw a1, 64(s5)
\r
30036 BFD00BF0 003CF895 SW A0, 60(S5) 258: sw a0, 60(s5)
\r
30037 BFD00BF4 0038F875 SW V1, 56(S5) 259: sw v1, 56(s5)
\r
30038 BFD00BF8 0034F855 SW V0, 52(S5) 260: sw v0, 52(s5)
\r
30039 BFD00BFC 0030FAF5 SW S7, 48(S5) 261: sw s7, 48(s5)
\r
30040 BFD00C00 007CFAD5 SW S6, 124(S5) 262: sw s6, portEPC_STACK_LOCATION(s5)
\r
30041 263: /* s5 and s6 has already been saved. */
\r
30042 BFD00C04 0024FA95 SW S4, 36(S5) 264: sw s4, 36(s5)
\r
30043 BFD00C08 0020FA75 SW S3, 32(S5) 265: sw s3, 32(s5)
\r
30044 BFD00C0C 001CFA55 SW S2, 28(S5) 266: sw s2, 28(s5)
\r
30045 BFD00C10 0018FA35 SW S1, 24(S5) 267: sw s1, 24(s5)
\r
30046 BFD00C14 0014FA15 SW S0, 20(S5) 268: sw s0, 20(s5)
\r
30047 BFD00C18 0010F835 SW AT, 16(S5) 269: sw $1, 16(s5)
\r
30049 271: /* s7 is used as a scratch register as this should always be saved acro ss
\r
30050 272: nesting interrupts. */
\r
30051 BFD00C1C 4617 MFHI S7 273: mfhi s7
\r
30052 BFD00C1E 000CFAF5 SW S7, 12(S5) 274: sw s7, 12(s5)
\r
30053 BFD00C22 4657 MFLO S7 275: mflo s7
\r
30054 BFD00C24 0008FAF5 SW S7, 8(S5) 276: sw s7, 8(s5)
\r
30056 278: /* Save the stack pointer to the task. */
\r
30057 BFD00C28 BFD241B7 LUI S7, 0xBFD2 279: la s7, pxCurrentTCB
\r
30058 BFD00C30 0000FEF7 LW S7, 0(S7) 280: lw s7, (s7)
\r
30059 BFD00C34 0000FAB7 SW S5, 0(S7) 281: sw s5, (s7)
\r
30061 283: /* Set the interrupt mask to the max priority that can use the API.
\r
30062 284: The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY
\r
30063 285: which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only
\r
30064 286: ever raise the IPL value and never lower it. */
\r
30065 BFD00C38 477C0000 DI ZERO 287: di
\r
30066 BFD00C3C 18000000 SLL ZERO, ZERO, 3 288: ehb
\r
30067 BFD00C40 00FC02EC MFC0 S7, Status 289: mfc0 s7, _CP0_STATUS
\r
30068 BFD00C44 828C02E0 INS S7, ZERO, 10, 7 290: ins s7, zero, 10, 7
\r
30069 BFD00C48 948C02E0 INS S7, ZERO, 18, 1 291: ins s7, zero, 18, 1
\r
30070 BFD00C4C 0C0152D7 ORI S6, S7, 3073 292: ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
\r
30072 294: /* This mtc0 re-enables interrupts, but only above
\r
30073 295: configMAX_SYSCALL_INTERRUPT_PRIORITY. */
\r
30074 BFD00C50 02FC02CC MTC0 S6, Status 296: mtc0 s6, _CP0_STATUS
\r
30075 BFD00C54 18000000 SLL ZERO, ZERO, 3 297: ehb
\r
30077 299: /* Clear the software interrupt in the core. */
\r
30078 BFD00C58 00FC02CD MFC0 S6, Cause 300: mfc0 s6, _CP0_CAUSE
\r
30079 BFD00C5C 420C02C0 INS S6, ZERO, 8, 1 301: ins s6, zero, 8, 1
\r
30080 BFD00C60 02FC02CD MTC0 S6, Cause 302: mtc0 s6, _CP0_CAUSE
\r
30081 BFD00C64 18000000 SLL ZERO, ZERO, 3 303: ehb
\r
30083 305: /* Clear the interrupt in the interrupt controller.
\r
30084 306: MEC14xx GIRQ24 Source bit[1] = 1 to clear */
\r
30085 BFD00C68 BFFF41B6 LUI S6, 0xBFFF 307: la s6, PORT_CCP_JTVIC_GIRQ24_SRC
\r
30086 BFD00C70 00023280 ADDIU S4, ZERO, 2 308: addiu s4, zero, 2
\r
30087 BFD00C74 0000FA96 SW S4, 0(S6) 309: sw s4, (s6)
\r
30088 BFD00C78 16DEF7E8 JAL 0xBFD02DBC 310: jal vTaskSwitchContext
\r
30089 BFD00C7C 00000000 NOP 311: nop
\r
30091 313: /* Clear the interrupt mask again. The saved status value is still in s7 */
\r
30092 BFD00C80 02FC02EC MTC0 S7, Status 314: mtc0 s7, _CP0_STATUS
\r
30093 BFD00C84 18000000 SLL ZERO, ZERO, 3 315: ehb
\r
30095 317: /* Restore the stack pointer from the TCB. */
\r
30096 BFD00C88 BFD241B0 LUI S0, 0xBFD2 318: la s0, pxCurrentTCB
\r
30097 BFD00C90 6800 LW S0, 0(S0) 319: lw s0, (s0)
\r
30098 BFD00C92 0000FEB0 LW S5, 0(S0) 320: lw s5, (s0)
\r
30100 322: /* Restore the rest of the context. */
\r
30101 BFD00C96 0008FE15 LW S0, 8(S5) 323: lw s0, 8(s5)
\r
30102 BFD00C9A 3D7C0010 MTLO S0 324: mtlo s0
\r
30103 BFD00C9E 000CFE15 LW S0, 12(S5) 325: lw s0, 12(s5)
\r
30104 BFD00CA2 2D7C0010 MTHI S0 326: mthi s0
\r
30106 BFD00CA6 0010FC35 LW AT, 16(S5) 328: lw $1, 16(s5)
\r
30107 BFD00CAA 0014FE15 LW S0, 20(S5) 329: lw s0, 20(s5)
\r
30108 BFD00CAE 0018FE35 LW S1, 24(S5) 330: lw s1, 24(s5)
\r
30109 BFD00CB2 001CFE55 LW S2, 28(S5) 331: lw s2, 28(s5)
\r
30110 BFD00CB6 0020FE75 LW S3, 32(S5) 332: lw s3, 32(s5)
\r
30111 BFD00CBA 0024FE95 LW S4, 36(S5) 333: lw s4, 36(s5)
\r
30113 335: /* s5 is loaded later. */
\r
30114 BFD00CBE 002CFED5 LW S6, 44(S5) 336: lw s6, 44(s5)
\r
30115 BFD00CC2 0030FEF5 LW S7, 48(S5) 337: lw s7, 48(s5)
\r
30116 BFD00CC6 0034FC55 LW V0, 52(S5) 338: lw v0, 52(s5)
\r
30117 BFD00CCA 0038FC75 LW V1, 56(S5) 339: lw v1, 56(s5)
\r
30118 BFD00CCE 003CFC95 LW A0, 60(S5) 340: lw a0, 60(s5)
\r
30119 BFD00CD2 0040FCB5 LW A1, 64(S5) 341: lw a1, 64(s5)
\r
30120 BFD00CD6 0044FCD5 LW A2, 68(S5) 342: lw a2, 68(s5)
\r
30121 BFD00CDA 0048FCF5 LW A3, 72(S5) 343: lw a3, 72(s5)
\r
30122 BFD00CDE 004CFD15 LW T0, 76(S5) 344: lw t0, 76(s5)
\r
30123 BFD00CE2 0050FD35 LW T1, 80(S5) 345: lw t1, 80(s5)
\r
30124 BFD00CE6 0054FD55 LW T2, 84(S5) 346: lw t2, 84(s5)
\r
30125 BFD00CEA 0058FD75 LW T3, 88(S5) 347: lw t3, 88(s5)
\r
30126 BFD00CEE 005CFD95 LW T4, 92(S5) 348: lw t4, 92(s5)
\r
30127 BFD00CF2 0060FDB5 LW T5, 96(S5) 349: lw t5, 96(s5)
\r
30128 BFD00CF6 0064FDD5 LW T6, 100(S5) 350: lw t6, 100(s5)
\r
30129 BFD00CFA 0068FDF5 LW T7, 104(S5) 351: lw t7, 104(s5)
\r
30130 BFD00CFE 006CFF15 LW T8, 108(S5) 352: lw t8, 108(s5)
\r
30131 BFD00D02 0070FF35 LW T9, 112(S5) 353: lw t9, 112(s5)
\r
30132 BFD00D06 0074FFD5 LW S8, 116(S5) 354: lw s8, 116(s5)
\r
30133 BFD00D0A 0078FFF5 LW RA, 120(S5) 355: lw ra, 120(s5)
\r
30135 357: /* Protect access to the k registers, and others. */
\r
30136 BFD00D0E 477C0000 DI ZERO 358: di
\r
30137 BFD00D12 18000000 SLL ZERO, ZERO, 3 359: ehb
\r
30139 361: /* Set nesting back to zero. As the lowest priority interrupt this
\r
30140 362: interrupt cannot have nested. */
\r
30141 BFD00D16 BFD241BA LUI K0, 0xBFD2 363: la k0, uxInterruptNesting
\r
30142 BFD00D1E 0000F81A SW ZERO, 0(K0) 364: sw zero, 0(k0)
\r
30144 366: /* Switch back to use the real stack pointer. */
\r
30145 BFD00D22 E91002A0 ADD SP, ZERO, S5 367: add sp, zero, s5
\r
30147 369: /* Restore the real s5 value. */
\r
30148 BFD00D26 4AAA LW S5, 40(SP) 370: lw s5, 40(sp)
\r
30150 372: /* Pop the status and epc values. */
\r
30151 BFD00D28 0080FF7D LW K1, 128(SP) 373: lw k1, portSTATUS_STACK_LOCATION(sp)
\r
30152 BFD00D2C 4B5F LW K0, 124(SP) 374: lw k0, portEPC_STACK_LOCATION(sp)
\r
30154 376: /* Remove stack frame. */
\r
30155 BFD00D2E 4C43 ADDIU SP, SP, 132 377: addiu sp, sp, portCONTEXT_SIZE
\r
30157 BFD00D30 02FC036C MTC0 K1, Status 379: mtc0 k1, _CP0_STATUS
\r
30158 BFD00D34 02FC034E MTC0 K0, EPC 380: mtc0 k0, _CP0_EPC
\r
30159 BFD00D38 18000000 SLL ZERO, ZERO, 3 381: ehb
\r
30160 BFD00D3C F37C0000 ERET 382: eret
\r
30161 BFD00D40 0C00 NOP 383: nop
\r
30163 385: .end vPortYieldISR
\r
30168 --- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S ---
\r
30169 1: /*********************************************************************
\r
30171 3: * C Runtime Startup
\r
30173 5: *********************************************************************
\r
30174 6: * Filename: crtn.s
\r
30176 8: * Processor: PIC32
\r
30178 10: * Compiler: MPLAB XC32
\r
30179 11: * MPLAB X IDE
\r
30180 12: * Company: Microchip Technology Inc.
\r
30182 14: * Software License Agreement
\r
30184 16: * This software is developed by Microchip Technology Inc. and its
\r
30185 17: * subsidiaries ("Microchip").
\r
30187 19: * Redistribution and use in source and binary forms, with or without
\r
30188 20: * modification, are permitted provided that the following conditions are met:
\r
30190 22: * 1. Redistributions of source code must retain the above copyright
\r
30191 23: * notice, this list of conditions and the following disclaimer.
\r
30193 25: * 2. Redistributions in binary form must reproduce the above copyright
\r
30194 26: * notice, this list of conditions and the following disclaimer in the
\r
30195 27: * documentation and/or other materials provided with the distribution.
\r
30197 29: * 3. Microchip's name may not be used to endorse or promote products
\r
30198 30: * derived from this software without specific prior written permission.
\r
30200 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
\r
30201 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
30202 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
\r
30203 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
\r
30204 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
\r
30205 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
\r
30206 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
\r
30207 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
\r
30208 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
\r
30209 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
30211 43: ********************************************************************/
\r
30213 45: #ifdef __LIBBUILD__
\r
30214 46: # Replace the standard debugging information with a simple filename. This
\r
30215 47: # prevents the library build directory from showing up in MPLAB IDE. It
\r
30216 48: # also effectively disables source-line debugging.
\r
30217 49: .file 1 "libpic32/startup/crtn.s"
\r
30221 53: .section .init, code
\r
30222 BFD00440 8FBF0014 LW RA, 20(SP) 54: lw $31,20($sp)
\r
30223 55: addu $sp,$sp,32
\r
30224 BFD00444 03E00008 JR RA 56: j $31
\r
30226 58: .section .fini, code
\r
30227 BFD00454 8FBF0014 LW RA, 20(SP) 59: lw $31,20($sp)
\r
30228 60: addu $sp,$sp,32
\r
30229 BFD00458 03E00008 JR RA 61: j $31
\r
30231 --- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S ---
\r
30232 1: /*********************************************************************
\r
30234 3: * C Runtime Startup
\r
30236 5: *********************************************************************
\r
30237 6: * Filename: crti.s
\r
30239 8: * Processor: PIC32
\r
30241 10: * Compiler: MPLAB XC32
\r
30242 11: * MPLAB X IDE
\r
30243 12: * Company: Microchip Technology Inc.
\r
30245 14: * Software License Agreement
\r
30247 16: * This software is developed by Microchip Technology Inc. and its
\r
30248 17: * subsidiaries ("Microchip").
\r
30250 19: * Redistribution and use in source and binary forms, with or without
\r
30251 20: * modification, are permitted provided that the following conditions are met:
\r
30253 22: * 1. Redistributions of source code must retain the above copyright
\r
30254 23: * notice, this list of conditions and the following disclaimer.
\r
30256 25: * 2. Redistributions in binary form must reproduce the above copyright
\r
30257 26: * notice, this list of conditions and the following disclaimer in the
\r
30258 27: * documentation and/or other materials provided with the distribution.
\r
30260 29: * 3. Microchip's name may not be used to endorse or promote products
\r
30261 30: * derived from this software without specific prior written permission.
\r
30263 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
\r
30264 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
30265 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
\r
30266 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
\r
30267 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
\r
30268 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
\r
30269 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
\r
30270 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
\r
30271 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
\r
30272 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
30274 43: ********************************************************************/
\r
30276 45: #ifdef __LIBBUILD__
\r
30277 46: # Replace the standard debugging information with a simple filename. This
\r
30278 47: # prevents the library build directory from showing up in MPLAB IDE. It
\r
30279 48: # also effectively disables source-line debugging.
\r
30280 49: .file 1 "libpic32/startup/crti.s"
\r
30284 53: /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
\r
30285 54: Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */
\r
30287 56: .section .init, code
\r
30289 58: .type _init,@function
\r
30291 BFD00438 27BDFFE0 ADDIU SP, SP, -32 60: addu $sp,$sp,-32
\r
30292 BFD0043C AFBF0014 SW RA, 20(SP) 61: sw $31,20($sp)
\r
30294 63: .section .fini, code
\r
30296 65: .type _fini,@function
\r
30298 BFD0044C 27BDFFE0 ADDIU SP, SP, -32 67: addu $sp,$sp,-32
\r
30299 BFD00450 AFBF0014 SW RA, 20(SP) 68: sw $31,20($sp)
\r
30300 --- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crt0.S ---
\r
30301 1: /*********************************************************************
\r
30303 3: * C Runtime Startup
\r
30305 5: *********************************************************************
\r
30306 6: * Filename: crt0.S
\r
30308 8: * Processor: PIC32
\r
30310 10: * Compiler: MPLAB XC32
\r
30311 11: * MPLAB X IDE
\r
30312 12: * Company: Microchip Technology Inc.
\r
30314 14: * Software License Agreement
\r
30316 16: * This software is developed by Microchip Technology Inc. and its
\r
30317 17: * subsidiaries ("Microchip").
\r
30319 19: * Redistribution and use in source and binary forms, with or without
\r
30320 20: * modification, are permitted provided that the following conditions are met:
\r
30322 22: * 1. Redistributions of source code must retain the above copyright
\r
30323 23: * notice, this list of conditions and the following disclaimer.
\r
30325 25: * 2. Redistributions in binary form must reproduce the above copyright
\r
30326 26: * notice, this list of conditions and the following disclaimer in the
\r
30327 27: * documentation and/or other materials provided with the distribution.
\r
30329 29: * 3. Microchip's name may not be used to endorse or promote products
\r
30330 30: * derived from this software without specific prior written permission.
\r
30332 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
\r
30333 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
30334 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
\r
30335 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
\r
30336 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
\r
30337 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
\r
30338 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
\r
30339 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
\r
30340 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
\r
30341 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
30343 43: ********************************************************************/
\r
30345 45: #include <xc.h>
\r
30346 46: #include <cp0defs.h>
\r
30348 48: /* MEC14xx */
\r
30349 49: #define PIC32_SRS_SET_COUNT 1
\r
30350 50: #define INIT_SSX
\r
30351 51: #undef INIT_MMU_MZ_FIXED
\r
30352 52: #undef INIT_L1_CACHE
\r
30354 54: /* MEC14xx fill stack with sentinel value */
\r
30355 55: #define EN_STACK_FILL */
\r
30357 57: #if (__XC32_VERSION > 1000) && !defined(CPP_INIT)
\r
30358 58: #define CPP_INIT
\r
30361 61: #if !defined(PIC32_SRS_SET_COUNT)
\r
30362 62: # warning PIC32_SRS_SET_COUNT not defined on build line
\r
30363 63: # define PIC32_SRS_SET_COUNT 2
\r
30366 66: #if !defined(STACK_FILL_VALUE)
\r
30367 67: # define STACK_FILL_VALUE 0xDEADBEEFul
\r
30370 70: /* This file contains 32-bit assembly code */
\r
30371 71: .set nomips16
\r
30373 73: ##################################################################
\r
30374 74: # Entry point of the entire application
\r
30375 75: ##################################################################
\r
30376 76: .section .reset,code,keep
\r
30378 78: .set noreorder
\r
30381 81: ############################
\r
30382 82: # Begin ISA switching code #
\r
30383 83: ############################
\r
30385 85: #if defined(__PIC32_HAS_MICROMIPS) || defined(__mips_micromips)
\r
30386 86: #if defined (__mips_micromips)
\r
30387 87: .set micromips
\r
30390 90: .word 0x10000003 /* MIPS32: branch to 0xBFC00010 from here */
\r
30391 91: /* MicroMIPS: ADDI32 $0, $0, 0x0007 (nop) */
\r
30392 92: /* DO NOT change the relative branch */
\r
30394 94: .word 0x00000000 /* NOP */
\r
30395 95: __reset_micromips_isa:
\r
30396 96: .set micromips
\r
30401 101: /* Device not in proper ISA mode */
\r
30402 102: .set nomicromips
\r
30403 103: __reset_switch_isa:
\r
30404 104: jal _startup
\r
30410 BFD00000 0FF400A2 JAL 0xBFD00288 110: jal _startup
\r
30411 BFD00004 00000000 NOP 111: nop
\r
30413 113: #endif /* __PIC32_HAS_MICROMIPS */
\r
30417 117: .globl _reset
\r
30418 118: .size _reset, .-_reset
\r
30420 120: .section .reset.startup,code,keep
\r
30422 122: .set noreorder
\r
30424 124: #if defined (__mips_micromips)
\r
30425 125: .set micromips
\r
30427 127: .set nomicromips
\r
30430 130: ############################
\r
30431 131: # End ISA switching code #
\r
30432 132: ############################
\r
30435 135: ##################################################################
\r
30436 136: # Startup code
\r
30437 137: ##################################################################
\r
30439 139: .set noreorder
\r
30440 140: .ent _startup
\r
30443 143: ##################################################################
\r
30444 144: # New - Set BEV=1 for the cases where M14K instruction pointer
\r
30445 145: # is changed to force ROM to run again. CP0.BEV must be 1 to
\r
30446 146: # safely write CP0.EBASE
\r
30447 147: ##################################################################
\r
30448 BFD00288 401A6000 MFC0 K0, Status 148: mfc0 k0, _CP0_STATUS
\r
30449 BFD0028C 3C1B0040 LUI K1, 64 149: lui k1, 0x0040
\r
30450 BFD00290 035BD025 OR K0, K0, K1 150: or k0, k0, k1 # CP0.STATUS.BEV(bit[22]) = 1
\r
30451 BFD00294 409A6000 MTC0 K0, Status 151: mtc0 k0, _CP0_STATUS
\r
30452 BFD00298 000000C0 EHB 152: ehb
\r
30454 154: ##################################################################
\r
30455 155: # Initialize Stack Pointer
\r
30456 156: # _stack is initialized by the linker script to point to the
\r
30457 157: # starting location of the stack in DRM
\r
30458 158: ##################################################################
\r
30459 BFD0029C 3C1DBFD2 LUI SP, -16430 159: la sp,_stack
\r
30461 161: ##################################################################
\r
30462 162: # Initialize Global Pointer
\r
30463 163: # _gp is initialized by the linker script to point to "middle"
\r
30464 164: # of the small variables region
\r
30465 165: ##################################################################
\r
30466 BFD002A4 3C1CBFD2 LUI GP, -16430 166: la gp,_gp
\r
30468 168: #if (PIC32_SRS_SET_COUNT == 2)
\r
30469 169: ##################################################################
\r
30470 170: # Initialize Global Pointer in Shadow Set
\r
30471 171: # The SRSCtl's PSS field must be set to the shadow set in which
\r
30472 172: # to initialize the global pointer. Since we have only a
\r
30473 173: # single shadow set (besides the normal), we will initialize
\r
30474 174: # SRSCtl<PSS> to SRSCtl<HSS>. We then write the global pointer
\r
30475 175: # to the previous shadow set to ensure that on interrupt, the
\r
30476 176: # global pointer has been initialized.
\r
30477 177: ##################################################################
\r
30478 178: mfc0 t1,_CP0_SRSCTL # Read SRSCtl register
\r
30479 179: add t3,t1,zero # Save off current SRSCtl
\r
30480 180: ext t2,t1,26,4 # to obtain HSS field
\r
30481 181: ins t1,t2,6,4 # Put HSS field
\r
30482 182: mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>
\r
30483 183: ehb # Clear hazard before using new SRSCTL
\r
30484 184: wrpgpr gp,gp # Set global pointer in PSS
\r
30485 185: mtc0 t3,_CP0_SRSCTL # Restore SRSCtl
\r
30488 188: #elif (PIC32_SRS_SET_COUNT > 2)
\r
30489 189: ##################################################################
\r
30490 190: # Initialize Global Pointer in Shadow Set(s)
\r
30491 191: # The SRSCtl PSS field must be set to the shadow set in which
\r
30492 192: # to initialize the global pointer. We will initialize
\r
30493 193: # SRSCtl<PSS> to the number of reg sets and work down to set zero.
\r
30494 194: # We write the global pointer to the previous shadow set to
\r
30495 195: # ensure that on interrupt, the global pointer has been
\r
30496 196: # initialized.
\r
30497 197: ##################################################################
\r
30498 198: mfc0 t1,_CP0_SRSCTL # Read SRSCtl register
\r
30499 199: add t3,t1,zero # Save off current SRSCtl
\r
30501 201: li t2,(PIC32_SRS_SET_COUNT-1)
\r
30503 203: 1: ins t1,t2,6,4 # Put next shadow set field
\r
30504 204: mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>
\r
30505 205: ehb # Clear hazard before using new SRSCTL
\r
30506 206: wrpgpr gp,gp # Set global pointer in PSS
\r
30508 208: addiu t2,t2,-1 # Next lower shadow set
\r
30509 209: # Loop for all sets
\r
30510 210: bne t2,$0,1b # Down to zero (normal GPR set)
\r
30513 213: mtc0 t3,_CP0_SRSCTL # Restore SRSCtl
\r
30516 216: #endif /* (PIC32_SRS_SET_COUNT > 2) */
\r
30518 218: ##################################################################
\r
30519 219: # Call the "on reset" procedure
\r
30520 220: ##################################################################
\r
30521 BFD002AC 3C08BFD1 LUI T0, -16431 221: la t0,_on_reset
\r
30522 BFD002B4 0100F809 JALR T0 222: jalr t0
\r
30523 BFD002B8 00000000 NOP 223: nop
\r
30525 225: #if defined(INIT_MMU_MZ_FIXED)
\r
30526 226: ##################################################################
\r
30527 227: # Initialize TLB for fixed mapping to EBI and SQI
\r
30528 228: ##################################################################
\r
30529 229: .extern __pic32_tlb_init_ebi_sqi
\r
30530 230: la t0,__pic32_tlb_init_ebi_sqi
\r
30535 235: #if defined(INIT_L1_CACHE)
\r
30536 236: ##################################################################
\r
30537 237: # Initialize L1 cache register
\r
30538 238: ##################################################################
\r
30539 239: .extern __pic32_init_cache
\r
30540 240: la t0,__pic32_init_cache
\r
30545 245: #if defined(EN_STACK_FILL)
\r
30546 246: ##################################################################
\r
30547 247: # Fill stack
\r
30548 248: # TODO - handle different stack lengths:
\r
30549 249: # mulitple of 4, 8, 16, or 32
\r
30550 250: ##################################################################
\r
30551 BFD002BC 3C08BFD2 LUI T0, -16430 251: la t0,_stack_start
\r
30552 BFD002C4 3C09BFD2 LUI T1, -16430 252: la t1,_stack
\r
30553 BFD002CC 10000005 BEQ ZERO, ZERO, 0xBFD002E4 253: b _stack_check
\r
30555 255: _stack_init:
\r
30556 BFD002D0 AD000000 SW ZERO, 0(T0) 256: sw zero,0x0(t0)
\r
30557 BFD002D4 AD000004 SW ZERO, 4(T0) 257: sw zero,0x4(t0)
\r
30558 BFD002D8 AD000008 SW ZERO, 8(T0) 258: sw zero,0x8(t0)
\r
30559 BFD002DC AD00000C SW ZERO, 12(T0) 259: sw zero,0xc(t0)
\r
30560 BFD002E0 25080010 ADDIU T0, T0, 16 260: addu t0,16
\r
30562 262: _stack_check:
\r
30563 BFD002E4 0109082B SLTU AT, T0, T1 263: bltu t0,t1,_stack_init
\r
30564 BFD002EC 00000000 NOP 264: nop
\r
30567 267: ##################################################################
\r
30568 268: # Clear uninitialized data sections
\r
30569 269: ##################################################################
\r
30570 BFD002F0 3C08BFD2 LUI T0, -16430 270: la t0,_bss_begin
\r
30571 BFD002F8 3C09BFD2 LUI T1, -16430 271: la t1,_bss_end
\r
30572 BFD00300 10000006 BEQ ZERO, ZERO, 0xBFD0031C 272: b _bss_check
\r
30573 BFD00304 00000000 NOP 273: nop
\r
30576 BFD00308 AD000000 SW ZERO, 0(T0) 276: sw zero,0x0(t0)
\r
30577 BFD0030C AD000004 SW ZERO, 4(T0) 277: sw zero,0x4(t0)
\r
30578 BFD00310 AD000008 SW ZERO, 8(T0) 278: sw zero,0x8(t0)
\r
30579 BFD00314 AD00000C SW ZERO, 12(T0) 279: sw zero,0xc(t0)
\r
30580 BFD00318 25080010 ADDIU T0, T0, 16 280: addu t0,16
\r
30582 BFD0031C 0109082B SLTU AT, T0, T1 282: bltu t0,t1,_bss_init
\r
30583 BFD00324 00000000 NOP 283: nop
\r
30585 285: ##################################################################
\r
30586 286: # Initialize data using the linker-generated .dinit table
\r
30587 287: ##################################################################
\r
30588 288: .equiv FMT_CLEAR,0
\r
30589 289: .equiv FMT_COPY,1
\r
30590 290: _dinit_init:
\r
30591 BFD00328 3C08BFD0 LUI T0, -16432 291: la t0,_dinit_addr
\r
30593 293: #define SRC t0
\r
30594 294: #define DST t1
\r
30595 295: #define LEN t2
\r
30596 296: #define FMT t3
\r
30598 BFD00330 8D090000 LW T1, 0(T0) 298: 0: lw DST,0(SRC)
\r
30599 BFD00334 11200018 BEQ T1, ZERO, 0xBFD00398 299: beqz DST,9f
\r
30600 BFD00338 25080004 ADDIU T0, T0, 4 300: addu SRC,4
\r
30601 BFD0033C 8D0A0000 LW T2, 0(T0) 301: lw LEN,0(SRC)
\r
30602 BFD00340 25080004 ADDIU T0, T0, 4 302: addu SRC,4
\r
30603 BFD00344 8D0B0000 LW T3, 0(T0) 303: lw FMT,0(SRC)
\r
30604 BFD00348 11600009 BEQ T3, ZERO, 0xBFD00370 304: beq FMT,$0,_dinit_clear
\r
30605 BFD0034C 25080004 ADDIU T0, T0, 4 305: addu SRC,4
\r
30607 307: _dinit_copy:
\r
30608 BFD00350 910C0000 LBU T4, 0(T0) 308: lbu t4,0(SRC)
\r
30609 BFD00354 254AFFFF ADDIU T2, T2, -1 309: subu LEN,1
\r
30610 BFD00358 25080001 ADDIU T0, T0, 1 310: addu SRC,1
\r
30611 BFD0035C A12C0000 SB T4, 0(T1) 311: sb t4,0(DST)
\r
30612 BFD00360 1540FFFB BNE T2, ZERO, 0xBFD00350 312: bne LEN,$0,_dinit_copy
\r
30613 BFD00364 25290001 ADDIU T1, T1, 1 313: addu DST,1
\r
30615 BFD00368 10000005 BEQ ZERO, ZERO, 0xBFD00380 315: b _dinit_end
\r
30616 BFD0036C 00000000 NOP 316: nop
\r
30618 318: _dinit_clear:
\r
30619 BFD00370 A1200000 SB ZERO, 0(T1) 319: sb $0,(DST)
\r
30620 BFD00374 254AFFFF ADDIU T2, T2, -1 320: subu LEN,1
\r
30621 BFD00378 1540FFFD BNE T2, ZERO, 0xBFD00370 321: bne LEN,$0,_dinit_clear
\r
30622 BFD0037C 25290001 ADDIU T1, T1, 1 322: addu DST,1
\r
30625 BFD00380 25080003 ADDIU T0, T0, 3 325: addu SRC,3
\r
30626 BFD00384 240AFFFC ADDIU T2, ZERO, -4 326: addiu LEN,$0,0xFFFFFFFC
\r
30627 BFD00388 01484024 AND T0, T2, T0 327: and SRC,LEN,SRC
\r
30628 BFD0038C 8D090000 LW T1, 0(T0) 328: lw DST,0(SRC)
\r
30629 BFD00390 1520FFE7 BNE T1, ZERO, 0xBFD00330 329: bne DST,$0,0b
\r
30630 BFD00394 00000000 NOP 330: nop
\r
30633 333: ##################################################################
\r
30634 334: # If there are no RAM functions, skip the next section --
\r
30635 335: # initializing bus matrix registers.
\r
30636 336: ##################################################################
\r
30637 BFD00398 3C090000 LUI T1, 0 337: la t1,_ramfunc_begin
\r
30638 BFD003A0 11200001 BEQ T1, ZERO, 0xBFD003A8 338: beqz t1,_ramfunc_done
\r
30639 BFD003A4 00000000 NOP 339: nop
\r
30641 341: #if defined(INIT_SSX)
\r
30642 342: /* No initialization required */
\r
30643 343: #else /* Use BMX */
\r
30644 344: ##################################################################
\r
30645 345: # Initialize bus matrix registers if RAM functions exist in the
\r
30646 346: # application
\r
30647 347: ##################################################################
\r
30648 348: la t1,_bmxdkpba_address
\r
30649 349: la t2,BMXDKPBA
\r
30651 351: la t1,_bmxdudba_address
\r
30652 352: la t2,BMXDUDBA
\r
30654 354: la t1,_bmxdupba_address
\r
30655 355: la t2,BMXDUPBA
\r
30657 357: #endif /* INIT_SSX */
\r
30659 359: _ramfunc_done:
\r
30661 361: ##################################################################
\r
30662 362: # Initialize CP0 registers
\r
30663 363: ##################################################################
\r
30664 364: # Initialize Count register
\r
30665 365: ##################################################################
\r
30666 BFD003A8 40804800 MTC0 ZERO, Count 366: mtc0 zero,_CP0_COUNT
\r
30668 368: ##################################################################
\r
30669 369: # Initialize Compare register
\r
30670 370: ##################################################################
\r
30671 BFD003AC 240AFFFF ADDIU T2, ZERO, -1 371: li t2,-1
\r
30672 BFD003B0 408A5800 MTC0 T2, Compare 372: mtc0 t2,_CP0_COMPARE
\r
30674 374: ##################################################################
\r
30675 375: # Initialize EBase register
\r
30676 376: ##################################################################
\r
30677 BFD003B4 3C09BFD0 LUI T1, -16432 377: la t1,_ebase_address
\r
30678 BFD003BC 40897801 MTC0 T1, EBase 378: mtc0 t1,_CP0_EBASE
\r
30680 380: ##################################################################
\r
30681 381: # Initialize IntCtl register
\r
30682 382: ##################################################################
\r
30683 BFD003C0 3C090000 LUI T1, 0 383: la t1,_vector_spacing
\r
30684 BFD003C8 240A0000 ADDIU T2, ZERO, 0 384: li t2,0 # Clear t2 and
\r
30685 BFD003CC 7D2A4944 INS T2, T1, 5, 5 385: ins t2,t1,5,5 # shift value to VS field
\r
30686 BFD003D0 408A6001 MTC0 T2, IntCtl 386: mtc0 t2,_CP0_INTCTL
\r
30688 388: ##################################################################
\r
30689 389: # Initialize CAUSE registers
\r
30690 390: # - Enable counting of Count register <DC = 0>
\r
30691 391: # - Use special exception vector <IV = 1>
\r
30692 392: # - Clear pending software interrupts <IP1:IP0 = 0>
\r
30693 393: ##################################################################
\r
30694 BFD003D4 3C090080 LUI T1, 128 394: li t1,0x00800000
\r
30695 BFD003D8 40896800 MTC0 T1, Cause 395: mtc0 t1,_CP0_CAUSE
\r
30697 397: ##################################################################
\r
30698 398: # Initialize STATUS register
\r
30699 399: # - Access to Coprocessor 0 not allowed in user mode <CU0 = 0>
\r
30700 400: # - User mode uses configured endianness <RE = 0>
\r
30701 401: # - Preserve Bootstrap Exception vectors <BEV>
\r
30702 402: # - Preserve soft reset <SR> and non-maskable interrupt <NMI>
\r
30703 403: # - CorExtend enabled based on whether CorExtend User Defined
\r
30704 404: # Instructions have been implemented <CEE = Config<UDI>>
\r
30705 405: # - Disable any pending interrups <IM7..IM2 = 0, IM1..IM0 = 0>
\r
30706 406: # - Disable hardware interrupts <IPL7:IPL2 = 0>
\r
30707 407: # - Base mode is Kernel mode <UM = 0>
\r
30708 408: # - Error level is normal <ERL = 0>
\r
30709 409: # - Exception level is normal <EXL = 0>
\r
30710 410: # - Interrupts are disabled <IE = 0>
\r
30711 411: # - DSPr2 ASE is enabled for devices that support it <MX = 1>
\r
30712 412: ##################################################################
\r
30713 BFD003DC 40088000 MFC0 T0, Config 413: mfc0 t0,_CP0_CONFIG
\r
30714 BFD003E0 7D090580 EXT T1, T0, 22, 1 414: ext t1,t0,22,1 # Extract UDI from Config register
\r
30715 BFD003E4 00094C40 SLL T1, T1, 17 415: sll t1,t1,17 # Move UDI to Status.CEE location
\r
30716 BFD003E8 40086000 MFC0 T0, Status 416: mfc0 t0,_CP0_STATUS
\r
30717 BFD003EC 3C010058 LUI AT, 88 417: and t0,t0,0x00580000 # Preserve SR, NMI, and BEV
\r
30718 418: #if defined(INIT_DSPR2)
\r
30719 419: li t2, 0x01000000 # Set the Status.MX bit to enable DSP
\r
30722 BFD003F4 01284025 OR T0, T1, T0 422: or t0,t1,t0 # Include Status.CEE (from UDI)
\r
30723 BFD003F8 40886000 MTC0 T0, Status 423: mtc0 t0,_CP0_STATUS
\r
30725 425: ##################################################################
\r
30726 426: # Call the "on bootstrap" procedure
\r
30727 427: ##################################################################
\r
30728 BFD003FC 3C08BFD1 LUI T0, -16431 428: la t0,_on_bootstrap
\r
30729 BFD00404 0100F809 JALR T0 429: jalr t0
\r
30730 BFD00408 00000000 NOP 430: nop
\r
30732 432: ##################################################################
\r
30733 433: # Initialize Status<BEV> for normal exception vectors
\r
30734 434: ##################################################################
\r
30735 BFD0040C 40086000 MFC0 T0, Status 435: mfc0 t0,_CP0_STATUS
\r
30736 BFD00410 3C01FFBF LUI AT, -65 436: and t0,t0,0xffbfffff # Clear BEV
\r
30737 BFD0041C 40886000 MTC0 T0, Status 437: mtc0 t0,_CP0_STATUS
\r
30739 439: ##################################################################
\r
30740 440: # Call main. We do this via a thunk in the text section so that
\r
30741 441: # a normal jump and link can be used, enabling the startup code
\r
30742 442: # to work properly whether main is written in MIPS16 or MIPS32
\r
30743 443: # code. I.e., the linker will correctly adjust the JAL to JALX if
\r
30745 445: ##################################################################
\r
30746 BFD00420 30840000 ANDI A0, A0, 0 446: and a0,a0,0
\r
30747 BFD00424 30A50000 ANDI A1, A1, 0 447: and a1,a1,0
\r
30748 BFD00428 3C08BFD0 LUI T0, -16432 448: la t0,_main_entry
\r
30749 BFD00430 01000008 JR T0 449: jr t0
\r
30750 BFD00434 00000000 NOP 450: nop
\r
30752 452: .end _startup
\r
30755 455: ##################################################################
\r
30756 456: # General Exception Vector Handler
\r
30757 457: # Jumps to _general_exception_context
\r
30758 458: ##################################################################
\r
30759 459: .section .gen_handler,code
\r
30760 460: .set noreorder
\r
30761 461: .ent _gen_exception
\r
30762 462: _gen_exception:
\r
30763 BFD00180 3C1ABFD0 LUI K0, -16432 463: 0: la k0,_general_exception_context
\r
30764 BFD00188 03400008 JR K0 464: jr k0
\r
30765 BFD0018C 00000000 NOP 465: nop
\r
30767 467: .end _gen_exception
\r
30769 469: #if defined(INIT_MMU_MZ_FIXED)
\r
30770 470: ##################################################################
\r
30771 471: # Simple TLB-Refill Exception Vector
\r
30772 472: # Jumps to _simple_tlb_refill_exception_context
\r
30773 473: ##################################################################
\r
30774 474: .section .simple_tlb_refill_vector,code,keep
\r
30775 475: .set noreorder
\r
30776 476: .ent simple_tlb_refill_vector
\r
30777 477: simple_tlb_refill_vector:
\r
30778 478: la k0,_simple_tlb_refill_exception_context
\r
30782 482: .end simple_tlb_refill_vector
\r
30785 485: #if defined(INIT_L1_CACHE)
\r
30786 486: ##################################################################
\r
30787 487: # Cache-Error Exception Vector Handler
\r
30788 488: # Jumps to _cache_err_exception_context
\r
30789 489: ##################################################################
\r
30790 490: .section .cache_err_vector,code,keep
\r
30791 491: .set noreorder
\r
30792 492: .ent _cache_err_vector
\r
30793 493: _cache_err_vector:
\r
30794 494: la k0,_cache_err_exception_context
\r
30798 498: .end _cache_err_vector
\r
30801 501: .section .text.main_entry,code,keep
\r
30802 502: .ent _main_entry
\r
30803 503: _main_entry:
\r
30805 505: #if defined(CPP_INIT)
\r
30807 507: # call .init section to run constructors etc
\r
30808 BFD06804 3C04BFD0 LUI A0, -16432 508: lui a0,%hi(_init)
\r
30809 BFD06808 27BDFFE8 ADDIU SP, SP, -24 509: addiu sp,sp,-24
\r
30810 BFD0680C 24840438 ADDIU A0, A0, 1080 510: addiu a0,a0,%lo(_init)
\r
30811 BFD06810 10800003 BEQ A0, ZERO, 0xBFD06820 511: beq a0,$0,2f
\r
30812 BFD06814 AFBF0014 SW RA, 20(SP) 512: sw $31,20(sp) #,
\r
30813 BFD06818 0080F809 JALR A0 513: jalr a0
\r
30814 BFD0681C 00000000 NOP 514: nop
\r
30817 BFD06820 30840000 ANDI A0, A0, 0 517: and a0,a0,0
\r
30818 BFD06824 30A50000 ANDI A1, A1, 0 518: and a1,a1,0
\r
30820 520: ##################################################################
\r
30823 523: ##################################################################
\r
30824 BFD06828 77F425B0 JALX 0xBFD096C0 524: jal main
\r
30825 BFD0682C 00000000 NOP 525: nop
\r
30827 527: #if defined(CALL_EXIT)
\r
30828 528: ##################################################################
\r
30829 529: # Call exit()
\r
30830 530: ##################################################################
\r
30835 535: ##################################################################
\r
30836 536: # Just in case, go into infinite loop
\r
30837 537: # Call a software breakpoint only with -mdebugger compiler option
\r
30838 538: ##################################################################
\r
30839 539: .weak __exception_handler_break
\r
30840 540: __crt0_exit:
\r
30842 BFD06830 3C020000 LUI V0, 0 542: la v0,__exception_handler_break
\r
30843 BFD06838 10400003 BEQ V0, ZERO, 0xBFD06848 543: beq v0,0,0f
\r
30844 BFD0683C 00000000 NOP 544: nop
\r
30845 BFD06840 0040F809 JALR V0 545: jalr v0
\r
30846 BFD06844 00000000 NOP 546: nop
\r
30848 BFD06848 1000FFF9 BEQ ZERO, ZERO, 0xBFD06830 548: 0: b 1b
\r
30849 BFD0684C 00000000 NOP 549: nop
\r
30851 551: .globl __crt0_exit
\r
30852 552: .end _main_entry
\r
30854 554: ###############################################################
\r
30856 556: ###############################################################
\r
30857 557: .globl rom_launch_fw
\r
30858 558: .set nomips16
\r
30859 559: .set micromips
\r
30860 560: .ent rom_launch_fw
\r
30861 561: .type rom_launch_fw, @function
\r
30863 563: rom_launch_fw:
\r
30865 565: .set noreorder
\r
30866 566: .set nomacro
\r
30869 BFD06850 477C0000 DI ZERO 569: di
\r
30871 BFD06854 18000000 SLL ZERO, ZERO, 3 571: ehb
\r
30873 BFD06858 0C00 NOP 573: nop
\r
30875 575: # turn off core timer
\r
30877 BFD0685A 00FC010D MFC0 T0, Cause 577: mfc0 t0, _CP0_CAUSE
\r
30879 BFD0685E F7FF41A9 LUI T1, 0xF7FF 579: lui t1, 0xf7ff
\r
30881 BFD06862 FFFF5129 ORI T1, T1, -1 581: ori t1, t1, 0xffff
\r
30883 BFD06866 42500128 AND T0, T0, T1 583: and t0, t0, t1
\r
30885 BFD0686A 02FC010D MTC0 T0, Cause 585: mtc0 t0, _CP0_CAUSE
\r
30887 BFD0686E 18000000 SLL ZERO, ZERO, 3 587: ehb
\r
30889 BFD06872 0C00 NOP 589: nop
\r
30891 BFD06874 00FC010C MFC0 T0, Status 591: mfc0 t0, _CP0_STATUS
\r
30893 BFD06878 004041A9 LUI T1, 0x40 593: lui t1, 0x0040
\r
30895 BFD0687C 42900128 OR T0, T0, T1 595: or t0, t0, t1 # BEV(bit[22]) = 1
\r
30897 BFD06880 02FC010C MTC0 T0, Status 597: mtc0 t0, _CP0_STATUS
\r
30899 BFD06884 18000000 SLL ZERO, ZERO, 3 599: ehb
\r
30901 BFD06888 0C00 NOP 601: nop
\r
30903 BFD0688A 1F3C0004 JALR.HB ZERO, A0 603: JR.HB a0
\r
30905 BFD0688E 00000000 NOP 605: nop
\r
30907 BFD06892 3449D7E8 J 0xBFD06892 607: j 0b # should not get here
\r
30909 BFD06896 0C00 NOP 609: nop
\r
30912 612: .set reorder
\r
30914 614: .end rom_launch_fw
\r
30915 615: .size rom_launch_fw, .-rom_launch_fw
\r
30917 --- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq24d.S ---
\r
30919 2: Copyright (C) 2014 Microchip Inc.
\r
30920 3: All rights reserved
\r
30922 5: 1 tab == 4 spaces!
\r
30926 9: #include <xc.h>
\r
30927 10: #include <sys/asm.h>
\r
30929 12: #include "Regs.S"
\r
30932 15: #include "MEC14xx/mec14xx_girqm.h"
\r
30934 17: /******************************************************************/
\r
30936 19: /***************************************************************
\r
30937 20: * MEC14xx GIRQ24 Disaggregated Vector Jump table
\r
30939 22: ***************************************************************/
\r
30941 24: .extern girq24_b0
\r
30942 25: .extern girq24_b1
\r
30943 26: .extern girq24_b2
\r
30945 28: #if GIRQ24_DISAGG != 0
\r
30948 31: * FreeRTOS Handler for MIPS M14K Software Interrupt 0
\r
30949 32: * implemented in the porting layer.
\r
30951 34: .extern vPortYieldISR
\r
30954 37: * Disaggregated girq24_isr
\r
30955 38: * Program address of this version of girq24_isr into JTVIC GIRQ24
\r
30956 39: * Aggregator Control register with bit[0] = 1.
\r
30960 43: * NOTE: All the additional labels surrounding every instruction are
\r
30961 44: * there to force GCC OBJDUMP to disassemble microMIPS correctly.
\r
30965 48: #ifdef __XC32
\r
30966 49: .section .girqs.girq24_isr, code
\r
30968 51: .section .girqs.girq24_isr,"x"
\r
30970 53: .set nomips16
\r
30971 54: .set micromips
\r
30972 55: .set noreorder
\r
30974 57: .ent girq24_isr
\r
30975 58: .global girq24_isr
\r
30979 BFD00270 32D4D7E8 J 0xBFD065A8 62: J girq24_b0
\r
30981 BFD00274 0C00 NOP 64: NOP
\r
30985 BFD00278 05B8D7E8 J 0xBFD00B70 68: J vPortYieldISR /* girq24_b1 */
\r
30987 BFD0027C 0C00 NOP 70: NOP
\r
30991 BFD00280 23A0D7E8 J 0xBFD04740 74: J girq24_b2
\r
30993 BFD00284 0C00 NOP 76: NOP
\r
30995 78: .end girq24_isr
\r
30999 82: /******************************************************************/
\r
31002 --- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq23d.S ---
\r
31004 2: Copyright (C) 2014 Microchip Inc.
\r
31005 3: All rights reserved
\r
31007 5: 1 tab == 4 spaces!
\r
31011 9: #include <xc.h>
\r
31012 10: #include <sys/asm.h>
\r
31014 12: #include "Regs.S"
\r
31017 15: #include "MEC14xx/mec14xx_girqm.h"
\r
31020 18: /***************************************************************
\r
31021 19: * MEC14xx GIRQ23 Disaggregated Vector Jump table
\r
31023 21: ***************************************************************/
\r
31025 23: .extern girq23_b0
\r
31026 24: .extern girq23_b1
\r
31027 25: .extern girq23_b2
\r
31028 26: .extern girq23_b3
\r
31029 27: .extern girq23_b4
\r
31030 28: .extern girq23_b5
\r
31031 29: .extern girq23_b6
\r
31032 30: .extern girq23_b7
\r
31033 31: .extern girq23_b8
\r
31034 32: .extern girq23_b9
\r
31035 33: .extern girq23_b10
\r
31036 34: .extern girq23_b11
\r
31037 35: .extern girq23_b12
\r
31038 36: .extern girq23_b13
\r
31040 38: #if GIRQ23_DISAGG != 0
\r
31043 41: * FreeRTOS Handler for MEC14xx RTOS Timer
\r
31044 42: * implemented in the porting layer.
\r
31046 44: .extern vPortTickInterruptHandler
\r
31049 47: * Disaggregated girq23_isr
\r
31050 48: * Program address of this version of girq23_isr into JTVIC GIRQ23
\r
31051 49: * Aggregator Control register with bit[0] = 1.
\r
31055 53: * NOTE: All the additional labels surrounding every instruction are
\r
31056 54: * there to force GCC OBJDUMP to disassemble microMIPS correctly.
\r
31060 58: #ifdef __XC32
\r
31061 59: .section .girqs.girq23_isr, code
\r
31063 61: .section .girqs.girq23_isr,"x"
\r
31065 63: .set nomips16
\r
31066 64: .set micromips
\r
31067 65: .set noreorder
\r
31069 67: .ent girq23_isr
\r
31070 68: .global girq23_isr
\r
31075 BFD00200 3950D7E8 J 0xBFD072A0 73: J girq23_b0
\r
31077 BFD00204 0C00 NOP 75: NOP
\r
31081 BFD00208 2638D7E8 J 0xBFD04C70 79: J girq23_b1
\r
31083 BFD0020C 0C00 NOP 81: NOP
\r
31087 BFD00210 26A0D7E8 J 0xBFD04D40 85: J girq23_b2
\r
31089 BFD00214 0C00 NOP 87: NOP
\r
31093 BFD00218 2708D7E8 J 0xBFD04E10 91: J girq23_b3
\r
31095 BFD0021C 0C00 NOP 93: NOP
\r
31099 BFD00220 0490D7E8 J 0xBFD00920 97: J girq23_b4
\r
31101 BFD00224 0C00 NOP 99: NOP
\r
31105 BFD00228 2770D7E8 J 0xBFD04EE0 103: J girq23_b5
\r
31107 BFD0022C 0C00 NOP 105: NOP
\r
31111 BFD00230 27D8D7E8 J 0xBFD04FB0 109: J girq23_b6
\r
31113 BFD00234 0C00 NOP 111: NOP
\r
31117 BFD00238 2840D7E8 J 0xBFD05080 115: J girq23_b7
\r
31119 BFD0023C 0C00 NOP 117: NOP
\r
31123 BFD00240 28A8D7E8 J 0xBFD05150 121: J girq23_b8
\r
31125 BFD00244 0C00 NOP 123: NOP
\r
31129 BFD00248 2910D7E8 J 0xBFD05220 127: J girq23_b9
\r
31131 BFD0024C 0C00 NOP 129: NOP
\r
31135 BFD00250 2978D7E8 J 0xBFD052F0 133: J girq23_b10
\r
31137 BFD00254 0C00 NOP 135: NOP
\r
31141 BFD00258 29E0D7E8 J 0xBFD053C0 139: J girq23_b11
\r
31143 BFD0025C 0C00 NOP 141: NOP
\r
31147 BFD00260 2A48D7E8 J 0xBFD05490 145: J girq23_b12
\r
31149 BFD00264 0C00 NOP 147: NOP
\r
31153 BFD00268 2AB0D7E8 J 0xBFD05560 151: J girq23_b13
\r
31155 BFD0026C 0C00 NOP 153: NOP
\r
31157 155: .end girq23_isr
\r
31161 159: /******************************************************************/
\r
31166 --- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/exceptions/MPLAB/general_exception_ctx.S
\r
31167 1: /*********************************************************************
\r
31169 3: * General Exception
\r
31171 5: *********************************************************************
\r
31172 6: * Filename: general-exception.S
\r
31174 8: * Processor: PIC32
\r
31176 10: * Compiler: MPLAB XC32 v1.00
\r
31177 11: * MPLAB X IDE
\r
31178 12: * Company: Microchip Technology Inc.
\r
31180 14: * Software License Agreement
\r
31182 16: * This software is developed by Microchip Technology Inc. and its
\r
31183 17: * subsidiaries ("Microchip").
\r
31185 19: * Redistribution and use in source and binary forms, with or without
\r
31186 20: * modification, are permitted provided that the following conditions are met:
\r
31188 22: * 1. Redistributions of source code must retain the above copyright
\r
31189 23: * notice, this list of conditions and the following disclaimer.
\r
31191 25: * 2. Redistributions in binary form must reproduce the above copyright
\r
31192 26: * notice, this list of conditions and the following disclaimer in the
\r
31193 27: * documentation and/or other materials provided with the distribution.
\r
31195 29: * 3. Microchip's name may not be used to endorse or promote products
\r
31196 30: * derived from this software without specific prior written permission.
\r
31198 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
\r
31199 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
31200 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
\r
31201 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
\r
31202 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
\r
31203 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
\r
31204 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
\r
31205 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
\r
31206 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
\r
31207 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
31209 43: ********************************************************************/
\r
31211 45: #include <xc.h>
\r
31212 46: #ifdef __LIBBUILD__
\r
31213 47: .file 1 "general-exception.S"
\r
31216 50: ###################
\r
31217 51: # Default general exception handler
\r
31218 52: ###################
\r
31220 54: .extern _general_exception_handler
\r
31222 56: .section .text.general_exception, code
\r
31223 57: .set noreorder
\r
31225 59: .set nomips16
\r
31226 60: .globl _general_exception_context
\r
31227 61: .ent _general_exception_context
\r
31229 63: _general_exception_context:
\r
31231 65: # Save off the non-callee saved registers that may get mucked with
\r
31232 BFD049E4 27BDFFA8 ADDIU SP, SP, -88 66: addiu sp, sp, -88
\r
31233 BFD049E8 AFA10004 SW AT, 4(SP) 67: sw $1, 4(sp)
\r
31234 BFD049EC AFA20008 SW V0, 8(SP) 68: sw v0, 8(sp)
\r
31235 BFD049F0 AFA3000C SW V1, 12(SP) 69: sw v1, 12(sp)
\r
31236 BFD049F4 AFA40010 SW A0, 16(SP) 70: sw a0, 16(sp)
\r
31237 BFD049F8 AFA50014 SW A1, 20(SP) 71: sw a1, 20(sp)
\r
31238 BFD049FC AFA60018 SW A2, 24(SP) 72: sw a2, 24(sp)
\r
31239 BFD04A00 AFA7001C SW A3, 28(SP) 73: sw a3, 28(sp)
\r
31240 BFD04A04 AFA80020 SW T0, 32(SP) 74: sw t0, 32(sp)
\r
31241 BFD04A08 AFA90024 SW T1, 36(SP) 75: sw t1, 36(sp)
\r
31242 BFD04A0C AFAA0028 SW T2, 40(SP) 76: sw t2, 40(sp)
\r
31243 BFD04A10 AFAB002C SW T3, 44(SP) 77: sw t3, 44(sp)
\r
31244 BFD04A14 AFAC0030 SW T4, 48(SP) 78: sw t4, 48(sp)
\r
31245 BFD04A18 AFAD0034 SW T5, 52(SP) 79: sw t5, 52(sp)
\r
31246 BFD04A1C AFAE0038 SW T6, 56(SP) 80: sw t6, 56(sp)
\r
31247 BFD04A20 AFAF003C SW T7, 60(SP) 81: sw t7, 60(sp)
\r
31248 BFD04A24 AFB80040 SW T8, 64(SP) 82: sw t8, 64(sp)
\r
31249 BFD04A28 AFB90044 SW T9, 68(SP) 83: sw t9, 68(sp)
\r
31250 BFD04A2C AFBF0048 SW RA, 72(SP) 84: sw ra, 72(sp)
\r
31251 BFD04A30 00004012 MFLO T0, 0 85: mflo t0
\r
31252 BFD04A34 AFA8004C SW T0, 76(SP) 86: sw t0, 76(sp)
\r
31253 BFD04A38 00004010 MFHI T0, 0 87: mfhi t0
\r
31254 BFD04A3C AFA80050 SW T0, 80(SP) 88: sw t0, 80(sp)
\r
31256 BFD04A40 3C1ABFD0 LUI K0, -16432 90: la k0,_general_exception_handler
\r
31257 BFD04A48 00000000 NOP 91: nop
\r
31259 93: # Pass Cause and Status to the handler function
\r
31260 BFD04A4C 40046800 MFC0 A0, Cause 94: mfc0 a0, _CP0_CAUSE
\r
31261 BFD04A50 40056000 MFC0 A1, Status 95: mfc0 a1, _CP0_STATUS
\r
31262 BFD04A54 0340F809 JALR K0 96: jalr k0
\r
31263 BFD04A58 00000000 NOP 97: nop
\r
31265 BFD04A5C 8FA80050 LW T0, 80(SP) 99: lw t0, 80(sp)
\r
31266 BFD04A60 01000011 MTHI T0, 0 100: mthi t0
\r
31267 BFD04A64 8FA8004C LW T0, 76(SP) 101: lw t0, 76(sp)
\r
31268 BFD04A68 01000013 MTLO T0, 0 102: mtlo t0
\r
31270 BFD04A6C 8FA10004 LW AT, 4(SP) 104: lw $1, 4(sp)
\r
31271 BFD04A70 8FA20008 LW V0, 8(SP) 105: lw v0, 8(sp)
\r
31272 BFD04A74 8FA3000C LW V1, 12(SP) 106: lw v1, 12(sp)
\r
31273 BFD04A78 8FA40010 LW A0, 16(SP) 107: lw a0, 16(sp)
\r
31274 BFD04A7C 8FA50014 LW A1, 20(SP) 108: lw a1, 20(sp)
\r
31275 BFD04A80 8FA60018 LW A2, 24(SP) 109: lw a2, 24(sp)
\r
31276 BFD04A84 8FA7001C LW A3, 28(SP) 110: lw a3, 28(sp)
\r
31277 BFD04A88 8FA80020 LW T0, 32(SP) 111: lw t0, 32(sp)
\r
31278 BFD04A8C 8FA90024 LW T1, 36(SP) 112: lw t1, 36(sp)
\r
31279 BFD04A90 8FAA0028 LW T2, 40(SP) 113: lw t2, 40(sp)
\r
31280 BFD04A94 8FAB002C LW T3, 44(SP) 114: lw t3, 44(sp)
\r
31281 BFD04A98 8FAC0030 LW T4, 48(SP) 115: lw t4, 48(sp)
\r
31282 BFD04A9C 8FAD0034 LW T5, 52(SP) 116: lw t5, 52(sp)
\r
31283 BFD04AA0 8FAE0038 LW T6, 56(SP) 117: lw t6, 56(sp)
\r
31284 BFD04AA4 8FAF003C LW T7, 60(SP) 118: lw t7, 60(sp)
\r
31285 BFD04AA8 8FB80040 LW T8, 64(SP) 119: lw t8, 64(sp)
\r
31286 BFD04AAC 8FB90044 LW T9, 68(SP) 120: lw t9, 68(sp)
\r
31287 BFD04AB0 8FBF0048 LW RA, 72(SP) 121: lw ra, 72(sp)
\r
31288 BFD04AB4 27BD0058 ADDIU SP, SP, 88 122: addiu sp, sp, 88
\r
31290 BFD04AB8 000000C0 EHB 124: ehb
\r
31291 BFD04ABC 42000018 ERET 125: eret
\r
31293 127: .end _general_exception_context
\r
projects / freertos / blob