git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Standard includes. */\r
  29 #include <stdint.h>\r
  30 \r
  31 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
  32  * is defined correctly and privileged functions are placed in correct sections. */\r
  33 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  34 \r
  35 /* Portasm includes. */\r
  36 #include "portasm.h"\r
  37 \r
  38 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
  39  * header files. */\r
  40 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  41 \r
  42 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
  43 {\r
  44         __asm volatile\r
  45         (\r
  46         "       .syntax unified                                                                 \n"\r
  47         "                                                                                                       \n"\r
  48         "       ldr  r2, pxCurrentTCBConst2                                             \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  49         "       ldr  r1, [r2]                                                                   \n" /* Read pxCurrentTCB. */\r
  50         "       ldr  r0, [r1]                                                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  51         "                                                                                                       \n"\r
  52         #if( configENABLE_MPU == 1 )\r
  53         "       dmb                                                                                             \n" /* Complete outstanding transfers before disabling MPU. */\r
  54         "       ldr r2, xMPUCTRLConst2                                                  \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  55         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
  56         "       bic r4, #1                                                                              \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
  57         "       str r4, [r2]                                                                    \n" /* Disable MPU. */\r
  58         "                                                                                                       \n"\r
  59         "       adds r1, #4                                                                             \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  60         "       ldr  r3, [r1]                                                                   \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
  61         "       ldr  r2, xMAIR0Const2                                                   \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  62         "       str  r3, [r2]                                                                   \n" /* Program MAIR0. */\r
  63         "       ldr  r2, xRNRConst2                                                             \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
  64         "       movs r3, #4                                                                             \n" /* r3 = 4. */\r
  65         "       str  r3, [r2]                                                                   \n" /* Program RNR = 4. */\r
  66         "       adds r1, #4                                                                             \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
  67         "       ldr  r2, xRBARConst2                                                    \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
  68         "       ldmia r1!, {r4-r11}                                                             \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
  69         "       stmia r2!, {r4-r11}                                                             \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  70         "                                                                                                       \n"\r
  71         "       ldr r2, xMPUCTRLConst2                                                  \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  72         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
  73         "       orr r4, #1                                                                              \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
  74         "       str r4, [r2]                                                                    \n" /* Enable MPU. */\r
  75         "       dsb                                                                                             \n" /* Force memory writes before continuing. */\r
  76         #endif /* configENABLE_MPU */\r
  77         "                                                                                                       \n"\r
  78         #if( configENABLE_MPU == 1 )\r
  79         "       ldm  r0!, {r1-r3}                                                               \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
  80         "       msr  psplim, r1                                                                 \n" /* Set this task's PSPLIM value. */\r
  81         "       msr  control, r2                                                                \n" /* Set this task's CONTROL value. */\r
  82         "       adds r0, #32                                                                    \n" /* Discard everything up to r0. */\r
  83         "       msr  psp, r0                                                                    \n" /* This is now the new top of stack to use in the task. */\r
  84         "       isb                                                                                             \n"\r
  85         "       bx   r3                                                                                 \n" /* Finally, branch to EXC_RETURN. */\r
  86         #else /* configENABLE_MPU */\r
  87         "       ldm  r0!, {r1-r2}                                                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
  88         "       msr  psplim, r1                                                                 \n" /* Set this task's PSPLIM value. */\r
  89         "       movs r1, #2                                                                             \n" /* r1 = 2. */\r
  90         "       msr  CONTROL, r1                                                                \n" /* Switch to use PSP in the thread mode. */\r
  91         "       adds r0, #32                                                                    \n" /* Discard everything up to r0. */\r
  92         "       msr  psp, r0                                                                    \n" /* This is now the new top of stack to use in the task. */\r
  93         "       isb                                                                                             \n"\r
  94         "       bx   r2                                                                                 \n" /* Finally, branch to EXC_RETURN. */\r
  95         #endif /* configENABLE_MPU */\r
  96         "                                                                                                       \n"\r
  97         "       .align 4                                                                                \n"\r
  98         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
  99         #if( configENABLE_MPU == 1 )\r
 100         "xMPUCTRLConst2: .word 0xe000ed94                                       \n"\r
 101         "xMAIR0Const2: .word 0xe000edc0                                         \n"\r
 102         "xRNRConst2: .word 0xe000ed98                                           \n"\r
 103         "xRBARConst2: .word 0xe000ed9c                                          \n"\r
 104         #endif /* configENABLE_MPU */\r
 105         );\r
 106 }\r
 107 /*-----------------------------------------------------------*/\r
 108 \r
 109 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 110 {\r
 111         __asm volatile\r
 112         (\r
 113         "       mrs r0, control                                                                 \n" /* r0 = CONTROL. */\r
 114         "       tst r0, #1                                                                              \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
 115         "       ite ne                                                                                  \n"\r
 116         "       movne r0, #0                                                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 117         "       moveq r0, #1                                                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 118         "       bx lr                                                                                   \n" /* Return. */\r
 119         "                                                                                                       \n"\r
 120         "       .align 4                                                                                \n"\r
 121         ::: "r0", "memory"\r
 122         );\r
 123 }\r
 124 /*-----------------------------------------------------------*/\r
 125 \r
 126 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 127 {\r
 128          __asm volatile\r
 129         (\r
 130         "       mrs  r0, control                                                                \n" /* Read the CONTROL register. */\r
 131         "       bic r0, #1                                                                              \n" /* Clear the bit 0. */\r
 132         "       msr  control, r0                                                                \n" /* Write back the new CONTROL value. */\r
 133         "       bx lr                                                                                   \n" /* Return to the caller. */\r
 134         ::: "r0", "memory"\r
 135         );\r
 136 }\r
 137 /*-----------------------------------------------------------*/\r
 138 \r
 139 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 140 {\r
 141         __asm volatile\r
 142         (\r
 143         "       mrs r0, control                                                                 \n" /* r0 = CONTROL. */\r
 144         "       orr r0, #1                                                                              \n" /* r0 = r0 | 1. */\r
 145         "       msr control, r0                                                                 \n" /* CONTROL = r0. */\r
 146         "       bx lr                                                                                   \n" /* Return to the caller. */\r
 147         :::"r0", "memory"\r
 148         );\r
 149 }\r
 150 /*-----------------------------------------------------------*/\r
 151 \r
 152 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 153 {\r
 154         __asm volatile\r
 155         (\r
 156         "       ldr r0, xVTORConst                                                              \n" /* Use the NVIC offset register to locate the stack. */\r
 157         "       ldr r0, [r0]                                                                    \n" /* Read the VTOR register which gives the address of vector table. */\r
 158         "       ldr r0, [r0]                                                                    \n" /* The first entry in vector table is stack pointer. */\r
 159         "       msr msp, r0                                                                             \n" /* Set the MSP back to the start of the stack. */\r
 160         "       cpsie i                                                                                 \n" /* Globally enable interrupts. */\r
 161         "       cpsie f                                                                                 \n"\r
 162         "       dsb                                                                                             \n"\r
 163         "       isb                                                                                             \n"\r
 164         "       svc %0                                                                                  \n" /* System call to start the first task. */\r
 165         "       nop                                                                                             \n"\r
 166         "                                                                                                       \n"\r
 167         "   .align 4                                                                            \n"\r
 168         "xVTORConst: .word 0xe000ed08                                           \n"\r
 169         :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
 170         );\r
 171 }\r
 172 /*-----------------------------------------------------------*/\r
 173 \r
 174 uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 175 {\r
 176         __asm volatile\r
 177         (\r
 178         "       mrs r0, PRIMASK                                                                 \n"\r
 179         "       cpsid i                                                                                 \n"\r
 180         "       bx lr                                                                                   \n"\r
 181         ::: "memory"\r
 182         );\r
 183 }\r
 184 /*-----------------------------------------------------------*/\r
 185 \r
 186 void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 187 {\r
 188         __asm volatile\r
 189         (\r
 190         "       msr PRIMASK, r0                                                                 \n"\r
 191         "       bx lr                                                                                   \n"\r
 192         ::: "memory"\r
 193         );\r
 194 }\r
 195 /*-----------------------------------------------------------*/\r
 196 \r
 197 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 198 {\r
 199         __asm volatile\r
 200         (\r
 201         "       .syntax unified                                                                 \n"\r
 202         "                                                                                                       \n"\r
 203         "       mrs r0, psp                                                                             \n" /* Read PSP in r0. */\r
 204         #if( configENABLE_FPU == 1 )\r
 205         "       tst lr, #0x10                                                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 206         "       it eq                                                                                   \n"\r
 207         "       vstmdbeq r0!, {s16-s31}                                                 \n" /* Store the FPU registers which are not saved automatically. */\r
 208         #endif /* configENABLE_FPU */\r
 209         #if( configENABLE_MPU == 1 )\r
 210         "       mrs r1, psplim                                                                  \n" /* r1 = PSPLIM. */\r
 211         "       mrs r2, control                                                                 \n" /* r2 = CONTROL. */\r
 212         "       mov r3, lr                                                                              \n" /* r3 = LR/EXC_RETURN. */\r
 213         "       stmdb r0!, {r1-r11}                                                             \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
 214         #else /* configENABLE_MPU */\r
 215         "       mrs r2, psplim                                                                  \n" /* r2 = PSPLIM. */\r
 216         "       mov r3, lr                                                                              \n" /* r3 = LR/EXC_RETURN. */\r
 217         "       stmdb r0!, {r2-r11}                                                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
 218         #endif /* configENABLE_MPU */\r
 219         "                                                                                                       \n"\r
 220         "       ldr r2, pxCurrentTCBConst                                               \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 221         "       ldr r1, [r2]                                                                    \n" /* Read pxCurrentTCB. */\r
 222         "       str r0, [r1]                                                                    \n" /* Save the new top of stack in TCB. */\r
 223         "                                                                                                       \n"\r
 224         "       cpsid i                                                                                 \n"\r
 225         "       bl vTaskSwitchContext                                                   \n"\r
 226         "       cpsie i                                                                                 \n"\r
 227         "                                                                                                       \n"\r
 228         "       ldr r2, pxCurrentTCBConst                                               \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 229         "       ldr r1, [r2]                                                                    \n" /* Read pxCurrentTCB. */\r
 230         "       ldr r0, [r1]                                                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 231         "                                                                                                       \n"\r
 232         #if( configENABLE_MPU == 1 )\r
 233         "       dmb                                                                                             \n" /* Complete outstanding transfers before disabling MPU. */\r
 234         "       ldr r2, xMPUCTRLConst                                                   \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 235         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
 236         "       bic r4, #1                                                                              \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 237         "       str r4, [r2]                                                                    \n" /* Disable MPU. */\r
 238         "                                                                                                       \n"\r
 239         "       adds r1, #4                                                                             \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 240         "       ldr r3, [r1]                                                                    \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
 241         "       ldr r2, xMAIR0Const                                                             \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 242         "       str r3, [r2]                                                                    \n" /* Program MAIR0. */\r
 243         "       ldr r2, xRNRConst                                                               \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
 244         "       movs r3, #4                                                                             \n" /* r3 = 4. */\r
 245         "       str r3, [r2]                                                                    \n" /* Program RNR = 4. */\r
 246         "       adds r1, #4                                                                             \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 247         "       ldr r2, xRBARConst                                                              \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 248         "       ldmia r1!, {r4-r11}                                                             \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 249         "       stmia r2!, {r4-r11}                                                             \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 250         "                                                                                                       \n"\r
 251         "       ldr r2, xMPUCTRLConst                                                   \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 252         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
 253         "       orr r4, #1                                                                              \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 254         "       str r4, [r2]                                                                    \n" /* Enable MPU. */\r
 255         "       dsb                                                                                             \n" /* Force memory writes before continuing. */\r
 256         #endif /* configENABLE_MPU */\r
 257         "                                                                                                       \n"\r
 258         #if( configENABLE_MPU == 1 )\r
 259         "       ldmia r0!, {r1-r11}                                                             \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
 260         #else /* configENABLE_MPU */\r
 261         "       ldmia r0!, {r2-r11}                                                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
 262         #endif /* configENABLE_MPU */\r
 263         "                                                                                                       \n"\r
 264         #if( configENABLE_FPU == 1 )\r
 265         "       tst r3, #0x10                                                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 266         "       it eq                                                                                   \n"\r
 267         "       vldmiaeq r0!, {s16-s31}                                                 \n" /* Restore the FPU registers which are not restored automatically. */\r
 268         #endif /* configENABLE_FPU */\r
 269         "                                                                                                       \n"\r
 270         #if( configENABLE_MPU == 1 )\r
 271         "       msr psplim, r1                                                                  \n" /* Restore the PSPLIM register value for the task. */\r
 272         "       msr control, r2                                                                 \n" /* Restore the CONTROL register value for the task. */\r
 273         #else /* configENABLE_MPU */\r
 274         "       msr psplim, r2                                                                  \n" /* Restore the PSPLIM register value for the task. */\r
 275         #endif /* configENABLE_MPU */\r
 276         "       msr psp, r0                                                                             \n" /* Remember the new top of stack for the task. */\r
 277         "       bx r3                                                                                   \n"\r
 278         "                                                                                                       \n"\r
 279         "       .align 4                                                                                \n"\r
 280         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 281         #if( configENABLE_MPU == 1 )\r
 282         "xMPUCTRLConst: .word 0xe000ed94                                        \n"\r
 283         "xMAIR0Const: .word 0xe000edc0                                          \n"\r
 284         "xRNRConst: .word 0xe000ed98                                            \n"\r
 285         "xRBARConst: .word 0xe000ed9c                                           \n"\r
 286         #endif /* configENABLE_MPU */\r
 287         );\r
 288 }\r
 289 /*-----------------------------------------------------------*/\r
 290 \r
 291 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 292 {\r
 293         __asm volatile\r
 294         (\r
 295         "       tst lr, #4                                                                              \n"\r
 296         "       ite eq                                                                                  \n"\r
 297         "       mrseq r0, msp                                                                   \n"\r
 298         "       mrsne r0, psp                                                                   \n"\r
 299         "       ldr r1, svchandler_address_const                                \n"\r
 300         "       bx r1                                                                                   \n"\r
 301         "                                                                                                       \n"\r
 302         "       .align 4                                                                                \n"\r
 303         "svchandler_address_const: .word vPortSVCHandler_C      \n"\r
 304         );\r
 305 }\r
 306 /*-----------------------------------------------------------*/\r