git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  14     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  15     >>!   obliged to provide the source code for proprietary components     !<<\r
  16     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  17 \r
  18     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  19     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  20     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  21     link: http://www.freertos.org/a00114.html\r
  22 \r
  23     1 tab == 4 spaces!\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  28      *    not run, what could be wrong?".  Have you defined configASSERT()?  *\r
  29      *                                                                       *\r
  30      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  31      *                                                                       *\r
  32     ***************************************************************************\r
  33 \r
  34     ***************************************************************************\r
  35      *                                                                       *\r
  36      *    FreeRTOS provides completely free yet professionally developed,    *\r
  37      *    robust, strictly quality controlled, supported, and cross          *\r
  38      *    platform software that is more than just the market leader, it     *\r
  39      *    is the industry's de facto standard.                               *\r
  40      *                                                                       *\r
  41      *    Help yourself get started quickly while simultaneously helping     *\r
  42      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
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  44      *    http://www.FreeRTOS.org/Documentation                              *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     ***************************************************************************\r
  49      *                                                                       *\r
  50      *   Investing in training allows your team to be as productive as       *\r
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  52      *   cost, and enabling you to bring a more robust product to market     *\r
  53      *   earlier than would otherwise be possible.  Richard Barry is both    *\r
  54      *   the architect and key author of FreeRTOS, and so also the world's   *\r
  55      *   leading authority on what is the world's most popular real time     *\r
  56      *   kernel for deeply embedded MCU designs.  Obtaining your training    *\r
  57      *   from Richard ensures your team will gain directly from his in-depth *\r
  58      *   product knowledge and years of usage experience.  Contact Real Time *\r
  59      *   Engineers Ltd to enquire about the FreeRTOS Masterclass, presented  *\r
  60      *   by Richard Barry:  http://www.FreeRTOS.org/contact\r
  61      *                                                                       *\r
  62     ***************************************************************************\r
  63 \r
  64     ***************************************************************************\r
  65      *                                                                       *\r
  66      *    You are receiving this top quality software for free.  Please play *\r
  67      *    fair and reciprocate by reporting any suspected issues and         *\r
  68      *    participating in the community forum:                              *\r
  69      *    http://www.FreeRTOS.org/support                                    *\r
  70      *                                                                       *\r
  71      *    Thank you!                                                         *\r
  72      *                                                                       *\r
  73     ***************************************************************************\r
  74 \r
  75     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  76     license and Real Time Engineers Ltd. contact details.\r
  77 \r
  78     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  79     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  80     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  81 \r
  82     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  83     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  84 \r
  85     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  86     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  87     licenses offer ticketed support, indemnification and commercial middleware.\r
  88 \r
  89     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  90     engineered and independently SIL3 certified version for use in safety and\r
  91     mission critical applications that require provable dependability.\r
  92 \r
  93     1 tab == 4 spaces!\r
  94 */\r
  95 \r
  96 /*-----------------------------------------------------------\r
  97  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  98  *----------------------------------------------------------*/\r
  99 \r
 100 /* Scheduler includes. */\r
 101 #include "FreeRTOS.h"\r
 102 #include "task.h"\r
 103 \r
 104 #ifndef __VFP_FP__\r
 105         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
 106 #endif\r
 107 \r
 108 #ifndef configSYSTICK_CLOCK_HZ\r
 109         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
 110         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
 111         #define portNVIC_SYSTICK_CLK_BIT        ( 1UL << 2UL )\r
 112 #else\r
 113         /* The way the SysTick is clocked is not modified in case it is not the same\r
 114         as the core. */\r
 115         #define portNVIC_SYSTICK_CLK_BIT        ( 0 )\r
 116 #endif\r
 117 \r
 118 /* Constants required to manipulate the core.  Registers first... */\r
 119 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
 120 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
 121 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
 122 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
 123 /* ...then bits in the registers. */\r
 124 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
 125 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 126 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 127 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 128 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 129 \r
 130 #define portNVIC_PENDSV_PRI                                     ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 131 #define portNVIC_SYSTICK_PRI                            ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 132 \r
 133 /* Constants required to check the validity of an interrupt priority. */\r
 134 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 135 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 136 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 137 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 138 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 139 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 140 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 141 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 142 \r
 143 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
 144 #define portVECTACTIVE_MASK                                     ( 0xFFUL )\r
 145 \r
 146 /* Constants required to manipulate the VFP. */\r
 147 #define portFPCCR                                       ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
 148 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
 149 \r
 150 /* Constants required to set up the initial stack. */\r
 151 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 152 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 153 \r
 154 /* The systick is a 24-bit counter. */\r
 155 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 156 \r
 157 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 158 occurred while the SysTick counter is stopped during tickless idle\r
 159 calculations. */\r
 160 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 161 \r
 162 /* Let the user override the pre-loading of the initial LR with the address of\r
 163 prvTaskExitError() in case is messes up unwinding of the stack in the\r
 164 debugger. */\r
 165 #ifdef configTASK_RETURN_ADDRESS\r
 166         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
 167 #else\r
 168         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 169 #endif\r
 170 \r
 171 /* Each task maintains its own interrupt status in the critical nesting\r
 172 variable. */\r
 173 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 174 \r
 175 /*\r
 176  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 177  * file is weak to allow application writers to change the timer used to\r
 178  * generate the tick interrupt.\r
 179  */\r
 180 void vPortSetupTimerInterrupt( void );\r
 181 \r
 182 /*\r
 183  * Exception handlers.\r
 184  */\r
 185 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 186 void xPortSysTickHandler( void );\r
 187 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 188 \r
 189 /*\r
 190  * Start first task is a separate function so it can be tested in isolation.\r
 191  */\r
 192 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 193 \r
 194 /*\r
 195  * Function to enable the VFP.\r
 196  */\r
 197  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 198 \r
 199 /*\r
 200  * Used to catch tasks that attempt to return from their implementing function.\r
 201  */\r
 202 static void prvTaskExitError( void );\r
 203 \r
 204 /*-----------------------------------------------------------*/\r
 205 \r
 206 /*\r
 207  * The number of SysTick increments that make up one tick period.\r
 208  */\r
 209 #if configUSE_TICKLESS_IDLE == 1\r
 210         static uint32_t ulTimerCountsForOneTick = 0;\r
 211 #endif /* configUSE_TICKLESS_IDLE */\r
 212 \r
 213 /*\r
 214  * The maximum number of tick periods that can be suppressed is limited by the\r
 215  * 24 bit resolution of the SysTick timer.\r
 216  */\r
 217 #if configUSE_TICKLESS_IDLE == 1\r
 218         static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
 219 #endif /* configUSE_TICKLESS_IDLE */\r
 220 \r
 221 /*\r
 222  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 223  * power functionality only.\r
 224  */\r
 225 #if configUSE_TICKLESS_IDLE == 1\r
 226         static uint32_t ulStoppedTimerCompensation = 0;\r
 227 #endif /* configUSE_TICKLESS_IDLE */\r
 228 \r
 229 /*\r
 230  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 231  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 232  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 233  */\r
 234 #if ( configASSERT_DEFINED == 1 )\r
 235          static uint8_t ucMaxSysCallPriority = 0;\r
 236          static uint32_t ulMaxPRIGROUPValue = 0;\r
 237          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 238 #endif /* configASSERT_DEFINED */\r
 239 \r
 240 /*-----------------------------------------------------------*/\r
 241 \r
 242 /*\r
 243  * See header file for description.\r
 244  */\r
 245 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 246 {\r
 247         /* Simulate the stack frame as it would be created by a context switch\r
 248         interrupt. */\r
 249 \r
 250         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 251         of interrupts, and to ensure alignment. */\r
 252         pxTopOfStack--;\r
 253 \r
 254         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 255         pxTopOfStack--;\r
 256         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 257         pxTopOfStack--;\r
 258         *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 259 \r
 260         /* Save code space by skipping register initialisation. */\r
 261         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 262         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 263 \r
 264         /* A save method is being used that requires each task to maintain its\r
 265         own exec return value. */\r
 266         pxTopOfStack--;\r
 267         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 268 \r
 269         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 270 \r
 271         return pxTopOfStack;\r
 272 }\r
 273 /*-----------------------------------------------------------*/\r
 274 \r
 275 static void prvTaskExitError( void )\r
 276 {\r
 277         /* A function that implements a task must not exit or attempt to return to\r
 278         its caller as there is nothing to return to.  If a task wants to exit it\r
 279         should instead call vTaskDelete( NULL ).\r
 280 \r
 281         Artificially force an assert() to be triggered if configASSERT() is\r
 282         defined, then stop here so application writers can catch the error. */\r
 283         configASSERT( uxCriticalNesting == ~0UL );\r
 284         portDISABLE_INTERRUPTS();\r
 285         for( ;; );\r
 286 }\r
 287 /*-----------------------------------------------------------*/\r
 288 \r
 289 void vPortSVCHandler( void )\r
 290 {\r
 291         __asm volatile (\r
 292                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 293                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 294                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 295                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 296                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 297                                         "       isb                                                             \n"\r
 298                                         "       mov r0, #0                                              \n"\r
 299                                         "       msr     basepri, r0                                     \n"\r
 300                                         "       bx r14                                                  \n"\r
 301                                         "                                                                       \n"\r
 302                                         "       .align 2                                                \n"\r
 303                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 304                                 );\r
 305 }\r
 306 /*-----------------------------------------------------------*/\r
 307 \r
 308 static void prvPortStartFirstTask( void )\r
 309 {\r
 310         __asm volatile(\r
 311                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 312                                         " ldr r0, [r0]                  \n"\r
 313                                         " ldr r0, [r0]                  \n"\r
 314                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 315                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 316                                         " cpsie f                               \n"\r
 317                                         " dsb                                   \n"\r
 318                                         " isb                                   \n"\r
 319                                         " svc 0                                 \n" /* System call to start first task. */\r
 320                                         " nop                                   \n"\r
 321                                 );\r
 322 }\r
 323 /*-----------------------------------------------------------*/\r
 324 \r
 325 /*\r
 326  * See header file for description.\r
 327  */\r
 328 BaseType_t xPortStartScheduler( void )\r
 329 {\r
 330         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 331         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 332         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 333 \r
 334         #if( configASSERT_DEFINED == 1 )\r
 335         {\r
 336                 volatile uint32_t ulOriginalPriority;\r
 337                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 338                 volatile uint8_t ucMaxPriorityValue;\r
 339 \r
 340                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 341                 functions can be called.  ISR safe functions are those that end in\r
 342                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 343                 ensure interrupt entry is as fast and simple as possible.\r
 344 \r
 345                 Save the interrupt priority value that is about to be clobbered. */\r
 346                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 347 \r
 348                 /* Determine the number of priority bits available.  First write to all\r
 349                 possible bits. */\r
 350                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 351 \r
 352                 /* Read the value back to see how many bits stuck. */\r
 353                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 354 \r
 355                 /* Use the same mask on the maximum system call priority. */\r
 356                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 357 \r
 358                 /* Calculate the maximum acceptable priority group value for the number\r
 359                 of bits read back. */\r
 360                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 361                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 362                 {\r
 363                         ulMaxPRIGROUPValue--;\r
 364                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 365                 }\r
 366 \r
 367                 /* Shift the priority group value back to its position within the AIRCR\r
 368                 register. */\r
 369                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 370                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 371 \r
 372                 /* Restore the clobbered interrupt priority register to its original\r
 373                 value. */\r
 374                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 375         }\r
 376         #endif /* conifgASSERT_DEFINED */\r
 377 \r
 378         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 379         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 380         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 381 \r
 382         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 383         here already. */\r
 384         vPortSetupTimerInterrupt();\r
 385 \r
 386         /* Initialise the critical nesting count ready for the first task. */\r
 387         uxCriticalNesting = 0;\r
 388 \r
 389         /* Ensure the VFP is enabled - it should be anyway. */\r
 390         vPortEnableVFP();\r
 391 \r
 392         /* Lazy save always. */\r
 393         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 394 \r
 395         /* Start the first task. */\r
 396         prvPortStartFirstTask();\r
 397 \r
 398         /* Should never get here as the tasks will now be executing!  Call the task\r
 399         exit error function to prevent compiler warnings about a static function\r
 400         not being called in the case that the application writer overrides this\r
 401         functionality by defining configTASK_RETURN_ADDRESS. */\r
 402         prvTaskExitError();\r
 403 \r
 404         /* Should not get here! */\r
 405         return 0;\r
 406 }\r
 407 /*-----------------------------------------------------------*/\r
 408 \r
 409 void vPortEndScheduler( void )\r
 410 {\r
 411         /* Not implemented in ports where there is nothing to return to.\r
 412         Artificially force an assert. */\r
 413         configASSERT( uxCriticalNesting == 1000UL );\r
 414 }\r
 415 /*-----------------------------------------------------------*/\r
 416 \r
 417 void vPortEnterCritical( void )\r
 418 {\r
 419         portDISABLE_INTERRUPTS();\r
 420         uxCriticalNesting++;\r
 421 \r
 422         /* This is not the interrupt safe version of the enter critical function so\r
 423         assert() if it is being called from an interrupt context.  Only API\r
 424         functions that end in "FromISR" can be used in an interrupt.  Only assert if\r
 425         the critical nesting count is 1 to protect against recursive calls if the\r
 426         assert function also uses a critical section. */\r
 427         if( uxCriticalNesting == 1 )\r
 428         {\r
 429                 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
 430         }\r
 431 }\r
 432 /*-----------------------------------------------------------*/\r
 433 \r
 434 void vPortExitCritical( void )\r
 435 {\r
 436         configASSERT( uxCriticalNesting );\r
 437         uxCriticalNesting--;\r
 438         if( uxCriticalNesting == 0 )\r
 439         {\r
 440                 portENABLE_INTERRUPTS();\r
 441         }\r
 442 }\r
 443 /*-----------------------------------------------------------*/\r
 444 \r
 445 void xPortPendSVHandler( void )\r
 446 {\r
 447         /* This is a naked function. */\r
 448 \r
 449         __asm volatile\r
 450         (\r
 451         "       mrs r0, psp                                                     \n"\r
 452         "       isb                                                                     \n"\r
 453         "                                                                               \n"\r
 454         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 455         "       ldr     r2, [r3]                                                \n"\r
 456         "                                                                               \n"\r
 457         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 458         "       it eq                                                           \n"\r
 459         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 460         "                                                                               \n"\r
 461         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 462         "                                                                               \n"\r
 463         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 464         "                                                                               \n"\r
 465         "       stmdb sp!, {r3}                                         \n"\r
 466         "       mov r0, %0                                                      \n"\r
 467         "       msr basepri, r0                                         \n"\r
 468         "       dsb                                                                     \n"\r
 469         "   isb                                                                 \n"\r
 470         "       bl vTaskSwitchContext                           \n"\r
 471         "       mov r0, #0                                                      \n"\r
 472         "       msr basepri, r0                                         \n"\r
 473         "       ldmia sp!, {r3}                                         \n"\r
 474         "                                                                               \n"\r
 475         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 476         "       ldr r0, [r1]                                            \n"\r
 477         "                                                                               \n"\r
 478         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 479         "                                                                               \n"\r
 480         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 481         "       it eq                                                           \n"\r
 482         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 483         "                                                                               \n"\r
 484         "       msr psp, r0                                                     \n"\r
 485         "       isb                                                                     \n"\r
 486         "                                                                               \n"\r
 487         #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\r
 488                 #if WORKAROUND_PMU_CM001 == 1\r
 489         "                       push { r14 }                            \n"\r
 490         "                       pop { pc }                                      \n"\r
 491                 #endif\r
 492         #endif\r
 493         "                                                                               \n"\r
 494         "       bx r14                                                          \n"\r
 495         "                                                                               \n"\r
 496         "       .align 2                                                        \n"\r
 497         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 498         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 499         );\r
 500 }\r
 501 /*-----------------------------------------------------------*/\r
 502 \r
 503 void xPortSysTickHandler( void )\r
 504 {\r
 505         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 506         executes all interrupts must be unmasked.  There is therefore no need to\r
 507         save and then restore the interrupt mask value as its value is already\r
 508         known. */\r
 509         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 510         {\r
 511                 /* Increment the RTOS tick. */\r
 512                 if( xTaskIncrementTick() != pdFALSE )\r
 513                 {\r
 514                         /* A context switch is required.  Context switching is performed in\r
 515                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 516                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 517                 }\r
 518         }\r
 519         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 520 }\r
 521 /*-----------------------------------------------------------*/\r
 522 \r
 523 #if configUSE_TICKLESS_IDLE == 1\r
 524 \r
 525         __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
 526         {\r
 527         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
 528         TickType_t xModifiableIdleTime;\r
 529 \r
 530                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 531                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 532                 {\r
 533                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 534                 }\r
 535 \r
 536                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 537                 is accounted for as best it can be, but using the tickless mode will\r
 538                 inevitably result in some tiny drift of the time maintained by the\r
 539                 kernel with respect to calendar time. */\r
 540                 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
 541 \r
 542                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 543                 tick periods.  -1 is used because this code will execute part way\r
 544                 through one of the tick periods. */\r
 545                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 546                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 547                 {\r
 548                         ulReloadValue -= ulStoppedTimerCompensation;\r
 549                 }\r
 550 \r
 551                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 552                 method as that will mask interrupts that should exit sleep mode. */\r
 553                 __asm volatile( "cpsid i" );\r
 554 \r
 555                 /* If a context switch is pending or a task is waiting for the scheduler\r
 556                 to be unsuspended then abandon the low power entry. */\r
 557                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 558                 {\r
 559                         /* Restart from whatever is left in the count register to complete\r
 560                         this tick period. */\r
 561                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 562 \r
 563                         /* Restart SysTick. */\r
 564                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 565 \r
 566                         /* Reset the reload register to the value required for normal tick\r
 567                         periods. */\r
 568                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 569 \r
 570                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 571                         above. */\r
 572                         __asm volatile( "cpsie i" );\r
 573                 }\r
 574                 else\r
 575                 {\r
 576                         /* Set the new reload value. */\r
 577                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 578 \r
 579                         /* Clear the SysTick count flag and set the count value back to\r
 580                         zero. */\r
 581                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 582 \r
 583                         /* Restart SysTick. */\r
 584                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 585 \r
 586                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 587                         set its parameter to 0 to indicate that its implementation contains\r
 588                         its own wait for interrupt or wait for event instruction, and so wfi\r
 589                         should not be executed again.  However, the original expected idle\r
 590                         time variable must remain unmodified, so a copy is taken. */\r
 591                         xModifiableIdleTime = xExpectedIdleTime;\r
 592                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 593                         if( xModifiableIdleTime > 0 )\r
 594                         {\r
 595                                 __asm volatile( "dsb" );\r
 596                                 __asm volatile( "wfi" );\r
 597                                 __asm volatile( "isb" );\r
 598                         }\r
 599                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 600 \r
 601                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 602                         accounted for as best it can be, but using the tickless mode will\r
 603                         inevitably result in some tiny drift of the time maintained by the\r
 604                         kernel with respect to calendar time. */\r
 605                         ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
 606                         portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
 607 \r
 608                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 609                         above. */\r
 610                         __asm volatile( "cpsie i" );\r
 611 \r
 612                         if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 613                         {\r
 614                                 uint32_t ulCalculatedLoadValue;\r
 615 \r
 616                                 /* The tick interrupt has already executed, and the SysTick\r
 617                                 count reloaded with ulReloadValue.  Reset the\r
 618                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 619                                 period. */\r
 620                                 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 621 \r
 622                                 /* Don't allow a tiny value, or values that have somehow\r
 623                                 underflowed because the post sleep hook did something\r
 624                                 that took too long. */\r
 625                                 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
 626                                 {\r
 627                                         ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
 628                                 }\r
 629 \r
 630                                 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
 631 \r
 632                                 /* The tick interrupt handler will already have pended the tick\r
 633                                 processing in the kernel.  As the pending tick will be\r
 634                                 processed as soon as this function exits, the tick value\r
 635                                 maintained by the tick is stepped forward by one less than the\r
 636                                 time spent waiting. */\r
 637                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 638                         }\r
 639                         else\r
 640                         {\r
 641                                 /* Something other than the tick interrupt ended the sleep.\r
 642                                 Work out how long the sleep lasted rounded to complete tick\r
 643                                 periods (not the ulReload value which accounted for part\r
 644                                 ticks). */\r
 645                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 646 \r
 647                                 /* How many complete tick periods passed while the processor\r
 648                                 was waiting? */\r
 649                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 650 \r
 651                                 /* The reload value is set to whatever fraction of a single tick\r
 652                                 period remains. */\r
 653                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 654                         }\r
 655 \r
 656                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 657                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 658                         value.  The critical section is used to ensure the tick interrupt\r
 659                         can only execute once in the case that the reload register is near\r
 660                         zero. */\r
 661                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 662                         portENTER_CRITICAL();\r
 663                         {\r
 664                                 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 665                                 vTaskStepTick( ulCompleteTickPeriods );\r
 666                                 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 667                         }\r
 668                         portEXIT_CRITICAL();\r
 669                 }\r
 670         }\r
 671 \r
 672 #endif /* #if configUSE_TICKLESS_IDLE */\r
 673 /*-----------------------------------------------------------*/\r
 674 \r
 675 /*\r
 676  * Setup the systick timer to generate the tick interrupts at the required\r
 677  * frequency.\r
 678  */\r
 679 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 680 {\r
 681         /* Calculate the constants required to configure the tick interrupt. */\r
 682         #if configUSE_TICKLESS_IDLE == 1\r
 683         {\r
 684                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 685                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 686                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 687         }\r
 688         #endif /* configUSE_TICKLESS_IDLE */\r
 689 \r
 690         /* Configure SysTick to interrupt at the requested rate. */\r
 691         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 692         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
 693 }\r
 694 /*-----------------------------------------------------------*/\r
 695 \r
 696 /* This is a naked function. */\r
 697 static void vPortEnableVFP( void )\r
 698 {\r
 699         __asm volatile\r
 700         (\r
 701                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 702                 "       ldr r1, [r0]                            \n"\r
 703                 "                                                               \n"\r
 704                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 705                 "       str r1, [r0]                            \n"\r
 706                 "       bx r14                                          "\r
 707         );\r
 708 }\r
 709 /*-----------------------------------------------------------*/\r
 710 \r
 711 #if( configASSERT_DEFINED == 1 )\r
 712 \r
 713         void vPortValidateInterruptPriority( void )\r
 714         {\r
 715         uint32_t ulCurrentInterrupt;\r
 716         uint8_t ucCurrentPriority;\r
 717 \r
 718                 /* Obtain the number of the currently executing interrupt. */\r
 719                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 720 \r
 721                 /* Is the interrupt number a user defined interrupt? */\r
 722                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 723                 {\r
 724                         /* Look up the interrupt's priority. */\r
 725                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 726 \r
 727                         /* The following assertion will fail if a service routine (ISR) for\r
 728                         an interrupt that has been assigned a priority above\r
 729                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 730                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 731                         from interrupts that have been assigned a priority at or below\r
 732                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 733 \r
 734                         Numerically low interrupt priority numbers represent logically high\r
 735                         interrupt priorities, therefore the priority of the interrupt must\r
 736                         be set to a value equal to or numerically *higher* than\r
 737                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 738 \r
 739                         Interrupts that use the FreeRTOS API must not be left at their\r
 740                         default priority of     zero as that is the highest possible priority,\r
 741                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 742                         and     therefore also guaranteed to be invalid.\r
 743 \r
 744                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 745                         interrupt entry is as fast and simple as possible.\r
 746 \r
 747                         The following links provide detailed information:\r
 748                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 749                         http://www.freertos.org/FAQHelp.html */\r
 750                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 751                 }\r
 752 \r
 753                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 754                 that define each interrupt's priority to be split between bits that\r
 755                 define the interrupt's pre-emption priority bits and bits that define\r
 756                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 757                 to be pre-emption priority bits.  The following assertion will fail if\r
 758                 this is not the case (if some bits represent a sub-priority).\r
 759 \r
 760                 If the application only uses CMSIS libraries for interrupt\r
 761                 configuration then the correct setting can be achieved on all Cortex-M\r
 762                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 763                 scheduler.  Note however that some vendor specific peripheral libraries\r
 764                 assume a non-zero priority group setting, in which cases using a value\r
 765                 of zero will result in unpredicable behaviour. */\r
 766                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 767         }\r
 768 \r
 769 #endif /* configASSERT_DEFINED */\r
 770 \r
 771 \r