2 * FreeRTOS Kernel V10.3.0
\r
3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /*-----------------------------------------------------------
\r
29 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
30 *----------------------------------------------------------*/
\r
32 /* Scheduler includes. */
\r
33 #include "FreeRTOS.h"
\r
37 #error This port can only be used when the project options are configured to enable hardware floating point support.
\r
40 #ifndef configSYSTICK_CLOCK_HZ
\r
41 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
42 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
43 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
45 /* The way the SysTick is clocked is not modified in case it is not the same
\r
47 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
50 /* Constants required to manipulate the core. Registers first... */
\r
51 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
52 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
53 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
54 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
55 /* ...then bits in the registers. */
\r
56 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
57 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
58 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
59 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
60 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
62 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
\r
64 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
\r
65 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
\r
66 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
\r
68 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
69 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
71 /* Constants required to check the validity of an interrupt priority. */
\r
72 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
73 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
74 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
75 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
76 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
77 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
78 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
79 #define portPRIGROUP_SHIFT ( 8UL )
\r
81 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
82 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
84 /* Constants required to manipulate the VFP. */
\r
85 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
\r
86 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
88 /* Constants required to set up the initial stack. */
\r
89 #define portINITIAL_XPSR ( 0x01000000 )
\r
90 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
\r
92 /* The systick is a 24-bit counter. */
\r
93 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
95 /* For strict compliance with the Cortex-M spec the task start address should
\r
96 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
\r
97 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
\r
99 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
100 occurred while the SysTick counter is stopped during tickless idle
\r
102 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
104 /* Let the user override the pre-loading of the initial LR with the address of
\r
105 prvTaskExitError() in case it messes up unwinding of the stack in the
\r
107 #ifdef configTASK_RETURN_ADDRESS
\r
108 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
110 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
114 * Setup the timer to generate the tick interrupts. The implementation in this
\r
115 * file is weak to allow application writers to change the timer used to
\r
116 * generate the tick interrupt.
\r
118 void vPortSetupTimerInterrupt( void );
\r
121 * Exception handlers.
\r
123 void xPortPendSVHandler( void ) __attribute__ (( naked ));
\r
124 void xPortSysTickHandler( void );
\r
125 void vPortSVCHandler( void ) __attribute__ (( naked ));
\r
128 * Start first task is a separate function so it can be tested in isolation.
\r
130 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
\r
133 * Function to enable the VFP.
\r
135 static void vPortEnableVFP( void ) __attribute__ (( naked ));
\r
138 * Used to catch tasks that attempt to return from their implementing function.
\r
140 static void prvTaskExitError( void );
\r
142 /*-----------------------------------------------------------*/
\r
144 /* Each task maintains its own interrupt status in the critical nesting
\r
146 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
149 * The number of SysTick increments that make up one tick period.
\r
151 #if( configUSE_TICKLESS_IDLE == 1 )
\r
152 static uint32_t ulTimerCountsForOneTick = 0;
\r
153 #endif /* configUSE_TICKLESS_IDLE */
\r
156 * The maximum number of tick periods that can be suppressed is limited by the
\r
157 * 24 bit resolution of the SysTick timer.
\r
159 #if( configUSE_TICKLESS_IDLE == 1 )
\r
160 static uint32_t xMaximumPossibleSuppressedTicks = 0;
\r
161 #endif /* configUSE_TICKLESS_IDLE */
\r
164 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
165 * power functionality only.
\r
167 #if( configUSE_TICKLESS_IDLE == 1 )
\r
168 static uint32_t ulStoppedTimerCompensation = 0;
\r
169 #endif /* configUSE_TICKLESS_IDLE */
\r
172 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
173 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
174 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
176 #if( configASSERT_DEFINED == 1 )
\r
177 static uint8_t ucMaxSysCallPriority = 0;
\r
178 static uint32_t ulMaxPRIGROUPValue = 0;
\r
179 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
180 #endif /* configASSERT_DEFINED */
\r
182 /*-----------------------------------------------------------*/
\r
185 * See header file for description.
\r
187 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
189 /* Simulate the stack frame as it would be created by a context switch
\r
192 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
193 of interrupts, and to ensure alignment. */
\r
196 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
198 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
\r
200 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
\r
202 /* Save code space by skipping register initialisation. */
\r
203 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
204 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
206 /* A save method is being used that requires each task to maintain its
\r
207 own exec return value. */
\r
209 *pxTopOfStack = portINITIAL_EXC_RETURN;
\r
211 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
213 return pxTopOfStack;
\r
215 /*-----------------------------------------------------------*/
\r
217 static void prvTaskExitError( void )
\r
219 volatile uint32_t ulDummy = 0;
\r
221 /* A function that implements a task must not exit or attempt to return to
\r
222 its caller as there is nothing to return to. If a task wants to exit it
\r
223 should instead call vTaskDelete( NULL ).
\r
225 Artificially force an assert() to be triggered if configASSERT() is
\r
226 defined, then stop here so application writers can catch the error. */
\r
227 configASSERT( uxCriticalNesting == ~0UL );
\r
228 portDISABLE_INTERRUPTS();
\r
229 while( ulDummy == 0 )
\r
231 /* This file calls prvTaskExitError() after the scheduler has been
\r
232 started to remove a compiler warning about the function being defined
\r
233 but never called. ulDummy is used purely to quieten other warnings
\r
234 about code appearing after this function is called - making ulDummy
\r
235 volatile makes the compiler think the function could return and
\r
236 therefore not output an 'unreachable code' warning for code that appears
\r
240 /*-----------------------------------------------------------*/
\r
242 void vPortSVCHandler( void )
\r
245 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
\r
246 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
\r
247 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
248 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
\r
249 " msr psp, r0 \n" /* Restore the task stack pointer. */
\r
252 " msr basepri, r0 \n"
\r
256 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
\r
259 /*-----------------------------------------------------------*/
\r
261 static void prvPortStartFirstTask( void )
\r
263 /* Start the first task. This also clears the bit that indicates the FPU is
\r
264 in use in case the FPU was used before the scheduler was started - which
\r
265 would otherwise result in the unnecessary leaving of space in the SVC stack
\r
266 for lazy saving of FPU registers. */
\r
268 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
\r
271 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
\r
272 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
\r
273 " msr control, r0 \n"
\r
274 " cpsie i \n" /* Globally enable interrupts. */
\r
278 " svc 0 \n" /* System call to start first task. */
\r
282 /*-----------------------------------------------------------*/
\r
285 * See header file for description.
\r
287 BaseType_t xPortStartScheduler( void )
\r
289 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
290 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
291 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
293 /* This port can be used on all revisions of the Cortex-M7 core other than
\r
294 the r0p1 parts. r0p1 parts should use the port from the
\r
295 /source/portable/GCC/ARM_CM7/r0p1 directory. */
\r
296 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
\r
297 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
\r
299 #if( configASSERT_DEFINED == 1 )
\r
301 volatile uint32_t ulOriginalPriority;
\r
302 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
303 volatile uint8_t ucMaxPriorityValue;
\r
305 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
306 functions can be called. ISR safe functions are those that end in
\r
307 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
308 ensure interrupt entry is as fast and simple as possible.
\r
310 Save the interrupt priority value that is about to be clobbered. */
\r
311 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
313 /* Determine the number of priority bits available. First write to all
\r
315 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
317 /* Read the value back to see how many bits stuck. */
\r
318 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
320 /* Use the same mask on the maximum system call priority. */
\r
321 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
323 /* Calculate the maximum acceptable priority group value for the number
\r
324 of bits read back. */
\r
325 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
326 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
328 ulMaxPRIGROUPValue--;
\r
329 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
332 #ifdef __NVIC_PRIO_BITS
\r
334 /* Check the CMSIS configuration that defines the number of
\r
335 priority bits matches the number of priority bits actually queried
\r
336 from the hardware. */
\r
337 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
\r
341 #ifdef configPRIO_BITS
\r
343 /* Check the FreeRTOS configuration that defines the number of
\r
344 priority bits matches the number of priority bits actually queried
\r
345 from the hardware. */
\r
346 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
\r
350 /* Shift the priority group value back to its position within the AIRCR
\r
352 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
353 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
355 /* Restore the clobbered interrupt priority register to its original
\r
357 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
359 #endif /* conifgASSERT_DEFINED */
\r
361 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
362 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
363 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
365 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
367 vPortSetupTimerInterrupt();
\r
369 /* Initialise the critical nesting count ready for the first task. */
\r
370 uxCriticalNesting = 0;
\r
372 /* Ensure the VFP is enabled - it should be anyway. */
\r
375 /* Lazy save always. */
\r
376 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
378 /* Start the first task. */
\r
379 prvPortStartFirstTask();
\r
381 /* Should never get here as the tasks will now be executing! Call the task
\r
382 exit error function to prevent compiler warnings about a static function
\r
383 not being called in the case that the application writer overrides this
\r
384 functionality by defining configTASK_RETURN_ADDRESS. Call
\r
385 vTaskSwitchContext() so link time optimisation does not remove the
\r
387 vTaskSwitchContext();
\r
388 prvTaskExitError();
\r
390 /* Should not get here! */
\r
393 /*-----------------------------------------------------------*/
\r
395 void vPortEndScheduler( void )
\r
397 /* Not implemented in ports where there is nothing to return to.
\r
398 Artificially force an assert. */
\r
399 configASSERT( uxCriticalNesting == 1000UL );
\r
401 /*-----------------------------------------------------------*/
\r
403 void vPortEnterCritical( void )
\r
405 portDISABLE_INTERRUPTS();
\r
406 uxCriticalNesting++;
\r
408 /* This is not the interrupt safe version of the enter critical function so
\r
409 assert() if it is being called from an interrupt context. Only API
\r
410 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
411 the critical nesting count is 1 to protect against recursive calls if the
\r
412 assert function also uses a critical section. */
\r
413 if( uxCriticalNesting == 1 )
\r
415 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
418 /*-----------------------------------------------------------*/
\r
420 void vPortExitCritical( void )
\r
422 configASSERT( uxCriticalNesting );
\r
423 uxCriticalNesting--;
\r
424 if( uxCriticalNesting == 0 )
\r
426 portENABLE_INTERRUPTS();
\r
429 /*-----------------------------------------------------------*/
\r
431 void xPortPendSVHandler( void )
\r
433 /* This is a naked function. */
\r
440 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
\r
443 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
\r
445 " vstmdbeq r0!, {s16-s31} \n"
\r
447 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
\r
448 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
\r
450 " stmdb sp!, {r0, r3} \n"
\r
452 " msr basepri, r0 \n"
\r
455 " bl vTaskSwitchContext \n"
\r
457 " msr basepri, r0 \n"
\r
458 " ldmia sp!, {r0, r3} \n"
\r
460 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
463 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
\r
465 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
\r
467 " vldmiaeq r0!, {s16-s31} \n"
\r
472 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
\r
473 #if WORKAROUND_PMU_CM001 == 1
\r
482 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
483 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
\r
486 /*-----------------------------------------------------------*/
\r
488 void xPortSysTickHandler( void )
\r
490 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
491 executes all interrupts must be unmasked. There is therefore no need to
\r
492 save and then restore the interrupt mask value as its value is already
\r
494 portDISABLE_INTERRUPTS();
\r
496 /* Increment the RTOS tick. */
\r
497 if( xTaskIncrementTick() != pdFALSE )
\r
499 /* A context switch is required. Context switching is performed in
\r
500 the PendSV interrupt. Pend the PendSV interrupt. */
\r
501 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
504 portENABLE_INTERRUPTS();
\r
506 /*-----------------------------------------------------------*/
\r
508 #if( configUSE_TICKLESS_IDLE == 1 )
\r
510 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
512 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
\r
513 TickType_t xModifiableIdleTime;
\r
515 /* Make sure the SysTick reload value does not overflow the counter. */
\r
516 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
518 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
521 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
522 is accounted for as best it can be, but using the tickless mode will
\r
523 inevitably result in some tiny drift of the time maintained by the
\r
524 kernel with respect to calendar time. */
\r
525 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
\r
527 /* Calculate the reload value required to wait xExpectedIdleTime
\r
528 tick periods. -1 is used because this code will execute part way
\r
529 through one of the tick periods. */
\r
530 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
531 if( ulReloadValue > ulStoppedTimerCompensation )
\r
533 ulReloadValue -= ulStoppedTimerCompensation;
\r
536 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
537 method as that will mask interrupts that should exit sleep mode. */
\r
538 __asm volatile( "cpsid i" ::: "memory" );
\r
539 __asm volatile( "dsb" );
\r
540 __asm volatile( "isb" );
\r
542 /* If a context switch is pending or a task is waiting for the scheduler
\r
543 to be unsuspended then abandon the low power entry. */
\r
544 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
546 /* Restart from whatever is left in the count register to complete
\r
547 this tick period. */
\r
548 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
550 /* Restart SysTick. */
\r
551 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
553 /* Reset the reload register to the value required for normal tick
\r
555 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
557 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
559 __asm volatile( "cpsie i" ::: "memory" );
\r
563 /* Set the new reload value. */
\r
564 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
566 /* Clear the SysTick count flag and set the count value back to
\r
568 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
570 /* Restart SysTick. */
\r
571 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
573 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
574 set its parameter to 0 to indicate that its implementation contains
\r
575 its own wait for interrupt or wait for event instruction, and so wfi
\r
576 should not be executed again. However, the original expected idle
\r
577 time variable must remain unmodified, so a copy is taken. */
\r
578 xModifiableIdleTime = xExpectedIdleTime;
\r
579 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
580 if( xModifiableIdleTime > 0 )
\r
582 __asm volatile( "dsb" ::: "memory" );
\r
583 __asm volatile( "wfi" );
\r
584 __asm volatile( "isb" );
\r
586 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
588 /* Re-enable interrupts to allow the interrupt that brought the MCU
\r
589 out of sleep mode to execute immediately. see comments above
\r
590 __disable_interrupt() call above. */
\r
591 __asm volatile( "cpsie i" ::: "memory" );
\r
592 __asm volatile( "dsb" );
\r
593 __asm volatile( "isb" );
\r
595 /* Disable interrupts again because the clock is about to be stopped
\r
596 and interrupts that execute while the clock is stopped will increase
\r
597 any slippage between the time maintained by the RTOS and calendar
\r
599 __asm volatile( "cpsid i" ::: "memory" );
\r
600 __asm volatile( "dsb" );
\r
601 __asm volatile( "isb" );
\r
603 /* Disable the SysTick clock without reading the
\r
604 portNVIC_SYSTICK_CTRL_REG register to ensure the
\r
605 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
\r
606 the time the SysTick is stopped for is accounted for as best it can
\r
607 be, but using the tickless mode will inevitably result in some tiny
\r
608 drift of the time maintained by the kernel with respect to calendar
\r
610 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
\r
612 /* Determine if the SysTick clock has already counted to zero and
\r
613 been set back to the current reload value (the reload back being
\r
614 correct for the entire expected idle time) or if the SysTick is yet
\r
615 to count to zero (in which case an interrupt other than the SysTick
\r
616 must have brought the system out of sleep mode). */
\r
617 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
619 uint32_t ulCalculatedLoadValue;
\r
621 /* The tick interrupt is already pending, and the SysTick count
\r
622 reloaded with ulReloadValue. Reset the
\r
623 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
625 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
627 /* Don't allow a tiny value, or values that have somehow
\r
628 underflowed because the post sleep hook did something
\r
629 that took too long. */
\r
630 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
632 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
635 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
637 /* As the pending tick will be processed as soon as this
\r
638 function exits, the tick value maintained by the tick is stepped
\r
639 forward by one less than the time spent waiting. */
\r
640 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
644 /* Something other than the tick interrupt ended the sleep.
\r
645 Work out how long the sleep lasted rounded to complete tick
\r
646 periods (not the ulReload value which accounted for part
\r
648 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
650 /* How many complete tick periods passed while the processor
\r
652 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
654 /* The reload value is set to whatever fraction of a single tick
\r
656 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
659 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
660 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
662 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
663 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
664 vTaskStepTick( ulCompleteTickPeriods );
\r
665 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
667 /* Exit with interrupts enabled. */
\r
668 __asm volatile( "cpsie i" ::: "memory" );
\r
672 #endif /* #if configUSE_TICKLESS_IDLE */
\r
673 /*-----------------------------------------------------------*/
\r
676 * Setup the systick timer to generate the tick interrupts at the required
\r
679 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
681 /* Calculate the constants required to configure the tick interrupt. */
\r
682 #if( configUSE_TICKLESS_IDLE == 1 )
\r
684 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
685 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
686 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
688 #endif /* configUSE_TICKLESS_IDLE */
\r
690 /* Stop and clear the SysTick. */
\r
691 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
692 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
694 /* Configure SysTick to interrupt at the requested rate. */
\r
695 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
696 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
698 /*-----------------------------------------------------------*/
\r
700 /* This is a naked function. */
\r
701 static void vPortEnableVFP( void )
\r
705 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
708 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
713 /*-----------------------------------------------------------*/
\r
715 #if( configASSERT_DEFINED == 1 )
\r
717 void vPortValidateInterruptPriority( void )
\r
719 uint32_t ulCurrentInterrupt;
\r
720 uint8_t ucCurrentPriority;
\r
722 /* Obtain the number of the currently executing interrupt. */
\r
723 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
725 /* Is the interrupt number a user defined interrupt? */
\r
726 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
728 /* Look up the interrupt's priority. */
\r
729 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
731 /* The following assertion will fail if a service routine (ISR) for
\r
732 an interrupt that has been assigned a priority above
\r
733 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
734 function. ISR safe FreeRTOS API functions must *only* be called
\r
735 from interrupts that have been assigned a priority at or below
\r
736 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
738 Numerically low interrupt priority numbers represent logically high
\r
739 interrupt priorities, therefore the priority of the interrupt must
\r
740 be set to a value equal to or numerically *higher* than
\r
741 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
743 Interrupts that use the FreeRTOS API must not be left at their
\r
744 default priority of zero as that is the highest possible priority,
\r
745 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
746 and therefore also guaranteed to be invalid.
\r
748 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
749 interrupt entry is as fast and simple as possible.
\r
751 The following links provide detailed information:
\r
752 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
753 http://www.freertos.org/FAQHelp.html */
\r
754 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
757 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
758 that define each interrupt's priority to be split between bits that
\r
759 define the interrupt's pre-emption priority bits and bits that define
\r
760 the interrupt's sub-priority. For simplicity all bits must be defined
\r
761 to be pre-emption priority bits. The following assertion will fail if
\r
762 this is not the case (if some bits represent a sub-priority).
\r
764 If the application only uses CMSIS libraries for interrupt
\r
765 configuration then the correct setting can be achieved on all Cortex-M
\r
766 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
767 scheduler. Note however that some vendor specific peripheral libraries
\r
768 assume a non-zero priority group setting, in which cases using a value
\r
769 of zero will result in unpredictable behaviour. */
\r
770 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
773 #endif /* configASSERT_DEFINED */
\r