git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
   5     http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
  10      *    Complete, revised, and edited pdf reference manuals are also       *\r
  11      *    available.                                                         *\r
  12      *                                                                       *\r
  13      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  14      *    ensuring you get running as quickly as possible and with an        *\r
  15      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  16      *    the FreeRTOS project to continue with its mission of providing     *\r
  17      *    professional grade, cross platform, de facto standard solutions    *\r
  18      *    for microcontrollers - completely free of charge!                  *\r
  19      *                                                                       *\r
  20      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  21      *                                                                       *\r
  22      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  23      *                                                                       *\r
  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32 \r
  33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
  34     distribute a combined work that includes FreeRTOS without being obliged to\r
  35     provide the source code for proprietary components outside of the FreeRTOS\r
  36     kernel.\r
  37 \r
  38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
  41     details. You should have received a copy of the GNU General Public License\r
  42     and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
  43     viewed here: http://www.freertos.org/a00114.html and also obtained by\r
  44     writing to Real Time Engineers Ltd., contact details for whom are available\r
  45     on the FreeRTOS WEB site.\r
  46 \r
  47     1 tab == 4 spaces!\r
  48 \r
  49     ***************************************************************************\r
  50      *                                                                       *\r
  51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  52      *    not run, what could be wrong?"                                     *\r
  53      *                                                                       *\r
  54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  55      *                                                                       *\r
  56     ***************************************************************************\r
  57 \r
  58 \r
  59     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  60     license and Real Time Engineers Ltd. contact details.\r
  61 \r
  62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
  64     fully thread aware and reentrant UDP/IP stack.\r
  65 \r
  66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  67     Integrity Systems, who sell the code with commercial support,\r
  68     indemnification and middleware, under the OpenRTOS brand.\r
  69 \r
  70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  71     engineered and independently SIL3 certified version for use in safety and\r
  72     mission critical applications that require provable dependability.\r
  73 */\r
  74 \r
  75 /*-----------------------------------------------------------\r
  76  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  77  *----------------------------------------------------------*/\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 \r
  83 #ifndef __VFP_FP__\r
  84         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  85 #endif\r
  86 \r
  87 #ifndef configSYSTICK_CLOCK_HZ\r
  88         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  89 #endif\r
  90 \r
  91 /* Constants required to manipulate the core.  Registers first... */\r
  92 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  93 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  95 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  96 /* ...then bits in the registers. */\r
  97 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  98 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  99 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 101 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 103 \r
 104 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 105 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 106 \r
 107 /* Constants required to check the validity of an interrupt prority. */\r
 108 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 109 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 110 #define portAIRCR_REG                                           ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
 111 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 112 \r
 113 /* Constants required to manipulate the VFP. */\r
 114 #define portFPCCR                                       ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
 115 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
 116 \r
 117 /* Constants required to set up the initial stack. */\r
 118 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 119 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 120 \r
 121 /* The systick is a 24-bit counter. */\r
 122 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 123 \r
 124 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 125 occurred while the SysTick counter is stopped during tickless idle\r
 126 calculations. */\r
 127 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 128 \r
 129 /* Each task maintains its own interrupt status in the critical nesting\r
 130 variable. */\r
 131 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 132 \r
 133 /*\r
 134  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 135  * file is weak to allow application writers to change the timer used to\r
 136  * generate the tick interrupt.\r
 137  */\r
 138 void vPortSetupTimerInterrupt( void );\r
 139 \r
 140 /*\r
 141  * Exception handlers.\r
 142  */\r
 143 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 144 void xPortSysTickHandler( void );\r
 145 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 146 \r
 147 /*\r
 148  * Start first task is a separate function so it can be tested in isolation.\r
 149  */\r
 150 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 151 \r
 152 /*\r
 153  * Function to enable the VFP.\r
 154  */\r
 155  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 156 \r
 157 /*-----------------------------------------------------------*/\r
 158 \r
 159 /*\r
 160  * The number of SysTick increments that make up one tick period.\r
 161  */\r
 162 #if configUSE_TICKLESS_IDLE == 1\r
 163         static unsigned long ulTimerCountsForOneTick = 0;\r
 164 #endif /* configUSE_TICKLESS_IDLE */\r
 165 \r
 166 /*\r
 167  * The maximum number of tick periods that can be suppressed is limited by the\r
 168  * 24 bit resolution of the SysTick timer.\r
 169  */\r
 170 #if configUSE_TICKLESS_IDLE == 1\r
 171         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 172 #endif /* configUSE_TICKLESS_IDLE */\r
 173 \r
 174 /*\r
 175  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 176  * power functionality only.\r
 177  */\r
 178 #if configUSE_TICKLESS_IDLE == 1\r
 179         static unsigned long ulStoppedTimerCompensation = 0;\r
 180 #endif /* configUSE_TICKLESS_IDLE */\r
 181 \r
 182 /*\r
 183  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure \r
 184  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 185  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 186  */\r
 187 #if ( configASSERT_DEFINED == 1 )\r
 188          static unsigned char ucMaxSysCallPriority = 0;\r
 189          static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 190 #endif /* configASSERT_DEFINED */\r
 191 \r
 192 /*-----------------------------------------------------------*/\r
 193 \r
 194 /*\r
 195  * See header file for description.\r
 196  */\r
 197 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 198 {\r
 199         /* Simulate the stack frame as it would be created by a context switch\r
 200         interrupt. */\r
 201 \r
 202         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 203         of interrupts, and to ensure alignment. */\r
 204         pxTopOfStack--;\r
 205 \r
 206         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 207         pxTopOfStack--;\r
 208         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 209         pxTopOfStack--;\r
 210         *pxTopOfStack = 0;      /* LR */\r
 211 \r
 212         /* Save code space by skipping register initialisation. */\r
 213         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 214         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 215 \r
 216         /* A save method is being used that requires each task to maintain its\r
 217         own exec return value. */\r
 218         pxTopOfStack--;\r
 219         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 220 \r
 221         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 222 \r
 223         return pxTopOfStack;\r
 224 }\r
 225 /*-----------------------------------------------------------*/\r
 226 \r
 227 void vPortSVCHandler( void )\r
 228 {\r
 229         __asm volatile (\r
 230                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 231                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 232                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 233                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 234                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 235                                         "       mov r0, #0                                              \n"\r
 236                                         "       msr     basepri, r0                                     \n"\r
 237                                         "       bx r14                                                  \n"\r
 238                                         "                                                                       \n"\r
 239                                         "       .align 2                                                \n"\r
 240                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 241                                 );\r
 242 }\r
 243 /*-----------------------------------------------------------*/\r
 244 \r
 245 static void prvPortStartFirstTask( void )\r
 246 {\r
 247         __asm volatile(\r
 248                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 249                                         " ldr r0, [r0]                  \n"\r
 250                                         " ldr r0, [r0]                  \n"\r
 251                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 252                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 253                                         " svc 0                                 \n" /* System call to start first task. */\r
 254                                         " nop                                   \n"\r
 255                                 );\r
 256 }\r
 257 /*-----------------------------------------------------------*/\r
 258 \r
 259 /*\r
 260  * See header file for description.\r
 261  */\r
 262 portBASE_TYPE xPortStartScheduler( void )\r
 263 {\r
 264         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 265         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 266         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 267 \r
 268         #if( configASSERT_DEFINED == 1 )\r
 269         {\r
 270                 volatile unsigned long ulOriginalPriority;\r
 271                 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 272 \r
 273                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 274                 functions can be called.  ISR safe functions are those that end in\r
 275                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 276                 ensure interrupt entry is as fast and simple as possible.\r
 277 \r
 278                 Save the interrupt priority value that is about to be clobbered. */\r
 279                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 280 \r
 281                 /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
 282                 priority register. */\r
 283                 *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
 284 \r
 285                 /* Read back the written priority to obtain its value as seen by the\r
 286                 hardware, which will only implement a subset of the priority bits. */\r
 287                 ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
 288 \r
 289                 /* Restore the clobbered interrupt priority register to its original\r
 290                 value. */\r
 291                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 292         }\r
 293         #endif /* conifgASSERT_DEFINED */\r
 294 \r
 295         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 296         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 297         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 298 \r
 299         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 300         here already. */\r
 301         vPortSetupTimerInterrupt();\r
 302 \r
 303         /* Initialise the critical nesting count ready for the first task. */\r
 304         uxCriticalNesting = 0;\r
 305 \r
 306         /* Ensure the VFP is enabled - it should be anyway. */\r
 307         vPortEnableVFP();\r
 308 \r
 309         /* Lazy save always. */\r
 310         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 311 \r
 312         /* Start the first task. */\r
 313         prvPortStartFirstTask();\r
 314 \r
 315         /* Should not get here! */\r
 316         return 0;\r
 317 }\r
 318 /*-----------------------------------------------------------*/\r
 319 \r
 320 void vPortEndScheduler( void )\r
 321 {\r
 322         /* It is unlikely that the CM4F port will require this function as there\r
 323         is nothing to return to.  */\r
 324 }\r
 325 /*-----------------------------------------------------------*/\r
 326 \r
 327 void vPortYield( void )\r
 328 {\r
 329         /* Set a PendSV to request a context switch. */\r
 330         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 331 \r
 332         /* Barriers are normally not required but do ensure the code is completely\r
 333         within the specified behaviour for the architecture. */\r
 334         __asm volatile( "dsb" );\r
 335         __asm volatile( "isb" );\r
 336 }\r
 337 /*-----------------------------------------------------------*/\r
 338 \r
 339 void vPortEnterCritical( void )\r
 340 {\r
 341         portDISABLE_INTERRUPTS();\r
 342         uxCriticalNesting++;\r
 343         __asm volatile( "dsb" );\r
 344         __asm volatile( "isb" );\r
 345 }\r
 346 /*-----------------------------------------------------------*/\r
 347 \r
 348 void vPortExitCritical( void )\r
 349 {\r
 350         uxCriticalNesting--;\r
 351         if( uxCriticalNesting == 0 )\r
 352         {\r
 353                 portENABLE_INTERRUPTS();\r
 354         }\r
 355 }\r
 356 /*-----------------------------------------------------------*/\r
 357 \r
 358 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 359 {\r
 360         __asm volatile                                                                                                          \\r
 361         (                                                                                                                                       \\r
 362                 "       mrs r0, basepri                                                                                 \n" \\r
 363                 "       mov r1, %0                                                                                              \n"     \\r
 364                 "       msr basepri, r1                                                                                 \n" \\r
 365                 "       bx lr                                                                                                   \n" \\r
 366                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 367         );\r
 368 \r
 369         /* This return will not be reached but is necessary to prevent compiler\r
 370         warnings. */\r
 371         return 0;\r
 372 }\r
 373 /*-----------------------------------------------------------*/\r
 374 \r
 375 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 376 {\r
 377         __asm volatile                                                                                                  \\r
 378         (                                                                                                                               \\r
 379                 "       msr basepri, r0                                                                         \n"     \\r
 380                 "       bx lr                                                                                           \n" \\r
 381                 :::"r0"                                                                                                         \\r
 382         );\r
 383 \r
 384         /* Just to avoid compiler warnings. */\r
 385         ( void ) ulNewMaskValue;\r
 386 }\r
 387 /*-----------------------------------------------------------*/\r
 388 \r
 389 void xPortPendSVHandler( void )\r
 390 {\r
 391         /* This is a naked function. */\r
 392 \r
 393         __asm volatile\r
 394         (\r
 395         "       mrs r0, psp                                                     \n"\r
 396         "                                                                               \n"\r
 397         "       ldr     r3, pxCurrentTCBConst                           \n" /* Get the location of the current TCB. */\r
 398         "       ldr     r2, [r3]                                                \n"\r
 399         "                                                                               \n"\r
 400         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 401         "       it eq                                                           \n"\r
 402         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 403         "                                                                               \n"\r
 404         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 405         "                                                                               \n"\r
 406         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 407         "                                                                               \n"\r
 408         "       stmdb sp!, {r3, r14}                            \n"\r
 409         "       mov r0, %0                                                      \n"\r
 410         "       msr basepri, r0                                         \n"\r
 411         "       bl vTaskSwitchContext                           \n"\r
 412         "       mov r0, #0                                                      \n"\r
 413         "       msr basepri, r0                                         \n"\r
 414         "       ldmia sp!, {r3, r14}                            \n"\r
 415         "                                                                               \n"\r
 416         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 417         "       ldr r0, [r1]                                            \n"\r
 418         "                                                                               \n"\r
 419         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 420         "                                                                               \n"\r
 421         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 422         "       it eq                                                           \n"\r
 423         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 424         "                                                                               \n"\r
 425         "       msr psp, r0                                                     \n"\r
 426         "       bx r14                                                          \n"\r
 427         "                                                                               \n"\r
 428         "       .align 2                                                        \n"\r
 429         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 430         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 431         );\r
 432 }\r
 433 /*-----------------------------------------------------------*/\r
 434 \r
 435 void xPortSysTickHandler( void )\r
 436 {\r
 437         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 438         executes all interrupts must be unmasked.  There is therefore no need to\r
 439         save and then restore the interrupt mask value as its value is already\r
 440         known. */\r
 441         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 442         {\r
 443                 /* Increment the RTOS tick. */\r
 444                 if( xTaskIncrementTick() != pdFALSE )\r
 445                 {\r
 446                         /* A context switch is required.  Context switching is performed in\r
 447                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 448                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 449                 }\r
 450         }\r
 451         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 452 }\r
 453 /*-----------------------------------------------------------*/\r
 454 \r
 455 #if configUSE_TICKLESS_IDLE == 1\r
 456 \r
 457         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 458         {\r
 459         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 460         portTickType xModifiableIdleTime;\r
 461 \r
 462                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 463                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 464                 {\r
 465                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 466                 }\r
 467 \r
 468                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 469                 is accounted for as best it can be, but using the tickless mode will\r
 470                 inevitably result in some tiny drift of the time maintained by the\r
 471                 kernel with respect to calendar time. */\r
 472                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 473 \r
 474                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 475                 tick periods.  -1 is used because this code will execute part way\r
 476                 through one of the tick periods. */\r
 477                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 478                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 479                 {\r
 480                         ulReloadValue -= ulStoppedTimerCompensation;\r
 481                 }\r
 482 \r
 483                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 484                 method as that will mask interrupts that should exit sleep mode. */\r
 485                 __asm volatile( "cpsid i" );\r
 486 \r
 487                 /* If a context switch is pending or a task is waiting for the scheduler\r
 488                 to be unsuspended then abandon the low power entry. */\r
 489                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 490                 {\r
 491                         /* Restart SysTick. */\r
 492                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 493 \r
 494                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 495                         above. */\r
 496                         __asm volatile( "cpsie i" );\r
 497                 }\r
 498                 else\r
 499                 {\r
 500                         /* Set the new reload value. */\r
 501                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 502 \r
 503                         /* Clear the SysTick count flag and set the count value back to\r
 504                         zero. */\r
 505                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 506 \r
 507                         /* Restart SysTick. */\r
 508                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 509 \r
 510                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 511                         set its parameter to 0 to indicate that its implementation contains\r
 512                         its own wait for interrupt or wait for event instruction, and so wfi\r
 513                         should not be executed again.  However, the original expected idle\r
 514                         time variable must remain unmodified, so a copy is taken. */\r
 515                         xModifiableIdleTime = xExpectedIdleTime;\r
 516                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 517                         if( xModifiableIdleTime > 0 )\r
 518                         {\r
 519                                 __asm volatile( "dsb" );\r
 520                                 __asm volatile( "wfi" );\r
 521                                 __asm volatile( "isb" );\r
 522                         }\r
 523                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 524 \r
 525                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 526                         accounted for as best it can be, but using the tickless mode will\r
 527                         inevitably result in some tiny drift of the time maintained by the\r
 528                         kernel with respect to calendar time. */\r
 529                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 530 \r
 531                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 532                         above. */\r
 533                         __asm volatile( "cpsie i" );\r
 534 \r
 535                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 536                         {\r
 537                                 /* The tick interrupt has already executed, and the SysTick\r
 538                                 count reloaded with ulReloadValue.  Reset the\r
 539                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 540                                 period. */\r
 541                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 542 \r
 543                                 /* The tick interrupt handler will already have pended the tick\r
 544                                 processing in the kernel.  As the pending tick will be\r
 545                                 processed as soon as this function exits, the tick value\r
 546                                 maintained by the tick is stepped forward by one less than the\r
 547                                 time spent waiting. */\r
 548                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 549                         }\r
 550                         else\r
 551                         {\r
 552                                 /* Something other than the tick interrupt ended the sleep.\r
 553                                 Work out how long the sleep lasted rounded to complete tick\r
 554                                 periods (not the ulReload value which accounted for part\r
 555                                 ticks). */\r
 556                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 557 \r
 558                                 /* How many complete tick periods passed while the processor\r
 559                                 was waiting? */\r
 560                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 561 \r
 562                                 /* The reload value is set to whatever fraction of a single tick\r
 563                                 period remains. */\r
 564                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 565                         }\r
 566 \r
 567                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 568                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 569                         value. */\r
 570                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 571                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 572 \r
 573                         vTaskStepTick( ulCompleteTickPeriods );\r
 574 \r
 575                         /* The counter must start by the time the reload value is reset. */\r
 576                         configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 577                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 578                 }\r
 579         }\r
 580 \r
 581 #endif /* #if configUSE_TICKLESS_IDLE */\r
 582 /*-----------------------------------------------------------*/\r
 583 \r
 584 /*\r
 585  * Setup the systick timer to generate the tick interrupts at the required\r
 586  * frequency.\r
 587  */\r
 588 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 589 {\r
 590         /* Calculate the constants required to configure the tick interrupt. */\r
 591         #if configUSE_TICKLESS_IDLE == 1\r
 592         {\r
 593                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 594                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 595                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 596         }\r
 597         #endif /* configUSE_TICKLESS_IDLE */\r
 598 \r
 599         /* Configure SysTick to interrupt at the requested rate. */\r
 600         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 601         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 602 }\r
 603 /*-----------------------------------------------------------*/\r
 604 \r
 605 /* This is a naked function. */\r
 606 static void vPortEnableVFP( void )\r
 607 {\r
 608         __asm volatile\r
 609         (\r
 610                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 611                 "       ldr r1, [r0]                            \n"\r
 612                 "                                                               \n"\r
 613                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 614                 "       str r1, [r0]                            \n"\r
 615                 "       bx r14                                          "\r
 616         );\r
 617 }\r
 618 /*-----------------------------------------------------------*/\r
 619 \r
 620 #if( configASSERT_DEFINED == 1 )\r
 621 \r
 622         void vPortValidateInterruptPriority( void )\r
 623         {\r
 624         unsigned long ulCurrentInterrupt;\r
 625         unsigned char ucCurrentPriority;\r
 626 \r
 627                 /* Obtain the number of the currently executing interrupt. */\r
 628                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 629 \r
 630                 /* Is the interrupt number a user defined interrupt? */\r
 631                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 632                 {\r
 633                         /* Look up the interrupt's priority. */\r
 634                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 635 \r
 636                         /* The following assertion will fail if a service routine (ISR) for \r
 637                         an interrupt that has been assigned a priority above\r
 638                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 639                         function.  ISR safe FreeRTOS API functions must *only* be called \r
 640                         from interrupts that have been assigned a priority at or below\r
 641                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 642                         \r
 643                         Numerically low interrupt priority numbers represent logically high\r
 644                         interrupt priorities, therefore the priority of the interrupt must \r
 645                         be set to a value equal to or numerically *higher* than \r
 646                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 647                         \r
 648                         Interrupts that use the FreeRTOS API must not be left at their\r
 649                         default priority of     zero as that is the highest possible priority,\r
 650                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
 651                         and     therefore also guaranteed to be invalid.  \r
 652                         \r
 653                         FreeRTOS maintains separate thread and ISR API functions to ensure \r
 654                         interrupt entry is as fast and simple as possible.\r
 655                         \r
 656                         The following links provide detailed information:\r
 657                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 658                         http://www.freertos.org/FAQHelp.html */\r
 659                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 660                 }\r
 661 \r
 662                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits \r
 663                 that define each interrupt's priority to be split between bits that \r
 664                 define the interrupt's pre-emption priority bits and bits that define\r
 665                 the interrupt's sub-priority.  For simplicity all bits must be defined \r
 666                 to be pre-emption priority bits.  The following assertion will fail if\r
 667                 this is not the case (if some bits represent a sub-priority).  \r
 668                 \r
 669                 If CMSIS libraries are being used then the correct setting can be \r
 670                 achieved by calling     NVIC_SetPriorityGrouping( 0 ); before starting the \r
 671                 scheduler. */\r
 672                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
 673         }\r
 674 \r
 675 #endif /* configASSERT_DEFINED */\r
 676 \r
 677 \r