2 FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to distribute
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28 >>! a combined work that includes FreeRTOS without being obliged to provide
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29 >>! the source code for proprietary components outside of the FreeRTOS
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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66 /*-----------------------------------------------------------
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67 * Implementation of functions defined in portable.h for the ARM CM4F port.
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68 *----------------------------------------------------------*/
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70 /* Scheduler includes. */
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71 #include "FreeRTOS.h"
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75 #error This port can only be used when the project options are configured to enable hardware floating point support.
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78 #ifndef configSYSTICK_CLOCK_HZ
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79 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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80 /* Ensure the SysTick is clocked at the same frequency as the core. */
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81 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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83 /* The way the SysTick is clocked is not modified in case it is not the same
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85 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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88 /* Constants required to manipulate the core. Registers first... */
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89 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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90 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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91 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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92 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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93 /* ...then bits in the registers. */
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94 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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95 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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96 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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97 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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98 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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100 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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101 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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103 /* Constants required to check the validity of an interrupt priority. */
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104 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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105 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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106 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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107 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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108 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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109 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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110 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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111 #define portPRIGROUP_SHIFT ( 8UL )
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113 /* Constants required to manipulate the VFP. */
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114 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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115 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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117 /* Constants required to set up the initial stack. */
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118 #define portINITIAL_XPSR ( 0x01000000 )
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119 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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121 /* The systick is a 24-bit counter. */
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122 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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124 /* A fiddle factor to estimate the number of SysTick counts that would have
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125 occurred while the SysTick counter is stopped during tickless idle
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127 #define portMISSED_COUNTS_FACTOR ( 45UL )
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129 /* Let the user override the pre-loading of the initial LR with the address of
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130 prvTaskExitError() in case is messes up unwinding of the stack in the
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132 #ifdef configTASK_RETURN_ADDRESS
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133 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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135 #define portTASK_RETURN_ADDRESS prvTaskExitError
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138 /* Each task maintains its own interrupt status in the critical nesting
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140 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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143 * Setup the timer to generate the tick interrupts. The implementation in this
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144 * file is weak to allow application writers to change the timer used to
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145 * generate the tick interrupt.
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147 void vPortSetupTimerInterrupt( void );
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150 * Exception handlers.
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152 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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153 void xPortSysTickHandler( void );
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154 void vPortSVCHandler( void ) __attribute__ (( naked ));
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157 * Start first task is a separate function so it can be tested in isolation.
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159 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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162 * Function to enable the VFP.
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164 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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167 * Used to catch tasks that attempt to return from their implementing function.
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169 static void prvTaskExitError( void );
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171 /*-----------------------------------------------------------*/
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174 * The number of SysTick increments that make up one tick period.
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176 #if configUSE_TICKLESS_IDLE == 1
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177 static uint32_t ulTimerCountsForOneTick = 0;
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178 #endif /* configUSE_TICKLESS_IDLE */
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181 * The maximum number of tick periods that can be suppressed is limited by the
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182 * 24 bit resolution of the SysTick timer.
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184 #if configUSE_TICKLESS_IDLE == 1
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185 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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186 #endif /* configUSE_TICKLESS_IDLE */
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189 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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190 * power functionality only.
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192 #if configUSE_TICKLESS_IDLE == 1
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193 static uint32_t ulStoppedTimerCompensation = 0;
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194 #endif /* configUSE_TICKLESS_IDLE */
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197 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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198 * FreeRTOS API functions are not called from interrupts that have been assigned
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199 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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201 #if ( configASSERT_DEFINED == 1 )
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202 static uint8_t ucMaxSysCallPriority = 0;
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203 static uint32_t ulMaxPRIGROUPValue = 0;
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204 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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205 #endif /* configASSERT_DEFINED */
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207 /*-----------------------------------------------------------*/
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210 * See header file for description.
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212 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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214 /* Simulate the stack frame as it would be created by a context switch
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217 /* Offset added to account for the way the MCU uses the stack on entry/exit
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218 of interrupts, and to ensure alignment. */
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221 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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223 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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225 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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227 /* Save code space by skipping register initialisation. */
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228 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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229 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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231 /* A save method is being used that requires each task to maintain its
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232 own exec return value. */
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234 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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236 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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238 return pxTopOfStack;
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240 /*-----------------------------------------------------------*/
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242 static void prvTaskExitError( void )
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244 /* A function that implements a task must not exit or attempt to return to
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245 its caller as there is nothing to return to. If a task wants to exit it
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246 should instead call vTaskDelete( NULL ).
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248 Artificially force an assert() to be triggered if configASSERT() is
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249 defined, then stop here so application writers can catch the error. */
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250 configASSERT( uxCriticalNesting == ~0UL );
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251 portDISABLE_INTERRUPTS();
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254 /*-----------------------------------------------------------*/
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256 void vPortSVCHandler( void )
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259 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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260 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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261 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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262 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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263 " msr psp, r0 \n" /* Restore the task stack pointer. */
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266 " msr basepri, r0 \n"
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270 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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273 /*-----------------------------------------------------------*/
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275 static void prvPortStartFirstTask( void )
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278 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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281 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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282 " cpsie i \n" /* Globally enable interrupts. */
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285 " svc 0 \n" /* System call to start first task. */
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289 /*-----------------------------------------------------------*/
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292 * See header file for description.
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294 BaseType_t xPortStartScheduler( void )
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296 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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297 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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298 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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300 #if( configASSERT_DEFINED == 1 )
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302 volatile uint32_t ulOriginalPriority;
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303 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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304 volatile uint8_t ucMaxPriorityValue;
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306 /* Determine the maximum priority from which ISR safe FreeRTOS API
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307 functions can be called. ISR safe functions are those that end in
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308 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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309 ensure interrupt entry is as fast and simple as possible.
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311 Save the interrupt priority value that is about to be clobbered. */
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312 ulOriginalPriority = *pucFirstUserPriorityRegister;
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314 /* Determine the number of priority bits available. First write to all
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316 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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318 /* Read the value back to see how many bits stuck. */
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319 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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321 /* Use the same mask on the maximum system call priority. */
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322 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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324 /* Calculate the maximum acceptable priority group value for the number
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325 of bits read back. */
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326 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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327 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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329 ulMaxPRIGROUPValue--;
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330 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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333 /* Shift the priority group value back to its position within the AIRCR
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335 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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336 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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338 /* Restore the clobbered interrupt priority register to its original
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340 *pucFirstUserPriorityRegister = ulOriginalPriority;
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342 #endif /* conifgASSERT_DEFINED */
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344 /* Make PendSV and SysTick the lowest priority interrupts. */
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345 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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346 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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348 /* Start the timer that generates the tick ISR. Interrupts are disabled
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350 vPortSetupTimerInterrupt();
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352 /* Initialise the critical nesting count ready for the first task. */
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353 uxCriticalNesting = 0;
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355 /* Ensure the VFP is enabled - it should be anyway. */
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358 /* Lazy save always. */
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359 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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361 /* Start the first task. */
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362 prvPortStartFirstTask();
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364 /* Should never get here as the tasks will now be executing! Call the task
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365 exit error function to prevent compiler warnings about a static function
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366 not being called in the case that the application writer overrides this
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367 functionality by defining configTASK_RETURN_ADDRESS. */
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368 prvTaskExitError();
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370 /* Should not get here! */
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373 /*-----------------------------------------------------------*/
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375 void vPortEndScheduler( void )
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377 /* Not implemented in ports where there is nothing to return to.
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378 Artificially force an assert. */
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379 configASSERT( uxCriticalNesting == 1000UL );
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381 /*-----------------------------------------------------------*/
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383 void vPortYield( void )
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385 /* Set a PendSV to request a context switch. */
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386 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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388 /* Barriers are normally not required but do ensure the code is completely
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389 within the specified behaviour for the architecture. */
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390 __asm volatile( "dsb" );
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391 __asm volatile( "isb" );
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393 /*-----------------------------------------------------------*/
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395 void vPortEnterCritical( void )
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397 portDISABLE_INTERRUPTS();
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398 uxCriticalNesting++;
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399 __asm volatile( "dsb" );
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400 __asm volatile( "isb" );
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402 /*-----------------------------------------------------------*/
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404 void vPortExitCritical( void )
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406 configASSERT( uxCriticalNesting );
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407 uxCriticalNesting--;
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408 if( uxCriticalNesting == 0 )
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410 portENABLE_INTERRUPTS();
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413 /*-----------------------------------------------------------*/
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415 __attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )
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419 " mrs r0, basepri \n" \
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421 " msr basepri, r1 \n" \
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423 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
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426 /* This return will not be reached but is necessary to prevent compiler
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430 /*-----------------------------------------------------------*/
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432 __attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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436 " msr basepri, r0 \n" \
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441 /* Just to avoid compiler warnings. */
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442 ( void ) ulNewMaskValue;
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444 /*-----------------------------------------------------------*/
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446 void xPortPendSVHandler( void )
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448 /* This is a naked function. */
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455 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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458 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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460 " vstmdbeq r0!, {s16-s31} \n"
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462 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
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464 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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466 " stmdb sp!, {r3} \n"
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468 " msr basepri, r0 \n"
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469 " bl vTaskSwitchContext \n"
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471 " msr basepri, r0 \n"
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472 " ldmia sp!, {r3} \n"
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474 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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477 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
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479 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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481 " vldmiaeq r0!, {s16-s31} \n"
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486 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
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487 #if WORKAROUND_PMU_CM001 == 1
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496 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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497 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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500 /*-----------------------------------------------------------*/
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502 void xPortSysTickHandler( void )
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504 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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505 executes all interrupts must be unmasked. There is therefore no need to
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506 save and then restore the interrupt mask value as its value is already
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508 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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510 /* Increment the RTOS tick. */
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511 if( xTaskIncrementTick() != pdFALSE )
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513 /* A context switch is required. Context switching is performed in
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514 the PendSV interrupt. Pend the PendSV interrupt. */
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515 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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518 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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520 /*-----------------------------------------------------------*/
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522 #if configUSE_TICKLESS_IDLE == 1
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524 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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526 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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527 TickType_t xModifiableIdleTime;
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529 /* Make sure the SysTick reload value does not overflow the counter. */
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530 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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532 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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535 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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536 is accounted for as best it can be, but using the tickless mode will
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537 inevitably result in some tiny drift of the time maintained by the
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538 kernel with respect to calendar time. */
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539 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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541 /* Calculate the reload value required to wait xExpectedIdleTime
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542 tick periods. -1 is used because this code will execute part way
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543 through one of the tick periods. */
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544 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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545 if( ulReloadValue > ulStoppedTimerCompensation )
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547 ulReloadValue -= ulStoppedTimerCompensation;
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550 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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551 method as that will mask interrupts that should exit sleep mode. */
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552 __asm volatile( "cpsid i" );
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554 /* If a context switch is pending or a task is waiting for the scheduler
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555 to be unsuspended then abandon the low power entry. */
\r
556 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
558 /* Restart from whatever is left in the count register to complete
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559 this tick period. */
\r
560 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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562 /* Restart SysTick. */
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563 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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565 /* Reset the reload register to the value required for normal tick
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567 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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569 /* Re-enable interrupts - see comments above the cpsid instruction()
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571 __asm volatile( "cpsie i" );
\r
575 /* Set the new reload value. */
\r
576 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
578 /* Clear the SysTick count flag and set the count value back to
\r
580 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
582 /* Restart SysTick. */
\r
583 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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585 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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586 set its parameter to 0 to indicate that its implementation contains
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587 its own wait for interrupt or wait for event instruction, and so wfi
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588 should not be executed again. However, the original expected idle
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589 time variable must remain unmodified, so a copy is taken. */
\r
590 xModifiableIdleTime = xExpectedIdleTime;
\r
591 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
592 if( xModifiableIdleTime > 0 )
\r
594 __asm volatile( "dsb" );
\r
595 __asm volatile( "wfi" );
\r
596 __asm volatile( "isb" );
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598 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
600 /* Stop SysTick. Again, the time the SysTick is stopped for is
\r
601 accounted for as best it can be, but using the tickless mode will
\r
602 inevitably result in some tiny drift of the time maintained by the
\r
603 kernel with respect to calendar time. */
\r
604 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
\r
605 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
\r
607 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
609 __asm volatile( "cpsie i" );
\r
611 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
613 uint32_t ulCalculatedLoadValue;
\r
615 /* The tick interrupt has already executed, and the SysTick
\r
616 count reloaded with ulReloadValue. Reset the
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617 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
619 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
621 /* Don't allow a tiny value, or values that have somehow
\r
622 underflowed because the post sleep hook did something
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623 that took too long. */
\r
624 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
626 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
629 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
631 /* The tick interrupt handler will already have pended the tick
\r
632 processing in the kernel. As the pending tick will be
\r
633 processed as soon as this function exits, the tick value
\r
634 maintained by the tick is stepped forward by one less than the
\r
635 time spent waiting. */
\r
636 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
640 /* Something other than the tick interrupt ended the sleep.
\r
641 Work out how long the sleep lasted rounded to complete tick
\r
642 periods (not the ulReload value which accounted for part
\r
644 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
646 /* How many complete tick periods passed while the processor
\r
648 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
650 /* The reload value is set to whatever fraction of a single tick
\r
652 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
655 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
656 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
657 value. The critical section is used to ensure the tick interrupt
\r
658 can only execute once in the case that the reload register is near
\r
660 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
661 portENTER_CRITICAL();
\r
663 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
664 vTaskStepTick( ulCompleteTickPeriods );
\r
665 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
667 portEXIT_CRITICAL();
\r
671 #endif /* #if configUSE_TICKLESS_IDLE */
\r
672 /*-----------------------------------------------------------*/
\r
675 * Setup the systick timer to generate the tick interrupts at the required
\r
678 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
680 /* Calculate the constants required to configure the tick interrupt. */
\r
681 #if configUSE_TICKLESS_IDLE == 1
\r
683 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
684 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
685 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
687 #endif /* configUSE_TICKLESS_IDLE */
\r
689 /* Configure SysTick to interrupt at the requested rate. */
\r
690 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
\r
691 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
693 /*-----------------------------------------------------------*/
\r
695 /* This is a naked function. */
\r
696 static void vPortEnableVFP( void )
\r
700 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
703 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
708 /*-----------------------------------------------------------*/
\r
710 #if( configASSERT_DEFINED == 1 )
\r
712 void vPortValidateInterruptPriority( void )
\r
714 uint32_t ulCurrentInterrupt;
\r
715 uint8_t ucCurrentPriority;
\r
717 /* Obtain the number of the currently executing interrupt. */
\r
718 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
720 /* Is the interrupt number a user defined interrupt? */
\r
721 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
723 /* Look up the interrupt's priority. */
\r
724 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
726 /* The following assertion will fail if a service routine (ISR) for
\r
727 an interrupt that has been assigned a priority above
\r
728 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
729 function. ISR safe FreeRTOS API functions must *only* be called
\r
730 from interrupts that have been assigned a priority at or below
\r
731 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
733 Numerically low interrupt priority numbers represent logically high
\r
734 interrupt priorities, therefore the priority of the interrupt must
\r
735 be set to a value equal to or numerically *higher* than
\r
736 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
738 Interrupts that use the FreeRTOS API must not be left at their
\r
739 default priority of zero as that is the highest possible priority,
\r
740 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
741 and therefore also guaranteed to be invalid.
\r
743 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
744 interrupt entry is as fast and simple as possible.
\r
746 The following links provide detailed information:
\r
747 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
748 http://www.freertos.org/FAQHelp.html */
\r
749 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
752 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
753 that define each interrupt's priority to be split between bits that
\r
754 define the interrupt's pre-emption priority bits and bits that define
\r
755 the interrupt's sub-priority. For simplicity all bits must be defined
\r
756 to be pre-emption priority bits. The following assertion will fail if
\r
757 this is not the case (if some bits represent a sub-priority).
\r
759 If the application only uses CMSIS libraries for interrupt
\r
760 configuration then the correct setting can be achieved on all Cortex-M
\r
761 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
762 scheduler. Note however that some vendor specific peripheral libraries
\r
763 assume a non-zero priority group setting, in which cases using a value
\r
764 of zero will result in unpredicable behaviour. */
\r
765 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
768 #endif /* configASSERT_DEFINED */
\r