2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /*-----------------------------------------------------------
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76 * Implementation of functions defined in portable.h for the ARM CM4F port.
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77 *----------------------------------------------------------*/
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79 /* Scheduler includes. */
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80 #include "FreeRTOS.h"
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84 #error This port can only be used when the project options are configured to enable hardware floating point support.
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87 #ifndef configSYSTICK_CLOCK_HZ
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88 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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91 /* Constants required to manipulate the core. Registers first... */
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92 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
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93 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
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94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
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95 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
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96 /* ...then bits in the registers. */
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97 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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98 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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99 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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101 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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104 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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105 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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107 /* Constants required to manipulate the VFP. */
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108 #define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */
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109 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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111 /* Constants required to set up the initial stack. */
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112 #define portINITIAL_XPSR ( 0x01000000 )
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113 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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115 /* The priority used by the kernel is assigned to a variable to make access
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116 from inline assembler easier. */
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117 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
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119 /* Each task maintains its own interrupt status in the critical nesting
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121 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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124 * Setup the timer to generate the tick interrupts. The implementation in this
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125 * file is weak to allow application writers to change the timer used to
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126 * generate the tick interrupt.
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128 void vPortSetupTimerInterrupt( void );
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131 * Exception handlers.
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133 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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134 void xPortSysTickHandler( void );
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135 void vPortSVCHandler( void ) __attribute__ (( naked ));
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138 * Start first task is a separate function so it can be tested in isolation.
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140 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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143 * Function to enable the VFP.
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145 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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147 /*-----------------------------------------------------------*/
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150 * The number of SysTick increments that make up one tick period.
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152 #if configUSE_TICKLESS_IDLE == 1
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153 static unsigned long ulTimerReloadValueForOneTick = 0;
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157 * The maximum number of tick periods that can be suppressed is limited by the
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158 * 24 bit resolution of the SysTick timer.
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160 #if configUSE_TICKLESS_IDLE == 1
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161 static unsigned long xMaximumPossibleSuppressedTicks = 0;
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162 #endif /* configUSE_TICKLESS_IDLE */
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165 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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166 * power functionality only.
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168 #if configUSE_TICKLESS_IDLE == 1
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169 static unsigned long ulStoppedTimerCompensation = 0;
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170 #endif /* configUSE_TICKLESS_IDLE */
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172 /*-----------------------------------------------------------*/
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175 * See header file for description.
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177 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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179 /* Simulate the stack frame as it would be created by a context switch
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182 /* Offset added to account for the way the MCU uses the stack on entry/exit
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183 of interrupts, and to ensure alignment. */
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186 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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188 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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190 *pxTopOfStack = 0; /* LR */
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192 /* Save code space by skipping register initialisation. */
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193 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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194 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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196 /* A save method is being used that requires each task to maintain its
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197 own exec return value. */
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199 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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201 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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203 return pxTopOfStack;
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205 /*-----------------------------------------------------------*/
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207 void vPortSVCHandler( void )
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210 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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211 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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212 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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213 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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214 " msr psp, r0 \n" /* Restore the task stack pointer. */
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216 " msr basepri, r0 \n"
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220 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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223 /*-----------------------------------------------------------*/
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225 static void prvPortStartFirstTask( void )
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228 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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231 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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232 " cpsie i \n" /* Globally enable interrupts. */
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233 " svc 0 \n" /* System call to start first task. */
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237 /*-----------------------------------------------------------*/
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240 * See header file for description.
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242 portBASE_TYPE xPortStartScheduler( void )
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244 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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245 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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246 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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248 /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
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249 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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250 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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252 /* Start the timer that generates the tick ISR. Interrupts are disabled
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254 vPortSetupTimerInterrupt();
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256 /* Initialise the critical nesting count ready for the first task. */
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257 uxCriticalNesting = 0;
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259 /* Ensure the VFP is enabled - it should be anyway. */
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262 /* Lazy save always. */
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263 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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265 /* Start the first task. */
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266 prvPortStartFirstTask();
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268 /* Should not get here! */
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271 /*-----------------------------------------------------------*/
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273 void vPortEndScheduler( void )
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275 /* It is unlikely that the CM4F port will require this function as there
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276 is nothing to return to. */
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278 /*-----------------------------------------------------------*/
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280 void vPortYield( void )
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282 /* Set a PendSV to request a context switch. */
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283 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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285 /* Barriers are normally not required but do ensure the code is completely
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286 within the specified behaviour for the architecture. */
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287 __asm volatile( "dsb" );
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288 __asm volatile( "isb" );
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290 /*-----------------------------------------------------------*/
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292 void vPortEnterCritical( void )
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294 portDISABLE_INTERRUPTS();
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295 uxCriticalNesting++;
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296 __asm volatile( "dsb" );
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297 __asm volatile( "isb" );
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299 /*-----------------------------------------------------------*/
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301 void vPortExitCritical( void )
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303 uxCriticalNesting--;
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304 if( uxCriticalNesting == 0 )
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306 portENABLE_INTERRUPTS();
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309 /*-----------------------------------------------------------*/
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311 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )
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315 " mrs r0, basepri \n" \
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317 " msr basepri, r1 \n" \
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319 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
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322 /* This return will not be reached but is necessary to prevent compiler
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326 /*-----------------------------------------------------------*/
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328 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )
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332 " msr basepri, r0 \n" \
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337 /* Just to avoid compiler warnings. */
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338 ( void ) ulNewMaskValue;
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340 /*-----------------------------------------------------------*/
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342 void xPortPendSVHandler( void )
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344 /* This is a naked function. */
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350 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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353 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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355 " vstmdbeq r0!, {s16-s31} \n"
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357 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
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359 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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361 " stmdb sp!, {r3, r14} \n"
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363 " msr basepri, r0 \n"
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364 " bl vTaskSwitchContext \n"
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366 " msr basepri, r0 \n"
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367 " ldmia sp!, {r3, r14} \n"
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369 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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372 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
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374 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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376 " vldmiaeq r0!, {s16-s31} \n"
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382 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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383 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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386 /*-----------------------------------------------------------*/
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388 void xPortSysTickHandler( void )
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390 /* If using preemption, also force a context switch. */
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391 #if configUSE_PREEMPTION == 1
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392 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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395 /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to
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396 1. If it is set to 0 tickless idle is not being used. If it is set to a
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397 value other than 0 or 1 then a timer other than the SysTick is being used
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398 to generate the tick interrupt. */
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399 #if configUSE_TICKLESS_IDLE == 1
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400 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;
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403 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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405 vTaskIncrementTick();
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407 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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409 /*-----------------------------------------------------------*/
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411 #if configUSE_TICKLESS_IDLE == 1
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413 __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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415 unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;
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416 portTickType xModifiableIdleTime;
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418 /* Make sure the SysTick reload value does not overflow the counter. */
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419 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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421 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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424 /* Calculate the reload value required to wait xExpectedIdleTime
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425 tick periods. -1 is used because this code will execute part way
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426 through one of the tick periods, and the fraction of a tick period is
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427 accounted for later. */
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428 ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );
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429 if( ulReloadValue > ulStoppedTimerCompensation )
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431 ulReloadValue -= ulStoppedTimerCompensation;
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434 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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435 is accounted for as best it can be, but using the tickless mode will
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436 inevitably result in some tiny drift of the time maintained by the
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437 kernel with respect to calendar time. */
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438 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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440 /* Adjust the reload value to take into account that the current time
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441 slice is already partially complete. */
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442 ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );
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444 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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445 method as that will mask interrupts that should exit sleep mode. */
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446 __asm volatile( "cpsid i" );
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448 /* If a context switch is pending or a task is waiting for the scheduler
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449 to be unsuspended then abandon the low power entry. */
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450 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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452 /* Restart SysTick. */
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453 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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455 /* Re-enable interrupts - see comments above the cpsid instruction()
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457 __asm volatile( "cpsie i" );
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461 /* Set the new reload value. */
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462 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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464 /* Clear the SysTick count flag and set the count value back to
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466 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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468 /* Restart SysTick. */
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469 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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471 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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472 set its parameter to 0 to indicate that its implementation contains
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473 its own wait for interrupt or wait for event instruction, and so wfi
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474 should not be executed again. However, the original expected idle
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475 time variable must remain unmodified, so a copy is taken. */
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476 xModifiableIdleTime = xExpectedIdleTime;
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477 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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478 if( xModifiableIdleTime > 0 )
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480 __asm volatile( "wfi" );
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481 __asm volatile( "dsb" );
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482 __asm volatile( "isb" );
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484 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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486 /* Stop SysTick. Again, the time the SysTick is stopped for is
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487 accounted for as best it can be, but using the tickless mode will
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488 inevitably result in some tiny drift of the time maintained by the
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489 kernel with respect to calendar time. */
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490 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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492 /* Re-enable interrupts - see comments above the cpsid instruction()
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494 __asm volatile( "cpsie i" );
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496 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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498 /* The tick interrupt has already executed, and the SysTick
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499 count reloaded with the portNVIC_SYSTICK_LOAD_REG value.
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500 Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of
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501 this tick period. */
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502 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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504 /* The tick interrupt handler will already have pended the tick
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505 processing in the kernel. As the pending tick will be
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506 processed as soon as this function exits, the tick value
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507 maintained by the tick is stepped forward by one less than the
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508 time spent waiting. */
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509 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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513 /* Something other than the tick interrupt ended the sleep.
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514 Work out how long the sleep lasted. */
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515 ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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517 /* How many complete tick periods passed while the processor
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519 ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;
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521 /* The reload value is set to whatever fraction of a single tick
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523 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;
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526 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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527 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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529 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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530 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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532 vTaskStepTick( ulCompleteTickPeriods );
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536 #endif /* #if configUSE_TICKLESS_IDLE */
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537 /*-----------------------------------------------------------*/
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540 * Setup the systick timer to generate the tick interrupts at the required
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543 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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545 /* Calculate the constants required to configure the tick interrupt. */
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546 #if configUSE_TICKLESS_IDLE == 1
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548 ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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549 xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
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550 ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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552 #endif /* configUSE_TICKLESS_IDLE */
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554 /* Configure SysTick to interrupt at the requested rate. */
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555 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
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556 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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558 /*-----------------------------------------------------------*/
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560 /* This is a naked function. */
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561 static void vPortEnableVFP( void )
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565 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
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568 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
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