git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
   8      *    FreeRTOS provides completely free yet professionally developed,    *\r
   9      *    robust, strictly quality controlled, supported, and cross          *\r
  10      *    platform software that has become a de facto standard.             *\r
  11      *                                                                       *\r
  12      *    Help yourself get started quickly and support the FreeRTOS         *\r
  13      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  15      *                                                                       *\r
  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
  31     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  41      *    not run, what could be wrong?"                                     *\r
  42      *                                                                       *\r
  43      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  44      *                                                                       *\r
  45     ***************************************************************************\r
  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  48     license and Real Time Engineers Ltd. contact details.\r
  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  52     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  55     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  56     licenses offer ticketed support, indemnification and middleware.\r
  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 /*-----------------------------------------------------------\r
  66  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  67  *----------------------------------------------------------*/\r
  68 \r
  69 /* Scheduler includes. */\r
  70 #include "FreeRTOS.h"\r
  71 #include "task.h"\r
  72 \r
  73 #ifndef __VFP_FP__\r
  74         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  75 #endif\r
  76 \r
  77 #ifndef configSYSTICK_CLOCK_HZ\r
  78         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  79 #endif\r
  80 \r
  81 /* Constants required to manipulate the core.  Registers first... */\r
  82 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  83 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  84 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  85 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  86 /* ...then bits in the registers. */\r
  87 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  88 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  89 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  90 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  91 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
  92 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
  93 \r
  94 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  95 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  96 \r
  97 /* Constants required to check the validity of an interrupt prority. */\r
  98 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
  99 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 100 #define portAIRCR_REG                                           ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
 101 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 102 \r
 103 /* Constants required to manipulate the VFP. */\r
 104 #define portFPCCR                                       ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
 105 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
 106 \r
 107 /* Constants required to set up the initial stack. */\r
 108 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 109 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 110 \r
 111 /* The systick is a 24-bit counter. */\r
 112 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 113 \r
 114 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 115 occurred while the SysTick counter is stopped during tickless idle\r
 116 calculations. */\r
 117 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 118 \r
 119 /* Each task maintains its own interrupt status in the critical nesting\r
 120 variable. */\r
 121 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 122 \r
 123 /*\r
 124  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 125  * file is weak to allow application writers to change the timer used to\r
 126  * generate the tick interrupt.\r
 127  */\r
 128 void vPortSetupTimerInterrupt( void );\r
 129 \r
 130 /*\r
 131  * Exception handlers.\r
 132  */\r
 133 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 134 void xPortSysTickHandler( void );\r
 135 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 136 \r
 137 /*\r
 138  * Start first task is a separate function so it can be tested in isolation.\r
 139  */\r
 140 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 141 \r
 142 /*\r
 143  * Function to enable the VFP.\r
 144  */\r
 145  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 146 \r
 147 /*-----------------------------------------------------------*/\r
 148 \r
 149 /*\r
 150  * The number of SysTick increments that make up one tick period.\r
 151  */\r
 152 #if configUSE_TICKLESS_IDLE == 1\r
 153         static unsigned long ulTimerCountsForOneTick = 0;\r
 154 #endif /* configUSE_TICKLESS_IDLE */\r
 155 \r
 156 /*\r
 157  * The maximum number of tick periods that can be suppressed is limited by the\r
 158  * 24 bit resolution of the SysTick timer.\r
 159  */\r
 160 #if configUSE_TICKLESS_IDLE == 1\r
 161         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 162 #endif /* configUSE_TICKLESS_IDLE */\r
 163 \r
 164 /*\r
 165  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 166  * power functionality only.\r
 167  */\r
 168 #if configUSE_TICKLESS_IDLE == 1\r
 169         static unsigned long ulStoppedTimerCompensation = 0;\r
 170 #endif /* configUSE_TICKLESS_IDLE */\r
 171 \r
 172 /*\r
 173  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure \r
 174  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 175  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 176  */\r
 177 #if ( configASSERT_DEFINED == 1 )\r
 178          static unsigned char ucMaxSysCallPriority = 0;\r
 179          static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 180 #endif /* configASSERT_DEFINED */\r
 181 \r
 182 /*-----------------------------------------------------------*/\r
 183 \r
 184 /*\r
 185  * See header file for description.\r
 186  */\r
 187 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 188 {\r
 189         /* Simulate the stack frame as it would be created by a context switch\r
 190         interrupt. */\r
 191 \r
 192         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 193         of interrupts, and to ensure alignment. */\r
 194         pxTopOfStack--;\r
 195 \r
 196         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 197         pxTopOfStack--;\r
 198         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 199         pxTopOfStack--;\r
 200         *pxTopOfStack = 0;      /* LR */\r
 201 \r
 202         /* Save code space by skipping register initialisation. */\r
 203         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 204         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 205 \r
 206         /* A save method is being used that requires each task to maintain its\r
 207         own exec return value. */\r
 208         pxTopOfStack--;\r
 209         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 210 \r
 211         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 212 \r
 213         return pxTopOfStack;\r
 214 }\r
 215 /*-----------------------------------------------------------*/\r
 216 \r
 217 void vPortSVCHandler( void )\r
 218 {\r
 219         __asm volatile (\r
 220                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 221                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 222                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 223                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 224                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 225                                         "       mov r0, #0                                              \n"\r
 226                                         "       msr     basepri, r0                                     \n"\r
 227                                         "       bx r14                                                  \n"\r
 228                                         "                                                                       \n"\r
 229                                         "       .align 2                                                \n"\r
 230                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 231                                 );\r
 232 }\r
 233 /*-----------------------------------------------------------*/\r
 234 \r
 235 static void prvPortStartFirstTask( void )\r
 236 {\r
 237         __asm volatile(\r
 238                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 239                                         " ldr r0, [r0]                  \n"\r
 240                                         " ldr r0, [r0]                  \n"\r
 241                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 242                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 243                                         " svc 0                                 \n" /* System call to start first task. */\r
 244                                         " nop                                   \n"\r
 245                                 );\r
 246 }\r
 247 /*-----------------------------------------------------------*/\r
 248 \r
 249 /*\r
 250  * See header file for description.\r
 251  */\r
 252 portBASE_TYPE xPortStartScheduler( void )\r
 253 {\r
 254         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 255         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 256         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 257 \r
 258         #if( configASSERT_DEFINED == 1 )\r
 259         {\r
 260                 volatile unsigned long ulOriginalPriority;\r
 261                 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 262 \r
 263                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 264                 functions can be called.  ISR safe functions are those that end in\r
 265                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 266                 ensure interrupt entry is as fast and simple as possible.\r
 267 \r
 268                 Save the interrupt priority value that is about to be clobbered. */\r
 269                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 270 \r
 271                 /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
 272                 priority register. */\r
 273                 *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
 274 \r
 275                 /* Read back the written priority to obtain its value as seen by the\r
 276                 hardware, which will only implement a subset of the priority bits. */\r
 277                 ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
 278 \r
 279                 /* Restore the clobbered interrupt priority register to its original\r
 280                 value. */\r
 281                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 282         }\r
 283         #endif /* conifgASSERT_DEFINED */\r
 284 \r
 285         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 286         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 287         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 288 \r
 289         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 290         here already. */\r
 291         vPortSetupTimerInterrupt();\r
 292 \r
 293         /* Initialise the critical nesting count ready for the first task. */\r
 294         uxCriticalNesting = 0;\r
 295 \r
 296         /* Ensure the VFP is enabled - it should be anyway. */\r
 297         vPortEnableVFP();\r
 298 \r
 299         /* Lazy save always. */\r
 300         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 301 \r
 302         /* Start the first task. */\r
 303         prvPortStartFirstTask();\r
 304 \r
 305         /* Should not get here! */\r
 306         return 0;\r
 307 }\r
 308 /*-----------------------------------------------------------*/\r
 309 \r
 310 void vPortEndScheduler( void )\r
 311 {\r
 312         /* It is unlikely that the CM4F port will require this function as there\r
 313         is nothing to return to.  */\r
 314 }\r
 315 /*-----------------------------------------------------------*/\r
 316 \r
 317 void vPortYield( void )\r
 318 {\r
 319         /* Set a PendSV to request a context switch. */\r
 320         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 321 \r
 322         /* Barriers are normally not required but do ensure the code is completely\r
 323         within the specified behaviour for the architecture. */\r
 324         __asm volatile( "dsb" );\r
 325         __asm volatile( "isb" );\r
 326 }\r
 327 /*-----------------------------------------------------------*/\r
 328 \r
 329 void vPortEnterCritical( void )\r
 330 {\r
 331         portDISABLE_INTERRUPTS();\r
 332         uxCriticalNesting++;\r
 333         __asm volatile( "dsb" );\r
 334         __asm volatile( "isb" );\r
 335 }\r
 336 /*-----------------------------------------------------------*/\r
 337 \r
 338 void vPortExitCritical( void )\r
 339 {\r
 340         uxCriticalNesting--;\r
 341         if( uxCriticalNesting == 0 )\r
 342         {\r
 343                 portENABLE_INTERRUPTS();\r
 344         }\r
 345 }\r
 346 /*-----------------------------------------------------------*/\r
 347 \r
 348 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 349 {\r
 350         __asm volatile                                                                                                          \\r
 351         (                                                                                                                                       \\r
 352                 "       mrs r0, basepri                                                                                 \n" \\r
 353                 "       mov r1, %0                                                                                              \n"     \\r
 354                 "       msr basepri, r1                                                                                 \n" \\r
 355                 "       bx lr                                                                                                   \n" \\r
 356                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 357         );\r
 358 \r
 359         /* This return will not be reached but is necessary to prevent compiler\r
 360         warnings. */\r
 361         return 0;\r
 362 }\r
 363 /*-----------------------------------------------------------*/\r
 364 \r
 365 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 366 {\r
 367         __asm volatile                                                                                                  \\r
 368         (                                                                                                                               \\r
 369                 "       msr basepri, r0                                                                         \n"     \\r
 370                 "       bx lr                                                                                           \n" \\r
 371                 :::"r0"                                                                                                         \\r
 372         );\r
 373 \r
 374         /* Just to avoid compiler warnings. */\r
 375         ( void ) ulNewMaskValue;\r
 376 }\r
 377 /*-----------------------------------------------------------*/\r
 378 \r
 379 void xPortPendSVHandler( void )\r
 380 {\r
 381         /* This is a naked function. */\r
 382 \r
 383         __asm volatile\r
 384         (\r
 385         "       mrs r0, psp                                                     \n"\r
 386         "                                                                               \n"\r
 387         "       ldr     r3, pxCurrentTCBConst                           \n" /* Get the location of the current TCB. */\r
 388         "       ldr     r2, [r3]                                                \n"\r
 389         "                                                                               \n"\r
 390         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 391         "       it eq                                                           \n"\r
 392         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 393         "                                                                               \n"\r
 394         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 395         "                                                                               \n"\r
 396         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 397         "                                                                               \n"\r
 398         "       stmdb sp!, {r3, r14}                            \n"\r
 399         "       mov r0, %0                                                      \n"\r
 400         "       msr basepri, r0                                         \n"\r
 401         "       bl vTaskSwitchContext                           \n"\r
 402         "       mov r0, #0                                                      \n"\r
 403         "       msr basepri, r0                                         \n"\r
 404         "       ldmia sp!, {r3, r14}                            \n"\r
 405         "                                                                               \n"\r
 406         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 407         "       ldr r0, [r1]                                            \n"\r
 408         "                                                                               \n"\r
 409         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 410         "                                                                               \n"\r
 411         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 412         "       it eq                                                           \n"\r
 413         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 414         "                                                                               \n"\r
 415         "       msr psp, r0                                                     \n"\r
 416         "       bx r14                                                          \n"\r
 417         "                                                                               \n"\r
 418         "       .align 2                                                        \n"\r
 419         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 420         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 421         );\r
 422 }\r
 423 /*-----------------------------------------------------------*/\r
 424 \r
 425 void xPortSysTickHandler( void )\r
 426 {\r
 427         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 428         executes all interrupts must be unmasked.  There is therefore no need to\r
 429         save and then restore the interrupt mask value as its value is already\r
 430         known. */\r
 431         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 432         {\r
 433                 /* Increment the RTOS tick. */\r
 434                 if( xTaskIncrementTick() != pdFALSE )\r
 435                 {\r
 436                         /* A context switch is required.  Context switching is performed in\r
 437                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 438                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 439                 }\r
 440         }\r
 441         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 442 }\r
 443 /*-----------------------------------------------------------*/\r
 444 \r
 445 #if configUSE_TICKLESS_IDLE == 1\r
 446 \r
 447         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 448         {\r
 449         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 450         portTickType xModifiableIdleTime;\r
 451 \r
 452                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 453                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 454                 {\r
 455                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 456                 }\r
 457 \r
 458                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 459                 is accounted for as best it can be, but using the tickless mode will\r
 460                 inevitably result in some tiny drift of the time maintained by the\r
 461                 kernel with respect to calendar time. */\r
 462                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 463 \r
 464                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 465                 tick periods.  -1 is used because this code will execute part way\r
 466                 through one of the tick periods. */\r
 467                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 468                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 469                 {\r
 470                         ulReloadValue -= ulStoppedTimerCompensation;\r
 471                 }\r
 472 \r
 473                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 474                 method as that will mask interrupts that should exit sleep mode. */\r
 475                 __asm volatile( "cpsid i" );\r
 476 \r
 477                 /* If a context switch is pending or a task is waiting for the scheduler\r
 478                 to be unsuspended then abandon the low power entry. */\r
 479                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 480                 {\r
 481                         /* Restart SysTick. */\r
 482                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 483 \r
 484                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 485                         above. */\r
 486                         __asm volatile( "cpsie i" );\r
 487                 }\r
 488                 else\r
 489                 {\r
 490                         /* Set the new reload value. */\r
 491                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 492 \r
 493                         /* Clear the SysTick count flag and set the count value back to\r
 494                         zero. */\r
 495                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 496 \r
 497                         /* Restart SysTick. */\r
 498                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 499 \r
 500                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 501                         set its parameter to 0 to indicate that its implementation contains\r
 502                         its own wait for interrupt or wait for event instruction, and so wfi\r
 503                         should not be executed again.  However, the original expected idle\r
 504                         time variable must remain unmodified, so a copy is taken. */\r
 505                         xModifiableIdleTime = xExpectedIdleTime;\r
 506                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 507                         if( xModifiableIdleTime > 0 )\r
 508                         {\r
 509                                 __asm volatile( "dsb" );\r
 510                                 __asm volatile( "wfi" );\r
 511                                 __asm volatile( "isb" );\r
 512                         }\r
 513                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 514 \r
 515                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 516                         accounted for as best it can be, but using the tickless mode will\r
 517                         inevitably result in some tiny drift of the time maintained by the\r
 518                         kernel with respect to calendar time. */\r
 519                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 520 \r
 521                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 522                         above. */\r
 523                         __asm volatile( "cpsie i" );\r
 524 \r
 525                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 526                         {\r
 527                                 /* The tick interrupt has already executed, and the SysTick\r
 528                                 count reloaded with ulReloadValue.  Reset the\r
 529                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 530                                 period. */\r
 531                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 532 \r
 533                                 /* The tick interrupt handler will already have pended the tick\r
 534                                 processing in the kernel.  As the pending tick will be\r
 535                                 processed as soon as this function exits, the tick value\r
 536                                 maintained by the tick is stepped forward by one less than the\r
 537                                 time spent waiting. */\r
 538                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 539                         }\r
 540                         else\r
 541                         {\r
 542                                 /* Something other than the tick interrupt ended the sleep.\r
 543                                 Work out how long the sleep lasted rounded to complete tick\r
 544                                 periods (not the ulReload value which accounted for part\r
 545                                 ticks). */\r
 546                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 547 \r
 548                                 /* How many complete tick periods passed while the processor\r
 549                                 was waiting? */\r
 550                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 551 \r
 552                                 /* The reload value is set to whatever fraction of a single tick\r
 553                                 period remains. */\r
 554                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 555                         }\r
 556 \r
 557                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 558                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 559                         value. */\r
 560                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 561                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 562 \r
 563                         vTaskStepTick( ulCompleteTickPeriods );\r
 564 \r
 565                         /* The counter must start by the time the reload value is reset. */\r
 566                         configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 567                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 568                 }\r
 569         }\r
 570 \r
 571 #endif /* #if configUSE_TICKLESS_IDLE */\r
 572 /*-----------------------------------------------------------*/\r
 573 \r
 574 /*\r
 575  * Setup the systick timer to generate the tick interrupts at the required\r
 576  * frequency.\r
 577  */\r
 578 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 579 {\r
 580         /* Calculate the constants required to configure the tick interrupt. */\r
 581         #if configUSE_TICKLESS_IDLE == 1\r
 582         {\r
 583                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 584                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 585                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 586         }\r
 587         #endif /* configUSE_TICKLESS_IDLE */\r
 588 \r
 589         /* Configure SysTick to interrupt at the requested rate. */\r
 590         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 591         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 592 }\r
 593 /*-----------------------------------------------------------*/\r
 594 \r
 595 /* This is a naked function. */\r
 596 static void vPortEnableVFP( void )\r
 597 {\r
 598         __asm volatile\r
 599         (\r
 600                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 601                 "       ldr r1, [r0]                            \n"\r
 602                 "                                                               \n"\r
 603                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 604                 "       str r1, [r0]                            \n"\r
 605                 "       bx r14                                          "\r
 606         );\r
 607 }\r
 608 /*-----------------------------------------------------------*/\r
 609 \r
 610 #if( configASSERT_DEFINED == 1 )\r
 611 \r
 612         void vPortValidateInterruptPriority( void )\r
 613         {\r
 614         unsigned long ulCurrentInterrupt;\r
 615         unsigned char ucCurrentPriority;\r
 616 \r
 617                 /* Obtain the number of the currently executing interrupt. */\r
 618                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 619 \r
 620                 /* Is the interrupt number a user defined interrupt? */\r
 621                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 622                 {\r
 623                         /* Look up the interrupt's priority. */\r
 624                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 625 \r
 626                         /* The following assertion will fail if a service routine (ISR) for \r
 627                         an interrupt that has been assigned a priority above\r
 628                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 629                         function.  ISR safe FreeRTOS API functions must *only* be called \r
 630                         from interrupts that have been assigned a priority at or below\r
 631                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 632                         \r
 633                         Numerically low interrupt priority numbers represent logically high\r
 634                         interrupt priorities, therefore the priority of the interrupt must \r
 635                         be set to a value equal to or numerically *higher* than \r
 636                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 637                         \r
 638                         Interrupts that use the FreeRTOS API must not be left at their\r
 639                         default priority of     zero as that is the highest possible priority,\r
 640                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
 641                         and     therefore also guaranteed to be invalid.  \r
 642                         \r
 643                         FreeRTOS maintains separate thread and ISR API functions to ensure \r
 644                         interrupt entry is as fast and simple as possible.\r
 645                         \r
 646                         The following links provide detailed information:\r
 647                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 648                         http://www.freertos.org/FAQHelp.html */\r
 649                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 650                 }\r
 651 \r
 652                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits \r
 653                 that define each interrupt's priority to be split between bits that \r
 654                 define the interrupt's pre-emption priority bits and bits that define\r
 655                 the interrupt's sub-priority.  For simplicity all bits must be defined \r
 656                 to be pre-emption priority bits.  The following assertion will fail if\r
 657                 this is not the case (if some bits represent a sub-priority).  \r
 658                 \r
 659                 If CMSIS libraries are being used then the correct setting can be \r
 660                 achieved by calling     NVIC_SetPriorityGrouping( 0 ); before starting the \r
 661                 scheduler. */\r
 662                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
 663         }\r
 664 \r
 665 #endif /* configASSERT_DEFINED */\r
 666 \r
 667 \r