2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM3 port.
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72 *----------------------------------------------------------*/
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74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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75 all the API functions to use the MPU wrappers. That should only be done when
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76 task.h is included from an application file. */
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77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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79 /* Scheduler includes. */
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80 #include "FreeRTOS.h"
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82 #include "event_groups.h"
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83 #include "mpu_prototypes.h"
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86 #error This port can only be used when the project options are configured to enable hardware floating point support.
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89 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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91 /* Constants required to access and manipulate the NVIC. */
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92 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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93 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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94 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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95 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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96 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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97 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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99 /* Constants required to access and manipulate the MPU. */
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100 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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101 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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102 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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103 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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104 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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105 #define portMPU_ENABLE ( 0x01UL )
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106 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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107 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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108 #define portMPU_REGION_VALID ( 0x10UL )
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109 #define portMPU_REGION_ENABLE ( 0x01UL )
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110 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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111 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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113 /* Constants required to access and manipulate the SysTick. */
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114 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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115 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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116 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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117 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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118 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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119 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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121 /* Constants required to manipulate the VFP. */
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122 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
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123 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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125 /* Constants required to set up the initial stack. */
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126 #define portINITIAL_XPSR ( 0x01000000UL )
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127 #define portINITIAL_EXEC_RETURN ( 0xfffffffdUL )
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128 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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129 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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131 /* Constants required to check the validity of an interrupt priority. */
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132 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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133 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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134 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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135 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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136 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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137 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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138 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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139 #define portPRIGROUP_SHIFT ( 8UL )
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141 /* Offsets in the stack to the parameters when inside the SVC handler. */
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142 #define portOFFSET_TO_PC ( 6 )
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144 /* For strict compliance with the Cortex-M spec the task start address should
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145 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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146 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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148 /* Each task maintains its own interrupt status in the critical nesting
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149 variable. Note this is not saved as part of the task context as context
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150 switches can only occur when uxCriticalNesting is zero. */
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151 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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154 * Setup the timer to generate the tick interrupts.
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156 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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159 * Configure a number of standard MPU regions that are used by all tasks.
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161 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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164 * Return the smallest MPU region size that a given number of bytes will fit
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165 * into. The region size is returned as the value that should be programmed
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166 * into the region attribute register for that region.
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168 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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171 * Checks to see if being called from the context of an unprivileged task, and
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172 * if so raises the privilege level and returns false - otherwise does nothing
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173 * other than return true.
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175 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
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178 * Standard FreeRTOS exception handlers.
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180 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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181 void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
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182 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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185 * Starts the scheduler by restoring the context of the first task to run.
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187 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
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190 * C portion of the SVC handler. The SVC handler is split between an asm entry
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191 * and a C wrapper for simplicity of coding and maintenance.
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193 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
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196 * Function to enable the VFP.
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198 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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201 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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202 * FreeRTOS API functions are not called from interrupts that have been assigned
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203 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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205 #if ( configASSERT_DEFINED == 1 )
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206 static uint8_t ucMaxSysCallPriority = 0;
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207 static uint32_t ulMaxPRIGROUPValue = 0;
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208 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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209 #endif /* configASSERT_DEFINED */
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211 /*-----------------------------------------------------------*/
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214 * See header file for description.
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216 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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218 /* Simulate the stack frame as it would be created by a context switch
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220 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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221 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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223 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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225 *pxTopOfStack = 0; /* LR */
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226 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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227 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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229 /* A save method is being used that requires each task to maintain its
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230 own exec return value. */
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232 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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234 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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236 if( xRunPrivileged == pdTRUE )
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238 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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242 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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245 return pxTopOfStack;
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247 /*-----------------------------------------------------------*/
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249 void vPortSVCHandler( void )
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251 /* Assumes psp was in use. */
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254 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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257 " mrseq r0, msp \n"
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258 " mrsne r0, psp \n"
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263 ::"i"(prvSVCHandler):"r0"
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266 /*-----------------------------------------------------------*/
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268 static void prvSVCHandler( uint32_t *pulParam )
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270 uint8_t ucSVCNumber;
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272 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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273 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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274 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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275 switch( ucSVCNumber )
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277 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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278 prvRestoreContextOfFirstTask();
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281 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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282 /* Barriers are normally not required
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283 but do ensure the code is completely
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284 within the specified behaviour for the
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286 __asm volatile( "dsb" );
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287 __asm volatile( "isb" );
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291 case portSVC_RAISE_PRIVILEGE : __asm volatile
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293 " mrs r1, control \n" /* Obtain current control value. */
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294 " bic r1, #1 \n" /* Set privilege bit. */
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295 " msr control, r1 \n" /* Write back new control value. */
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300 default : /* Unknown SVC call. */
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304 /*-----------------------------------------------------------*/
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306 static void prvRestoreContextOfFirstTask( void )
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310 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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313 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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314 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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316 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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317 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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318 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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319 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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320 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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321 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
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322 " msr control, r3 \n"
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323 " msr psp, r0 \n" /* Restore the task stack pointer. */
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325 " msr basepri, r0 \n"
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329 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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332 /*-----------------------------------------------------------*/
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335 * See header file for description.
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337 BaseType_t xPortStartScheduler( void )
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339 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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340 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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341 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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343 #if( configASSERT_DEFINED == 1 )
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345 volatile uint32_t ulOriginalPriority;
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346 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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347 volatile uint8_t ucMaxPriorityValue;
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349 /* Determine the maximum priority from which ISR safe FreeRTOS API
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350 functions can be called. ISR safe functions are those that end in
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351 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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352 ensure interrupt entry is as fast and simple as possible.
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354 Save the interrupt priority value that is about to be clobbered. */
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355 ulOriginalPriority = *pucFirstUserPriorityRegister;
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357 /* Determine the number of priority bits available. First write to all
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359 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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361 /* Read the value back to see how many bits stuck. */
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362 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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364 /* Use the same mask on the maximum system call priority. */
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365 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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367 /* Calculate the maximum acceptable priority group value for the number
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368 of bits read back. */
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369 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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370 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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372 ulMaxPRIGROUPValue--;
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373 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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376 /* Shift the priority group value back to its position within the AIRCR
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378 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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379 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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381 /* Restore the clobbered interrupt priority register to its original
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383 *pucFirstUserPriorityRegister = ulOriginalPriority;
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385 #endif /* conifgASSERT_DEFINED */
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387 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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388 handler higher priority so it can be used to exit a critical section (where
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389 lower priorities are masked). */
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390 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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391 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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393 /* Configure the regions in the MPU that are common to all tasks. */
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396 /* Start the timer that generates the tick ISR. Interrupts are disabled
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398 prvSetupTimerInterrupt();
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400 /* Initialise the critical nesting count ready for the first task. */
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401 uxCriticalNesting = 0;
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403 /* Ensure the VFP is enabled - it should be anyway. */
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406 /* Lazy save always. */
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407 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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409 /* Start the first task. */
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411 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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414 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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415 " cpsie i \n" /* Globally enable interrupts. */
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419 " svc %0 \n" /* System call to start first task. */
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421 :: "i" (portSVC_START_SCHEDULER) );
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423 /* Should not get here! */
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426 /*-----------------------------------------------------------*/
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428 void vPortEndScheduler( void )
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430 /* Not implemented in ports where there is nothing to return to.
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431 Artificially force an assert. */
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432 configASSERT( uxCriticalNesting == 1000UL );
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434 /*-----------------------------------------------------------*/
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436 void vPortEnterCritical( void )
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438 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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440 portDISABLE_INTERRUPTS();
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441 uxCriticalNesting++;
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443 vPortResetPrivilege( xRunningPrivileged );
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445 /*-----------------------------------------------------------*/
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447 void vPortExitCritical( void )
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449 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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451 configASSERT( uxCriticalNesting );
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452 uxCriticalNesting--;
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453 if( uxCriticalNesting == 0 )
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455 portENABLE_INTERRUPTS();
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457 vPortResetPrivilege( xRunningPrivileged );
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459 /*-----------------------------------------------------------*/
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461 void xPortPendSVHandler( void )
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463 /* This is a naked function. */
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469 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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472 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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474 " vstmdbeq r0!, {s16-s31} \n"
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476 " mrs r1, control \n"
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477 " stmdb r0!, {r1, r4-r11, r14} \n" /* Save the remaining registers. */
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478 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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480 " stmdb sp!, {r3} \n"
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482 " msr basepri, r0 \n"
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485 " bl vTaskSwitchContext \n"
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487 " msr basepri, r0 \n"
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488 " ldmia sp!, {r3} \n"
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489 " \n" /* Restore the context. */
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491 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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492 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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493 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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494 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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495 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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496 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
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497 " msr control, r3 \n"
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499 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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501 " vldmiaeq r0!, {s16-s31} \n"
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507 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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508 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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511 /*-----------------------------------------------------------*/
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513 void xPortSysTickHandler( void )
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517 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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519 /* Increment the RTOS tick. */
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520 if( xTaskIncrementTick() != pdFALSE )
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522 /* Pend a context switch. */
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523 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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526 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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528 /*-----------------------------------------------------------*/
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531 * Setup the systick timer to generate the tick interrupts at the required
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534 static void prvSetupTimerInterrupt( void )
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536 /* Configure SysTick to interrupt at the requested rate. */
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537 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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538 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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540 /*-----------------------------------------------------------*/
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542 /* This is a naked function. */
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543 static void vPortEnableVFP( void )
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547 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
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550 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
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555 /*-----------------------------------------------------------*/
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557 static void prvSetupMPU( void )
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559 extern uint32_t __privileged_functions_end__[];
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560 extern uint32_t __FLASH_segment_start__[];
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561 extern uint32_t __FLASH_segment_end__[];
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562 extern uint32_t __privileged_data_start__[];
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563 extern uint32_t __privileged_data_end__[];
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565 /* Check the expected MPU is present. */
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566 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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568 /* First setup the entire flash for unprivileged read only access. */
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569 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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570 ( portMPU_REGION_VALID ) |
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571 ( portUNPRIVILEGED_FLASH_REGION );
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573 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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574 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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575 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
576 ( portMPU_REGION_ENABLE );
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578 /* Setup the first 16K for privileged only access (even though less
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579 than 10K is actually being used). This is where the kernel code is
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581 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
582 ( portMPU_REGION_VALID ) |
\r
583 ( portPRIVILEGED_FLASH_REGION );
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585 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
586 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
587 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
588 ( portMPU_REGION_ENABLE );
\r
590 /* Setup the privileged data RAM region. This is where the kernel data
\r
592 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
593 ( portMPU_REGION_VALID ) |
\r
594 ( portPRIVILEGED_RAM_REGION );
\r
596 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
597 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
598 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
599 ( portMPU_REGION_ENABLE );
\r
601 /* By default allow everything to access the general peripherals. The
\r
602 system peripherals and registers are protected. */
\r
603 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
604 ( portMPU_REGION_VALID ) |
\r
605 ( portGENERAL_PERIPHERALS_REGION );
\r
607 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
608 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
609 ( portMPU_REGION_ENABLE );
\r
611 /* Enable the memory fault exception. */
\r
612 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
614 /* Enable the MPU with the background region configured. */
\r
615 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
618 /*-----------------------------------------------------------*/
\r
620 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
622 uint32_t ulRegionSize, ulReturnValue = 4;
\r
624 /* 32 is the smallest region size, 31 is the largest valid value for
\r
626 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
628 if( ulActualSizeInBytes <= ulRegionSize )
\r
638 /* Shift the code by one before returning so it can be written directly
\r
639 into the the correct bit position of the attribute register. */
\r
640 return ( ulReturnValue << 1UL );
\r
642 /*-----------------------------------------------------------*/
\r
644 BaseType_t xPortRaisePrivilege( void )
\r
648 " mrs r0, control \n"
\r
649 " tst r0, #1 \n" /* Is the task running privileged? */
\r
651 " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
\r
652 " svcne %0 \n" /* Switch to privileged. */
\r
653 " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
\r
655 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
\r
660 /*-----------------------------------------------------------*/
\r
662 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
664 extern uint32_t __SRAM_segment_start__[];
\r
665 extern uint32_t __SRAM_segment_end__[];
\r
666 extern uint32_t __privileged_data_start__[];
\r
667 extern uint32_t __privileged_data_end__[];
\r
671 if( xRegions == NULL )
\r
673 /* No MPU regions are specified so allow access to all RAM. */
\r
674 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
675 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
676 ( portMPU_REGION_VALID ) |
\r
677 ( portSTACK_REGION );
\r
679 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
680 ( portMPU_REGION_READ_WRITE ) |
\r
681 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
682 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
683 ( portMPU_REGION_ENABLE );
\r
685 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
686 just removed the privileged only parameters. */
\r
687 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
688 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
689 ( portMPU_REGION_VALID ) |
\r
690 ( portSTACK_REGION + 1 );
\r
692 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
693 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
694 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
695 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
696 ( portMPU_REGION_ENABLE );
\r
698 /* Invalidate all other regions. */
\r
699 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
701 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
702 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
707 /* This function is called automatically when the task is created - in
\r
708 which case the stack region parameters will be valid. At all other
\r
709 times the stack parameters will not be valid and it is assumed that the
\r
710 stack region has already been configured. */
\r
711 if( ulStackDepth > 0 )
\r
713 /* Define the region that allows access to the stack. */
\r
714 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
715 ( ( uint32_t ) pxBottomOfStack ) |
\r
716 ( portMPU_REGION_VALID ) |
\r
717 ( portSTACK_REGION ); /* Region number. */
\r
719 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
720 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
721 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
722 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
723 ( portMPU_REGION_ENABLE );
\r
728 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
730 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
732 /* Translate the generic region definition contained in
\r
733 xRegions into the CM3 specific MPU settings that are then
\r
734 stored in xMPUSettings. */
\r
735 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
736 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
737 ( portMPU_REGION_VALID ) |
\r
738 ( portSTACK_REGION + ul ); /* Region number. */
\r
740 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
741 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
742 ( xRegions[ lIndex ].ulParameters ) |
\r
743 ( portMPU_REGION_ENABLE );
\r
747 /* Invalidate the region. */
\r
748 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
749 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
756 /*-----------------------------------------------------------*/
\r
758 #if( configASSERT_DEFINED == 1 )
\r
760 void vPortValidateInterruptPriority( void )
\r
762 uint32_t ulCurrentInterrupt;
\r
763 uint8_t ucCurrentPriority;
\r
765 /* Obtain the number of the currently executing interrupt. */
\r
766 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
768 /* Is the interrupt number a user defined interrupt? */
\r
769 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
771 /* Look up the interrupt's priority. */
\r
772 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
774 /* The following assertion will fail if a service routine (ISR) for
\r
775 an interrupt that has been assigned a priority above
\r
776 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
777 function. ISR safe FreeRTOS API functions must *only* be called
\r
778 from interrupts that have been assigned a priority at or below
\r
779 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
781 Numerically low interrupt priority numbers represent logically high
\r
782 interrupt priorities, therefore the priority of the interrupt must
\r
783 be set to a value equal to or numerically *higher* than
\r
784 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
786 Interrupts that use the FreeRTOS API must not be left at their
\r
787 default priority of zero as that is the highest possible priority,
\r
788 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
789 and therefore also guaranteed to be invalid.
\r
791 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
792 interrupt entry is as fast and simple as possible.
\r
794 The following links provide detailed information:
\r
795 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
796 http://www.freertos.org/FAQHelp.html */
\r
797 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
800 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
801 that define each interrupt's priority to be split between bits that
\r
802 define the interrupt's pre-emption priority bits and bits that define
\r
803 the interrupt's sub-priority. For simplicity all bits must be defined
\r
804 to be pre-emption priority bits. The following assertion will fail if
\r
805 this is not the case (if some bits represent a sub-priority).
\r
807 If the application only uses CMSIS libraries for interrupt
\r
808 configuration then the correct setting can be achieved on all Cortex-M
\r
809 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
810 scheduler. Note however that some vendor specific peripheral libraries
\r
811 assume a non-zero priority group setting, in which cases using a value
\r
812 of zero will result in unpredicable behaviour. */
\r
813 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
816 #endif /* configASSERT_DEFINED */
\r
817 /*-----------------------------------------------------------*/
\r