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Add GCC ARM Cortex-M4F MPU port.
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 18 May 2016 10:41:28 +0000 (10:41 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 18 May 2016 10:41:28 +0000 (10:41 +0000)
Add RVDS ARM Cortex-M4F MPU port.
Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining.
Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2458 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/sections.ld patch | blob | history
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwipopts.h patch | blob | history
FreeRTOS/Source/portable/Common/mpu_wrappers.c patch | blob | history
FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c patch | blob | history
FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c [new file with mode: 0644] patch | blob
FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h [new file with mode: 0644] patch | blob
FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c patch | blob | history
FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c [new file with mode: 0644] patch | blob
FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h [new file with mode: 0644] patch | blob

diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri
deleted file mode 100644 (file)
index 867b36c..0000000
--- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri
+++ /dev/null
@@ -1,2646 +0,0 @@
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diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/sections.ld b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/sections.ld
index c7515cb470941460f93c742f17a44d18ff2acf0a..ac94a5d11bb9a6a35ad62fa29c5fb913fd2216f4 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/sections.ld
+++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/sections.ld
@@ -5,22 +5,6 @@ MEMORY
   RAM (rw)         : ORIGIN = 0x20000000, LENGTH = 0x8000\r
 }\r
 \r
-/* Variables required by FreeRTOS MPU. */\r
-_Privileged_Functions_Region_Size = 16K;\r
-_Privileged_Data_Region_Size = 256;\r
-\r
-__FLASH_segment_start__ = ORIGIN( ROM );\r
-__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( ROM );\r
-\r
-__privileged_functions_start__ = ORIGIN( ROM );\r
-__privileged_functions_end__ = __privileged_functions_start__ + _Privileged_Functions_Region_Size;\r
-\r
-__SRAM_segment_start__ = ORIGIN( RAM );\r
-__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM );\r
-\r
-__privileged_data_start__ = ORIGIN( RAM );\r
-__privileged_data_end__ = ORIGIN( RAM ) + _Privileged_Data_Region_Size;\r
-\r
 /* Variables used by FreeRTOS-MPU. */\r
 _Privileged_Functions_Region_Size = 16K;\r
 _Privileged_Data_Region_Size = 256;\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwipopts.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwipopts.h
index 567026d67ad1769ad4c29d833e54618df16adfa6..cfd4639128194592672fc13b2f9bdd7867c4cb35 100644 (file)
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwipopts.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwipopts.h
@@ -70,7 +70,7 @@ void vLwipAppsReleaseTxBuffer( void );
 #define LWIP_SO_RCVTIMEO                               1
 #define LWIP_SO_RCVBUF                                 1
 
-#define LWIP_DEBUG
+#define NOT_LWIP_DEBUG
 #ifdef LWIP_DEBUG
 
 #define LWIP_DBG_MIN_LEVEL        LWIP_DBG_LEVEL_ALL // LWIP_DBG_LEVEL_SERIOUS
@@ -112,7 +112,7 @@ void vLwipAppsReleaseTxBuffer( void );
    byte alignment -> define MEM_ALIGNMENT to 2. */
 /* MSVC port: intel processors don't need 4-byte alignment,
    but are faster that way! */
-#define MEM_ALIGNMENT                  4
+#define MEM_ALIGNMENT                  64 /* For Eth lite. */
 
 /* MEM_SIZE: the size of the heap memory. If the application will send
 a lot of data that needs to be copied, this should be set high. */
@@ -159,8 +159,8 @@ a lot of data that needs to be copied, this should be set high. */
 /* MEMP_NUM_TCPIP_MSG_*: the number of struct tcpip_msg, which is used
    for sequential API communication and incoming packets. Used in
    src/api/tcpip.c. */
-#define MEMP_NUM_TCPIP_MSG_API   8
-#define MEMP_NUM_TCPIP_MSG_INPKT 8
+#define MEMP_NUM_TCPIP_MSG_API   16
+#define MEMP_NUM_TCPIP_MSG_INPKT 16
 
 #define MEMP_NUM_ARP_QUEUE             10
 
@@ -169,7 +169,7 @@ a lot of data that needs to be copied, this should be set high. */
 #define PBUF_POOL_SIZE                 40
 
 /* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-#define PBUF_POOL_BUFSIZE              512
+#define PBUF_POOL_BUFSIZE              1518 /* Max eth frame size so no chaining. */
 
 /* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
    link level header. */
diff --git a/FreeRTOS/Source/portable/Common/mpu_wrappers.c b/FreeRTOS/Source/portable/Common/mpu_wrappers.c
index 18435cb2f794e932fc1492a9fff6ec550fbea132..06a53802cb4cd71ff9425f70c63bd8fabb772976 100644 (file)
--- a/FreeRTOS/Source/portable/Common/mpu_wrappers.c
+++ b/FreeRTOS/Source/portable/Common/mpu_wrappers.c
@@ -337,7 +337,7 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
 #endif\r
 /*-----------------------------------------------------------*/\r
 \r
-#if ( configUSE_TRACE_FACILITY == 1 )\r
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r
        void MPU_vTaskList( char *pcWriteBuffer )\r
        {\r
        BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
index 9997e5642ce14d04e4461c478f6d3eb48bdd9f13..61268361a8274f6d904333f891d06e5f5bc77c87 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -384,7 +384,17 @@ BaseType_t xPortStartScheduler( void )
        uxCriticalNesting = 0;\r
 \r
        /* Start the first task. */\r
-       __asm volatile( "       svc %0                  \n"\r
+       __asm volatile(\r
+                                       " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
+                                       " ldr r0, [r0]                  \n"\r
+                                       " ldr r0, [r0]                  \n"\r
+                                       " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
+                                       " cpsie i                               \n" /* Globally enable interrupts. */\r
+                                       " cpsie f                               \n"\r
+                                       " dsb                                   \n"\r
+                                       " isb                                   \n"\r
+                                       " svc %0                                \n" /* System call to start first task. */\r
+                                       " nop                                   \n"\r
                                        :: "i" (portSVC_START_SCHEDULER) );\r
 \r
        /* Should not get here! */\r
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
new file mode 100644 (file)
index 0000000..842a9c5
--- /dev/null
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
@@ -0,0 +1,819 @@
+/*\r
+    FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+    All rights reserved\r
+\r
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+    ***************************************************************************\r
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
+    >>!   obliged to provide the source code for proprietary components     !<<\r
+    >>!   outside of the FreeRTOS kernel.                                   !<<\r
+    ***************************************************************************\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
+    link: http://www.freertos.org/a00114.html\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS provides completely free yet professionally developed,    *\r
+     *    robust, strictly quality controlled, supported, and cross          *\r
+     *    platform software that is more than just the market leader, it     *\r
+     *    is the industry's de facto standard.                               *\r
+     *                                                                       *\r
+     *    Help yourself get started quickly while simultaneously helping     *\r
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
+     *    tutorial book, reference manual, or both:                          *\r
+     *    http://www.FreeRTOS.org/Documentation                              *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
+    the FAQ page "My application does not run, what could be wrong?".  Have you\r
+    defined configASSERT()?\r
+\r
+    http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+    embedded software for free we request you assist our global community by\r
+    participating in the support forum.\r
+\r
+    http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+    be as productive as possible as early as possible.  Now you can receive\r
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+    Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
+    licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+\r
+    1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM3 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers.  That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "event_groups.h"\r
+#include "mpu_prototypes.h"\r
+\r
+#ifndef __VFP_FP__\r
+       #error This port can only be used when the project options are configured to enable hardware floating point support.\r
+#endif\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Constants required to access and manipulate the NVIC. */\r
+#define portNVIC_SYSTICK_CTRL_REG                              ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG                              ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSPRI2_REG                                   ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+#define portNVIC_SYSPRI1_REG                                   ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
+#define portNVIC_SYS_CTRL_STATE_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
+#define portNVIC_MEM_FAULT_ENABLE                              ( 1UL << 16UL )\r
+\r
+/* Constants required to access and manipulate the MPU. */\r
+#define portMPU_TYPE_REG                                               ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_REGION_BASE_ADDRESS_REG                        ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
+#define portMPU_REGION_ATTRIBUTE_REG                   ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
+#define portMPU_CTRL_REG                                               ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portEXPECTED_MPU_TYPE_VALUE                            ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portMPU_ENABLE                                                 ( 0x01UL )\r
+#define portMPU_BACKGROUND_ENABLE                              ( 1UL << 2UL )\r
+#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )\r
+#define portMPU_REGION_VALID                                   ( 0x10UL )\r
+#define portMPU_REGION_ENABLE                                  ( 0x01UL )\r
+#define portPERIPHERALS_START_ADDRESS                  0x40000000UL\r
+#define portPERIPHERALS_END_ADDRESS                            0x5FFFFFFFUL\r
+\r
+/* Constants required to access and manipulate the SysTick. */\r
+#define portNVIC_SYSTICK_CLK                                   ( 0x00000004UL )\r
+#define portNVIC_SYSTICK_INT                                   ( 0x00000002UL )\r
+#define portNVIC_SYSTICK_ENABLE                                        ( 0x00000001UL )\r
+#define portNVIC_PENDSV_PRI                                            ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI                                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+#define portNVIC_SVC_PRI                                               ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
+\r
+/* Constants required to manipulate the VFP. */\r
+#define portFPCCR                                                              ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
+#define portASPEN_AND_LSPEN_BITS                               ( 0x3UL << 30UL )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR                                               ( 0x01000000UL )\r
+#define portINITIAL_EXEC_RETURN                                        ( 0xfffffffdUL )\r
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED            ( 0x03 )\r
+#define portINITIAL_CONTROL_IF_PRIVILEGED              ( 0x02 )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER                ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16        ( 0xE000E3F0 )\r
+#define portAIRCR_REG                                          ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE                                    ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE                                    ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS                          ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK                                ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT                                     ( 8UL )\r
+\r
+/* Offsets in the stack to the parameters when inside the SVC handler. */\r
+#define portOFFSET_TO_PC                                               ( 6 )\r
+\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK                         ( ( StackType_t ) 0xfffffffeUL )\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable.  Note this is not saved as part of the task context as context\r
+switches can only occur when uxCriticalNesting is zero. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Configure a number of standard MPU regions that are used by all tasks.\r
+ */\r
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Return the smallest MPU region size that a given number of bytes will fit\r
+ * into.  The region size is returned as the value that should be programmed\r
+ * into the region attribute register for that region.\r
+ */\r
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Checks to see if being called from the context of an unprivileged task, and\r
+ * if so raises the privilege level and returns false - otherwise does nothing\r
+ * other than return true.\r
+ */\r
+BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
+\r
+/*\r
+ * Standard FreeRTOS exception handlers.\r
+ */\r
+void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
+void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Starts the scheduler by restoring the context of the first task to run.\r
+ */\r
+static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
+ * and a C wrapper for simplicity of coding and maintenance.\r
+ */\r
+static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Function to enable the VFP.\r
+ */\r
+ static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
+ \r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+        static uint8_t ucMaxSysCallPriority = 0;\r
+        static uint32_t ulMaxPRIGROUPValue = 0;\r
+        static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
+{\r
+       /* Simulate the stack frame as it would be created by a context switch\r
+       interrupt. */\r
+       pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+       *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = 0;      /* LR */\r
+       pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
+       *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
+       \r
+       /* A save method is being used that requires each task to maintain its\r
+       own exec return value. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+       \r
+       pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+       if( xRunPrivileged == pdTRUE )\r
+       {\r
+               *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
+       }\r
+       else\r
+       {\r
+               *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
+       }\r
+\r
+       return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler( void )\r
+{\r
+       /* Assumes psp was in use. */\r
+       __asm volatile\r
+       (\r
+               #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
+                       "       tst lr, #4                                              \n"\r
+                       "       ite eq                                                  \n"\r
+                       "       mrseq r0, msp                                   \n"\r
+                       "       mrsne r0, psp                                   \n"\r
+               #else\r
+                       "       mrs r0, psp                                             \n"\r
+               #endif\r
+                       "       b %0                                                    \n"\r
+                       ::"i"(prvSVCHandler):"r0"\r
+       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSVCHandler(     uint32_t *pulParam )\r
+{\r
+uint8_t ucSVCNumber;\r
+\r
+       /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
+       xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
+       ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
+       switch( ucSVCNumber )\r
+       {\r
+               case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
+                                                                                       prvRestoreContextOfFirstTask();\r
+                                                                                       break;\r
+\r
+               case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+                                                                                       /* Barriers are normally not required\r
+                                                                                       but do ensure the code is completely\r
+                                                                                       within the specified behaviour for the\r
+                                                                                       architecture. */\r
+                                                                                       __asm volatile( "dsb" );\r
+                                                                                       __asm volatile( "isb" );\r
+\r
+                                                                                       break;\r
+\r
+               case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
+                                                                                       (\r
+                                                                                               "       mrs r1, control         \n" /* Obtain current control value. */\r
+                                                                                               "       bic r1, #1                      \n" /* Set privilege bit. */\r
+                                                                                               "       msr control, r1         \n" /* Write back new control value. */\r
+                                                                                               :::"r1"\r
+                                                                                       );\r
+                                                                                       break;\r
+\r
+               default                                                 :       /* Unknown SVC call. */\r
+                                                                                       break;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRestoreContextOfFirstTask( void )\r
+{\r
+       __asm volatile\r
+       (\r
+               "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
+               "       ldr r0, [r0]                                    \n"\r
+               "       ldr r0, [r0]                                    \n"\r
+               "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
+               "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
+               "       ldr r1, [r3]                                    \n"\r
+               "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
+               "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
+               "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
+               "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
+               "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
+               "       ldmia r0!, {r3-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry. */\r
+               "       msr control, r3                                 \n"\r
+               "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
+               "       mov r0, #0                                              \n"\r
+               "       msr     basepri, r0                                     \n"\r
+               "       bx r14                                                  \n"\r
+               "                                                                       \n"\r
+               "       .align 4                                                \n"\r
+               "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+       /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
+       http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+       configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
+\r
+       #if( configASSERT_DEFINED == 1 )\r
+       {\r
+               volatile uint32_t ulOriginalPriority;\r
+               volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+               volatile uint8_t ucMaxPriorityValue;\r
+\r
+               /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+               functions can be called.  ISR safe functions are those that end in\r
+               "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
+               ensure interrupt entry is as fast and simple as possible.\r
+\r
+               Save the interrupt priority value that is about to be clobbered. */\r
+               ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+               /* Determine the number of priority bits available.  First write to all\r
+               possible bits. */\r
+               *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+               /* Read the value back to see how many bits stuck. */\r
+               ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+               /* Use the same mask on the maximum system call priority. */\r
+               ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+               /* Calculate the maximum acceptable priority group value for the number\r
+               of bits read back. */\r
+               ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+               while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+               {\r
+                       ulMaxPRIGROUPValue--;\r
+                       ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+               }\r
+\r
+               /* Shift the priority group value back to its position within the AIRCR\r
+               register. */\r
+               ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+               ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+               /* Restore the clobbered interrupt priority register to its original\r
+               value. */\r
+               *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+       }\r
+       #endif /* conifgASSERT_DEFINED */\r
+\r
+       /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
+       handler higher priority so it can be used to exit a critical section (where\r
+       lower priorities are masked). */\r
+       portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+       portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
+\r
+       /* Configure the regions in the MPU that are common to all tasks. */\r
+       prvSetupMPU();\r
+\r
+       /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
+       here already. */\r
+       prvSetupTimerInterrupt();\r
+\r
+       /* Initialise the critical nesting count ready for the first task. */\r
+       uxCriticalNesting = 0;\r
+\r
+       /* Ensure the VFP is enabled - it should be anyway. */\r
+       vPortEnableVFP();\r
+\r
+       /* Lazy save always. */\r
+       *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
+\r
+       /* Start the first task. */\r
+       __asm volatile(\r
+                                       " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
+                                       " ldr r0, [r0]                  \n"\r
+                                       " ldr r0, [r0]                  \n"\r
+                                       " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
+                                       " cpsie i                               \n" /* Globally enable interrupts. */\r
+                                       " cpsie f                               \n"\r
+                                       " dsb                                   \n"\r
+                                       " isb                                   \n"\r
+                                       " svc %0                                \n" /* System call to start first task. */\r
+                                       " nop                                   \n"\r
+                                       :: "i" (portSVC_START_SCHEDULER) );\r
+\r
+       /* Should not get here! */\r
+       return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+       /* Not implemented in ports where there is nothing to return to.\r
+       Artificially force an assert. */\r
+       configASSERT( uxCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
+\r
+       portDISABLE_INTERRUPTS();\r
+       uxCriticalNesting++;\r
+\r
+       vPortResetPrivilege( xRunningPrivileged );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
+\r
+       configASSERT( uxCriticalNesting );\r
+       uxCriticalNesting--;\r
+       if( uxCriticalNesting == 0 )\r
+       {\r
+               portENABLE_INTERRUPTS();\r
+       }\r
+       vPortResetPrivilege( xRunningPrivileged );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortPendSVHandler( void )\r
+{\r
+       /* This is a naked function. */\r
+\r
+       __asm volatile\r
+       (\r
+               "       mrs r0, psp                                                     \n"\r
+               "                                                                               \n"\r
+               "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
+               "       ldr     r2, [r3]                                                \n"\r
+               "                                                                               \n"\r
+               "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
+               "       it eq                                                           \n"\r
+               "       vstmdbeq r0!, {s16-s31}                         \n"\r
+               "                                                                               \n"\r
+               "       mrs r1, control                                         \n"\r
+               "       stmdb r0!, {r1, r4-r11, r14}            \n" /* Save the remaining registers. */\r
+               "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
+               "                                                                               \n"\r
+               "       stmdb sp!, {r3}                                         \n"\r
+               "       mov r0, %0                                                      \n"\r
+               "       msr basepri, r0                                         \n"\r
+               "       dsb                                                                     \n"\r
+               "       isb                                                                     \n"\r
+               "       bl vTaskSwitchContext                           \n"\r
+               "       mov r0, #0                                                      \n"\r
+               "       msr basepri, r0                                         \n"\r
+               "       ldmia sp!, {r3}                                         \n"\r
+               "                                                                               \n"     /* Restore the context. */\r
+               "       ldr r1, [r3]                                            \n"\r
+               "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
+               "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
+               "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
+               "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
+               "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
+               "       ldmia r0!, {r3-r11, r14}                        \n" /* Pop the registers that are not automatically saved on exception entry. */\r
+               "       msr control, r3                                         \n"\r
+               "                                                                               \n"\r
+               "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
+               "       it eq                                                           \n"\r
+               "       vldmiaeq r0!, {s16-s31}                         \n"\r
+               "                                                                               \n"\r
+               "       msr psp, r0                                                     \n"\r
+               "       bx r14                                                          \n"\r
+               "                                                                               \n"\r
+               "       .align 4                                                        \n"\r
+               "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
+               ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
+       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+uint32_t ulDummy;\r
+\r
+       ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
+       {\r
+               /* Increment the RTOS tick. */\r
+               if( xTaskIncrementTick() != pdFALSE )\r
+               {\r
+                       /* Pend a context switch. */\r
+                       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+               }\r
+       }\r
+       portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+       /* Configure SysTick to interrupt at the requested rate. */\r
+       portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+       portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is a naked function. */\r
+static void vPortEnableVFP( void )\r
+{\r
+       __asm volatile\r
+       (\r
+               "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
+               "       ldr r1, [r0]                            \n"\r
+               "                                                               \n"\r
+               "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
+               "       str r1, [r0]                            \n"\r
+               "       bx r14                                          "\r
+       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupMPU( void )\r
+{\r
+extern uint32_t __privileged_functions_end__[];\r
+extern uint32_t __FLASH_segment_start__[];\r
+extern uint32_t __FLASH_segment_end__[];\r
+extern uint32_t __privileged_data_start__[];\r
+extern uint32_t __privileged_data_end__[];\r
+\r
+       /* Check the expected MPU is present. */\r
+       if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+       {\r
+               /* First setup the entire flash for unprivileged read only access. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portUNPRIVILEGED_FLASH_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
+                                                                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                                                               ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Setup the first 16K for privileged only access (even though less\r
+               than 10K is actually being used).  This is where the kernel code is\r
+               placed. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portPRIVILEGED_FLASH_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
+                                                                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                                                               ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Setup the privileged data RAM region.  This is where the kernel data\r
+               is placed. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portPRIVILEGED_RAM_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+                                                                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                                                               prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* By default allow everything to access the general peripherals.  The\r
+               system peripherals and registers are protected. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portGENERAL_PERIPHERALS_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
+                                                                               ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Enable the memory fault exception. */\r
+               portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
+\r
+               /* Enable the MPU with the background region configured. */\r
+               portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
+{\r
+uint32_t ulRegionSize, ulReturnValue = 4;\r
+\r
+       /* 32 is the smallest region size, 31 is the largest valid value for\r
+       ulReturnValue. */\r
+       for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
+       {\r
+               if( ulActualSizeInBytes <= ulRegionSize )\r
+               {\r
+                       break;\r
+               }\r
+               else\r
+               {\r
+                       ulReturnValue++;\r
+               }\r
+       }\r
+\r
+       /* Shift the code by one before returning so it can be written directly\r
+       into the the correct bit position of the attribute register. */\r
+       return ( ulReturnValue << 1UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortRaisePrivilege( void )\r
+{\r
+       __asm volatile\r
+       (\r
+               "       mrs r0, control                                         \n"\r
+               "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
+               "       itte ne                                                         \n"\r
+               "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
+               "       svcne %0                                                        \n" /* Switch to privileged. */\r
+               "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
+               "       bx lr                                                           \n"\r
+               :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
+       );\r
+\r
+       return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+{\r
+extern uint32_t __SRAM_segment_start__[];\r
+extern uint32_t __SRAM_segment_end__[];\r
+extern uint32_t __privileged_data_start__[];\r
+extern uint32_t __privileged_data_end__[];\r
+int32_t lIndex;\r
+uint32_t ul;\r
+\r
+       if( xRegions == NULL )\r
+       {\r
+               /* No MPU regions are specified so allow access to all RAM. */\r
+               xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
+                               ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
+                               ( portMPU_REGION_VALID ) |\r
+                               ( portSTACK_REGION );\r
+\r
+               xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
+                               ( portMPU_REGION_READ_WRITE ) |\r
+                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                               ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
+                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
+               just removed the privileged only parameters. */\r
+               xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
+                               ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
+                               ( portMPU_REGION_VALID ) |\r
+                               ( portSTACK_REGION + 1 );\r
+\r
+               xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                               prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
+                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Invalidate all other regions. */\r
+               for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
+               {\r
+                       xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
+                       xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
+               }\r
+       }\r
+       else\r
+       {\r
+               /* This function is called automatically when the task is created - in\r
+               which case the stack region parameters will be valid.  At all other\r
+               times the stack parameters will not be valid and it is assumed that the\r
+               stack region has already been configured. */\r
+               if( ulStackDepth > 0 )\r
+               {\r
+                       /* Define the region that allows access to the stack. */\r
+                       xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
+                                       ( ( uint32_t ) pxBottomOfStack ) |\r
+                                       ( portMPU_REGION_VALID ) |\r
+                                       ( portSTACK_REGION ); /* Region number. */\r
+\r
+                       xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
+                                       ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
+                                       ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
+                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                       ( portMPU_REGION_ENABLE );\r
+               }\r
+\r
+               lIndex = 0;\r
+\r
+               for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
+               {\r
+                       if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
+                       {\r
+                               /* Translate the generic region definition contained in\r
+                               xRegions into the CM3 specific MPU settings that are then\r
+                               stored in xMPUSettings. */\r
+                               xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
+                                               ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
+                                               ( portMPU_REGION_VALID ) |\r
+                                               ( portSTACK_REGION + ul ); /* Region number. */\r
+\r
+                               xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
+                                               ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
+                                               ( xRegions[ lIndex ].ulParameters ) |\r
+                                               ( portMPU_REGION_ENABLE );\r
+                       }\r
+                       else\r
+                       {\r
+                               /* Invalidate the region. */\r
+                               xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
+                               xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
+                       }\r
+\r
+                       lIndex++;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+       void vPortValidateInterruptPriority( void )\r
+       {\r
+       uint32_t ulCurrentInterrupt;\r
+       uint8_t ucCurrentPriority;\r
+\r
+               /* Obtain the number of the currently executing interrupt. */\r
+               __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+\r
+               /* Is the interrupt number a user defined interrupt? */\r
+               if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+               {\r
+                       /* Look up the interrupt's priority. */\r
+                       ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+                       /* The following assertion will fail if a service routine (ISR) for\r
+                       an interrupt that has been assigned a priority above\r
+                       configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+                       function.  ISR safe FreeRTOS API functions must *only* be called\r
+                       from interrupts that have been assigned a priority at or below\r
+                       configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+                       Numerically low interrupt priority numbers represent logically high\r
+                       interrupt priorities, therefore the priority of the interrupt must\r
+                       be set to a value equal to or numerically *higher* than\r
+                       configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+                       Interrupts that use the FreeRTOS API must not be left at their\r
+                       default priority of     zero as that is the highest possible priority,\r
+                       which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+                       and     therefore also guaranteed to be invalid.\r
+\r
+                       FreeRTOS maintains separate thread and ISR API functions to ensure\r
+                       interrupt entry is as fast and simple as possible.\r
+\r
+                       The following links provide detailed information:\r
+                       http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+                       http://www.freertos.org/FAQHelp.html */\r
+                       configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+               }\r
+\r
+               /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
+               that define each interrupt's priority to be split between bits that\r
+               define the interrupt's pre-emption priority bits and bits that define\r
+               the interrupt's sub-priority.  For simplicity all bits must be defined\r
+               to be pre-emption priority bits.  The following assertion will fail if\r
+               this is not the case (if some bits represent a sub-priority).\r
+\r
+               If the application only uses CMSIS libraries for interrupt\r
+               configuration then the correct setting can be achieved on all Cortex-M\r
+               devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+               scheduler.  Note however that some vendor specific peripheral libraries\r
+               assume a non-zero priority group setting, in which cases using a value\r
+               of zero will result in unpredicable behaviour. */\r
+               configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
+       }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
new file mode 100644 (file)
index 0000000..3ffd383
--- /dev/null
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -0,0 +1,332 @@
+/*\r
+    FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+    All rights reserved\r
+\r
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+    ***************************************************************************\r
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
+    >>!   obliged to provide the source code for proprietary components     !<<\r
+    >>!   outside of the FreeRTOS kernel.                                   !<<\r
+    ***************************************************************************\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
+    link: http://www.freertos.org/a00114.html\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS provides completely free yet professionally developed,    *\r
+     *    robust, strictly quality controlled, supported, and cross          *\r
+     *    platform software that is more than just the market leader, it     *\r
+     *    is the industry's de facto standard.                               *\r
+     *                                                                       *\r
+     *    Help yourself get started quickly while simultaneously helping     *\r
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
+     *    tutorial book, reference manual, or both:                          *\r
+     *    http://www.FreeRTOS.org/Documentation                              *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
+    the FAQ page "My application does not run, what could be wrong?".  Have you\r
+    defined configASSERT()?\r
+\r
+    http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+    embedded software for free we request you assist our global community by\r
+    participating in the support forum.\r
+\r
+    http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+    be as productive as possible as early as possible.  Now you can receive\r
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+    Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
+    licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+\r
+    1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR               char\r
+#define portFLOAT              float\r
+#define portDOUBLE             double\r
+#define portLONG               long\r
+#define portSHORT              short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE  long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+       typedef uint16_t TickType_t;\r
+       #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+       typedef uint32_t TickType_t;\r
+       #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+       /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+       not need to be guarded with a critical section. */\r
+       #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* MPU specific constants. */\r
+#define portUSING_MPU_WRAPPERS         1\r
+#define portPRIVILEGE_BIT                      ( 0x80000000UL )\r
+\r
+#define portMPU_REGION_READ_WRITE                              ( 0x03UL << 24UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY            ( 0x05UL << 24UL )\r
+#define portMPU_REGION_READ_ONLY                               ( 0x06UL << 24UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE   ( 0x01UL << 24UL )\r
+#define portMPU_REGION_CACHEABLE_BUFFERABLE            ( 0x07UL << 16UL )\r
+#define portMPU_REGION_EXECUTE_NEVER                   ( 0x01UL << 28UL )\r
+\r
+#define portUNPRIVILEGED_FLASH_REGION          ( 0UL )\r
+#define portPRIVILEGED_FLASH_REGION                    ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION                      ( 2UL )\r
+#define portGENERAL_PERIPHERALS_REGION         ( 3UL )\r
+#define portSTACK_REGION                                       ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION      ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION           ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS           ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS                          ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )\r
+\r
+typedef struct MPU_REGION_REGISTERS\r
+{\r
+       uint32_t ulRegionBaseAddress;\r
+       uint32_t ulRegionAttribute;\r
+} xMPU_REGION_REGISTERS;\r
+\r
+/* Plus 1 to create space for the stack region. */\r
+typedef struct MPU_SETTINGS\r
+{\r
+       xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];\r
+} xMPU_SETTINGS;\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH                       ( -1 )\r
+#define portTICK_PERIOD_MS                     ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT                     8\r
+/*-----------------------------------------------------------*/\r
+\r
+/* SVC numbers for various services. */\r
+#define portSVC_START_SCHEDULER                                0\r
+#define portSVC_YIELD                                          1\r
+#define portSVC_RAISE_PRIVILEGE                                2\r
+\r
+/* Scheduler utilities. */\r
+\r
+#define portYIELD()                            __asm volatile ( "      SVC     %0      \n" :: "i" (portSVC_YIELD) )\r
+#define portYIELD_WITHIN_API()                                                                                                         \\r
+{                                                                                                                                                              \\r
+       /* Set a PendSV to request a context switch. */                                                         \\r
+       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;                                                         \\r
+                                                                                                                                                               \\r
+       /* Barriers are normally not required but do ensure the code is completely      \\r
+       within the specified behaviour for the architecture. */                                         \\r
+       __asm volatile( "dsb" );                                                                                                        \\r
+       __asm volatile( "isb" );                                                                                                        \\r
+}\r
+\r
+#define portNVIC_INT_CTRL_REG          ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT         ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+#define portSET_INTERRUPT_MASK_FROM_ISR()              ulPortRaiseBASEPRI()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vPortSetBASEPRI(x)\r
+#define portDISABLE_INTERRUPTS()                               vPortRaiseBASEPRI()\r
+#define portENABLE_INTERRUPTS()                                        vPortSetBASEPRI(0)\r
+#define portENTER_CRITICAL()                                   vPortEnterCritical()\r
+#define portEXIT_CRITICAL()                                            vPortExitCritical()\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are\r
+not necessary for to use this port.  They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+       #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+       /* Generic helper function. */\r
+       __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\r
+       {\r
+       uint8_t ucReturn;\r
+\r
+               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+               return ucReturn;\r
+       }\r
+\r
+       /* Check the configuration. */\r
+       #if( configMAX_PRIORITIES > 32 )\r
+               #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+       #endif\r
+\r
+       /* Store/clear the ready priorities in a bit map. */\r
+       #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+       #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+       /*-----------------------------------------------------------*/\r
+\r
+       #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+       void vPortValidateInterruptPriority( void );\r
+       #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()      vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/* portNOP() is not required by this port. */\r
+#define portNOP()\r
+\r
+#define portINLINE     __inline\r
+\r
+#ifndef portFORCE_INLINE\r
+       #define portFORCE_INLINE inline __attribute__(( always_inline))\r
+#endif\r
+\r
+/* Set the privilege level to user mode if xRunningPrivileged is false. */\r
+portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )\r
+{\r
+       if( xRunningPrivileged != pdTRUE ) \r
+       {\r
+               __asm volatile ( " mrs r0, control      \n" \\r
+                                                " orr r0, #1           \n" \\r
+                                                " msr control, r0      \n"     \\r
+                                                :::"r0" );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+       /* Obtain the number of the currently executing interrupt. */\r
+       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+\r
+       if( ulCurrentInterrupt == 0 )\r
+       {\r
+               xReturn = pdFALSE;\r
+       }\r
+       else\r
+       {\r
+               xReturn = pdTRUE;\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulNewBASEPRI;\r
+\r
+       __asm volatile\r
+       (\r
+               "       mov %0, %1                                                                                              \n"     \\r
+               "       msr basepri, %0                                                                                 \n" \\r
+               "       isb                                                                                                             \n" \\r
+               "       dsb                                                                                                             \n" \\r
+               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+       );\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\r
+\r
+       __asm volatile\r
+       (\r
+               "       mrs %0, basepri                                                                                 \n" \\r
+               "       mov %1, %2                                                                                              \n"     \\r
+               "       msr basepri, %1                                                                                 \n" \\r
+               "       isb                                                                                                             \n" \\r
+               "       dsb                                                                                                             \n" \\r
+               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+       );\r
+\r
+       /* This return will not be reached but is necessary to prevent compiler\r
+       warnings. */\r
+       return ulOriginalBASEPRI;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\r
+{\r
+       __asm volatile\r
+       (\r
+               "       msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
index 6c73906293e481bd0ad847809274e511dcf298b1..fbdaafe8d47e78304a517da889282565f8e83b30 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
+++ b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
@@ -99,6 +99,7 @@ FSR register is saved as part of the task context.  portINITIAL_FSR is the value
 given to the FSR register when the initial context is set up for a task being\r
 created. */\r
 #define portINITIAL_FSR                                ( 0U )\r
+\r
 /*-----------------------------------------------------------*/\r
 \r
 /*\r
@@ -150,6 +151,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 extern void *_SDA2_BASE_, *_SDA_BASE_;\r
 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;\r
 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;\r
+extern void _start1( void );\r
 \r
        /* Place a few bytes of known values on the bottom of the stack.\r
        This is essential for the Microblaze port and these lines must\r
@@ -204,7 +206,7 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
                pxTopOfStack--;\r
                *pxTopOfStack = ( StackType_t ) 0x07;   /* R7 - other parameters and temporaries. */\r
                pxTopOfStack--;\r
-               *pxTopOfStack = ( StackType_t ) 0x08;   /* R8 - other parameters and temporaries. */\r
+               *pxTopOfStack = ( StackType_t ) NULL;   /* R8 - other parameters and temporaries. */\r
                pxTopOfStack--;\r
                *pxTopOfStack = ( StackType_t ) 0x09;   /* R9 - other parameters and temporaries. */\r
                pxTopOfStack--;\r
@@ -222,7 +224,7 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
        pxTopOfStack--;\r
        *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */\r
        pxTopOfStack--;\r
-       *pxTopOfStack = ( StackType_t ) NULL;   /* R15 - return address for subroutine. */\r
+       *pxTopOfStack = ( StackType_t ) _start1;        /* R15 - return address for subroutine. */\r
 \r
        #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING\r
                pxTopOfStack--;\r
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
new file mode 100644 (file)
index 0000000..599c589
--- /dev/null
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
@@ -0,0 +1,845 @@
+/*\r
+    FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+    All rights reserved\r
+\r
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+    ***************************************************************************\r
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
+    >>!   obliged to provide the source code for proprietary components     !<<\r
+    >>!   outside of the FreeRTOS kernel.                                   !<<\r
+    ***************************************************************************\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
+    link: http://www.freertos.org/a00114.html\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS provides completely free yet professionally developed,    *\r
+     *    robust, strictly quality controlled, supported, and cross          *\r
+     *    platform software that is more than just the market leader, it     *\r
+     *    is the industry's de facto standard.                               *\r
+     *                                                                       *\r
+     *    Help yourself get started quickly while simultaneously helping     *\r
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
+     *    tutorial book, reference manual, or both:                          *\r
+     *    http://www.FreeRTOS.org/Documentation                              *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
+    the FAQ page "My application does not run, what could be wrong?".  Have you\r
+    defined configASSERT()?\r
+\r
+    http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+    embedded software for free we request you assist our global community by\r
+    participating in the support forum.\r
+\r
+    http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+    be as productive as possible as early as possible.  Now you can receive\r
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+    Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
+    licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+\r
+    1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM3 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers.  That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "event_groups.h"\r
+#include "mpu_prototypes.h"\r
+\r
+#ifndef __TARGET_FPU_VFP\r
+       #error This port can only be used when the project options are configured to enable hardware floating point support.\r
+#endif\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Constants required to access and manipulate the NVIC. */\r
+#define portNVIC_SYSTICK_CTRL_REG                              ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG                              ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSPRI2_REG                                   ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+#define portNVIC_SYSPRI1_REG                                   ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
+#define portNVIC_SYS_CTRL_STATE_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
+#define portNVIC_MEM_FAULT_ENABLE                              ( 1UL << 16UL )\r
+\r
+/* Constants required to access and manipulate the MPU. */\r
+#define portMPU_TYPE_REG                                               ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_REGION_BASE_ADDRESS_REG                        ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
+#define portMPU_REGION_ATTRIBUTE_REG                   ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
+#define portMPU_CTRL_REG                                               ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portEXPECTED_MPU_TYPE_VALUE                            ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portMPU_ENABLE                                                 ( 0x01UL )\r
+#define portMPU_BACKGROUND_ENABLE                              ( 1UL << 2UL )\r
+#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )\r
+#define portMPU_REGION_VALID                                   ( 0x10UL )\r
+#define portMPU_REGION_ENABLE                                  ( 0x01UL )\r
+#define portPERIPHERALS_START_ADDRESS                  0x40000000UL\r
+#define portPERIPHERALS_END_ADDRESS                            0x5FFFFFFFUL\r
+\r
+/* Constants required to access and manipulate the SysTick. */\r
+#define portNVIC_SYSTICK_CLK                                   ( 0x00000004UL )\r
+#define portNVIC_SYSTICK_INT                                   ( 0x00000002UL )\r
+#define portNVIC_SYSTICK_ENABLE                                        ( 0x00000001UL )\r
+#define portNVIC_PENDSV_PRI                                            ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI                                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+#define portNVIC_SVC_PRI                                               ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
+\r
+/* Constants required to manipulate the VFP. */\r
+#define portFPCCR                                                              ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
+#define portASPEN_AND_LSPEN_BITS                               ( 0x3UL << 30UL )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR                                               ( 0x01000000UL )\r
+#define portINITIAL_EXEC_RETURN                                        ( 0xfffffffdUL )\r
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED            ( 0x03 )\r
+#define portINITIAL_CONTROL_IF_PRIVILEGED              ( 0x02 )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER                ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16        ( 0xE000E3F0 )\r
+#define portAIRCR_REG                                          ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE                                    ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE                                    ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS                          ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK                                ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT                                     ( 8UL )\r
+\r
+/* Offsets in the stack to the parameters when inside the SVC handler. */\r
+#define portOFFSET_TO_PC                                               ( 6 )\r
+\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK                         ( ( StackType_t ) 0xfffffffeUL )\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable.  Note this is not saved as part of the task context as context\r
+switches can only occur when uxCriticalNesting is zero. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Configure a number of standard MPU regions that are used by all tasks.\r
+ */\r
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Return the smallest MPU region size that a given number of bytes will fit\r
+ * into.  The region size is returned as the value that should be programmed\r
+ * into the region attribute register for that region.\r
+ */\r
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Checks to see if being called from the context of an unprivileged task, and\r
+ * if so raises the privilege level and returns false - otherwise does nothing\r
+ * other than return true.\r
+ */\r
+BaseType_t xPortRaisePrivilege( void );\r
+\r
+/*\r
+ * Standard FreeRTOS exception handlers.\r
+ */\r
+void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;\r
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;\r
+void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Starts the scheduler by restoring the context of the first task to run.\r
+ */\r
+static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
+ * and a C wrapper for simplicity of coding and maintenance.\r
+ */\r
+void prvSVCHandler( uint32_t *pulRegisters ) __attribute__((used)) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Function to enable the VFP.\r
+ */\r
+static void vPortEnableVFP( void );\r
+\r
+/*\r
+ * Utility function.\r
+ */\r
+static uint32_t prvPortGetIPSR( void );\r
+       \r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+        static uint8_t ucMaxSysCallPriority = 0;\r
+        static uint32_t ulMaxPRIGROUPValue = 0;\r
+        static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
+{\r
+       /* Simulate the stack frame as it would be created by a context switch\r
+       interrupt. */\r
+       pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+       *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = 0;      /* LR */\r
+       pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
+       *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
+\r
+       /* A save method is being used that requires each task to maintain its\r
+       own exec return value. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+\r
+       pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+       if( xRunPrivileged == pdTRUE )\r
+       {\r
+               *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
+       }\r
+       else\r
+       {\r
+               *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
+       }\r
+\r
+       return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSVCHandler( uint32_t *pulParam )\r
+{\r
+uint8_t ucSVCNumber;\r
+uint32_t ulReg;\r
+\r
+       /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
+       xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
+       ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
+       switch( ucSVCNumber )\r
+       {\r
+               case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
+                                                                                       prvRestoreContextOfFirstTask();\r
+                                                                                       break;\r
+\r
+               case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+                                                                                       /* Barriers are normally not required\r
+                                                                                       but do ensure the code is completely\r
+                                                                                       within the specified behaviour for the\r
+                                                                                       architecture. */\r
+                                                                                       __asm volatile( "dsb" );\r
+                                                                                       __asm volatile( "isb" );\r
+\r
+                                                                                       break;\r
+\r
+               case portSVC_RAISE_PRIVILEGE    :       __asm\r
+                                                                                       {\r
+                                                                                               mrs ulReg, control      /* Obtain current control value. */\r
+                                                                                               bic ulReg, #1           /* Set privilege bit. */\r
+                                                                                               msr control, ulReg      /* Write back new control value. */\r
+                                                                                       }\r
+                                                                                       break;\r
+\r
+               default                                                 :       /* Unknown SVC call. */\r
+                                                                                       break;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vPortSVCHandler( void )\r
+{\r
+       extern prvSVCHandler\r
+               \r
+       PRESERVE8\r
+\r
+       /* Assumes psp was in use. */\r
+       #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
+               tst lr, #4\r
+               ite eq\r
+               mrseq r0, msp\r
+               mrsne r0, psp\r
+       #else\r
+               mrs r0, psp\r
+       #endif\r
+               b prvSVCHandler\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvRestoreContextOfFirstTask( void )\r
+{\r
+       PRESERVE8\r
+\r
+       ldr r0, =0xE000ED08                             /* Use the NVIC offset register to locate the stack. */\r
+       ldr r0, [r0]\r
+       ldr r0, [r0]\r
+       msr msp, r0                                             /* Set the msp back to the start of the stack. */\r
+       ldr     r3, =pxCurrentTCB                       /* Restore the context. */\r
+       ldr r1, [r3]\r
+       ldr r0, [r1]                                    /* The first item in the TCB is the task top of stack. */\r
+       add r1, r1, #4                                  /* Move onto the second item in the TCB... */\r
+       ldr r2, =0xe000ed9c                             /* Region Base Address register. */\r
+       ldmia r1!, {r4-r11}                             /* Read 4 sets of MPU registers. */\r
+       stmia r2!, {r4-r11}                             /* Write 4 sets of MPU registers. */\r
+       ldmia r0!, {r3-r11, r14}        /* Pop the registers that are not automatically saved on exception entry. */\r
+       msr control, r3\r
+       msr psp, r0                                             /* Restore the task stack pointer. */\r
+       mov r0, #0\r
+       msr     basepri, r0\r
+       bx r14\r
+       nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+       /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
+       http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+       configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
+\r
+       #if( configASSERT_DEFINED == 1 )\r
+       {\r
+               volatile uint32_t ulOriginalPriority;\r
+               volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+               volatile uint8_t ucMaxPriorityValue;\r
+\r
+               /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+               functions can be called.  ISR safe functions are those that end in\r
+               "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
+               ensure interrupt entry is as fast and simple as possible.\r
+\r
+               Save the interrupt priority value that is about to be clobbered. */\r
+               ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+               /* Determine the number of priority bits available.  First write to all\r
+               possible bits. */\r
+               *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+               /* Read the value back to see how many bits stuck. */\r
+               ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+               /* Use the same mask on the maximum system call priority. */\r
+               ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+               /* Calculate the maximum acceptable priority group value for the number\r
+               of bits read back. */\r
+               ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+               while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+               {\r
+                       ulMaxPRIGROUPValue--;\r
+                       ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+               }\r
+\r
+               /* Shift the priority group value back to its position within the AIRCR\r
+               register. */\r
+               ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+               ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+               /* Restore the clobbered interrupt priority register to its original\r
+               value. */\r
+               *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+       }\r
+       #endif /* conifgASSERT_DEFINED */\r
+\r
+       /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
+       handler higher priority so it can be used to exit a critical section (where\r
+       lower priorities are masked). */\r
+       portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+       portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
+\r
+       /* Configure the regions in the MPU that are common to all tasks. */\r
+       prvSetupMPU();\r
+\r
+       /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
+       here already. */\r
+       prvSetupTimerInterrupt();\r
+\r
+       /* Initialise the critical nesting count ready for the first task. */\r
+       uxCriticalNesting = 0;\r
+\r
+       /* Ensure the VFP is enabled - it should be anyway. */\r
+       vPortEnableVFP();\r
+\r
+       /* Lazy save always. */\r
+       *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
+\r
+       /* Start the first task. */\r
+       prvStartFirstTask();\r
+\r
+       /* Should not get here! */\r
+       return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvStartFirstTask( void )\r
+{\r
+       PRESERVE8\r
+       \r
+       ldr r0, =0xE000ED08     /* Use the NVIC offset register to locate the stack. */\r
+       ldr r0, [r0]\r
+       ldr r0, [r0]\r
+       msr msp, r0                     /* Set the msp back to the start of the stack. */\r
+       cpsie i                         /* Globally enable interrupts. */\r
+       cpsie f\r
+       dsb\r
+       isb\r
+       svc portSVC_START_SCHEDULER     /* System call to start first task. */\r
+       nop\r
+       nop\r
+}\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+       /* Not implemented in ports where there is nothing to return to.\r
+       Artificially force an assert. */\r
+       configASSERT( uxCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
+\r
+       portDISABLE_INTERRUPTS();\r
+       uxCriticalNesting++;\r
+\r
+       vPortResetPrivilege( xRunningPrivileged );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
+\r
+       configASSERT( uxCriticalNesting );\r
+       uxCriticalNesting--;\r
+       if( uxCriticalNesting == 0 )\r
+       {\r
+               portENABLE_INTERRUPTS();\r
+       }\r
+       vPortResetPrivilege( xRunningPrivileged );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void xPortPendSVHandler( void )\r
+{\r
+       extern uxCriticalNesting;\r
+       extern pxCurrentTCB;\r
+       extern vTaskSwitchContext;\r
+\r
+       PRESERVE8\r
+\r
+       mrs r0, psp\r
+\r
+       ldr     r3, =pxCurrentTCB                       /* Get the location of the current TCB. */\r
+       ldr     r2, [r3]\r
+\r
+       tst r14, #0x10                                  /* Is the task using the FPU context?  If so, push high vfp registers. */\r
+       it eq\r
+       vstmdbeq r0!, {s16-s31}\r
+\r
+       mrs r1, control\r
+       stmdb r0!, {r1, r4-r11, r14}    /* Save the remaining registers. */\r
+       str r0, [r2]                                    /* Save the new top of stack into the first member of the TCB. */\r
+\r
+       stmdb sp!, {r3}\r
+       mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+       msr basepri, r0\r
+       dsb\r
+       isb\r
+       bl vTaskSwitchContext\r
+       mov r0, #0\r
+       msr basepri, r0\r
+       ldmia sp!, {r3}\r
+                                                                       /* Restore the context. */\r
+       ldr r1, [r3]\r
+       ldr r0, [r1]                                    /* The first item in the TCB is the task top of stack. */\r
+       add r1, r1, #4                                  /* Move onto the second item in the TCB... */\r
+       ldr r2, =0xe000ed9c                             /* Region Base Address register. */\r
+       ldmia r1!, {r4-r11}                             /* Read 4 sets of MPU registers. */\r
+       stmia r2!, {r4-r11}                             /* Write 4 sets of MPU registers. */\r
+       ldmia r0!, {r3-r11, r14}                /* Pop the registers that are not automatically saved on exception entry. */\r
+       msr control, r3\r
+\r
+       tst r14, #0x10                                  /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
+       it eq\r
+       vldmiaeq r0!, {s16-s31}\r
+\r
+       msr psp, r0\r
+       bx r14\r
+       nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+uint32_t ulDummy;\r
+\r
+       ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
+       {\r
+               /* Increment the RTOS tick. */\r
+               if( xTaskIncrementTick() != pdFALSE )\r
+               {\r
+                       /* Pend a context switch. */\r
+                       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+               }\r
+       }\r
+       portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+       /* Configure SysTick to interrupt at the requested rate. */\r
+       portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+       portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vPortSwitchToUserMode( void )\r
+{\r
+       PRESERVE8\r
+       \r
+       mrs r0, control\r
+       orr r0, #1\r
+       msr control, r0\r
+       bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+       \r
+__asm void vPortEnableVFP( void )\r
+{\r
+       PRESERVE8\r
+       \r
+       ldr.w r0, =0xE000ED88           /* The FPU enable bits are in the CPACR. */\r
+       ldr r1, [r0]\r
+\r
+       orr r1, r1, #( 0xf << 20 )      /* Enable CP10 and CP11 coprocessors, then save back. */\r
+       str r1, [r0]\r
+       bx r14\r
+       nop\r
+       nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupMPU( void )\r
+{\r
+extern uint32_t __privileged_functions_end__;\r
+extern uint32_t __FLASH_segment_start__;\r
+extern uint32_t __FLASH_segment_end__;\r
+extern uint32_t __privileged_data_start__;\r
+extern uint32_t __privileged_data_end__;\r
+\r
+       /* Check the expected MPU is present. */\r
+       if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+       {\r
+               /* First setup the entire flash for unprivileged read only access. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portUNPRIVILEGED_FLASH_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
+                                                                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                                                               ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Setup the first 16K for privileged only access (even though less\r
+               than 10K is actually being used).  This is where the kernel code is\r
+               placed. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portPRIVILEGED_FLASH_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
+                                                                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                                                               ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Setup the privileged data RAM region.  This is where the kernel data\r
+               is placed. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portPRIVILEGED_RAM_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+                                                                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                                                               prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* By default allow everything to access the general peripherals.  The\r
+               system peripherals and registers are protected. */\r
+               portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
+                                                                                       ( portMPU_REGION_VALID ) |\r
+                                                                                       ( portGENERAL_PERIPHERALS_REGION );\r
+\r
+               portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
+                                                                               ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
+                                                                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Enable the memory fault exception. */\r
+               portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
+\r
+               /* Enable the MPU with the background region configured. */\r
+               portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
+{\r
+uint32_t ulRegionSize, ulReturnValue = 4;\r
+\r
+       /* 32 is the smallest region size, 31 is the largest valid value for\r
+       ulReturnValue. */\r
+       for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
+       {\r
+               if( ulActualSizeInBytes <= ulRegionSize )\r
+               {\r
+                       break;\r
+               }\r
+               else\r
+               {\r
+                       ulReturnValue++;\r
+               }\r
+       }\r
+\r
+       /* Shift the code by one before returning so it can be written directly\r
+       into the the correct bit position of the attribute register. */\r
+       return ( ulReturnValue << 1UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm BaseType_t xPortRaisePrivilege( void )\r
+{\r
+       mrs r0, control\r
+       tst r0, #1                                              /* Is the task running privileged? */\r
+       itte ne\r
+       movne r0, #0                                    /* CONTROL[0]!=0, return false. */\r
+       svcne portSVC_RAISE_PRIVILEGE   /* Switch to privileged. */\r
+       moveq r0, #1                                    /* CONTROL[0]==0, return true. */\r
+       bx lr\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+{\r
+extern uint32_t __SRAM_segment_start__;\r
+extern uint32_t __SRAM_segment_end__;\r
+extern uint32_t __privileged_data_start__;\r
+extern uint32_t __privileged_data_end__;\r
+\r
+       \r
+int32_t lIndex;\r
+uint32_t ul;\r
+\r
+       if( xRegions == NULL )\r
+       {\r
+               /* No MPU regions are specified so allow access to all RAM. */\r
+               xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
+                               ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
+                               ( portMPU_REGION_VALID ) |\r
+                               ( portSTACK_REGION );\r
+\r
+               xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
+                               ( portMPU_REGION_READ_WRITE ) |\r
+                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                               ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
+                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
+               just removed the privileged only parameters. */\r
+               xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
+                               ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
+                               ( portMPU_REGION_VALID ) |\r
+                               ( portSTACK_REGION + 1 );\r
+\r
+               xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+                               ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                               prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
+                               ( portMPU_REGION_ENABLE );\r
+\r
+               /* Invalidate all other regions. */\r
+               for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
+               {\r
+                       xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
+                       xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
+               }\r
+       }\r
+       else\r
+       {\r
+               /* This function is called automatically when the task is created - in\r
+               which case the stack region parameters will be valid.  At all other\r
+               times the stack parameters will not be valid and it is assumed that the\r
+               stack region has already been configured. */\r
+               if( ulStackDepth > 0 )\r
+               {\r
+                       /* Define the region that allows access to the stack. */\r
+                       xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
+                                       ( ( uint32_t ) pxBottomOfStack ) |\r
+                                       ( portMPU_REGION_VALID ) |\r
+                                       ( portSTACK_REGION ); /* Region number. */\r
+\r
+                       xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
+                                       ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
+                                       ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
+                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+                                       ( portMPU_REGION_ENABLE );\r
+               }\r
+\r
+               lIndex = 0;\r
+\r
+               for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
+               {\r
+                       if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
+                       {\r
+                               /* Translate the generic region definition contained in\r
+                               xRegions into the CM3 specific MPU settings that are then\r
+                               stored in xMPUSettings. */\r
+                               xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
+                                               ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
+                                               ( portMPU_REGION_VALID ) |\r
+                                               ( portSTACK_REGION + ul ); /* Region number. */\r
+\r
+                               xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
+                                               ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
+                                               ( xRegions[ lIndex ].ulParameters ) |\r
+                                               ( portMPU_REGION_ENABLE );\r
+                       }\r
+                       else\r
+                       {\r
+                               /* Invalidate the region. */\r
+                               xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
+                               xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
+                       }\r
+\r
+                       lIndex++;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm uint32_t prvPortGetIPSR( void )\r
+{\r
+       PRESERVE8\r
+\r
+       mrs r0, ipsr\r
+       bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+       void vPortValidateInterruptPriority( void )\r
+       {\r
+       uint32_t ulCurrentInterrupt;\r
+       uint8_t ucCurrentPriority;\r
+\r
+               /* Obtain the number of the currently executing interrupt. */\r
+               ulCurrentInterrupt = prvPortGetIPSR();\r
+\r
+               /* Is the interrupt number a user defined interrupt? */\r
+               if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+               {\r
+                       /* Look up the interrupt's priority. */\r
+                       ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+                       /* The following assertion will fail if a service routine (ISR) for\r
+                       an interrupt that has been assigned a priority above\r
+                       configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+                       function.  ISR safe FreeRTOS API functions must *only* be called\r
+                       from interrupts that have been assigned a priority at or below\r
+                       configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+                       Numerically low interrupt priority numbers represent logically high\r
+                       interrupt priorities, therefore the priority of the interrupt must\r
+                       be set to a value equal to or numerically *higher* than\r
+                       configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+                       Interrupts that use the FreeRTOS API must not be left at their\r
+                       default priority of     zero as that is the highest possible priority,\r
+                       which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+                       and     therefore also guaranteed to be invalid.\r
+\r
+                       FreeRTOS maintains separate thread and ISR API functions to ensure\r
+                       interrupt entry is as fast and simple as possible.\r
+\r
+                       The following links provide detailed information:\r
+                       http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+                       http://www.freertos.org/FAQHelp.html */\r
+                       configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+               }\r
+\r
+               /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
+               that define each interrupt's priority to be split between bits that\r
+               define the interrupt's pre-emption priority bits and bits that define\r
+               the interrupt's sub-priority.  For simplicity all bits must be defined\r
+               to be pre-emption priority bits.  The following assertion will fail if\r
+               this is not the case (if some bits represent a sub-priority).\r
+\r
+               If the application only uses CMSIS libraries for interrupt\r
+               configuration then the correct setting can be achieved on all Cortex-M\r
+               devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+               scheduler.  Note however that some vendor specific peripheral libraries\r
+               assume a non-zero priority group setting, in which cases using a value\r
+               of zero will result in unpredicable behaviour. */\r
+               configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
+       }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+\r
+\r
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
new file mode 100644 (file)
index 0000000..bbe3c53
--- /dev/null
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -0,0 +1,348 @@
+/*\r
+    FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+    All rights reserved\r
+\r
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+    ***************************************************************************\r
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
+    >>!   obliged to provide the source code for proprietary components     !<<\r
+    >>!   outside of the FreeRTOS kernel.                                   !<<\r
+    ***************************************************************************\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
+    link: http://www.freertos.org/a00114.html\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS provides completely free yet professionally developed,    *\r
+     *    robust, strictly quality controlled, supported, and cross          *\r
+     *    platform software that is more than just the market leader, it     *\r
+     *    is the industry's de facto standard.                               *\r
+     *                                                                       *\r
+     *    Help yourself get started quickly while simultaneously helping     *\r
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
+     *    tutorial book, reference manual, or both:                          *\r
+     *    http://www.FreeRTOS.org/Documentation                              *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
+    the FAQ page "My application does not run, what could be wrong?".  Have you\r
+    defined configASSERT()?\r
+\r
+    http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+    embedded software for free we request you assist our global community by\r
+    participating in the support forum.\r
+\r
+    http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+    be as productive as possible as early as possible.  Now you can receive\r
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+    Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
+    licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+\r
+    1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR               char\r
+#define portFLOAT              float\r
+#define portDOUBLE             double\r
+#define portLONG               long\r
+#define portSHORT              short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE  long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+       typedef uint16_t TickType_t;\r
+       #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+       typedef uint32_t TickType_t;\r
+       #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+       /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+       not need to be guarded with a critical section. */\r
+       #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* MPU specific constants. */\r
+#define portUSING_MPU_WRAPPERS         1\r
+#define portPRIVILEGE_BIT                      ( 0x80000000UL )\r
+\r
+#define portMPU_REGION_READ_WRITE                              ( 0x03UL << 24UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY            ( 0x05UL << 24UL )\r
+#define portMPU_REGION_READ_ONLY                               ( 0x06UL << 24UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE   ( 0x01UL << 24UL )\r
+#define portMPU_REGION_CACHEABLE_BUFFERABLE            ( 0x07UL << 16UL )\r
+#define portMPU_REGION_EXECUTE_NEVER                   ( 0x01UL << 28UL )\r
+\r
+#define portUNPRIVILEGED_FLASH_REGION          ( 0UL )\r
+#define portPRIVILEGED_FLASH_REGION                    ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION                      ( 2UL )\r
+#define portGENERAL_PERIPHERALS_REGION         ( 3UL )\r
+#define portSTACK_REGION                                       ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION      ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION           ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS           ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS                          ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+void vPortSwitchToUserMode( void );\r
+#define portSWITCH_TO_USER_MODE()      vPortSwitchToUserMode()\r
+\r
+typedef struct MPU_REGION_REGISTERS\r
+{\r
+       uint32_t ulRegionBaseAddress;\r
+       uint32_t ulRegionAttribute;\r
+} xMPU_REGION_REGISTERS;\r
+\r
+/* Plus 1 to create space for the stack region. */\r
+typedef struct MPU_SETTINGS\r
+{\r
+       xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];\r
+} xMPU_SETTINGS;\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH                       ( -1 )\r
+#define portTICK_PERIOD_MS                     ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT                     8\r
+\r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE         ( 15 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* SVC numbers for various services. */\r
+#define portSVC_START_SCHEDULER                                0\r
+#define portSVC_YIELD                                          1\r
+#define portSVC_RAISE_PRIVILEGE                                2\r
+\r
+/* Scheduler utilities. */\r
+\r
+#define portYIELD()                            __asm{ SVC portSVC_YIELD }\r
+#define portYIELD_WITHIN_API()                                                                                                         \\r
+{                                                                                                                                                              \\r
+       /* Set a PendSV to request a context switch. */                                                         \\r
+       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;                                                         \\r
+                                                                                                                                                               \\r
+       /* Barriers are normally not required but do ensure the code is completely      \\r
+       within the specified behaviour for the architecture. */                                         \\r
+       __dsb( portSY_FULL_READ_WRITE );                                                                                        \\r
+       __isb( portSY_FULL_READ_WRITE );                                                                                        \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portNVIC_INT_CTRL_REG          ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT         ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS()                               vPortRaiseBASEPRI()\r
+#define portENABLE_INTERRUPTS()                                        vPortSetBASEPRI(0)\r
+#define portENTER_CRITICAL()                                   vPortEnterCritical()\r
+#define portEXIT_CRITICAL()                                            vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR()              ulPortRaiseBASEPRI()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vPortSetBASEPRI(x)\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+       #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+       /* Check the configuration. */\r
+       #if( configMAX_PRIORITIES > 32 )\r
+               #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+       #endif\r
+\r
+       /* Store/clear the ready priorities in a bit map. */\r
+       #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+       #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+       /*-----------------------------------------------------------*/\r
+\r
+       #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are\r
+not necessary for to use this port.  They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+       void vPortValidateInterruptPriority( void );\r
+       #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()      vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/* portNOP() is not required by this port. */\r
+#define portNOP()\r
+\r
+#define portINLINE __inline\r
+\r
+#ifndef portFORCE_INLINE\r
+       #define portFORCE_INLINE __forceinline\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\r
+{\r
+       __asm\r
+       {\r
+               /* Barrier instructions are not used as this function is only used to\r
+               lower the BASEPRI value. */\r
+               msr basepri, ulBASEPRI\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+       __asm\r
+       {\r
+               /* Set BASEPRI to the max syscall priority to effect a critical\r
+               section. */\r
+               msr basepri, ulNewBASEPRI\r
+               dsb\r
+               isb\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )\r
+{\r
+       __asm\r
+       {\r
+               /* Set BASEPRI to 0 so no interrupts are masked.  This function is only\r
+               used to lower the mask in an interrupt, so memory barriers are not \r
+               used. */\r
+               msr basepri, #0\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+       __asm\r
+       {\r
+               /* Set BASEPRI to the max syscall priority to effect a critical\r
+               section. */\r
+               mrs ulReturn, basepri\r
+               msr basepri, ulNewBASEPRI\r
+               dsb\r
+               isb\r
+       }\r
+\r
+       return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )\r
+{\r
+uint32_t ulCurrentInterrupt;\r
+BaseType_t xReturn;\r
+\r
+       /* Obtain the number of the currently executing interrupt. */\r
+       __asm\r
+       {\r
+               mrs ulCurrentInterrupt, ipsr\r
+       }\r
+\r
+       if( ulCurrentInterrupt == 0 )\r
+       {\r
+               xReturn = pdFALSE;\r
+       }\r
+       else\r
+       {\r
+               xReturn = pdTRUE;\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Set the privilege level to user mode if xRunningPrivileged is false. */\r
+portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )\r
+{\r
+uint32_t ulReg;\r
+       \r
+       if( xRunningPrivileged != pdTRUE ) \r
+       {\r
+               __asm \r
+               {\r
+                       mrs ulReg, control\r
+                       orr ulReg, #1\r
+                       msr control, ulReg\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
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