2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Including FreeRTOSConfig.h here will cause build errors if the header file
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29 contains code not understood by the assembler - for example the 'extern' keyword.
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30 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
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31 the code is included in C files but excluded by the preprocessor in assembly
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32 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
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33 #include "FreeRTOSConfig.h"
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36 EXTERN xSecureContext
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37 EXTERN vTaskSwitchContext
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38 EXTERN vPortSVCHandler_C
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39 EXTERN SecureContext_SaveContext
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40 EXTERN SecureContext_LoadContext
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42 PUBLIC xIsPrivileged
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43 PUBLIC vResetPrivilege
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44 PUBLIC vPortAllocateSecureContext
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45 PUBLIC vRestoreContextOfFirstTask
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46 PUBLIC vRaisePrivilege
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47 PUBLIC vStartFirstTask
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48 PUBLIC ulSetInterruptMask
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49 PUBLIC vClearInterruptMask
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50 PUBLIC PendSV_Handler
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52 PUBLIC vPortFreeSecureContext
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53 /*-----------------------------------------------------------*/
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55 /*---------------- Unprivileged Functions -------------------*/
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57 /*-----------------------------------------------------------*/
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59 SECTION .text:CODE:NOROOT(2)
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61 /*-----------------------------------------------------------*/
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64 mrs r0, control /* r0 = CONTROL. */
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65 tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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67 movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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68 moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
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70 /*-----------------------------------------------------------*/
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73 mrs r0, control /* r0 = CONTROL. */
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74 orr r0, r0, #1 /* r0 = r0 | 1. */
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75 msr control, r0 /* CONTROL = r0. */
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76 bx lr /* Return to the caller. */
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77 /*-----------------------------------------------------------*/
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79 vPortAllocateSecureContext:
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80 svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
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82 /*-----------------------------------------------------------*/
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84 /*----------------- Privileged Functions --------------------*/
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86 /*-----------------------------------------------------------*/
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88 SECTION privileged_functions:CODE:NOROOT(2)
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90 /*-----------------------------------------------------------*/
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92 vRestoreContextOfFirstTask:
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93 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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94 ldr r3, [r2] /* Read pxCurrentTCB. */
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95 ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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97 #if ( configENABLE_MPU == 1 )
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98 dmb /* Complete outstanding transfers before disabling MPU. */
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99 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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100 ldr r4, [r2] /* Read the value of MPU_CTRL. */
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101 bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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102 str r4, [r2] /* Disable MPU. */
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104 adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
\r
105 ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
\r
106 ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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107 str r4, [r2] /* Program MAIR0. */
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108 ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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109 movs r4, #4 /* r4 = 4. */
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110 str r4, [r2] /* Program RNR = 4. */
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111 adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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112 ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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113 ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
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114 stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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116 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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117 ldr r4, [r2] /* Read the value of MPU_CTRL. */
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118 orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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119 str r4, [r2] /* Enable MPU. */
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120 dsb /* Force memory writes before continuing. */
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121 #endif /* configENABLE_MPU */
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123 #if ( configENABLE_MPU == 1 )
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124 ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
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125 ldr r5, =xSecureContext
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126 str r1, [r5] /* Set xSecureContext to this task's value for the same. */
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127 msr psplim, r2 /* Set this task's PSPLIM value. */
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128 msr control, r3 /* Set this task's CONTROL value. */
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129 adds r0, #32 /* Discard everything up to r0. */
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130 msr psp, r0 /* This is now the new top of stack to use in the task. */
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132 bx r4 /* Finally, branch to EXC_RETURN. */
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133 #else /* configENABLE_MPU */
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134 ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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135 ldr r4, =xSecureContext
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136 str r1, [r4] /* Set xSecureContext to this task's value for the same. */
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137 msr psplim, r2 /* Set this task's PSPLIM value. */
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138 movs r1, #2 /* r1 = 2. */
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139 msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
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140 adds r0, #32 /* Discard everything up to r0. */
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141 msr psp, r0 /* This is now the new top of stack to use in the task. */
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143 bx r3 /* Finally, branch to EXC_RETURN. */
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144 #endif /* configENABLE_MPU */
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145 /*-----------------------------------------------------------*/
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148 mrs r0, control /* Read the CONTROL register. */
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149 bic r0, r0, #1 /* Clear the bit 0. */
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150 msr control, r0 /* Write back the new CONTROL value. */
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151 bx lr /* Return to the caller. */
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152 /*-----------------------------------------------------------*/
\r
155 ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
\r
156 ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
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157 ldr r0, [r0] /* The first entry in vector table is stack pointer. */
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158 msr msp, r0 /* Set the MSP back to the start of the stack. */
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159 cpsie i /* Globally enable interrupts. */
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163 svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
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164 /*-----------------------------------------------------------*/
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166 ulSetInterruptMask:
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167 mrs r0, basepri /* r0 = basepri. Return original basepri value. */
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168 mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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169 msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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172 bx lr /* Return. */
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173 /*-----------------------------------------------------------*/
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175 vClearInterruptMask:
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176 msr basepri, r0 /* basepri = ulMask. */
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179 bx lr /* Return. */
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180 /*-----------------------------------------------------------*/
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183 mrs r1, psp /* Read PSP in r1. */
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184 ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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185 ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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187 cbz r0, save_ns_context /* No secure context to save. */
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189 bl SecureContext_SaveContext
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190 pop {r0-r3} /* LR is now in r3. */
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191 mov lr, r3 /* LR = r3. */
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192 lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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193 bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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194 ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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195 ldr r2, [r3] /* Read pxCurrentTCB. */
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196 #if ( configENABLE_MPU == 1 )
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197 subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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198 str r1, [r2] /* Save the new top of stack in TCB. */
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199 mrs r2, psplim /* r2 = PSPLIM. */
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200 mrs r3, control /* r3 = CONTROL. */
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201 mov r4, lr /* r4 = LR/EXC_RETURN. */
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202 stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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203 #else /* configENABLE_MPU */
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204 subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
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205 str r1, [r2] /* Save the new top of stack in TCB. */
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206 mrs r2, psplim /* r2 = PSPLIM. */
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207 mov r3, lr /* r3 = LR/EXC_RETURN. */
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208 stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
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209 #endif /* configENABLE_MPU */
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213 ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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214 ldr r2, [r3] /* Read pxCurrentTCB. */
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215 #if ( configENABLE_FPU == 1 )
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216 tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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218 vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
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219 #endif /* configENABLE_FPU */
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220 #if ( configENABLE_MPU == 1 )
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221 subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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222 str r1, [r2] /* Save the new top of stack in TCB. */
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223 adds r1, r1, #16 /* r1 = r1 + 16. */
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224 stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
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225 mrs r2, psplim /* r2 = PSPLIM. */
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226 mrs r3, control /* r3 = CONTROL. */
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227 mov r4, lr /* r4 = LR/EXC_RETURN. */
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228 subs r1, r1, #16 /* r1 = r1 - 16. */
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229 stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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230 #else /* configENABLE_MPU */
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231 subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
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232 str r1, [r2] /* Save the new top of stack in TCB. */
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233 adds r1, r1, #12 /* r1 = r1 + 12. */
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234 stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
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235 mrs r2, psplim /* r2 = PSPLIM. */
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236 mov r3, lr /* r3 = LR/EXC_RETURN. */
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237 subs r1, r1, #12 /* r1 = r1 - 12. */
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238 stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
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239 #endif /* configENABLE_MPU */
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242 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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243 msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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246 bl vTaskSwitchContext
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247 mov r0, #0 /* r0 = 0. */
\r
248 msr basepri, r0 /* Enable interrupts. */
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250 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
\r
251 ldr r3, [r2] /* Read pxCurrentTCB. */
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252 ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
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254 #if ( configENABLE_MPU == 1 )
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255 dmb /* Complete outstanding transfers before disabling MPU. */
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256 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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257 ldr r4, [r2] /* Read the value of MPU_CTRL. */
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258 bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
\r
259 str r4, [r2] /* Disable MPU. */
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261 adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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262 ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
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263 ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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264 str r4, [r2] /* Program MAIR0. */
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265 ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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266 movs r4, #4 /* r4 = 4. */
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267 str r4, [r2] /* Program RNR = 4. */
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268 adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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269 ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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270 ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
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271 stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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273 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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274 ldr r4, [r2] /* Read the value of MPU_CTRL. */
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275 orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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276 str r4, [r2] /* Enable MPU. */
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277 dsb /* Force memory writes before continuing. */
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278 #endif /* configENABLE_MPU */
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280 #if ( configENABLE_MPU == 1 )
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281 ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
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282 msr psplim, r2 /* Restore the PSPLIM register value for the task. */
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283 msr control, r3 /* Restore the CONTROL register value for the task. */
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284 mov lr, r4 /* LR = r4. */
\r
285 ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
\r
286 str r0, [r2] /* Restore the task's xSecureContext. */
\r
287 cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
\r
289 bl SecureContext_LoadContext /* Restore the secure context. */
\r
291 mov lr, r4 /* LR = r4. */
\r
292 lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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293 bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
\r
294 msr psp, r1 /* Remember the new top of stack for the task. */
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296 #else /* configENABLE_MPU */
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297 ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
\r
298 msr psplim, r2 /* Restore the PSPLIM register value for the task. */
\r
299 mov lr, r3 /* LR = r3. */
\r
300 ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
\r
301 str r0, [r2] /* Restore the task's xSecureContext. */
\r
302 cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
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304 bl SecureContext_LoadContext /* Restore the secure context. */
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306 mov lr, r3 /* LR = r3. */
\r
307 lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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308 bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
\r
309 msr psp, r1 /* Remember the new top of stack for the task. */
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311 #endif /* configENABLE_MPU */
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313 restore_ns_context:
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314 ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */
\r
315 #if ( configENABLE_FPU == 1 )
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316 tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
\r
318 vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
\r
319 #endif /* configENABLE_FPU */
\r
320 msr psp, r1 /* Remember the new top of stack for the task. */
\r
322 /*-----------------------------------------------------------*/
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329 b vPortSVCHandler_C
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330 /*-----------------------------------------------------------*/
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332 vPortFreeSecureContext:
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333 /* r0 = uint32_t *pulTCB. */
\r
334 ldr r1, [r0] /* The first item in the TCB is the top of the stack. */
\r
335 ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */
\r
336 cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */
\r
338 svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
\r
339 bx lr /* Return. */
\r
340 /*-----------------------------------------------------------*/
\r