2 ******************************************************************************
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3 * @file stm32fxx_hal_eth.c
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4 * @author MCD Application Team
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7 * @brief ETH HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Ethernet (ETH) peripheral:
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10 * + Initialization and de-initialization functions
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11 * + IO operation functions
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12 * + Peripheral Control functions
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13 * + Peripheral State and Errors functions
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16 ==============================================================================
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17 ##### How to use this driver #####
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18 ==============================================================================
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20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
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21 ETH_HandleTypeDef heth;
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23 (#)Fill parameters of Init structure in heth handle
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25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
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27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
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28 (##) Enable the Ethernet interface clock using
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29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
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30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
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31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
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33 (##) Initialize the related GPIO clocks
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34 (##) Configure Ethernet pin-out
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35 (##) Configure Ethernet NVIC interrupt (IT mode)
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37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
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38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
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39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
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41 (#)Enable MAC and DMA transmission and reception:
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42 (##) HAL_ETH_Start();
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44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
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45 the frame to MAC TX FIFO:
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46 (##) HAL_ETH_TransmitFrame();
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48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
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50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
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52 (#) Get a received frame when an ETH RX interrupt occurs:
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53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
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55 (#) Communicate with external PHY device:
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56 (##) Read a specific register from the PHY
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57 HAL_ETH_ReadPHYRegister();
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58 (##) Write data to a specific RHY register:
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59 HAL_ETH_WritePHYRegister();
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61 (#) Configure the Ethernet MAC after ETH peripheral initialization
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62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
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64 (#) Configure the Ethernet DMA after ETH peripheral initialization
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65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
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67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
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71 ******************************************************************************
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74 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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76 * Redistribution and use in source and binary forms, with or without modification,
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77 * are permitted provided that the following conditions are met:
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78 * 1. Redistributions of source code must retain the above copyright notice,
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79 * this list of conditions and the following disclaimer.
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80 * 2. Redistributions in binary form must reproduce the above copyright notice,
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81 * this list of conditions and the following disclaimer in the documentation
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82 * and/or other materials provided with the distribution.
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83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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84 * may be used to endorse or promote products derived from this software
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85 * without specific prior written permission.
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87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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98 ******************************************************************************
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101 /* Includes ------------------------------------------------------------------*/
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102 #define __STM32_HAL_LEGACY 1
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104 #if defined(STM32F7xx)
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105 #include "stm32f7xx_hal.h"
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106 #include "stm32f7xx_hal_def.h"
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107 #define stm_is_F7 1
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108 #elif defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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109 #include "stm32f4xx_hal.h"
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110 #include "stm32f4xx_hal_def.h"
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111 #define stm_is_F4 1
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112 #elif defined(STM32F2xx)
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113 #include "stm32f2xx_hal.h"
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114 #include "stm32f2xx_hal_def.h"
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115 #define stm_is_F2 1
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117 #error For what part should this be compiled?
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120 #include "stm32fxx_hal_eth.h"
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122 /** @addtogroup STM32F4xx_HAL_Driver
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126 /** @defgroup ETH ETH
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127 * @brief ETH HAL module driver
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131 #if !defined( ARRAY_SIZE )
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132 #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] )
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135 #ifdef HAL_ETH_MODULE_ENABLED
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137 #if( stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 )
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139 /* Private typedef -----------------------------------------------------------*/
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140 /* Private define ------------------------------------------------------------*/
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141 /** @defgroup ETH_Private_Constants ETH Private Constants
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148 /* Private macro -------------------------------------------------------------*/
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149 /* Private variables ---------------------------------------------------------*/
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150 /* Private function prototypes -----------------------------------------------*/
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151 /** @defgroup ETH_Private_Functions ETH Private Functions
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154 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
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155 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
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156 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
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157 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
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158 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
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159 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
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160 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
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161 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
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162 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
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163 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
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164 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
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169 /* Private functions ---------------------------------------------------------*/
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171 /** @defgroup ETH_Exported_Functions ETH Exported Functions
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175 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
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176 * @brief Initialization and Configuration functions
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179 ===============================================================================
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180 ##### Initialization and de-initialization functions #####
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181 ===============================================================================
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182 [..] This section provides functions allowing to:
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183 (+) Initialize and configure the Ethernet peripheral
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184 (+) De-initialize the Ethernet peripheral
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189 extern void vMACBProbePhy ( void );
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192 * @brief Initializes the Ethernet MAC and DMA according to default
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194 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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195 * the configuration information for ETHERNET module
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196 * @retval HAL status
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198 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
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200 uint32_t tmpreg = 0;
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201 uint32_t hclk = 60000000;
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202 uint32_t err = ETH_SUCCESS;
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204 /* Check the ETH peripheral state */
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210 /* Check parameters */
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211 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
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212 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
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213 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
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214 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
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216 if( heth->State == HAL_ETH_STATE_RESET )
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218 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
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219 HAL_ETH_MspInit( heth );
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222 /* Enable SYSCFG Clock */
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223 __HAL_RCC_SYSCFG_CLK_ENABLE();
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225 /* Select MII or RMII Mode*/
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226 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
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227 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
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229 /* Ethernet Software reset */
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230 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
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231 /* After reset all the registers holds their respective reset values */
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232 /* Also enable EDFE: Enhanced descriptor format enable. */
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233 heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE;
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235 /* Wait for software reset */
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236 while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
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238 /* If your program hangs here, please check the value of 'ipconfigUSE_RMII'. */
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241 /*-------------------------------- MAC Initialization ----------------------*/
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242 /* Get the ETHERNET MACMIIAR value */
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243 tmpreg = heth->Instance->MACMIIAR;
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244 /* Clear CSR Clock Range CR[2:0] bits */
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245 tmpreg &= ETH_MACMIIAR_CR_MASK;
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247 /* Get hclk frequency value (168,000,000) */
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248 hclk = HAL_RCC_GetHCLKFreq();
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250 /* Set CR bits depending on hclk value */
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251 if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) )
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253 /* CSR Clock Range between 20-35 MHz */
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254 tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16;
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256 else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) )
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258 /* CSR Clock Range between 35-60 MHz */
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259 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;
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261 else if((hclk >= 60000000 ) && ( hclk < 100000000 ) )
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263 /* CSR Clock Range between 60-100 MHz */
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264 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
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266 else if((hclk >= 100000000 ) && ( hclk < 150000000))
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268 /* CSR Clock Range between 100-150 MHz */
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269 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
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271 else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */
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273 /* CSR Clock Range between 150-168 MHz */
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274 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
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277 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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278 heth->Instance->MACMIIAR = (uint32_t)tmpreg;
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280 /* Initialise the MACB and set all PHY properties */
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283 /* Config MAC and DMA */
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284 ETH_MACDMAConfig(heth, err);
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286 /* Set ETH HAL State to Ready */
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287 heth->State= HAL_ETH_STATE_READY;
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289 /* Return function status */
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294 * @brief De-Initializes the ETH peripheral.
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295 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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296 * the configuration information for ETHERNET module
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297 * @retval HAL status
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299 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
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301 /* Set the ETH peripheral state to BUSY */
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302 heth->State = HAL_ETH_STATE_BUSY;
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304 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
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305 HAL_ETH_MspDeInit( heth );
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307 /* Set ETH HAL state to Disabled */
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308 heth->State= HAL_ETH_STATE_RESET;
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311 __HAL_UNLOCK( heth );
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313 /* Return function status */
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318 * @brief Initializes the DMA Tx descriptors in chain mode.
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319 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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320 * the configuration information for ETHERNET module
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321 * @param DMATxDescTab: Pointer to the first Tx desc list
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322 * @param TxBuff: Pointer to the first TxBuffer list
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323 * @param TxBuffCount: Number of the used Tx desc in the list
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324 * @retval HAL status
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326 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)
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329 ETH_DMADescTypeDef *pxDMADescriptor;
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331 /* Process Locked */
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332 __HAL_LOCK( heth );
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334 /* Set the ETH peripheral state to BUSY */
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335 heth->State = HAL_ETH_STATE_BUSY;
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337 /* Set the TxDesc pointer with the first one of the pxDMATable list */
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338 heth->TxDesc = pxDMATable;
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340 /* Fill each DMA descriptor with the right values */
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341 for( i=0; i < ulBufferCount; i++ )
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343 /* Get the pointer on the ith member of the descriptor list */
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344 pxDMADescriptor = pxDMATable + i;
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346 /* Set Second Address Chained bit */
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347 pxDMADescriptor->Status = ETH_DMATXDESC_TCH;
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349 pxDMADescriptor->ControlBufferSize = 0;
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351 /* Set Buffer1 address pointer */
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352 if( ucDataBuffer != NULL )
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354 pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] );
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358 /* Buffer space is not provided because it uses zero-copy transmissions. */
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359 pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;
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362 if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
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364 /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */
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365 pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
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368 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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369 if(i < ( ulBufferCount - 1 ) )
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371 /* Set next descriptor address register with next descriptor base address */
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372 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 );
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376 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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377 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;
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381 /* Set Transmit Descriptor List Address Register */
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382 heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable;
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384 /* Set ETH HAL State to Ready */
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385 heth->State= HAL_ETH_STATE_READY;
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387 /* Process Unlocked */
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388 __HAL_UNLOCK( heth );
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390 /* Return function status */
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395 * @brief Initializes the DMA Rx descriptors in chain mode.
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396 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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397 * the configuration information for ETHERNET module
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398 * @param DMARxDescTab: Pointer to the first Rx desc list
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399 * @param RxBuff: Pointer to the first RxBuffer list
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400 * @param RxBuffCount: Number of the used Rx desc in the list
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401 * @retval HAL status
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403 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)
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406 ETH_DMADescTypeDef *pxDMADescriptor;
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408 /* Process Locked */
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409 __HAL_LOCK( heth );
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411 /* Set the ETH peripheral state to BUSY */
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412 heth->State = HAL_ETH_STATE_BUSY;
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414 /* Set the RxDesc pointer with the first one of the pxDMATable list */
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415 heth->RxDesc = pxDMATable;
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417 /* Fill each DMA descriptor with the right values */
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418 for(i=0; i < ulBufferCount; i++)
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420 /* Get the pointer on the ith member of the descriptor list */
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421 pxDMADescriptor = pxDMATable+i;
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423 /* Set Own bit of the Rx descriptor Status */
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424 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
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426 /* Set Buffer1 size and Second Address Chained bit */
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427 pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
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429 /* Set Buffer1 address pointer */
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430 if( ucDataBuffer != NULL )
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432 pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] );
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436 /* Buffer space is not provided because it uses zero-copy reception. */
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437 pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;
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440 if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE )
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442 /* Enable Ethernet DMA Rx Descriptor interrupt */
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443 pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
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446 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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447 if(i < (ulBufferCount-1))
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449 /* Set next descriptor address register with next descriptor base address */
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450 pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1);
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454 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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455 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;
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459 /* Set Receive Descriptor List Address Register */
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460 heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable;
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462 /* Set ETH HAL State to Ready */
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463 heth->State= HAL_ETH_STATE_READY;
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465 /* Process Unlocked */
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466 __HAL_UNLOCK( heth );
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468 /* Return function status */
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473 * @brief Initializes the ETH MSP.
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474 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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475 * the configuration information for ETHERNET module
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478 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
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480 /* NOTE : This function Should not be modified, when the callback is needed,
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481 the HAL_ETH_MspInit could be implemented in the user file
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486 * @brief DeInitializes ETH MSP.
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487 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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488 * the configuration information for ETHERNET module
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491 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
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493 /* NOTE : This function Should not be modified, when the callback is needed,
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494 the HAL_ETH_MspDeInit could be implemented in the user file
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502 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
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503 * @brief Data transfers functions
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506 ==============================================================================
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507 ##### IO operation functions #####
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508 ==============================================================================
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509 [..] This section provides functions allowing to:
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510 (+) Transmit a frame
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511 HAL_ETH_TransmitFrame();
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512 (+) Receive a frame
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513 HAL_ETH_GetReceivedFrame();
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514 HAL_ETH_GetReceivedFrame_IT();
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515 (+) Read from an External PHY register
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516 HAL_ETH_ReadPHYRegister();
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517 (+) Write to an External PHY register
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518 HAL_ETH_WritePHYRegister();
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526 * @brief Sends an Ethernet frame.
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527 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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528 * the configuration information for ETHERNET module
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529 * @param FrameLength: Amount of data to be sent
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530 * @retval HAL status
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532 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
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534 uint32_t bufcount = 0, size = 0, i = 0;
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535 __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc;
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536 /* Process Locked */
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537 __HAL_LOCK( heth );
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539 /* Set the ETH peripheral state to BUSY */
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540 heth->State = HAL_ETH_STATE_BUSY;
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542 if( FrameLength == 0 )
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544 /* Set ETH HAL state to READY */
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545 heth->State = HAL_ETH_STATE_READY;
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547 /* Process Unlocked */
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548 __HAL_UNLOCK( heth );
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553 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
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554 if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET )
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557 heth->State = HAL_ETH_STATE_BUSY_TX;
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559 /* Process Unlocked */
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560 __HAL_UNLOCK( heth );
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565 /* Get the number of needed Tx buffers for the current frame, rounding up. */
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566 bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE;
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570 /* Set LAST and FIRST segment */
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571 pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
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572 /* Set frame size */
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573 pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 );
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574 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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575 pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;
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576 /* Point to next descriptor */
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577 heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr );
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581 for( i = 0; i < bufcount; i++ )
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583 /* Clear FIRST and LAST segment bits */
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584 uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS );
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588 /* Setting the first segment bit */
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589 heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS;
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593 if (i < (bufcount-1))
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595 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
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599 /* Setting the last segment bit */
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600 heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS;
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601 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
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602 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
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605 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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606 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
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607 /* point to next descriptor */
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608 heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr );
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614 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
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615 if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET )
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617 heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc;
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619 /* Clear TBUS ETHERNET DMA flag */
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620 heth->Instance->DMASR = ETH_DMASR_TBUS;
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621 /* Resume DMA transmission*/
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622 heth->Instance->DMATPDR = 0;
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625 /* Set ETH HAL State to Ready */
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626 heth->State = HAL_ETH_STATE_READY;
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628 /* Process Unlocked */
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629 __HAL_UNLOCK( heth );
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631 /* Return function status */
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636 * @brief Checks for received frames.
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637 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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638 * the configuration information for ETHERNET module
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639 * @retval HAL status
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641 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth )
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643 return HAL_ETH_GetReceivedFrame( heth );
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646 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth )
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648 uint32_t ulCounter = 0;
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649 ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc;
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650 HAL_StatusTypeDef xResult = HAL_ERROR;
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652 /* Process Locked */
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653 __HAL_LOCK( heth );
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655 /* Check the ETH state to BUSY */
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656 heth->State = HAL_ETH_STATE_BUSY;
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658 /* Scan descriptors owned by CPU */
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659 while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) )
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661 uint32_t ulStatus = pxDescriptor->Status;
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663 /* Just for security. */
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666 if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS )
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668 /* First segment in frame, but not the last. */
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669 heth->RxFrameInfos.FSRxDesc = pxDescriptor;
\r
670 heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL;
\r
671 heth->RxFrameInfos.SegCount = 1;
\r
672 /* Point to next descriptor. */
\r
673 pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr);
\r
674 heth->RxDesc = pxDescriptor;
\r
676 else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul )
\r
678 /* This is an intermediate segment, not first, not last. */
\r
679 /* Increment segment count. */
\r
680 heth->RxFrameInfos.SegCount++;
\r
681 /* Move to the next descriptor. */
\r
682 pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr );
\r
683 heth->RxDesc = pxDescriptor;
\r
685 /* Must be a last segment */
\r
688 /* This is the last segment. */
\r
689 /* Check if last segment is first segment: one segment contains the frame */
\r
690 if( heth->RxFrameInfos.SegCount == 0 )
\r
692 /* Remember the first segment. */
\r
693 heth->RxFrameInfos.FSRxDesc = pxDescriptor;
\r
696 /* Increment segment count */
\r
697 heth->RxFrameInfos.SegCount++;
\r
699 /* Remember the last segment. */
\r
700 heth->RxFrameInfos.LSRxDesc = pxDescriptor;
\r
702 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
\r
703 heth->RxFrameInfos.length =
\r
704 ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;
\r
706 /* Get the address of the buffer start address */
\r
707 heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr;
\r
709 /* Point to next descriptor */
\r
710 heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr;
\r
712 /* Return OK status: a packet was received. */
\r
718 /* Set ETH HAL State to Ready */
\r
719 heth->State = HAL_ETH_STATE_READY;
\r
721 /* Process Unlocked */
\r
722 __HAL_UNLOCK( heth );
\r
724 /* Return function status */
\r
728 #define ETH_DMA_ALL_INTS \
\r
729 ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \
\r
730 ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \
\r
731 ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )
\r
733 //#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS
\r
735 #define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) )
\r
736 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
\r
740 dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS;
\r
741 heth->Instance->DMASR = dmasr;
\r
743 /* Frame received */
\r
744 if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 )
\r
746 /* Receive complete callback */
\r
747 HAL_ETH_RxCpltCallback( heth );
\r
749 /* Frame transmitted */
\r
750 if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 )
\r
752 /* Transfer complete callback */
\r
753 HAL_ETH_TxCpltCallback( heth );
\r
756 /* ETH DMA Error */
\r
757 if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 )
\r
759 /* Ethernet Error callback */
\r
760 HAL_ETH_ErrorCallback( heth );
\r
765 * @brief Tx Transfer completed callbacks.
\r
766 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
767 * the configuration information for ETHERNET module
\r
770 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
\r
772 /* NOTE : This function Should not be modified, when the callback is needed,
\r
773 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
778 * @brief Rx Transfer completed callbacks.
\r
779 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
780 * the configuration information for ETHERNET module
\r
783 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
\r
785 /* NOTE : This function Should not be modified, when the callback is needed,
\r
786 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
791 * @brief Ethernet transfer error callbacks
\r
792 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
793 * the configuration information for ETHERNET module
\r
796 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
\r
798 /* NOTE : This function Should not be modified, when the callback is needed,
\r
799 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
804 * @brief Reads a PHY register
\r
805 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
806 * the configuration information for ETHERNET module
\r
807 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
\r
808 * This parameter can be one of the following values:
\r
809 * PHY_BCR: Transceiver Basic Control Register,
\r
810 * PHY_BSR: Transceiver Basic Status Register.
\r
811 * More PHY register could be read depending on the used PHY
\r
812 * @param RegValue: PHY register value
\r
813 * @retval HAL status
\r
815 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
\r
817 uint32_t tmpreg = 0;
\r
818 uint32_t tickstart = 0;
\r
819 HAL_StatusTypeDef xResult;
\r
821 /* Check parameters */
\r
822 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
\r
824 /* Check the ETH peripheral state */
\r
825 if( heth->State == HAL_ETH_STATE_BUSY_RD )
\r
827 xResult = HAL_BUSY;
\r
831 __HAL_LOCK( heth );
\r
833 /* Set ETH HAL State to BUSY_RD */
\r
834 heth->State = HAL_ETH_STATE_BUSY_RD;
\r
836 /* Get the ETHERNET MACMIIAR value */
\r
837 tmpreg = heth->Instance->MACMIIAR;
\r
839 /* Keep only the CSR Clock Range CR[2:0] bits value */
\r
840 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
\r
842 /* Prepare the MII address register value */
\r
843 tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */
\r
844 tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */
\r
845 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
\r
846 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
\r
848 /* Write the result value into the MII Address register */
\r
849 heth->Instance->MACMIIAR = tmpreg;
\r
852 tickstart = HAL_GetTick();
\r
854 /* Check for the Busy flag */
\r
857 tmpreg = heth->Instance->MACMIIAR;
\r
859 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )
\r
861 /* Get MACMIIDR value */
\r
862 *RegValue = ( uint32_t ) heth->Instance->MACMIIDR;
\r
866 /* Check for the Timeout */
\r
867 if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO )
\r
869 xResult = HAL_TIMEOUT;
\r
875 /* Set ETH HAL State to READY */
\r
876 heth->State = HAL_ETH_STATE_READY;
\r
878 /* Process Unlocked */
\r
879 __HAL_UNLOCK( heth );
\r
882 /* Return function status */
\r
887 * @brief Writes to a PHY register.
\r
888 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
889 * the configuration information for ETHERNET module
\r
890 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
\r
891 * This parameter can be one of the following values:
\r
892 * PHY_BCR: Transceiver Control Register.
\r
893 * More PHY register could be written depending on the used PHY
\r
894 * @param RegValue: the value to write
\r
895 * @retval HAL status
\r
897 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
\r
899 uint32_t tmpreg = 0;
\r
900 uint32_t tickstart = 0;
\r
901 HAL_StatusTypeDef xResult;
\r
903 /* Check parameters */
\r
904 assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) );
\r
906 /* Check the ETH peripheral state */
\r
907 if( heth->State == HAL_ETH_STATE_BUSY_WR )
\r
909 xResult = HAL_BUSY;
\r
913 __HAL_LOCK( heth );
\r
915 /* Set ETH HAL State to BUSY_WR */
\r
916 heth->State = HAL_ETH_STATE_BUSY_WR;
\r
918 /* Get the ETHERNET MACMIIAR value */
\r
919 tmpreg = heth->Instance->MACMIIAR;
\r
921 /* Keep only the CSR Clock Range CR[2:0] bits value */
\r
922 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
\r
924 /* Prepare the MII register address value */
\r
925 tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */
\r
926 tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */
\r
927 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
\r
928 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
\r
930 /* Give the value to the MII data register */
\r
931 heth->Instance->MACMIIDR = ( uint16_t ) RegValue;
\r
933 /* Write the result value into the MII Address register */
\r
934 heth->Instance->MACMIIAR = tmpreg;
\r
937 tickstart = HAL_GetTick();
\r
939 /* Check for the Busy flag */
\r
942 tmpreg = heth->Instance->MACMIIAR;
\r
944 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )
\r
949 /* Check for the Timeout */
\r
950 if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO )
\r
952 xResult = HAL_TIMEOUT;
\r
957 /* Set ETH HAL State to READY */
\r
958 heth->State = HAL_ETH_STATE_READY;
\r
959 /* Process Unlocked */
\r
960 __HAL_UNLOCK( heth );
\r
963 /* Return function status */
\r
971 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
\r
972 * @brief Peripheral Control functions
\r
975 ===============================================================================
\r
976 ##### Peripheral Control functions #####
\r
977 ===============================================================================
\r
978 [..] This section provides functions allowing to:
\r
979 (+) Enable MAC and DMA transmission and reception.
\r
981 (+) Disable MAC and DMA transmission and reception.
\r
983 (+) Set the MAC configuration in runtime mode
\r
984 HAL_ETH_ConfigMAC();
\r
985 (+) Set the DMA configuration in runtime mode
\r
986 HAL_ETH_ConfigDMA();
\r
993 * @brief Enables Ethernet MAC and DMA reception/transmission
\r
994 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
995 * the configuration information for ETHERNET module
\r
996 * @retval HAL status
\r
998 HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth )
\r
1000 /* Process Locked */
\r
1001 __HAL_LOCK( heth );
\r
1003 /* Set the ETH peripheral state to BUSY */
\r
1004 heth->State = HAL_ETH_STATE_BUSY;
\r
1006 /* Enable transmit state machine of the MAC for transmission on the MII */
\r
1007 ETH_MACTransmissionEnable( heth );
\r
1009 /* Enable receive state machine of the MAC for reception from the MII */
\r
1010 ETH_MACReceptionEnable( heth );
\r
1012 /* Flush Transmit FIFO */
\r
1013 ETH_FlushTransmitFIFO( heth );
\r
1015 /* Start DMA transmission */
\r
1016 ETH_DMATransmissionEnable( heth );
\r
1018 /* Start DMA reception */
\r
1019 ETH_DMAReceptionEnable( heth );
\r
1021 /* Set the ETH state to READY*/
\r
1022 heth->State= HAL_ETH_STATE_READY;
\r
1024 /* Process Unlocked */
\r
1025 __HAL_UNLOCK( heth );
\r
1027 /* Return function status */
\r
1032 * @brief Stop Ethernet MAC and DMA reception/transmission
\r
1033 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1034 * the configuration information for ETHERNET module
\r
1035 * @retval HAL status
\r
1037 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
\r
1039 /* Process Locked */
\r
1040 __HAL_LOCK( heth );
\r
1042 /* Set the ETH peripheral state to BUSY */
\r
1043 heth->State = HAL_ETH_STATE_BUSY;
\r
1045 /* Stop DMA transmission */
\r
1046 ETH_DMATransmissionDisable( heth );
\r
1048 /* Stop DMA reception */
\r
1049 ETH_DMAReceptionDisable( heth );
\r
1051 /* Disable receive state machine of the MAC for reception from the MII */
\r
1052 ETH_MACReceptionDisable( heth );
\r
1054 /* Flush Transmit FIFO */
\r
1055 ETH_FlushTransmitFIFO( heth );
\r
1057 /* Disable transmit state machine of the MAC for transmission on the MII */
\r
1058 ETH_MACTransmissionDisable( heth );
\r
1060 /* Set the ETH state*/
\r
1061 heth->State = HAL_ETH_STATE_READY;
\r
1063 /* Process Unlocked */
\r
1064 __HAL_UNLOCK( heth );
\r
1066 /* Return function status */
\r
1070 static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
1072 /* Enable the MAC transmission */
\r
1073 heth->Instance->MACFCR = ulValue;
\r
1075 /* Wait until the write operation will be taken into account:
\r
1076 at least four TX_CLK/RX_CLK clock cycles.
\r
1077 Read it back, wait a ms and */
\r
1078 ( void ) heth->Instance->MACFCR;
\r
1080 HAL_Delay( ETH_REG_WRITE_DELAY );
\r
1082 heth->Instance->MACFCR = ulValue;
\r
1085 static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
1087 /* Enable the MAC transmission */
\r
1088 heth->Instance->DMAOMR = ulValue;
\r
1090 /* Wait until the write operation will be taken into account:
\r
1091 at least four TX_CLK/RX_CLK clock cycles.
\r
1092 Read it back, wait a ms and */
\r
1093 ( void ) heth->Instance->DMAOMR;
\r
1095 HAL_Delay( ETH_REG_WRITE_DELAY );
\r
1097 heth->Instance->DMAOMR = ulValue;
\r
1100 static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
1102 /* Enable the MAC transmission */
\r
1103 heth->Instance->MACCR = ulValue;
\r
1105 /* Wait until the write operation will be taken into account:
\r
1106 at least four TX_CLK/RX_CLK clock cycles.
\r
1107 Read it back, wait a ms and */
\r
1108 ( void ) heth->Instance->MACCR;
\r
1110 HAL_Delay( ETH_REG_WRITE_DELAY );
\r
1112 heth->Instance->MACCR = ulValue;
\r
1116 * @brief Set ETH MAC Configuration.
\r
1117 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1118 * the configuration information for ETHERNET module
\r
1119 * @param macconf: MAC Configuration structure
\r
1120 * @retval HAL status
\r
1122 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
\r
1124 uint32_t tmpreg = 0;
\r
1126 /* Process Locked */
\r
1127 __HAL_LOCK( heth );
\r
1129 /* Set the ETH peripheral state to BUSY */
\r
1130 heth->State= HAL_ETH_STATE_BUSY;
\r
1132 assert_param(IS_ETH_SPEED(heth->Init.Speed));
\r
1133 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
\r
1135 if (macconf != NULL)
\r
1137 /* Check the parameters */
\r
1138 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
\r
1139 assert_param(IS_ETH_JABBER(macconf->Jabber));
\r
1140 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
\r
1141 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
\r
1142 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
\r
1143 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
\r
1144 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
\r
1145 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
\r
1146 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
\r
1147 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
\r
1148 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
\r
1149 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
\r
1150 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
\r
1151 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
\r
1152 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
\r
1153 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
\r
1154 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
\r
1155 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
\r
1156 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
\r
1157 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
\r
1158 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
\r
1159 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
\r
1160 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
\r
1161 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
\r
1162 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
\r
1163 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
\r
1164 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
\r
1166 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1167 /* Get the ETHERNET MACCR value */
\r
1168 tmpreg = heth->Instance->MACCR;
\r
1169 /* Clear WD, PCE, PS, TE and RE bits */
\r
1170 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
1172 tmpreg |= (uint32_t)(
\r
1173 macconf->Watchdog |
\r
1175 macconf->InterFrameGap |
\r
1176 macconf->CarrierSense |
\r
1177 heth->Init.Speed |
\r
1178 macconf->ReceiveOwn |
\r
1179 macconf->LoopbackMode |
\r
1180 heth->Init.DuplexMode |
\r
1181 macconf->ChecksumOffload |
\r
1182 macconf->RetryTransmission |
\r
1183 macconf->AutomaticPadCRCStrip |
\r
1184 macconf->BackOffLimit |
\r
1185 macconf->DeferralCheck);
\r
1187 /* Write to ETHERNET MACCR */
\r
1188 prvWriteMACCR( heth, tmpreg );
\r
1190 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
1191 /* Write to ETHERNET MACFFR */
\r
1192 heth->Instance->MACFFR = (uint32_t)(
\r
1193 macconf->ReceiveAll |
\r
1194 macconf->SourceAddrFilter |
\r
1195 macconf->PassControlFrames |
\r
1196 macconf->BroadcastFramesReception |
\r
1197 macconf->DestinationAddrFilter |
\r
1198 macconf->PromiscuousMode |
\r
1199 macconf->MulticastFramesFilter |
\r
1200 macconf->UnicastFramesFilter);
\r
1202 /* Wait until the write operation will be taken into account :
\r
1203 at least four TX_CLK/RX_CLK clock cycles */
\r
1204 tmpreg = heth->Instance->MACFFR;
\r
1205 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1206 heth->Instance->MACFFR = tmpreg;
\r
1208 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
\r
1209 /* Write to ETHERNET MACHTHR */
\r
1210 heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh;
\r
1212 /* Write to ETHERNET MACHTLR */
\r
1213 heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow;
\r
1214 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
\r
1216 /* Get the ETHERNET MACFCR value */
\r
1217 tmpreg = heth->Instance->MACFCR;
\r
1218 /* Clear xx bits */
\r
1219 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
1221 tmpreg |= (uint32_t)((
\r
1222 macconf->PauseTime << 16) |
\r
1223 macconf->ZeroQuantaPause |
\r
1224 macconf->PauseLowThreshold |
\r
1225 macconf->UnicastPauseFrameDetect |
\r
1226 macconf->ReceiveFlowControl |
\r
1227 macconf->TransmitFlowControl);
\r
1229 /* Write to ETHERNET MACFCR */
\r
1230 prvWriteMACFCR( heth, tmpreg );
\r
1232 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
\r
1233 heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
\r
1234 macconf->VLANTagIdentifier);
\r
1236 /* Wait until the write operation will be taken into account :
\r
1237 at least four TX_CLK/RX_CLK clock cycles */
\r
1238 tmpreg = heth->Instance->MACVLANTR;
\r
1239 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1240 heth->Instance->MACVLANTR = tmpreg;
\r
1242 else /* macconf == NULL : here we just configure Speed and Duplex mode */
\r
1244 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1245 /* Get the ETHERNET MACCR value */
\r
1246 tmpreg = heth->Instance->MACCR;
\r
1248 /* Clear FES and DM bits */
\r
1249 tmpreg &= ~((uint32_t)0x00004800);
\r
1251 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
\r
1253 /* Write to ETHERNET MACCR */
\r
1254 prvWriteMACCR( heth, tmpreg );
\r
1257 /* Set the ETH state to Ready */
\r
1258 heth->State= HAL_ETH_STATE_READY;
\r
1260 /* Process Unlocked */
\r
1261 __HAL_UNLOCK( heth );
\r
1263 /* Return function status */
\r
1268 * @brief Sets ETH DMA Configuration.
\r
1269 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1270 * the configuration information for ETHERNET module
\r
1271 * @param dmaconf: DMA Configuration structure
\r
1272 * @retval HAL status
\r
1274 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
\r
1276 uint32_t tmpreg = 0;
\r
1278 /* Process Locked */
\r
1279 __HAL_LOCK( heth );
\r
1281 /* Set the ETH peripheral state to BUSY */
\r
1282 heth->State= HAL_ETH_STATE_BUSY;
\r
1284 /* Check parameters */
\r
1285 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
\r
1286 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
\r
1287 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
\r
1288 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
\r
1289 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
\r
1290 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
\r
1291 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
\r
1292 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
\r
1293 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
\r
1294 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
\r
1295 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
\r
1296 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
\r
1297 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
\r
1298 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
\r
1299 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
\r
1300 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
\r
1302 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
\r
1303 /* Get the ETHERNET DMAOMR value */
\r
1304 tmpreg = heth->Instance->DMAOMR;
\r
1305 /* Clear xx bits */
\r
1306 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
1308 tmpreg |= (uint32_t)(
\r
1309 dmaconf->DropTCPIPChecksumErrorFrame |
\r
1310 dmaconf->ReceiveStoreForward |
\r
1311 dmaconf->FlushReceivedFrame |
\r
1312 dmaconf->TransmitStoreForward |
\r
1313 dmaconf->TransmitThresholdControl |
\r
1314 dmaconf->ForwardErrorFrames |
\r
1315 dmaconf->ForwardUndersizedGoodFrames |
\r
1316 dmaconf->ReceiveThresholdControl |
\r
1317 dmaconf->SecondFrameOperate);
\r
1319 /* Write to ETHERNET DMAOMR */
\r
1320 prvWriteDMAOMR( heth, tmpreg );
\r
1322 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
\r
1323 heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
\r
1324 dmaconf->FixedBurst |
\r
1325 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
1326 dmaconf->TxDMABurstLength |
\r
1327 dmaconf->EnhancedDescriptorFormat |
\r
1328 (dmaconf->DescriptorSkipLength << 2) |
\r
1329 dmaconf->DMAArbitration |
\r
1330 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
1332 /* Wait until the write operation will be taken into account:
\r
1333 at least four TX_CLK/RX_CLK clock cycles */
\r
1334 tmpreg = heth->Instance->DMABMR;
\r
1335 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1336 heth->Instance->DMABMR = tmpreg;
\r
1338 /* Set the ETH state to Ready */
\r
1339 heth->State= HAL_ETH_STATE_READY;
\r
1341 /* Process Unlocked */
\r
1342 __HAL_UNLOCK( heth );
\r
1344 /* Return function status */
\r
1352 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
\r
1353 * @brief Peripheral State functions
\r
1356 ===============================================================================
\r
1357 ##### Peripheral State functions #####
\r
1358 ===============================================================================
\r
1360 This subsection permits to get in run-time the status of the peripheral
\r
1361 and the data flow.
\r
1362 (+) Get the ETH handle state:
\r
1363 HAL_ETH_GetState();
\r
1371 * @brief Return the ETH HAL state
\r
1372 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1373 * the configuration information for ETHERNET module
\r
1374 * @retval HAL state
\r
1376 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
\r
1378 /* Return ETH state */
\r
1379 return heth->State;
\r
1390 /** @addtogroup ETH_Private_Functions
\r
1395 * @brief Configures Ethernet MAC and DMA with default parameters.
\r
1396 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1397 * the configuration information for ETHERNET module
\r
1398 * @param err: Ethernet Init error
\r
1399 * @retval HAL status
\r
1401 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
\r
1403 ETH_MACInitTypeDef macinit;
\r
1404 ETH_DMAInitTypeDef dmainit;
\r
1405 uint32_t tmpreg = 0;
\r
1407 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
\r
1409 /* Set Ethernet duplex mode to Full-duplex */
\r
1410 heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX;
\r
1412 /* Set Ethernet speed to 100M */
\r
1413 heth->Init.Speed = ETH_SPEED_100M;
\r
1416 /* Ethernet MAC default initialization **************************************/
\r
1417 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
\r
1418 macinit.Jabber = ETH_JABBER_ENABLE;
\r
1419 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
\r
1420 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
\r
1421 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
\r
1422 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
\r
1423 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
\r
1425 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
\r
1429 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
\r
1431 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
\r
1432 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
\r
1433 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
\r
1434 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
\r
1435 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
\r
1436 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
\r
1437 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
\r
1438 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
\r
1439 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
\r
1440 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
\r
1441 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
\r
1442 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
\r
1443 macinit.HashTableHigh = 0x0;
\r
1444 macinit.HashTableLow = 0x0;
\r
1445 macinit.PauseTime = 0x0;
\r
1446 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
\r
1447 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
\r
1448 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
\r
1449 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
\r
1450 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
\r
1451 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
\r
1452 macinit.VLANTagIdentifier = 0x0;
\r
1454 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1455 /* Get the ETHERNET MACCR value */
\r
1456 tmpreg = heth->Instance->MACCR;
\r
1457 /* Clear WD, PCE, PS, TE and RE bits */
\r
1458 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
1459 /* Set the WD bit according to ETH Watchdog value */
\r
1460 /* Set the JD: bit according to ETH Jabber value */
\r
1461 /* Set the IFG bit according to ETH InterFrameGap value */
\r
1462 /* Set the DCRS bit according to ETH CarrierSense value */
\r
1463 /* Set the FES bit according to ETH Speed value */
\r
1464 /* Set the DO bit according to ETH ReceiveOwn value */
\r
1465 /* Set the LM bit according to ETH LoopbackMode value */
\r
1466 /* Set the DM bit according to ETH Mode value */
\r
1467 /* Set the IPCO bit according to ETH ChecksumOffload value */
\r
1468 /* Set the DR bit according to ETH RetryTransmission value */
\r
1469 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
\r
1470 /* Set the BL bit according to ETH BackOffLimit value */
\r
1471 /* Set the DC bit according to ETH DeferralCheck value */
\r
1472 tmpreg |= (uint32_t)(macinit.Watchdog |
\r
1474 macinit.InterFrameGap |
\r
1475 macinit.CarrierSense |
\r
1476 heth->Init.Speed |
\r
1477 macinit.ReceiveOwn |
\r
1478 macinit.LoopbackMode |
\r
1479 heth->Init.DuplexMode |
\r
1480 macinit.ChecksumOffload |
\r
1481 macinit.RetryTransmission |
\r
1482 macinit.AutomaticPadCRCStrip |
\r
1483 macinit.BackOffLimit |
\r
1484 macinit.DeferralCheck);
\r
1486 /* Write to ETHERNET MACCR */
\r
1487 prvWriteMACCR( heth, tmpreg );
\r
1489 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
1490 /* Set the RA bit according to ETH ReceiveAll value */
\r
1491 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
\r
1492 /* Set the PCF bit according to ETH PassControlFrames value */
\r
1493 /* Set the DBF bit according to ETH BroadcastFramesReception value */
\r
1494 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
\r
1495 /* Set the PR bit according to ETH PromiscuousMode value */
\r
1496 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
\r
1497 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
\r
1498 /* Write to ETHERNET MACFFR */
\r
1499 heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll |
\r
1500 macinit.SourceAddrFilter |
\r
1501 macinit.PassControlFrames |
\r
1502 macinit.BroadcastFramesReception |
\r
1503 macinit.DestinationAddrFilter |
\r
1504 macinit.PromiscuousMode |
\r
1505 macinit.MulticastFramesFilter |
\r
1506 macinit.UnicastFramesFilter);
\r
1508 /* Wait until the write operation will be taken into account:
\r
1509 at least four TX_CLK/RX_CLK clock cycles */
\r
1510 tmpreg = heth->Instance->MACFFR;
\r
1511 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1512 heth->Instance->MACFFR = tmpreg;
\r
1514 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
\r
1515 /* Write to ETHERNET MACHTHR */
\r
1516 heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh;
\r
1518 /* Write to ETHERNET MACHTLR */
\r
1519 heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow;
\r
1520 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
\r
1522 /* Get the ETHERNET MACFCR value */
\r
1523 tmpreg = heth->Instance->MACFCR;
\r
1524 /* Clear xx bits */
\r
1525 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
1527 /* Set the PT bit according to ETH PauseTime value */
\r
1528 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
\r
1529 /* Set the PLT bit according to ETH PauseLowThreshold value */
\r
1530 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
\r
1531 /* Set the RFE bit according to ETH ReceiveFlowControl value */
\r
1532 /* Set the TFE bit according to ETH TransmitFlowControl value */
\r
1533 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
\r
1534 macinit.ZeroQuantaPause |
\r
1535 macinit.PauseLowThreshold |
\r
1536 macinit.UnicastPauseFrameDetect |
\r
1537 macinit.ReceiveFlowControl |
\r
1538 macinit.TransmitFlowControl);
\r
1540 /* Write to ETHERNET MACFCR */
\r
1541 prvWriteMACFCR( heth, tmpreg );
\r
1543 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
\r
1544 /* Set the ETV bit according to ETH VLANTagComparison value */
\r
1545 /* Set the VL bit according to ETH VLANTagIdentifier value */
\r
1546 heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
\r
1547 macinit.VLANTagIdentifier);
\r
1549 /* Wait until the write operation will be taken into account:
\r
1550 at least four TX_CLK/RX_CLK clock cycles */
\r
1551 tmpreg = heth->Instance->MACVLANTR;
\r
1552 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1553 heth->Instance->MACVLANTR = tmpreg;
\r
1555 /* Ethernet DMA default initialization ************************************/
\r
1556 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
\r
1557 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
\r
1558 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
\r
1559 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
\r
1560 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
\r
1561 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
\r
1562 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
\r
1563 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
\r
1564 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
\r
1565 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
\r
1566 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
\r
1567 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
\r
1568 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
\r
1569 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
\r
1570 dmainit.DescriptorSkipLength = 0x0;
\r
1571 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
\r
1573 /* Get the ETHERNET DMAOMR value */
\r
1574 tmpreg = heth->Instance->DMAOMR;
\r
1575 /* Clear xx bits */
\r
1576 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
1578 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
\r
1579 /* Set the RSF bit according to ETH ReceiveStoreForward value */
\r
1580 /* Set the DFF bit according to ETH FlushReceivedFrame value */
\r
1581 /* Set the TSF bit according to ETH TransmitStoreForward value */
\r
1582 /* Set the TTC bit according to ETH TransmitThresholdControl value */
\r
1583 /* Set the FEF bit according to ETH ForwardErrorFrames value */
\r
1584 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
\r
1585 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
\r
1586 /* Set the OSF bit according to ETH SecondFrameOperate value */
\r
1587 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
\r
1588 dmainit.ReceiveStoreForward |
\r
1589 dmainit.FlushReceivedFrame |
\r
1590 dmainit.TransmitStoreForward |
\r
1591 dmainit.TransmitThresholdControl |
\r
1592 dmainit.ForwardErrorFrames |
\r
1593 dmainit.ForwardUndersizedGoodFrames |
\r
1594 dmainit.ReceiveThresholdControl |
\r
1595 dmainit.SecondFrameOperate);
\r
1597 /* Write to ETHERNET DMAOMR */
\r
1598 prvWriteDMAOMR( heth, tmpreg );
\r
1600 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
\r
1601 /* Set the AAL bit according to ETH AddressAlignedBeats value */
\r
1602 /* Set the FB bit according to ETH FixedBurst value */
\r
1603 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
\r
1604 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
\r
1605 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
\r
1606 /* Set the DSL bit according to ETH DesciptorSkipLength value */
\r
1607 /* Set the PR and DA bits according to ETH DMAArbitration value */
\r
1608 heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
\r
1609 dmainit.FixedBurst |
\r
1610 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
1611 dmainit.TxDMABurstLength |
\r
1612 dmainit.EnhancedDescriptorFormat |
\r
1613 (dmainit.DescriptorSkipLength << 2) |
\r
1614 dmainit.DMAArbitration |
\r
1615 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
1617 /* Wait until the write operation will be taken into account:
\r
1618 at least four TX_CLK/RX_CLK clock cycles */
\r
1619 tmpreg = heth->Instance->DMABMR;
\r
1620 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1621 heth->Instance->DMABMR = tmpreg;
\r
1623 if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)
\r
1625 /* Enable the Ethernet Rx Interrupt */
\r
1626 __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
\r
1629 /* Initialize MAC address in ethernet MAC */
\r
1630 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
\r
1634 * @brief Configures the selected MAC address.
\r
1635 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1636 * the configuration information for ETHERNET module
\r
1637 * @param MacAddr: The MAC address to configure
\r
1638 * This parameter can be one of the following values:
\r
1639 * @arg ETH_MAC_Address0: MAC Address0
\r
1640 * @arg ETH_MAC_Address1: MAC Address1
\r
1641 * @arg ETH_MAC_Address2: MAC Address2
\r
1642 * @arg ETH_MAC_Address3: MAC Address3
\r
1643 * @param Addr: Pointer to MAC address buffer data (6 bytes)
\r
1644 * @retval HAL status
\r
1646 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
\r
1650 /* Check the parameters */
\r
1651 assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );
\r
1653 /* Calculate the selected MAC address high register */
\r
1654 tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];
\r
1655 /* Load the selected MAC address high register */
\r
1656 ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;
\r
1657 /* Calculate the selected MAC address low register */
\r
1658 tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ];
\r
1660 /* Load the selected MAC address low register */
\r
1661 ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg;
\r
1665 * @brief Enables the MAC transmission.
\r
1666 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1667 * the configuration information for ETHERNET module
\r
1670 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
\r
1672 uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE;
\r
1674 prvWriteMACCR( heth, tmpreg );
\r
1678 * @brief Disables the MAC transmission.
\r
1679 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1680 * the configuration information for ETHERNET module
\r
1683 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
\r
1685 uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE );
\r
1687 prvWriteMACCR( heth, tmpreg );
\r
1691 * @brief Enables the MAC reception.
\r
1692 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1693 * the configuration information for ETHERNET module
\r
1696 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
\r
1698 __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE;
\r
1700 prvWriteMACCR( heth, tmpreg );
\r
1704 * @brief Disables the MAC reception.
\r
1705 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1706 * the configuration information for ETHERNET module
\r
1709 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
\r
1711 __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE );
\r
1713 prvWriteMACCR( heth, tmpreg );
\r
1717 * @brief Enables the DMA transmission.
\r
1718 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1719 * the configuration information for ETHERNET module
\r
1722 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
\r
1724 /* Enable the DMA transmission */
\r
1725 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST;
\r
1727 prvWriteDMAOMR( heth, tmpreg );
\r
1731 * @brief Disables the DMA transmission.
\r
1732 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1733 * the configuration information for ETHERNET module
\r
1736 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
\r
1738 /* Disable the DMA transmission */
\r
1739 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST );
\r
1741 prvWriteDMAOMR( heth, tmpreg );
\r
1745 * @brief Enables the DMA reception.
\r
1746 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1747 * the configuration information for ETHERNET module
\r
1750 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
\r
1752 /* Enable the DMA reception */
\r
1753 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR;
\r
1755 prvWriteDMAOMR( heth, tmpreg );
\r
1759 * @brief Disables the DMA reception.
\r
1760 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1761 * the configuration information for ETHERNET module
\r
1764 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
\r
1766 /* Disable the DMA reception */
\r
1767 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR );
\r
1769 prvWriteDMAOMR( heth, tmpreg );
\r
1773 * @brief Clears the ETHERNET transmit FIFO.
\r
1774 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1775 * the configuration information for ETHERNET module
\r
1778 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
\r
1780 /* Set the Flush Transmit FIFO bit */
\r
1781 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF;
\r
1783 prvWriteDMAOMR( heth, tmpreg );
\r
1789 #endif /* stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 */
\r
1791 #endif /* HAL_ETH_MODULE_ENABLED */
\r
1800 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r