located. */\r
#define dhcpFIRST_OPTION_BYTE_OFFSET ( 0xf0 )\r
\r
-/* When walking the variable length options field, the following value is used\r
-to ensure the walk has not gone past the end of the valid options. 2 bytes is\r
-made up of the length byte, and minimum one byte value. */\r
-#define dhcpMAX_OPTION_LENGTH_OF_INTEREST ( 2L )\r
-\r
/* Standard DHCP port numbers and magic cookie value. */\r
#if( ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN )\r
#define dhcpCLIENT_PORT 0x4400u\r
/* Walk through the options until the dhcpOPTION_END_BYTE byte\r
is found, taking care not to walk off the end of the options. */\r
pucByte = &( pxDHCPMessage->ucFirstOptionByte );\r
- pucLastByte = &( pucUDPPayload[ lBytes - dhcpMAX_OPTION_LENGTH_OF_INTEREST ] );\r
+ /* Maintain a pointer to the last valid byte (i.e. not the first\r
+ invalid byte). */\r
+ pucLastByte = pucUDPPayload + lBytes - 1;\r
\r
- while( pucByte < pucLastByte )\r
+ while( pucByte <= pucLastByte )\r
{\r
ucOptionCode = pucByte[ 0 ];\r
if( ucOptionCode == dhcpOPTION_END_BYTE )\r
}\r
\r
/* Stop if the response is malformed. */\r
- if( pucByte < pucLastByte - 1 )\r
+ if( pucByte < pucLastByte )\r
{\r
+ /* There are at least two bytes left. */\r
ucLength = pucByte[ 1 ];\r
pucByte += 2;\r
\r
- if( pucByte >= pucLastByte - ucLength )\r
+ if( pucByte + ucLength > pucLastByte )\r
{\r
break;\r
}\r
FreeRTOS_debug_printf( ( "vDHCPProcess: reply %lxip\n", FreeRTOS_ntohl( xDHCPData.ulOfferedIPAddress ) ) );\r
iptraceSENDING_DHCP_REQUEST();\r
\r
- if( FreeRTOS_sendto( xDHCPData.xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( DHCPMessage_t ) + xOptionsLength ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 )\r
+ /* 'ucFirstOptionByte' is part of DHCP message struct, so subtract one byte. */\r
+ if( FreeRTOS_sendto( xDHCPData.xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( DHCPMessage_t ) + xOptionsLength - 1 ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 )\r
{\r
/* The packet was not successfully queued for sending and must be\r
returned to the stack. */\r
FreeRTOS_debug_printf( ( "vDHCPProcess: discover\n" ) );\r
iptraceSENDING_DHCP_DISCOVER();\r
\r
- if( FreeRTOS_sendto( xDHCPData.xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( DHCPMessage_t ) + xOptionsLength ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 )\r
+ /* 'ucFirstOptionByte' is part of DHCP message struct, so subtract one byte. */\r
+ if( FreeRTOS_sendto( xDHCPData.xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( DHCPMessage_t ) + xOptionsLength - 1 ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 )\r
{\r
/* The packet was not successfully queued for sending and must be\r
returned to the stack. */\r
} DNSCacheRow_t;\r
\r
static DNSCacheRow_t xDNSCache[ ipconfigDNS_CACHE_ENTRIES ];\r
+\r
+ void FreeRTOS_dnsclear()\r
+ {\r
+ memset( xDNSCache, 0x0, sizeof( xDNSCache ) );\r
+ }\r
#endif /* ipconfigUSE_DNS_CACHE == 1 */\r
\r
#if( ipconfigUSE_LLMNR == 1 )\r
\r
uint32_t ulDNSHandlePacket( NetworkBufferDescriptor_t *pxNetworkBuffer )\r
{\r
-uint8_t *pucUDPPayloadBuffer;\r
-size_t xPlayloadBufferLength;\r
DNSMessage_t *pxDNSMessageHeader;\r
\r
- xPlayloadBufferLength = pxNetworkBuffer->xDataLength - sizeof( UDPPacket_t );\r
- if ( xPlayloadBufferLength < sizeof( DNSMessage_t ) )\r
+ if( pxNetworkBuffer->xDataLength >= sizeof( DNSMessage_t ) )\r
{\r
- return pdFAIL;\r
- }\r
-\r
- pucUDPPayloadBuffer = pxNetworkBuffer->pucEthernetBuffer + sizeof( UDPPacket_t );\r
- pxDNSMessageHeader = ( DNSMessage_t * ) pucUDPPayloadBuffer;\r
+ pxDNSMessageHeader = \r
+ ( DNSMessage_t * )( pxNetworkBuffer->pucEthernetBuffer + sizeof( UDPPacket_t ) );\r
\r
- if( pxNetworkBuffer->xDataLength > sizeof( UDPPacket_t ) )\r
- {\r
- prvParseDNSReply( pucUDPPayloadBuffer,\r
- xPlayloadBufferLength,\r
- ( uint32_t )pxDNSMessageHeader->usIdentifier );\r
+ prvParseDNSReply( ( uint8_t * )pxDNSMessageHeader,\r
+ pxNetworkBuffer->xDataLength,\r
+ ( uint32_t )pxDNSMessageHeader->usIdentifier );\r
}\r
\r
/* The packet was not consumed. */\r
UDPPacket_t *pxUDPPacket = ( UDPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer;\r
uint8_t *pucUDPPayloadBuffer = pxNetworkBuffer->pucEthernetBuffer + sizeof( UDPPacket_t );\r
\r
- if( pxNetworkBuffer->xDataLength > sizeof( UDPPacket_t) )\r
- {\r
- prvTreatNBNS( pucUDPPayloadBuffer,\r
- pxNetworkBuffer->xDataLength - sizeof( UDPPacket_t ),\r
- pxUDPPacket->xIPHeader.ulSourceIPAddress );\r
- }\r
+ /* The network buffer data length has already been set to the \r
+ length of the UDP payload. */\r
+ prvTreatNBNS( pucUDPPayloadBuffer,\r
+ pxNetworkBuffer->xDataLength,\r
+ pxUDPPacket->xIPHeader.ulSourceIPAddress );\r
\r
/* The packet was not consumed. */\r
return pdFAIL;\r
pxUDPHeader->usLength = FreeRTOS_htons( lNetLength + ipSIZE_OF_UDP_HEADER );\r
vFlip_16( pxUDPPacket->xUDPHeader.usSourcePort, pxUDPPacket->xUDPHeader.usDestinationPort );\r
\r
+ /* Important: tell NIC driver how many bytes must be sent */\r
+ pxNetworkBuffer->xDataLength = ( size_t ) ( lNetLength + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_UDP_HEADER + ipSIZE_OF_ETH_HEADER );\r
+\r
#if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 )\r
{\r
/* calculate the IP header checksum */\r
pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum );\r
\r
/* calculate the UDP checksum for outgoing package */\r
- usGenerateProtocolChecksum( ( uint8_t* ) pxUDPPacket, lNetLength, pdTRUE );\r
+ usGenerateProtocolChecksum( ( uint8_t* ) pxUDPPacket, pxNetworkBuffer->xDataLength, pdTRUE );\r
}\r
#endif\r
\r
- /* Important: tell NIC driver how many bytes must be sent */\r
- pxNetworkBuffer->xDataLength = ( size_t ) ( lNetLength + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_UDP_HEADER + ipSIZE_OF_ETH_HEADER );\r
-\r
/* This function will fill in the eth addresses and send the packet */\r
vReturnEthernetFrame( pxNetworkBuffer, pdFALSE );\r
}\r
BaseType_t xFound = pdFALSE;\r
uint32_t ulCurrentTimeSeconds = ( xTaskGetTickCount() / portTICK_PERIOD_MS ) / 1000;\r
static BaseType_t xFreeEntry = 0;\r
+ configASSERT(pcName);\r
+\r
\r
/* For each entry in the DNS cache table. */\r
for( x = 0; x < ipconfigDNS_CACHE_ENTRIES; x++ )\r
{\r
if( xDNSCache[ x ].pcName[ 0 ] == 0 )\r
{\r
- break;\r
+ continue;\r
}\r
\r
if( 0 == strcmp( xDNSCache[ x ].pcName, pcName ) )\r
\r
/* Provide access to private members for testing. */\r
#ifdef AMAZON_FREERTOS_ENABLE_UNIT_TESTS\r
- #include "aws_freertos_tcp_test_access_dns_define.h"\r
+ #include "iot_freertos_tcp_test_access_dns_define.h"\r
#endif\r
\r
{\r
return ipINVALID_LENGTH;\r
}\r
- if( uxBufferLength < FreeRTOS_ntohs( pxIPPacket->xIPHeader.usLength ) )\r
+ if( uxBufferLength < ( size_t ) ( ipSIZE_OF_ETH_HEADER + FreeRTOS_ntohs( pxIPPacket->xIPHeader.usLength ) ) )\r
{\r
return ipINVALID_LENGTH;\r
}\r
}\r
#endif\r
/*-----------------------------------------------------------*/\r
+\r
+/* Provide access to private members for verification. */\r
+#ifdef FREERTOS_TCP_ENABLE_VERIFICATION\r
+ #include "aws_freertos_ip_verification_access_ip_define.h"\r
+#endif\r
+\r
#define socketNEXT_UDP_PORT_NUMBER_INDEX 0\r
#define socketNEXT_TCP_PORT_NUMBER_INDEX 1\r
\r
+/* Some helper macro's for defining the 20/80 % limits of uxLittleSpace / uxEnoughSpace. */\r
+#define sock20_PERCENT 20\r
+#define sock80_PERCENT 80\r
+#define sock100_PERCENT 100\r
+\r
\r
/*-----------------------------------------------------------*/\r
\r
break;\r
#endif /* ipconfigSOCKET_HAS_USER_WAKE_CALLBACK */\r
\r
+ case FREERTOS_SO_SET_LOW_HIGH_WATER:\r
+ {\r
+ LowHighWater_t *pxLowHighWater = ( LowHighWater_t * ) pvOptionValue;\r
+\r
+ if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP )\r
+ {\r
+ /* It is not allowed to access 'pxSocket->u.xTCP'. */\r
+ FreeRTOS_debug_printf( ( "FREERTOS_SO_SET_LOW_HIGH_WATER: wrong socket type\n" ) );\r
+ break; /* will return -pdFREERTOS_ERRNO_EINVAL */\r
+ }\r
+ if( ( pxLowHighWater->uxLittleSpace >= pxLowHighWater->uxEnoughSpace ) ||\r
+ ( pxLowHighWater->uxEnoughSpace > pxSocket->u.xTCP.uxRxStreamSize ) )\r
+ {\r
+ /* Impossible values. */\r
+ FreeRTOS_debug_printf( ( "FREERTOS_SO_SET_LOW_HIGH_WATER: bad values\n" ) );\r
+ break; /* will return -pdFREERTOS_ERRNO_EINVAL */\r
+ }\r
+ /* Send a STOP when buffer space drops below 'uxLittleSpace' bytes. */\r
+ pxSocket->u.xTCP.uxLittleSpace = pxLowHighWater->uxLittleSpace;\r
+ /* Send a GO when buffer space grows above 'uxEnoughSpace' bytes. */\r
+ pxSocket->u.xTCP.uxEnoughSpace = pxLowHighWater->uxEnoughSpace;\r
+ xReturn = 0;\r
+ }\r
+ break;\r
+\r
case FREERTOS_SO_SNDBUF: /* Set the size of the send buffer, in units of MSS (TCP only) */\r
case FREERTOS_SO_RCVBUF: /* Set the size of the receive buffer, in units of MSS (TCP only) */\r
{\r
}\r
\r
pxProps = ( ( WinProperties_t * ) pvOptionValue );\r
- FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDBUF, &( pxProps->lTxBufSize ), sizeof( pxProps->lTxBufSize ) );\r
- FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVBUF, &( pxProps->lRxBufSize ), sizeof( pxProps->lRxBufSize ) );\r
+\r
+ if ( FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDBUF, &( pxProps->lTxBufSize ), sizeof( pxProps->lTxBufSize ) ) != 0 )\r
+ {\r
+ break; /* will return -pdFREERTOS_ERRNO_EINVAL */\r
+ }\r
+\r
+ if ( FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVBUF, &( pxProps->lRxBufSize ), sizeof( pxProps->lRxBufSize ) ) != 0 )\r
+ {\r
+ break; /* will return -pdFREERTOS_ERRNO_EINVAL */\r
+ }\r
+\r
#if( ipconfigUSE_TCP_WIN == 1 )\r
{\r
pxSocket->u.xTCP.uxRxWinSize = ( uint32_t )pxProps->lRxWinSize; /* Fixed value: size of the TCP reception window */\r
{\r
xResult = -pdFREERTOS_ERRNO_ENOMEM;\r
}\r
- else if( pxSocket->u.xTCP.ucTCPState == eCLOSED )\r
+ else if( pxSocket->u.xTCP.ucTCPState == eCLOSED ||\r
+ pxSocket->u.xTCP.ucTCPState == eCLOSE_WAIT ||\r
+ pxSocket->u.xTCP.ucTCPState == eCLOSING )\r
{\r
xResult = -pdFREERTOS_ERRNO_ENOTCONN;\r
}\r
'*pxLength' will contain the number of bytes that may be written. */\r
uint8_t *FreeRTOS_get_tx_head( Socket_t xSocket, BaseType_t *pxLength )\r
{\r
- uint8_t *pucReturn;\r
+ uint8_t *pucReturn = NULL;\r
FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket;\r
- StreamBuffer_t *pxBuffer = pxSocket->u.xTCP.txStream;\r
+ StreamBuffer_t *pxBuffer = NULL;\r
\r
- if( pxBuffer != NULL )\r
- {\r
- BaseType_t xSpace = ( BaseType_t ) uxStreamBufferGetSpace( pxBuffer );\r
- BaseType_t xRemain = ( BaseType_t ) ( pxBuffer->LENGTH - pxBuffer->uxHead );\r
+ *pxLength = 0;\r
\r
- *pxLength = FreeRTOS_min_BaseType( xSpace, xRemain );\r
- pucReturn = pxBuffer->ucArray + pxBuffer->uxHead;\r
- }\r
- else\r
+ /* Confirm that this is a TCP socket before dereferencing structure\r
+ member pointers. */\r
+ if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdFALSE ) == pdTRUE )\r
{\r
- *pxLength = 0;\r
- pucReturn = NULL;\r
+ pxBuffer = pxSocket->u.xTCP.txStream;\r
+ if( pxBuffer != NULL )\r
+ {\r
+ BaseType_t xSpace = ( BaseType_t )uxStreamBufferGetSpace( pxBuffer );\r
+ BaseType_t xRemain = ( BaseType_t )( pxBuffer->LENGTH - pxBuffer->uxHead );\r
+\r
+ *pxLength = FreeRTOS_min_BaseType( xSpace, xRemain );\r
+ pucReturn = pxBuffer->ucArray + pxBuffer->uxHead;\r
+ }\r
}\r
\r
return pucReturn;\r
\r
const struct xSTREAM_BUFFER *FreeRTOS_get_rx_buf( Socket_t xSocket )\r
{\r
- FreeRTOS_Socket_t *pxSocket = (FreeRTOS_Socket_t *)xSocket;\r
+ FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * )xSocket;\r
+ struct xSTREAM_BUFFER *pxReturn = NULL;\r
+\r
+ /* Confirm that this is a TCP socket before dereferencing structure\r
+ member pointers. */\r
+ if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdFALSE ) == pdTRUE )\r
+ {\r
+ pxReturn = pxSocket->u.xTCP.rxStream;\r
+ }\r
\r
- return pxSocket->u.xTCP.rxStream;\r
+ return pxReturn;\r
}\r
\r
#endif /* ipconfigUSE_TCP */\r
\r
if( pxSocket->u.xTCP.uxLittleSpace == 0ul )\r
{\r
- pxSocket->u.xTCP.uxLittleSpace = ( 1ul * pxSocket->u.xTCP.uxRxStreamSize ) / 5u; /*_RB_ Why divide by 5? Can this be changed to a #define? */\r
+ pxSocket->u.xTCP.uxLittleSpace = ( sock20_PERCENT * pxSocket->u.xTCP.uxRxStreamSize ) / sock100_PERCENT;\r
}\r
\r
if( pxSocket->u.xTCP.uxEnoughSpace == 0ul )\r
{\r
- pxSocket->u.xTCP.uxEnoughSpace = ( 4ul * pxSocket->u.xTCP.uxRxStreamSize ) / 5u; /*_RB_ Why multiply by 4? Maybe sock80_PERCENT?*/\r
+ pxSocket->u.xTCP.uxEnoughSpace = ( sock80_PERCENT * pxSocket->u.xTCP.uxRxStreamSize ) / sock100_PERCENT;\r
}\r
}\r
else\r
*/\r
static BaseType_t prvTCPHandleState( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer );\r
\r
+/*\r
+ * Common code for sending a TCP protocol control packet (i.e. no options, no\r
+ * payload, just flags).\r
+ */\r
+static BaseType_t prvTCPSendSpecialPacketHelper( NetworkBufferDescriptor_t *pxNetworkBuffer,\r
+ uint8_t ucTCPFlags );\r
+\r
+/*\r
+ * A "challenge ACK" is as per https://tools.ietf.org/html/rfc5961#section-3.2,\r
+ * case #3. In summary, an RST was received with a sequence number that is\r
+ * unexpected but still within the window.\r
+ */\r
+static BaseType_t prvTCPSendChallengeAck( NetworkBufferDescriptor_t *pxNetworkBuffer );\r
+\r
/*\r
* Reply to a peer with the RST flag on, in case a packet can not be handled.\r
*/\r
}\r
\r
/* Take the minimum of the RX buffer space and the RX window size. */\r
- ulSpace = FreeRTOS_min_uint32( pxSocket->u.xTCP.ulRxCurWinSize, pxTCPWindow->xSize.ulRxWindowLength );\r
+ ulSpace = FreeRTOS_min_uint32( pxTCPWindow->xSize.ulRxWindowLength, ulFrontSpace );\r
\r
if( ( pxSocket->u.xTCP.bits.bLowWater != pdFALSE_UNSIGNED ) || ( pxSocket->u.xTCP.bits.bRxStopped != pdFALSE_UNSIGNED ) )\r
{\r
/* Set the values of usInitMSS / usCurMSS for this socket. */\r
prvSocketSetMSS( pxSocket );\r
\r
- /* For now this is also the advertised window size. */\r
- pxSocket->u.xTCP.ulRxCurWinSize = pxSocket->u.xTCP.usInitMSS;\r
-\r
/* The initial sequence numbers at our side are known. Later\r
vTCPWindowInit() will be called to fill in the peer's sequence numbers, but\r
first wait for a SYN+ACK reply. */\r
TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader;\r
TCPWindow_t *pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow;\r
/* Find out what window size we may advertised. */\r
-uint32_t ulFrontSpace;\r
int32_t lRxSpace;\r
#if( ipconfigUSE_TCP_WIN == 1 )\r
#if( ipconfigTCP_ACK_EARLIER_PACKET == 0 )\r
int32_t lMinLength;\r
#endif\r
#endif\r
- pxSocket->u.xTCP.ulRxCurWinSize = pxTCPWindow->xSize.ulRxWindowLength -\r
- ( pxTCPWindow->rx.ulHighestSequenceNumber - pxTCPWindow->rx.ulCurrentSequenceNumber );\r
-\r
- /* Free space in rxStream. */\r
- if( pxSocket->u.xTCP.rxStream != NULL )\r
- {\r
- ulFrontSpace = ( uint32_t ) uxStreamBufferFrontSpace( pxSocket->u.xTCP.rxStream );\r
- }\r
- else\r
- {\r
- ulFrontSpace = ( uint32_t ) pxSocket->u.xTCP.uxRxStreamSize;\r
- }\r
-\r
- pxSocket->u.xTCP.ulRxCurWinSize = FreeRTOS_min_uint32( ulFrontSpace, pxSocket->u.xTCP.ulRxCurWinSize );\r
\r
/* Set the time-out field, so that we'll be called by the IP-task in case no\r
next message will be received. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static BaseType_t prvTCPSendReset( NetworkBufferDescriptor_t *pxNetworkBuffer )\r
+static BaseType_t prvTCPSendSpecialPacketHelper( NetworkBufferDescriptor_t *pxNetworkBuffer, \r
+ uint8_t ucTCPFlags )\r
{\r
- #if( ipconfigIGNORE_UNKNOWN_PACKETS == 0 )\r
+#if( ipconfigIGNORE_UNKNOWN_PACKETS == 0 )\r
{\r
- TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer );\r
- const BaseType_t xSendLength = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + 0u ); /* Plus 0 options. */\r
+ TCPPacket_t *pxTCPPacket = ( TCPPacket_t * )( pxNetworkBuffer->pucEthernetBuffer );\r
+ const BaseType_t xSendLength = ( BaseType_t )\r
+ ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + 0u ); /* Plus 0 options. */\r
\r
- pxTCPPacket->xTCPHeader.ucTCPFlags = ipTCP_FLAG_ACK | ipTCP_FLAG_RST;\r
+ pxTCPPacket->xTCPHeader.ucTCPFlags = ucTCPFlags;\r
pxTCPPacket->xTCPHeader.ucTCPOffset = ( ipSIZE_OF_TCP_HEADER + 0u ) << 2;\r
\r
- prvTCPReturnPacket( NULL, pxNetworkBuffer, ( uint32_t ) xSendLength, pdFALSE );\r
+ prvTCPReturnPacket( NULL, pxNetworkBuffer, ( uint32_t )xSendLength, pdFALSE );\r
}\r
- #endif /* !ipconfigIGNORE_UNKNOWN_PACKETS */\r
+#endif /* !ipconfigIGNORE_UNKNOWN_PACKETS */\r
\r
/* Remove compiler warnings if ipconfigIGNORE_UNKNOWN_PACKETS == 1. */\r
- ( void ) pxNetworkBuffer;\r
+ ( void )pxNetworkBuffer;\r
+ ( void )ucTCPFlags;\r
\r
/* The packet was not consumed. */\r
return pdFAIL;\r
}\r
/*-----------------------------------------------------------*/\r
\r
+static BaseType_t prvTCPSendChallengeAck( NetworkBufferDescriptor_t *pxNetworkBuffer )\r
+{\r
+ return prvTCPSendSpecialPacketHelper( pxNetworkBuffer, ipTCP_FLAG_ACK );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static BaseType_t prvTCPSendReset( NetworkBufferDescriptor_t *pxNetworkBuffer )\r
+{\r
+ return prvTCPSendSpecialPacketHelper( pxNetworkBuffer, \r
+ ipTCP_FLAG_ACK | ipTCP_FLAG_RST );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
static void prvSocketSetMSS( FreeRTOS_Socket_t *pxSocket )\r
{\r
uint32_t ulMSS = ipconfigTCP_MSS;\r
uint16_t xLocalPort;\r
uint32_t ulRemoteIP;\r
uint16_t xRemotePort;\r
+uint32_t ulSequenceNumber;\r
+uint32_t ulAckNumber;\r
BaseType_t xResult = pdPASS;\r
\r
+ configASSERT( pxNetworkBuffer );\r
+ configASSERT( pxNetworkBuffer->pucEthernetBuffer );\r
+\r
/* Check for a minimum packet size. */\r
if( pxNetworkBuffer->xDataLength >= ( ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER ) )\r
{\r
xLocalPort = FreeRTOS_htons( pxTCPPacket->xTCPHeader.usDestinationPort );\r
ulRemoteIP = FreeRTOS_htonl( pxTCPPacket->xIPHeader.ulSourceIPAddress );\r
xRemotePort = FreeRTOS_htons( pxTCPPacket->xTCPHeader.usSourcePort );\r
+ ulSequenceNumber = FreeRTOS_ntohl( pxTCPPacket->xTCPHeader.ulSequenceNumber );\r
+ ulAckNumber = FreeRTOS_ntohl( pxTCPPacket->xTCPHeader.ulAckNr );\r
\r
/* Find the destination socket, and if not found: return a socket listing to\r
the destination PORT. */\r
flag. */\r
if( ( ucTCPFlags & ipTCP_FLAG_RST ) != 0u )\r
{\r
- /* The target socket is not in a listening state, any RST packet\r
- will cause the socket to be closed. */\r
FreeRTOS_debug_printf( ( "TCP: RST received from %lxip:%u for %u\n", ulRemoteIP, xRemotePort, xLocalPort ) );\r
- /* _HT_: should indicate that 'ECONNRESET' must be returned to the used during next API. */\r
- vTCPStateChange( pxSocket, eCLOSED );\r
\r
- /* The packet cannot be handled. */\r
+ /* Implement https://tools.ietf.org/html/rfc5961#section-3.2. */\r
+ if( pxSocket->u.xTCP.ucTCPState == eCONNECT_SYN )\r
+ {\r
+ /* Per the above RFC, "In the SYN-SENT state ... the RST is \r
+ acceptable if the ACK field acknowledges the SYN." */\r
+ if( ulAckNumber == pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber + 1 )\r
+ {\r
+ vTCPStateChange( pxSocket, eCLOSED );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check whether the packet matches the next expected sequence number. */\r
+ if( ulSequenceNumber == pxSocket->u.xTCP.xTCPWindow.rx.ulCurrentSequenceNumber )\r
+ {\r
+ vTCPStateChange( pxSocket, eCLOSED );\r
+ }\r
+ /* Otherwise, check whether the packet is within the receive window. */\r
+ else if( ulSequenceNumber > pxSocket->u.xTCP.xTCPWindow.rx.ulCurrentSequenceNumber &&\r
+ ulSequenceNumber < ( pxSocket->u.xTCP.xTCPWindow.rx.ulCurrentSequenceNumber +\r
+ pxSocket->u.xTCP.xTCPWindow.xSize.ulRxWindowLength ) )\r
+ {\r
+ /* Send a challenge ACK. */\r
+ prvTCPSendChallengeAck( pxNetworkBuffer );\r
+ }\r
+ }\r
+\r
+ /* Otherwise, do nothing. In any case, the packet cannot be handled. */\r
xResult = pdFAIL;\r
}\r
else if( ( ( ucTCPFlags & ipTCP_FLAG_CTRL ) == ipTCP_FLAG_SYN ) && ( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) )\r
\r
/* Provide access to private members for testing. */\r
#ifdef AMAZON_FREERTOS_ENABLE_UNIT_TESTS\r
- #include "aws_freertos_tcp_test_access_tcp_define.h"\r
+ #include "iot_freertos_tcp_test_access_tcp_define.h"\r
+#endif\r
+\r
+/* Provide access to private members for verification. */\r
+#ifdef FREERTOS_TCP_ENABLE_VERIFICATION\r
+ #include "aws_freertos_tcp_verification_access_tcp_define.h"\r
#endif\r
\r
pxWhere->pxPrevious = pxNewListItem;\r
\r
/* Remember which list the item is in. */\r
- pxNewListItem->pvContainer = ( void * ) pxList; /* If this line fails to build then ensure configENABLE_BACKWARD_COMPATIBILITY is set to 1 in FreeRTOSConfig.h. */\r
+ listLIST_ITEM_CONTAINER( pxNewListItem ) = ( void * ) pxList;\r
\r
( pxList->uxNumberOfItems )++;\r
}\r
\r
#if( ipconfigUSE_TCP_WIN == 1 )\r
\r
- void vTCPSegmentCleanup( void )\r
- {\r
- /* Free and clear the TCP segments pointer. This function should only be called\r
- * once FreeRTOS+TCP will no longer be used. No thread-safety is provided for this\r
- * function. */\r
- if( xTCPSegments != NULL )\r
- {\r
- vPortFreeLarge( xTCPSegments );\r
- xTCPSegments = NULL;\r
- }\r
- }\r
+ void vTCPSegmentCleanup( void )\r
+ {\r
+ /* Free and clear the TCP segments pointer. This function should only be called\r
+ * once FreeRTOS+TCP will no longer be used. No thread-safety is provided for this\r
+ * function. */\r
+ if( xTCPSegments != NULL )\r
+ {\r
+ vPortFreeLarge( xTCPSegments );\r
+ xTCPSegments = NULL;\r
+ }\r
+ }\r
\r
#endif /* ipconfgiUSE_TCP_WIN == 1 */\r
/*-----------------------------------------------------------*/\r
{\r
ulSavedSequenceNumber = ulCurrentSequenceNumber;\r
\r
- /* Clean up all sequence received between ulSequenceNumber and ulSequenceNumber + ulLength since they are duplicated.\r
- If the server is forced to retransmit packets several time in a row it might send a batch of concatenated packet for speed.\r
- So we cannot rely on the packets between ulSequenceNumber and ulSequenceNumber + ulLength to be sequential and it is better to just\r
- clean them out. */\r
- do\r
- {\r
- pxFound = xTCPWindowRxConfirm( pxWindow, ulSequenceNumber, ulLength );\r
-\r
- if ( pxFound != NULL )\r
- {\r
- /* Remove it because it will be passed to user directly. */\r
- vTCPWindowFree( pxFound );\r
- }\r
- } while ( pxFound );\r
+ /* Clean up all sequence received between ulSequenceNumber and ulSequenceNumber + ulLength since they are duplicated.\r
+ If the server is forced to retransmit packets several time in a row it might send a batch of concatenated packet for speed.\r
+ So we cannot rely on the packets between ulSequenceNumber and ulSequenceNumber + ulLength to be sequential and it is better to just\r
+ clean them out. */\r
+ do\r
+ {\r
+ pxFound = xTCPWindowRxConfirm( pxWindow, ulSequenceNumber, ulLength );\r
+\r
+ if ( pxFound != NULL )\r
+ {\r
+ /* Remove it because it will be passed to user directly. */\r
+ vTCPWindowFree( pxFound );\r
+ }\r
+ } while ( pxFound );\r
\r
/* Check for following segments that are already in the\r
queue and increment ulCurrentSequenceNumber. */\r
{\r
BaseType_t xReturn = pdPASS;\r
FreeRTOS_Socket_t *pxSocket;\r
+UDPPacket_t *pxUDPPacket;\r
\r
-UDPPacket_t *pxUDPPacket = (UDPPacket_t *) pxNetworkBuffer->pucEthernetBuffer;\r
+ configASSERT( pxNetworkBuffer );\r
+ configASSERT( pxNetworkBuffer->pucEthernetBuffer );\r
\r
+ pxUDPPacket = ( UDPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer;\r
+ \r
/* Caller must check for minimum packet size. */\r
pxSocket = pxUDPSocketLookup( usPort );\r
\r
typedef struct xARP_CACHE_TABLE_ROW\r
{\r
uint32_t ulIPAddress; /* The IP address of an ARP cache entry. */\r
- MACAddress_t xMACAddress; /* The MAC address of an ARP cache entry. */\r
+ MACAddress_t xMACAddress; /* The MAC address of an ARP cache entry. */\r
uint8_t ucAge; /* A value that is periodically decremented but can also be refreshed by active communication. The ARP cache entry is removed if the value reaches zero. */\r
- uint8_t ucValid; /* pdTRUE: xMACAddress is valid, pdFALSE: waiting for ARP reply */\r
+ uint8_t ucValid; /* pdTRUE: xMACAddress is valid, pdFALSE: waiting for ARP reply */\r
} ARPCacheRow_t;\r
\r
typedef enum\r
\r
#if( ipconfigUSE_DNS_CACHE != 0 )\r
\r
+ /* Look for the indicated host name in the DNS cache. Returns the IPv4 \r
+ address if present, or 0x0 otherwise. */\r
uint32_t FreeRTOS_dnslookup( const char *pcHostName );\r
\r
+ /* Remove all entries from the DNS cache. */\r
+ void FreeRTOS_dnsclear();\r
#endif /* ipconfigUSE_DNS_CACHE != 0 */\r
\r
#if( ipconfigDNS_USE_CALLBACKS != 0 )\r
#include "FreeRTOS_TCP_IP.h"\r
#endif\r
\r
+#if( ipconfigSOCKET_HAS_USER_SEMAPHORE == 1 )\r
+ #include "semphr.h"\r
+#endif\r
+\r
#include "event_groups.h"\r
\r
typedef struct xNetworkAddressingParameters\r
FOnConnected_t pxHandleConnected; /* Actually type: typedef void (* FOnConnected_t) (Socket_t xSocket, BaseType_t ulConnected ); */\r
#endif /* ipconfigUSE_CALLBACKS */\r
uint32_t ulWindowSize; /* Current Window size advertised by peer */\r
- uint32_t ulRxCurWinSize; /* Constantly changing: this is the current size available for data reception */\r
size_t uxRxWinSize; /* Fixed value: size of the TCP reception window */\r
size_t uxTxWinSize; /* Fixed value: size of the TCP transmit window */\r
\r
#define FREERTOS_SO_WAKEUP_CALLBACK ( 17 )\r
#endif\r
\r
+#define FREERTOS_SO_SET_LOW_HIGH_WATER ( 18 )\r
\r
#define FREERTOS_NOT_LAST_IN_FRAGMENTED_PACKET ( 0x80 ) /* For internal use only, but also part of an 8-bit bitwise value. */\r
#define FREERTOS_FRAGMENTED_PACKET ( 0x40 ) /* For internal use only, but also part of an 8-bit bitwise value. */\r
int32_t lRxWinSize; /* Unit: MSS */\r
} WinProperties_t;\r
\r
+typedef struct xLOW_HIGH_WATER {\r
+ /* Structure to pass for the 'FREERTOS_SO_SET_LOW_HIGH_WATER' option */\r
+ size_t uxLittleSpace; /* Send a STOP when buffer space drops below X bytes */\r
+ size_t uxEnoughSpace; /* Send a GO when buffer space grows above X bytes */\r
+} LowHighWater_t;\r
+\r
/* For compatibility with the expected Berkeley sockets naming. */\r
#define socklen_t uint32_t\r
\r
NetworkBufferDescriptor_t *pxReturn = NULL;\r
size_t uxCount;\r
\r
- if( ( xRequestedSizeBytes != 0u ) && ( xRequestedSizeBytes < ( size_t ) baMINIMAL_BUFFER_SIZE ) )\r
+ if( xNetworkBufferSemaphore != NULL )\r
{\r
- /* ARP packets can replace application packets, so the storage must be\r
- at least large enough to hold an ARP. */\r
- xRequestedSizeBytes = baMINIMAL_BUFFER_SIZE;\r
- }\r
-\r
- /* Add 2 bytes to xRequestedSizeBytes and round up xRequestedSizeBytes\r
- to the nearest multiple of N bytes, where N equals 'sizeof( size_t )'. */\r
- xRequestedSizeBytes += 2u;\r
- if( ( xRequestedSizeBytes & ( sizeof( size_t ) - 1u ) ) != 0u )\r
- {\r
- xRequestedSizeBytes = ( xRequestedSizeBytes | ( sizeof( size_t ) - 1u ) ) + 1u;\r
- }\r
-\r
- /* If there is a semaphore available, there is a network buffer available. */\r
- if( xSemaphoreTake( xNetworkBufferSemaphore, xBlockTimeTicks ) == pdPASS )\r
- {\r
- /* Protect the structure as it is accessed from tasks and interrupts. */\r
- taskENTER_CRITICAL();\r
+ if( ( xRequestedSizeBytes != 0u ) && ( xRequestedSizeBytes < ( size_t ) baMINIMAL_BUFFER_SIZE ) )\r
{\r
- pxReturn = ( NetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList );\r
- uxListRemove( &( pxReturn->xBufferListItem ) );\r
+ /* ARP packets can replace application packets, so the storage must be\r
+ at least large enough to hold an ARP. */\r
+ xRequestedSizeBytes = baMINIMAL_BUFFER_SIZE;\r
}\r
- taskEXIT_CRITICAL();\r
-\r
- /* Reading UBaseType_t, no critical section needed. */\r
- uxCount = listCURRENT_LIST_LENGTH( &xFreeBuffersList );\r
\r
- if( uxMinimumFreeNetworkBuffers > uxCount )\r
+ /* Add 2 bytes to xRequestedSizeBytes and round up xRequestedSizeBytes\r
+ to the nearest multiple of N bytes, where N equals 'sizeof( size_t )'. */\r
+ xRequestedSizeBytes += 2u;\r
+ if( ( xRequestedSizeBytes & ( sizeof( size_t ) - 1u ) ) != 0u )\r
{\r
- uxMinimumFreeNetworkBuffers = uxCount;\r
+ xRequestedSizeBytes = ( xRequestedSizeBytes | ( sizeof( size_t ) - 1u ) ) + 1u;\r
}\r
\r
- /* Allocate storage of exactly the requested size to the buffer. */\r
- configASSERT( pxReturn->pucEthernetBuffer == NULL );\r
- if( xRequestedSizeBytes > 0 )\r
+ /* If there is a semaphore available, there is a network buffer available. */\r
+ if( xSemaphoreTake( xNetworkBufferSemaphore, xBlockTimeTicks ) == pdPASS )\r
{\r
- /* Extra space is obtained so a pointer to the network buffer can\r
- be stored at the beginning of the buffer. */\r
- pxReturn->pucEthernetBuffer = ( uint8_t * ) pvPortMalloc( xRequestedSizeBytes + ipBUFFER_PADDING );\r
+ /* Protect the structure as it is accessed from tasks and interrupts. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ pxReturn = ( NetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList );\r
+ uxListRemove( &( pxReturn->xBufferListItem ) );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Reading UBaseType_t, no critical section needed. */\r
+ uxCount = listCURRENT_LIST_LENGTH( &xFreeBuffersList );\r
\r
- if( pxReturn->pucEthernetBuffer == NULL )\r
+ if( uxMinimumFreeNetworkBuffers > uxCount )\r
{\r
- /* The attempt to allocate storage for the buffer payload failed,\r
- so the network buffer structure cannot be used and must be\r
- released. */\r
- vReleaseNetworkBufferAndDescriptor( pxReturn );\r
- pxReturn = NULL;\r
+ uxMinimumFreeNetworkBuffers = uxCount;\r
}\r
- else\r
+\r
+ /* Allocate storage of exactly the requested size to the buffer. */\r
+ configASSERT( pxReturn->pucEthernetBuffer == NULL );\r
+ if( xRequestedSizeBytes > 0 )\r
{\r
- /* Store a pointer to the network buffer structure in the\r
- buffer storage area, then move the buffer pointer on past the\r
- stored pointer so the pointer value is not overwritten by the\r
- application when the buffer is used. */\r
- *( ( NetworkBufferDescriptor_t ** ) ( pxReturn->pucEthernetBuffer ) ) = pxReturn;\r
- pxReturn->pucEthernetBuffer += ipBUFFER_PADDING;\r
-\r
- /* Store the actual size of the allocated buffer, which may be\r
- greater than the original requested size. */\r
- pxReturn->xDataLength = xRequestedSizeBytes;\r
-\r
- #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )\r
+ /* Extra space is obtained so a pointer to the network buffer can\r
+ be stored at the beginning of the buffer. */\r
+ pxReturn->pucEthernetBuffer = ( uint8_t * ) pvPortMalloc( xRequestedSizeBytes + ipBUFFER_PADDING );\r
+\r
+ if( pxReturn->pucEthernetBuffer == NULL )\r
+ {\r
+ /* The attempt to allocate storage for the buffer payload failed,\r
+ so the network buffer structure cannot be used and must be\r
+ released. */\r
+ vReleaseNetworkBufferAndDescriptor( pxReturn );\r
+ pxReturn = NULL;\r
+ }\r
+ else\r
{\r
- /* make sure the buffer is not linked */\r
- pxReturn->pxNextBuffer = NULL;\r
+ /* Store a pointer to the network buffer structure in the\r
+ buffer storage area, then move the buffer pointer on past the\r
+ stored pointer so the pointer value is not overwritten by the\r
+ application when the buffer is used. */\r
+ *( ( NetworkBufferDescriptor_t ** ) ( pxReturn->pucEthernetBuffer ) ) = pxReturn;\r
+ pxReturn->pucEthernetBuffer += ipBUFFER_PADDING;\r
+\r
+ /* Store the actual size of the allocated buffer, which may be\r
+ greater than the original requested size. */\r
+ pxReturn->xDataLength = xRequestedSizeBytes;\r
+\r
+ #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )\r
+ {\r
+ /* make sure the buffer is not linked */\r
+ pxReturn->pxNextBuffer = NULL;\r
+ }\r
+ #endif /* ipconfigUSE_LINKED_RX_MESSAGES */\r
}\r
- #endif /* ipconfigUSE_LINKED_RX_MESSAGES */\r
}\r
- }\r
- else\r
- {\r
- /* A descriptor is being returned without an associated buffer being\r
- allocated. */\r
+ else\r
+ {\r
+ /* A descriptor is being returned without an associated buffer being\r
+ allocated. */\r
+ }\r
}\r
}\r
\r
#pragma unpack\r
#endif\r
#endif\r
+#ifdef __RX\r
+ #ifdef __CCRX__\r
+ ;\r
+ #pragma packoption\r
+ #endif\r
+#endif\r
\r
\r
\r
#pragma pack 1\r
#endif\r
#endif\r
+#ifdef __RX\r
+ #ifdef __CCRX__\r
+ #pragma pack\r
+ #endif\r
+#endif\r
\r
\r
\r
configASSERT( xTXDescriptorSemaphore );\r
}\r
/* When returning non-zero, the stack will become active and\r
- start DHCP (in configured) */\r
+ start DHCP (in configured) */\r
return ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0;\r
}\r
/*-----------------------------------------------------------*/\r
+/*\r
+ * FreeRTOS+TCP V2.0.11\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://aws.amazon.com/freertos\r
+ * http://www.FreeRTOS.org\r
+ */\r
+\r
/*\r
* Handling of Ethernet PHY's\r
* PHY's communicate with an EMAC either through\r
\r
#include "phyHandling.h"\r
\r
-#include "eventLogging.h"\r
-\r
#define phyMIN_PHY_ADDRESS 0\r
#define phyMAX_PHY_ADDRESS 31\r
\r
/* Bit fields for 'phyREG_00_BMCR', the 'Basic Mode Control Register'. */\r
#define phyBMCR_FULL_DUPLEX 0x0100u /* Full duplex. */\r
#define phyBMCR_AN_RESTART 0x0200u /* Auto negotiation restart. */\r
+#define phyBMCR_ISOLATE 0x0400u /* 1 = Isolates 0 = Normal operation. */\r
#define phyBMCR_AN_ENABLE 0x1000u /* Enable auto negotiation. */\r
#define phyBMCR_SPEED_100 0x2000u /* Select 100Mbps. */\r
#define phyBMCR_RESET 0x8000u /* Reset the PHY. */\r
case PHY_ID_KSZ8051: // same ID as 8041\r
case PHY_ID_KSZ8081: // same ID as 8041\r
*/\r
+ case PHY_ID_KSZ8081MNXIA:\r
+\r
case PHY_ID_KSZ8863:\r
default:\r
/* Most PHY's have a 1F_PHYSPCS */\r
if( pxPhyObject->xPortCount > 0 )\r
{\r
FreeRTOS_printf( ( "PHY ID %lX\n", pxPhyObject->ulPhyIDs[ 0 ] ) );\r
- eventLogAdd( "PHY ID 0x%lX", pxPhyObject->ulPhyIDs[ 0 ] );\r
}\r
\r
return pxPhyObject->xPortCount;\r
FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );\r
break;\r
}\r
+ /* Block for a while */\r
+ vTaskDelay( pdMS_TO_TICKS( 50ul ) );\r
}\r
\r
/* Clear the reset bits. */\r
}\r
\r
vTaskDelay( pdMS_TO_TICKS( 50ul ) );\r
- eventLogAdd( "PHY reset %d ports", (int)pxPhyObject->xPortCount );\r
+\r
return ulDoneMask;\r
}\r
/*-----------------------------------------------------------*/\r
\r
ulConfig |= phyBMCR_AN_ENABLE;\r
\r
- if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 )\r
+ if( ( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 ) || ( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO ) )\r
{\r
ulConfig |= phyBMCR_SPEED_100;\r
}\r
ulConfig &= ~phyBMCR_SPEED_100;\r
}\r
\r
- if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
+ if( ( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL ) || ( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO ) )\r
{\r
ulConfig |= phyBMCR_FULL_DUPLEX;\r
}\r
}\r
\r
FreeRTOS_printf( ( "+TCP: advertise: %04lX config %04lX\n", ulAdvertise, ulConfig ) );\r
- eventLogAdd( "adv: %04lX config %04lX", ulAdvertise, ulConfig );\r
}\r
\r
/* Keep these values for later use. */\r
- pxPhyObject->ulBCRValue = ulConfig;\r
+ pxPhyObject->ulBCRValue = ulConfig & ~phyBMCR_ISOLATE;\r
pxPhyObject->ulACRValue = ulAdvertise;\r
\r
return 0;\r
pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue | phyBMCR_AN_RESTART );\r
}\r
}\r
-eventLogAdd( "AN start" );\r
xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( 3000UL );\r
vTaskSetTimeOutState( &xTimer );\r
ulDoneMask = 0;\r
if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE )\r
{\r
FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );\r
- eventLogAdd( "ANtimed out");\r
break;\r
}\r
+ vTaskDelay( pdMS_TO_TICKS( 50 ) );\r
}\r
-eventLogAdd( "AN done %02lX / %02lX", ulDoneMask, ulPhyMask );\r
\r
if( ulDoneMask != ( uint32_t)0u )\r
{\r
ulPHYLinkStatus &= ~( phyBMSR_LINK_STATUS );\r
}\r
\r
- if( xHas_1F_PHYSPCS( ulPhyID ) )\r
+ if( ulPhyID == PHY_ID_KSZ8081MNXIA )\r
+ {\r
+ uint32_t ulControlStatus;\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, 0x1E, &ulControlStatus);\r
+ switch( ulControlStatus & 0x07 )\r
+ {\r
+ case 0x01:\r
+ case 0x05:\r
+// [001] = 10BASE-T half-duplex\r
+// [101] = 10BASE-T full-duplex\r
+ /* 10 Mbps. */\r
+ ulRegValue |= phyPHYSTS_SPEED_STATUS;\r
+ break;\r
+ case 0x02:\r
+ case 0x06:\r
+// [010] = 100BASE-TX half-duplex\r
+// [110] = 100BASE-TX full-duplex\r
+ break;\r
+ }\r
+ switch( ulControlStatus & 0x07 )\r
+ {\r
+ case 0x05:\r
+ case 0x06:\r
+// [101] = 10BASE-T full-duplex\r
+// [110] = 100BASE-TX full-duplex\r
+ /* Full duplex. */\r
+ ulRegValue |= phyPHYSTS_DUPLEX_STATUS;\r
+ break;\r
+ case 0x01:\r
+ case 0x02:\r
+// [001] = 10BASE-T half-duplex\r
+// [010] = 100BASE-TX half-duplex\r
+ break;\r
+ }\r
+ }\r
+ else if( xHas_1F_PHYSPCS( ulPhyID ) )\r
{\r
/* 31 RW PHY Special Control Status */\r
uint32_t ulControlStatus;\r
{\r
ulRegValue |= phyPHYSTS_SPEED_STATUS;\r
}\r
-\r
}\r
else\r
{\r
( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half",\r
( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100,\r
( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" ) );\r
- eventLogAdd( "%s duplex %u mbit %s st",\r
- ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half",\r
- ( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100,\r
- ( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" );\r
-{\r
- uint32_t regs[4];\r
- int i,j;\r
- int address = 0x10;\r
- for (i = 0; i < 4; i++)\r
- {\r
- for (j = 0; j < 4; j++)\r
- {\r
- pxPhyObject->fnPhyRead( xPhyAddress, address, regs + j );\r
- address++;\r
- }\r
- eventLogAdd("%04lX %04lX %04lX %04lX",\r
- regs[0], regs[1], regs[2], regs[3]);\r
- }\r
-}\r
if( ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) != ( uint32_t )0u )\r
{\r
pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_FULL;\r
but set a timer to check it later on. */\r
vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );\r
pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
+ {\r
+ if( ( pxPhyObject->ulLinkStatusMask & ulBitMask ) == 0ul )\r
+ {\r
+ pxPhyObject->ulLinkStatusMask |= ulBitMask;\r
+ FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );\r
+ xNeedCheck = pdTRUE;\r
+ }\r
+ }\r
}\r
else if( xTaskCheckForTimeOut( &( pxPhyObject->xLinkStatusTimer ), &( pxPhyObject->xLinkStatusRemaining ) ) != pdFALSE )\r
{\r
pxPhyObject->ulLinkStatusMask &= ~( ulBitMask );\r
}\r
FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );\r
- eventLogAdd( "PHY LS now %02lX", pxPhyObject->ulLinkStatusMask );\r
xNeedCheck = pdTRUE;\r
}\r
}\r
/* For now pdFAIL will be returned. But prvEMACHandlerTask() is running\r
and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */\r
xResult = pdFAIL;\r
- FreeRTOS_printf( ( "Link Status still low\n" ) ) ;\r
}\r
/* When returning non-zero, the stack will become active and\r
start DHCP (in configured) */\r
/* Open a do {} while ( 0 ) loop to be able to call break. */\r
do\r
{\r
- if( xCheckLoopback( pxDescriptor, bReleaseAfterSend ) != 0 )\r
- {\r
- /* The packet has been sent back to the IP-task.\r
- The IP-task will further handle it.\r
- Do not release the descriptor. */\r
- bReleaseAfterSend = pdFALSE;\r
- break;\r
- }\r
#if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )\r
{\r
ProtocolPacket_t *pxPacket;\r
--- /dev/null
+This is a FreeeRTOS+TCP driver that works for both STM32F4xx and STM32F7xx parts.\r
+\r
+The code of stm32fxx_hal_eth.c is based on both drivers as provided by ST.\r
+\r
+These modules should be included:\r
+\r
+ NetworkInterface.c\r
+ stm32fxx_hal_eth.c\r
+\r
+It is assumed that one of these words are defined:\r
+\r
+ STM32F7xx\r
+ STM32F407xx\r
+ STM32F417xx\r
+ STM32F427xx\r
+ STM32F437xx\r
+ STM32F429xx\r
+ STM32F439xx\r
+\r
+The driver has been tested on both Eval and Discovery boards with both STM32F4 and STM32F7.\r
--- /dev/null
+/*\r
+ * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to\r
+ * a single module that works for both parts: "stm32fxx_hal_eth"\r
+ */\r
+\r
+#include "stm32fxx_hal_eth.h"\r
--- /dev/null
+/*\r
+ * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to\r
+ * a single module that works for both parts: "stm32fxx_hal_eth"\r
+ */\r
+\r
+#include "stm32fxx_hal_eth.h"\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32fxx_hal_eth.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 26-June-2015\r
+ * @brief ETH HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Ethernet (ETH) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:\r
+ ETH_HandleTypeDef heth;\r
+\r
+ (#)Fill parameters of Init structure in heth handle\r
+\r
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)\r
+\r
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:\r
+ (##) Enable the Ethernet interface clock using\r
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();\r
+\r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure Ethernet pin-out\r
+ (##) Configure Ethernet NVIC interrupt (IT mode)\r
+\r
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:\r
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process\r
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process\r
+\r
+ (#)Enable MAC and DMA transmission and reception:\r
+ (##) HAL_ETH_Start();\r
+\r
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer\r
+ the frame to MAC TX FIFO:\r
+ (##) HAL_ETH_TransmitFrame();\r
+\r
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received\r
+ frame parameters\r
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)\r
+\r
+ (#) Get a received frame when an ETH RX interrupt occurs:\r
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)\r
+\r
+ (#) Communicate with external PHY device:\r
+ (##) Read a specific register from the PHY\r
+ HAL_ETH_ReadPHYRegister();\r
+ (##) Write data to a specific RHY register:\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ (#) Configure the Ethernet MAC after ETH peripheral initialization\r
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.\r
+\r
+ (#) Configure the Ethernet DMA after ETH peripheral initialization\r
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.\r
+\r
+ -@- The PTP protocol and the DMA descriptors ring mode are not supported\r
+ in this driver\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#define __STM32_HAL_LEGACY 1\r
+\r
+#if defined(STM32F7xx)\r
+ #include "stm32f7xx_hal.h"\r
+ #include "stm32f7xx_hal_def.h"\r
+ #define stm_is_F7 1\r
+#elif defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
+ #include "stm32f4xx_hal.h"\r
+ #include "stm32f4xx_hal_def.h"\r
+ #define stm_is_F4 1\r
+#elif defined(STM32F2xx)\r
+ #include "stm32f2xx_hal.h"\r
+ #include "stm32f2xx_hal_def.h"\r
+ #define stm_is_F2 1\r
+#else\r
+ #error For what part should this be compiled?\r
+#endif\r
+\r
+#include "stm32fxx_hal_eth.h"\r
+\r
+/** @addtogroup STM32F4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH ETH\r
+ * @brief ETH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#if !defined( ARRAY_SIZE )\r
+ #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] )\r
+#endif\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+\r
+#if( stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 )\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup ETH_Private_Constants ETH Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup ETH_Private_Functions ETH Private Functions\r
+ * @{\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ETH_Exported_Functions ETH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the Ethernet peripheral\r
+ (+) De-initialize the Ethernet peripheral\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+extern void vMACBProbePhy ( void );\r
+\r
+/**\r
+ * @brief Initializes the Ethernet MAC and DMA according to default\r
+ * parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ uint32_t hclk = 60000000;\r
+ uint32_t err = ETH_SUCCESS;\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth == NULL )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));\r
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));\r
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));\r
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));\r
+\r
+ if( heth->State == HAL_ETH_STATE_RESET )\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspInit( heth );\r
+ }\r
+\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ /* Select MII or RMII Mode*/\r
+ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);\r
+ SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;\r
+\r
+ /* Ethernet Software reset */\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ /* Also enable EDFE: Enhanced descriptor format enable. */\r
+ heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE;\r
+\r
+ /* Wait for software reset */\r
+ while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ /* If your program hangs here, please check the value of 'ipconfigUSE_RMII'. */\r
+ }\r
+\r
+ /*-------------------------------- MAC Initialization ----------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tmpreg &= ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Get hclk frequency value (168,000,000) */\r
+ hclk = HAL_RCC_GetHCLKFreq();\r
+\r
+ /* Set CR bits depending on hclk value */\r
+ if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) )\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) )\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */\r
+ tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;\r
+ }\r
+ else if((hclk >= 60000000 ) && ( hclk < 100000000 ) )\r
+ {\r
+ /* CSR Clock Range between 60-100 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r
+ }\r
+ else if((hclk >= 100000000 ) && ( hclk < 150000000))\r
+ {\r
+ /* CSR Clock Range between 100-150 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r
+ }\r
+ else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */\r
+ {\r
+ /* CSR Clock Range between 150-168 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;\r
+ }\r
+\r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ heth->Instance->MACMIIAR = (uint32_t)tmpreg;\r
+\r
+ /* Initialise the MACB and set all PHY properties */\r
+ vMACBProbePhy();\r
+\r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the ETH peripheral.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspDeInit( heth );\r
+\r
+ /* Set ETH HAL state to Disabled */\r
+ heth->State= HAL_ETH_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMATxDescTab: Pointer to the first Tx desc list\r
+ * @param TxBuff: Pointer to the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the TxDesc pointer with the first one of the pxDMATable list */\r
+ heth->TxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for( i=0; i < ulBufferCount; i++ )\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable + i;\r
+\r
+ /* Set Second Address Chained bit */\r
+ pxDMADescriptor->Status = ETH_DMATXDESC_TCH;\r
+\r
+ pxDMADescriptor->ControlBufferSize = 0;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy transmissions. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */\r
+ pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < ( ulBufferCount - 1 ) )\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 );\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Transmit Descriptor List Address Register */\r
+ heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMARxDescTab: Pointer to the first Rx desc list\r
+ * @param RxBuff: Pointer to the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the RxDesc pointer with the first one of the pxDMATable list */\r
+ heth->RxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for(i=0; i < ulBufferCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable+i;\r
+\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ pxDMADescriptor->Status = ETH_DMARXDESC_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy reception. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE )\r
+ {\r
+ /* Enable Ethernet DMA Rx Descriptor interrupt */\r
+ pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (ulBufferCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Receive Descriptor List Address Register */\r
+ heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a frame\r
+ HAL_ETH_TransmitFrame();\r
+ (+) Receive a frame\r
+ HAL_ETH_GetReceivedFrame();\r
+ HAL_ETH_GetReceivedFrame_IT();\r
+ (+) Read from an External PHY register\r
+ HAL_ETH_ReadPHYRegister();\r
+ (+) Write to an External PHY register\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ @endverbatim\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an Ethernet frame.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param FrameLength: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r
+{\r
+ uint32_t bufcount = 0, size = 0, i = 0;\r
+ __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc;\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ if( FrameLength == 0 )\r
+ {\r
+ /* Set ETH HAL state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET )\r
+ {\r
+ /* OWN bit set */\r
+ heth->State = HAL_ETH_STATE_BUSY_TX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get the number of needed Tx buffers for the current frame, rounding up. */\r
+ bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE;\r
+\r
+ if (bufcount == 1)\r
+ {\r
+ /* Set LAST and FIRST segment */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;\r
+ /* Set frame size */\r
+ pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 );\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* Point to next descriptor */\r
+ heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ else\r
+ {\r
+ for( i = 0; i < bufcount; i++ )\r
+ {\r
+ /* Clear FIRST and LAST segment bits */\r
+ uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS );\r
+\r
+ if( i == 0 )\r
+ {\r
+ /* Setting the first segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS;\r
+ }\r
+\r
+ /* Program size */\r
+ if (i < (bufcount-1))\r
+ {\r
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r
+ }\r
+ else\r
+ {\r
+ /* Setting the last segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS;\r
+ size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r
+ }\r
+\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* point to next descriptor */\r
+ heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ }\r
+\r
+ __DSB();\r
+\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET )\r
+ {\r
+ heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc;\r
+\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ heth->Instance->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ heth->Instance->DMATPDR = 0;\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Checks for received frames.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth )\r
+{\r
+ return HAL_ETH_GetReceivedFrame( heth );\r
+}\r
+\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth )\r
+{\r
+uint32_t ulCounter = 0;\r
+ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc;\r
+HAL_StatusTypeDef xResult = HAL_ERROR;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Check the ETH state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Scan descriptors owned by CPU */\r
+ while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) )\r
+ {\r
+ uint32_t ulStatus = pxDescriptor->Status;\r
+\r
+ /* Just for security. */\r
+ ulCounter++;\r
+\r
+ if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS )\r
+ {\r
+ /* First segment in frame, but not the last. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL;\r
+ heth->RxFrameInfos.SegCount = 1;\r
+ /* Point to next descriptor. */\r
+ pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr);\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul )\r
+ {\r
+ /* This is an intermediate segment, not first, not last. */\r
+ /* Increment segment count. */\r
+ heth->RxFrameInfos.SegCount++;\r
+ /* Move to the next descriptor. */\r
+ pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr );\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ /* Must be a last segment */\r
+ else\r
+ {\r
+ /* This is the last segment. */\r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if( heth->RxFrameInfos.SegCount == 0 )\r
+ {\r
+ /* Remember the first segment. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ }\r
+\r
+ /* Increment segment count */\r
+ heth->RxFrameInfos.SegCount++;\r
+\r
+ /* Remember the last segment. */\r
+ heth->RxFrameInfos.LSRxDesc = pxDescriptor;\r
+\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ heth->RxFrameInfos.length =\r
+ ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;\r
+\r
+ /* Get the address of the buffer start address */\r
+ heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr;\r
+\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr;\r
+\r
+ /* Return OK status: a packet was received. */\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+#define ETH_DMA_ALL_INTS \\r
+ ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \\r
+ ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \\r
+ ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )\r
+\r
+//#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS\r
+\r
+#define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) )\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t dmasr;\r
+\r
+ dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS;\r
+ heth->Instance->DMASR = dmasr;\r
+\r
+ /* Frame received */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 )\r
+ {\r
+ /* Receive complete callback */\r
+ HAL_ETH_RxCpltCallback( heth );\r
+ }\r
+ /* Frame transmitted */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 )\r
+ {\r
+ /* Transfer complete callback */\r
+ HAL_ETH_TxCpltCallback( heth );\r
+ }\r
+\r
+ /* ETH DMA Error */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 )\r
+ {\r
+ /* Ethernet Error callback */\r
+ HAL_ETH_ErrorCallback( heth );\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Ethernet transfer error callbacks\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Reads a PHY register\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Basic Control Register,\r
+ * PHY_BSR: Transceiver Basic Status Register.\r
+ * More PHY register could be read depending on the used PHY\r
+ * @param RegValue: PHY register value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_RD )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_RD */\r
+ heth->State = HAL_ETH_STATE_BUSY_RD;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII address register value */\r
+ tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ /* Get MACMIIDR value */\r
+ *RegValue = ( uint32_t ) heth->Instance->MACMIIDR;\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @brief Writes to a PHY register.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Control Register.\r
+ * More PHY register could be written depending on the used PHY\r
+ * @param RegValue: the value to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) );\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_WR )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_WR */\r
+ heth->State = HAL_ETH_STATE_BUSY_WR;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII register address value */\r
+ tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Give the value to the MII data register */\r
+ heth->Instance->MACMIIDR = ( uint16_t ) RegValue;\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Enable MAC and DMA transmission and reception.\r
+ HAL_ETH_Start();\r
+ (+) Disable MAC and DMA transmission and reception.\r
+ HAL_ETH_Stop();\r
+ (+) Set the MAC configuration in runtime mode\r
+ HAL_ETH_ConfigMAC();\r
+ (+) Set the DMA configuration in runtime mode\r
+ HAL_ETH_ConfigDMA();\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Enables Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth )\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Enable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionEnable( heth );\r
+\r
+ /* Enable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionEnable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionEnable( heth );\r
+\r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionEnable( heth );\r
+\r
+ /* Set the ETH state to READY*/\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Stop DMA transmission */\r
+ ETH_DMATransmissionDisable( heth );\r
+\r
+ /* Stop DMA reception */\r
+ ETH_DMAReceptionDisable( heth );\r
+\r
+ /* Disable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionDisable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Disable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionDisable( heth );\r
+\r
+ /* Set the ETH state*/\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACFCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACFCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACFCR = ulValue;\r
+}\r
+\r
+static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->DMAOMR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->DMAOMR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->DMAOMR = ulValue;\r
+}\r
+\r
+static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACCR = ulValue;\r
+}\r
+\r
+/**\r
+ * @brief Set ETH MAC Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param macconf: MAC Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));\r
+\r
+ if (macconf != NULL)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));\r
+ assert_param(IS_ETH_JABBER(macconf->Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));\r
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));\r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ macconf->Watchdog |\r
+ macconf->Jabber |\r
+ macconf->InterFrameGap |\r
+ macconf->CarrierSense |\r
+ heth->Init.Speed |\r
+ macconf->ReceiveOwn |\r
+ macconf->LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macconf->ChecksumOffload |\r
+ macconf->RetryTransmission |\r
+ macconf->AutomaticPadCRCStrip |\r
+ macconf->BackOffLimit |\r
+ macconf->DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(\r
+ macconf->ReceiveAll |\r
+ macconf->SourceAddrFilter |\r
+ macconf->PassControlFrames |\r
+ macconf->BroadcastFramesReception |\r
+ macconf->DestinationAddrFilter |\r
+ macconf->PromiscuousMode |\r
+ macconf->MulticastFramesFilter |\r
+ macconf->UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)((\r
+ macconf->PauseTime << 16) |\r
+ macconf->ZeroQuantaPause |\r
+ macconf->PauseLowThreshold |\r
+ macconf->UnicastPauseFrameDetect |\r
+ macconf->ReceiveFlowControl |\r
+ macconf->TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |\r
+ macconf->VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+ }\r
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */\r
+ {\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+\r
+ /* Clear FES and DM bits */\r
+ tmpreg &= ~((uint32_t)0x00004800);\r
+\r
+ tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+ }\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets ETH DMA Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param dmaconf: DMA Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));\r
+ assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));\r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));\r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));\r
+\r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ dmaconf->DropTCPIPChecksumErrorFrame |\r
+ dmaconf->ReceiveStoreForward |\r
+ dmaconf->FlushReceivedFrame |\r
+ dmaconf->TransmitStoreForward |\r
+ dmaconf->TransmitThresholdControl |\r
+ dmaconf->ForwardErrorFrames |\r
+ dmaconf->ForwardUndersizedGoodFrames |\r
+ dmaconf->ReceiveThresholdControl |\r
+ dmaconf->SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/\r
+ heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |\r
+ dmaconf->FixedBurst |\r
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmaconf->TxDMABurstLength |\r
+ dmaconf->EnhancedDescriptorFormat |\r
+ (dmaconf->DescriptorSkipLength << 2) |\r
+ dmaconf->DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+ (+) Get the ETH handle state:\r
+ HAL_ETH_GetState();\r
+\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the ETH HAL state\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL state\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Return ETH state */\r
+ return heth->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures Ethernet MAC and DMA with default parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param err: Ethernet Init error\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)\r
+{\r
+ ETH_MACInitTypeDef macinit;\r
+ ETH_DMAInitTypeDef dmainit;\r
+ uint32_t tmpreg = 0;\r
+\r
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex */\r
+ heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
+\r
+ /* Set Ethernet speed to 100M */\r
+ heth->Init.Speed = ETH_SPEED_100M;\r
+ }\r
+\r
+ /* Ethernet MAC default initialization **************************************/\r
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;\r
+ macinit.Jabber = ETH_JABBER_ENABLE;\r
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;\r
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;\r
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;\r
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;\r
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;\r
+ }\r
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;\r
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;\r
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;\r
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;\r
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;\r
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;\r
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;\r
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;\r
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;\r
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r
+ macinit.HashTableHigh = 0x0;\r
+ macinit.HashTableLow = 0x0;\r
+ macinit.PauseTime = 0x0;\r
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r
+ macinit.VLANTagIdentifier = 0x0;\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH Watchdog value */\r
+ /* Set the JD: bit according to ETH Jabber value */\r
+ /* Set the IFG bit according to ETH InterFrameGap value */\r
+ /* Set the DCRS bit according to ETH CarrierSense value */\r
+ /* Set the FES bit according to ETH Speed value */\r
+ /* Set the DO bit according to ETH ReceiveOwn value */\r
+ /* Set the LM bit according to ETH LoopbackMode value */\r
+ /* Set the DM bit according to ETH Mode value */\r
+ /* Set the IPCO bit according to ETH ChecksumOffload value */\r
+ /* Set the DR bit according to ETH RetryTransmission value */\r
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */\r
+ /* Set the BL bit according to ETH BackOffLimit value */\r
+ /* Set the DC bit according to ETH DeferralCheck value */\r
+ tmpreg |= (uint32_t)(macinit.Watchdog |\r
+ macinit.Jabber |\r
+ macinit.InterFrameGap |\r
+ macinit.CarrierSense |\r
+ heth->Init.Speed |\r
+ macinit.ReceiveOwn |\r
+ macinit.LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macinit.ChecksumOffload |\r
+ macinit.RetryTransmission |\r
+ macinit.AutomaticPadCRCStrip |\r
+ macinit.BackOffLimit |\r
+ macinit.DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Set the RA bit according to ETH ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH PassControlFrames value */\r
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll |\r
+ macinit.SourceAddrFilter |\r
+ macinit.PassControlFrames |\r
+ macinit.BroadcastFramesReception |\r
+ macinit.DestinationAddrFilter |\r
+ macinit.PromiscuousMode |\r
+ macinit.MulticastFramesFilter |\r
+ macinit.UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ /* Set the PT bit according to ETH PauseTime value */\r
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH TransmitFlowControl value */\r
+ tmpreg |= (uint32_t)((macinit.PauseTime << 16) |\r
+ macinit.ZeroQuantaPause |\r
+ macinit.PauseLowThreshold |\r
+ macinit.UnicastPauseFrameDetect |\r
+ macinit.ReceiveFlowControl |\r
+ macinit.TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/\r
+ /* Set the ETV bit according to ETH VLANTagComparison value */\r
+ /* Set the VL bit according to ETH VLANTagIdentifier value */\r
+ heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |\r
+ macinit.VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+\r
+ /* Ethernet DMA default initialization ************************************/\r
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;\r
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;\r
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;\r
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;\r
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;\r
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;\r
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;\r
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;\r
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;\r
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r
+ dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r
+ dmainit.DescriptorSkipLength = 0x0;\r
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r
+\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |\r
+ dmainit.ReceiveStoreForward |\r
+ dmainit.FlushReceivedFrame |\r
+ dmainit.TransmitStoreForward |\r
+ dmainit.TransmitThresholdControl |\r
+ dmainit.ForwardErrorFrames |\r
+ dmainit.ForwardUndersizedGoodFrames |\r
+ dmainit.ReceiveThresholdControl |\r
+ dmainit.SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/\r
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */\r
+ /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/\r
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH DMAArbitration value */\r
+ heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |\r
+ dmainit.FixedBurst |\r
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmainit.TxDMABurstLength |\r
+ dmainit.EnhancedDescriptorFormat |\r
+ (dmainit.DescriptorSkipLength << 2) |\r
+ dmainit.DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable the Ethernet Rx Interrupt */\r
+ __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R);\r
+ }\r
+\r
+ /* Initialize MAC address in ethernet MAC */\r
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param MacAddr: The MAC address to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0: MAC Address0\r
+ * @arg ETH_MAC_Address1: MAC Address1\r
+ * @arg ETH_MAC_Address2: MAC Address2\r
+ * @arg ETH_MAC_Address3: MAC Address3\r
+ * @param Addr: Pointer to MAC address buffer data (6 bytes)\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ /* Check the parameters */\r
+ assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );\r
+\r
+ /* Calculate the selected MAC address high register */\r
+ tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];\r
+ /* Load the selected MAC address high register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;\r
+ /* Calculate the selected MAC address low register */\r
+ tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ];\r
+\r
+ /* Load the selected MAC address low register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the Flush Transmit FIFO bit */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 */\r
+\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32fxx_hal_eth.h\r
+ * @author MCD Application Team\r
+ * @version V1.2.2\r
+ * @date 14-April-2017\r
+ * @brief Header file of ETH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32Fxx_HAL_ETH_H\r
+#define __STM32Fxx_HAL_ETH_H\r
+\r
+/* make sure that the original ETH headers files won't be included after this. */\r
+#define __STM32F2xx_HAL_ETH_H\r
+#define __STM32F4xx_HAL_ETH_H\r
+#define __STM32F7xx_HAL_ETH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** @addtogroup STM32Fxx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\r
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\r
+ ((SPEED) == ETH_SPEED_100M))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\r
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\r
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\r
+ ((CMD) == ETH_WATCHDOG_DISABLE))\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\r
+ ((CMD) == ETH_JABBER_DISABLE))\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\r
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\r
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\r
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\r
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\r
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\r
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEAll_DISABLE))\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\r
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\r
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\r
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\r
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\r
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\r
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\r
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\r
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\r
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\r
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\r
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\r
+ ((CMD) == ETH_FIXEDBURST_DISABLE))\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMATXDESC_IC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LS) || \\r
+ ((FLAG) == ETH_DMATXDESC_FS) || \\r
+ ((FLAG) == ETH_DMATXDESC_DC) || \\r
+ ((FLAG) == ETH_DMATXDESC_DP) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \\r
+ ((FLAG) == ETH_DMATXDESC_TER) || \\r
+ ((FLAG) == ETH_DMATXDESC_TCH) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \\r
+ ((FLAG) == ETH_DMATXDESC_IHE) || \\r
+ ((FLAG) == ETH_DMATXDESC_ES) || \\r
+ ((FLAG) == ETH_DMATXDESC_JT) || \\r
+ ((FLAG) == ETH_DMATXDESC_FF) || \\r
+ ((FLAG) == ETH_DMATXDESC_PCE) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCA) || \\r
+ ((FLAG) == ETH_DMATXDESC_NC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCO) || \\r
+ ((FLAG) == ETH_DMATXDESC_EC) || \\r
+ ((FLAG) == ETH_DMATXDESC_VF) || \\r
+ ((FLAG) == ETH_DMATXDESC_CC) || \\r
+ ((FLAG) == ETH_DMATXDESC_ED) || \\r
+ ((FLAG) == ETH_DMATXDESC_UF) || \\r
+ ((FLAG) == ETH_DMATXDESC_DB))\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\r
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMARXDESC_AFM) || \\r
+ ((FLAG) == ETH_DMARXDESC_ES) || \\r
+ ((FLAG) == ETH_DMARXDESC_DE) || \\r
+ ((FLAG) == ETH_DMARXDESC_SAF) || \\r
+ ((FLAG) == ETH_DMARXDESC_LE) || \\r
+ ((FLAG) == ETH_DMARXDESC_OE) || \\r
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \\r
+ ((FLAG) == ETH_DMARXDESC_FS) || \\r
+ ((FLAG) == ETH_DMARXDESC_LS) || \\r
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARXDESC_LC) || \\r
+ ((FLAG) == ETH_DMARXDESC_FT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RWT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RE) || \\r
+ ((FLAG) == ETH_DMARXDESC_DBE) || \\r
+ ((FLAG) == ETH_DMARXDESC_CE) || \\r
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\r
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\r
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\r
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Defines\r
+ * @{\r
+ */\r
+/* Delay to wait when writing to some Ethernet registers */\r
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)\r
+\r
+/* Ethernet Errors */\r
+#define ETH_SUCCESS ((uint32_t)0U)\r
+#define ETH_ERROR ((uint32_t)1U)\r
+\r
+/* Ethernet DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U)\r
+\r
+/* Ethernet DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Frame length Shift */\r
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet MAC address offsets */\r
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */\r
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */\r
+\r
+/* Ethernet MACMIIAR register Mask */\r
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)\r
+\r
+/* Ethernet MACCR register Mask */\r
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU)\r
+\r
+/* Ethernet MACFCR register Mask */\r
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U)\r
+\r
+/* Ethernet DMAOMR register Mask */\r
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U)\r
+\r
+/* Ethernet Remote Wake-up frame register length */\r
+#define ETH_WAKEUP_REGISTER_LENGTH 8U\r
+\r
+/* Ethernet Missed frames counter Shift */\r
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Types ETH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */\r
+ HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */\r
+ HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
+ HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */\r
+}HAL_ETH_StateTypeDef;\r
+\r
+/**\r
+ * @brief ETH Init Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
+ and the mode (half/full-duplex).\r
+ This parameter can be a value of @ref ETH_AutoNegotiation */\r
+\r
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.\r
+ This parameter can be a value of @ref ETH_Speed */\r
+\r
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
+ This parameter can be a value of @ref ETH_Duplex_Mode */\r
+\r
+ uint16_t PhyAddress; /*!< Ethernet PHY address.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+\r
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r
+\r
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r
+ This parameter can be a value of @ref ETH_Rx_Mode */\r
+\r
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.\r
+ This parameter can be a value of @ref ETH_Checksum_Mode */\r
+\r
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.\r
+ This parameter can be a value of @ref ETH_Media_Interface */\r
+\r
+} ETH_InitTypeDef;\r
+\r
+\r
+ /**\r
+ * @brief ETH MAC Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be received.\r
+ When disabled, the MAC can receive up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Watchdog */\r
+\r
+ uint32_t Jabber; /*!< Selects or not Jabber timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be sent.\r
+ When disabled, the MAC can send up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Jabber */\r
+\r
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.\r
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */\r
+\r
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.\r
+ This parameter can be a value of @ref ETH_Carrier_Sense */\r
+\r
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,\r
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
+ in Half-Duplex mode.\r
+ This parameter can be a value of @ref ETH_Receive_Own */\r
+\r
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.\r
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */\r
+\r
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
+ This parameter can be a value of @ref ETH_Checksum_Offload */\r
+\r
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
+ when a collision occurs (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Retry_Transmission */\r
+\r
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */\r
+\r
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.\r
+ This parameter can be a value of @ref ETH_Back_Off_Limit */\r
+\r
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Deferral_Check */\r
+\r
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).\r
+ This parameter can be a value of @ref ETH_Receive_All */\r
+\r
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.\r
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */\r
+\r
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)\r
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */\r
+\r
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.\r
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
+\r
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.\r
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */\r
+\r
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
+\r
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */\r
+\r
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */\r
+\r
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */\r
+\r
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
+ automatic retransmission of PAUSE Frame.\r
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
+\r
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
+ unicast address and unique multicast address).\r
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */\r
+\r
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
+ disable its transmitter for a specified time (Pause Time)\r
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
+\r
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
+ or the MAC back-pressure operation (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */\r
+\r
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
+ comparison and filtering.\r
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */\r
+\r
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
+\r
+} ETH_MACInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief ETH DMA Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */\r
+\r
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.\r
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */\r
+\r
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.\r
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */\r
+\r
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.\r
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */\r
+\r
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.\r
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
+\r
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.\r
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
+\r
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
+ and length less than 64 bytes) including pad-bytes and CRC)\r
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
+\r
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.\r
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
+\r
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
+ frame of Transmit data even before obtaining the status for the first frame.\r
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
+\r
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.\r
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
+\r
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.\r
+ This parameter can be a value of @ref ETH_Fixed_Burst */\r
+\r
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */\r
+\r
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r
+\r
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.\r
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r
+\r
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+\r
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.\r
+ This parameter can be a value of @ref ETH_DMA_Arbitration */\r
+} ETH_DMAInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief ETH DMA Descriptors data structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t Status; /*!< Status */\r
+\r
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
+\r
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
+\r
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
+\r
+ /*!< Enhanced Ethernet DMA PTP Descriptors */\r
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */\r
+\r
+ uint32_t Reserved1; /*!< Reserved */\r
+\r
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */\r
+\r
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */\r
+\r
+} ETH_DMADescTypeDef;\r
+\r
+\r
+/**\r
+ * @brief Received Frame Informations structure definition\r
+ */\r
+typedef struct\r
+{\r
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */\r
+\r
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */\r
+\r
+ uint32_t SegCount; /*!< Segment count */\r
+\r
+ uint32_t length; /*!< Frame length */\r
+\r
+ uint32_t buffer; /*!< Frame buffer */\r
+\r
+} ETH_DMARxFrameInfos;\r
+\r
+\r
+/**\r
+ * @brief ETH Handle Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ ETH_TypeDef *Instance; /*!< Register base address */\r
+\r
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */\r
+\r
+ uint32_t LinkStatus; /*!< Ethernet link status */\r
+\r
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */\r
+\r
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */\r
+\r
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */\r
+\r
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */\r
+\r
+ HAL_LockTypeDef Lock; /*!< ETH Lock */\r
+\r
+} ETH_HandleTypeDef;\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Constants ETH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Buffers_setting ETH Buffers setting\r
+ * @{\r
+ */\r
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1536U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */\r
+#define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */\r
+#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */\r
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */\r
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */\r
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */\r
+\r
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when\r
+ an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r
+ to the driver receive buffers memory.\r
+\r
+ Depending on the size of the received Ethernet packet and the size of\r
+ each Ethernet driver receive buffer, the received packet can take one or more\r
+ Ethernet driver receive buffer.\r
+\r
+ In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE\r
+ and the total count of the driver receive buffers ETH_RXBUFNB.\r
+\r
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as\r
+ example, they can be reconfigured in the application layer to fit the application\r
+ needs */\r
+\r
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_RX_BUF_SIZE\r
+ #error please define ETH_RX_BUF_SIZE\r
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/\r
+#ifndef ETH_RXBUFNB\r
+ #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#endif\r
+\r
+\r
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r
+ an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the\r
+ driver transmit buffers memory to the TxFIFO.\r
+\r
+ Depending on the size of the Ethernet packet to be transmitted and the size of\r
+ each Ethernet driver transmit buffer, the packet to be transmitted can take\r
+ one or more Ethernet driver transmit buffer.\r
+\r
+ In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE\r
+ and the total count of the driver transmit buffers ETH_TXBUFNB.\r
+\r
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as\r
+ example, they can be reconfigured in the application layer to fit the application\r
+ needs */\r
+\r
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_TX_BUF_SIZE\r
+ #error please define ETH_TX_BUF_SIZE\r
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/\r
+#ifndef ETH_TXBUFNB\r
+ #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */\r
+#endif\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Tx Descriptor\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/**\r
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
+ */\r
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */\r
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */\r
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */\r
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */\r
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */\r
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */\r
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */\r
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */\r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */\r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */\r
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */\r
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */\r
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */\r
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */\r
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */\r
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */\r
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */\r
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */\r
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */\r
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */\r
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */\r
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */\r
+\r
+/**\r
+ * @brief Bit definition of TDES1 register\r
+ */\r
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */\r
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */\r
+\r
+/**\r
+ * @brief Bit definition of TDES2 register\r
+ */\r
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */\r
+\r
+/**\r
+ * @brief Bit definition of TDES3 register\r
+ */\r
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */\r
+\r
+ /*---------------------------------------------------------------------------------------------\r
+ TDES6 | Transmit Time Stamp Low [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES7 | Transmit Time Stamp High [31:0] |\r
+ ----------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of TDES6 register */\r
+ #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */\r
+\r
+/* Bit definition of TDES7 register */\r
+ #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Rx Descriptor\r
+ --------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/**\r
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register\r
+ */\r
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */\r
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */\r
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */\r
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */\r
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */\r
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */\r
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */\r
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */\r
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */\r
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */\r
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */\r
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/**\r
+ * @brief Bit definition of RDES1 register\r
+ */\r
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */\r
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */\r
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */\r
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */\r
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */\r
+\r
+/**\r
+ * @brief Bit definition of RDES2 register\r
+ */\r
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */\r
+\r
+/**\r
+ * @brief Bit definition of RDES3 register\r
+ */\r
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES5 | Reserved[31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES6 | Receive Time Stamp Low [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES7 | Receive Time Stamp High [31:0] |\r
+ --------------------------------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of RDES4 register */\r
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */\r
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */\r
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */\r
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */\r
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */\r
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */\r
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */\r
+ #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */\r
+ #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */\r
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */\r
+\r
+/* Bit definition of RDES6 register */\r
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */\r
+\r
+/* Bit definition of RDES7 register */\r
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */\r
+/**\r
+ * @}\r
+ */\r
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation\r
+ * @{\r
+ */\r
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U)\r
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Speed ETH Speed\r
+ * @{\r
+ */\r
+#define ETH_SPEED_10M ((uint32_t)0x00000000U)\r
+#define ETH_SPEED_100M ((uint32_t)0x00004000U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode\r
+ * @{\r
+ */\r
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U)\r
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Rx_Mode ETH Rx Mode\r
+ * @{\r
+ */\r
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U)\r
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode\r
+ * @{\r
+ */\r
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U)\r
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Media_Interface ETH Media Interface\r
+ * @{\r
+ */\r
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U)\r
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Watchdog ETH Watchdog\r
+ * @{\r
+ */\r
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Jabber ETH Jabber\r
+ * @{\r
+ */\r
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap\r
+ * @{\r
+ */\r
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense\r
+ * @{\r
+ */\r
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Own ETH Receive Own\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode\r
+ * @{\r
+ */\r
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U)\r
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload\r
+ * @{\r
+ */\r
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U)\r
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission\r
+ * @{\r
+ */\r
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip\r
+ * @{\r
+ */\r
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit\r
+ * @{\r
+ */\r
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U)\r
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U)\r
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U)\r
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Deferral_Check ETH Deferral Check\r
+ * @{\r
+ */\r
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U)\r
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_All ETH Receive All\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U)\r
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter\r
+ * @{\r
+ */\r
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U)\r
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U)\r
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames\r
+ * @{\r
+ */\r
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception\r
+ * @{\r
+ */\r
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter\r
+ * @{\r
+ */\r
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U)\r
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode\r
+ * @{\r
+ */\r
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U)\r
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter\r
+ * @{\r
+ */\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U)\r
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U)\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)\r
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter\r
+ * @{\r
+ */\r
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)\r
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U)\r
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause\r
+ * @{\r
+ */\r
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold\r
+ * @{\r
+ */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect\r
+ * @{\r
+ */\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U)\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U)\r
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U)\r
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison\r
+ * @{\r
+ */\r
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U)\r
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses ETH MAC addresses\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)\r
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)\r
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)\r
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U)\r
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags\r
+ * @{\r
+ */\r
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */\r
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame\r
+ * @{\r
+ */\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward\r
+ * @{\r
+ */\r
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U)\r
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame\r
+ * @{\r
+ */\r
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U)\r
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames\r
+ * @{\r
+ */\r
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames\r
+ * @{\r
+ */\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U)\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate\r
+ * @{\r
+ */\r
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U)\r
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats\r
+ * @{\r
+ */\r
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U)\r
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst\r
+ * @{\r
+ */\r
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U)\r
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length\r
+ * @{\r
+ */\r
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length\r
+ * @{\r
+ */\r
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format\r
+ * @{\r
+ */\r
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration\r
+ * @{\r
+ */\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U)\r
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment\r
+ * @{\r
+ */\r
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control\r
+ * @{\r
+ */\r
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */\r
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers\r
+ * @{\r
+ */\r
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */\r
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PMT_Flags ETH PMT Flags\r
+ * @{\r
+ */\r
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Flags ETH MAC Flags\r
+ * @{\r
+ */\r
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Flags ETH DMA Flags\r
+ * @{\r
+ */\r
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */\r
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */\r
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts\r
+ * @{\r
+ */\r
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */\r
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state\r
+ * @{\r
+ */\r
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */\r
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */\r
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */\r
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state\r
+ * @{\r
+ */\r
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */\r
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */\r
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_overflow ETH DMA overflow\r
+ * @{\r
+ */\r
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP\r
+ * @{\r
+ */\r
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Macros ETH Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset ETH handle state\r
+ * @param __HANDLE__: specifies the ETH handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of TDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of RDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))\r
+\r
+/**\r
+ * @brief Disables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)\r
+\r
+/**\r
+ * @brief Set the specified DMA Rx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)\r
+\r
+/**\r
+ * @brief Returns the specified Ethernet DMA Tx Desc collision count.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The Transmit descriptor collision counter value.\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)\r
+\r
+/**\r
+ * @brief Set the specified DMA Tx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)\r
+\r
+/**\r
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass\r
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Enables the specified Ethernet MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Initiate a Pause Control Frame (Full-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the Ethernet flow control busy bit is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The new state of flow control busy status bit (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet MAC flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag\r
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag\r
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag\r
+ * @arg ETH_MAC_FLAG_MMC : MMC flag\r
+ * @arg ETH_MAC_FLAG_PMT : PMT flag\r
+ * @retval The state of Ethernet MAC flag.\r
+ */\r
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified Ethernet DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r
+ * enabled @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r
+ * disabled. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clears the Ethernet DMA IT pending bit.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA flag is set or not.\r
+* @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA overflow flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter\r
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter\r
+ * @retval The state of Ethernet DMA overflow Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))\r
+\r
+/**\r
+ * @brief Set the DMA Receive status watchdog timer register value\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __VALUE__: DMA Receive status watchdog timer register value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))\r
+\r
+/**\r
+ * @brief Enables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Disables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Enables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Disables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)\r
+\r
+/**\r
+ * @brief Disables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Disables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet PMT flag is set or not.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset\r
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received\r
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received\r
+ * @retval The new state of Ethernet PMT Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\\r
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Enables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Disables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Resets the MMC Counters.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)\r
+\r
+/**\r
+ * @brief Enables the specified Ethernet MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Disables the specified Ethernet MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Enables the specified Ethernet MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enable event on ETH External event line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disable event on ETH External event line\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Get flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Clear flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\\r
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\r
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on selected EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup ETH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* IO operation functions ****************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);\r
+/* Communication with PHY functions*/\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);\r
+/* Callback in non blocking modes (Interrupt) */\r
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral State functions ************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32Fxx_HAL_ETH_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
\r
/* _HT_ made the PCAP interface number configurable through the program's\r
parameters in order to test in different machines. */\r
-static BaseType_t xConfigNextworkInterfaceToUse = configNETWORK_INTERFACE_TO_USE;\r
+static BaseType_t xConfigNetworkInterfaceToUse = configNETWORK_INTERFACE_TO_USE;\r
\r
/* Handles to the Windows threads that handle the PCAP IO. */\r
static HANDLE vWinPcapRecvThreadHandle = NULL;\r
printf( "\r\nThe interface that will be opened is set by " );\r
printf( "\"configNETWORK_INTERFACE_TO_USE\", which\r\nshould be defined in FreeRTOSConfig.h\r\n" );\r
\r
- if( ( xConfigNextworkInterfaceToUse < 0L ) || ( xConfigNextworkInterfaceToUse >= lInterfaceNumber ) )\r
+ if( ( xConfigNetworkInterfaceToUse < 1L ) || ( xConfigNetworkInterfaceToUse >= lInterfaceNumber ) )\r
{\r
- printf( "\r\nERROR: configNETWORK_INTERFACE_TO_USE is set to %d, which is an invalid value.\r\n", xConfigNextworkInterfaceToUse );\r
+ printf( "\r\nERROR: configNETWORK_INTERFACE_TO_USE is set to %d, which is an invalid value.\r\n", xConfigNetworkInterfaceToUse );\r
printf( "Please set configNETWORK_INTERFACE_TO_USE to one of the interface numbers listed above,\r\n" );\r
printf( "then re-compile and re-start the application. Only Ethernet (as opposed to WiFi)\r\n" );\r
printf( "interfaces are supported.\r\n\r\nHALTING\r\n\r\n\r\n" );\r
}\r
else\r
{\r
- printf( "Attempting to open interface number %d.\n", xConfigNextworkInterfaceToUse );\r
+ printf( "Attempting to open interface number %d.\n", xConfigNetworkInterfaceToUse );\r
}\r
}\r
\r
\r
static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces )\r
{\r
-pcap_if_t *xInterface;\r
+pcap_if_t *pxInterface;\r
int32_t x;\r
\r
/* Walk the list of devices until the selected device is located. */\r
- xInterface = pxAllNetworkInterfaces;\r
- if (0 == xConfigNextworkInterfaceToUse) {\r
- while (NULL != xInterface) {\r
- xInterface = xInterface->next;\r
- if (0 == prvOpenInterface(xInterface->name)) {\r
- break;\r
- }\r
- }\r
+ pxInterface = pxAllNetworkInterfaces;\r
+ for( x = 0L; x < ( xConfigNetworkInterfaceToUse - 1L ); x++ )\r
+ {\r
+ pxInterface = pxInterface->next;\r
}\r
- else {\r
- for (x = 1L; x < xConfigNextworkInterfaceToUse; x++)\r
- {\r
- xInterface = xInterface->next;\r
- }\r
- /* Open the selected interface. */\r
- (void) prvOpenInterface(xInterface->name);\r
+\r
+ /* Open the selected interface. */\r
+ if( prvOpenInterface( pxInterface->name ) == 0 )\r
+ {\r
+ printf( "Successfully opened interface number %d.\n", x + 1 );\r
+ }\r
+ else\r
+ {\r
+ printf( "Failed to open interface number %d.\n", x + 1 );\r
}\r
\r
/* The device list is no longer required. */\r
{\r
printf( "\nAn error occurred setting the packet filter.\n" );\r
}\r
-\r
+ /* When pcap_compile() succeeds, it allocates memory for the memory pointed to by the bpf_program struct \r
+ parameter.pcap_freecode() will free that memory. */\r
pcap_freecode( &xFilterCode );\r
}\r
\r
\r
iptraceNETWORK_INTERFACE_RECEIVE();\r
\r
- /* Check for minimal size. */\r
- if( pxHeader->len >= sizeof( EthernetHeader_t ) )\r
- {\r
- eResult = ipCONSIDER_FRAME_FOR_PROCESSING( pucPacketData );\r
- }\r
- else\r
- {\r
- eResult = eReleaseBuffer;\r
- }\r
+ /* Check for minimal size. */\r
+ if( pxHeader->len >= sizeof( EthernetHeader_t ) )\r
+ {\r
+ eResult = ipCONSIDER_FRAME_FOR_PROCESSING( pucPacketData );\r
+ }\r
+ else\r
+ {\r
+ eResult = eReleaseBuffer;\r
+ }\r
\r
if( eResult == eProcessBuffer )\r
{\r
\r
return pcBuffer;\r
}\r
-\r
/*\r
-FreeRTOS+TCP V2.0.11\r
-Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
-\r
-Permission is hereby granted, free of charge, to any person obtaining a copy of\r
-this software and associated documentation files (the "Software"), to deal in\r
-the Software without restriction, including without limitation the rights to\r
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
-the Software, and to permit persons to whom the Software is furnished to do so,\r
-subject to the following conditions:\r
-\r
-The above copyright notice and this permission notice shall be included in all\r
-copies or substantial portions of the Software.\r
-\r
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
-COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
-CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-\r
- http://aws.amazon.com/freertos\r
- http://www.FreeRTOS.org\r
+ * FreeRTOS+TCP V2.0.11\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://aws.amazon.com/freertos\r
+ * http://www.FreeRTOS.org\r
*/\r
\r
/* Standard includes. */\r
#include "FreeRTOS_IP.h"\r
#include "FreeRTOS_Sockets.h"\r
#include "FreeRTOS_IP_Private.h"\r
-#include "FreeRTOS_ARP.h"\r
#include "NetworkBufferManagement.h"\r
#include "NetworkInterface.h"\r
\r
#endif\r
\r
#define niBMSR_LINK_STATUS 0x0004UL\r
-#define niBMSR_AN_COMPLETE 0x0020u /* Auto-Negotiation process completed */\r
\r
#ifndef PHY_LS_HIGH_CHECK_TIME_MS\r
/* Check if the LinkSStatus in the PHY is still high after 15 seconds of not\r
\r
BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxBuffer, BaseType_t bReleaseAfterSend )\r
{\r
- if( xCheckLoopback( pxBuffer, bReleaseAfterSend ) != 0 )\r
- {\r
- /* The packet has been sent back to the IP-task.\r
- The IP-task will further handle it.\r
- Do not release the descriptor. */\r
- return pdTRUE;\r
- }\r
#if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )\r
{\r
ProtocolPacket_t *pxPacket;\r
xEMACpsif.isr_events &= ~EMAC_IF_ERR_EVENT;\r
emacps_check_errors( &xEMACpsif );\r
}\r
+\r
if( xResult > 0 )\r
{\r
/* A packet was received. No need to check for the PHY status now,\r
#include "xil_exception.h"\r
#include "xpseudo_asm.h"\r
#include "xil_cache.h"\r
-#include "xil_printf.h"\r
#include "xuartps.h"\r
#include "xscugic.h"\r
#include "xemacps.h" /* defines XEmacPs API */\r
/*\r
-FreeRTOS+TCP V2.0.11\r
-Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
-\r
-Permission is hereby granted, free of charge, to any person obtaining a copy of\r
-this software and associated documentation files (the "Software"), to deal in\r
-the Software without restriction, including without limitation the rights to\r
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
-the Software, and to permit persons to whom the Software is furnished to do so,\r
-subject to the following conditions:\r
-\r
-The above copyright notice and this permission notice shall be included in all\r
-copies or substantial portions of the Software.\r
-\r
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
-COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
-CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-\r
- http://aws.amazon.com/freertos\r
- http://www.FreeRTOS.org\r
+ * FreeRTOS+TCP V2.0.11\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://aws.amazon.com/freertos\r
+ * http://www.FreeRTOS.org\r
*/\r
\r
#include "FreeRTOS.h"\r
break;\r
}\r
#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
-#warning ipconfigZERO_COPY_TX_DRIVER is defined\r
{\r
void *pvBuffer = pxDMA_tx_buffers[ tail ];\r
NetworkBufferDescriptor_t *pxBuffer;\r
XStatus emacps_send_message(xemacpsif_s *xemacpsif, NetworkBufferDescriptor_t *pxBuffer, int iReleaseAfterSend )\r
{\r
int head = xemacpsif->txHead;\r
-//int tail = xemacpsif->txTail;\r
int iHasSent = 0;\r
uint32_t ulBaseAddress = xemacpsif->emacps.Config.BaseAddress;\r
TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 5000u );\r
/* Start transmit */\r
xemacpsif->txBusy = pdTRUE;\r
XEmacPs_WriteReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET, ( ulValue | XEMACPS_NWCTRL_STARTTX_MASK ) );\r
+ /* Reading it back is important compiler is optimised. */\r
+ XEmacPs_ReadReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET );\r
}\r
dsb();\r
\r
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
}\r
\r
-static void passEthMessages( NetworkBufferDescriptor_t *ethMsg )\r
+static void prvPassEthMessages( NetworkBufferDescriptor_t *pxDescriptor )\r
{\r
IPStackEvent_t xRxEvent;\r
\r
xRxEvent.eEventType = eNetworkRxEvent;\r
- xRxEvent.pvData = ( void * ) ethMsg;\r
+ xRxEvent.pvData = ( void * ) pxDescriptor;\r
\r
if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 1000 ) != pdPASS )\r
{\r
/* The buffer could not be sent to the stack so must be released again.\r
This is a deferred handler taskr, not a real interrupt, so it is ok to\r
use the task level function here. */\r
- do\r
+ #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )\r
{\r
- NetworkBufferDescriptor_t *xNext = ethMsg->pxNextBuffer;\r
- vReleaseNetworkBufferAndDescriptor( ethMsg );\r
- ethMsg = xNext;\r
- } while( ethMsg != NULL );\r
-\r
+ do\r
+ {\r
+ NetworkBufferDescriptor_t *pxNext = pxDescriptor->pxNextBuffer;\r
+ vReleaseNetworkBufferAndDescriptor( pxDescriptor );\r
+ pxDescriptor = pxNext;\r
+ } while( pxDescriptor != NULL );\r
+ }\r
+ #else\r
+ {\r
+ vReleaseNetworkBufferAndDescriptor( pxDescriptor );\r
+ }\r
+ #endif /* ipconfigUSE_LINKED_RX_MESSAGES */\r
iptraceETHERNET_RX_EVENT_LOST();\r
- FreeRTOS_printf( ( "passEthMessages: Can not queue return packet!\n" ) );\r
+ FreeRTOS_printf( ( "prvPassEthMessages: Can not queue return packet!\n" ) );\r
}\r
}\r
\r
-TickType_t ack_reception_delay = 10;\r
-\r
int emacps_check_rx( xemacpsif_s *xemacpsif )\r
{\r
NetworkBufferDescriptor_t *pxBuffer, *pxNewBuffer;\r
int rx_bytes;\r
volatile int msgCount = 0;\r
int head = xemacpsif->rxHead;\r
-BaseType_t bHasDataPacket = pdFALSE;\r
-NetworkBufferDescriptor_t *ethMsg = NULL;\r
-NetworkBufferDescriptor_t *ethLast = NULL;\r
+#if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )\r
+ NetworkBufferDescriptor_t *pxFirstDescriptor = NULL;\r
+ NetworkBufferDescriptor_t *pxLastDescriptor = NULL;\r
+#endif /* ipconfigUSE_LINKED_RX_MESSAGES */\r
\r
/* There seems to be an issue (SI# 692601), see comments below. */\r
resetrx_on_no_rxdata(xemacpsif);\r
\r
- {\r
- static int maxcount = 0;\r
- int count = 0;\r
- for( ;; )\r
- {\r
- if( ( ( xemacpsif->rxSegments[ head ].address & XEMACPS_RXBUF_NEW_MASK ) == 0 ) ||\r
- ( pxDMA_rx_buffers[ head ] == NULL ) )\r
- {\r
- break;\r
- }\r
- count++;\r
- if( ++head == ipconfigNIC_N_RX_DESC )\r
- {\r
- head = 0;\r
- }\r
- if( head == xemacpsif->rxHead )\r
- {\r
- break;\r
- }\r
- }\r
- if (maxcount < count) {\r
- maxcount = count;\r
- FreeRTOS_printf( ( "emacps_check_rx: %d packets\n", maxcount ) );\r
- }\r
- head = xemacpsif->rxHead;\r
- }\r
-\r
/* This FreeRTOS+TCP driver shall be compiled with the option\r
"ipconfigUSE_LINKED_RX_MESSAGES" enabled. It allows the driver to send a\r
chain of RX messages within one message to the IP-task. */\r
rx_bytes = xemacpsif->rxSegments[ head ].flags & XEMACPS_RXBUF_LEN_MASK;\r
\r
pxBuffer->xDataLength = rx_bytes;\r
-if( rx_bytes > 60 )\r
-{\r
- bHasDataPacket = 1;\r
-}\r
if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 )\r
{\r
Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, (unsigned)rx_bytes );\r
/* store it in the receive queue, where it'll be processed by a\r
different handler. */\r
iptraceNETWORK_INTERFACE_RECEIVE();\r
- pxBuffer->pxNextBuffer = NULL;\r
-\r
- if( ethMsg == NULL )\r
+ #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )\r
{\r
- // Becomes the first message\r
- ethMsg = pxBuffer;\r
+ pxBuffer->pxNextBuffer = NULL;\r
+\r
+ if( pxFirstDescriptor == NULL )\r
+ {\r
+ // Becomes the first message\r
+ pxFirstDescriptor = pxBuffer;\r
+ }\r
+ else if( pxLastDescriptor != NULL )\r
+ {\r
+ // Add to the tail\r
+ pxLastDescriptor->pxNextBuffer = pxBuffer;\r
+ }\r
+\r
+ pxLastDescriptor = pxBuffer;\r
}\r
- else if( ethLast != NULL )\r
+ #else\r
{\r
- // Add to the tail\r
- ethLast->pxNextBuffer = pxBuffer;\r
+ prvPassEthMessages( pxBuffer );\r
}\r
+ #endif /* ipconfigUSE_LINKED_RX_MESSAGES */\r
\r
- ethLast = pxBuffer;\r
msgCount++;\r
}\r
{\r
/* Clearing 'XEMACPS_RXBUF_NEW_MASK' 0x00000001 *< Used bit.. */\r
xemacpsif->rxSegments[ head ].flags = 0;\r
xemacpsif->rxSegments[ head ].address = addr;\r
- if (xemacpsif->rxSegments[ head ].address) {\r
+ if (xemacpsif->rxSegments[ head ].address)\r
+ {\r
// Just to read it\r
}\r
}\r
xemacpsif->rxHead = head;\r
}\r
\r
- if( ethMsg != NULL )\r
+ #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )\r
{\r
- if( bHasDataPacket == pdFALSE )\r
+ if( pxFirstDescriptor != NULL )\r
{\r
-// vTaskDelay( ack_reception_delay );\r
+ prvPassEthMessages( pxFirstDescriptor );\r
}\r
- passEthMessages( ethMsg );\r
}\r
+ #endif /* ipconfigUSE_LINKED_RX_MESSAGES */\r
\r
return msgCount;\r
}\r
tempcntr = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET );\r
if ( ( tempcntr == 0 ) && ( xemacpsif->last_rx_frms_cntr == 0 ) )\r
{\r
-FreeRTOS_printf( ( "resetrx_on_no_rxdata: RESET~\n" ) );\r
regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,\r
XEMACPS_NWCTRL_OFFSET);\r
regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);\r
}\r
}\r
\r
-extern XEmacPs_Config mac_config;\r
-\r
void HandleTxErrors(xemacpsif_s *xemacpsif)\r
{\r
u32 netctrlreg;\r
if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS)\r
return 10;\r
\r
- xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\n",\r
- __FUNCTION__);\r
+ FreeRTOS_printf( ( "%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\n",\r
+ __FUNCTION__ ) );\r
return 10;\r
\r
} else {\r
case (IEEE_CTRL_LINKSPEED_10M):\r
return 10;\r
default:\r
- xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\n",\r
- __FUNCTION__, phylinkspeed);\r
+ FreeRTOS_printf( ( "%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\n",\r
+ __FUNCTION__, phylinkspeed ) );\r
return 10;\r
}\r
\r
#else\r
u32 phy_addr = detect_phy(xemacpsp);\r
#endif\r
- xil_printf("Start PHY autonegotiation \n");\r
+ FreeRTOS_printf( ( "Start PHY autonegotiation \n" ) );\r
\r
#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1\r
#else\r
break;\r
}\r
#endif\r
- xil_printf("Waiting for PHY to complete autonegotiation.\n");\r
+ FreeRTOS_printf( ( "Waiting for PHY to complete autonegotiation.\n" ) );\r
\r
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);\r
while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {\r
- sleep(1);\r
+ vTaskDelay(1);\r
#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1\r
#else\r
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2,\r
&temp);\r
if (temp & IEEE_AUTONEG_ERROR_MASK) {\r
- xil_printf("Auto negotiation error \n");\r
+ FreeRTOS_printf( ( "Auto negotiation error \n" ) );\r
}\r
#endif\r
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET,\r
&status);\r
}\r
\r
- xil_printf("autonegotiation complete \n");\r
+ FreeRTOS_printf( ( "autonegotiation complete \n" ) );\r
\r
#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1\r
#else\r
#endif\r
\r
#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1\r
- xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \n");\r
+ FreeRTOS_printf( ( "Waiting for Link to be up; Polling for SGMII core Reg \n" ) );\r
XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp);\r
while(!(temp & 0x8000)) {\r
XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp);\r
XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp);\r
return 10;\r
} else {\r
- xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Deafulting to Speed = 10 Mbps\n");\r
+ FreeRTOS_printf( ( "get_IEEE_phy_speed(): Invalid speed bit value, Deafulting to Speed = 10 Mbps\n" ) );\r
XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp);\r
XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, 0x0100);\r
return 10;\r
link_speed = 1000;\r
configure_IEEE_phy_speed(xemacpsp, link_speed);\r
convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;\r
- sleep(1);\r
+ vTaskDelay(1);\r
#elif defined(ipconfigNIC_LINKSPEED100)\r
SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);\r
link_speed = 100;\r
configure_IEEE_phy_speed(xemacpsp, link_speed);\r
convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;\r
- sleep(1);\r
+ vTaskDelay(1);\r
#elif defined(ipconfigNIC_LINKSPEED10)\r
SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);\r
link_speed = 10;\r
configure_IEEE_phy_speed(xemacpsp, link_speed);\r
convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;\r
- sleep(1);\r
+ vTaskDelay(1);\r
#endif\r
if (conv_present) {\r
XEmacPs_PhyWrite(xemacpsp, convphyaddr,\r
XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting);\r
}\r
\r
- xil_printf("link speed: %d\n", link_speed);\r
+ FreeRTOS_printf( ( "link speed: %d\n", link_speed ) );\r
return link_speed;\r
}\r
\r
+/*\r
+ * FreeRTOS+TCP V2.0.11\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://aws.amazon.com/freertos\r
+ * http://www.FreeRTOS.org\r
+ */\r
+\r
/*\r
* Handling of Ethernet PHY's\r
* PHY's communicate with an EMAC either through\r
#define PHY_ID_KSZ8081 0x000010A1\r
\r
#define PHY_ID_KSZ8863 0x00221430\r
+#define PHY_ID_KSZ8081MNXIA 0x00221560\r
\r
#define PHY_ID_DP83848I 0x20005C90\r
\r
projects / freertos / commitdiff