2 * Copyright (c) 2007-2008, Advanced Micro Devices, Inc.
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3 * All rights reserved.
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5 * Redistribution and use in source and binary forms, with or without
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6 * modification, are permitted provided that the following conditions
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9 * * Redistributions of source code must retain the above copyright
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10 * notice, this list of conditions and the following disclaimer.
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11 * * Redistributions in binary form must reproduce the above copyright
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12 * notice, this list of conditions and the following disclaimer in
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13 * the documentation and/or other materials provided with the
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15 * * Neither the name of Advanced Micro Devices, Inc. nor the names
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16 * of its contributors may be used to endorse or promote products
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17 * derived from this software without specific prior written
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 * Some portions copyright (c) 2010-2013 Xilinx, Inc. All rights reserved.
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37 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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38 * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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39 * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
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40 * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
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41 * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
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42 * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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43 * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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44 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
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45 * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
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46 * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
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47 * AND FITNESS FOR A PARTICULAR PURPOSE.
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51 /* Standard includes. */
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56 /* FreeRTOS includes. */
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57 #include "FreeRTOS.h"
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62 /* FreeRTOS+TCP includes. */
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63 #include "FreeRTOS_IP.h"
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64 #include "FreeRTOS_Sockets.h"
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65 #include "FreeRTOS_IP_Private.h"
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66 #include "NetworkBufferManagement.h"
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68 #include "Zynq/x_emacpsif.h"
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69 #include "xparameters_ps.h"
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70 #include "xparameters.h"
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73 int phy_detected = 0;
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75 /*** IMPORTANT: Define PEEP in xemacpsif.h and sys_arch_raw.c
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76 *** to run it on a PEEP board
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79 /* Advertisement control register. */
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80 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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81 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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82 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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83 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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85 #define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \
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86 ADVERTISE_10HALF | ADVERTISE_100HALF)
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87 #define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF)
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88 #define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF)
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90 #define ADVERTISE_1000 0x0300
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93 //#define PHY_REG_00_BMCR 0x00 // Basic mode control register
\r
94 //#define PHY_REG_01_BMSR 0x01 // Basic mode status register
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95 //#define PHY_REG_02_PHYSID1 0x02 // PHYS ID 1
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96 //#define PHY_REG_03_PHYSID2 0x03 // PHYS ID 2
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97 //#define PHY_REG_04_ADVERTISE 0x04 // Advertisement control reg
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99 #define IEEE_CONTROL_REG_OFFSET 0
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100 #define IEEE_STATUS_REG_OFFSET 1
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101 #define IEEE_PHYSID1_OFFSET 2
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102 #define IEEE_PHYSID2_OFFSET 3
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103 #define IEEE_AUTONEGO_ADVERTISE_REG 4
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104 #define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5
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105 #define IEEE_1000_ADVERTISE_REG_OFFSET 9
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106 #define IEEE_PARTNER_ABILITIES_3_REG_OFFSET 10
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107 #define IEEE_COPPER_SPECIFIC_CONTROL_REG 16
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108 #define IEEE_SPECIFIC_STATUS_REG 17
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109 #define IEEE_COPPER_SPECIFIC_STATUS_REG_2 19
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110 #define IEEE_CONTROL_REG_MAC 21
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111 #define IEEE_PAGE_ADDRESS_REGISTER 22
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114 #define IEEE_CTRL_1GBPS_LINKSPEED_MASK 0x2040
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115 #define IEEE_CTRL_LINKSPEED_MASK 0x0040
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116 #define IEEE_CTRL_LINKSPEED_1000M 0x0040
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117 #define IEEE_CTRL_LINKSPEED_100M 0x2000
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118 #define IEEE_CTRL_LINKSPEED_10M 0x0000
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119 #define IEEE_CTRL_RESET_MASK 0x8000
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120 #define IEEE_CTRL_AUTONEGOTIATE_ENABLE 0x1000
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121 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
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122 #define IEEE_CTRL_RESET 0x9140
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123 #define IEEE_CTRL_ISOLATE_DISABLE 0xFBFF
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125 #define IEEE_STAT_AUTONEGOTIATE_CAPABLE 0x0008
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126 #define IEEE_STAT_AUTONEGOTIATE_COMPLETE 0x0020
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127 #define IEEE_STAT_AUTONEGOTIATE_RESTART 0x0200
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128 #define IEEE_STAT_1GBPS_EXTENSIONS 0x0100
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129 #define IEEE_AN1_ABILITY_MASK 0x1FE0
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130 #define IEEE_AN3_ABILITY_MASK_1GBPS 0x0C00
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131 #define IEEE_AN1_ABILITY_MASK_100MBPS 0x0380
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132 #define IEEE_AN1_ABILITY_MASK_10MBPS 0x0060
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133 #define IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK 0x0030
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135 #define IEEE_ASYMMETRIC_PAUSE_MASK 0x0800
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136 #define IEEE_PAUSE_MASK 0x0400
\r
137 #define IEEE_AUTONEG_ERROR_MASK 0x8000
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139 #define XEMACPS_GMII2RGMII_SPEED1000_FD 0x140
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140 #define XEMACPS_GMII2RGMII_SPEED100_FD 0x2100
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141 #define XEMACPS_GMII2RGMII_SPEED10_FD 0x100
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142 #define XEMACPS_GMII2RGMII_REG_NUM 0x10
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144 /* Frequency setting */
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145 #define SLCR_LOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x4)
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146 #define SLCR_UNLOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x8)
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147 #define SLCR_GEM0_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x140)
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148 #define SLCR_GEM1_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x144)
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150 #define SLCR_GEM_10M_CLK_CTRL_VALUE 0x00103031
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151 #define SLCR_GEM_100M_CLK_CTRL_VALUE 0x00103001
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152 #define SLCR_GEM_1G_CLK_CTRL_VALUE 0x00103011
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154 #define SLCR_LOCK_KEY_VALUE 0x767B
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155 #define SLCR_UNLOCK_KEY_VALUE 0xDF0D
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156 #define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214)
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157 #define EMACPS_SLCR_DIV_MASK 0xFC0FC0FF
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159 #define EMAC0_BASE_ADDRESS 0xE000B000
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160 #define EMAC1_BASE_ADDRESS 0xE000C000
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162 static int detect_phy(XEmacPs *xemacpsp)
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164 u16 id_lower, id_upper;
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167 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
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168 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PHYSID1_OFFSET, &id_lower);
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170 if ((id_lower != ( u16 )0xFFFFu) && (id_lower != ( u16 )0x0u)) {
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172 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PHYSID2_OFFSET, &id_upper);
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173 id = ( ( ( uint32_t ) id_upper ) << 16 ) | ( id_lower & 0xFFF0 );
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174 FreeRTOS_printf( ("XEmacPs detect_phy: %04lX at address %d.\n", id, phy_addr ) );
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175 phy_detected = phy_addr;
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180 FreeRTOS_printf( ("XEmacPs detect_phy: No PHY detected. Assuming a PHY at address 0\n" ) );
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182 /* default to zero */
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187 unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp)
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192 u16 partner_capabilities;
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193 u16 partner_capabilities_1000;
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195 u32 phy_addr = detect_phy(xemacpsp);
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197 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
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199 /* Advertise PHY speed of 100 and 10 Mbps */
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200 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG,
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201 ADVERTISE_100_AND_10);
\r
203 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET,
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205 control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE |
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206 IEEE_STAT_AUTONEGOTIATE_RESTART);
\r
208 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
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210 /* Read PHY control and status registers is successful. */
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211 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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212 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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214 if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) && (status &
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215 IEEE_STAT_AUTONEGOTIATE_CAPABLE)) {
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217 while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
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218 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET,
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222 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET,
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223 &partner_capabilities);
\r
225 if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
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226 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_3_REG_OFFSET,
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227 &partner_capabilities_1000);
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228 if (partner_capabilities_1000 & IEEE_AN3_ABILITY_MASK_1GBPS)
\r
232 if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS)
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234 if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS)
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237 FreeRTOS_printf( ( "%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\n",
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243 /* Update TEMAC speed accordingly */
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244 if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
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245 /* Get commanded link speed */
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246 phylinkspeed = control & IEEE_CTRL_1GBPS_LINKSPEED_MASK;
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248 switch (phylinkspeed) {
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249 case (IEEE_CTRL_LINKSPEED_1000M):
\r
251 case (IEEE_CTRL_LINKSPEED_100M):
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253 case (IEEE_CTRL_LINKSPEED_10M):
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256 FreeRTOS_printf( ( "%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\n",
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257 __FUNCTION__, phylinkspeed ) );
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263 return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10;
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270 unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp)
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275 u16 partner_capabilities;
\r
276 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
\r
277 u32 phy_addr = XPAR_PCSPMA_SGMII_PHYADDR;
\r
279 u32 phy_addr = detect_phy(xemacpsp);
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281 FreeRTOS_printf( ( "Start PHY autonegotiation \n" ) );
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283 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
\r
285 XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
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286 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
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287 control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
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288 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control);
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290 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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292 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
\r
293 control |= IEEE_ASYMMETRIC_PAUSE_MASK;
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294 control |= IEEE_PAUSE_MASK;
\r
295 control |= ADVERTISE_100;
\r
296 control |= ADVERTISE_10;
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297 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
\r
299 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
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301 control |= ADVERTISE_1000;
\r
302 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
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305 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
\r
306 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
\r
308 control |= (7 << 12); /* max number of gigabit attempts */
\r
309 control |= (1 << 11); /* enable downshift */
\r
310 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
\r
313 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
\r
314 control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
\r
315 control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
\r
316 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
\r
317 control &= IEEE_CTRL_ISOLATE_DISABLE;
\r
320 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
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323 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
\r
325 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
\r
326 control |= IEEE_CTRL_RESET_MASK;
\r
327 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
\r
330 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
\r
331 if (control & IEEE_CTRL_RESET_MASK)
\r
337 FreeRTOS_printf( ( "Waiting for PHY to complete autonegotiation.\n" ) );
\r
339 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
\r
340 while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
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342 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
\r
344 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2,
\r
346 if (temp & IEEE_AUTONEG_ERROR_MASK) {
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347 FreeRTOS_printf( ( "Auto negotiation error \n" ) );
\r
350 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET,
\r
354 FreeRTOS_printf( ( "autonegotiation complete \n" ) );
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356 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
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358 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_SPECIFIC_STATUS_REG, &partner_capabilities);
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361 #if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1
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362 FreeRTOS_printf( ( "Waiting for Link to be up; Polling for SGMII core Reg \n" ) );
\r
363 XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp);
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364 while(!(temp & 0x8000)) {
\r
365 XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp);
\r
367 if((temp & 0x0C00) == 0x0800) {
\r
368 XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp);
\r
371 else if((temp & 0x0C00) == 0x0400) {
\r
372 XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp);
\r
375 else if((temp & 0x0C00) == 0x0000) {
\r
376 XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp);
\r
379 FreeRTOS_printf( ( "get_IEEE_phy_speed(): Invalid speed bit value, Deafulting to Speed = 10 Mbps\n" ) );
\r
380 XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp);
\r
381 XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, 0x0100);
\r
385 if ( ((partner_capabilities >> 14) & 3) == 2)/* 1000Mbps */
\r
387 else if ( ((partner_capabilities >> 14) & 3) == 1)/* 100Mbps */
\r
395 unsigned configure_IEEE_phy_speed(XEmacPs *xemacpsp, unsigned speed)
\r
398 u32 phy_addr = detect_phy(xemacpsp);
\r
400 XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
\r
401 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
\r
402 control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
\r
403 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control);
\r
405 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
\r
407 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
\r
408 control |= IEEE_ASYMMETRIC_PAUSE_MASK;
\r
409 control |= IEEE_PAUSE_MASK;
\r
410 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
\r
412 XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
\r
413 control &= ~IEEE_CTRL_LINKSPEED_1000M;
\r
414 control &= ~IEEE_CTRL_LINKSPEED_100M;
\r
415 control &= ~IEEE_CTRL_LINKSPEED_10M;
\r
417 if (speed == 1000) {
\r
418 control |= IEEE_CTRL_LINKSPEED_1000M;
\r
421 else if (speed == 100) {
\r
422 control |= IEEE_CTRL_LINKSPEED_100M;
\r
423 /* Dont advertise PHY speed of 1000 Mbps */
\r
424 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, 0);
\r
425 /* Dont advertise PHY speed of 10 Mbps */
\r
426 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG,
\r
430 else if (speed == 10) {
\r
431 control |= IEEE_CTRL_LINKSPEED_10M;
\r
432 /* Dont advertise PHY speed of 1000 Mbps */
\r
433 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
\r
435 /* Dont advertise PHY speed of 100 Mbps */
\r
436 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG,
\r
440 XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET,
\r
441 control | IEEE_CTRL_RESET_MASK);
\r
444 for (wait=0; wait < 100000; wait++);
\r
449 static void SetUpSLCRDivisors(int mac_baseaddr, int speed)
\r
451 volatile u32 slcrBaseAddress;
\r
455 u32 SlcrTxClkCntrl;
\r
458 *(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
\r
460 if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) {
\r
461 slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
\r
463 slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
\r
466 if (speed == 1000) {
\r
467 *(volatile unsigned int *)(slcrBaseAddress) =
\r
468 SLCR_GEM_1G_CLK_CTRL_VALUE;
\r
469 } else if (speed == 100) {
\r
470 *(volatile unsigned int *)(slcrBaseAddress) =
\r
471 SLCR_GEM_100M_CLK_CTRL_VALUE;
\r
473 *(volatile unsigned int *)(slcrBaseAddress) =
\r
474 SLCR_GEM_10M_CLK_CTRL_VALUE;
\r
477 if (speed == 1000) {
\r
478 if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) {
\r
479 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
\r
480 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
\r
481 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
\r
484 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
\r
485 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
\r
486 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
\r
489 } else if (speed == 100) {
\r
490 if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) {
\r
491 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
\r
492 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
\r
493 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
\r
496 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
\r
497 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
\r
498 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
\r
502 if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) {
\r
503 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
\r
504 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
\r
505 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
\r
508 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
\r
509 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
\r
510 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
\r
514 SlcrTxClkCntrl = *(volatile unsigned int *)(slcrBaseAddress);
\r
515 SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
\r
516 SlcrTxClkCntrl |= (SlcrDiv1 << 20);
\r
517 SlcrTxClkCntrl |= (SlcrDiv0 << 8);
\r
518 *(volatile unsigned int *)(slcrBaseAddress) = SlcrTxClkCntrl;
\r
520 *(volatile unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
\r
525 unsigned link_speed;
\r
526 unsigned Phy_Setup (XEmacPs *xemacpsp)
\r
528 unsigned long conv_present = 0;
\r
529 unsigned long convspeeddupsetting = 0;
\r
530 unsigned long convphyaddr = 0;
\r
532 #ifdef XPAR_GMII2RGMIICON_0N_ETH0_ADDR
\r
533 convphyaddr = XPAR_GMII2RGMIICON_0N_ETH0_ADDR;
\r
536 #ifdef XPAR_GMII2RGMIICON_0N_ETH1_ADDR
\r
537 convphyaddr = XPAR_GMII2RGMIICON_0N_ETH1_ADDR;
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542 #ifdef ipconfigNIC_LINKSPEED_AUTODETECT
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543 link_speed = get_IEEE_phy_speed(xemacpsp);
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544 if (link_speed == 1000) {
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545 SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
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546 convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
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547 } else if (link_speed == 100) {
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548 SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
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549 convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
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551 SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
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552 convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
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554 #elif defined(ipconfigNIC_LINKSPEED1000)
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555 SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
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557 configure_IEEE_phy_speed(xemacpsp, link_speed);
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558 convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
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560 #elif defined(ipconfigNIC_LINKSPEED100)
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561 SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
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563 configure_IEEE_phy_speed(xemacpsp, link_speed);
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564 convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
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566 #elif defined(ipconfigNIC_LINKSPEED10)
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567 SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
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569 configure_IEEE_phy_speed(xemacpsp, link_speed);
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570 convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
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573 if (conv_present) {
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574 XEmacPs_PhyWrite(xemacpsp, convphyaddr,
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575 XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting);
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578 FreeRTOS_printf( ( "link speed: %d\n", link_speed ) );
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