2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arcregs.h>
10 /* Bit values in IC_CTRL */
11 #define IC_CTRL_CACHE_DISABLE (1 << 0)
13 /* Bit values in DC_CTRL */
14 #define DC_CTRL_CACHE_DISABLE (1 << 0)
15 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
16 #define DC_CTRL_FLUSH_STATUS (1 << 8)
18 int icache_status(void)
20 return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
21 IC_CTRL_CACHE_DISABLE;
24 void icache_enable(void)
26 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
27 ~IC_CTRL_CACHE_DISABLE);
30 void icache_disable(void)
32 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
33 IC_CTRL_CACHE_DISABLE);
36 void invalidate_icache_all(void)
38 #ifndef CONFIG_SYS_ICACHE_OFF
39 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
40 write_aux_reg(ARC_AUX_IC_IVIC, 1);
41 #endif /* CONFIG_SYS_ICACHE_OFF */
44 int dcache_status(void)
46 return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
47 DC_CTRL_CACHE_DISABLE;
50 void dcache_enable(void)
52 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
53 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
56 void dcache_disable(void)
58 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
59 DC_CTRL_CACHE_DISABLE);
62 void flush_dcache_all(void)
64 /* Do flush of entire cache */
65 write_aux_reg(ARC_AUX_DC_FLSH, 1);
68 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
72 #ifndef CONFIG_SYS_DCACHE_OFF
73 static void dcache_flush_line(unsigned addr)
75 #if (CONFIG_ARC_MMU_VER > 2)
76 write_aux_reg(ARC_AUX_DC_PTAG, addr);
78 write_aux_reg(ARC_AUX_DC_FLDL, addr);
81 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
84 #ifndef CONFIG_SYS_ICACHE_OFF
86 * Invalidate I$ for addresses range just flushed from D$.
87 * If we try to execute data flushed above it will be valid/correct
89 #if (CONFIG_ARC_MMU_VER > 2)
90 write_aux_reg(ARC_AUX_IC_PTAG, addr);
92 write_aux_reg(ARC_AUX_IC_IVIL, addr);
93 #endif /* CONFIG_SYS_ICACHE_OFF */
95 #endif /* CONFIG_SYS_DCACHE_OFF */
97 void flush_dcache_range(unsigned long start, unsigned long end)
99 #ifndef CONFIG_SYS_DCACHE_OFF
102 start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
103 end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
105 for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
106 dcache_flush_line(addr);
107 #endif /* CONFIG_SYS_DCACHE_OFF */
110 void invalidate_dcache_range(unsigned long start, unsigned long end)
112 #ifndef CONFIG_SYS_DCACHE_OFF
115 start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
116 end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
118 for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
119 #if (CONFIG_ARC_MMU_VER > 2)
120 write_aux_reg(ARC_AUX_DC_PTAG, addr);
122 write_aux_reg(ARC_AUX_DC_IVDL, addr);
124 #endif /* CONFIG_SYS_DCACHE_OFF */
127 void invalidate_dcache_all(void)
129 #ifndef CONFIG_SYS_DCACHE_OFF
130 /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
131 write_aux_reg(ARC_AUX_DC_IVDC, 1);
132 #endif /* CONFIG_SYS_DCACHE_OFF */
135 void flush_cache(unsigned long start, unsigned long size)
137 flush_dcache_range(start, start + size);