2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARC_CACHE_H
8 #define __ASM_ARC_CACHE_H
13 * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
14 * We use that value for aligning DMA buffers unless the board config has
15 * specified an alternate cache line size.
17 #ifdef CONFIG_SYS_CACHELINE_SIZE
18 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
20 #define ARCH_DMA_MINALIGN 128
23 #if defined(CONFIG_ARC_MMU_V2)
24 #define CONFIG_ARC_MMU_VER 2
25 #elif defined(CONFIG_ARC_MMU_V3)
26 #define CONFIG_ARC_MMU_VER 3
29 #endif /* __ASM_ARC_CACHE_H */