1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
6 #ifndef __ASM_ARC_CACHE_H
7 #define __ASM_ARC_CACHE_H
12 * As of today we may handle any L1 cache line length right in software.
13 * For that essentially cache line length is a variable not constant.
14 * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
15 * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
17 #define ARCH_DMA_MINALIGN 128
19 #if defined(ARC_MMU_ABSENT)
20 #define CONFIG_ARC_MMU_VER 0
21 #elif defined(CONFIG_ARC_MMU_V2)
22 #define CONFIG_ARC_MMU_VER 2
23 #elif defined(CONFIG_ARC_MMU_V3)
24 #define CONFIG_ARC_MMU_VER 3
25 #elif defined(CONFIG_ARC_MMU_V4)
26 #define CONFIG_ARC_MMU_VER 4
31 void cache_init(void);
32 void flush_n_invalidate_dcache_all(void);
33 void sync_n_cleanup_cache_all(void);
35 static const inline int is_ioc_enabled(void)
37 return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
40 #endif /* __ASSEMBLY__ */
42 #endif /* __ASM_ARC_CACHE_H */