git.sur5r.net Git - u-boot/blob - arch/arc/lib/cache.c

   1 /*
   2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <config.h>
   8 #include <asm/arcregs.h>
   9 #include <asm/cache.h>
  10
  11 /* Bit values in IC_CTRL */
  12 #define IC_CTRL_CACHE_DISABLE   (1 << 0)
  13
  14 /* Bit values in DC_CTRL */
  15 #define DC_CTRL_CACHE_DISABLE   (1 << 0)
  16 #define DC_CTRL_INV_MODE_FLUSH  (1 << 6)
  17 #define DC_CTRL_FLUSH_STATUS    (1 << 8)
  18 #define CACHE_VER_NUM_MASK      0xF
  19
  20 int icache_status(void)
  21 {
  22         /* If no cache in CPU exit immediately */
  23         if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
  24                 return 0;
  25
  26         return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
  27                IC_CTRL_CACHE_DISABLE;
  28 }
  29
  30 void icache_enable(void)
  31 {
  32         /* If no cache in CPU exit immediately */
  33         if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
  34                 return;
  35
  36         write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
  37                       ~IC_CTRL_CACHE_DISABLE);
  38 }
  39
  40 void icache_disable(void)
  41 {
  42         /* If no cache in CPU exit immediately */
  43         if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
  44                 return;
  45
  46         write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
  47                       IC_CTRL_CACHE_DISABLE);
  48 }
  49
  50 void invalidate_icache_all(void)
  51 {
  52 #ifndef CONFIG_SYS_ICACHE_OFF
  53         /* Any write to IC_IVIC register triggers invalidation of entire I$ */
  54         write_aux_reg(ARC_AUX_IC_IVIC, 1);
  55 #endif /* CONFIG_SYS_ICACHE_OFF */
  56 }
  57
  58 int dcache_status(void)
  59 {
  60         /* If no cache in CPU exit immediately */
  61         if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
  62                 return 0;
  63
  64         return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
  65                 DC_CTRL_CACHE_DISABLE;
  66 }
  67
  68 void dcache_enable(void)
  69 {
  70         /* If no cache in CPU exit immediately */
  71         if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
  72                 return;
  73
  74         write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
  75                       ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
  76 }
  77
  78 void dcache_disable(void)
  79 {
  80         /* If no cache in CPU exit immediately */
  81         if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
  82                 return;
  83
  84         write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
  85                       DC_CTRL_CACHE_DISABLE);
  86 }
  87
  88 void flush_dcache_all(void)
  89 {
  90         /* If no cache in CPU exit immediately */
  91         if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
  92                 return;
  93
  94         /* Do flush of entire cache */
  95         write_aux_reg(ARC_AUX_DC_FLSH, 1);
  96
  97         /* Wait flush end */
  98         while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
  99                 ;
 100 }
 101
 102 #ifndef CONFIG_SYS_DCACHE_OFF
 103 static void dcache_flush_line(unsigned addr)
 104 {
 105 #if (CONFIG_ARC_MMU_VER == 3)
 106         write_aux_reg(ARC_AUX_DC_PTAG, addr);
 107 #endif
 108         write_aux_reg(ARC_AUX_DC_FLDL, addr);
 109
 110         /* Wait flush end */
 111         while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
 112                 ;
 113
 114 #ifndef CONFIG_SYS_ICACHE_OFF
 115         /*
 116          * Invalidate I$ for addresses range just flushed from D$.
 117          * If we try to execute data flushed above it will be valid/correct
 118          */
 119 #if (CONFIG_ARC_MMU_VER == 3)
 120         write_aux_reg(ARC_AUX_IC_PTAG, addr);
 121 #endif
 122         write_aux_reg(ARC_AUX_IC_IVIL, addr);
 123 #endif /* CONFIG_SYS_ICACHE_OFF */
 124 }
 125 #endif /* CONFIG_SYS_DCACHE_OFF */
 126
 127 void flush_dcache_range(unsigned long start, unsigned long end)
 128 {
 129 #ifndef CONFIG_SYS_DCACHE_OFF
 130         unsigned int addr;
 131
 132         start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 133         end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 134
 135         for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
 136                 dcache_flush_line(addr);
 137 #endif /* CONFIG_SYS_DCACHE_OFF */
 138 }
 139
 140 void invalidate_dcache_range(unsigned long start, unsigned long end)
 141 {
 142 #ifndef CONFIG_SYS_DCACHE_OFF
 143         unsigned int addr;
 144
 145         start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 146         end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 147
 148         for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
 149 #if (CONFIG_ARC_MMU_VER == 3)
 150                 write_aux_reg(ARC_AUX_DC_PTAG, addr);
 151 #endif
 152                 write_aux_reg(ARC_AUX_DC_IVDL, addr);
 153         }
 154 #endif /* CONFIG_SYS_DCACHE_OFF */
 155 }
 156
 157 void invalidate_dcache_all(void)
 158 {
 159 #ifndef CONFIG_SYS_DCACHE_OFF
 160         /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
 161         write_aux_reg(ARC_AUX_DC_IVDC, 1);
 162 #endif /* CONFIG_SYS_DCACHE_OFF */
 163 }
 164
 165 void flush_cache(unsigned long start, unsigned long size)
 166 {
 167         flush_dcache_range(start, start + size);
 168 }