2 * (C) Copyright 2004 Texas Insturments
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/system.h>
38 static void cache_flush(void);
40 int cleanup_before_linux (void)
43 * this function is called just before we call linux
44 * it prepares the processor for linux
46 * we turn off caches etc ...
49 disable_interrupts ();
53 extern void lcd_disable(void);
54 extern void lcd_panel_disable(void);
56 lcd_disable(); /* proper disable of lcd & panel */
61 /* turn off I/D-cache */
70 static void cache_flush(void)
74 asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
75 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */
76 asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
79 #ifndef CONFIG_SYS_DCACHE_OFF
81 #ifndef CONFIG_SYS_CACHELINE_SIZE
82 #define CONFIG_SYS_CACHELINE_SIZE 32
85 void invalidate_dcache_all(void)
87 asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
90 void flush_dcache_all(void)
92 asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
93 asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
96 static inline int bad_cache_range(unsigned long start, unsigned long stop)
100 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
103 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
107 debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
113 void invalidate_dcache_range(unsigned long start, unsigned long stop)
115 if (bad_cache_range(start, stop))
118 while (start < stop) {
119 asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
120 start += CONFIG_SYS_CACHELINE_SIZE;
124 void flush_dcache_range(unsigned long start, unsigned long stop)
126 if (bad_cache_range(start, stop))
129 while (start < stop) {
130 asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
131 start += CONFIG_SYS_CACHELINE_SIZE;
134 asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
137 void flush_cache(unsigned long start, unsigned long size)
139 flush_dcache_range(start, start + size);
142 void enable_caches(void)
144 #ifndef CONFIG_SYS_ICACHE_OFF
147 #ifndef CONFIG_SYS_DCACHE_OFF
152 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
153 void invalidate_dcache_all(void)
157 void flush_dcache_all(void)
161 void invalidate_dcache_range(unsigned long start, unsigned long stop)
165 void flush_dcache_range(unsigned long start, unsigned long stop)
169 void flush_cache(unsigned long start, unsigned long size)
172 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */