3 * Sascha Hauer, Pengutronix
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
15 static u32 mx31_decode_pll(u32 reg, u32 infreq)
17 u32 mfi = GET_PLL_MFI(reg);
18 s32 mfn = GET_PLL_MFN(reg);
19 u32 mfd = GET_PLL_MFD(reg);
20 u32 pd = GET_PLL_PD(reg);
22 mfi = mfi <= 5 ? 5 : mfi;
23 mfn = mfn >= 512 ? mfn - 1024 : mfn;
27 return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
31 static u32 mx31_get_mpl_dpdgck_clk(void)
35 if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
36 infreq = MXC_CLK32 * 1024;
40 return mx31_decode_pll(readl(CCM_MPCTL), infreq);
43 static u32 mx31_get_mcu_main_clk(void)
45 /* For now we assume mpl_dpdgck_clk == mcu_main_clk
46 * which should be correct for most boards
48 return mx31_get_mpl_dpdgck_clk();
51 static u32 mx31_get_ipg_clk(void)
53 u32 freq = mx31_get_mcu_main_clk();
54 u32 pdr0 = readl(CCM_PDR0);
56 freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
57 freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
62 /* hsp is the clock for the ipu */
63 static u32 mx31_get_hsp_clk(void)
65 u32 freq = mx31_get_mcu_main_clk();
66 u32 pdr0 = readl(CCM_PDR0);
68 freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
73 void mx31_dump_clocks(void)
75 u32 cpufreq = mx31_get_mcu_main_clk();
76 printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
77 printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
78 printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
81 unsigned int mxc_get_clock(enum mxc_clock clk)
85 return mx31_get_mcu_main_clk();
92 return mx31_get_ipg_clk();
94 return mx31_get_hsp_clk();
99 u32 imx_get_uartclk(void)
101 return mxc_get_clock(MXC_UART_CLK);
104 void mx31_gpio_mux(unsigned long mode)
106 unsigned long reg, shift, tmp;
108 reg = IOMUXC_BASE + (mode & 0x1fc);
109 shift = (~mode & 0x3) * 8;
112 tmp &= ~(0xff << shift);
113 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
117 void mx31_set_pad(enum iomux_pins pin, u32 config)
121 pin &= IOMUX_PADNUM_MASK;
122 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
123 field = (pin + 2) % 3;
126 l &= ~(0x1ff << (field * 10));
127 l |= config << (field * 10);
132 void mx31_set_gpr(enum iomux_gp_func gp, char en)
135 struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
137 l = readl(&iomuxc->gpr);
143 writel(l, &iomuxc->gpr);
146 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
148 struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
149 struct mx31_weim_cscr *cscr = &weim->cscr[cs];
151 writel(weimcs->upper, &cscr->upper);
152 writel(weimcs->lower, &cscr->lower);
153 writel(weimcs->additional, &cscr->additional);
156 struct mx3_cpu_type mx31_cpu_type[] = {
157 { .srev = 0x00, .v = 0x10 },
158 { .srev = 0x10, .v = 0x11 },
159 { .srev = 0x11, .v = 0x11 },
160 { .srev = 0x12, .v = 0x1F },
161 { .srev = 0x13, .v = 0x1F },
162 { .srev = 0x14, .v = 0x12 },
163 { .srev = 0x15, .v = 0x12 },
164 { .srev = 0x28, .v = 0x20 },
165 { .srev = 0x29, .v = 0x20 },
168 u32 get_cpu_rev(void)
172 /* read SREV register from IIM module */
173 struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
174 srev = readl(&iim->iim_srev);
176 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
177 if (srev == mx31_cpu_type[i].srev)
178 return mx31_cpu_type[i].v;
180 return srev | 0x8000;
183 static char *get_reset_cause(void)
185 /* read RCSR register from CCM module */
186 struct clock_control_regs *ccm =
187 (struct clock_control_regs *)CCM_BASE;
189 u32 cause = readl(&ccm->rcsr) & 0x07;
201 return "ARM11P power gating";
203 return "unknown reset";
207 #if defined(CONFIG_DISPLAY_CPUINFO)
208 int print_cpuinfo(void)
210 u32 srev = get_cpu_rev();
212 printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
213 (srev & 0xF0) >> 4, (srev & 0x0F),
214 ((srev & 0x8000) ? " unknown" : ""),
215 mx31_get_mcu_main_clk() / 1000000);
216 printf("Reset cause: %s\n", get_reset_cause());