3 * Sascha Hauer, Pengutronix
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/clock.h>
28 #include <asm/arch/sys_proto.h>
30 static u32 mx31_decode_pll(u32 reg, u32 infreq)
32 u32 mfi = GET_PLL_MFI(reg);
33 u32 mfn = GET_PLL_MFN(reg);
34 u32 mfd = GET_PLL_MFD(reg);
35 u32 pd = GET_PLL_PD(reg);
37 mfi = mfi <= 5 ? 5 : mfi;
41 return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
45 static u32 mx31_get_mpl_dpdgck_clk(void)
49 if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
50 infreq = CONFIG_MX31_CLK32 * 1024;
52 infreq = CONFIG_MX31_HCLK_FREQ;
54 return mx31_decode_pll(readl(CCM_MPCTL), infreq);
57 static u32 mx31_get_mcu_main_clk(void)
59 /* For now we assume mpl_dpdgck_clk == mcu_main_clk
60 * which should be correct for most boards
62 return mx31_get_mpl_dpdgck_clk();
65 static u32 mx31_get_ipg_clk(void)
67 u32 freq = mx31_get_mcu_main_clk();
68 u32 pdr0 = readl(CCM_PDR0);
70 freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
71 freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
76 /* hsp is the clock for the ipu */
77 static u32 mx31_get_hsp_clk(void)
79 u32 freq = mx31_get_mcu_main_clk();
80 u32 pdr0 = readl(CCM_PDR0);
82 freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
87 void mx31_dump_clocks(void)
89 u32 cpufreq = mx31_get_mcu_main_clk();
90 printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
91 printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
92 printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
95 unsigned int mxc_get_clock(enum mxc_clock clk)
99 return mx31_get_mcu_main_clk();
105 return mx31_get_ipg_clk();
107 return mx31_get_hsp_clk();
112 u32 imx_get_uartclk(void)
114 return mxc_get_clock(MXC_UART_CLK);
117 void mx31_gpio_mux(unsigned long mode)
119 unsigned long reg, shift, tmp;
121 reg = IOMUXC_BASE + (mode & 0x1fc);
122 shift = (~mode & 0x3) * 8;
125 tmp &= ~(0xff << shift);
126 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
130 void mx31_set_pad(enum iomux_pins pin, u32 config)
134 pin &= IOMUX_PADNUM_MASK;
135 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
136 field = (pin + 2) % 3;
139 l &= ~(0x1ff << (field * 10));
140 l |= config << (field * 10);
145 void mx31_set_gpr(enum iomux_gp_func gp, char en)
148 struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
150 l = readl(&iomuxc->gpr);
156 writel(l, &iomuxc->gpr);
159 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
161 struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
162 struct mx31_weim_cscr *cscr = &weim->cscr[cs];
164 writel(weimcs->upper, &cscr->upper);
165 writel(weimcs->lower, &cscr->lower);
166 writel(weimcs->additional, &cscr->additional);
169 struct mx3_cpu_type mx31_cpu_type[] = {
170 { .srev = 0x00, .v = 0x10 },
171 { .srev = 0x10, .v = 0x11 },
172 { .srev = 0x11, .v = 0x11 },
173 { .srev = 0x12, .v = 0x1F },
174 { .srev = 0x13, .v = 0x1F },
175 { .srev = 0x14, .v = 0x12 },
176 { .srev = 0x15, .v = 0x12 },
177 { .srev = 0x28, .v = 0x20 },
178 { .srev = 0x29, .v = 0x20 },
181 u32 get_cpu_rev(void)
185 /* read SREV register from IIM module */
186 struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
187 srev = readl(&iim->iim_srev);
189 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
190 if (srev == mx31_cpu_type[i].srev)
191 return mx31_cpu_type[i].v;
193 return srev | 0x8000;
196 static char *get_reset_cause(void)
198 /* read RCSR register from CCM module */
199 struct clock_control_regs *ccm =
200 (struct clock_control_regs *)CCM_BASE;
202 u32 cause = readl(&ccm->rcsr) & 0x07;
214 return "ARM11P power gating";
216 return "unknown reset";
220 #if defined(CONFIG_DISPLAY_CPUINFO)
221 int print_cpuinfo(void)
223 u32 srev = get_cpu_rev();
225 printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
226 (srev & 0xF0) >> 4, (srev & 0x0F),
227 ((srev & 0x8000) ? " unknown" : ""),
228 mx31_get_mcu_main_clk() / 1000000);
229 printf("Reset cause: %s\n", get_reset_cause());