3 * Sascha Hauer, Pengutronix
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/clock.h>
29 #include <asm/arch/sys_proto.h>
31 static u32 mx31_decode_pll(u32 reg, u32 infreq)
33 u32 mfi = GET_PLL_MFI(reg);
34 s32 mfn = GET_PLL_MFN(reg);
35 u32 mfd = GET_PLL_MFD(reg);
36 u32 pd = GET_PLL_PD(reg);
38 mfi = mfi <= 5 ? 5 : mfi;
39 mfn = mfn >= 512 ? mfn - 1024 : mfn;
43 return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
47 static u32 mx31_get_mpl_dpdgck_clk(void)
51 if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
52 infreq = MXC_CLK32 * 1024;
56 return mx31_decode_pll(readl(CCM_MPCTL), infreq);
59 static u32 mx31_get_mcu_main_clk(void)
61 /* For now we assume mpl_dpdgck_clk == mcu_main_clk
62 * which should be correct for most boards
64 return mx31_get_mpl_dpdgck_clk();
67 static u32 mx31_get_ipg_clk(void)
69 u32 freq = mx31_get_mcu_main_clk();
70 u32 pdr0 = readl(CCM_PDR0);
72 freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
73 freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
78 /* hsp is the clock for the ipu */
79 static u32 mx31_get_hsp_clk(void)
81 u32 freq = mx31_get_mcu_main_clk();
82 u32 pdr0 = readl(CCM_PDR0);
84 freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
89 void mx31_dump_clocks(void)
91 u32 cpufreq = mx31_get_mcu_main_clk();
92 printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
93 printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
94 printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
97 unsigned int mxc_get_clock(enum mxc_clock clk)
101 return mx31_get_mcu_main_clk();
108 return mx31_get_ipg_clk();
110 return mx31_get_hsp_clk();
115 u32 imx_get_uartclk(void)
117 return mxc_get_clock(MXC_UART_CLK);
120 void mx31_gpio_mux(unsigned long mode)
122 unsigned long reg, shift, tmp;
124 reg = IOMUXC_BASE + (mode & 0x1fc);
125 shift = (~mode & 0x3) * 8;
128 tmp &= ~(0xff << shift);
129 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
133 void mx31_set_pad(enum iomux_pins pin, u32 config)
137 pin &= IOMUX_PADNUM_MASK;
138 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
139 field = (pin + 2) % 3;
142 l &= ~(0x1ff << (field * 10));
143 l |= config << (field * 10);
148 void mx31_set_gpr(enum iomux_gp_func gp, char en)
151 struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
153 l = readl(&iomuxc->gpr);
159 writel(l, &iomuxc->gpr);
162 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
164 struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
165 struct mx31_weim_cscr *cscr = &weim->cscr[cs];
167 writel(weimcs->upper, &cscr->upper);
168 writel(weimcs->lower, &cscr->lower);
169 writel(weimcs->additional, &cscr->additional);
172 struct mx3_cpu_type mx31_cpu_type[] = {
173 { .srev = 0x00, .v = 0x10 },
174 { .srev = 0x10, .v = 0x11 },
175 { .srev = 0x11, .v = 0x11 },
176 { .srev = 0x12, .v = 0x1F },
177 { .srev = 0x13, .v = 0x1F },
178 { .srev = 0x14, .v = 0x12 },
179 { .srev = 0x15, .v = 0x12 },
180 { .srev = 0x28, .v = 0x20 },
181 { .srev = 0x29, .v = 0x20 },
184 u32 get_cpu_rev(void)
188 /* read SREV register from IIM module */
189 struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
190 srev = readl(&iim->iim_srev);
192 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
193 if (srev == mx31_cpu_type[i].srev)
194 return mx31_cpu_type[i].v;
196 return srev | 0x8000;
199 static char *get_reset_cause(void)
201 /* read RCSR register from CCM module */
202 struct clock_control_regs *ccm =
203 (struct clock_control_regs *)CCM_BASE;
205 u32 cause = readl(&ccm->rcsr) & 0x07;
217 return "ARM11P power gating";
219 return "unknown reset";
223 #if defined(CONFIG_DISPLAY_CPUINFO)
224 int print_cpuinfo(void)
226 u32 srev = get_cpu_rev();
228 printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
229 (srev & 0xF0) >> 4, (srev & 0x0F),
230 ((srev & 0x8000) ? " unknown" : ""),
231 mx31_get_mcu_main_clk() / 1000000);
232 printf("Reset cause: %s\n", get_reset_cause());