2 * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/errno.h>
25 #include <asm/arch/imx-regs.h>
26 #include <linux/types.h>
27 #include <asm/arch/sys_proto.h>
29 #define ESDCTL_DDR2_EMR2 0x04000000
30 #define ESDCTL_DDR2_EMR3 0x06000000
31 #define ESDCTL_PRECHARGE 0x00000400
32 #define ESDCTL_DDR2_EN_DLL 0x02000400
33 #define ESDCTL_DDR2_RESET_DLL 0x00000333
34 #define ESDCTL_DDR2_MR 0x00000233
35 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
45 #define set_mode(x, en, m) (x | (en << 31) | (m << 28))
47 static inline void dram_wait(unsigned int count)
49 volatile unsigned int wait = count;
56 void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
57 u32 row, u32 col, u32 dsize, u32 refresh)
59 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
60 u32 *cfg_reg, *ctl_reg;
64 switch (start_address) {
66 cfg_reg = &esdc->esdcfg0;
67 ctl_reg = &esdc->esdctl0;
70 cfg_reg = &esdc->esdcfg1;
71 ctl_reg = &esdc->esdctl1;
77 /* The MX35 supports 11 up to 14 rows */
78 if (row < 11 || row > 14 || col < 8 || col > 10)
80 ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
82 /* Initialize MISC register for DDR2 */
83 val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
84 ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
85 writel(val, &esdc->esdmisc);
86 val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
87 writel(val, &esdc->esdmisc);
90 * according to DDR2 specs, wait a while before
91 * the PRECHARGE_ALL command
95 /* Load DDR2 config and timing */
96 writel(ddr2_config, cfg_reg);
99 writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
101 writel(0xda, start_address + ESDCTL_PRECHARGE);
104 writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
106 writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
107 writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
108 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
109 writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
112 writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
114 writel(0xda, start_address + ESDCTL_PRECHARGE);
116 /* Set mode auto refresh : at least two refresh are required */
117 writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
119 writel(0xda, start_address);
120 writel(0xda, start_address);
122 writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
124 writeb(0xda, start_address + ESDCTL_DDR2_MR);
125 writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
128 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
130 /* Set normal mode */
131 writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
136 /* Do not set delay lines, only for MDDR */