2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm-offsets.h>
36 #ifdef CONFIG_SPL_BUILD
53 .word 0x12345678 /* now 16*4=64 */
55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort
63 _undefined_instruction: .word undefined_instruction
64 _software_interrupt: .word software_interrupt
65 _prefetch_abort: .word prefetch_abort
66 _data_abort: .word data_abort
67 _not_used: .word not_used
70 _pad: .word 0x12345678 /* now 16*4=64 */
71 #endif /* CONFIG_SPL_BUILD */
75 .balignl 16,0xdeadbeef
77 *************************************************************************
79 * Startup Code (reset vector)
81 * do important init only if we don't start from memory!
82 * setup Memory and board specific bits prior to relocation.
83 * relocate armboot to ram
86 *************************************************************************
91 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
92 .word CONFIG_SPL_TEXT_BASE
94 .word CONFIG_SYS_TEXT_BASE
98 * These are defined in the board-specific linker script.
99 * Subtracting _start from them lets the linker put their
100 * relative position in the executable instead of leaving
103 .globl _bss_start_ofs
105 .word __bss_start - _start
109 .word __bss_end - _start
115 #ifdef CONFIG_USE_IRQ
116 /* IRQ stack memory (calculated at run-time) */
117 .globl IRQ_STACK_START
121 /* IRQ stack memory (calculated at run-time) */
122 .globl FIQ_STACK_START
127 /* IRQ stack memory (calculated at run-time) + 8 bytes */
128 .globl IRQ_STACK_START_IN
133 * the actual reset code
138 * set the cpu to SVC32 mode
145 #ifdef CONFIG_OMAP2420H4
146 /* Copy vectors to mask ROM indirect addr */
147 adr r0, _start /* r0 <- current position of code */
148 add r0, r0, #4 /* skip reset vector */
149 mov r2, #64 /* r2 <- size to copy */
150 add r2, r0, r2 /* r2 <- source end address */
151 mov r1, #SRAM_OFFSET0 /* build vect addr */
152 mov r3, #SRAM_OFFSET1
154 mov r3, #SRAM_OFFSET2
157 ldmia r0!, {r3-r10} /* copy from source address [r0] */
158 stmia r1!, {r3-r10} /* copy to target address [r1] */
159 cmp r0, r2 /* until source end address [r2] */
160 bne next /* loop until equal */
161 bl cpy_clk_code /* put dpll adjust code behind vectors */
163 /* the mask ROM code should have PLL and others stable */
164 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
170 /*------------------------------------------------------------------------------*/
172 .globl c_runtime_cpu_setup
178 *************************************************************************
180 * CPU_init_critical registers
182 * setup important registers
183 * setup memory timing
185 *************************************************************************
187 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
190 * flush v4 I/D caches
193 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
194 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
197 * disable MMU stuff and caches
199 mrc p15, 0, r0, c1, c0, 0
200 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
201 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
202 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
203 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
204 mcr p15, 0, r0, c1, c0, 0
207 * Jump to board specific initialization... The Mask ROM will have already initialized
208 * basic memory. Go here to bump up clock rate and handle wake up conditions.
210 mov ip, lr /* persevere link reg across call */
211 bl lowlevel_init /* go setup pll,mux,memory */
212 mov lr, ip /* restore link */
213 mov pc, lr /* back to my caller */
214 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
216 #ifndef CONFIG_SPL_BUILD
218 *************************************************************************
222 *************************************************************************
227 #define S_FRAME_SIZE 72
249 #define MODE_SVC 0x13
253 * use bad_save_user_regs for abort/prefetch/undef/swi ...
254 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
257 .macro bad_save_user_regs
258 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
259 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
261 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
262 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
263 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
267 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
268 mov r0, sp @ save current stack into r0 (param register)
271 .macro irq_save_user_regs
272 sub sp, sp, #S_FRAME_SIZE
273 stmia sp, {r0 - r12} @ Calling r0-r12
274 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
275 stmdb r8, {sp, lr}^ @ Calling SP, LR
276 str lr, [r8, #0] @ Save calling PC
278 str r6, [r8, #4] @ Save CPSR
279 str r0, [r8, #8] @ Save OLD_R0
283 .macro irq_restore_user_regs
284 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
286 ldr lr, [sp, #S_PC] @ Get PC
287 add sp, sp, #S_FRAME_SIZE
288 subs pc, lr, #4 @ return & move spsr_svc into cpsr
292 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
294 str lr, [r13] @ save caller lr in position 0 of saved stack
295 mrs lr, spsr @ get the spsr
296 str lr, [r13, #4] @ save spsr in position 1 of saved stack
298 mov r13, #MODE_SVC @ prepare SVC-Mode
300 msr spsr, r13 @ switch modes, make sure moves will execute
301 mov lr, pc @ capture return pc
302 movs pc, lr @ jump to next instruction & switch modes.
305 .macro get_bad_stack_swi
306 sub r13, r13, #4 @ space on current stack for scratch reg.
307 str r0, [r13] @ save R0's value.
308 ldr r0, IRQ_STACK_START_IN @ get data regions start
309 str lr, [r0] @ save caller lr in position 0 of saved stack
310 mrs lr, spsr @ get the spsr
311 str lr, [r0, #4] @ save spsr in position 1 of saved stack
312 ldr lr, [r0] @ restore lr
313 ldr r0, [r13] @ restore r0
314 add r13, r13, #4 @ pop stack entry
317 .macro get_irq_stack @ setup IRQ stack
318 ldr sp, IRQ_STACK_START
321 .macro get_fiq_stack @ setup FIQ stack
322 ldr sp, FIQ_STACK_START
324 #endif /* CONFIG_SPL_BUILD */
329 #ifdef CONFIG_SPL_BUILD
332 ldr sp, _TEXT_BASE /* use 32 words about stack */
333 bl hang /* hang and never return */
334 #else /* !CONFIG_SPL_BUILD */
336 undefined_instruction:
339 bl do_undefined_instruction
345 bl do_software_interrupt
365 #ifdef CONFIG_USE_IRQ
372 irq_restore_user_regs
377 /* someone ought to write a more effiction fiq_save_user_regs */
380 irq_restore_user_regs
398 .global arm1136_cache_flush
400 #if !defined(CONFIG_SYS_ICACHE_OFF)
401 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
403 #if !defined(CONFIG_SYS_DCACHE_OFF)
404 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
406 mov pc, lr @ back to caller
407 #endif /* CONFIG_SPL_BUILD */