2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm-offsets.h>
20 #ifdef CONFIG_SPL_BUILD
37 .word 0x12345678 /* now 16*4=64 */
39 ldr pc, _undefined_instruction
40 ldr pc, _software_interrupt
41 ldr pc, _prefetch_abort
47 _undefined_instruction: .word undefined_instruction
48 _software_interrupt: .word software_interrupt
49 _prefetch_abort: .word prefetch_abort
50 _data_abort: .word data_abort
51 _not_used: .word not_used
54 _pad: .word 0x12345678 /* now 16*4=64 */
55 #endif /* CONFIG_SPL_BUILD */
59 .balignl 16,0xdeadbeef
61 *************************************************************************
63 * Startup Code (reset vector)
65 * do important init only if we don't start from memory!
66 * setup Memory and board specific bits prior to relocation.
67 * relocate armboot to ram
70 *************************************************************************
74 /* IRQ stack memory (calculated at run-time) */
75 .globl IRQ_STACK_START
79 /* IRQ stack memory (calculated at run-time) */
80 .globl FIQ_STACK_START
85 /* IRQ stack memory (calculated at run-time) + 8 bytes */
86 .globl IRQ_STACK_START_IN
91 * the actual reset code
96 * set the cpu to SVC32 mode
103 /* the mask ROM code should have PLL and others stable */
104 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
110 /*------------------------------------------------------------------------------*/
112 .globl c_runtime_cpu_setup
118 *************************************************************************
120 * CPU_init_critical registers
122 * setup important registers
123 * setup memory timing
125 *************************************************************************
127 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
130 * flush v4 I/D caches
133 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
134 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
137 * disable MMU stuff and caches
139 mrc p15, 0, r0, c1, c0, 0
140 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
141 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
142 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
143 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
144 mcr p15, 0, r0, c1, c0, 0
147 * Jump to board specific initialization... The Mask ROM will have already initialized
148 * basic memory. Go here to bump up clock rate and handle wake up conditions.
150 mov ip, lr /* persevere link reg across call */
151 bl lowlevel_init /* go setup pll,mux,memory */
152 mov lr, ip /* restore link */
153 mov pc, lr /* back to my caller */
154 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
156 #ifndef CONFIG_SPL_BUILD
158 *************************************************************************
162 *************************************************************************
167 #define S_FRAME_SIZE 72
189 #define MODE_SVC 0x13
193 * use bad_save_user_regs for abort/prefetch/undef/swi ...
194 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
197 .macro bad_save_user_regs
198 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
199 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
201 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
202 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
203 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
207 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
208 mov r0, sp @ save current stack into r0 (param register)
211 .macro irq_save_user_regs
212 sub sp, sp, #S_FRAME_SIZE
213 stmia sp, {r0 - r12} @ Calling r0-r12
214 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
215 stmdb r8, {sp, lr}^ @ Calling SP, LR
216 str lr, [r8, #0] @ Save calling PC
218 str r6, [r8, #4] @ Save CPSR
219 str r0, [r8, #8] @ Save OLD_R0
223 .macro irq_restore_user_regs
224 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
226 ldr lr, [sp, #S_PC] @ Get PC
227 add sp, sp, #S_FRAME_SIZE
228 subs pc, lr, #4 @ return & move spsr_svc into cpsr
232 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
234 str lr, [r13] @ save caller lr in position 0 of saved stack
235 mrs lr, spsr @ get the spsr
236 str lr, [r13, #4] @ save spsr in position 1 of saved stack
238 mov r13, #MODE_SVC @ prepare SVC-Mode
240 msr spsr, r13 @ switch modes, make sure moves will execute
241 mov lr, pc @ capture return pc
242 movs pc, lr @ jump to next instruction & switch modes.
245 .macro get_bad_stack_swi
246 sub r13, r13, #4 @ space on current stack for scratch reg.
247 str r0, [r13] @ save R0's value.
248 ldr r0, IRQ_STACK_START_IN @ get data regions start
249 str lr, [r0] @ save caller lr in position 0 of saved stack
250 mrs lr, spsr @ get the spsr
251 str lr, [r0, #4] @ save spsr in position 1 of saved stack
252 ldr lr, [r0] @ restore lr
253 ldr r0, [r13] @ restore r0
254 add r13, r13, #4 @ pop stack entry
257 .macro get_irq_stack @ setup IRQ stack
258 ldr sp, IRQ_STACK_START
261 .macro get_fiq_stack @ setup FIQ stack
262 ldr sp, FIQ_STACK_START
264 #endif /* CONFIG_SPL_BUILD */
269 #ifdef CONFIG_SPL_BUILD
272 bl hang /* hang and never return */
273 #else /* !CONFIG_SPL_BUILD */
275 undefined_instruction:
278 bl do_undefined_instruction
284 bl do_software_interrupt
304 #ifdef CONFIG_USE_IRQ
311 irq_restore_user_regs
316 /* someone ought to write a more effiction fiq_save_user_regs */
319 irq_restore_user_regs
336 #endif /* CONFIG_SPL_BUILD */