2 * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
5 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/s3c6400.h>
29 .globl mem_ctrl_asm_init
31 /* DMC1 base address 0x7e001000 */
32 ldr r0, =ELFIN_DMC1_BASE
35 str r1, [r0, #INDEX_DMC_MEMC_CMD]
37 ldr r1, =DMC_DDR_REFRESH_PRD
38 str r1, [r0, #INDEX_DMC_REFRESH_PRD]
40 ldr r1, =DMC_DDR_CAS_LATENCY
41 str r1, [r0, #INDEX_DMC_CAS_LATENCY]
43 ldr r1, =DMC_DDR_t_DQSS
44 str r1, [r0, #INDEX_DMC_T_DQSS]
46 ldr r1, =DMC_DDR_t_MRD
47 str r1, [r0, #INDEX_DMC_T_MRD]
49 ldr r1, =DMC_DDR_t_RAS
50 str r1, [r0, #INDEX_DMC_T_RAS]
53 str r1, [r0, #INDEX_DMC_T_RC]
55 ldr r1, =DMC_DDR_t_RCD
56 ldr r2, =DMC_DDR_schedule_RCD
58 str r1, [r0, #INDEX_DMC_T_RCD]
60 ldr r1, =DMC_DDR_t_RFC
61 ldr r2, =DMC_DDR_schedule_RFC
63 str r1, [r0, #INDEX_DMC_T_RFC]
66 ldr r2, =DMC_DDR_schedule_RP
68 str r1, [r0, #INDEX_DMC_T_RP]
70 ldr r1, =DMC_DDR_t_RRD
71 str r1, [r0, #INDEX_DMC_T_RRD]
74 str r1, [r0, #INDEX_DMC_T_WR]
76 ldr r1, =DMC_DDR_t_WTR
77 str r1, [r0, #INDEX_DMC_T_WTR]
80 str r1, [r0, #INDEX_DMC_T_XP]
82 ldr r1, =DMC_DDR_t_XSR
83 str r1, [r0, #INDEX_DMC_T_XSR]
85 ldr r1, =DMC_DDR_t_ESR
86 str r1, [r0, #INDEX_DMC_T_ESR]
89 str r1, [r0, #INDEX_DMC_MEMORY_CFG]
91 ldr r1, =DMC1_MEM_CFG2
92 str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
94 ldr r1, =DMC1_CHIP0_CFG
95 str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
97 ldr r1, =DMC_DDR_32_CFG
98 str r1, [r0, #INDEX_DMC_USER_CONFIG]
100 /* DMC0 DDR Chip 0 configuration direct command reg */
102 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
106 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
108 /* Auto Refresh 2 time */
110 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
111 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
114 ldr r1, =DMC_mDDR_EMR0
115 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
118 ldr r1, =DMC_mDDR_MR0
119 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
123 str r1, [r0, #INDEX_DMC_MEMC_CMD]
126 ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]