2 * armboot - Startup Code for ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * SPDX-License-Identifier: GPL-2.0+
11 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
12 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
13 * jsgood (jsgood.yang@samsung.com)
14 * Base codes by scsuh (sc.suh)
17 #include <asm-offsets.h>
21 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
22 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
26 *************************************************************************
28 * Jump vector table as in table 3.1 in [1]
30 *************************************************************************
35 #ifndef CONFIG_SPL_BUILD
36 ldr pc, _undefined_instruction
37 ldr pc, _software_interrupt
38 ldr pc, _prefetch_abort
44 _undefined_instruction:
45 .word undefined_instruction
47 .word software_interrupt
59 .word 0x12345678 /* now 16*4=64 */
66 .balignl 16,0xdeadbeef
68 *************************************************************************
70 * Startup Code (reset vector)
72 * do important init only if we don't start from memory!
73 * setup Memory and board specific bits prior to relocation.
74 * relocate armboot to ram
77 *************************************************************************
80 /* IRQ stack memory (calculated at run-time) + 8 bytes */
81 .globl IRQ_STACK_START_IN
86 * the actual reset code
91 * set the cpu to SVC32 mode
99 *************************************************************************
101 * CPU_init_critical registers
103 * setup important registers
104 * setup memory timing
106 *************************************************************************
109 * we do sys-critical inits only at reboot,
110 * not when booting from ram!
114 * When booting from NAND - it has definitely been a reset, so, no need
115 * to flush caches and disable the MMU
117 #ifndef CONFIG_SPL_BUILD
119 * flush v4 I/D caches
122 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
123 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
126 * disable MMU stuff and caches
128 mrc p15, 0, r0, c1, c0, 0
129 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
130 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
131 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
132 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
134 /* Prepare to disable the MMU */
135 adr r2, mmu_disable_phys
136 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
140 /* Run in a single cache-line */
142 mcr p15, 0, r0, c1, c0, 0
148 #ifdef CONFIG_DISABLE_TCM
152 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
158 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
160 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
165 #ifdef CONFIG_PERIPORT_REMAP
166 /* Peri port setup */
167 ldr r0, =CONFIG_PERIPORT_BASE
168 orr r0, r0, #CONFIG_PERIPORT_SIZE
169 mcr p15,0,r0,c15,c2,4
173 * Go setup Memory and board specific bits prior to relocation.
175 bl lowlevel_init /* go setup pll,mux,memory */
179 /*------------------------------------------------------------------------------*/
181 .globl c_runtime_cpu_setup
186 #ifndef CONFIG_SPL_BUILD
188 *************************************************************************
192 *************************************************************************
197 #define S_FRAME_SIZE 72
219 #define MODE_SVC 0x13
223 * use bad_save_user_regs for abort/prefetch/undef/swi ...
226 .macro bad_save_user_regs
227 /* carve out a frame on current user stack */
228 sub sp, sp, #S_FRAME_SIZE
229 /* Save user registers (now in svc mode) r0-r12 */
232 ldr r2, IRQ_STACK_START_IN
233 /* get values for "aborted" pc and cpsr (into parm regs) */
235 /* grab pointer to old stack */
236 add r0, sp, #S_FRAME_SIZE
240 /* save sp_SVC, lr_SVC, pc, cpsr */
242 /* save current stack into r0 (param register) */
247 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
249 /* save caller lr in position 0 of saved stack */
253 /* save spsr in position 1 of saved stack */
256 /* prepare SVC-Mode */
259 /* switch modes, make sure moves will execute */
261 /* capture return pc */
263 /* jump to next instruction & switch modes. */
267 .macro get_bad_stack_swi
268 /* space on current stack for scratch reg. */
270 /* save R0's value. */
272 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
273 /* save caller lr in position 0 of saved stack */
277 /* save spsr in position 1 of saved stack */
283 /* pop stack entry */
291 undefined_instruction:
294 bl do_undefined_instruction
300 bl do_software_interrupt
331 #endif /* CONFIG_SPL_BUILD */