2 * armboot - Startup Code for ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
29 * jsgood (jsgood.yang@samsung.com)
30 * Base codes by scsuh (sc.suh)
33 #include <asm-offsets.h>
37 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
38 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
42 *************************************************************************
44 * Jump vector table as in table 3.1 in [1]
46 *************************************************************************
51 #ifndef CONFIG_SPL_BUILD
52 ldr pc, _undefined_instruction
53 ldr pc, _software_interrupt
54 ldr pc, _prefetch_abort
60 _undefined_instruction:
61 .word undefined_instruction
63 .word software_interrupt
75 .word 0x12345678 /* now 16*4=64 */
82 .balignl 16,0xdeadbeef
84 *************************************************************************
86 * Startup Code (reset vector)
88 * do important init only if we don't start from memory!
89 * setup Memory and board specific bits prior to relocation.
90 * relocate armboot to ram
93 *************************************************************************
98 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
99 .word CONFIG_SPL_TEXT_BASE
101 .word CONFIG_SYS_TEXT_BASE
105 * These are defined in the board-specific linker script.
106 * Subtracting _start from them lets the linker put their
107 * relative position in the executable instead of leaving
111 .globl _bss_start_ofs
113 .word __bss_start - _start
115 .globl _image_copy_end_ofs
117 .word __image_copy_end - _start
121 .word __bss_end - _start
127 /* IRQ stack memory (calculated at run-time) + 8 bytes */
128 .globl IRQ_STACK_START_IN
133 * the actual reset code
138 * set the cpu to SVC32 mode
146 *************************************************************************
148 * CPU_init_critical registers
150 * setup important registers
151 * setup memory timing
153 *************************************************************************
156 * we do sys-critical inits only at reboot,
157 * not when booting from ram!
161 * When booting from NAND - it has definitely been a reset, so, no need
162 * to flush caches and disable the MMU
164 #ifndef CONFIG_SPL_BUILD
166 * flush v4 I/D caches
169 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
170 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
173 * disable MMU stuff and caches
175 mrc p15, 0, r0, c1, c0, 0
176 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
177 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
178 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
179 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
181 /* Prepare to disable the MMU */
182 adr r2, mmu_disable_phys
183 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
187 /* Run in a single cache-line */
189 mcr p15, 0, r0, c1, c0, 0
195 #ifdef CONFIG_DISABLE_TCM
199 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
205 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
207 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
212 #ifdef CONFIG_PERIPORT_REMAP
213 /* Peri port setup */
214 ldr r0, =CONFIG_PERIPORT_BASE
215 orr r0, r0, #CONFIG_PERIPORT_SIZE
216 mcr p15,0,r0,c15,c2,4
220 * Go setup Memory and board specific bits prior to relocation.
222 bl lowlevel_init /* go setup pll,mux,memory */
226 /*------------------------------------------------------------------------------*/
229 * void relocate_code(addr_moni)
231 * This function relocates the monitor code.
235 mov r6, r0 /* save addr of destination */
238 subs r9, r6, r0 /* r9 <- relocation offset */
239 beq relocate_done /* skip relocation */
240 mov r1, r6 /* r1 <- scratch for copy_loop */
241 ldr r3, _image_copy_end_ofs
242 add r2, r0, r3 /* r2 <- source end address */
245 ldmia r0!, {r10-r11} /* copy from source address [r0] */
246 stmia r1!, {r10-r11} /* copy to target address [r1] */
247 cmp r0, r2 /* until source end address [r2] */
250 #ifndef CONFIG_SPL_BUILD
252 * fix .rel.dyn relocations
254 ldr r0, _TEXT_BASE /* r0 <- Text base */
255 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
256 add r10, r10, r0 /* r10 <- sym table in FLASH */
257 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
258 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
259 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
260 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
262 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
263 add r0, r0, r9 /* r0 <- location to fix up in RAM */
266 cmp r7, #23 /* relative fixup? */
268 cmp r7, #2 /* absolute fixup? */
270 /* ignore unknown type of fixup */
273 /* absolute fix: set location to (offset) symbol value */
274 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
275 add r1, r10, r1 /* r1 <- address of symbol in table */
276 ldr r1, [r1, #4] /* r1 <- symbol value */
277 add r1, r1, r9 /* r1 <- relocated sym addr */
280 /* relative fix: increase location by offset */
285 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
295 .word __rel_dyn_start - _start
297 .word __rel_dyn_end - _start
299 .word __dynsym_start - _start
301 .globl c_runtime_cpu_setup
306 #ifndef CONFIG_SPL_BUILD
308 *************************************************************************
312 *************************************************************************
317 #define S_FRAME_SIZE 72
339 #define MODE_SVC 0x13
343 * use bad_save_user_regs for abort/prefetch/undef/swi ...
346 .macro bad_save_user_regs
347 /* carve out a frame on current user stack */
348 sub sp, sp, #S_FRAME_SIZE
349 /* Save user registers (now in svc mode) r0-r12 */
352 ldr r2, IRQ_STACK_START_IN
353 /* get values for "aborted" pc and cpsr (into parm regs) */
355 /* grab pointer to old stack */
356 add r0, sp, #S_FRAME_SIZE
360 /* save sp_SVC, lr_SVC, pc, cpsr */
362 /* save current stack into r0 (param register) */
367 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
369 /* save caller lr in position 0 of saved stack */
373 /* save spsr in position 1 of saved stack */
376 /* prepare SVC-Mode */
379 /* switch modes, make sure moves will execute */
381 /* capture return pc */
383 /* jump to next instruction & switch modes. */
387 .macro get_bad_stack_swi
388 /* space on current stack for scratch reg. */
390 /* save R0's value. */
392 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
393 /* save caller lr in position 0 of saved stack */
397 /* save spsr in position 1 of saved stack */
403 /* pop stack entry */
411 undefined_instruction:
414 bl do_undefined_instruction
420 bl do_software_interrupt
451 #endif /* CONFIG_SPL_BUILD */