2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */
54 _undefined_instruction: .word undefined_instruction
55 _software_interrupt: .word software_interrupt
56 _prefetch_abort: .word prefetch_abort
57 _data_abort: .word data_abort
58 _not_used: .word not_used
62 .balignl 16,0xdeadbeef
66 *************************************************************************
68 * Startup Code (reset vector)
70 * do important init only if we don't start from RAM!
71 * relocate armboot to ram
73 * jump to second stage
75 *************************************************************************
82 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
89 * These are defined in the board-specific linker script.
100 /* IRQ stack memory (calculated at run-time) */
101 .globl IRQ_STACK_START
105 /* IRQ stack memory (calculated at run-time) */
106 .globl FIQ_STACK_START
111 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
112 /* IRQ stack memory (calculated at run-time) + 8 bytes */
113 .globl IRQ_STACK_START_IN
117 .globl _datarel_start
119 .word __datarel_start
121 .globl _datarelrolocal_start
122 _datarelrolocal_start:
123 .word __datarelrolocal_start
125 .globl _datarellocal_start
127 .word __datarellocal_start
129 .globl _datarelro_start
131 .word __datarelro_start
142 * the actual reset code
147 * set the cpu to SVC32 mode
155 * we do sys-critical inits only at reboot,
156 * not when booting from ram!
158 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
162 #ifdef CONFIG_LPC2292
166 /* Set stackpointer in internal RAM to call board_init_f */
168 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
172 /*------------------------------------------------------------------------------*/
175 * void relocate_code (addr_sp, gd, addr_moni)
177 * This "function" does not return, instead it continues in RAM
178 * after relocating the monitor code.
183 mov r4, r0 /* save addr_sp */
184 mov r5, r1 /* save addr of gd */
185 mov r6, r2 /* save addr of destination */
186 mov r7, r2 /* save addr of destination */
188 /* Set up the stack */
195 sub r2, r3, r2 /* r2 <- size of armboot */
196 add r2, r0, r2 /* r2 <- source end address */
200 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
202 ldmia r0!, {r9-r10} /* copy from source address [r0] */
203 stmia r6!, {r9-r10} /* copy to target address [r1] */
204 cmp r0, r2 /* until source end addreee [r2] */
207 #ifndef CONFIG_PRELOADER
208 /* fix got entries */
209 ldr r1, _TEXT_BASE /* Text base */
210 mov r0, r7 /* reloc addr */
211 ldr r2, _got_start /* addr in Flash */
212 ldr r3, _got_end /* addr in Flash */
227 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
230 #ifndef CONFIG_PRELOADER
233 ldr r3, _TEXT_BASE /* Text base */
234 mov r4, r7 /* reloc addr */
239 mov r2, #0x00000000 /* clear */
241 clbss_l:str r2, [r0] /* clear loop... */
251 * We are done. Do not return, instead branch to second part of board
252 * initialization, now running from RAM.
255 ldr r2, _board_init_r
257 add r2, r2, r7 /* position from board_init_r in RAM */
258 /* setup parameters for board_init_r */
259 mov r0, r5 /* gd_t */
260 mov r1, r7 /* dest_addr */
265 _board_init_r: .word board_init_r
267 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
270 * the actual reset code
275 * set the cpu to SVC32 mode
283 * we do sys-critical inits only at reboot,
284 * not when booting from ram!
286 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
290 #ifdef CONFIG_LPC2292
294 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
295 relocate: /* relocate U-Boot to RAM */
296 adr r0, _start /* r0 <- current position of code */
297 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
298 cmp r0, r1 /* don't reloc during debug */
302 #ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
303 ldr r2, =0x0 /* Relocate the exception vectors */
304 cmp r1, r2 /* and associated data to address */
305 ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */
306 stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */
309 adrne r0, _start /* restore r0 */
310 #endif /* !CONFIG_LPC2292 */
313 ldr r2, _armboot_start
315 sub r2, r3, r2 /* r2 <- size of armboot */
316 add r2, r0, r2 /* r2 <- source end address */
319 ldmia r0!, {r3-r10} /* copy from source address [r0] */
320 stmia r1!, {r3-r10} /* copy to target address [r1] */
321 cmp r0, r2 /* until source end addreee [r2] */
324 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
326 /* Set up the stack */
328 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
329 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
330 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
331 #ifdef CONFIG_USE_IRQ
332 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
334 sub sp, r0, #12 /* leave 3 words for abort-stack */
335 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
338 ldr r0, _bss_start /* find start of bss segment */
339 ldr r1, _bss_end /* stop here */
340 mov r2, #0x00000000 /* clear */
342 clbss_l:str r2, [r0] /* clear loop... */
347 ldr pc, _start_armboot
349 _start_armboot: .word start_armboot
351 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
354 *************************************************************************
356 * CPU_init_critical registers
358 * setup important registers
359 * setup memory timing
361 *************************************************************************
364 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
366 /* Interupt-Controller base addresses */
367 INTMR1: .word 0x80000280 @ 32 bit size
368 INTMR2: .word 0x80001280 @ 16 bit size
369 INTMR3: .word 0x80002280 @ 8 bit size
372 SYSCON1: .word 0x80000100
373 SYSCON2: .word 0x80001100
374 SYSCON3: .word 0x80002200
376 #define CLKCTL 0x6 /* mask */
377 #define CLKCTL_18 0x0 /* 18.432 MHz */
378 #define CLKCTL_36 0x2 /* 36.864 MHz */
379 #define CLKCTL_49 0x4 /* 49.152 MHz */
380 #define CLKCTL_73 0x6 /* 73.728 MHz */
382 #elif defined(CONFIG_LPC2292)
383 PLLCFG_ADR: .word PLLCFG
384 PLLFEED_ADR: .word PLLFEED
385 PLLCON_ADR: .word PLLCON
386 PLLSTAT_ADR: .word PLLSTAT
387 VPBDIV_ADR: .word VPBDIV
388 MEMMAP_ADR: .word MEMMAP
393 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
396 * mask all IRQs by clearing all bits in the INTMRs
407 * flush v4 I/D caches
410 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
411 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
414 * disable MMU stuff and caches
417 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
418 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
419 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
421 #elif defined(CONFIG_NETARM)
423 * prior to software reset : need to set pin PORTC4 to be *HRESET
425 ldr r0, =NETARM_GEN_MODULE_BASE
426 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
427 NETARM_GEN_PORT_DIR(0x10))
428 str r1, [r0, #+NETARM_GEN_PORTC]
430 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
431 * for an explanation of this process
433 ldr r0, =NETARM_GEN_MODULE_BASE
434 ldr r1, =NETARM_GEN_SW_SVC_RESETA
435 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
436 ldr r1, =NETARM_GEN_SW_SVC_RESETB
437 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
438 ldr r1, =NETARM_GEN_SW_SVC_RESETA
439 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
440 ldr r1, =NETARM_GEN_SW_SVC_RESETB
441 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
443 * setup PLL and System Config
445 ldr r0, =NETARM_GEN_MODULE_BASE
447 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
448 NETARM_GEN_SYS_CFG_BUSFULL | \
449 NETARM_GEN_SYS_CFG_USER_EN | \
450 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
451 NETARM_GEN_SYS_CFG_BUSARB_INT | \
452 NETARM_GEN_SYS_CFG_BUSMON_EN )
454 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
456 #ifndef CONFIG_NETARM_PLL_BYPASS
457 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
458 NETARM_GEN_PLL_CTL_POLTST_DEF | \
459 NETARM_GEN_PLL_CTL_INDIV(1) | \
460 NETARM_GEN_PLL_CTL_ICP_DEF | \
461 NETARM_GEN_PLL_CTL_OUTDIV(2) )
462 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
466 * mask all IRQs by clearing all bits in the INTMRs
469 ldr r0, =NETARM_GEN_MODULE_BASE
470 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
472 #elif defined(CONFIG_S3C4510B)
475 * Mask off all IRQ sources
485 ldr r1, =0x83ffffa0 /* cache-disabled */
488 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
489 /* No specific initialisation for IntegratorAP/CM720T as yet */
490 #elif defined(CONFIG_LPC2292)
494 /* First disconnect and disable the PLL */
498 ldr r0, PLLFEED_ADR /* start feed sequence */
500 str r4, [r0] /* feed sequence done */
501 /* Set new M and P values */
503 mov r1, #0x23 /* M=4 and P=2 */
505 ldr r0, PLLFEED_ADR /* start feed sequence */
507 str r4, [r0] /* feed sequence done */
508 /* Then enable the PLL */
510 mov r1, #0x01 /* PLL enable bit */
512 ldr r0, PLLFEED_ADR /* start feed sequence */
514 str r4, [r0] /* feed sequence done */
515 /* Wait for the lock */
517 mov r1, #0x400 /* lock bit */
523 /* And finally connect the PLL */
525 mov r1, #0x03 /* PLL enable bit and connect bit */
527 ldr r0, PLLFEED_ADR /* start feed sequence */
529 str r4, [r0] /* feed sequence done */
530 /* Set-up VPBDIV register */
532 mov r1, #0x01 /* VPB clock is same as process clock */
535 #error No cpu_init_crit() defined for current CPU type
538 #ifdef CONFIG_ARM7_REVD
539 /* set clock speed */
540 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
541 /* !!! not doing DRAM refresh properly! */
545 orr r1, r1, #CLKCTL_36
549 #ifndef CONFIG_LPC2292
552 * before relocating, we have to setup RAM timing
553 * because memory timing is board-dependent, you will
554 * find a lowlevel_init.S in your board directory.
564 *************************************************************************
568 *************************************************************************
574 #define S_FRAME_SIZE 72
596 #define MODE_SVC 0x13
600 * use bad_save_user_regs for abort/prefetch/undef/swi ...
601 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
604 .macro bad_save_user_regs
605 sub sp, sp, #S_FRAME_SIZE
606 stmia sp, {r0 - r12} @ Calling r0-r12
609 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
610 ldr r2, _armboot_start
611 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
612 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
614 ldr r2, IRQ_STACK_START_IN
616 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
617 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
621 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
625 .macro irq_save_user_regs
626 sub sp, sp, #S_FRAME_SIZE
627 stmia sp, {r0 - r12} @ Calling r0-r12
629 stmdb r8, {sp, lr}^ @ Calling SP, LR
630 str lr, [r8, #0] @ Save calling PC
632 str r6, [r8, #4] @ Save CPSR
633 str r0, [r8, #8] @ Save OLD_R0
637 .macro irq_restore_user_regs
638 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
640 ldr lr, [sp, #S_PC] @ Get PC
641 add sp, sp, #S_FRAME_SIZE
642 subs pc, lr, #4 @ return & move spsr_svc into cpsr
646 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
647 ldr r13, _armboot_start @ setup our mode stack
648 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
649 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
651 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
654 str lr, [r13] @ save caller lr / spsr
658 mov r13, #MODE_SVC @ prepare SVC-Mode
664 .macro get_irq_stack @ setup IRQ stack
665 ldr sp, IRQ_STACK_START
668 .macro get_fiq_stack @ setup FIQ stack
669 ldr sp, FIQ_STACK_START
676 undefined_instruction:
679 bl do_undefined_instruction
685 bl do_software_interrupt
705 #ifdef CONFIG_USE_IRQ
712 irq_restore_user_regs
717 /* someone ought to write a more effiction fiq_save_user_regs */
720 irq_restore_user_regs
738 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
743 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
744 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
745 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
746 bic ip, ip, #0x000f @ ............wcam
747 bic ip, ip, #0x2100 @ ..v....s........
748 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
750 #elif defined(CONFIG_NETARM)
754 ldr r1, =NETARM_MEM_MODULE_BASE
755 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
758 ldr r1, =(relocate-TEXT_BASE)
760 ldr r4, =NETARM_GEN_MODULE_BASE
761 ldr r1, =NETARM_GEN_SW_SVC_RESETA
762 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
763 ldr r1, =NETARM_GEN_SW_SVC_RESETB
764 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
765 ldr r1, =NETARM_GEN_SW_SVC_RESETA
766 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
767 ldr r1, =NETARM_GEN_SW_SVC_RESETB
768 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
770 #elif defined(CONFIG_S3C4510B)
771 /* Nothing done here as reseting the CPU is board specific, depending
772 * on external peripherals such as watchdog timers, etc. */
773 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
774 /* No specific reset actions for IntegratorAP/CM720T as yet */
775 #elif defined(CONFIG_LPC2292)
781 #error No reset_cpu() defined for current CPU type