2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm-offsets.h>
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */
54 #ifdef CONFIG_SPL_BUILD
55 _undefined_instruction: .word _undefined_instruction
56 _software_interrupt: .word _software_interrupt
57 _prefetch_abort: .word _prefetch_abort
58 _data_abort: .word _data_abort
59 _not_used: .word _not_used
62 _pad: .word 0x12345678 /* now 16*4=64 */
64 _undefined_instruction: .word undefined_instruction
65 _software_interrupt: .word software_interrupt
66 _prefetch_abort: .word prefetch_abort
67 _data_abort: .word data_abort
68 _not_used: .word not_used
71 _pad: .word 0x12345678 /* now 16*4=64 */
72 #endif /* CONFIG_SPL_BUILD */
74 .balignl 16,0xdeadbeef
78 *************************************************************************
80 * Startup Code (reset vector)
82 * do important init only if we don't start from RAM!
83 * relocate armboot to ram
85 * jump to second stage
87 *************************************************************************
92 #ifdef CONFIG_SPL_BUILD
93 .word CONFIG_SPL_TEXT_BASE
95 .word CONFIG_SYS_TEXT_BASE
99 * These are defined in the board-specific linker script.
100 * Subtracting _start from them lets the linker put their
101 * relative position in the executable instead of leaving
104 .globl _bss_start_ofs
106 .word __bss_start - _start
110 .word __bss_end__ - _start
116 #ifdef CONFIG_USE_IRQ
117 /* IRQ stack memory (calculated at run-time) */
118 .globl IRQ_STACK_START
122 /* IRQ stack memory (calculated at run-time) */
123 .globl FIQ_STACK_START
128 /* IRQ stack memory (calculated at run-time) + 8 bytes */
129 .globl IRQ_STACK_START_IN
134 * the actual reset code
139 * set the cpu to SVC32 mode
147 * we do sys-critical inits only at reboot,
148 * not when booting from ram!
150 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
154 #ifdef CONFIG_LPC2292
158 /* Set stackpointer in internal RAM to call board_init_f */
160 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
161 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
165 /*------------------------------------------------------------------------------*/
168 * void relocate_code (addr_sp, gd, addr_moni)
170 * This "function" does not return, instead it continues in RAM
171 * after relocating the monitor code.
176 mov r4, r0 /* save addr_sp */
177 mov r5, r1 /* save addr of gd */
178 mov r6, r2 /* save addr of destination */
180 /* Set up the stack */
186 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
187 beq clear_bss /* skip relocation */
188 mov r1, r6 /* r1 <- scratch for copy_loop */
189 ldr r3, _bss_start_ofs
190 add r2, r0, r3 /* r2 <- source end address */
193 ldmia r0!, {r9-r10} /* copy from source address [r0] */
194 stmia r1!, {r9-r10} /* copy to target address [r1] */
195 cmp r0, r2 /* until source end address [r2] */
198 #ifndef CONFIG_SPL_BUILD
200 * fix .rel.dyn relocations
202 ldr r0, _TEXT_BASE /* r0 <- Text base */
203 sub r9, r6, r0 /* r9 <- relocation offset */
204 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
205 add r10, r10, r0 /* r10 <- sym table in FLASH */
206 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
207 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
208 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
209 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
211 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
212 add r0, r0, r9 /* r0 <- location to fix up in RAM */
215 cmp r7, #23 /* relative fixup? */
217 cmp r7, #2 /* absolute fixup? */
219 /* ignore unknown type of fixup */
222 /* absolute fix: set location to (offset) symbol value */
223 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
224 add r1, r10, r1 /* r1 <- address of symbol in table */
225 ldr r1, [r1, #4] /* r1 <- symbol value */
226 add r1, r1, r9 /* r1 <- relocated sym addr */
229 /* relative fix: increase location by offset */
234 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
240 #ifndef CONFIG_SPL_BUILD
241 ldr r0, _bss_start_ofs
243 mov r4, r6 /* reloc addr */
246 mov r2, #0x00000000 /* clear */
248 clbss_l:cmp r0, r1 /* clear loop... */
249 bhs clbss_e /* if reached end of bss, exit */
260 * We are done. Do not return, instead branch to second part of board
261 * initialization, now running from RAM.
263 ldr r0, _board_init_r_ofs
267 /* setup parameters for board_init_r */
268 mov r0, r5 /* gd_t */
269 mov r1, r6 /* dest_addr */
274 .word board_init_r - _start
277 .word __rel_dyn_start - _start
279 .word __rel_dyn_end - _start
281 .word __dynsym_start - _start
284 *************************************************************************
286 * CPU_init_critical registers
288 * setup important registers
289 * setup memory timing
291 *************************************************************************
294 #if defined(CONFIG_LPC2292)
295 PLLCFG_ADR: .word PLLCFG
296 PLLFEED_ADR: .word PLLFEED
297 PLLCON_ADR: .word PLLCON
298 PLLSTAT_ADR: .word PLLSTAT
299 VPBDIV_ADR: .word VPBDIV
300 MEMMAP_ADR: .word MEMMAP
305 #if defined(CONFIG_NETARM)
307 * prior to software reset : need to set pin PORTC4 to be *HRESET
309 ldr r0, =NETARM_GEN_MODULE_BASE
310 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
311 NETARM_GEN_PORT_DIR(0x10))
312 str r1, [r0, #+NETARM_GEN_PORTC]
314 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
315 * for an explanation of this process
317 ldr r0, =NETARM_GEN_MODULE_BASE
318 ldr r1, =NETARM_GEN_SW_SVC_RESETA
319 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
320 ldr r1, =NETARM_GEN_SW_SVC_RESETB
321 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
322 ldr r1, =NETARM_GEN_SW_SVC_RESETA
323 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
324 ldr r1, =NETARM_GEN_SW_SVC_RESETB
325 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
327 * setup PLL and System Config
329 ldr r0, =NETARM_GEN_MODULE_BASE
331 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
332 NETARM_GEN_SYS_CFG_BUSFULL | \
333 NETARM_GEN_SYS_CFG_USER_EN | \
334 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
335 NETARM_GEN_SYS_CFG_BUSARB_INT | \
336 NETARM_GEN_SYS_CFG_BUSMON_EN )
338 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
340 #ifndef CONFIG_NETARM_PLL_BYPASS
341 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
342 NETARM_GEN_PLL_CTL_POLTST_DEF | \
343 NETARM_GEN_PLL_CTL_INDIV(1) | \
344 NETARM_GEN_PLL_CTL_ICP_DEF | \
345 NETARM_GEN_PLL_CTL_OUTDIV(2) )
346 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
350 * mask all IRQs by clearing all bits in the INTMRs
353 ldr r0, =NETARM_GEN_MODULE_BASE
354 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
356 #elif defined(CONFIG_S3C4510B)
359 * Mask off all IRQ sources
369 ldr r1, =0x83ffffa0 /* cache-disabled */
372 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
373 /* No specific initialisation for IntegratorAP/CM720T as yet */
374 #elif defined(CONFIG_LPC2292)
378 /* First disconnect and disable the PLL */
382 ldr r0, PLLFEED_ADR /* start feed sequence */
384 str r4, [r0] /* feed sequence done */
385 /* Set new M and P values */
387 mov r1, #0x23 /* M=4 and P=2 */
389 ldr r0, PLLFEED_ADR /* start feed sequence */
391 str r4, [r0] /* feed sequence done */
392 /* Then enable the PLL */
394 mov r1, #0x01 /* PLL enable bit */
396 ldr r0, PLLFEED_ADR /* start feed sequence */
398 str r4, [r0] /* feed sequence done */
399 /* Wait for the lock */
401 mov r1, #0x400 /* lock bit */
407 /* And finally connect the PLL */
409 mov r1, #0x03 /* PLL enable bit and connect bit */
411 ldr r0, PLLFEED_ADR /* start feed sequence */
413 str r4, [r0] /* feed sequence done */
414 /* Set-up VPBDIV register */
416 mov r1, #0x01 /* VPB clock is same as process clock */
418 #elif defined(CONFIG_TEGRA)
419 /* No cpu_init_crit for tegra as yet */
421 #error No cpu_init_crit() defined for current CPU type
424 #ifdef CONFIG_ARM7_REVD
425 /* set clock speed */
426 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
427 /* !!! not doing DRAM refresh properly! */
431 orr r1, r1, #CLKCTL_36
435 #if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
438 * before relocating, we have to setup RAM timing
439 * because memory timing is board-dependent, you will
440 * find a lowlevel_init.S in your board directory.
449 #ifndef CONFIG_SPL_BUILD
451 *************************************************************************
455 *************************************************************************
461 #define S_FRAME_SIZE 72
483 #define MODE_SVC 0x13
487 * use bad_save_user_regs for abort/prefetch/undef/swi ...
488 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
491 .macro bad_save_user_regs
492 sub sp, sp, #S_FRAME_SIZE
493 stmia sp, {r0 - r12} @ Calling r0-r12
496 ldr r2, IRQ_STACK_START_IN
497 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
498 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
502 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
506 .macro irq_save_user_regs
507 sub sp, sp, #S_FRAME_SIZE
508 stmia sp, {r0 - r12} @ Calling r0-r12
510 stmdb r8, {sp, lr}^ @ Calling SP, LR
511 str lr, [r8, #0] @ Save calling PC
513 str r6, [r8, #4] @ Save CPSR
514 str r0, [r8, #8] @ Save OLD_R0
518 .macro irq_restore_user_regs
519 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
521 ldr lr, [sp, #S_PC] @ Get PC
522 add sp, sp, #S_FRAME_SIZE
523 subs pc, lr, #4 @ return & move spsr_svc into cpsr
527 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
529 str lr, [r13] @ save caller lr / spsr
533 mov r13, #MODE_SVC @ prepare SVC-Mode
539 .macro get_irq_stack @ setup IRQ stack
540 ldr sp, IRQ_STACK_START
543 .macro get_fiq_stack @ setup FIQ stack
544 ldr sp, FIQ_STACK_START
551 undefined_instruction:
554 bl do_undefined_instruction
560 bl do_software_interrupt
580 #ifdef CONFIG_USE_IRQ
587 irq_restore_user_regs
592 /* someone ought to write a more effiction fiq_save_user_regs */
595 irq_restore_user_regs
612 #endif /* CONFIG_SPL_BUILD */
614 #if defined(CONFIG_NETARM)
618 ldr r1, =NETARM_MEM_MODULE_BASE
619 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
622 ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
624 ldr r4, =NETARM_GEN_MODULE_BASE
625 ldr r1, =NETARM_GEN_SW_SVC_RESETA
626 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
627 ldr r1, =NETARM_GEN_SW_SVC_RESETB
628 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
629 ldr r1, =NETARM_GEN_SW_SVC_RESETA
630 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
631 ldr r1, =NETARM_GEN_SW_SVC_RESETB
632 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
634 #elif defined(CONFIG_S3C4510B)
635 /* Nothing done here as reseting the CPU is board specific, depending
636 * on external peripherals such as watchdog timers, etc. */
637 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
638 /* No specific reset actions for IntegratorAP/CM720T as yet */
639 #elif defined(CONFIG_LPC2292)
644 #elif defined(CONFIG_TEGRA)
645 /* No specific reset actions for tegra as yet */
647 #error No reset_cpu() defined for current CPU type