2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm-offsets.h>
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */
54 _undefined_instruction: .word undefined_instruction
55 _software_interrupt: .word software_interrupt
56 _prefetch_abort: .word prefetch_abort
57 _data_abort: .word data_abort
58 _not_used: .word not_used
62 .balignl 16,0xdeadbeef
66 *************************************************************************
68 * Startup Code (reset vector)
70 * do important init only if we don't start from RAM!
71 * relocate armboot to ram
73 * jump to second stage
75 *************************************************************************
80 .word CONFIG_SYS_TEXT_BASE
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
90 .word __bss_start - _start
94 .word __bss_end__ - _start
100 #ifdef CONFIG_USE_IRQ
101 /* IRQ stack memory (calculated at run-time) */
102 .globl IRQ_STACK_START
106 /* IRQ stack memory (calculated at run-time) */
107 .globl FIQ_STACK_START
112 /* IRQ stack memory (calculated at run-time) + 8 bytes */
113 .globl IRQ_STACK_START_IN
118 * the actual reset code
123 * set the cpu to SVC32 mode
131 * we do sys-critical inits only at reboot,
132 * not when booting from ram!
134 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
138 #ifdef CONFIG_LPC2292
142 /* Set stackpointer in internal RAM to call board_init_f */
144 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
145 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
149 /*------------------------------------------------------------------------------*/
152 * void relocate_code (addr_sp, gd, addr_moni)
154 * This "function" does not return, instead it continues in RAM
155 * after relocating the monitor code.
160 mov r4, r0 /* save addr_sp */
161 mov r5, r1 /* save addr of gd */
162 mov r6, r2 /* save addr of destination */
164 /* Set up the stack */
170 beq clear_bss /* skip relocation */
171 mov r1, r6 /* r1 <- scratch for copy_loop */
172 ldr r3, _bss_start_ofs
173 add r2, r0, r3 /* r2 <- source end address */
176 ldmia r0!, {r9-r10} /* copy from source address [r0] */
177 stmia r1!, {r9-r10} /* copy to target address [r1] */
178 cmp r0, r2 /* until source end address [r2] */
181 #ifndef CONFIG_SPL_BUILD
183 * fix .rel.dyn relocations
185 ldr r0, _TEXT_BASE /* r0 <- Text base */
186 sub r9, r6, r0 /* r9 <- relocation offset */
187 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
188 add r10, r10, r0 /* r10 <- sym table in FLASH */
189 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
190 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
191 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
192 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
194 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
195 add r0, r0, r9 /* r0 <- location to fix up in RAM */
198 cmp r7, #23 /* relative fixup? */
200 cmp r7, #2 /* absolute fixup? */
202 /* ignore unknown type of fixup */
205 /* absolute fix: set location to (offset) symbol value */
206 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
207 add r1, r10, r1 /* r1 <- address of symbol in table */
208 ldr r1, [r1, #4] /* r1 <- symbol value */
209 add r1, r1, r9 /* r1 <- relocated sym addr */
212 /* relative fix: increase location by offset */
217 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
223 #ifndef CONFIG_SPL_BUILD
224 ldr r0, _bss_start_ofs
226 mov r4, r6 /* reloc addr */
229 mov r2, #0x00000000 /* clear */
231 clbss_l:cmp r0, r1 /* clear loop... */
232 bhs clbss_e /* if reached end of bss, exit */
243 * We are done. Do not return, instead branch to second part of board
244 * initialization, now running from RAM.
246 ldr r0, _board_init_r_ofs
250 /* setup parameters for board_init_r */
251 mov r0, r5 /* gd_t */
252 mov r1, r6 /* dest_addr */
257 .word board_init_r - _start
260 .word __rel_dyn_start - _start
262 .word __rel_dyn_end - _start
264 .word __dynsym_start - _start
267 *************************************************************************
269 * CPU_init_critical registers
271 * setup important registers
272 * setup memory timing
274 *************************************************************************
277 #if defined(CONFIG_LPC2292)
278 PLLCFG_ADR: .word PLLCFG
279 PLLFEED_ADR: .word PLLFEED
280 PLLCON_ADR: .word PLLCON
281 PLLSTAT_ADR: .word PLLSTAT
282 VPBDIV_ADR: .word VPBDIV
283 MEMMAP_ADR: .word MEMMAP
288 #if defined(CONFIG_NETARM)
290 * prior to software reset : need to set pin PORTC4 to be *HRESET
292 ldr r0, =NETARM_GEN_MODULE_BASE
293 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
294 NETARM_GEN_PORT_DIR(0x10))
295 str r1, [r0, #+NETARM_GEN_PORTC]
297 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
298 * for an explanation of this process
300 ldr r0, =NETARM_GEN_MODULE_BASE
301 ldr r1, =NETARM_GEN_SW_SVC_RESETA
302 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
303 ldr r1, =NETARM_GEN_SW_SVC_RESETB
304 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
305 ldr r1, =NETARM_GEN_SW_SVC_RESETA
306 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
307 ldr r1, =NETARM_GEN_SW_SVC_RESETB
308 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
310 * setup PLL and System Config
312 ldr r0, =NETARM_GEN_MODULE_BASE
314 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
315 NETARM_GEN_SYS_CFG_BUSFULL | \
316 NETARM_GEN_SYS_CFG_USER_EN | \
317 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
318 NETARM_GEN_SYS_CFG_BUSARB_INT | \
319 NETARM_GEN_SYS_CFG_BUSMON_EN )
321 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
323 #ifndef CONFIG_NETARM_PLL_BYPASS
324 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
325 NETARM_GEN_PLL_CTL_POLTST_DEF | \
326 NETARM_GEN_PLL_CTL_INDIV(1) | \
327 NETARM_GEN_PLL_CTL_ICP_DEF | \
328 NETARM_GEN_PLL_CTL_OUTDIV(2) )
329 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
333 * mask all IRQs by clearing all bits in the INTMRs
336 ldr r0, =NETARM_GEN_MODULE_BASE
337 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
339 #elif defined(CONFIG_S3C4510B)
342 * Mask off all IRQ sources
352 ldr r1, =0x83ffffa0 /* cache-disabled */
355 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
356 /* No specific initialisation for IntegratorAP/CM720T as yet */
357 #elif defined(CONFIG_LPC2292)
361 /* First disconnect and disable the PLL */
365 ldr r0, PLLFEED_ADR /* start feed sequence */
367 str r4, [r0] /* feed sequence done */
368 /* Set new M and P values */
370 mov r1, #0x23 /* M=4 and P=2 */
372 ldr r0, PLLFEED_ADR /* start feed sequence */
374 str r4, [r0] /* feed sequence done */
375 /* Then enable the PLL */
377 mov r1, #0x01 /* PLL enable bit */
379 ldr r0, PLLFEED_ADR /* start feed sequence */
381 str r4, [r0] /* feed sequence done */
382 /* Wait for the lock */
384 mov r1, #0x400 /* lock bit */
390 /* And finally connect the PLL */
392 mov r1, #0x03 /* PLL enable bit and connect bit */
394 ldr r0, PLLFEED_ADR /* start feed sequence */
396 str r4, [r0] /* feed sequence done */
397 /* Set-up VPBDIV register */
399 mov r1, #0x01 /* VPB clock is same as process clock */
402 #error No cpu_init_crit() defined for current CPU type
405 #ifdef CONFIG_ARM7_REVD
406 /* set clock speed */
407 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
408 /* !!! not doing DRAM refresh properly! */
412 orr r1, r1, #CLKCTL_36
416 #ifndef CONFIG_LPC2292
419 * before relocating, we have to setup RAM timing
420 * because memory timing is board-dependent, you will
421 * find a lowlevel_init.S in your board directory.
431 *************************************************************************
435 *************************************************************************
441 #define S_FRAME_SIZE 72
463 #define MODE_SVC 0x13
467 * use bad_save_user_regs for abort/prefetch/undef/swi ...
468 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
471 .macro bad_save_user_regs
472 sub sp, sp, #S_FRAME_SIZE
473 stmia sp, {r0 - r12} @ Calling r0-r12
476 ldr r2, IRQ_STACK_START_IN
477 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
478 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
482 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
486 .macro irq_save_user_regs
487 sub sp, sp, #S_FRAME_SIZE
488 stmia sp, {r0 - r12} @ Calling r0-r12
490 stmdb r8, {sp, lr}^ @ Calling SP, LR
491 str lr, [r8, #0] @ Save calling PC
493 str r6, [r8, #4] @ Save CPSR
494 str r0, [r8, #8] @ Save OLD_R0
498 .macro irq_restore_user_regs
499 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
501 ldr lr, [sp, #S_PC] @ Get PC
502 add sp, sp, #S_FRAME_SIZE
503 subs pc, lr, #4 @ return & move spsr_svc into cpsr
507 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
509 str lr, [r13] @ save caller lr / spsr
513 mov r13, #MODE_SVC @ prepare SVC-Mode
519 .macro get_irq_stack @ setup IRQ stack
520 ldr sp, IRQ_STACK_START
523 .macro get_fiq_stack @ setup FIQ stack
524 ldr sp, FIQ_STACK_START
531 undefined_instruction:
534 bl do_undefined_instruction
540 bl do_software_interrupt
560 #ifdef CONFIG_USE_IRQ
567 irq_restore_user_regs
572 /* someone ought to write a more effiction fiq_save_user_regs */
575 irq_restore_user_regs
593 #if defined(CONFIG_NETARM)
597 ldr r1, =NETARM_MEM_MODULE_BASE
598 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
601 ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
603 ldr r4, =NETARM_GEN_MODULE_BASE
604 ldr r1, =NETARM_GEN_SW_SVC_RESETA
605 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
606 ldr r1, =NETARM_GEN_SW_SVC_RESETB
607 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
608 ldr r1, =NETARM_GEN_SW_SVC_RESETA
609 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
610 ldr r1, =NETARM_GEN_SW_SVC_RESETB
611 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
613 #elif defined(CONFIG_S3C4510B)
614 /* Nothing done here as reseting the CPU is board specific, depending
615 * on external peripherals such as watchdog timers, etc. */
616 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
617 /* No specific reset actions for IntegratorAP/CM720T as yet */
618 #elif defined(CONFIG_LPC2292)
624 #error No reset_cpu() defined for current CPU type