2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm-offsets.h>
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */
54 _undefined_instruction: .word undefined_instruction
55 _software_interrupt: .word software_interrupt
56 _prefetch_abort: .word prefetch_abort
57 _data_abort: .word data_abort
58 _not_used: .word not_used
62 .balignl 16,0xdeadbeef
66 *************************************************************************
68 * Startup Code (reset vector)
70 * do important init only if we don't start from RAM!
71 * relocate armboot to ram
73 * jump to second stage
75 *************************************************************************
80 .word CONFIG_SYS_TEXT_BASE
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
90 .word __bss_start - _start
97 /* IRQ stack memory (calculated at run-time) */
98 .globl IRQ_STACK_START
102 /* IRQ stack memory (calculated at run-time) */
103 .globl FIQ_STACK_START
108 /* IRQ stack memory (calculated at run-time) + 8 bytes */
109 .globl IRQ_STACK_START_IN
114 * the actual reset code
119 * set the cpu to SVC32 mode
127 * we do sys-critical inits only at reboot,
128 * not when booting from ram!
130 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
134 #ifdef CONFIG_LPC2292
138 /* Set stackpointer in internal RAM to call board_init_f */
140 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
144 /*------------------------------------------------------------------------------*/
147 * void relocate_code (addr_sp, gd, addr_moni)
149 * This "function" does not return, instead it continues in RAM
150 * after relocating the monitor code.
155 mov r4, r0 /* save addr_sp */
156 mov r5, r1 /* save addr of gd */
157 mov r6, r2 /* save addr of destination */
158 mov r7, r2 /* save addr of destination */
160 /* Set up the stack */
166 ldr r3, _bss_start_ofs
167 add r2, r0, r3 /* r2 <- source end address */
172 ldmia r0!, {r9-r10} /* copy from source address [r0] */
173 stmia r6!, {r9-r10} /* copy to target address [r1] */
174 cmp r0, r2 /* until source end address [r2] */
177 #ifndef CONFIG_PRELOADER
179 * fix .rel.dyn relocations
181 ldr r0, _TEXT_BASE /* r0 <- Text base */
182 sub r9, r7, r0 /* r9 <- relocation offset */
183 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
184 add r10, r10, r0 /* r10 <- sym table in FLASH */
185 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
186 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
187 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
188 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
190 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
191 add r0, r0, r9 /* r0 <- location to fix up in RAM */
194 cmp r8, #23 /* relative fixup? */
196 cmp r8, #2 /* absolute fixup? */
198 /* ignore unknown type of fixup */
201 /* absolute fix: set location to (offset) symbol value */
202 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
203 add r1, r10, r1 /* r1 <- address of symbol in table */
204 ldr r1, [r1, #4] /* r1 <- symbol value */
205 add r1, r9 /* r1 <- relocated sym addr */
208 /* relative fix: increase location by offset */
213 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
219 #ifndef CONFIG_PRELOADER
220 ldr r0, _bss_start_ofs
222 ldr r3, _TEXT_BASE /* Text base */
223 mov r4, r7 /* reloc addr */
226 mov r2, #0x00000000 /* clear */
228 clbss_l:str r2, [r0] /* clear loop... */
238 * We are done. Do not return, instead branch to second part of board
239 * initialization, now running from RAM.
241 ldr r0, _board_init_r_ofs
245 /* setup parameters for board_init_r */
246 mov r0, r5 /* gd_t */
247 mov r1, r7 /* dest_addr */
252 .word board_init_r - _start
255 .word __rel_dyn_start - _start
257 .word __rel_dyn_end - _start
259 .word __dynsym_start - _start
262 *************************************************************************
264 * CPU_init_critical registers
266 * setup important registers
267 * setup memory timing
269 *************************************************************************
272 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
274 /* Interupt-Controller base addresses */
275 INTMR1: .word 0x80000280 @ 32 bit size
276 INTMR2: .word 0x80001280 @ 16 bit size
277 INTMR3: .word 0x80002280 @ 8 bit size
280 SYSCON1: .word 0x80000100
281 SYSCON2: .word 0x80001100
282 SYSCON3: .word 0x80002200
284 #define CLKCTL 0x6 /* mask */
285 #define CLKCTL_18 0x0 /* 18.432 MHz */
286 #define CLKCTL_36 0x2 /* 36.864 MHz */
287 #define CLKCTL_49 0x4 /* 49.152 MHz */
288 #define CLKCTL_73 0x6 /* 73.728 MHz */
290 #elif defined(CONFIG_LPC2292)
291 PLLCFG_ADR: .word PLLCFG
292 PLLFEED_ADR: .word PLLFEED
293 PLLCON_ADR: .word PLLCON
294 PLLSTAT_ADR: .word PLLSTAT
295 VPBDIV_ADR: .word VPBDIV
296 MEMMAP_ADR: .word MEMMAP
301 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
304 * mask all IRQs by clearing all bits in the INTMRs
315 * flush v4 I/D caches
318 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
319 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
322 * disable MMU stuff and caches
325 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
326 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
327 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
329 #elif defined(CONFIG_NETARM)
331 * prior to software reset : need to set pin PORTC4 to be *HRESET
333 ldr r0, =NETARM_GEN_MODULE_BASE
334 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
335 NETARM_GEN_PORT_DIR(0x10))
336 str r1, [r0, #+NETARM_GEN_PORTC]
338 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
339 * for an explanation of this process
341 ldr r0, =NETARM_GEN_MODULE_BASE
342 ldr r1, =NETARM_GEN_SW_SVC_RESETA
343 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
344 ldr r1, =NETARM_GEN_SW_SVC_RESETB
345 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
346 ldr r1, =NETARM_GEN_SW_SVC_RESETA
347 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
348 ldr r1, =NETARM_GEN_SW_SVC_RESETB
349 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
351 * setup PLL and System Config
353 ldr r0, =NETARM_GEN_MODULE_BASE
355 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
356 NETARM_GEN_SYS_CFG_BUSFULL | \
357 NETARM_GEN_SYS_CFG_USER_EN | \
358 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
359 NETARM_GEN_SYS_CFG_BUSARB_INT | \
360 NETARM_GEN_SYS_CFG_BUSMON_EN )
362 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
364 #ifndef CONFIG_NETARM_PLL_BYPASS
365 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
366 NETARM_GEN_PLL_CTL_POLTST_DEF | \
367 NETARM_GEN_PLL_CTL_INDIV(1) | \
368 NETARM_GEN_PLL_CTL_ICP_DEF | \
369 NETARM_GEN_PLL_CTL_OUTDIV(2) )
370 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
374 * mask all IRQs by clearing all bits in the INTMRs
377 ldr r0, =NETARM_GEN_MODULE_BASE
378 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
380 #elif defined(CONFIG_S3C4510B)
383 * Mask off all IRQ sources
393 ldr r1, =0x83ffffa0 /* cache-disabled */
396 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
397 /* No specific initialisation for IntegratorAP/CM720T as yet */
398 #elif defined(CONFIG_LPC2292)
402 /* First disconnect and disable the PLL */
406 ldr r0, PLLFEED_ADR /* start feed sequence */
408 str r4, [r0] /* feed sequence done */
409 /* Set new M and P values */
411 mov r1, #0x23 /* M=4 and P=2 */
413 ldr r0, PLLFEED_ADR /* start feed sequence */
415 str r4, [r0] /* feed sequence done */
416 /* Then enable the PLL */
418 mov r1, #0x01 /* PLL enable bit */
420 ldr r0, PLLFEED_ADR /* start feed sequence */
422 str r4, [r0] /* feed sequence done */
423 /* Wait for the lock */
425 mov r1, #0x400 /* lock bit */
431 /* And finally connect the PLL */
433 mov r1, #0x03 /* PLL enable bit and connect bit */
435 ldr r0, PLLFEED_ADR /* start feed sequence */
437 str r4, [r0] /* feed sequence done */
438 /* Set-up VPBDIV register */
440 mov r1, #0x01 /* VPB clock is same as process clock */
443 #error No cpu_init_crit() defined for current CPU type
446 #ifdef CONFIG_ARM7_REVD
447 /* set clock speed */
448 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
449 /* !!! not doing DRAM refresh properly! */
453 orr r1, r1, #CLKCTL_36
457 #ifndef CONFIG_LPC2292
460 * before relocating, we have to setup RAM timing
461 * because memory timing is board-dependent, you will
462 * find a lowlevel_init.S in your board directory.
472 *************************************************************************
476 *************************************************************************
482 #define S_FRAME_SIZE 72
504 #define MODE_SVC 0x13
508 * use bad_save_user_regs for abort/prefetch/undef/swi ...
509 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
512 .macro bad_save_user_regs
513 sub sp, sp, #S_FRAME_SIZE
514 stmia sp, {r0 - r12} @ Calling r0-r12
517 ldr r2, IRQ_STACK_START_IN
518 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
519 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
523 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
527 .macro irq_save_user_regs
528 sub sp, sp, #S_FRAME_SIZE
529 stmia sp, {r0 - r12} @ Calling r0-r12
531 stmdb r8, {sp, lr}^ @ Calling SP, LR
532 str lr, [r8, #0] @ Save calling PC
534 str r6, [r8, #4] @ Save CPSR
535 str r0, [r8, #8] @ Save OLD_R0
539 .macro irq_restore_user_regs
540 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
542 ldr lr, [sp, #S_PC] @ Get PC
543 add sp, sp, #S_FRAME_SIZE
544 subs pc, lr, #4 @ return & move spsr_svc into cpsr
548 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
550 str lr, [r13] @ save caller lr / spsr
554 mov r13, #MODE_SVC @ prepare SVC-Mode
560 .macro get_irq_stack @ setup IRQ stack
561 ldr sp, IRQ_STACK_START
564 .macro get_fiq_stack @ setup FIQ stack
565 ldr sp, FIQ_STACK_START
572 undefined_instruction:
575 bl do_undefined_instruction
581 bl do_software_interrupt
601 #ifdef CONFIG_USE_IRQ
608 irq_restore_user_regs
613 /* someone ought to write a more effiction fiq_save_user_regs */
616 irq_restore_user_regs
634 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
639 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
640 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
641 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
642 bic ip, ip, #0x000f @ ............wcam
643 bic ip, ip, #0x2100 @ ..v....s........
644 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
646 #elif defined(CONFIG_NETARM)
650 ldr r1, =NETARM_MEM_MODULE_BASE
651 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
654 ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
656 ldr r4, =NETARM_GEN_MODULE_BASE
657 ldr r1, =NETARM_GEN_SW_SVC_RESETA
658 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
659 ldr r1, =NETARM_GEN_SW_SVC_RESETB
660 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
661 ldr r1, =NETARM_GEN_SW_SVC_RESETA
662 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
663 ldr r1, =NETARM_GEN_SW_SVC_RESETB
664 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
666 #elif defined(CONFIG_S3C4510B)
667 /* Nothing done here as reseting the CPU is board specific, depending
668 * on external peripherals such as watchdog timers, etc. */
669 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
670 /* No specific reset actions for IntegratorAP/CM720T as yet */
671 #elif defined(CONFIG_LPC2292)
677 #error No reset_cpu() defined for current CPU type