2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gp_padctrl.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/pmc.h>
25 #include <asm/arch-tegra/scu.h>
28 int get_num_cpus(void)
30 struct apb_misc_gp_ctlr *gp;
33 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
34 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
49 * Timing tables for each SOC for all four oscillator options.
51 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
54 {{ 1000, 13, 0, 12}, /* OSC 13M */
55 { 625, 12, 0, 8}, /* OSC 19.2M */
56 { 1000, 12, 0, 12}, /* OSC 12M */
57 { 1000, 26, 0, 12}, /* OSC 26M */
82 void adjust_pllp_out_freqs(void)
84 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
85 struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
88 /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
89 reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
90 reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
91 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
92 writel(reg, &pll->pll_out[0]);
94 reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
95 reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
96 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
97 writel(reg, &pll->pll_out[1]);
100 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
105 /* If PLLX is already enabled, just return */
106 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
107 debug("pllx_set_rate: PLLX already enabled, returning\n");
111 debug(" pllx_set_rate entry\n");
113 /* Set BYPASS, m, n and p to PLLX_BASE */
114 reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
115 reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
116 writel(reg, &pll->pll_base);
118 /* Set cpcon to PLLX_MISC */
119 reg = (cpcon << PLL_CPCON_SHIFT);
121 /* Set dccon to PLLX_MISC if freq > 600MHz */
123 reg |= (1 << PLL_DCCON_SHIFT);
124 writel(reg, &pll->pll_misc);
127 reg = readl(&pll->pll_base);
128 reg |= PLL_ENABLE_MASK;
131 reg &= ~PLL_BYPASS_MASK;
132 writel(reg, &pll->pll_base);
134 /* Set lock_enable to PLLX_MISC */
135 reg = readl(&pll->pll_misc);
136 reg |= PLL_LOCK_ENABLE_MASK;
137 writel(reg, &pll->pll_misc);
144 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
145 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
146 int soc_type, sku_info, chip_sku;
147 enum clock_osc_freq osc;
148 struct clk_pll_table *sel;
150 debug("init_pllx entry\n");
152 /* get SOC (chip) type */
153 soc_type = tegra_get_chip();
154 debug(" init_pllx: SoC = 0x%02X\n", soc_type);
157 sku_info = tegra_get_sku_info();
158 debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
160 /* get chip SKU, combo of the above info */
161 chip_sku = tegra_get_chip_sku();
162 debug(" init_pllx: Chip SKU = %d\n", chip_sku);
165 osc = clock_get_osc_freq();
166 debug(" init_pllx: osc = %d\n", osc);
169 sel = &tegra_pll_x_table[chip_sku][osc];
170 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
172 /* adjust PLLP_out1-4 on T3x/T114 */
173 if (soc_type >= CHIPID_TEGRA30) {
174 debug(" init_pllx: adjusting PLLP out freqs\n");
175 adjust_pllp_out_freqs();
179 void enable_cpu_clock(int enable)
181 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
186 * Regardless of whether the request is to enable or disable the CPU
187 * clock, every processor in the CPU complex except the master (CPU 0)
188 * will have it's clock stopped because the AVP only talks to the
193 /* Initialize PLLX */
196 /* Wait until all clocks are stable */
197 udelay(PLL_STABILIZATION_DELAY);
199 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
200 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
204 * Read the register containing the individual CPU clock enables and
205 * always stop the clocks to CPUs > 0.
207 clk = readl(&clkrst->crc_clk_cpu_cmplx);
208 clk |= 1 << CPU1_CLK_STP_SHIFT;
209 if (get_num_cpus() == 4)
210 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
212 /* Stop/Unstop the CPU clock */
213 clk &= ~CPU0_CLK_STP_MASK;
214 clk |= !enable << CPU0_CLK_STP_SHIFT;
215 writel(clk, &clkrst->crc_clk_cpu_cmplx);
217 clock_enable(PERIPH_ID_CPU);
220 static int is_cpu_powered(void)
222 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
224 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
227 static void remove_cpu_io_clamps(void)
229 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
232 /* Remove the clamps on the CPU I/O signals */
233 reg = readl(&pmc->pmc_remove_clamping);
235 writel(reg, &pmc->pmc_remove_clamping);
237 /* Give I/O signals time to stabilize */
238 udelay(IO_STABILIZATION_DELAY);
241 void powerup_cpu(void)
243 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
245 int timeout = IO_STABILIZATION_DELAY;
247 if (!is_cpu_powered()) {
248 /* Toggle the CPU power state (OFF -> ON) */
249 reg = readl(&pmc->pmc_pwrgate_toggle);
252 writel(reg, &pmc->pmc_pwrgate_toggle);
254 /* Wait for the power to come up */
255 while (!is_cpu_powered()) {
257 printf("CPU failed to power up!\n");
263 * Remove the I/O clamps from CPU power partition.
264 * Recommended only on a Warm boot, if the CPU partition gets
265 * power gated. Shouldn't cause any harm when called after a
266 * cold boot according to HW, probably just redundant.
268 remove_cpu_io_clamps();
272 void reset_A9_cpu(int reset)
275 * NOTE: Regardless of whether the request is to hold the CPU in reset
276 * or take it out of reset, every processor in the CPU complex
277 * except the master (CPU 0) will be held in reset because the
278 * AVP only talks to the master. The AVP does not know that there
279 * are multiple processors in the CPU complex.
281 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
282 int num_cpus = get_num_cpus();
285 debug("reset_a9_cpu entry\n");
286 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
287 for (cpu = 1; cpu < num_cpus; cpu++)
288 reset_cmplx_set_enable(cpu, mask, 1);
289 reset_cmplx_set_enable(0, mask, reset);
291 /* Enable/Disable master CPU reset */
292 reset_set_enable(PERIPH_ID_CPU, reset);
295 void clock_enable_coresight(int enable)
300 debug("clock_enable_coresight entry\n");
301 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
302 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
306 * Put CoreSight on PLLP_OUT0 and divide it down as per
307 * PLLP base frequency based on SoC type (T20/T30/T114).
308 * Clock divider request would setup CSITE clock as 144MHz
309 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
312 soc_type = tegra_get_chip();
313 if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
314 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
315 else if (soc_type == CHIPID_TEGRA20)
316 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
318 printf("%s: Unknown SoC type %X!\n",
321 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
323 /* Unlock the CPU CoreSight interfaces */
324 rst = CORESIGHT_UNLOCK;
325 writel(rst, CSITE_CPU_DBG0_LAR);
326 writel(rst, CSITE_CPU_DBG1_LAR);
327 if (get_num_cpus() == 4) {
328 writel(rst, CSITE_CPU_DBG2_LAR);
329 writel(rst, CSITE_CPU_DBG3_LAR);
337 writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
338 | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
339 FLOW_CTLR_HALT_COP_EVENTS);