2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gp_padctrl.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/pmc.h>
25 #include <asm/arch-tegra/scu.h>
28 int get_num_cpus(void)
30 struct apb_misc_gp_ctlr *gp;
33 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
34 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
49 * Timing tables for each SOC for all four oscillator options.
51 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
55 * Register Field Bits Width
56 * ------------------------------
58 * PLLX_BASE n 17: 8 10
60 * PLLX_MISC cpcon 11: 8 4
63 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
64 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
65 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
66 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
71 * Register Field Bits Width
72 * ------------------------------
74 * PLLX_BASE n 17: 8 10
76 * PLLX_MISC cpcon 11: 8 4
79 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
80 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
81 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
82 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
87 * Register Field Bits Width
88 * ------------------------------
90 * PLLX_BASE n 17: 8 10
92 * PLLX_MISC cpcon 11: 8 4
95 { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
96 { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
97 { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
98 { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
103 * Register Field Bits Width
104 * ------------------------------
105 * PLLX_BASE p 23:20 4
106 * PLLX_BASE n 15: 8 8
110 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
111 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
112 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
113 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
117 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
120 int chip = tegra_get_chip();
123 /* If PLLX is already enabled, just return */
124 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
125 debug("pllx_set_rate: PLLX already enabled, returning\n");
129 debug(" pllx_set_rate entry\n");
131 /* Set BYPASS, m, n and p to PLLX_BASE */
132 reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
133 reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
134 writel(reg, &pll->pll_base);
136 /* Set cpcon to PLLX_MISC */
137 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
138 reg = (cpcon << PLL_CPCON_SHIFT);
142 /* Set dccon to PLLX_MISC if freq > 600MHz */
144 reg |= (1 << PLL_DCCON_SHIFT);
145 writel(reg, &pll->pll_misc);
148 reg = readl(&pll->pll_base);
149 reg &= ~PLL_BYPASS_MASK;
150 writel(reg, &pll->pll_base);
151 debug("pllx_set_rate: base = 0x%08X\n", reg);
153 /* Set lock_enable to PLLX_MISC */
154 reg = readl(&pll->pll_misc);
155 reg |= PLL_LOCK_ENABLE_MASK;
156 writel(reg, &pll->pll_misc);
157 debug("pllx_set_rate: misc = 0x%08X\n", reg);
159 /* Enable PLLX last, once it's all configured */
160 reg = readl(&pll->pll_base);
161 reg |= PLL_ENABLE_MASK;
162 writel(reg, &pll->pll_base);
163 debug("pllx_set_rate: base final = 0x%08X\n", reg);
170 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
171 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
172 int soc_type, sku_info, chip_sku;
173 enum clock_osc_freq osc;
174 struct clk_pll_table *sel;
176 debug("init_pllx entry\n");
178 /* get SOC (chip) type */
179 soc_type = tegra_get_chip();
180 debug(" init_pllx: SoC = 0x%02X\n", soc_type);
183 sku_info = tegra_get_sku_info();
184 debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
186 /* get chip SKU, combo of the above info */
187 chip_sku = tegra_get_chip_sku();
188 debug(" init_pllx: Chip SKU = %d\n", chip_sku);
191 osc = clock_get_osc_freq();
192 debug(" init_pllx: osc = %d\n", osc);
195 sel = &tegra_pll_x_table[chip_sku][osc];
196 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
199 void enable_cpu_clock(int enable)
201 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
206 * Regardless of whether the request is to enable or disable the CPU
207 * clock, every processor in the CPU complex except the master (CPU 0)
208 * will have it's clock stopped because the AVP only talks to the
213 /* Initialize PLLX */
216 /* Wait until all clocks are stable */
217 udelay(PLL_STABILIZATION_DELAY);
219 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
220 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
224 * Read the register containing the individual CPU clock enables and
225 * always stop the clocks to CPUs > 0.
227 clk = readl(&clkrst->crc_clk_cpu_cmplx);
228 clk |= 1 << CPU1_CLK_STP_SHIFT;
229 if (get_num_cpus() == 4)
230 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
232 /* Stop/Unstop the CPU clock */
233 clk &= ~CPU0_CLK_STP_MASK;
234 clk |= !enable << CPU0_CLK_STP_SHIFT;
235 writel(clk, &clkrst->crc_clk_cpu_cmplx);
237 clock_enable(PERIPH_ID_CPU);
240 static int is_cpu_powered(void)
242 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
244 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
247 static void remove_cpu_io_clamps(void)
249 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
252 /* Remove the clamps on the CPU I/O signals */
253 reg = readl(&pmc->pmc_remove_clamping);
255 writel(reg, &pmc->pmc_remove_clamping);
257 /* Give I/O signals time to stabilize */
258 udelay(IO_STABILIZATION_DELAY);
261 void powerup_cpu(void)
263 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
265 int timeout = IO_STABILIZATION_DELAY;
267 if (!is_cpu_powered()) {
268 /* Toggle the CPU power state (OFF -> ON) */
269 reg = readl(&pmc->pmc_pwrgate_toggle);
272 writel(reg, &pmc->pmc_pwrgate_toggle);
274 /* Wait for the power to come up */
275 while (!is_cpu_powered()) {
277 printf("CPU failed to power up!\n");
283 * Remove the I/O clamps from CPU power partition.
284 * Recommended only on a Warm boot, if the CPU partition gets
285 * power gated. Shouldn't cause any harm when called after a
286 * cold boot according to HW, probably just redundant.
288 remove_cpu_io_clamps();
292 void reset_A9_cpu(int reset)
295 * NOTE: Regardless of whether the request is to hold the CPU in reset
296 * or take it out of reset, every processor in the CPU complex
297 * except the master (CPU 0) will be held in reset because the
298 * AVP only talks to the master. The AVP does not know that there
299 * are multiple processors in the CPU complex.
301 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
302 int num_cpus = get_num_cpus();
305 debug("reset_a9_cpu entry\n");
306 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
307 for (cpu = 1; cpu < num_cpus; cpu++)
308 reset_cmplx_set_enable(cpu, mask, 1);
309 reset_cmplx_set_enable(0, mask, reset);
311 /* Enable/Disable master CPU reset */
312 reset_set_enable(PERIPH_ID_CPU, reset);
315 void clock_enable_coresight(int enable)
319 debug("clock_enable_coresight entry\n");
320 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
321 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
325 * Put CoreSight on PLLP_OUT0 and divide it down as per
326 * PLLP base frequency based on SoC type (T20/T30/T114).
327 * Clock divider request would setup CSITE clock as 144MHz
328 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
330 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
331 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
333 /* Unlock the CPU CoreSight interfaces */
334 rst = CORESIGHT_UNLOCK;
335 writel(rst, CSITE_CPU_DBG0_LAR);
336 writel(rst, CSITE_CPU_DBG1_LAR);
337 if (get_num_cpus() == 4) {
338 writel(rst, CSITE_CPU_DBG2_LAR);
339 writel(rst, CSITE_CPU_DBG3_LAR);
347 writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
348 | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
349 FLOW_CTLR_HALT_COP_EVENTS);