2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 /* Stabilization delays, in usec */
10 #define PLL_STABILIZATION_DELAY (300)
11 #define IO_STABILIZATION_DELAY (1000)
13 #if defined(CONFIG_TEGRA20)
14 #define NVBL_PLLP_KHZ (216000)
15 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
16 #define NVBL_PLLP_KHZ (408000)
18 #error "Unknown Tegra chip!"
21 #define PLLX_ENABLED (1 << 30)
22 #define CCLK_BURST_POLICY 0x20008888
23 #define SUPER_CCLK_DIVIDER 0x80000000
25 /* Calculate clock fractional divider value from ref and target frequencies */
26 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
28 /* Calculate clock frequency value from reference and clock divider value */
29 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
32 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
33 #define PG_UP_TAG_0 0x0
35 #define CORESIGHT_UNLOCK 0xC5ACCE55;
37 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
38 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
39 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
40 #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
41 #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
43 #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
44 #define FLOW_MODE_STOP 2
45 #define HALT_COP_EVENT_JTAG (1 << 28)
46 #define HALT_COP_EVENT_IRQ_1 (1 << 11)
47 #define HALT_COP_EVENT_FIQ_1 (1 << 9)
49 #define FLOW_MODE_NONE 0
51 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
53 struct clk_pll_table {
60 void clock_enable_coresight(int enable);
61 void enable_cpu_clock(int enable);
62 void halt_avp(void) __attribute__ ((noreturn));
64 void powerup_cpu(void);
65 void reset_A9_cpu(int reset);
66 void start_cpu(u32 reset_vector);
67 int tegra_get_chip(void);
68 int tegra_get_sku_info(void);
69 int tegra_get_chip_sku(void);
70 void adjust_pllp_out_freqs(void);