2 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
4 * Copyright (C) 2011 Andreas Bießmann
5 * Copyright (C) 2005 David Brownell
6 * Copyright (C) 2005 Ivan Kokshaysky
7 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/at91_pmc.h>
18 #include <asm/arch/clk.h>
20 #if !defined(CONFIG_AT91FAMILY)
21 # error You need to define CONFIG_AT91FAMILY in your board config!
24 DECLARE_GLOBAL_DATA_PTR;
26 static unsigned long at91_css_to_rate(unsigned long css)
29 case AT91_PMC_MCKR_CSS_SLOW:
30 return CONFIG_SYS_AT91_SLOW_CLOCK;
31 case AT91_PMC_MCKR_CSS_MAIN:
32 return gd->main_clk_rate_hz;
33 case AT91_PMC_MCKR_CSS_PLLA:
34 return gd->plla_rate_hz;
35 case AT91_PMC_MCKR_CSS_PLLB:
36 return gd->pllb_rate_hz;
42 #ifdef CONFIG_USB_ATMEL
43 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
45 unsigned i, div = 0, mul = 0, diff = 1 << 30;
46 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
48 /* PLL output max 240 MHz (or 180 MHz per errata) */
49 if (out_freq > 240000000)
52 for (i = 1; i < 256; i++) {
57 * PLL input between 1MHz and 32MHz per spec, but lower
58 * frequences seem necessary in some cases so allow 100K.
59 * Warning: some newer products need 2MHz min.
61 input = main_freq / i;
67 mul1 = out_freq / input;
73 diff1 = out_freq - input * mul1;
84 if (i == 256 && diff > (out_freq >> 5))
86 return ret | ((mul - 1) << 16) | div;
92 static u32 at91_pll_rate(u32 freq, u32 reg)
97 mul = (reg >> 16) & 0x7ff;
107 int at91_clock_init(unsigned long main_clock)
110 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
111 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
114 * When the bootloader initialized the main oscillator correctly,
115 * there's no problem using the cycle counter. But if it didn't,
116 * or when using oscillator bypass mode, we must be told the speed
121 tmp = readl(&pmc->mcfr);
122 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
123 tmp &= AT91_PMC_MCFR_MAINF_MASK;
124 main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
127 gd->main_clk_rate_hz = main_clock;
129 /* report if PLLA is more than mildly overclocked */
130 gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
132 #ifdef CONFIG_USB_ATMEL
134 * USB clock init: choose 48 MHz PLLB value,
135 * disable 48MHz clock during usb peripheral suspend.
137 * REVISIT: assumes MCK doesn't derive from PLLB!
139 gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
140 AT91_PMC_PLLBR_USBDIV_2;
141 gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
145 * MCK and CPU derive from one of those primary clocks.
146 * For now, assume this parentage won't change.
148 mckr = readl(&pmc->mckr);
149 gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
150 freq = gd->mck_rate_hz;
152 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
154 gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
155 gd->cpu_clk_rate_hz = freq;