2 * Low-level initialization for EP93xx
4 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
6 * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
8 * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
9 * Copyright (C) 2006 Cirrus Logic Inc.
11 * See file CREDITS for list of people who contributed to this
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch-ep93xx/ep93xx.h>
21 /* Configure the SDRAM based on the supplied settings.
23 * Input: r0 - SDRAM DEVCFG register
24 * r2 - configuration for SDRAM chips
29 /* Program the SDRAM device configuration register. */
31 #ifdef CONFIG_EDB93XX_SDCS0
32 str r0, [r3, #SDRAM_OFF_DEVCFG0]
34 #ifdef CONFIG_EDB93XX_SDCS1
35 str r0, [r3, #SDRAM_OFF_DEVCFG1]
37 #ifdef CONFIG_EDB93XX_SDCS2
38 str r0, [r3, #SDRAM_OFF_DEVCFG2]
40 #ifdef CONFIG_EDB93XX_SDCS3
41 str r0, [r3, #SDRAM_OFF_DEVCFG3]
44 /* Set the Initialize and MRS bits (issue continuous NOP commands
47 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
48 EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
49 EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
50 str r4, [r3, #SDRAM_OFF_GLCONFIG]
52 /* Delay for 200us. */
58 /* Clear the MRS bit to issue a precharge all. */
59 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
60 EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
61 str r4, [r3, #SDRAM_OFF_GLCONFIG]
63 /* Temporarily set the refresh timer to 0x10. Make it really low so
64 * that refresh cycles are generated.
67 str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
69 /* Delay for at least 80 SDRAM clock cycles. */
75 /* Set the refresh timer to the fastest required for any device
76 * that might be used. Set 9.6 ms refresh time.
79 str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
81 /* Select mode register update mode. */
82 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
83 EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
84 str r4, [r3, #SDRAM_OFF_GLCONFIG]
86 /* Program the mode register on the SDRAM by performing fake read */
89 /* Select normal operating mode. */
90 ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
91 str r4, [r3, #SDRAM_OFF_GLCONFIG]
93 /* Return to the caller. */
97 * Test to see if the SDRAM has been configured in a usable mode.
99 * Input: r0 - Test address of SDRAM
100 * Output: r0 - 0 -- Test OK, -1 -- Failed
104 /* Load the test patterns to be written to SDRAM. */
110 /* Store the test patterns to SDRAM. */
113 /* Load the test patterns from SDRAM one at a time and compare them
114 * to the actual pattern.
118 ldreq r5, [r0, #0x0004]
120 ldreq r5, [r0, #0x0008]
122 ldreq r5, [r0, #0x000c]
125 /* Return -1 if a mismatch was encountered, 0 otherwise. */
126 mvnne r0, #0xffffffff
127 moveq r0, #0x00000000
129 /* Return to the caller. */
133 * Determine the size of the SDRAM. Use data=address for the scan.
135 * Input: r0 - Start SDRAM address
136 * Return: r0 - Single block size
137 * r1 - Valid block mask
138 * r2 - Total block count
142 /* Store zero at offset zero. */
145 /* Start checking for an alias at 1MB into SDRAM. */
148 /* Store the offset at the current offset. */
152 /* Read back from zero. */
155 /* Stop searching of an alias was found. */
159 /* Advance to the next power of two boundary. */
162 /* Loop back if the size has not reached 256MB. */
166 /* A full 256MB of memory was found, so return it now. */
172 /* An alias was found. See if the first block is 128MB in size. */
176 /* The first block is 128MB, so there is no further memory. Return it
179 ldreq r0, =0x08000000
180 ldreq r1, =0x00000000
181 ldreq r2, =0x00000001
184 /* Save the block size, set the block address bits to zero, and
185 * initialize the block count to one.
191 /* Look for additional blocks of memory by searching for non-aliases. */
193 /* Store zero back to address zero. It may be overwritten. */
196 /* Advance to the next power of two boundary. */
199 /* Store the offset at the current offset. */
202 /* Read back from zero. */
205 /* See if a non-alias was found. */
208 /* If a non-alias was found, then or in the block address bit and
209 * multiply the block count by two (since there are two unique
210 * blocks, one with this bit zero and one with it one).
215 /* Continue searching if there are more address bits to check. */
219 /* Return the block size, address mask, and count. */
224 /* Return to the caller. */
233 /* Make sure caches are off and invalidated. */
235 mcr p15, 0, r0, c1, c0, 0
242 /* Turn off the green LED and turn on the red LED. If the red LED
243 * is left on for too long, the external reset circuit described
244 * by application note AN258 will cause the system to reset.
246 ldr r1, =EP93XX_LED_DATA
248 bic r0, r0, #EP93XX_LED_GREEN_ON
249 orr r0, r0, #EP93XX_LED_RED_ON
252 /* Undo the silly static memory controller programming performed
257 /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
260 /* Reset EP93XX_OFF_SMCBCR0 */
265 ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
267 str r2, [r0, #EP93XX_OFF_SMCBCR1]
269 ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
271 str r2, [r0, #EP93XX_OFF_SMCBCR2]
273 ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
275 str r2, [r0, #EP93XX_OFF_SMCBCR3]
277 ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
279 str r2, [r0, #EP93XX_OFF_SMCBCR6]
281 ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
283 str r2, [r0, #EP93XX_OFF_SMCBCR7]
285 /* Set the PLL1 and processor clock. */
287 #ifdef CONFIG_EDB9301
288 /* 332MHz, giving a 166MHz processor clock. */
292 #ifdef CONFIG_EDB93XX_INDUSTRIAL
293 /* 384MHz, giving a 196MHz processor clock. */
296 /* 400MHz, giving a 200MHz processor clock. */
300 str r1, [r0, #SYSCON_OFF_CLKSET1]
308 /* Need to make sure that SDRAM is configured correctly before
309 * coping the code into it.
312 #ifdef CONFIG_EDB93XX_SDCS0
313 mov r11, #SDRAM_DEVCFG0_BASE
315 #ifdef CONFIG_EDB93XX_SDCS1
316 mov r11, #SDRAM_DEVCFG1_BASE
318 #ifdef CONFIG_EDB93XX_SDCS2
319 mov r11, #SDRAM_DEVCFG2_BASE
321 #ifdef CONFIG_EDB93XX_SDCS3
323 ldr r0, [r0, #SYSCON_OFF_SYSCFG]
324 ands r0, r0, #SYSCON_SYSCFG_LASDO
325 moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
326 movne r11, #SDRAM_DEVCFG3_ASD1_BASE
328 /* See Table 13-5 in EP93xx datasheet for more info about DRAM
329 * register mapping */
331 /* Try a 32-bit wide configuration of SDRAM. */
332 ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
333 EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
334 EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
335 EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
337 /* Set burst count: 4 and CAS: 2
338 * Burst mode [A11:A10]; CAS [A16:A14]
340 orr r2, r11, #0x00008800
341 bl ep93xx_sdram_config
343 /* Test the SDRAM. */
347 beq ep93xx_sdram_done
349 /* Try a 16-bit wide configuration of SDRAM. */
350 ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
351 EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
352 EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
353 EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
354 EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
356 /* Set burst count: 8, CAS: 2, sequential burst
357 * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
358 * Burst mode [A10:A9]; CAS [A15:A13]
360 orr r2, r11, #0x00004600
361 bl ep93xx_sdram_config
363 /* Test the SDRAM. */
367 beq ep93xx_sdram_done
369 /* Turn off the red LED. */
370 ldr r0, =EP93XX_LED_DATA
372 bic r1, r1, #EP93XX_LED_RED_ON
375 /* There is no SDRAM so flash the green LED. */
377 orr r1, r1, #EP93XX_LED_GREEN_ON
382 bne flash_green_delay_1
383 bic r1, r1, #EP93XX_LED_GREEN_ON
388 bne flash_green_delay_2
389 orr r1, r1, #EP93XX_LED_GREEN_ON
394 bne flash_green_delay_3
395 bic r1, r1, #EP93XX_LED_GREEN_ON
400 bne flash_green_delay_4
405 ldr r1, =EP93XX_LED_DATA
407 bic r0, r0, #EP93XX_LED_RED_ON
410 /* Determine the size of the SDRAM. */
414 /* Save the SDRAM characteristics. */
419 /* Compute total memory size into r1 */
421 #ifdef CONFIG_EDB93XX_SDCS0
422 ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
424 #ifdef CONFIG_EDB93XX_SDCS1
425 ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
427 #ifdef CONFIG_EDB93XX_SDCS2
428 ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
430 #ifdef CONFIG_EDB93XX_SDCS3
431 ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
434 /* Consider small DRAM size as:
435 * < 32Mb for 32bit bus
436 * < 64Mb for 16bit bus
438 tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
442 #if defined(CONFIG_EDB9301)
443 /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
447 /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
451 str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
453 /* Save the memory configuration information. */
454 orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE