1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Low-level initialization for EP93xx
5 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
7 * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
9 * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
10 * Copyright (C) 2006 Cirrus Logic Inc.
12 * See file CREDITS for list of people who contributed to this
17 #include <asm/arch-ep93xx/ep93xx.h>
20 /* Configure the SDRAM based on the supplied settings.
22 * Input: r0 - SDRAM DEVCFG register
23 * r2 - configuration for SDRAM chips
28 /* Program the SDRAM device configuration register. */
30 #ifdef CONFIG_EDB93XX_SDCS0
31 str r0, [r3, #SDRAM_OFF_DEVCFG0]
33 #ifdef CONFIG_EDB93XX_SDCS1
34 str r0, [r3, #SDRAM_OFF_DEVCFG1]
36 #ifdef CONFIG_EDB93XX_SDCS2
37 str r0, [r3, #SDRAM_OFF_DEVCFG2]
39 #ifdef CONFIG_EDB93XX_SDCS3
40 str r0, [r3, #SDRAM_OFF_DEVCFG3]
43 /* Set the Initialize and MRS bits (issue continuous NOP commands
46 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
47 EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
48 EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
49 str r4, [r3, #SDRAM_OFF_GLCONFIG]
51 /* Delay for 200us. */
57 /* Clear the MRS bit to issue a precharge all. */
58 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
59 EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
60 str r4, [r3, #SDRAM_OFF_GLCONFIG]
62 /* Temporarily set the refresh timer to 0x10. Make it really low so
63 * that refresh cycles are generated.
66 str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
68 /* Delay for at least 80 SDRAM clock cycles. */
74 /* Set the refresh timer to the fastest required for any device
75 * that might be used. Set 9.6 ms refresh time.
78 str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
80 /* Select mode register update mode. */
81 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
82 EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
83 str r4, [r3, #SDRAM_OFF_GLCONFIG]
85 /* Program the mode register on the SDRAM by performing fake read */
88 /* Select normal operating mode. */
89 ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
90 str r4, [r3, #SDRAM_OFF_GLCONFIG]
92 /* Return to the caller. */
96 * Test to see if the SDRAM has been configured in a usable mode.
98 * Input: r0 - Test address of SDRAM
99 * Output: r0 - 0 -- Test OK, -1 -- Failed
103 /* Load the test patterns to be written to SDRAM. */
109 /* Store the test patterns to SDRAM. */
112 /* Load the test patterns from SDRAM one at a time and compare them
113 * to the actual pattern.
117 ldreq r5, [r0, #0x0004]
119 ldreq r5, [r0, #0x0008]
121 ldreq r5, [r0, #0x000c]
124 /* Return -1 if a mismatch was encountered, 0 otherwise. */
125 mvnne r0, #0xffffffff
126 moveq r0, #0x00000000
128 /* Return to the caller. */
132 * Determine the size of the SDRAM. Use data=address for the scan.
134 * Input: r0 - Start SDRAM address
135 * Return: r0 - Single block size
136 * r1 - Valid block mask
137 * r2 - Total block count
141 /* Store zero at offset zero. */
144 /* Start checking for an alias at 1MB into SDRAM. */
147 /* Store the offset at the current offset. */
151 /* Read back from zero. */
154 /* Stop searching of an alias was found. */
158 /* Advance to the next power of two boundary. */
161 /* Loop back if the size has not reached 256MB. */
165 /* A full 256MB of memory was found, so return it now. */
171 /* An alias was found. See if the first block is 128MB in size. */
175 /* The first block is 128MB, so there is no further memory. Return it
178 ldreq r0, =0x08000000
179 ldreq r1, =0x00000000
180 ldreq r2, =0x00000001
183 /* Save the block size, set the block address bits to zero, and
184 * initialize the block count to one.
190 /* Look for additional blocks of memory by searching for non-aliases. */
192 /* Store zero back to address zero. It may be overwritten. */
195 /* Advance to the next power of two boundary. */
198 /* Store the offset at the current offset. */
201 /* Read back from zero. */
204 /* See if a non-alias was found. */
207 /* If a non-alias was found, then or in the block address bit and
208 * multiply the block count by two (since there are two unique
209 * blocks, one with this bit zero and one with it one).
214 /* Continue searching if there are more address bits to check. */
218 /* Return the block size, address mask, and count. */
223 /* Return to the caller. */
232 /* Make sure caches are off and invalidated. */
234 mcr p15, 0, r0, c1, c0, 0
241 /* Turn off the green LED and turn on the red LED. If the red LED
242 * is left on for too long, the external reset circuit described
243 * by application note AN258 will cause the system to reset.
245 ldr r1, =EP93XX_LED_DATA
247 bic r0, r0, #EP93XX_LED_GREEN_ON
248 orr r0, r0, #EP93XX_LED_RED_ON
251 /* Undo the silly static memory controller programming performed
256 /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
259 /* Reset EP93XX_OFF_SMCBCR0 */
264 ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
266 str r2, [r0, #EP93XX_OFF_SMCBCR1]
268 ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
270 str r2, [r0, #EP93XX_OFF_SMCBCR2]
272 ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
274 str r2, [r0, #EP93XX_OFF_SMCBCR3]
276 ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
278 str r2, [r0, #EP93XX_OFF_SMCBCR6]
280 ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
282 str r2, [r0, #EP93XX_OFF_SMCBCR7]
284 /* Set the PLL1 and processor clock. */
286 #ifdef CONFIG_EDB9301
287 /* 332MHz, giving a 166MHz processor clock. */
291 #ifdef CONFIG_EDB93XX_INDUSTRIAL
292 /* 384MHz, giving a 196MHz processor clock. */
295 /* 400MHz, giving a 200MHz processor clock. */
299 str r1, [r0, #SYSCON_OFF_CLKSET1]
307 /* Need to make sure that SDRAM is configured correctly before
308 * coping the code into it.
311 #ifdef CONFIG_EDB93XX_SDCS0
312 mov r11, #SDRAM_DEVCFG0_BASE
314 #ifdef CONFIG_EDB93XX_SDCS1
315 mov r11, #SDRAM_DEVCFG1_BASE
317 #ifdef CONFIG_EDB93XX_SDCS2
318 mov r11, #SDRAM_DEVCFG2_BASE
320 #ifdef CONFIG_EDB93XX_SDCS3
322 ldr r0, [r0, #SYSCON_OFF_SYSCFG]
323 ands r0, r0, #SYSCON_SYSCFG_LASDO
324 moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
325 movne r11, #SDRAM_DEVCFG3_ASD1_BASE
327 /* See Table 13-5 in EP93xx datasheet for more info about DRAM
328 * register mapping */
330 /* Try a 32-bit wide configuration of SDRAM. */
331 ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
332 EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
333 EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
334 EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
336 /* Set burst count: 4 and CAS: 2
337 * Burst mode [A11:A10]; CAS [A16:A14]
339 orr r2, r11, #0x00008800
340 bl ep93xx_sdram_config
342 /* Test the SDRAM. */
346 beq ep93xx_sdram_done
348 /* Try a 16-bit wide configuration of SDRAM. */
349 ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
350 EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
351 EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
352 EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
353 EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
355 /* Set burst count: 8, CAS: 2, sequential burst
356 * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
357 * Burst mode [A10:A9]; CAS [A15:A13]
359 orr r2, r11, #0x00004600
360 bl ep93xx_sdram_config
362 /* Test the SDRAM. */
366 beq ep93xx_sdram_done
368 /* Turn off the red LED. */
369 ldr r0, =EP93XX_LED_DATA
371 bic r1, r1, #EP93XX_LED_RED_ON
374 /* There is no SDRAM so flash the green LED. */
376 orr r1, r1, #EP93XX_LED_GREEN_ON
381 bne flash_green_delay_1
382 bic r1, r1, #EP93XX_LED_GREEN_ON
387 bne flash_green_delay_2
388 orr r1, r1, #EP93XX_LED_GREEN_ON
393 bne flash_green_delay_3
394 bic r1, r1, #EP93XX_LED_GREEN_ON
399 bne flash_green_delay_4
404 ldr r1, =EP93XX_LED_DATA
406 bic r0, r0, #EP93XX_LED_RED_ON
409 /* Determine the size of the SDRAM. */
413 /* Save the SDRAM characteristics. */
418 /* Compute total memory size into r1 */
420 #ifdef CONFIG_EDB93XX_SDCS0
421 ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
423 #ifdef CONFIG_EDB93XX_SDCS1
424 ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
426 #ifdef CONFIG_EDB93XX_SDCS2
427 ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
429 #ifdef CONFIG_EDB93XX_SDCS3
430 ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
433 /* Consider small DRAM size as:
434 * < 32Mb for 32bit bus
435 * < 64Mb for 16bit bus
437 tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
441 #if defined(CONFIG_EDB9301)
442 /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
446 /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
450 str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
452 /* Save the memory configuration information. */
453 orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE