2 * Cirrus Logic EP93xx PLL support.
4 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
6 * See file CREDITS for list of people who contributed to this project.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/arch/ep93xx.h>
29 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
31 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
32 * the specified bus in HZ.
36 * return the PLL output frequency
38 * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
39 * / (X2IPD + 1) / 2^PS
41 static ulong get_PLLCLK(uint32_t *pllreg)
44 const uint32_t clkset = readl(pllreg);
45 uint64_t rate = CONFIG_SYS_CLK_FREQ;
46 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
47 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
48 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
49 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
55 /* return FCLK frequency */
58 const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
59 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
61 const uint32_t clkset1 = readl(&syscon->clkset1);
62 const uint8_t fclk_div =
63 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
64 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
69 /* return HCLK frequency */
72 const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
73 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
75 const uint32_t clkset1 = readl(&syscon->clkset1);
76 const uint8_t hclk_div =
77 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
78 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
83 /* return PCLK frequency */
86 const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
87 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
89 const uint32_t clkset1 = readl(&syscon->clkset1);
90 const uint8_t pclk_div =
91 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
92 const ulong pclk_rate = get_HCLK() / pclk_div;
97 /* return UCLK frequency */
100 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
103 const uint32_t value = readl(&syscon->pwrcnt);
104 if (value & SYSCON_PWRCNT_UART_BAUD)
105 uclk_rate = CONFIG_SYS_CLK_FREQ;
107 uclk_rate = CONFIG_SYS_CLK_FREQ / 2;