1 // SPDX-License-Identifier: GPL-2.0+
4 * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
9 #if defined (CONFIG_IMX)
11 #include <asm/arch/imx-regs.h>
13 /* ------------------------------------------------------------------------- */
14 /* NOTE: This describes the proper use of this file.
16 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
17 * SH FIXME: 16780000 in our case
18 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
19 * the specified bus in HZ.
21 /* ------------------------------------------------------------------------- */
23 ulong get_systemPLLCLK(void)
25 /* FIXME: We assume System_SEL = 0 here */
27 u32 mfi = (spctl0 >> 10) & 0xf;
28 u32 mfn = spctl0 & 0x3f;
29 u32 mfd = (spctl0 >> 16) & 0x3f;
30 u32 pd = (spctl0 >> 26) & 0xf;
32 mfi = mfi<=5 ? 5 : mfi;
34 return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
37 ulong get_mcuPLLCLK(void)
39 /* FIXME: We assume System_SEL = 0 here */
41 u32 mfi = (mpctl0 >> 10) & 0xf;
42 u32 mfn = mpctl0 & 0x3f;
43 u32 mfd = (mpctl0 >> 16) & 0x3f;
44 u32 pd = (mpctl0 >> 26) & 0xf;
46 mfi = mfi<=5 ? 5 : mfi;
48 return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
53 return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
56 /* return HCLK frequency */
59 u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
60 printf("bclkdiv: %d\n", bclkdiv);
61 return get_systemPLLCLK() / bclkdiv;
64 /* return BCLK frequency */
70 ulong get_PERCLK1(void)
72 return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
75 ulong get_PERCLK2(void)
77 return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
80 ulong get_PERCLK3(void)
82 return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
85 #endif /* defined (CONFIG_IMX) */