2 * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/platform.h>
11 * Initial timer set constants. Nothing complicated, just set for a 1ms
14 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
15 #define TIMER_COUNT (TIMER_INTERVAL / 2)
16 #define TIMER_PULSE TIMER_COUNT
19 * Handy KS8695 register access functions.
21 #define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
22 #define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
28 /* Set the hadware timer for 1ms */
29 ks8695_write(KS8695_TIMER1, TIMER_COUNT);
30 ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
31 ks8695_write(KS8695_TIMER_CTRL, 0x2);
37 ulong get_timer_masked(void)
39 /* Check for timer wrap */
40 if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
41 /* Clear interrupt condition */
42 ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
48 ulong get_timer(ulong base)
50 return (get_timer_masked() - base);
53 void __udelay(ulong usec)
55 ulong start = get_timer_masked();
58 /* Only 1ms resolution :-( */
60 while (get_timer(start) < end)
64 void reset_cpu (ulong ignored)
68 /* Set timer0 to watchdog, and let it timeout */
69 tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
70 ks8695_write(KS8695_TIMER_CTRL, tc);
71 ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
72 ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
74 /* Should only wait here till watchdog resets */