2 * (C) Copyright 2001-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
8 * SPDX-License-Identifier: GPL-2.0+
11 /* This code should work for both the S3C2400 and the S3C2410
12 * as they seem to have the same PLL and clock machinery inside.
13 * The different address mapping is handled by the s3c24xx.h files below.
20 #include <asm/arch/s3c24x0_cpu.h>
25 /* ------------------------------------------------------------------------- */
26 /* NOTE: This describes the proper use of this file.
28 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
30 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
31 * the specified bus in HZ.
33 /* ------------------------------------------------------------------------- */
35 static ulong get_PLLCLK(int pllreg)
37 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
41 r = readl(&clk_power->mpllcon);
42 else if (pllreg == UPLL)
43 r = readl(&clk_power->upllcon);
47 m = ((r & 0xFF000) >> 12) + 8;
48 p = ((r & 0x003F0) >> 4) + 2;
51 #if defined(CONFIG_S3C2440)
53 return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
55 return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
59 /* return FCLK frequency */
62 return get_PLLCLK(MPLL);
65 /* return HCLK frequency */
68 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
70 switch (readl(&clk_power->clkdivn) & 0x6) {
75 return get_FCLK() / 2;
77 return (readl(&clk_power->camdivn) & (1 << 9)) ?
78 get_FCLK() / 8 : get_FCLK() / 4;
80 return (readl(&clk_power->camdivn) & (1 << 8)) ?
81 get_FCLK() / 6 : get_FCLK() / 3;
84 return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
88 /* return PCLK frequency */
91 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
93 return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
96 /* return UCLK frequency */
99 return get_PLLCLK(UPLL);
102 #endif /* CONFIG_S3C24X0 */