3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
11 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
13 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/s3c24x0_cpu.h>
22 DECLARE_GLOBAL_DATA_PTR;
26 struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
29 /* use PWM Timer 4 because it has no output */
30 /* prescaler for Timer 4 is 16 */
31 writel(0x0f00, &timers->tcfg0);
32 if (gd->arch.tbu == 0) {
34 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
35 * (default) and prescaler = 16. Should be 10390
36 * @33.25MHz and 15625 @ 50 MHz
38 gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
39 gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
41 /* load value for 10 ms timeout */
42 writel(gd->arch.tbu, &timers->tcntb4);
43 /* auto load, manual update of timer 4 */
44 tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
45 writel(tmr, &timers->tcon);
46 /* auto load, start timer 4 */
47 tmr = (tmr & ~0x0700000) | 0x0500000;
48 writel(tmr, &timers->tcon);
56 * timer without interrupts
58 ulong get_timer(ulong base)
60 return get_timer_masked() - base;
63 void __udelay (unsigned long usec)
66 ulong start = get_ticks();
69 tmo *= (gd->arch.tbu * 100);
72 while ((ulong) (get_ticks() - start) < tmo)
76 ulong get_timer_masked(void)
78 ulong tmr = get_ticks();
80 return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
83 void udelay_masked(unsigned long usec)
91 tmo *= (gd->arch.tbu * 100);
94 tmo = usec * (gd->arch.tbu * 100);
98 endtime = get_ticks() + tmo;
101 ulong now = get_ticks();
102 diff = endtime - now;
107 * This function is derived from PowerPC code (read timebase as long long).
108 * On ARM it just returns the timer value.
110 unsigned long long get_ticks(void)
112 struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
113 ulong now = readl(&timers->tcnto4) & 0xffff;
115 if (gd->arch.lastinc >= now) {
117 gd->arch.tbl += gd->arch.lastinc - now;
119 /* we have an overflow ... */
120 gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
122 gd->arch.lastinc = now;
128 * This function is derived from PowerPC code (timebase clock frequency).
129 * On ARM it returns the number of timer ticks per second.
131 ulong get_tbclk(void)
133 return CONFIG_SYS_HZ;
137 * reset the cpu by setting up the watchdog timer and let him time out
139 void reset_cpu(ulong ignored)
141 struct s3c24x0_watchdog *watchdog;
143 watchdog = s3c24x0_get_base_watchdog();
145 /* Disable watchdog */
146 writel(0x0000, &watchdog->wtcon);
148 /* Initialize watchdog timer count register */
149 writel(0x0001, &watchdog->wtcnt);
151 /* Enable watchdog timer; assert reset at timer timeout */
152 writel(0x0021, &watchdog->wtcon);
155 /* loop forever and wait for reset to happen */;
160 #endif /* CONFIG_S3C24X0 */